From 23a7b6410e104c890b0dc04514316cf8383ac6fc Mon Sep 17 00:00:00 2001 From: Anuj Aggarwal Date: Fri, 10 Jul 2009 16:52:32 +0530 Subject: [PATCH 1/1] EDMA3: Adding release package 02.00.00.03 --- docs/EDMA3_Driver_Release_Notes.doc | Bin 0 -> 117248 bytes docs/EDMA3_RM_Release_Notes.doc | Bin 0 -> 114176 bytes docs/html/doxygen.css | 267 + docs/html/tag-comment.gif | Bin 0 -> 907 bytes docs/html/tilogo.gif | Bin 0 -> 1137 bytes docs/html/titagline.gif | Bin 0 -> 653 bytes .../CSL2_DAT_DEMO/csl2_legacy_include/csl.h | 196 + .../csl2_legacy_include/csl_atl.h | 141 + .../csl2_legacy_include/csl_atlhal.h | 235 + .../csl2_legacy_include/csl_cache.h | 471 + .../csl2_legacy_include/csl_cachehal.h | 1989 ++ .../csl2_legacy_include/csl_chip.h | 293 + .../csl2_legacy_include/csl_chiphal.h | 1797 ++ .../csl2_legacy_include/csl_dat.h | 161 + .../csl2_legacy_include/csl_dma.h | 392 + .../csl2_legacy_include/csl_dmahal.h | 1197 + .../csl2_legacy_include/csl_edma.h | 891 + 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z*?fH?FK40yz>tYW`UvcVcnaqIoI4?Fq;N+~u~C{vt6Qy6Wh(SipkZFWX}As^J9y^W zt`Y_`NHE8sm_C0PSE5plu4l*mN)hBoKq_d^d>v}M`Gz3^3EmDM3umBIUdyW+Pw?0_ zaafZmRRSPp%@m;om><<_Iaqe0(VypT@`T{(INO=`z6rF<+u&TgB%o~tZ9;>Bx4Sn} z%p0 +#include +#include + + +/******************************************************************************\ +* scope and inline control macros +\******************************************************************************/ +#ifdef __cplusplus +#define CSLAPI extern "C" far +#else +#define CSLAPI extern far +#endif + +#undef USEDEFS +#undef IDECL +#undef IDEF + +#ifdef _CSL_MOD_ + #define IDECL CSLAPI + #define USEDEFS + #define IDEF +#else + #ifdef _INLINE + #define IDECL static inline + #define USEDEFS + #define IDEF static inline + #else + #define IDECL CSLAPI + #endif +#endif + + +/******************************************************************************\ +* global macro declarations +\******************************************************************************/ + + +/******************************************************************************\ +* global typedef declarations +\******************************************************************************/ + +/* if this structure changes, be sure to also change it in csl_irq_.asm */ +typedef union { + struct { + Uint32 biosPresent; + _IRQ_Dispatch *dispatchTable; + Uint32 timerUsed; + Uint32 timerNum; + } args; + struct { + TIMER_Handle hTimer; + Uint32 *event2IntTbl; + Uint32 *int2EventTbl; + } ret; +} _CSL_Config; +/******************************************************************************\ +* global variable declarations +\******************************************************************************/ + +/******************************************************************************\ +* global function declarations +\******************************************************************************/ +CSLAPI void _CSL_init(_CSL_Config *config); + +CSLAPI void CSL6201_LIB_(); +CSLAPI void CSL6202_LIB_(); +CSLAPI void CSL6203_LIB_(); +CSLAPI void CSL6204_LIB_(); +CSLAPI void CSL6205_LIB_(); +CSLAPI void CSL6211_LIB_(); +CSLAPI void CSL6701_LIB_(); +CSLAPI void CSL6711_LIB_(); +CSLAPI void CSL6712_LIB_(); +CSLAPI void CSL6713_LIB_(); +CSLAPI void CSLDA610_LIB_(); +CSLAPI void CSLDM642_LIB_(); +CSLAPI void CSLDM640_LIB_(); +CSLAPI void CSLDM641_LIB_(); +CSLAPI void CSL6412_LIB_(); +CSLAPI void CSL6414_LIB_(); +CSLAPI void CSL6415_LIB_(); +CSLAPI void CSL6416_LIB_(); +CSLAPI void CSL6711C_LIB_(); +CSLAPI void CSL6712C_LIB_(); +CSLAPI void CSL6411_LIB_(); +/* next two options are DRI300 versions */ +CSLAPI void CSL6410_LIB_(); +CSLAPI void CSL6413_LIB_(); +CSLAPI void CSL6418_LIB_(); + +/******************************************************************************\ +* inline function declarations +\******************************************************************************/ + + +/******************************************************************************\ +* special inline function +\******************************************************************************/ + +/* This function checks to make sure that the correct library is being */ +/* linked in compared to the CHIP_XXXX definition. */ + +static inline void CSL_init() { + + #if (CHIP_6201) + CSL6201_LIB_(); + #elif (CHIP_6202) + CSL6202_LIB_(); + #elif (CHIP_6203) + CSL6203_LIB_(); + #elif (CHIP_6204) + CSL6204_LIB_(); + #elif (CHIP_6205) + CSL6205_LIB_(); + #elif (CHIP_6211) + CSL6211_LIB_(); + #elif (CHIP_6701) + CSL6701_LIB_(); + #elif (CHIP_6711) + CSL6711_LIB_(); + #elif (CHIP_6712) + CSL6712_LIB_(); + #elif (CHIP_6713) + CSL6713_LIB_(); + #elif (CHIP_DA610) + CSLDA610_LIB_(); + #elif (CHIP_DM642) + CSLDM642_LIB_(); + #elif (CHIP_DM640) + CSLDM640_LIB_(); + #elif (CHIP_DM641) + CSLDM641_LIB_(); + #elif (CHIP_6412) + CSL6412_LIB_(); + #elif (CHIP_6414) + CSL6414_LIB_(); + #elif (CHIP_6415) + CSL6415_LIB_(); + #elif (CHIP_6416) + CSL6416_LIB_(); + #elif (CHIP_6711C) + CSL6711C_LIB_(); + #elif (CHIP_6712C) + CSL6712C_LIB_(); + #elif (CHIP_6411) + CSL6411_LIB_(); +/* next three are DRI300 versions */ + #elif (CHIP_6410) + CSL6410_LIB_(); + #elif (CHIP_6413) + CSL6413_LIB_(); + #elif (CHIP_6418) + CSL6418_LIB_(); + #endif + + _CSL_init((_CSL_Config*)INV); +} + +/*----------------------------------------------------------------------------*/ + + +/******************************************************************************\ +* inline function definitions +\******************************************************************************/ +#ifdef USEDEFS +/*----------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------*/ +#endif /* USEDEFS */ + + +#endif /* _CSL_H_ */ +/******************************************************************************\ +* End of csl.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_atl.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_atl.h new file mode 100644 index 0000000..06df591 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_atl.h @@ -0,0 +1,141 @@ +/******************************************************************************\ +* Copyright (C) 1999-2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_atl.h +* DATE CREATED.. 07/01/2003 +* LAST MODIFIED. +\******************************************************************************/ +#ifndef _CSL_ATL_H_ +#define _CSL_ATL_H_ + +#include +#include +#include + + +#if (ATL_SUPPORT) +/******************************************************************************\ +* scope and inline control macros +\******************************************************************************/ +#ifdef __cplusplus +#define CSLAPI extern "C" far +#else +#define CSLAPI extern far +#endif + +#undef USEDEFS +#undef IDECL +#undef IDEF + +#ifdef _I2C_MOD_ + #define IDECL CSLAPI + #define USEDEFS + #define IDEF +#else + #ifdef _INLINE + #define IDECL static inline + #define USEDEFS + #define IDEF static inline + #else + #define IDECL CSLAPI + #endif +#endif + + +/******************************************************************************\ +* global macro declarations +\******************************************************************************/ + +/******************************************************************************\ +* global typedef declarations +\******************************************************************************/ + +/* device configuration structure */ +typedef struct { + Uint32 atlppmr; + Uint32 atlcr; +} ATL_Config; + +/******************************************************************************\ +* global variable declarations +\******************************************************************************/ + +/******************************************************************************\ +* global function declarations +\******************************************************************************/ + +/******************************************************************************\ +* inline function declarations +\******************************************************************************/ +IDECL void ATL_config(ATL_Config *config); +IDECL void ATL_configArgs(Uint32 atlppmr, Uint32 atlcr); +IDECL void ATL_getConfig(ATL_Config *config); + +/******************************************************************************\ +* inline function definitions +\******************************************************************************/ +#ifdef USEDEFS +/*----------------------------------------------------------------------------*/ +IDEF void ATL_config(ATL_Config *config) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)_ATL_BASE_PORT; + register int x0,x1; + + gie = IRQ_globalDisable(); + + /* the compiler generates more efficient code if the loads */ + /* and stores are grouped together raher than intermixed */ + x0 = config->atlppmr; + x1 = config->atlcr; + + base[_ATL_ATLPPMR_OFFSET] = x0; + base[_ATL_ATLCR_OFFSET] = x1; + + IRQ_globalRestore(gie); +} +/*----------------------------------------------------------------------------*/ +IDEF void ATL_configArgs(Uint32 atlppmr, Uint32 atlcr) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)_ATL_BASE_PORT; + + gie = IRQ_globalDisable(); + + base[_ATL_ATLPPMR_OFFSET] = atlppmr; + base[_ATL_ATLCR_OFFSET] = atlcr; + + IRQ_globalRestore(gie); +} +/*----------------------------------------------------------------------------*/ +IDEF void ATL_getConfig(ATL_Config *config) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)_ATL_BASE_PORT; + volatile ATL_Config* cfg = (volatile ATL_Config*)config; + register int x0,x1; + + gie = IRQ_globalDisable(); + + /* the compiler generates more efficient code if the loads */ + /* and stores are grouped together raher than intermixed */ + + x0 = base[_ATL_ATLPPMR_OFFSET]; + x1 = base[_ATL_ATLCR_OFFSET]; + + cfg->atlppmr = x0; + cfg->atlcr = x1; + + IRQ_globalRestore(gie); +} +/*----------------------------------------------------------------------------*/ +#endif /* USEDEFS */ + +#endif /* ATL_SUPPORT */ + +#endif /* _CSL_ATL_H_ */ +/******************************************************************************\ +* End of csl_atl.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_atlhal.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_atlhal.h new file mode 100644 index 0000000..b325e9f --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_atlhal.h @@ -0,0 +1,235 @@ +/******************************************************************************\ +* Copyright (C) 1999-2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_atlhal.h +* DATE CREATED.. 07/01/2003 +* .............. 07/02/2003 first draft completed +* LAST MODIFIED. +* +*------------------------------------------------------------------------------ +* REGISTERS +* +* ATLPPMR - ATL Parts Per Million Register +* ATLSCNTR - ATL Sample Count Register +* ATLCR - ATL Control Register +* +\******************************************************************************/ +#ifndef _CSL_ATLHAL_H_ +#define _CSL_ATLHAL_H_ + +#include +#include +#if (ATL_SUPPORT) +/******************************************************************************\ +* MISC section +\******************************************************************************/ + #define _ATL_BASE_PORT 0x01B7F000u + + +/******************************************************************************\ +* module level register/field access macros +\******************************************************************************/ + + /* ----------------- */ + /* FIELD MAKE MACROS */ + /* ----------------- */ + + #define ATL_FMK(REG,FIELD,x)\ + _PER_FMK(ATL,##REG,##FIELD,x) + + #define ATL_FMKS(REG,FIELD,SYM)\ + _PER_FMKS(ATL,##REG,##FIELD,##SYM) + + + /* -------------------------------- */ + /* RAW REGISTER/FIELD ACCESS MACROS */ + /* -------------------------------- */ + + #define ATL_ADDR(REG)\ + _ATL_##REG##_ADDR + + #define ATL_RGET(REG)\ + _PER_RGET(_ATL_##REG##_ADDR,ATL,##REG) + + #define ATL_RSET(REG,x)\ + _PER_RSET(_ATL_##REG##_ADDR,ATL,##REG,x) + + #define ATL_FGET(REG,FIELD)\ + _ATL_##REG##_FGET(##FIELD) + + #define ATL_FSET(REG,FIELD,x)\ + _ATL_##REG##_FSET(##FIELD,##x) + + #define ATL_FSETS(REG,FIELD,SYM)\ + _ATL_##REG##_FSETS(##FIELD,##SYM) + + + /* ------------------------------------------ */ + /* ADDRESS BASED REGISTER/FIELD ACCESS MACROS */ + /* ------------------------------------------ */ + + #define ATL_RGETA(addr,REG)\ + _PER_RGET(addr,ATL,##REG) + + #define ATL_RSETA(addr,REG,x)\ + _PER_RSET(addr,ATL,##REG,x) + + #define ATL_FGETA(addr,REG,FIELD)\ + _PER_FGET(addr,ATL,##REG,##FIELD) + + #define ATL_FSETA(addr,REG,FIELD,x)\ + _PER_FSET(addr,ATL,##REG,##FIELD,x) + + #define ATL_FSETSA(addr,REG,FIELD,SYM)\ + _PER_FSETS(addr,ATL,##REG,##FIELD,##SYM) + +/******************************************************************************\ +* ___________________ +* | | +* | A T L P P M R | +* |___________________| +* +* ATLPPMR - ATL Parts Per Million register +* +* FIELDS (msb -> lsb) +* (rw) PPMSD +* (rw) PPMSET +* +\******************************************************************************/ + #define _ATL_ATLPPMR_OFFSET 0 + + #define _ATL_ATLPPMR_ADDR 0x01B7F000 + + #define _ATL_ATLPPMR_PPMSD_MASK 0x00008000u + #define _ATL_ATLPPMR_PPMSD_SHIFT 0x0000000Fu + #define ATL_ATLPPMR_PPMSD_DEFAULT 0x00000000u + #define ATL_ATLPPMR_PPMSD_OF(x) _VALUEOF(x) + #define ATL_ATLPPMR_PPMSD_SLOWDOWN 0x00000000u + #define ATL_ATLPPMR_PPMSD_SPEEDUP 0x00000001u + + #define _ATL_ATLPPMR_PPMSET_MASK 0x000001FFu + #define _ATL_ATLPPMR_PPMSET_SHIFT 0x00000000u + #define ATL_ATLPPMR_PPMSET_DEFAULT 0x00000000u + #define ATL_ATLPPMR_PPMSET_OF(x) _VALUEOF(x) + + #define ATL_ATLPPMR_OF(x) _VALUEOF(x) + + #define ATL_ATLPPMR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(ATL,ATLPPMR,PPMSD)\ + |_PER_FDEFAULT(ATL,ATLPPMR,PPMSET)\ + ) + + #define ATL_ATLPPMR_RMK(ppmsd,ppmset) (Uint32)(\ + _PER_FMK(ATL,ATLPPMR,PPMSD,ppmsd)\ + |_PER_FMK(ATL,ATLPPMR,PPMSET,ppmset)\ + ) + + #define _ATL_ATLPPMR_FGET(N,FIELD)\ + _PER_FGET(_ATL_ATLPPMR##N##_ADDR,ATL,ATLPPMR,##FIELD) + + #define _ATL_ATLPPMR_FSET(N,FIELD,field)\ + _PER_FSET(_ATL_ATLPPMR##N##_ADDR,ATL,ATLPPMR,##FIELD,field) + + #define _ATL_ATLPPMR_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_ATL_ATLPPMR##N##_ADDR,ATL,ATLPPMR,##FIELD,##SYM) + +/******************************************************************************\ +* ___________________ +* | | +* | A T L S C N T R | +* |___________________| +* +* ATLSCNTR - ATL Sample Count register +* +* FIELDS (msb -> lsb) +* (r) SCNT +* +\******************************************************************************/ + #define _ATL_ATLSCNTR_OFFSET 1 + + #define _ATL_ATLSCNTR_ADDR 0x01B7F004 + + #define _ATL_ATLSCNTR_SCNT_MASK 0x0000FFFFu + #define _ATL_ATLSCNTR_SCNT_SHIFT 0x00000000u + #define ATL_ATLSCNTR_SCNT_DEFAULT 0x00000000u + #define ATL_ATLSCNTR_SCNT_OF(x) _VALUEOF(x) + + #define ATL_ATLSCNTR_OF(x) _VALUEOF(x) + + #define ATL_ATLSCNTR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(ATL,ATLSCNTR,SCNT)\ + ) + + #define ATL_ATLSCNTR_RMK(scnt) (Uint32)(\ + _PER_FMK(ATL,ATLSCNTR,SCNT,scnt)\ + ) + + #define _ATL_ATLSCNTR_FGET(N,FIELD)\ + _PER_FGET(_ATL_ATLSCNTR##N##_ADDR,ATL,ATLSCNTR,##FIELD) + +/******************************************************************************\ +* _______________ +* | | +* | A T L C R | +* |_______________| +* +* ATLCR - ATL Control register +* +* FIELDS (msb -> lsb) +* (rw) MUXCLKSEL +* (rw) MCDSEL +* (rw) ATLIDIV +* +\******************************************************************************/ + #define _ATL_ATLCR_OFFSET 2 + + #define _ATL_ATLCR_ADDR 0x01B7F008 + + #define _ATL_ATLCR_MUXCLKSEL_MASK 0x00000040u + #define _ATL_ATLCR_MUXCLKSEL_SHIFT 0x00000006u + #define ATL_ATLCR_MUXCLKSEL_DEFAULT 0x00000000u + #define ATL_ATLCR_MUXCLKSEL_OF(x) _VALUEOF(x) + #define ATL_ATLCR_MUXCLKSEL_ATLPCLK 0x00000000u + #define ATL_ATLCR_MUXCLKSEL_EATCLK 0x00000001u + + #define _ATL_ATLCR_MCDSEL_MASK 0x00000020u + #define _ATL_ATLCR_MCDSEL_SHIFT 0x00000005u + #define ATL_ATLCR_MCDSEL_DEFAULT 0x00000000u + #define ATL_ATLCR_MCDSEL_OF(x) _VALUEOF(x) + #define ATL_ATLCR_MCDSEL_BY2P16 0x00000000u + #define ATL_ATLCR_MCDSEL_BY2P14 0x00000001u + + #define _ATL_ATLCR_ATLIDIV_MASK 0x0000001Fu + #define _ATL_ATLCR_ATLIDIV_SHIFT 0x00000000u + #define ATL_ATLCR_ATLIDIV_DEFAULT 0x00000018u + #define ATL_ATLCR_ATLIDIV_OF(x) _VALUEOF(x) + + #define ATL_ATLCR_OF(x) _VALUEOF(x) + + #define ATL_ATLCR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(ATL,ATLCR,MUXCLKSEL)\ + |_PER_FDEFAULT(ATL,ATLCR,MCDSEL)\ + |_PER_FDEFAULT(ATL,ATLCR,ATLIDIV)\ + ) + + #define ATL_ATLCR_RMK(muxclksel,mcdsel,atlidiv) (Uint32)(\ + _PER_FMK(ATL,ATLCR,MUXCLKSEL,muxclksel)\ + |_PER_FMK(ATL,ATLCR,MCDCLK,mcdsel)\ + |_PER_FMK(ATL,ATLCR,ATLIDIV,atlidiv)\ + ) + + #define _ATL_ATLCR_FGET(N,FIELD)\ + _PER_FGET(_ATL_ATLCR##N##_ADDR,ATL,ATLCR,##FIELD) + + #define _ATL_ATLCR_FSET(N,FIELD,field)\ + _PER_FSET(_ATL_ATLCR##N##_ADDR,ATL,ATLCR,##FIELD,field) + + #define _ATL_ATLCR_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_ATL_ATLCR##N##_ADDR,ATL,ATLCR,##FIELD,##SYM) + +#endif /* ATL_SUPPORT */ +#endif /* _CSL_ATLHAL_H_ */ +/******************************************************************************\ +* End of csl_atlhal.h +\******************************************************************************/ diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_cache.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_cache.h new file mode 100644 index 0000000..f826209 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_cache.h @@ -0,0 +1,471 @@ +/******************************************************************************\ +* Copyright (C) 1999-2001 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_cache.h +* DATE CREATED.. 06/11/1999 +* LAST MODIFIED. 10/01/2001 - Addition of 192K L2 SRAM for 6713 +* 04/16/2004 - Modified CACHE_ROUND_TO_LINESIZE implementation +\******************************************************************************/ +#ifndef _CSL_CACHE_H_ +#define _CSL_CACHE_H_ + +#include +#include +#include + + +#if (CACHE_SUPPORT) +/******************************************************************************\ +* scope and inline control macros +\******************************************************************************/ +#ifdef __cplusplus +#define CSLAPI extern "C" far +#else +#define CSLAPI extern far +#endif + +#undef USEDEFS +#undef IDECL +#undef IDEF + +#ifdef _CACHE_MOD_ + #define IDECL CSLAPI + #define USEDEFS + #define IDEF +#else + #ifdef _INLINE + #define IDECL static inline + #define USEDEFS + #define IDEF static inline + #else + #define IDECL CSLAPI + #endif +#endif + + +/******************************************************************************\ +* global macro declarations +\******************************************************************************/ +#if (!C64_SUPPORT) + #define CACHE_CE00 CACHE_ADDR(MAR0) + #define CACHE_CE01 CACHE_ADDR(MAR1) + #define CACHE_CE02 CACHE_ADDR(MAR2) + #define CACHE_CE03 CACHE_ADDR(MAR3) + #define CACHE_CE10 CACHE_ADDR(MAR4) + #define CACHE_CE11 CACHE_ADDR(MAR5) + #define CACHE_CE12 CACHE_ADDR(MAR6) + #define CACHE_CE13 CACHE_ADDR(MAR7) + #define CACHE_CE20 CACHE_ADDR(MAR8) + #define CACHE_CE21 CACHE_ADDR(MAR9) + #define CACHE_CE22 CACHE_ADDR(MAR10) + #define CACHE_CE23 CACHE_ADDR(MAR11) + #define CACHE_CE30 CACHE_ADDR(MAR12) + #define CACHE_CE31 CACHE_ADDR(MAR13) + #define CACHE_CE32 CACHE_ADDR(MAR14) + #define CACHE_CE33 CACHE_ADDR(MAR15) +#else + + #if (CHIP_6414 | CHIP_6415 | CHIP_6416) + + #define CACHE_EMIFB_CE00 CACHE_ADDR(MAR96) + #define CACHE_EMIFB_CE01 CACHE_ADDR(MAR97) + #define CACHE_EMIFB_CE02 CACHE_ADDR(MAR98) + #define CACHE_EMIFB_CE03 CACHE_ADDR(MAR99) + #define CACHE_EMIFB_CE10 CACHE_ADDR(MAR100) + #define CACHE_EMIFB_CE11 CACHE_ADDR(MAR101) + #define CACHE_EMIFB_CE12 CACHE_ADDR(MAR102) + #define CACHE_EMIFB_CE13 CACHE_ADDR(MAR103) + #define CACHE_EMIFB_CE20 CACHE_ADDR(MAR104) + #define CACHE_EMIFB_CE21 CACHE_ADDR(MAR105) + #define CACHE_EMIFB_CE22 CACHE_ADDR(MAR106) + #define CACHE_EMIFB_CE23 CACHE_ADDR(MAR107) + #define CACHE_EMIFB_CE30 CACHE_ADDR(MAR108) + #define CACHE_EMIFB_CE31 CACHE_ADDR(MAR109) + #define CACHE_EMIFB_CE32 CACHE_ADDR(MAR110) + #define CACHE_EMIFB_CE33 CACHE_ADDR(MAR111) + + #endif + + #define CACHE_EMIFA_CE00 CACHE_ADDR(MAR128) + #define CACHE_EMIFA_CE01 CACHE_ADDR(MAR129) + #define CACHE_EMIFA_CE02 CACHE_ADDR(MAR130) + #define CACHE_EMIFA_CE03 CACHE_ADDR(MAR131) + #define CACHE_EMIFA_CE04 CACHE_ADDR(MAR132) + #define CACHE_EMIFA_CE05 CACHE_ADDR(MAR133) + #define CACHE_EMIFA_CE06 CACHE_ADDR(MAR134) + #define CACHE_EMIFA_CE07 CACHE_ADDR(MAR135) + #define CACHE_EMIFA_CE08 CACHE_ADDR(MAR136) + #define CACHE_EMIFA_CE09 CACHE_ADDR(MAR137) + #define CACHE_EMIFA_CE010 CACHE_ADDR(MAR138) + #define CACHE_EMIFA_CE011 CACHE_ADDR(MAR139) + #define CACHE_EMIFA_CE012 CACHE_ADDR(MAR140) + #define CACHE_EMIFA_CE013 CACHE_ADDR(MAR141) + #define CACHE_EMIFA_CE014 CACHE_ADDR(MAR142) + #define CACHE_EMIFA_CE015 CACHE_ADDR(MAR143) + + #define CACHE_EMIFA_CE10 CACHE_ADDR(MAR144) + #define CACHE_EMIFA_CE11 CACHE_ADDR(MAR145) + #define CACHE_EMIFA_CE12 CACHE_ADDR(MAR146) + #define CACHE_EMIFA_CE13 CACHE_ADDR(MAR147) + #define CACHE_EMIFA_CE14 CACHE_ADDR(MAR148) + #define CACHE_EMIFA_CE15 CACHE_ADDR(MAR149) + #define CACHE_EMIFA_CE16 CACHE_ADDR(MAR150) + #define CACHE_EMIFA_CE17 CACHE_ADDR(MAR151) + #define CACHE_EMIFA_CE18 CACHE_ADDR(MAR152) + #define CACHE_EMIFA_CE19 CACHE_ADDR(MAR153) + #define CACHE_EMIFA_CE110 CACHE_ADDR(MAR154) + #define CACHE_EMIFA_CE111 CACHE_ADDR(MAR155) + #define CACHE_EMIFA_CE112 CACHE_ADDR(MAR156) + #define CACHE_EMIFA_CE113 CACHE_ADDR(MAR157) + #define CACHE_EMIFA_CE114 CACHE_ADDR(MAR158) + #define CACHE_EMIFA_CE115 CACHE_ADDR(MAR159) + + #define CACHE_EMIFA_CE20 CACHE_ADDR(MAR160) + #define CACHE_EMIFA_CE21 CACHE_ADDR(MAR161) + #define CACHE_EMIFA_CE22 CACHE_ADDR(MAR162) + #define CACHE_EMIFA_CE23 CACHE_ADDR(MAR163) + #define CACHE_EMIFA_CE24 CACHE_ADDR(MAR164) + #define CACHE_EMIFA_CE25 CACHE_ADDR(MAR165) + #define CACHE_EMIFA_CE26 CACHE_ADDR(MAR166) + #define CACHE_EMIFA_CE27 CACHE_ADDR(MAR167) + #define CACHE_EMIFA_CE28 CACHE_ADDR(MAR168) + #define CACHE_EMIFA_CE29 CACHE_ADDR(MAR169) + #define CACHE_EMIFA_CE210 CACHE_ADDR(MAR170) + #define CACHE_EMIFA_CE211 CACHE_ADDR(MAR171) + #define CACHE_EMIFA_CE212 CACHE_ADDR(MAR172) + #define CACHE_EMIFA_CE213 CACHE_ADDR(MAR173) + #define CACHE_EMIFA_CE214 CACHE_ADDR(MAR174) + #define CACHE_EMIFA_CE215 CACHE_ADDR(MAR175) + + #define CACHE_EMIFA_CE30 CACHE_ADDR(MAR176) + #define CACHE_EMIFA_CE31 CACHE_ADDR(MAR177) + #define CACHE_EMIFA_CE32 CACHE_ADDR(MAR178) + #define CACHE_EMIFA_CE33 CACHE_ADDR(MAR179) + #define CACHE_EMIFA_CE34 CACHE_ADDR(MAR180) + #define CACHE_EMIFA_CE35 CACHE_ADDR(MAR181) + #define CACHE_EMIFA_CE36 CACHE_ADDR(MAR182) + #define CACHE_EMIFA_CE37 CACHE_ADDR(MAR183) + #define CACHE_EMIFA_CE38 CACHE_ADDR(MAR184) + #define CACHE_EMIFA_CE39 CACHE_ADDR(MAR185) + #define CACHE_EMIFA_CE310 CACHE_ADDR(MAR186) + #define CACHE_EMIFA_CE311 CACHE_ADDR(MAR187) + #define CACHE_EMIFA_CE312 CACHE_ADDR(MAR188) + #define CACHE_EMIFA_CE313 CACHE_ADDR(MAR189) + #define CACHE_EMIFA_CE314 CACHE_ADDR(MAR190) + #define CACHE_EMIFA_CE315 CACHE_ADDR(MAR191) + +#endif + + +#if (C64_SUPPORT) + #define CACHE_L2_LINESIZE 128 + #define CACHE_L1D_LINESIZE 64 + #define CACHE_L1P_LINESIZE 32 +#else + #define CACHE_L2_LINESIZE 128 + #define CACHE_L1D_LINESIZE 32 + #define CACHE_L1P_LINESIZE 64 +#endif /* C64_SUPPORT */ + +//#define CACHE_ROUND_TO_LINESIZE(CACHE,ELCNT,ELSIZE) \ +// ((CACHE_##CACHE##_LINESIZE * \ +// (( (((ELCNT)*(ELSIZE)) -1)/CACHE_##CACHE##_LINESIZE ) + 1))/ \ +// (ELSIZE)) + +#define CACHE_ROUND_TO_LINESIZE(CACHE,ELCNT,ELSIZE)\ +( ( ( ( (ELCNT) * (ELSIZE)\ + + CACHE_##CACHE##_LINESIZE - 1\ + ) / CACHE_##CACHE##_LINESIZE\ + * CACHE_##CACHE##_LINESIZE\ + ) + (ELSIZE) - 1\ + ) / (ELSIZE)\ +) + +/******************************************************************************\ +* global typedef declarations +\******************************************************************************/ +#if(!C64_SUPPORT && !CHIP_6713 && !CHIP_DA610) +typedef enum { + CACHE_64KSRAM = 0, + CACHE_0KCACHE = 0, + CACHE_48KSRAM = 1, + CACHE_16KCACHE = 1, + CACHE_32KSRAM = 2, + CACHE_32KCACHE = 2, + CACHE_16KSRAM = 3, + CACHE_48KCACHE = 3, + CACHE_0KSRAM = 7, + CACHE_64KCACHE = 7 +} CACHE_L2Mode; +#endif + +#if (CHIP_6414 | CHIP_6415 | CHIP_6416) +typedef enum { + CACHE_1024KSRAM = 0, + CACHE_0KCACHE = 0, + CACHE_992KSRAM = 1, + CACHE_32KCACHE = 1, + CACHE_960KSRAM = 2, + CACHE_64KCACHE = 2, + CACHE_896KSRAM = 3, + CACHE_128KCACHE = 3, + CACHE_768KSRAM = 7, + CACHE_256KCACHE = 7 /* 4-way cache 128Kbytes max */ +} CACHE_L2Mode; + #endif + +#if (CHIP_6713 || CHIP_DA610) + typedef enum { + CACHE_256KSRAM = 0, + CACHE_0KCACHE = 0, + CACHE_240KSRAM = 1, + CACHE_16KCACHE = 1, + CACHE_224KSRAM = 2, + CACHE_32KCACHE = 2, + CACHE_208KSRAM = 3, + CACHE_48KCACHE = 3, + CACHE_192KSRAM = 7, + CACHE_64KCACHE = 7 +} CACHE_L2Mode; + #endif + +#if (CHIP_DM642 | CHIP_6412 | CHIP_6411) + typedef enum { + CACHE_256KSRAM = 0, + CACHE_0KCACHE = 0, + CACHE_224KSRAM = 1, + CACHE_32KCACHE = 1, + CACHE_192KSRAM = 2, + CACHE_64KCACHE = 2, + CACHE_128KSRAM = 3, + CACHE_128KCACHE = 3, + CACHE_0KSRAM = 7, + CACHE_256KCACHE = 7 +} CACHE_L2Mode; +#endif + +/* Cache sizes for the DRI300 variants + - 6418 : 512 K + - 6413 : 256 K + - 6410 : 128 K +*/ + +#if (CHIP_6418) + typedef enum { + CACHE_512KSRAM = 0, + CACHE_0KCACHE = 0, + CACHE_480KSRAM = 1, + CACHE_32KCACHE = 1, + CACHE_448KSRAM = 2, + CACHE_64KCACHE = 2, + CACHE_384KSRAM = 3, + CACHE_128KCACHE = 3, + CACHE_256KSRAM = 7, + CACHE_256KCACHE = 7 +} CACHE_L2Mode; +#endif + +#if (CHIP_6413) + typedef enum { + CACHE_256KSRAM = 0, + CACHE_0KCACHE = 0, + CACHE_224KSRAM = 1, + CACHE_32KCACHE = 1, + CACHE_192KSRAM = 2, + CACHE_64KCACHE = 2, + CACHE_128KSRAM = 3, + CACHE_128KCACHE = 3, + CACHE_256KCACHE = 7 +} CACHE_L2Mode; +#endif + +#if (CHIP_6410 | CHIP_DM641 | CHIP_DM640) + typedef enum { + CACHE_128KSRAM = 0, + CACHE_0KCACHE = 0, + CACHE_96KSRAM = 1, + CACHE_32KCACHE = 1, + CACHE_64KSRAM = 2, + CACHE_64KCACHE = 2, + CACHE_128KCACHE = 3 /* All other modes are invalid */ +} CACHE_L2Mode; +#endif + +typedef enum { + CACHE_L2, + CACHE_L2ALL, + CACHE_L1P, + CACHE_L1PALL, + CACHE_L1D, + CACHE_L1DALL +} CACHE_Region; + +typedef enum { + CACHE_PCC_MAPPED = 0, + CACHE_PCC_ENABLE = 2, + CACHE_PCC_FREEZE = 3, + CACHE_PCC_BYPASS = 4 +} CACHE_Pcc; + +/* Define macros for L2 priority Level */ +#define CACHE_L2PRIURG 0 +#define CACHE_L2PRIHIGH 1 +#define CACHE_L2PRIMED 2 +#define CACHE_L2PRILOW 3 + +/* Define macros for L2 Queues */ +#define CACHE_L2Q0 0 +#define CACHE_L2Q1 1 +#define CACHE_L2Q2 2 +#define CACHE_L2Q3 3 + +/* Define CACHE wait flag */ +typedef enum { + CACHE_NOWAIT = 0, + CACHE_WAIT = 1 +} CACHE_Wait; + +#define CACHE_WAIT_L2WB 0x00000001 +#define CACHE_WAIT_L2INV 0x00000002 +#define CACHE_WAIT_L2WBINV 0x00000004 +#define CACHE_WAIT_L2WBALL 0x00000008 +#define CACHE_WAIT_L2WBINVALL 0x00000010 +#define CACHE_WAIT_L1DINV 0x00000020 +#define CACHE_WAIT_L1DWBINV 0x00000040 +#define CACHE_WAIT_L1PINV 0x00000080 + +/* Renaming Function */ + +#define CACHE_resetEMIFA CACHE_resetEmifa + +#if (CHIP_6414 | CHIP_6415 | CHIP_6416) + #define CACHE_resetEMIFB CACHE_resetEmifb +#endif + +/******************************************************************************\ +* global variable declarations +\******************************************************************************/ + + +/******************************************************************************\ +* global function declarations +\******************************************************************************/ +CSLAPI void CACHE_reset(); +CSLAPI void CACHE_resetEmifa(); + +#if (CHIP_6414 | CHIP_6415 | CHIP_6416) + CSLAPI void CACHE_resetEmifb(); +#endif + +CSLAPI CACHE_L2Mode CACHE_setL2Mode(CACHE_L2Mode newMode); +CSLAPI CACHE_L2Mode CACHE_getL2Mode(); +CSLAPI CACHE_Pcc CACHE_setPccMode(CACHE_Pcc newMode); +CSLAPI void CACHE_flush(CACHE_Region region,void *addr,Uint32 wordCnt); +CSLAPI void CACHE_clean(CACHE_Region region,void *addr,Uint32 wordCnt); +CSLAPI void CACHE_invalidate(CACHE_Region region,void *addr,Uint32 wordCnt); +CSLAPI Uint32 CACHE_getL2SramSize(); + +/* New API base on SPRU609 and SPRU610 */ +CSLAPI void CACHE_wbL2(void *blockPtr,Uint32 byteCnt,CACHE_Wait wait); +CSLAPI void CACHE_wbInvL2(void *blockPtr,Uint32 byteCnt,CACHE_Wait wait); +CSLAPI void CACHE_wbAllL2(CACHE_Wait wait); +CSLAPI void CACHE_wbInvAllL2(CACHE_Wait wait); +//CSLAPI void CACHE_invAllL1d(); +CSLAPI void CACHE_wbInvL1d(void *blockPtr,Uint32 byteCnt,CACHE_Wait wait); +CSLAPI void CACHE_invL1p(void *blockPtr,Uint32 byteCnt,CACHE_Wait wait); +CSLAPI void CACHE_invAllL1p(); +CSLAPI void CACHE_wait(); + +#if (C64_SUPPORT) +CSLAPI void CACHE_invL2(void *blockPtr,Uint32 byteCnt,CACHE_Wait wait); +CSLAPI void CACHE_invL1d(void *blockPtr,Uint32 byteCnt,CACHE_Wait wait); +#endif + +/* new APIs with user-determined blocksize option */ +CSLAPI void CACHE_wbInvL2_blocks(void *blockPtr,Uint32 byteCnt, Uint32 blockSize); +CSLAPI void CACHE_wbL2_blocks(void *blockPtr,Uint32 byteCnt, Uint32 blockSize); + + +/*#if (C64_SUPPORT) +CSLAPI void CACHE_freezeL1P(); +CSLAPI void CACHE_freezeL1D(); +#endif */ + +/******************************************************************************\ +* inline function declarations +\******************************************************************************/ +IDECL void CACHE_enableCaching(Uint32 block); +#if (CHIP_6414 | CHIP_6415 | CHIP_6416| CHIP_DM642 | CHIP_DM641 | CHIP_DM640 | CHIP_6412 | CHIP_6411 | CHIP_6410 | CHIP_6413 | CHIP_6418) +IDECL void CACHE_setPriL2Req(Uint32 priority); +IDECL void CACHE_setL2Queue(Uint32 queueNum,Uint32 length); +IDECL void CACHE_resetL2Queue(Uint32 queueNum); +#endif + +/******************************************************************************\ +* inline function definitions +\******************************************************************************/ +#ifdef USEDEFS +/*----------------------------------------------------------------------------*/ +IDEF void CACHE_enableCaching(Uint32 block) { + + #if (L2CACHE_SUPPORT) + CACHE_FSETA(block,MAR,CE,1); + while (!CACHE_FGETA(block,MAR,CE)) + ; + #else + UNREFERENCED_PARAMETER(block); + #endif +} + +/*----------------------------------------------------------------------------*/ +#if (CHIP_6414 | CHIP_6415 | CHIP_6416| CHIP_DM642 | CHIP_DM641 | CHIP_DM640 | CHIP_6412 | CHIP_6411 | CHIP_6410 | CHIP_6413 | CHIP_6418) +IDEF void CACHE_setPriL2Req(Uint32 priority) { + CACHE_FSET(CCFG,P,priority); + } +/*----------------------------------------------------------------------------*/ +IDEF void CACHE_setL2Queue(Uint32 queueNum,Uint32 length) { + if (queueNum == 0 ){ + CACHE_FSET(L2ALLOC0,Q0CNT,length); + } else { + if (queueNum == 1 ){ + CACHE_FSET(L2ALLOC1,Q1CNT,length); + } else { + if (queueNum == 2 ){ + CACHE_FSET(L2ALLOC2,Q2CNT,length); + } else { + if (queueNum == 3 ){ + CACHE_FSET(L2ALLOC3,Q3CNT,length); + } + } + } + } +} +/*----------------------------------------------------------------------------*/ +IDEF void CACHE_resetL2Queue(Uint32 queueNum) { + if (queueNum == 0 ) { + CACHE_FSET(L2ALLOC0,Q0CNT,6); + } else { + if (queueNum == 1 ) { + CACHE_FSET(L2ALLOC1,Q1CNT,2); + } else { + if (queueNum == 2 ) { + CACHE_FSET(L2ALLOC2,Q2CNT,2); + } else { + if (queueNum == 3 ) { + CACHE_FSET(L2ALLOC3,Q3CNT,2); + } + } + } + } +} +#endif +/*----------------------------------------------------------------------------*/ + +#endif /* USEDEFS */ + +#endif /* CACHE_SUPPORT */ +#endif /* _CSL_CACHE_H_ */ +/******************************************************************************\ +* End of csl_cache.h +\******************************************************************************/ diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_cachehal.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_cachehal.h new file mode 100644 index 0000000..4d584cf --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_cachehal.h @@ -0,0 +1,1989 @@ +/******************************************************************************\ +* Copyright (C) 1999-2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_cachehal.h +* DATE CREATED.. 06/12/1999 +* LAST MODIFIED. 04/13/2001 +*------------------------------------------------------------------------------ +* REGISTERS +* +* CCFG - cache configuration register +* L2FBAR - L2 flush base address register +* L2FWC - L2 flush word count register +* L2CBAR - L2 clean base register +* L2CWC - L2 clean word count register +* L1PFBAR - L1P flush base address register +* L1PFWC - L1P flush word count register +* L1DFBAR - L1D flush base address register +* L1DFWC - L1D flush word count register +* L2FLUSH - L2 flush register +* L2CLEAN - L2 clean register +* +* +* +* +* +* New Register Names based on SPRU609 for C621x/C671x +* and +* New Register Names based on SPRU610 for C64x +* +* +* L2WBAR - L2 writeback base address register +* L2WWC - L2 writeback word count register +* L2WIBAR - L2 writeback-invalidate base address register +* L2WIWC - L2 writeback-invalidate word count register +* L2IBAR - L2 invalidate base address register(2) +* L2IWC - L2 invalidate word count register(2) +* L1PIBAR - L1P invalidate base address register +* L1PIWC - L1P invalidate word count register +* L1DWIBAR - L1D writeback-invalidate base address register +* L1DWIWC - L1D writeback-invalidate word count register +* L1DIBAR - L1D invalidate base address register(2) +* L1DIWC - L1D invalidate word count register(2) +* L2WB - L2 writeback all register +* L2WBINV - L2 writeback-invalidate all register +* +* MAR0 - memory attribute register 0 +* MAR1 - memory attribute register 1 +* ... - ... +* MARn - memory attribute register n (1) +* L2ALLOC0 - L2 Allocation register 0 (2) +* L2ALLOC1 - L2 Allocation register 1 (2) +* L2ALLOC2 - L2 Allocation register 2 (2) +* L2ALLOC3 - L2 Allocation register 3 (2) +* +* (1) n is different between C6x1x and C64x +* (2) C64x devices only +* +\******************************************************************************/ +#ifndef _CSL_CACHEHAL_H_ +#define _CSL_CACHEHAL_H_ + +#include +#include + +#if (CACHE_SUPPORT) +/******************************************************************************\ +* MISC section +\******************************************************************************/ +#define _CACHE_BASE_GLOBAL 0x01840000u +#define CACHE_L2_SUPPORT L2CACHE_SUPPORT + + +/******************************************************************************\ +* module level register/field access macros +\******************************************************************************/ + + /* ----------------- */ + /* FIELD MAKE MACROS */ + /* ----------------- */ + + #define CACHE_FMK(REG,FIELD,x)\ + _PER_FMK(CACHE,##REG,##FIELD,x) + + #define CACHE_FMKS(REG,FIELD,SYM)\ + _PER_FMKS(CACHE,##REG,##FIELD,##SYM) + + + /* -------------------------------- */ + /* RAW REGISTER/FIELD ACCESS MACROS */ + /* -------------------------------- */ + + #define CACHE_ADDR(REG)\ + _CACHE_##REG##_ADDR + + #define CACHE_RGET(REG)\ + _PER_RGET(_CACHE_##REG##_ADDR,CACHE,##REG) + + #define CACHE_RSET(REG,x)\ + _PER_RSET(_CACHE_##REG##_ADDR,CACHE,##REG,x) + + #define CACHE_FGET(REG,FIELD)\ + _CACHE_##REG##_FGET(##FIELD) + + #define CACHE_FSET(REG,FIELD,x)\ + _CACHE_##REG##_FSET(##FIELD,x) + + #define CACHE_FSETS(REG,FIELD,SYM)\ + _CACHE_##REG##_FSETS(##FIELD,##SYM) + + + /* ------------------------------------------ */ + /* ADDRESS BASED REGISTER/FIELD ACCESS MACROS */ + /* ------------------------------------------ */ + + #define CACHE_RGETA(addr,REG)\ + _PER_RGET(addr,CACHE,##REG) + + #define CACHE_RSETA(addr,REG,x)\ + _PER_RSET(addr,CACHE,##REG,x) + + #define CACHE_FGETA(addr,REG,FIELD)\ + _PER_FGET(addr,CACHE,##REG,##FIELD) + + #define CACHE_FSETA(addr,REG,FIELD,x)\ + _PER_FSET(addr,CACHE,##REG,##FIELD,x) + + #define CACHE_FSETSA(addr,REG,FIELD,SYM)\ + _PER_FSETS(addr,CACHE,##REG,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | C C F G | +* |___________________| +* +* CCFG - cache configuration register +* +* FIELDS (msb -> lsb) +* (rw) P (1) +* (w) IP +* (w) ID +* (rw) L2MODE +* +* (1) only supported for C64x devices +* +\******************************************************************************/ +#if (L2CACHE_SUPPORT) + #define _CACHE_CCFG_ADDR 0x01840000u + +#if (C64_SUPPORT) + #define _CACHE_CCFG_P_MASK 0xE0000000u + #define _CACHE_CCFG_P_SHIFT 0x0000001Du + #define CACHE_CCFG_P_DEFAULT 0x00000000u + #define CACHE_CCFG_P_OF(x) _VALUEOF(x) + #define CACHE_CCFG_P_URGENT 0x00000000u + #define CACHE_CCFG_P_HIGH 0x00000001u + #define CACHE_CCFG_P_MEDIUM 0x00000002u + #define CACHE_CCFG_P_LOW 0x00000003u +#endif + + #define _CACHE_CCFG_IP_MASK 0x00000200u + #define _CACHE_CCFG_IP_SHIFT 0x00000009u + #define CACHE_CCFG_IP_DEFAULT 0x00000000u + #define CACHE_CCFG_IP_OF(x) _VALUEOF(x) + #define CACHE_CCFG_IP_NORMAL 0x00000000u + #define CACHE_CCFG_IP_INVALIDATE 0x00000001u + + #define _CACHE_CCFG_ID_MASK 0x00000100u + #define _CACHE_CCFG_ID_SHIFT 0x00000008u + #define CACHE_CCFG_ID_DEFAULT 0x00000000u + #define CACHE_CCFG_ID_OF(x) _VALUEOF(x) + #define CACHE_CCFG_ID_NORMAL 0x00000000u + #define CACHE_CCFG_ID_INVALIDATE 0x00000001u + +#if (!C64_SUPPORT) + #define _CACHE_CCFG_L2MODE_MASK 0x00000007u + #define _CACHE_CCFG_L2MODE_SHIFT 0x00000000u + #define CACHE_CCFG_L2MODE_DEFAULT 0x00000000u + #define CACHE_CCFG_L2MODE_OF(x) _VALUEOF(x) + #define CACHE_CCFG_L2MODE_0KC 0x00000000u + #define CACHE_CCFG_L2MODE_16KC 0x00000001u + #define CACHE_CCFG_L2MODE_32KC 0x00000002u + #define CACHE_CCFG_L2MODE_48KC 0x00000003u + #define CACHE_CCFG_L2MODE_64KC 0x00000007u +#else + #define _CACHE_CCFG_L2MODE_MASK 0x00000007u + #define _CACHE_CCFG_L2MODE_SHIFT 0x00000000u + #define CACHE_CCFG_L2MODE_DEFAULT 0x00000000u + #define CACHE_CCFG_L2MODE_OF(x) _VALUEOF(x) + #define CACHE_CCFG_L2MODE_0KC 0x00000000u + #define CACHE_CCFG_L2MODE_32KC 0x00000001u + #define CACHE_CCFG_L2MODE_64KC 0x00000002u + #define CACHE_CCFG_L2MODE_128KC 0x00000003u + + #if (!(CHIP_6410 | CHIP_DM641 | CHIP_DM640)) + #define CACHE_CCFG_L2MODE_256KC 0x00000007u /* This is an invalid mode for C6410,DM641,DM640 */ + #endif + +#endif + + #define CACHE_CCFG_OF(x) _VALUEOF(x) + +#if (!C64_SUPPORT) + #define CACHE_CCFG_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CACHE,CCFG,IP) \ + |_PER_FDEFAULT(CACHE,CCFG,ID) \ + |_PER_FDEFAULT(CACHE,CCFG,L2MODE) \ + ) + + #define CACHE_CCFG_RMK(ip,id,l2mode) (Uint32)( \ + _PER_FMK(CACHE,CCFG,IP,ip) \ + |_PER_FMK(CACHE,CCFG,ID,id) \ + |_PER_FMK(CACHE,CCFG,L2MODE,l2mode) \ + ) +#else + #define CACHE_CCFG_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CACHE,CCFG,P) \ + |_PER_FDEFAULT(CACHE,CCFG,IP) \ + |_PER_FDEFAULT(CACHE,CCFG,ID) \ + |_PER_FDEFAULT(CACHE,CCFG,L2MODE) \ + ) + + #define CACHE_CCFG_RMK(p,ip,id,l2mode) (Uint32)( \ + _PER_FMK(CACHE,CCFG,P,p) \ + |_PER_FMK(CACHE,CCFG,IP,ip) \ + |_PER_FMK(CACHE,CCFG,ID,id) \ + |_PER_FMK(CACHE,CCFG,L2MODE,l2mode) \ + ) +#endif + + #define _CACHE_CCFG_FGET(FIELD)\ + _PER_FGET(_CACHE_CCFG_ADDR,CACHE,CCFG,##FIELD) + + #define _CACHE_CCFG_FSET(FIELD,field)\ + _PER_FSET(_CACHE_CCFG_ADDR,CACHE,CCFG,##FIELD,field) + + #define _CACHE_CCFG_FSETS(FIELD,SYM)\ + _PER_FSETS(_CACHE_CCFG_ADDR,CACHE,CCFG,##FIELD,##SYM) + +#endif /* L2CACHE_SUPPORT */ + + +/******************************************************************************\ +* _____________________ +* | | +* | L 2 F B A R | +* |___________________| +* +* L2FBAR - L2 flush base address register +* +* Fields: +* (rw) L2FBAR +* +\******************************************************************************/ +#if (L2CACHE_SUPPORT) + #define _CACHE_L2FBAR_ADDR 0x01844000u + + #define _CACHE_L2FBAR_L2FBAR_MASK 0xFFFFFFFFu + #define _CACHE_L2FBAR_L2FBAR_SHIFT 0x00000000u + #define CACHE_L2FBAR_L2FBAR_DEFAULT 0x00000000u + #define CACHE_L2FBAR_L2FBAR_OF(x) _VALUEOF(x) + + #define CACHE_L2FBAR_OF(x) _VALUEOF(x) + + #define CACHE_L2FBAR_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CACHE,L2FBAR,L2FBAR) \ + ) + + #define CACHE_L2FBAR_RMK(l2fbar) (Uint32)( \ + _PER_FMK(CACHE,L2FBAR,L2FBAR,l2fbar) \ + ) + + #define _CACHE_L2FBAR_FGET(FIELD)\ + _PER_FGET(_CACHE_L2FBAR_ADDR,CACHE,L2FBAR,##FIELD) + + #define _CACHE_L2FBAR_FSET(FIELD,field)\ + _PER_FSET(_CACHE_L2FBAR_ADDR,CACHE,L2FBAR,##FIELD,field) + + #define _CACHE_L2FBAR_FSETS(FIELD,SYM)\ + _PER_FSETS(_CACHE_L2FBAR_ADDR,CACHE,L2FBAR,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* _____________________ +* | | +* | L 2 F W C | +* |___________________| +* +* L2FWC - L2 flush word count register +* +* Fields: +* (rw) L2FWC +* +\******************************************************************************/ +#if (L2CACHE_SUPPORT) + #define _CACHE_L2FWC_ADDR 0x01844004u + + #define _CACHE_L2FWC_L2FWC_MASK 0x0000FFFFu + #define _CACHE_L2FWC_L2FWC_SHIFT 0x00000000u + #define CACHE_L2FWC_L2FWC_DEFAULT 0x00000000u + #define CACHE_L2FWC_L2FWC_OF(x) _VALUEOF(x) + + #define CACHE_L2FWC_OF(x) _VALUEOF(x) + + #define CACHE_L2FWC_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CACHE,L2FWC,L2FWC) \ + ) + + #define CACHE_L2FWC_RMK(l2fwc) (Uint32)( \ + _PER_FMK(CACHE,L2FWC,L2FWC,l2fwc) \ + ) + + #define _CACHE_L2FWC_FGET(FIELD)\ + _PER_FGET(_CACHE_L2FWC_ADDR,CACHE,L2FWC,##FIELD) + + #define _CACHE_L2FWC_FSET(FIELD,field)\ + _PER_FSET(_CACHE_L2FWC_ADDR,CACHE,L2FWC,##FIELD,field) + + #define _CACHE_L2FWC_FSETS(FIELD,SYM)\ + _PER_FSETS(_CACHE_L2FWC_ADDR,CACHE,L2FWC,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* _____________________ +* | | +* | L 2 C B A R | +* |___________________| +* +* L2CBAR - L2 clean base address register +* +* Fields: +* (rw) L2CBAR +* +\******************************************************************************/ +#if (L2CACHE_SUPPORT) + #define _CACHE_L2CBAR_ADDR 0x01844010u + + #define _CACHE_L2CBAR_L2CBAR_MASK 0xFFFFFFFFu + #define _CACHE_L2CBAR_L2CBAR_SHIFT 0x00000000u + #define CACHE_L2CBAR_L2CBAR_DEFAULT 0x00000000u + #define CACHE_L2CBAR_L2CBAR_OF(x) _VALUEOF(x) + + #define CACHE_L2CBAR_OF(x) _VALUEOF(x) + + #define CACHE_L2CBAR_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CACHE,L2CBAR,L2CBAR) \ + ) + + #define CACHE_L2CBAR_RMK(l2cbar) (Uint32)( \ + _PER_FMK(CACHE,L2CBAR,L2CBAR,l2cbar) \ + ) + + #define _CACHE_L2CBAR_FGET(FIELD)\ + _PER_FGET(_CACHE_L2CBAR_ADDR,CACHE,L2CBAR,##FIELD) + + #define _CACHE_L2CBAR_FSET(FIELD,field)\ + _PER_FSET(_CACHE_L2CBAR_ADDR,CACHE,L2CBAR,##FIELD,field) + + #define _CACHE_L2CBAR_FSETS(FIELD,SYM)\ + _PER_FSETS(_CACHE_L2CBAR_ADDR,CACHE,L2CBAR,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* _____________________ +* | | +* | L 2 C W C | +* |___________________| +* +* L2CWC - L2 clean word count register +* +* Fields: +* (rw) L2CWC +* +\******************************************************************************/ +#if (L2CACHE_SUPPORT) + #define _CACHE_L2CWC_ADDR 0x01844014u + + #define _CACHE_L2CWC_L2CWC_MASK 0x0000FFFFu + #define _CACHE_L2CWC_L2CWC_SHIFT 0x00000000u + #define CACHE_L2CWC_L2CWC_DEFAULT 0x00000000u + #define CACHE_L2CWC_L2CWC_OF(x) _VALUEOF(x) + + #define CACHE_L2CWC_OF(x) _VALUEOF(x) + + #define CACHE_L2CWC_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CACHE,L2CWC,L2CWC) \ + ) + + #define CACHE_L2CWC_RMK(l2cwc) (Uint32)( \ + _PER_FMK(CACHE,L2CWC,L2CWC,l2cwc) \ + ) + + #define _CACHE_L2CWC_FGET(FIELD)\ + _PER_FGET(_CACHE_L2CWC_ADDR,CACHE,L2CWC,##FIELD) + + #define _CACHE_L2CWC_FSET(FIELD,field)\ + _PER_FSET(_CACHE_L2CWC_ADDR,CACHE,L2CWC,##FIELD,field) + + #define _CACHE_L2CWC_FSETS(FIELD,SYM)\ + _PER_FSETS(_CACHE_L2CWC_ADDR,CACHE,L2CWC,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* _____________________ +* | | +* | L 1 P F B A R | +* |___________________| +* +* L1PFBAR - L1P flush base address register +* +* Fields: +* (rw) L1PFBAR +* +\******************************************************************************/ +#if (L2CACHE_SUPPORT) + #define _CACHE_L1PFBAR_ADDR 0x01844020u + + #define _CACHE_L1PFBAR_L1PFBAR_MASK 0xFFFFFFFFu + #define _CACHE_L1PFBAR_L1PFBAR_SHIFT 0x00000000u + #define CACHE_L1PFBAR_L1PFBAR_DEFAULT 0x00000000u + #define CACHE_L1PFBAR_L1PFBAR_OF(x) _VALUEOF(x) + + #define CACHE_L1PFBAR_OF(x) _VALUEOF(x) + + #define CACHE_L1PFBAR_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CACHE,L1PFBAR,L1PFBAR) \ + ) + + #define _CACHE_L1PFBAR_FGET(FIELD)\ + _PER_FGET(_CACHE_L1PFBAR_ADDR,CACHE,L1PFBAR,##FIELD) + + #define _CACHE_L1PFBAR_FSET(FIELD,field)\ + _PER_FSET(_CACHE_L1PFBAR_ADDR,CACHE,L1PFBAR,##FIELD,field) + + #define _CACHE_L1PFBAR_FSETS(FIELD,SYM)\ + _PER_FSETS(_CACHE_L1PFBAR_ADDR,CACHE,L1PFBAR,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* _____________________ +* | | +* | L 1 P F W C | +* |___________________| +* +* L1PFWC - L1P flush word count register +* +* Fields: +* (rw) L1PFWC +* +\******************************************************************************/ +#if (L2CACHE_SUPPORT) + #define _CACHE_L1PFWC_ADDR 0x01844024u + + #define _CACHE_L1PFWC_L1PFWC_MASK 0x0000FFFFu + #define _CACHE_L1PFWC_L1PFWC_SHIFT 0x00000000u + #define CACHE_L1PFWC_L1PFWC_DEFAULT 0x00000000u + #define CACHE_L1PFWC_L1PFWC_OF(x) _VALUEOF(x) + + #define CACHE_L1PFWC_OF(x) _VALUEOF(x) + + #define CACHE_L1PFWC_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CACHE,L1PFWC,L1PFWC) \ + ) + + #define CACHE_L1PFWC_RMK(l1pfwc) (Uint32)( \ + _PER_FMK(CACHE,L1PFWC,L1PFWC,l1pfwc) \ + ) + + #define _CACHE_L1PFWC_FGET(FIELD)\ + _PER_FGET(_CACHE_L1PFWC_ADDR,CACHE,L1PFWC,##FIELD) + + #define _CACHE_L1PFWC_FSET(FIELD,field)\ + _PER_FSET(_CACHE_L1PFWC_ADDR,CACHE,L1PFWC,##FIELD,field) + + #define _CACHE_L1PFWC_FSETS(FIELD,SYM)\ + _PER_FSETS(_CACHE_L1PFWC_ADDR,CACHE,L1PFWC,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* _____________________ +* | | +* | L 1 D F B A R | +* |___________________| +* +* L1DFBAR - L1D flush base address register +* +* Fields: +* (rw) L1DFBAR +* +\******************************************************************************/ +#if (L2CACHE_SUPPORT) + #define _CACHE_L1DFBAR_ADDR 0x01844030u + + #define _CACHE_L1DFBAR_L1DFBAR_MASK 0xFFFFFFFFu + #define _CACHE_L1DFBAR_L1DFBAR_SHIFT 0x00000000u + #define CACHE_L1DFBAR_L1DFBAR_DEFAULT 0x00000000u + #define CACHE_L1DFBAR_L1DFBAR_OF(x) _VALUEOF(x) + + #define CACHE_L1DFBAR_OF(x) _VALUEOF(x) + + #define CACHE_L1DFBAR_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CACHE,L1DFBAR,L1DFBAR) \ + ) + + #define CACHE_L1DFBAR_RMK(l1dfbar) (Uint32)( \ + _PER_FMK(CACHE,L1DFBAR,L1DFBAR,l1dfbar) \ + ) + + #define _CACHE_L1DFBAR_FGET(FIELD)\ + _PER_FGET(_CACHE_L1DFBAR_ADDR,CACHE,L1DFBAR,##FIELD) + + #define _CACHE_L1DFBAR_FSET(FIELD,field)\ + _PER_FSET(_CACHE_L1DFBAR_ADDR,CACHE,L1DFBAR,##FIELD,field) + + #define _CACHE_L1DFBAR_FSETS(FIELD,SYM)\ + _PER_FSETS(_CACHE_L1DFBAR_ADDR,CACHE,L1DFBAR,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* _____________________ +* | | +* | L 1 D F W C | +* |___________________| +* +* L1DFWC - L1D flush word count register +* +* Fields: +* (rw) L1DFWC +* +\******************************************************************************/ +#if (L2CACHE_SUPPORT) + #define _CACHE_L1DFWC_ADDR 0x01844034u + + #define _CACHE_L1DFWC_L1DFWC_MASK 0x0000FFFFu + #define _CACHE_L1DFWC_L1DFWC_SHIFT 0x00000000u + #define CACHE_L1DFWC_L1DFWC_DEFAULT 0x00000000u + #define CACHE_L1DFWC_L1DFWC_OF(x) _VALUEOF(x) + + #define CACHE_L1DFWC_OF(x) _VALUEOF(x) + + #define CACHE_L1DFWC_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CACHE,L1DFWC,L1DFWC) \ + ) + + #define CACHE_L1DFWC_RMK(l1dfwc) (Uint32)( \ + _PER_FMK(CACHE,L1DFWC,L1DFWC,l1dfwc) \ + ) + + #define _CACHE_L1DFWC_FGET(FIELD)\ + _PER_FGET(_CACHE_L1DFWC_ADDR,CACHE,L1DFWC,##FIELD) + + #define _CACHE_L1DFWC_FSET(FIELD,field)\ + _PER_FSET(_CACHE_L1DFWC_ADDR,CACHE,L1DFWC,##FIELD,field) + + #define _CACHE_L1DFWC_FSETS(FIELD,SYM)\ + _PER_FSETS(_CACHE_L1DFWC_ADDR,CACHE,L1DFWC,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* _____________________ +* | | +* | L 2 F L U S H | +* |___________________| +* +* L2FLUSH - L2 flush register +* +* Fields: +* (rw) F +* +\******************************************************************************/ +#if (L2CACHE_SUPPORT) + #define _CACHE_L2FLUSH_ADDR 0x01845000u + + #define _CACHE_L2FLUSH_F_MASK 0x00000001u + #define _CACHE_L2FLUSH_F_SHIFT 0x00000000u + #define CACHE_L2FLUSH_F_DEFAULT 0x00000000u + #define CACHE_L2FLUSH_F_OF(x) _VALUEOF(x) + #define CACHE_L2FLUSH_F_NORMAL 0x00000000u + #define CACHE_L2FLUSH_F_FLUSH 0x00000001u + + #define CACHE_L2FLUSH_OF(x) _VALUEOF(x) + + #define CACHE_L2FLUSH_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CACHE,L2FLUSH,F) \ + ) + + #define CACHE_L2FLUSH_RMK(f) (Uint32)( \ + _PER_FMK(CACHE,L2FLUSH,F,f) \ + ) + + #define _CACHE_L2FLUSH_FGET(FIELD)\ + _PER_FGET(_CACHE_L2FLUSH_ADDR,CACHE,L2FLUSH,##FIELD) + + #define _CACHE_L2FLUSH_FSET(FIELD,field)\ + _PER_FSET(_CACHE_L2FLUSH_ADDR,CACHE,L2FLUSH,##FIELD,field) + + #define _CACHE_L2FLUSH_FSETS(FIELD,SYM)\ + _PER_FSETS(_CACHE_L2FLUSH_ADDR,CACHE,L2FLUSH,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* _____________________ +* | | +* | L 2 C L E A N | +* |___________________| +* +* L2CLEAN - L2 clean register +* +* Fields: +* (rw) C +* +\******************************************************************************/ +#if (L2CACHE_SUPPORT) + #define _CACHE_L2CLEAN_ADDR 0x01845004u + + #define _CACHE_L2CLEAN_C_MASK 0x00000001u + #define _CACHE_L2CLEAN_C_SHIFT 0x00000000u + #define CACHE_L2CLEAN_C_DEFAULT 0x00000000u + #define CACHE_L2CLEAN_C_OF(x) _VALUEOF(x) + #define CACHE_L2CLEAN_C_NORMAL 0x00000000u + #define CACHE_L2CLEAN_C_CLEAN 0x00000001u + + #define CACHE_L2CLEAN_OF(x) _VALUEOF(x) + + #define CACHE_L2CLEAN_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CACHE,L2CLEAN,C) \ + ) + + #define CACHE_L2CLEAN_RMK(c) (Uint32)( \ + _PER_FMK(CACHE,L2CLEAN,C,c) \ + ) + + #define _CACHE_L2CLEAN_FGET(FIELD)\ + _PER_FGET(_CACHE_L2CLEAN_ADDR,CACHE,L2CLEAN,##FIELD) + + #define _CACHE_L2CLEAN_FSET(FIELD,field)\ + _PER_FSET(_CACHE_L2CLEAN_ADDR,CACHE,L2CLEAN,##FIELD,field) + + #define _CACHE_L2CLEAN_FSETS(FIELD,SYM)\ + _PER_FSETS(_CACHE_L2CLEAN_ADDR,CACHE,L2CLEAN,##FIELD,##SYM) +#endif + +/******************************************************************************\ +* _____________________ +* | | +* | L 2 A L L O C 0 | +* |___________________| +* +* L2ALLOC0 - L2 allocation register 0 (1) +* +* Fields: +* (rw) Q0CNT (2) (3) +* +* (1) only supported for C6400 +* (2) default value is different from L2ALLOC1, L2ALLOC2, L2ALLOC3 +* (3) Rename bit filed based on spru610 +* +\******************************************************************************/ +#if (L2CACHE_SUPPORT && C64_SUPPORT) + #define _CACHE_L2ALLOC0_ADDR 0x01842000u + + #define _CACHE_L2ALLOC0_Q0CNT_MASK 0x00000007u + #define _CACHE_L2ALLOC0_Q0CNT_SHIFT 0x00000000u + #define CACHE_L2ALLOC0_Q0CNT_DEFAULT 0x00000006u + #define CACHE_L2ALLOC0_Q0CNT_OF(x) _VALUEOF(x) + + #define _CACHE_L2ALLOC0_L2ALLOC_MASK _CACHE_L2ALLOC0_Q0CNT_MASK + #define _CACHE_L2ALLOC0_L2ALLOC_SHIFT _CACHE_L2ALLOC0_Q0CNT_SHIFT + #define CACHE_L2ALLOC0_L2ALLOC_DEFAULT CACHE_L2ALLOC0_Q0CNT_DEFAULT + #define CACHE_L2ALLOC0_L2ALLOC_OF(x) CACHE_L2ALLOC0_Q0CNT_OF(x) + + #define CACHE_L2ALLOC0_OF(x) _VALUEOF(x) + + #define CACHE_L2ALLOC0_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CACHE,L2ALLOC0,Q0CNT) \ + ) + + #define CACHE_L2ALLOC0_RMK(q0cnt)(Uint32)( \ + _PER_FMK(CACHE,L2ALLOC0,Q0CNT,q0cnt) \ + ) + + #define _CACHE_L2ALLOC0_FGET(FIELD)\ + _PER_FGET(_CACHE_L2ALLOC0_ADDR,CACHE,L2ALLOC0,##FIELD) + + #define _CACHE_L2ALLOC0_FSET(FIELD,field)\ + _PER_FSET(_CACHE_L2ALLOC0_ADDR,CACHE,L2ALLOC0,##FIELD,field) + + #define _CACHE_L2ALLOC0_FSETS(FIELD,SYM)\ + _PER_FSETS(_CACHE_L2ALLOC0_ADDR,CACHE,L2ALLOC0,##FIELD,##SYM) + +#endif + +/******************************************************************************\ +* _____________________ +* | | +* | L 2 A L L O C 1 | +* |___________________| +* +* L2ALLOC1 - L2 allocation register 1 (1) +* +* Fields: +* (rw) Q1CNT (2) +* +* (1) only supported for C6400 +* (2) Rename bit filed based on spru610 +* +\******************************************************************************/ +#if (L2CACHE_SUPPORT && C64_SUPPORT) + #define _CACHE_L2ALLOC1_ADDR 0x01842004u + + #define _CACHE_L2ALLOC1_Q1CNT_MASK 0x00000007u + #define _CACHE_L2ALLOC1_Q1CNT_SHIFT 0x00000000u + #define CACHE_L2ALLOC1_Q1CNT_DEFAULT 0x00000002u + #define CACHE_L2ALLOC1_Q1CNT_OF(x) _VALUEOF(x) + + #define _CACHE_L2ALLOC1_L2ALLOC_MASK _CACHE_L2ALLOC1_Q1CNT_MASK + #define _CACHE_L2ALLOC1_L2ALLOC_SHIFT _CACHE_L2ALLOC1_Q1CNT_SHIFT + #define CACHE_L2ALLOC1_L2ALLOC_DEFAULT CACHE_L2ALLOC1_Q1CNT_DEFAULT + #define CACHE_L2ALLOC1_L2ALLOC_OF(x) CACHE_L2ALLOC1_Q1CNT_OF(x) + + #define CACHE_L2ALLOC1_OF(x) _VALUEOF(x) + + #define CACHE_L2ALLOC1_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CACHE,L2ALLOC1,Q1CNT) \ + ) + + #define CACHE_L2ALLOC1_RMK(q1cnt) (Uint32)( \ + _PER_FMK(CACHE,L2ALLOC1,Q1CNT,q1cnt) \ + ) + + #define _CACHE_L2ALLOC1_FGET(FIELD)\ + _PER_FGET(_CACHE_L2ALLOC1_ADDR,CACHE,L2ALLOC1,##FIELD) + + #define _CACHE_L2ALLOC1_FSET(FIELD,field)\ + _PER_FSET(_CACHE_L2ALLOC1_ADDR,CACHE,L2ALLOC1,##FIELD,field) + + #define _CACHE_L2ALLOC1_FSETS(FIELD,SYM)\ + _PER_FSETS(_CACHE_L2ALLOC1_ADDR,CACHE,L2ALLOC1,##FIELD,##SYM) + +#endif + +/******************************************************************************\ +* _____________________ +* | | +* | L 2 A L L O C 2 | +* |___________________| +* +* L2ALLOC2 - L2 allocation register 2 (1) +* +* Fields: +* (rw) Q2CNT (2) +* +* (1) only supported for C6400 +* (2) Rename bit filed based on spru610 +* +\******************************************************************************/ +#if (L2CACHE_SUPPORT && C64_SUPPORT) + #define _CACHE_L2ALLOC2_ADDR 0x01842008u + + #define _CACHE_L2ALLOC2_Q2CNT_MASK 0x00000007u + #define _CACHE_L2ALLOC2_Q2CNT_SHIFT 0x00000000u + #define CACHE_L2ALLOC2_Q2CNT_DEFAULT 0x00000002u + #define CACHE_L2ALLOC2_Q2CNT_OF(x) _VALUEOF(x) + + #define _CACHE_L2ALLOC2_L2ALLOC_MASK _CACHE_L2ALLOC2_Q2CNT_MASK + #define _CACHE_L2ALLOC2_L2ALLOC_SHIFT _CACHE_L2ALLOC2_Q2CNT_SHIFT + #define CACHE_L2ALLOC2_L2ALLOC_DEFAULT CACHE_L2ALLOC2_Q2CNT_DEFAULT + #define CACHE_L2ALLOC2_L2ALLOC_OF(x) CACHE_L2ALLOC2_Q2CNT_OF(x) + + #define CACHE_L2ALLOC2_OF(x) _VALUEOF(x) + + #define CACHE_L2ALLOC2_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CACHE,L2ALLOC2,Q2CNT) \ + ) + + #define CACHE_L2ALLOC2_RMK(q2cnt) (Uint32)( \ + _PER_FMK(CACHE,L2ALLOC2,Q2CNT,q2cnt) \ + ) + + #define _CACHE_L2ALLOC2_FGET(FIELD)\ + _PER_FGET(_CACHE_L2ALLOC2_ADDR,CACHE,L2ALLOC2,##FIELD) + + #define _CACHE_L2ALLOC2_FSET(FIELD,field)\ + _PER_FSET(_CACHE_L2ALLOC2_ADDR,CACHE,L2ALLOC2,##FIELD,field) + + #define _CACHE_L2ALLOC2_FSETS(FIELD,SYM)\ + _PER_FSETS(_CACHE_L2ALLOC2_ADDR,CACHE,L2ALLOC2,##FIELD,##SYM) + +#endif + +/******************************************************************************\ +* _____________________ +* | | +* | L 2 A L L O C 3 | +* |___________________| +* +* L2ALLOC3 - L2 allocation register 3 (1) +* +* Fields: +* (rw) Q2CNT (2) +* +* (1) only supported for C6400 +* (2) Rename bit filed based on spru610 +* +\******************************************************************************/ +#if (L2CACHE_SUPPORT && C64_SUPPORT) + #define _CACHE_L2ALLOC3_ADDR 0x0184200Cu + + #define _CACHE_L2ALLOC3_Q3CNT_MASK 0x00000007u + #define _CACHE_L2ALLOC3_Q3CNT_SHIFT 0x00000000u + #define CACHE_L2ALLOC3_Q3CNT_DEFAULT 0x00000002u + #define CACHE_L2ALLOC3_Q3CNT_OF(x) _VALUEOF(x) + + #define _CACHE_L2ALLOC3_L2ALLOC_MASK _CACHE_L2ALLOC3_Q3CNT_MASK + #define _CACHE_L2ALLOC3_L2ALLOC_SHIFT _CACHE_L2ALLOC3_Q3CNT_SHIFT + #define CACHE_L2ALLOC3_L2ALLOC_DEFAULT CACHE_L2ALLOC3_Q3CNT_DEFAULT + #define CACHE_L2ALLOC3_L2ALLOC_OF(x) CACHE_L2ALLOC3_Q3CNT_OF(x) + + #define CACHE_L2ALLOC3_OF(x) _VALUEOF(x) + + #define CACHE_L2ALLOC3_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CACHE,L2ALLOC3,Q3CNT) \ + ) + + #define CACHE_L2ALLOC3_RMK(q3cnt) (Uint32)( \ + _PER_FMK(CACHE,L2ALLOC3,Q3CNT,q3cnt) \ + ) + + #define _CACHE_L2ALLOC3_FGET(FIELD)\ + _PER_FGET(_CACHE_L2ALLOC3_ADDR,CACHE,L2ALLOC3,##FIELD) + + #define _CACHE_L2ALLOC3_FSET(FIELD,field)\ + _PER_FSET(_CACHE_L2ALLOC3_ADDR,CACHE,L2ALLOC3,##FIELD,field) + + #define _CACHE_L2ALLOC3_FSETS(FIELD,SYM)\ + _PER_FSETS(_CACHE_L2ALLOC3_ADDR,CACHE,L2ALLOC3,##FIELD,##SYM) + +#endif + +/******************************************************************************\ +* _____________________ +* | | +* | M A R | +* |___________________| +* +* MAR0 - memory attribute register 0 (1) +* MAR1 - memory attribute register 1 (1) +* MAR2 - memory attribute register 2 (1) +* ... - ... +* MARn - memory attribute register n (2) +* +* Fields: +* (rw) NR (3) +* (rw) NW (3) +* (rw) PE (3) +* (rw) CE (4) +* +* (1) register values are read only for C6400 +* (2) n = 15 for C6211/C6711, n = 255 for C6400 +* (3) only supported for C6400 +* (4) only supported for C6211/C6711 +* (5) MARn range for C6211/C6711 are from MAR0 ~ MAR15, +* MARn range for C6400 are: +* MAR0 ~ MAR2 : register values read only +* MAR48 ~ MAR51 : McBSP0 +* MAR52 ~ MAR55 : McBSP1 +* MAR56 ~ MAR59 : McBSP2 +* MAR60 ~ MAR63 : UTOPIAII +* MAR64 ~ MAR79 : HPI/PCI +* MAR96 ~ MAR111 : EMIFB (1) +* MAR128 ~ MAR191 : EMIFA +* +* (1) only in C6414, C6415, C6416 variants +\******************************************************************************/ +#if (L2CACHE_SUPPORT && !C64_SUPPORT) + #define _CACHE_MAR0_ADDR _CACHE_MAR128_ADDR + #define _CACHE_MAR1_ADDR _CACHE_MAR129_ADDR + #define _CACHE_MAR2_ADDR _CACHE_MAR130_ADDR + #define _CACHE_MAR3_ADDR _CACHE_MAR131_ADDR + #define _CACHE_MAR4_ADDR _CACHE_MAR144_ADDR + #define _CACHE_MAR5_ADDR _CACHE_MAR145_ADDR + #define _CACHE_MAR6_ADDR _CACHE_MAR146_ADDR + #define _CACHE_MAR7_ADDR _CACHE_MAR147_ADDR + #define _CACHE_MAR8_ADDR _CACHE_MAR160_ADDR + #define _CACHE_MAR9_ADDR _CACHE_MAR161_ADDR + #define _CACHE_MAR10_ADDR _CACHE_MAR162_ADDR + #define _CACHE_MAR11_ADDR _CACHE_MAR163_ADDR + #define _CACHE_MAR12_ADDR _CACHE_MAR176_ADDR + #define _CACHE_MAR13_ADDR _CACHE_MAR177_ADDR + #define _CACHE_MAR14_ADDR _CACHE_MAR178_ADDR + #define _CACHE_MAR15_ADDR _CACHE_MAR179_ADDR + + #define _CACHE_MAR128_ADDR 0x01848200u + #define _CACHE_MAR129_ADDR 0x01848204u + #define _CACHE_MAR130_ADDR 0x01848208u + #define _CACHE_MAR131_ADDR 0x0184820Cu + #define _CACHE_MAR144_ADDR 0x01848240u + #define _CACHE_MAR145_ADDR 0x01848244u + #define _CACHE_MAR146_ADDR 0x01848248u + #define _CACHE_MAR147_ADDR 0x0184824Cu + #define _CACHE_MAR160_ADDR 0x01848280u + #define _CACHE_MAR161_ADDR 0x01848284u + #define _CACHE_MAR162_ADDR 0x01848288u + #define _CACHE_MAR163_ADDR 0x0184828Cu + #define _CACHE_MAR176_ADDR 0x018482C0u + #define _CACHE_MAR177_ADDR 0x018482C4u + #define _CACHE_MAR178_ADDR 0x018482C8u + #define _CACHE_MAR179_ADDR 0x018482CCu + + #define _CACHE_MAR_CE_MASK 0x00000001u + #define _CACHE_MAR_CE_SHIFT 0x00000000u + #define CACHE_MAR_CE_DEFAULT 0x00000000u + #define CACHE_MAR_CE_OF(x) _VALUEOF(x) + #define CACHE_MAR_CE_DISABLE 0x00000000u + #define CACHE_MAR_CE_ENABLE 0x00000001u + + #define CACHE_MAR_OF(x) _VALUEOF(x) + + #define CACHE_MAR_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CACHE,MAR,CE) \ + ) + + #define CACHE_MAR_RMK(ce) (Uint32)( \ + _PER_FMK(CACHE,MAR,CE,ce) \ + ) + + #define _CACHE_MAR_FGET(N,FIELD)\ + _PER_FGET(_CACHE_MAR##N##_ADDR,CACHE,MAR,##FIELD) + + #define _CACHE_MAR_FSET(N,FIELD,field)\ + _PER_FSET(_CACHE_MAR##N##_ADDR,CACHE,MAR,##FIELD,field) + + #define _CACHE_MAR_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_CACHE_MAR##N##_ADDR,CACHE,MAR,##FIELD,##SYM) + + #define _CACHE_MAR0_FGET(FIELD) _CACHE_MAR_FGET(128,##FIELD) + #define _CACHE_MAR1_FGET(FIELD) _CACHE_MAR_FGET(129,##FIELD) + #define _CACHE_MAR2_FGET(FIELD) _CACHE_MAR_FGET(130,##FIELD) + #define _CACHE_MAR3_FGET(FIELD) _CACHE_MAR_FGET(131,##FIELD) + #define _CACHE_MAR4_FGET(FIELD) _CACHE_MAR_FGET(144,##FIELD) + #define _CACHE_MAR5_FGET(FIELD) _CACHE_MAR_FGET(145,##FIELD) + #define _CACHE_MAR6_FGET(FIELD) _CACHE_MAR_FGET(146,##FIELD) + #define _CACHE_MAR7_FGET(FIELD) _CACHE_MAR_FGET(147,##FIELD) + #define _CACHE_MAR8_FGET(FIELD) _CACHE_MAR_FGET(160,##FIELD) + #define _CACHE_MAR9_FGET(FIELD) _CACHE_MAR_FGET(161,##FIELD) + #define _CACHE_MAR10_FGET(FIELD) _CACHE_MAR_FGET(162,##FIELD) + #define _CACHE_MAR11_FGET(FIELD) _CACHE_MAR_FGET(163,##FIELD) + #define _CACHE_MAR12_FGET(FIELD) _CACHE_MAR_FGET(176,##FIELD) + #define _CACHE_MAR13_FGET(FIELD) _CACHE_MAR_FGET(177,##FIELD) + #define _CACHE_MAR14_FGET(FIELD) _CACHE_MAR_FGET(178,##FIELD) + #define _CACHE_MAR15_FGET(FIELD) _CACHE_MAR_FGET(179,##FIELD) + + #define _CACHE_MAR0_FSET(FIELD,f) _CACHE_MAR_FSET(128,##FIELD,f) + #define _CACHE_MAR1_FSET(FIELD,f) _CACHE_MAR_FSET(129,##FIELD,f) + #define _CACHE_MAR2_FSET(FIELD,f) _CACHE_MAR_FSET(130,##FIELD,f) + #define _CACHE_MAR3_FSET(FIELD,f) _CACHE_MAR_FSET(131,##FIELD,f) + #define _CACHE_MAR4_FSET(FIELD,f) _CACHE_MAR_FSET(144,##FIELD,f) + #define _CACHE_MAR5_FSET(FIELD,f) _CACHE_MAR_FSET(145,##FIELD,f) + #define _CACHE_MAR6_FSET(FIELD,f) _CACHE_MAR_FSET(146,##FIELD,f) + #define _CACHE_MAR7_FSET(FIELD,f) _CACHE_MAR_FSET(147,##FIELD,f) + #define _CACHE_MAR8_FSET(FIELD,f) _CACHE_MAR_FSET(160,##FIELD,f) + #define _CACHE_MAR9_FSET(FIELD,f) _CACHE_MAR_FSET(161,##FIELD,f) + #define _CACHE_MAR10_FSET(FIELD,f) _CACHE_MAR_FSET(162,##FIELD,f) + #define _CACHE_MAR11_FSET(FIELD,f) _CACHE_MAR_FSET(163,##FIELD,f) + #define _CACHE_MAR12_FSET(FIELD,f) _CACHE_MAR_FSET(176,##FIELD,f) + #define _CACHE_MAR13_FSET(FIELD,f) _CACHE_MAR_FSET(177,##FIELD,f) + #define _CACHE_MAR14_FSET(FIELD,f) _CACHE_MAR_FSET(178,##FIELD,f) + #define _CACHE_MAR15_FSET(FIELD,f) _CACHE_MAR_FSET(179,##FIELD,f) + + #define _CACHE_MAR0_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(128,##FIELD,##SYM) + #define _CACHE_MAR1_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(129,##FIELD,##SYM) + #define _CACHE_MAR2_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(130,##FIELD,##SYM) + #define _CACHE_MAR3_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(131,##FIELD,##SYM) + #define _CACHE_MAR4_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(144,##FIELD,##SYM) + #define _CACHE_MAR5_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(145,##FIELD,##SYM) + #define _CACHE_MAR6_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(146,##FIELD,##SYM) + #define _CACHE_MAR7_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(147,##FIELD,##SYM) + #define _CACHE_MAR8_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(160,##FIELD,##SYM) + #define _CACHE_MAR9_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(161,##FIELD,##SYM) + #define _CACHE_MAR10_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(162,##FIELD,##SYM) + #define _CACHE_MAR11_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(163,##FIELD,##SYM) + #define _CACHE_MAR12_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(176,##FIELD,##SYM) + #define _CACHE_MAR13_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(177,##FIELD,##SYM) + #define _CACHE_MAR14_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(178,##FIELD,##SYM) + #define _CACHE_MAR15_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(179,##FIELD,##SYM) + + #define _CACHE_MAR128_FGET(FIELD) _CACHE_MAR_FGET(128,##FIELD) + #define _CACHE_MAR129_FGET(FIELD) _CACHE_MAR_FGET(129,##FIELD) + #define _CACHE_MAR130_FGET(FIELD) _CACHE_MAR_FGET(130,##FIELD) + #define _CACHE_MAR131_FGET(FIELD) _CACHE_MAR_FGET(131,##FIELD) + #define _CACHE_MAR144_FGET(FIELD) _CACHE_MAR_FGET(144,##FIELD) + #define _CACHE_MAR145_FGET(FIELD) _CACHE_MAR_FGET(145,##FIELD) + #define _CACHE_MAR146_FGET(FIELD) _CACHE_MAR_FGET(146,##FIELD) + #define _CACHE_MAR147_FGET(FIELD) _CACHE_MAR_FGET(147,##FIELD) + #define _CACHE_MAR160_FGET(FIELD) _CACHE_MAR_FGET(160,##FIELD) + #define _CACHE_MAR161_FGET(FIELD) _CACHE_MAR_FGET(161,##FIELD) + #define _CACHE_MAR162_FGET(FIELD) _CACHE_MAR_FGET(162,##FIELD) + #define _CACHE_MAR163_FGET(FIELD) _CACHE_MAR_FGET(163,##FIELD) + #define _CACHE_MAR176_FGET(FIELD) _CACHE_MAR_FGET(176,##FIELD) + #define _CACHE_MAR177_FGET(FIELD) _CACHE_MAR_FGET(177,##FIELD) + #define _CACHE_MAR178_FGET(FIELD) _CACHE_MAR_FGET(178,##FIELD) + #define _CACHE_MAR179_FGET(FIELD) _CACHE_MAR_FGET(179,##FIELD) + + #define _CACHE_MAR128_FSET(FIELD,f) _CACHE_MAR_FSET(128,##FIELD,f) + #define _CACHE_MAR129_FSET(FIELD,f) _CACHE_MAR_FSET(129,##FIELD,f) + #define _CACHE_MAR130_FSET(FIELD,f) _CACHE_MAR_FSET(130,##FIELD,f) + #define _CACHE_MAR131_FSET(FIELD,f) _CACHE_MAR_FSET(131,##FIELD,f) + #define _CACHE_MAR144_FSET(FIELD,f) _CACHE_MAR_FSET(144,##FIELD,f) + #define _CACHE_MAR145_FSET(FIELD,f) _CACHE_MAR_FSET(145,##FIELD,f) + #define _CACHE_MAR146_FSET(FIELD,f) _CACHE_MAR_FSET(146,##FIELD,f) + #define _CACHE_MAR147_FSET(FIELD,f) _CACHE_MAR_FSET(147,##FIELD,f) + #define _CACHE_MAR160_FSET(FIELD,f) _CACHE_MAR_FSET(160,##FIELD,f) + #define _CACHE_MAR161_FSET(FIELD,f) _CACHE_MAR_FSET(161,##FIELD,f) + #define _CACHE_MAR162_FSET(FIELD,f) _CACHE_MAR_FSET(162,##FIELD,f) + #define _CACHE_MAR163_FSET(FIELD,f) _CACHE_MAR_FSET(163,##FIELD,f) + #define _CACHE_MAR176_FSET(FIELD,f) _CACHE_MAR_FSET(176,##FIELD,f) + #define _CACHE_MAR177_FSET(FIELD,f) _CACHE_MAR_FSET(177,##FIELD,f) + #define _CACHE_MAR178_FSET(FIELD,f) _CACHE_MAR_FSET(178,##FIELD,f) + #define _CACHE_MAR179_FSET(FIELD,f) _CACHE_MAR_FSET(179,##FIELD,f) + + #define _CACHE_MAR128_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(128,##FIELD,##SYM) + #define _CACHE_MAR129_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(129,##FIELD,##SYM) + #define _CACHE_MAR130_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(130,##FIELD,##SYM) + #define _CACHE_MAR131_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(131,##FIELD,##SYM) + #define _CACHE_MAR144_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(144,##FIELD,##SYM) + #define _CACHE_MAR145_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(145,##FIELD,##SYM) + #define _CACHE_MAR146_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(146,##FIELD,##SYM) + #define _CACHE_MAR147_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(147,##FIELD,##SYM) + #define _CACHE_MAR160_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(160,##FIELD,##SYM) + #define _CACHE_MAR161_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(161,##FIELD,##SYM) + #define _CACHE_MAR162_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(162,##FIELD,##SYM) + #define _CACHE_MAR163_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(163,##FIELD,##SYM) + #define _CACHE_MAR176_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(176,##FIELD,##SYM) + #define _CACHE_MAR177_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(177,##FIELD,##SYM) + #define _CACHE_MAR178_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(178,##FIELD,##SYM) + #define _CACHE_MAR179_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(179,##FIELD,##SYM) + +#else + + /* MAR96 to MAR111 are associated with EMIFB memory space. This is supported only in + * the C6414, C6415 and C6416 chips */ + + #if (CHIP_6414 | CHIP_6415 | CHIP_6416) + #define _CACHE_MAR96_ADDR 0x01848180u + #define _CACHE_MAR97_ADDR 0x01848184u + #define _CACHE_MAR98_ADDR 0x01848188u + #define _CACHE_MAR99_ADDR 0x0184818Cu + #define _CACHE_MAR100_ADDR 0x01848190u + #define _CACHE_MAR101_ADDR 0x01848194u + #define _CACHE_MAR102_ADDR 0x01848198u + #define _CACHE_MAR103_ADDR 0x0184819Cu + #define _CACHE_MAR104_ADDR 0x018481A0u + #define _CACHE_MAR105_ADDR 0x018481A4u + #define _CACHE_MAR106_ADDR 0x018481A8u + #define _CACHE_MAR107_ADDR 0x018481ACu + #define _CACHE_MAR108_ADDR 0x018481B0u + #define _CACHE_MAR109_ADDR 0x018481B4u + #define _CACHE_MAR110_ADDR 0x018481B8u + #define _CACHE_MAR111_ADDR 0x018481BCu + #endif + + #define _CACHE_MAR128_ADDR 0x01848200u + #define _CACHE_MAR129_ADDR 0x01848204u + #define _CACHE_MAR130_ADDR 0x01848208u + #define _CACHE_MAR131_ADDR 0x0184820Cu + #define _CACHE_MAR132_ADDR 0x01848210u + #define _CACHE_MAR133_ADDR 0x01848214u + #define _CACHE_MAR134_ADDR 0x01848218u + #define _CACHE_MAR135_ADDR 0x0184821Cu + #define _CACHE_MAR136_ADDR 0x01848220u + #define _CACHE_MAR137_ADDR 0x01848224u + #define _CACHE_MAR138_ADDR 0x01848228u + #define _CACHE_MAR139_ADDR 0x0184822Cu + #define _CACHE_MAR140_ADDR 0x01848230u + #define _CACHE_MAR141_ADDR 0x01848234u + #define _CACHE_MAR142_ADDR 0x01848238u + #define _CACHE_MAR143_ADDR 0x0184823Cu + #define _CACHE_MAR144_ADDR 0x01848240u + #define _CACHE_MAR145_ADDR 0x01848244u + #define _CACHE_MAR146_ADDR 0x01848248u + #define _CACHE_MAR147_ADDR 0x0184824Cu + #define _CACHE_MAR148_ADDR 0x01848250u + #define _CACHE_MAR149_ADDR 0x01848254u + #define _CACHE_MAR150_ADDR 0x01848258u + #define _CACHE_MAR151_ADDR 0x0184825Cu + #define _CACHE_MAR152_ADDR 0x01848260u + #define _CACHE_MAR153_ADDR 0x01848264u + #define _CACHE_MAR154_ADDR 0x01848268u + #define _CACHE_MAR155_ADDR 0x0184826Cu + #define _CACHE_MAR156_ADDR 0x01848270u + #define _CACHE_MAR157_ADDR 0x01848274u + #define _CACHE_MAR158_ADDR 0x01848278u + #define _CACHE_MAR159_ADDR 0x0184827Cu + #define _CACHE_MAR160_ADDR 0x01848280u + #define _CACHE_MAR161_ADDR 0x01848284u + #define _CACHE_MAR162_ADDR 0x01848288u + #define _CACHE_MAR163_ADDR 0x0184828Cu + #define _CACHE_MAR164_ADDR 0x01848290u + #define _CACHE_MAR165_ADDR 0x01848294u + #define _CACHE_MAR166_ADDR 0x01848298u + #define _CACHE_MAR167_ADDR 0x0184829Cu + #define _CACHE_MAR168_ADDR 0x018482A0u + #define _CACHE_MAR169_ADDR 0x018482A4u + #define _CACHE_MAR170_ADDR 0x018482A8u + #define _CACHE_MAR171_ADDR 0x018482ACu + #define _CACHE_MAR172_ADDR 0x018482B0u + #define _CACHE_MAR173_ADDR 0x018482B4u + #define _CACHE_MAR174_ADDR 0x018482B8u + #define _CACHE_MAR175_ADDR 0x018482BCu + #define _CACHE_MAR176_ADDR 0x018482C0u + #define _CACHE_MAR177_ADDR 0x018482C4u + #define _CACHE_MAR178_ADDR 0x018482C8u + #define _CACHE_MAR179_ADDR 0x018482CCu + #define _CACHE_MAR180_ADDR 0x018482D0u + #define _CACHE_MAR181_ADDR 0x018482D4u + #define _CACHE_MAR182_ADDR 0x018482D8u + #define _CACHE_MAR183_ADDR 0x018482DCu + #define _CACHE_MAR184_ADDR 0x018482E0u + #define _CACHE_MAR185_ADDR 0x018482E4u + #define _CACHE_MAR186_ADDR 0x018482E8u + #define _CACHE_MAR187_ADDR 0x018482ECu + #define _CACHE_MAR188_ADDR 0x018482F0u + #define _CACHE_MAR189_ADDR 0x018482F4u + #define _CACHE_MAR190_ADDR 0x018482F8u + #define _CACHE_MAR191_ADDR 0x018482FCu + + #define _CACHE_MAR_CE_MASK 0x00000001u + #define _CACHE_MAR_CE_SHIFT 0x00000000u + #define CACHE_MAR_CE_DEFAULT 0x00000000u + #define CACHE_MAR_CE_OF(x) _VALUEOF(x) + #define CACHE_MAR_CE_DISABLE 0x00000000u + #define CACHE_MAR_CE_ENABLE 0x00000001u + + #define CACHE_MAR_OF(x) _VALUEOF(x) + + #define CACHE_MAR_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CACHE,MAR,CE) \ + ) + + #define CACHE_MAR_RMK(ce) (Uint32)( \ + _PER_FMK(CACHE,MAR,CE,ce) \ + ) + + #define _CACHE_MAR_FGET(N,FIELD)\ + _PER_FGET(_CACHE_MAR##N##_ADDR,CACHE,MAR,##FIELD) + + #define _CACHE_MAR_FSET(N,FIELD,field)\ + _PER_FSET(_CACHE_MAR##N##_ADDR,CACHE,MAR,##FIELD,field) + + #define _CACHE_MAR_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_CACHE_MAR##N##_ADDR,CACHE,MAR,##FIELD,##SYM) + + #if (CHIP_6414 | CHIP_6415 | CHIP_6416) + #define _CACHE_MAR96_FGET(FIELD) _CACHE_MAR_FGET(96,##FIELD) + #define _CACHE_MAR97_FGET(FIELD) _CACHE_MAR_FGET(97,##FIELD) + #define _CACHE_MAR98_FGET(FIELD) _CACHE_MAR_FGET(98,##FIELD) + #define _CACHE_MAR99_FGET(FIELD) _CACHE_MAR_FGET(99,##FIELD) + #define _CACHE_MAR100_FGET(FIELD) _CACHE_MAR_FGET(100,##FIELD) + #define _CACHE_MAR101_FGET(FIELD) _CACHE_MAR_FGET(101,##FIELD) + #define _CACHE_MAR102_FGET(FIELD) _CACHE_MAR_FGET(102,##FIELD) + #define _CACHE_MAR103_FGET(FIELD) _CACHE_MAR_FGET(103,##FIELD) + #define _CACHE_MAR104_FGET(FIELD) _CACHE_MAR_FGET(104,##FIELD) + #define _CACHE_MAR105_FGET(FIELD) _CACHE_MAR_FGET(105,##FIELD) + #define _CACHE_MAR106_FGET(FIELD) _CACHE_MAR_FGET(106,##FIELD) + #define _CACHE_MAR107_FGET(FIELD) _CACHE_MAR_FGET(107,##FIELD) + #define _CACHE_MAR108_FGET(FIELD) _CACHE_MAR_FGET(108,##FIELD) + #define _CACHE_MAR109_FGET(FIELD) _CACHE_MAR_FGET(109,##FIELD) + #define _CACHE_MAR110_FGET(FIELD) _CACHE_MAR_FGET(110,##FIELD) + #define _CACHE_MAR111_FGET(FIELD) _CACHE_MAR_FGET(111,##FIELD) + #endif + + #define _CACHE_MAR128_FGET(FIELD) _CACHE_MAR_FGET(128,##FIELD) + #define _CACHE_MAR129_FGET(FIELD) _CACHE_MAR_FGET(129,##FIELD) + #define _CACHE_MAR130_FGET(FIELD) _CACHE_MAR_FGET(130,##FIELD) + #define _CACHE_MAR131_FGET(FIELD) _CACHE_MAR_FGET(131,##FIELD) + #define _CACHE_MAR132_FGET(FIELD) _CACHE_MAR_FGET(132,##FIELD) + #define _CACHE_MAR133_FGET(FIELD) _CACHE_MAR_FGET(133,##FIELD) + #define _CACHE_MAR134_FGET(FIELD) _CACHE_MAR_FGET(134,##FIELD) + #define _CACHE_MAR135_FGET(FIELD) _CACHE_MAR_FGET(135,##FIELD) + #define _CACHE_MAR136_FGET(FIELD) _CACHE_MAR_FGET(136,##FIELD) + #define _CACHE_MAR137_FGET(FIELD) _CACHE_MAR_FGET(137,##FIELD) + #define _CACHE_MAR138_FGET(FIELD) _CACHE_MAR_FGET(138,##FIELD) + #define _CACHE_MAR139_FGET(FIELD) _CACHE_MAR_FGET(139,##FIELD) + #define _CACHE_MAR140_FGET(FIELD) _CACHE_MAR_FGET(140,##FIELD) + #define _CACHE_MAR141_FGET(FIELD) _CACHE_MAR_FGET(141,##FIELD) + #define _CACHE_MAR142_FGET(FIELD) _CACHE_MAR_FGET(142,##FIELD) + #define _CACHE_MAR143_FGET(FIELD) _CACHE_MAR_FGET(143,##FIELD) + #define _CACHE_MAR144_FGET(FIELD) _CACHE_MAR_FGET(144,##FIELD) + #define _CACHE_MAR145_FGET(FIELD) _CACHE_MAR_FGET(145,##FIELD) + #define _CACHE_MAR146_FGET(FIELD) _CACHE_MAR_FGET(146,##FIELD) + #define _CACHE_MAR147_FGET(FIELD) _CACHE_MAR_FGET(147,##FIELD) + #define _CACHE_MAR148_FGET(FIELD) _CACHE_MAR_FGET(148,##FIELD) + #define _CACHE_MAR149_FGET(FIELD) _CACHE_MAR_FGET(149,##FIELD) + #define _CACHE_MAR150_FGET(FIELD) _CACHE_MAR_FGET(150,##FIELD) + #define _CACHE_MAR151_FGET(FIELD) _CACHE_MAR_FGET(151,##FIELD) + #define _CACHE_MAR152_FGET(FIELD) _CACHE_MAR_FGET(152,##FIELD) + #define _CACHE_MAR153_FGET(FIELD) _CACHE_MAR_FGET(153,##FIELD) + #define _CACHE_MAR154_FGET(FIELD) _CACHE_MAR_FGET(154,##FIELD) + #define _CACHE_MAR155_FGET(FIELD) _CACHE_MAR_FGET(155,##FIELD) + #define _CACHE_MAR156_FGET(FIELD) _CACHE_MAR_FGET(156,##FIELD) + #define _CACHE_MAR157_FGET(FIELD) _CACHE_MAR_FGET(157,##FIELD) + #define _CACHE_MAR158_FGET(FIELD) _CACHE_MAR_FGET(158,##FIELD) + #define _CACHE_MAR159_FGET(FIELD) _CACHE_MAR_FGET(159,##FIELD) + #define _CACHE_MAR160_FGET(FIELD) _CACHE_MAR_FGET(160,##FIELD) + #define _CACHE_MAR161_FGET(FIELD) _CACHE_MAR_FGET(161,##FIELD) + #define _CACHE_MAR162_FGET(FIELD) _CACHE_MAR_FGET(162,##FIELD) + #define _CACHE_MAR163_FGET(FIELD) _CACHE_MAR_FGET(163,##FIELD) + #define _CACHE_MAR164_FGET(FIELD) _CACHE_MAR_FGET(164,##FIELD) + #define _CACHE_MAR165_FGET(FIELD) _CACHE_MAR_FGET(165,##FIELD) + #define _CACHE_MAR166_FGET(FIELD) _CACHE_MAR_FGET(166,##FIELD) + #define _CACHE_MAR167_FGET(FIELD) _CACHE_MAR_FGET(167,##FIELD) + #define _CACHE_MAR168_FGET(FIELD) _CACHE_MAR_FGET(168,##FIELD) + #define _CACHE_MAR169_FGET(FIELD) _CACHE_MAR_FGET(169,##FIELD) + #define _CACHE_MAR170_FGET(FIELD) _CACHE_MAR_FGET(170,##FIELD) + #define _CACHE_MAR171_FGET(FIELD) _CACHE_MAR_FGET(171,##FIELD) + #define _CACHE_MAR172_FGET(FIELD) _CACHE_MAR_FGET(172,##FIELD) + #define _CACHE_MAR173_FGET(FIELD) _CACHE_MAR_FGET(173,##FIELD) + #define _CACHE_MAR174_FGET(FIELD) _CACHE_MAR_FGET(174,##FIELD) + #define _CACHE_MAR175_FGET(FIELD) _CACHE_MAR_FGET(175,##FIELD) + #define _CACHE_MAR176_FGET(FIELD) _CACHE_MAR_FGET(176,##FIELD) + #define _CACHE_MAR177_FGET(FIELD) _CACHE_MAR_FGET(177,##FIELD) + #define _CACHE_MAR178_FGET(FIELD) _CACHE_MAR_FGET(178,##FIELD) + #define _CACHE_MAR179_FGET(FIELD) _CACHE_MAR_FGET(179,##FIELD) + #define _CACHE_MAR180_FGET(FIELD) _CACHE_MAR_FGET(180,##FIELD) + #define _CACHE_MAR181_FGET(FIELD) _CACHE_MAR_FGET(181,##FIELD) + #define _CACHE_MAR182_FGET(FIELD) _CACHE_MAR_FGET(182,##FIELD) + #define _CACHE_MAR183_FGET(FIELD) _CACHE_MAR_FGET(183,##FIELD) + #define _CACHE_MAR184_FGET(FIELD) _CACHE_MAR_FGET(184,##FIELD) + #define _CACHE_MAR185_FGET(FIELD) _CACHE_MAR_FGET(185,##FIELD) + #define _CACHE_MAR186_FGET(FIELD) _CACHE_MAR_FGET(186,##FIELD) + #define _CACHE_MAR187_FGET(FIELD) _CACHE_MAR_FGET(187,##FIELD) + #define _CACHE_MAR188_FGET(FIELD) _CACHE_MAR_FGET(188,##FIELD) + #define _CACHE_MAR189_FGET(FIELD) _CACHE_MAR_FGET(189,##FIELD) + #define _CACHE_MAR190_FGET(FIELD) _CACHE_MAR_FGET(190,##FIELD) + #define _CACHE_MAR191_FGET(FIELD) _CACHE_MAR_FGET(191,##FIELD) + + #if (CHIP_6414 | CHIP_6415 | CHIP_6416) + #define _CACHE_MAR96_FSET(FIELD,f) _CACHE_MAR_FSET(96,##FIELD,f) + #define _CACHE_MAR97_FSET(FIELD,f) _CACHE_MAR_FSET(97,##FIELD,f) + #define _CACHE_MAR98_FSET(FIELD,f) _CACHE_MAR_FSET(98,##FIELD,f) + #define _CACHE_MAR99_FSET(FIELD,f) _CACHE_MAR_FSET(99,##FIELD,f) + #define _CACHE_MAR100_FSET(FIELD,f) _CACHE_MAR_FSET(100,##FIELD,f) + #define _CACHE_MAR101_FSET(FIELD,f) _CACHE_MAR_FSET(101,##FIELD,f) + #define _CACHE_MAR102_FSET(FIELD,f) _CACHE_MAR_FSET(102,##FIELD,f) + #define _CACHE_MAR103_FSET(FIELD,f) _CACHE_MAR_FSET(103,##FIELD,f) + #define _CACHE_MAR104_FSET(FIELD,f) _CACHE_MAR_FSET(104,##FIELD,f) + #define _CACHE_MAR105_FSET(FIELD,f) _CACHE_MAR_FSET(105,##FIELD,f) + #define _CACHE_MAR106_FSET(FIELD,f) _CACHE_MAR_FSET(106,##FIELD,f) + #define _CACHE_MAR107_FSET(FIELD,f) _CACHE_MAR_FSET(107,##FIELD,f) + #define _CACHE_MAR108_FSET(FIELD,f) _CACHE_MAR_FSET(108,##FIELD,f) + #define _CACHE_MAR109_FSET(FIELD,f) _CACHE_MAR_FSET(109,##FIELD,f) + #define _CACHE_MAR110_FSET(FIELD,f) _CACHE_MAR_FSET(110,##FIELD,f) + #define _CACHE_MAR111_FSET(FIELD,f) _CACHE_MAR_FSET(111,##FIELD,f) + #endif + + #define _CACHE_MAR128_FSET(FIELD,f) _CACHE_MAR_FSET(128,##FIELD,f) + #define _CACHE_MAR129_FSET(FIELD,f) _CACHE_MAR_FSET(129,##FIELD,f) + #define _CACHE_MAR130_FSET(FIELD,f) _CACHE_MAR_FSET(130,##FIELD,f) + #define _CACHE_MAR131_FSET(FIELD,f) _CACHE_MAR_FSET(131,##FIELD,f) + #define _CACHE_MAR132_FSET(FIELD,f) _CACHE_MAR_FSET(132,##FIELD,f) + #define _CACHE_MAR133_FSET(FIELD,f) _CACHE_MAR_FSET(133,##FIELD,f) + #define _CACHE_MAR134_FSET(FIELD,f) _CACHE_MAR_FSET(134,##FIELD,f) + #define _CACHE_MAR135_FSET(FIELD,f) _CACHE_MAR_FSET(135,##FIELD,f) + #define _CACHE_MAR136_FSET(FIELD,f) _CACHE_MAR_FSET(136,##FIELD,f) + #define _CACHE_MAR137_FSET(FIELD,f) _CACHE_MAR_FSET(137,##FIELD,f) + #define _CACHE_MAR138_FSET(FIELD,f) _CACHE_MAR_FSET(138,##FIELD,f) + #define _CACHE_MAR139_FSET(FIELD,f) _CACHE_MAR_FSET(139,##FIELD,f) + #define _CACHE_MAR140_FSET(FIELD,f) _CACHE_MAR_FSET(140,##FIELD,f) + #define _CACHE_MAR141_FSET(FIELD,f) _CACHE_MAR_FSET(141,##FIELD,f) + #define _CACHE_MAR142_FSET(FIELD,f) _CACHE_MAR_FSET(142,##FIELD,f) + #define _CACHE_MAR143_FSET(FIELD,f) _CACHE_MAR_FSET(143,##FIELD,f) + #define _CACHE_MAR144_FSET(FIELD,f) _CACHE_MAR_FSET(144,##FIELD,f) + #define _CACHE_MAR145_FSET(FIELD,f) _CACHE_MAR_FSET(145,##FIELD,f) + #define _CACHE_MAR146_FSET(FIELD,f) _CACHE_MAR_FSET(146,##FIELD,f) + #define _CACHE_MAR147_FSET(FIELD,f) _CACHE_MAR_FSET(147,##FIELD,f) + #define _CACHE_MAR148_FSET(FIELD,f) _CACHE_MAR_FSET(148,##FIELD,f) + #define _CACHE_MAR149_FSET(FIELD,f) _CACHE_MAR_FSET(149,##FIELD,f) + #define _CACHE_MAR150_FSET(FIELD,f) _CACHE_MAR_FSET(150,##FIELD,f) + #define _CACHE_MAR151_FSET(FIELD,f) _CACHE_MAR_FSET(151,##FIELD,f) + #define _CACHE_MAR152_FSET(FIELD,f) _CACHE_MAR_FSET(152,##FIELD,f) + #define _CACHE_MAR153_FSET(FIELD,f) _CACHE_MAR_FSET(153,##FIELD,f) + #define _CACHE_MAR154_FSET(FIELD,f) _CACHE_MAR_FSET(154,##FIELD,f) + #define _CACHE_MAR155_FSET(FIELD,f) _CACHE_MAR_FSET(155,##FIELD,f) + #define _CACHE_MAR156_FSET(FIELD,f) _CACHE_MAR_FSET(156,##FIELD,f) + #define _CACHE_MAR157_FSET(FIELD,f) _CACHE_MAR_FSET(157,##FIELD,f) + #define _CACHE_MAR158_FSET(FIELD,f) _CACHE_MAR_FSET(158,##FIELD,f) + #define _CACHE_MAR159_FSET(FIELD,f) _CACHE_MAR_FSET(159,##FIELD,f) + #define _CACHE_MAR160_FSET(FIELD,f) _CACHE_MAR_FSET(160,##FIELD,f) + #define _CACHE_MAR161_FSET(FIELD,f) _CACHE_MAR_FSET(161,##FIELD,f) + #define _CACHE_MAR162_FSET(FIELD,f) _CACHE_MAR_FSET(162,##FIELD,f) + #define _CACHE_MAR163_FSET(FIELD,f) _CACHE_MAR_FSET(163,##FIELD,f) + #define _CACHE_MAR164_FSET(FIELD,f) _CACHE_MAR_FSET(164,##FIELD,f) + #define _CACHE_MAR165_FSET(FIELD,f) _CACHE_MAR_FSET(165,##FIELD,f) + #define _CACHE_MAR166_FSET(FIELD,f) _CACHE_MAR_FSET(166,##FIELD,f) + #define _CACHE_MAR167_FSET(FIELD,f) _CACHE_MAR_FSET(167,##FIELD,f) + #define _CACHE_MAR168_FSET(FIELD,f) _CACHE_MAR_FSET(168,##FIELD,f) + #define _CACHE_MAR169_FSET(FIELD,f) _CACHE_MAR_FSET(169,##FIELD,f) + #define _CACHE_MAR170_FSET(FIELD,f) _CACHE_MAR_FSET(170,##FIELD,f) + #define _CACHE_MAR171_FSET(FIELD,f) _CACHE_MAR_FSET(171,##FIELD,f) + #define _CACHE_MAR172_FSET(FIELD,f) _CACHE_MAR_FSET(172,##FIELD,f) + #define _CACHE_MAR173_FSET(FIELD,f) _CACHE_MAR_FSET(173,##FIELD,f) + #define _CACHE_MAR174_FSET(FIELD,f) _CACHE_MAR_FSET(174,##FIELD,f) + #define _CACHE_MAR175_FSET(FIELD,f) _CACHE_MAR_FSET(175,##FIELD,f) + #define _CACHE_MAR176_FSET(FIELD,f) _CACHE_MAR_FSET(176,##FIELD,f) + #define _CACHE_MAR177_FSET(FIELD,f) _CACHE_MAR_FSET(177,##FIELD,f) + #define _CACHE_MAR178_FSET(FIELD,f) _CACHE_MAR_FSET(178,##FIELD,f) + #define _CACHE_MAR179_FSET(FIELD,f) _CACHE_MAR_FSET(179,##FIELD,f) + #define _CACHE_MAR180_FSET(FIELD,f) _CACHE_MAR_FSET(180,##FIELD,f) + #define _CACHE_MAR181_FSET(FIELD,f) _CACHE_MAR_FSET(181,##FIELD,f) + #define _CACHE_MAR182_FSET(FIELD,f) _CACHE_MAR_FSET(182,##FIELD,f) + #define _CACHE_MAR183_FSET(FIELD,f) _CACHE_MAR_FSET(183,##FIELD,f) + #define _CACHE_MAR184_FSET(FIELD,f) _CACHE_MAR_FSET(184,##FIELD,f) + #define _CACHE_MAR185_FSET(FIELD,f) _CACHE_MAR_FSET(185,##FIELD,f) + #define _CACHE_MAR186_FSET(FIELD,f) _CACHE_MAR_FSET(186,##FIELD,f) + #define _CACHE_MAR187_FSET(FIELD,f) _CACHE_MAR_FSET(187,##FIELD,f) + #define _CACHE_MAR188_FSET(FIELD,f) _CACHE_MAR_FSET(188,##FIELD,f) + #define _CACHE_MAR189_FSET(FIELD,f) _CACHE_MAR_FSET(189,##FIELD,f) + #define _CACHE_MAR190_FSET(FIELD,f) _CACHE_MAR_FSET(190,##FIELD,f) + #define _CACHE_MAR191_FSET(FIELD,f) _CACHE_MAR_FSET(191,##FIELD,f) + + #if (CHIP_6414 | CHIP_6415 | CHIP_6416) + #define _CACHE_MAR96_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(96,##FIELD,##SYM) + #define _CACHE_MAR97_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(97,##FIELD,##SYM) + #define _CACHE_MAR98_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(98,##FIELD,##SYM) + #define _CACHE_MAR99_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(99,##FIELD,##SYM) + #define _CACHE_MAR100_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(100,##FIELD,##SYM) + #define _CACHE_MAR101_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(101,##FIELD,##SYM) + #define _CACHE_MAR102_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(102,##FIELD,##SYM) + #define _CACHE_MAR103_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(103,##FIELD,##SYM) + #define _CACHE_MAR104_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(104,##FIELD,##SYM) + #define _CACHE_MAR105_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(105,##FIELD,##SYM) + #define _CACHE_MAR106_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(106,##FIELD,##SYM) + #define _CACHE_MAR107_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(107,##FIELD,##SYM) + #define _CACHE_MAR108_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(108,##FIELD,##SYM) + #define _CACHE_MAR109_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(109,##FIELD,##SYM) + #define _CACHE_MAR110_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(110,##FIELD,##SYM) + #define _CACHE_MAR111_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(111,##FIELD,##SYM) + #endif + + #define _CACHE_MAR128_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(128,##FIELD,##SYM) + #define _CACHE_MAR129_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(129,##FIELD,##SYM) + #define _CACHE_MAR130_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(130,##FIELD,##SYM) + #define _CACHE_MAR131_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(131,##FIELD,##SYM) + #define _CACHE_MAR132_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(132,##FIELD,##SYM) + #define _CACHE_MAR133_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(133,##FIELD,##SYM) + #define _CACHE_MAR134_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(134,##FIELD,##SYM) + #define _CACHE_MAR135_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(135,##FIELD,##SYM) + #define _CACHE_MAR136_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(136,##FIELD,##SYM) + #define _CACHE_MAR137_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(137,##FIELD,##SYM) + #define _CACHE_MAR138_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(138,##FIELD,##SYM) + #define _CACHE_MAR139_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(139,##FIELD,##SYM) + #define _CACHE_MAR140_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(140,##FIELD,##SYM) + #define _CACHE_MAR141_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(141,##FIELD,##SYM) + #define _CACHE_MAR142_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(142,##FIELD,##SYM) + #define _CACHE_MAR143_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(143,##FIELD,##SYM) + #define _CACHE_MAR144_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(144,##FIELD,##SYM) + #define _CACHE_MAR145_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(145,##FIELD,##SYM) + #define _CACHE_MAR146_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(146,##FIELD,##SYM) + #define _CACHE_MAR147_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(147,##FIELD,##SYM) + #define _CACHE_MAR148_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(148,##FIELD,##SYM) + #define _CACHE_MAR149_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(149,##FIELD,##SYM) + #define _CACHE_MAR150_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(150,##FIELD,##SYM) + #define _CACHE_MAR151_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(151,##FIELD,##SYM) + #define _CACHE_MAR152_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(152,##FIELD,##SYM) + #define _CACHE_MAR153_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(153,##FIELD,##SYM) + #define _CACHE_MAR154_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(154,##FIELD,##SYM) + #define _CACHE_MAR155_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(155,##FIELD,##SYM) + #define _CACHE_MAR156_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(156,##FIELD,##SYM) + #define _CACHE_MAR157_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(157,##FIELD,##SYM) + #define _CACHE_MAR158_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(158,##FIELD,##SYM) + #define _CACHE_MAR159_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(159,##FIELD,##SYM) + #define _CACHE_MAR160_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(160,##FIELD,##SYM) + #define _CACHE_MAR161_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(161,##FIELD,##SYM) + #define _CACHE_MAR162_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(162,##FIELD,##SYM) + #define _CACHE_MAR163_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(163,##FIELD,##SYM) + #define _CACHE_MAR164_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(164,##FIELD,##SYM) + #define _CACHE_MAR165_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(165,##FIELD,##SYM) + #define _CACHE_MAR166_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(166,##FIELD,##SYM) + #define _CACHE_MAR167_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(167,##FIELD,##SYM) + #define _CACHE_MAR168_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(168,##FIELD,##SYM) + #define _CACHE_MAR169_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(169,##FIELD,##SYM) + #define _CACHE_MAR170_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(170,##FIELD,##SYM) + #define _CACHE_MAR171_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(171,##FIELD,##SYM) + #define _CACHE_MAR172_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(172,##FIELD,##SYM) + #define _CACHE_MAR173_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(173,##FIELD,##SYM) + #define _CACHE_MAR174_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(174,##FIELD,##SYM) + #define _CACHE_MAR175_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(175,##FIELD,##SYM) + #define _CACHE_MAR176_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(176,##FIELD,##SYM) + #define _CACHE_MAR177_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(177,##FIELD,##SYM) + #define _CACHE_MAR178_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(178,##FIELD,##SYM) + #define _CACHE_MAR179_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(179,##FIELD,##SYM) + #define _CACHE_MAR180_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(180,##FIELD,##SYM) + #define _CACHE_MAR181_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(181,##FIELD,##SYM) + #define _CACHE_MAR182_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(182,##FIELD,##SYM) + #define _CACHE_MAR183_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(183,##FIELD,##SYM) + #define _CACHE_MAR184_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(184,##FIELD,##SYM) + #define _CACHE_MAR185_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(185,##FIELD,##SYM) + #define _CACHE_MAR186_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(186,##FIELD,##SYM) + #define _CACHE_MAR187_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(187,##FIELD,##SYM) + #define _CACHE_MAR188_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(188,##FIELD,##SYM) + #define _CACHE_MAR189_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(189,##FIELD,##SYM) + #define _CACHE_MAR190_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(190,##FIELD,##SYM) + #define _CACHE_MAR191_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(191,##FIELD,##SYM) +#endif + +/******************************************************************************\ +* _____________________ +* | | +* | L 2 W B A R | +* |___________________| +* +* L2WBAR - L2 writeback base address register +* +* Fields: +* (rw) L2WBAR +* +\******************************************************************************/ +#if (L2CACHE_SUPPORT) + #define _CACHE_L2WBAR_ADDR 0x01844000u + + #define _CACHE_L2WBAR_L2WBAR_MASK 0xFFFFFFFFu + #define _CACHE_L2WBAR_L2WBAR_SHIFT 0x00000000u + #define CACHE_L2WBAR_L2WBAR_DEFAULT 0x00000000u + #define CACHE_L2WBAR_L2WBAR_OF(x) _VALUEOF(x) + + #define CACHE_L2WBAR_OF(x) _VALUEOF(x) + + #define CACHE_L2WBAR_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CACHE,L2WBAR,L2WBAR) \ + ) + + #define CACHE_L2WBAR_RMK(l2wbar) (Uint32)( \ + _PER_FMK(CACHE,L2WBAR,L2WBAR,l2wbar) \ + ) + + #define _CACHE_L2WBAR_FGET(FIELD)\ + _PER_FGET(_CACHE_L2WBAR_ADDR,CACHE,L2WBAR,##FIELD) + + #define _CACHE_L2WBAR_FSET(FIELD,field)\ + _PER_FSET(_CACHE_L2WBAR_ADDR,CACHE,L2WBAR,##FIELD,field) + + #define _CACHE_L2WBAR_FSETS(FIELD,SYM)\ + _PER_FSETS(_CACHE_L2WBAR_ADDR,CACHE,L2WBAR,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* _____________________ +* | | +* | L 2 W W C | +* |___________________| +* +* L2WWC - L2 writeback word count register +* +* Fields: +* (rw) L2WWC +* +\******************************************************************************/ +#if (L2CACHE_SUPPORT) + #define _CACHE_L2WWC_ADDR 0x01844004u + + #define _CACHE_L2WWC_L2WWC_MASK 0x0000FFFFu + #define _CACHE_L2WWC_L2WWC_SHIFT 0x00000000u + #define CACHE_L2WWC_L2WWC_DEFAULT 0x00000000u + #define CACHE_L2WWC_L2WWC_OF(x) _VALUEOF(x) + + #define CACHE_L2WWC_OF(x) _VALUEOF(x) + + #define CACHE_L2WWC_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CACHE,L2WWC,L2WWC) \ + ) + + #define CACHE_L2WWC_RMK(l2wwc) (Uint32)( \ + _PER_FMK(CACHE,L2WWC,L2WWC,l2wwc) \ + ) + + #define _CACHE_L2WWC_FGET(FIELD)\ + _PER_FGET(_CACHE_L2WWC_ADDR,CACHE,L2WWC,##FIELD) + + #define _CACHE_L2WWC_FSET(FIELD,field)\ + _PER_FSET(_CACHE_L2WWC_ADDR,CACHE,L2WWC,##FIELD,field) + + #define _CACHE_L2WWC_FSETS(FIELD,SYM)\ + _PER_FSETS(_CACHE_L2WWC_ADDR,CACHE,L2WWC,##FIELD,##SYM) +#endif + +/******************************************************************************\ +* _____________________ +* | | +* | L 2 W I B A R | +* |___________________| +* +* L2WIBAR - L2 writeback-invalidate base address register +* +* Fields: +* (rw) L2WIBAR +* +\******************************************************************************/ +#if (L2CACHE_SUPPORT) + #define _CACHE_L2WIBAR_ADDR 0x01844010u + + #define _CACHE_L2WIBAR_L2WIBAR_MASK 0xFFFFFFFFu + #define _CACHE_L2WIBAR_L2WIBAR_SHIFT 0x00000000u + #define CACHE_L2WIBAR_L2WIBAR_DEFAULT 0x00000000u + #define CACHE_L2WIBAR_L2WIBAR_OF(x) _VALUEOF(x) + + #define CACHE_L2WIBAR_OF(x) _VALUEOF(x) + + #define CACHE_L2WIBAR_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CACHE,L2WIBAR,L2WIBAR) \ + ) + + #define CACHE_L2WIBAR_RMK(l2wibar) (Uint32)( \ + _PER_FMK(CACHE,L2WIBAR,L2WIBAR,l2wibar) \ + ) + + #define _CACHE_L2WIBAR_FGET(FIELD)\ + _PER_FGET(_CACHE_L2WIBAR_ADDR,CACHE,L2WIBAR,##FIELD) + + #define _CACHE_L2WIBAR_FSET(FIELD,field)\ + _PER_FSET(_CACHE_L2WIBAR_ADDR,CACHE,L2WIBAR,##FIELD,field) + + #define _CACHE_L2WIBAR_FSETS(FIELD,SYM)\ + _PER_FSETS(_CACHE_L2WIBAR_ADDR,CACHE,L2WIBAR,##FIELD,##SYM) +#endif + +/******************************************************************************\ +* _____________________ +* | | +* | L 2 W I W C | +* |___________________| +* +* L2WIWC - L2 writeback-invalidate word count register +* +* Fields: +* (rw) L2WIWC +* +\******************************************************************************/ +#if (L2CACHE_SUPPORT) + #define _CACHE_L2WIWC_ADDR 0x01844014u + + #define _CACHE_L2WIWC_L2WIWC_MASK 0x0000FFFFu + #define _CACHE_L2WIWC_L2WIWC_SHIFT 0x00000000u + #define CACHE_L2WIWC_L2WIWC_DEFAULT 0x00000000u + #define CACHE_L2WIWC_L2WIWC_OF(x) _VALUEOF(x) + + #define CACHE_L2WIWC_OF(x) _VALUEOF(x) + + #define CACHE_L2WIWC_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CACHE,L2WIWC,L2WIWC) \ + ) + + #define CACHE_L2WIWC_RMK(l2wiwc) (Uint32)( \ + _PER_FMK(CACHE,L2WIWC,L2WIWC,l2wiwc) \ + ) + + #define _CACHE_L2WIWC_FGET(FIELD)\ + _PER_FGET(_CACHE_L2WIWC_ADDR,CACHE,L2WIWC,##FIELD) + + #define _CACHE_L2WIWC_FSET(FIELD,field)\ + _PER_FSET(_CACHE_L2WIWC_ADDR,CACHE,L2WIWC,##FIELD,field) + + #define _CACHE_L2WIWC_FSETS(FIELD,SYM)\ + _PER_FSETS(_CACHE_L2WIWC_ADDR,CACHE,L2WIWC,##FIELD,##SYM) +#endif + +/******************************************************************************\ +* ___________________ +* | | +* | L 2 I B A R | +* |_________________| +* +* L2IBAR - L2 invalidate base address register +* +* Fields: +* (rw) L2IBAR +* +\******************************************************************************/ +#if (L2CACHE_SUPPORT && C64_SUPPORT) + #define _CACHE_L2IBAR_ADDR 0x01844018u + + #define _CACHE_L2IBAR_L2IBAR_MASK 0xFFFFFFFFu + #define _CACHE_L2IBAR_L2IBAR_SHIFT 0x00000000u + #define CACHE_L2IBAR_L2IBAR_DEFAULT 0x00000000u + #define CACHE_L2IBAR_L2IBAR_OF(x) _VALUEOF(x) + + #define CACHE_L2IBAR_OF(x) _VALUEOF(x) + + #define CACHE_L2IBAR_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CACHE,L2IBAR,L2IBAR) \ + ) + + #define CACHE_L2IBAR_RMK(l2ibar) (Uint32)( \ + _PER_FMK(CACHE,L2IBAR,L2IBAR,l2ibar) \ + ) + + #define _CACHE_L2IBAR_FGET(FIELD)\ + _PER_FGET(_CACHE_L2IBAR_ADDR,CACHE,L2IBAR,##FIELD) + + #define _CACHE_L2IBAR_FSET(FIELD,field)\ + _PER_FSET(_CACHE_L2IBAR_ADDR,CACHE,L2IBAR,##FIELD,field) + + #define _CACHE_L2IBAR_FSETS(FIELD,SYM)\ + _PER_FSETS(_CACHE_L2IBAR_ADDR,CACHE,L2IBAR,##FIELD,##SYM) +#endif + +/******************************************************************************\ +* ___________________ +* | | +* | L 2 I W C | +* |_________________| +* +* L2IWC - L2 invalidate word count register +* +* Fields: +* (rw) L2IWC +* +\******************************************************************************/ +#if (L2CACHE_SUPPORT && C64_SUPPORT) + #define _CACHE_L2IWC_ADDR 0x0184401Cu + + #define _CACHE_L2IWC_L2IWC_MASK 0x0000FFFFu + #define _CACHE_L2IWC_L2IWC_SHIFT 0x00000000u + #define CACHE_L2IWC_L2IWC_DEFAULT 0x00000000u + #define CACHE_L2IWC_L2IWC_OF(x) _VALUEOF(x) + + #define CACHE_L2IWC_OF(x) _VALUEOF(x) + + #define CACHE_L2IWC_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CACHE,L2IWC,L2IWC) \ + ) + + #define CACHE_L2IWC_RMK(l2iwc) (Uint32)( \ + _PER_FMK(CACHE,L2IWC,L2IWC,l2iwc) \ + ) + + #define _CACHE_L2IWC_FGET(FIELD)\ + _PER_FGET(_CACHE_L2IWC_ADDR,CACHE,L2IWC,##FIELD) + + #define _CACHE_L2IWC_FSET(FIELD,field)\ + _PER_FSET(_CACHE_L2IWC_ADDR,CACHE,L2IWC,##FIELD,field) + + #define _CACHE_L2IWC_FSETS(FIELD,SYM)\ + _PER_FSETS(_CACHE_L2IWC_ADDR,CACHE,L2IWC,##FIELD,##SYM) +#endif + +/******************************************************************************\ +* _____________________ +* | | +* | L 1 P I B A R | +* |___________________| +* +* L1PIBAR - L1P invalidate base address register +* +* Fields: +* (rw) L1PIBAR +* +\******************************************************************************/ +#if (L2CACHE_SUPPORT) + #define _CACHE_L1PIBAR_ADDR 0x01844020u + + #define _CACHE_L1PIBAR_L1PIBAR_MASK 0xFFFFFFFFu + #define _CACHE_L1PIBAR_L1PIBAR_SHIFT 0x00000000u + #define CACHE_L1PIBAR_L1PIBAR_DEFAULT 0x00000000u + #define CACHE_L1PIBAR_L1PIBAR_OF(x) _VALUEOF(x) + + #define CACHE_L1PIBAR_OF(x) _VALUEOF(x) + + #define CACHE_L1PIBAR_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CACHE,L1PIBAR,L1PIBAR) \ + ) + + #define CACHE_L1PIBAR_RMK(l1pibar) (Uint32)( \ + _PER_FMK(CACHE,L1PIBAR,L1PIBAR,l1pibar) \ + ) + + #define _CACHE_L1PIBAR_FGET(FIELD)\ + _PER_FGET(_CACHE_L1PIBAR_ADDR,CACHE,L1PIBAR,##FIELD) + + #define _CACHE_L1PIBAR_FSET(FIELD,field)\ + _PER_FSET(_CACHE_L1PIBAR_ADDR,CACHE,L1PIBAR,##FIELD,field) + + #define _CACHE_L1PIBAR_FSETS(FIELD,SYM)\ + _PER_FSETS(_CACHE_L1PIBAR_ADDR,CACHE,L1PIBAR,##FIELD,##SYM) +#endif + +/******************************************************************************\ +* _____________________ +* | | +* | L 1 P I W C | +* |___________________| +* +* L1PIWC - L1P invalidate word count register +* +* Fields: +* (rw) L1PFWC +* +\******************************************************************************/ +#if (L2CACHE_SUPPORT) + #define _CACHE_L1PIWC_ADDR 0x01844024u + + #define _CACHE_L1PIWC_L1PIWC_MASK 0x0000FFFFu + #define _CACHE_L1PIWC_L1PIWC_SHIFT 0x00000000u + #define CACHE_L1PIWC_L1PIWC_DEFAULT 0x00000000u + #define CACHE_L1PIWC_L1PIWC_OF(x) _VALUEOF(x) + + #define CACHE_L1PIWC_OF(x) _VALUEOF(x) + + #define CACHE_L1PIWC_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CACHE,L1PIWC,L1PIWC) \ + ) + + #define CACHE_L1PIWC_RMK(l1piwc) (Uint32)( \ + _PER_FMK(CACHE,L1PIWC,L1PIWC,l1piwc) \ + ) + + #define _CACHE_L1PIWC_FGET(FIELD)\ + _PER_FGET(_CACHE_L1PIWC_ADDR,CACHE,L1PIWC,##FIELD) + + #define _CACHE_L1PIWC_FSET(FIELD,field)\ + _PER_FSET(_CACHE_L1PIWC_ADDR,CACHE,L1PIWC,##FIELD,field) + + #define _CACHE_L1PIWC_FSETS(FIELD,SYM)\ + _PER_FSETS(_CACHE_L1PIWC_ADDR,CACHE,L1PIWC,##FIELD,##SYM) +#endif + +/******************************************************************************\ +* _____________________ +* | | +* | L 1 D W I B A R | +* |___________________| +* +* L1DWIBAR - L1D writeback-invalidate base address register +* +* Fields: +* (rw) L1DWIBAR +* +\******************************************************************************/ +#if (L2CACHE_SUPPORT) + #define _CACHE_L1DWIBAR_ADDR 0x01844030u + + #define _CACHE_L1DWIBAR_L1DWIBAR_MASK 0xFFFFFFFFu + #define _CACHE_L1DWIBAR_L1DWIBAR_SHIFT 0x00000000u + #define CACHE_L1DWIBAR_L1DWIBAR_DEFAULT 0x00000000u + #define CACHE_L1DWIBAR_L1DWIBAR_OF(x) _VALUEOF(x) + + #define CACHE_L1DWIBAR_OF(x) _VALUEOF(x) + + #define CACHE_L1DWIBAR_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CACHE,L1DWIBAR,L1DWIBAR) \ + ) + + #define CACHE_L1DWIBAR_RMK(l1dwibar) (Uint32)( \ + _PER_FMK(CACHE,L1DWIBAR,L1DWIBAR,l1dwibar) \ + ) + + #define _CACHE_L1DWIBAR_FGET(FIELD)\ + _PER_FGET(_CACHE_L1DWIBAR_ADDR,CACHE,L1DWIBAR,##FIELD) + + #define _CACHE_L1DWIBAR_FSET(FIELD,field)\ + _PER_FSET(_CACHE_L1DWIBAR_ADDR,CACHE,L1DWIBAR,##FIELD,field) + + #define _CACHE_L1DWIBAR_FSETS(FIELD,SYM)\ + _PER_FSETS(_CACHE_L1DWIBAR_ADDR,CACHE,L1DWIBAR,##FIELD,##SYM) +#endif + +/******************************************************************************\ +* _____________________ +* | | +* | L 1 D W I W C | +* |___________________| +* +* L1DWIWC - L1D writeback-invalidate word count register +* +* Fields: +* (rw) L1DWIWC +* +\******************************************************************************/ +#if (L2CACHE_SUPPORT) + #define _CACHE_L1DWIWC_ADDR 0x01844034u + + #define _CACHE_L1DWIWC_L1DWIWC_MASK 0x0000FFFFu + #define _CACHE_L1DWIWC_L1DWIWC_SHIFT 0x00000000u + #define CACHE_L1DWIWC_L1DWIWC_DEFAULT 0x00000000u + #define CACHE_L1DWIWC_L1DWIWC_OF(x) _VALUEOF(x) + + #define CACHE_L1DWIWC_OF(x) _VALUEOF(x) + + #define CACHE_L1DWIWC_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CACHE,L1DWIWC,L1DWIWC) \ + ) + + #define CACHE_L1DWIWC_RMK(l1dwiwc) (Uint32)( \ + _PER_FMK(CACHE,L1DWIWC,L1DWIWC,l1dwiwc) \ + ) + + #define _CACHE_L1DWIWC_FGET(FIELD)\ + _PER_FGET(_CACHE_L1DWIWC_ADDR,CACHE,L1DWIWC,##FIELD) + + #define _CACHE_L1DWIWC_FSET(FIELD,field)\ + _PER_FSET(_CACHE_L1DWIWC_ADDR,CACHE,L1DWIWC,##FIELD,field) + + #define _CACHE_L1DWIWC_FSETS(FIELD,SYM)\ + _PER_FSETS(_CACHE_L1DWIWC_ADDR,CACHE,L1DWIWC,##FIELD,##SYM) +#endif + +/******************************************************************************\ +* ___________________ +* | | +* | L 1 D I B A R | +* |_________________| +* +* L1DIBAR - L1D invalidate base address register +* +* Fields: +* (rw) L1DIBAR +* +\******************************************************************************/ +#if (L2CACHE_SUPPORT && C64_SUPPORT) + #define _CACHE_L1DIBAR_ADDR 0x01844048u + + #define _CACHE_L1DIBAR_L1DIBAR_MASK 0xFFFFFFFFu + #define _CACHE_L1DIBAR_L1DIBAR_SHIFT 0x00000000u + #define CACHE_L1DIBAR_L1DIBAR_DEFAULT 0x00000000u + #define CACHE_L1DIBAR_L1DIBAR_OF(x) _VALUEOF(x) + + #define CACHE_L1DIBAR_OF(x) _VALUEOF(x) + + #define CACHE_L1DIBAR_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CACHE,L1DIBAR,L1DIBAR) \ + ) + + #define CACHE_L1DIBAR_RMK(l1dibar) (Uint32)( \ + _PER_FMK(CACHE,L1DIBAR,L1DIBAR,l1dibar) \ + ) + + #define _CACHE_L1DIBAR_FGET(FIELD)\ + _PER_FGET(_CACHE_L1DIBAR_ADDR,CACHE,L1DIBAR,##FIELD) + + #define _CACHE_L1DIBAR_FSET(FIELD,field)\ + _PER_FSET(_CACHE_L1DIBAR_ADDR,CACHE,L1DIBAR,##FIELD,field) + + #define _CACHE_L1DIBAR_FSETS(FIELD,SYM)\ + _PER_FSETS(_CACHE_L1DIBAR_ADDR,CACHE,L1DIBAR,##FIELD,##SYM) +#endif + +/******************************************************************************\ +* ___________________ +* | | +* | L 1 D I W C | +* |_________________| +* +* L1DIWC - L1D invalidate word count register +* +* Fields: +* (rw) L1DIWC +* +\******************************************************************************/ +#if (L2CACHE_SUPPORT && C64_SUPPORT) + #define _CACHE_L1DIWC_ADDR 0x0184404Cu + + #define _CACHE_L1DIWC_L1DIWC_MASK 0x0000FFFFu + #define _CACHE_L1DIWC_L1DIWC_SHIFT 0x00000000u + #define CACHE_L1DIWC_L1DIWC_DEFAULT 0x00000000u + #define CACHE_L1DIWC_L1DIWC_OF(x) _VALUEOF(x) + + #define CACHE_L1DIWC_OF(x) _VALUEOF(x) + + #define CACHE_L1DIWC_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CACHE,L1DIWC,L1DIWC) \ + ) + + #define CACHE_L1DIWC_RMK(l1diwc) (Uint32)( \ + _PER_FMK(CACHE,L1DIWC,L1DIWC,l1diwc) \ + ) + + #define _CACHE_L1DIWC_FGET(FIELD)\ + _PER_FGET(_CACHE_L1DIWC_ADDR,CACHE,L1DIWC,##FIELD) + + #define _CACHE_L1DIWC_FSET(FIELD,field)\ + _PER_FSET(_CACHE_L1DIWC_ADDR,CACHE,L1DIWC,##FIELD,field) + + #define _CACHE_L1DIWC_FSETS(FIELD,SYM)\ + _PER_FSETS(_CACHE_L1DIWC_ADDR,CACHE,L1DIWC,##FIELD,##SYM) +#endif + +/******************************************************************************\ +* _______________ +* | | +* | L 2 W B | +* |_____________| +* +* L2WB - L2 writeback all register +* +* Fields: +* (rw) L2WB +* +\******************************************************************************/ +#if (L2CACHE_SUPPORT) + #define _CACHE_L2WB_ADDR 0x01845000u + + #define _CACHE_L2WB_C_MASK 0x00000001u + #define _CACHE_L2WB_C_SHIFT 0x00000000u + #define CACHE_L2WB_C_DEFAULT 0x00000000u + #define CACHE_L2WB_C_OF(x) _VALUEOF(x) + #define CACHE_L2WB_C_NORMAL 0x00000000u + #define CACHE_L2WB_C_FLUSH 0x00000001u + + #define CACHE_L2WB_OF(x) _VALUEOF(x) + + #define CACHE_L2WB_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CACHE,L2WB,C) \ + ) + + #define CACHE_L2WB_RMK(c) (Uint32)( \ + _PER_FMK(CACHE,L2WB,C,c) \ + ) + + #define _CACHE_L2WB_FGET(FIELD)\ + _PER_FGET(_CACHE_L2WB_ADDR,CACHE,L2WB,##FIELD) + + #define _CACHE_L2WB_FSET(FIELD,field)\ + _PER_FSET(_CACHE_L2WB_ADDR,CACHE,L2WB,##FIELD,field) + + #define _CACHE_L2WB_FSETS(FIELD,SYM)\ + _PER_FSETS(_CACHE_L2WB_ADDR,CACHE,L2WB,##FIELD,##SYM) +#endif + +/******************************************************************************\ +* _____________________ +* | | +* | L 2 W B I N V | +* |___________________| +* +* L2WBINV - L2 writeback-invalidate all register +* +* Fields: +* (rw) C +* +\******************************************************************************/ +#if (L2CACHE_SUPPORT) + #define _CACHE_L2WBINV_ADDR 0x01845004u + + #define _CACHE_L2WBINV_C_MASK 0x00000001u + #define _CACHE_L2WBINV_C_SHIFT 0x00000000u + #define CACHE_L2WBINV_C_DEFAULT 0x00000000u + #define CACHE_L2WBINV_C_OF(x) _VALUEOF(x) + #define CACHE_L2WBINV_C_NORMAL 0x00000000u + #define CACHE_L2WBINV_C_CLEAN 0x00000001u + + #define CACHE_L2WBINV_OF(x) _VALUEOF(x) + + #define CACHE_L2WBINV_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CACHE,L2WBINV,C) \ + ) + + #define CACHE_L2WBINV_RMK(c) (Uint32)( \ + _PER_FMK(CACHE,L2WBINV,C,c) \ + ) + + #define _CACHE_L2WBINV_FGET(FIELD)\ + _PER_FGET(_CACHE_L2WBINV_ADDR,CACHE,L2WBINV,##FIELD) + + #define _CACHE_L2WBINV_FSET(FIELD,field)\ + _PER_FSET(_CACHE_L2WBINV_ADDR,CACHE,L2WBINV,##FIELD,field) + + #define _CACHE_L2WBINV_FSETS(FIELD,SYM)\ + _PER_FSETS(_CACHE_L2WBINV_ADDR,CACHE,L2WBINV,##FIELD,##SYM) +#endif + +/*----------------------------------------------------------------------------*/ + +#endif /* CACHE_SUPPORT */ +#endif /* _CSL_CACHEHAL_H_ */ +/******************************************************************************\ +* End of csl_cachehal.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_chip.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_chip.h new file mode 100644 index 0000000..7995566 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_chip.h @@ -0,0 +1,293 @@ +/******************************************************************************\ +* Copyright (C) 1999-2001 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_chip.h +* DATE CREATED.. 08/19/1999 +* LAST MODIFIED. 08/02/2004 - Adding support for C6418 +* 06/17/2003 - Added support for 6712C +* 06/09/2003 - Added support for 6711C +* 12/03/2001 - CHIP_configArgs +* 11/08/2001 - CHIP_getSiliconRevId() +* - CHIP_config() / CHIP_getConfig DM642 +\******************************************************************************/ +#ifndef _CSL_CHIP_H_ +#define _CSL_CHIP_H_ + +#include + +#include +#include + +/******************************************************************************\ +* scope and inline control macros +\******************************************************************************/ +#ifdef __cplusplus +#define CSLAPI extern "C" far +#else +#define CSLAPI extern far +#endif + +#undef USEDEFS +#undef IDECL +#undef IDEF + +#ifdef _CHIP_MOD_ + #define IDECL CSLAPI + #define USEDEFS + #define IDEF +#else + #ifdef _INLINE + #define IDECL static inline + #define USEDEFS + #define IDEF static inline + #else + #define IDECL CSLAPI + #endif +#endif + + +/******************************************************************************\ +* global macro declarations +\******************************************************************************/ +#define CHIP_ENDIAN_BIG 0 +#define CHIP_ENDIAN_LITTLE 1 + +#define CHIP_MAP_0 0 +#define CHIP_MAP_1 1 + +/* Selected devices masks*/ +#if (CHIP_6713 || CHIP_DA610 || CHIP_6711C || CHIP_6712C) +#define CHIP_EKSRC_SYSCLK3 0x00000000u +#define CHIP_EKSRC_ECLKIN 0x00000010u +#endif + +#if (CHIP_6713 || CHIP_DA610) +#define CHIP_TOUT1 0x00000000u +#define CHIP_AXR04_AXR111 0x00000008u + +#define CHIP_TOUT0 0x00000000u +#define CHIP_AXR02_AXR113 0x00000004u + +#define CHIP_MCASP0 0x00000002u +#define CHIP_MCBSP0 0x00000000u + +#define CHIP_I2C1 0x00000001u +#define CHIP_MCBSP1 0x00000000u +/* Full mask value */ +#define _CHIP_DEVCFG_MASK 0x0000001Fu +#endif + +#if CHIP_DM642 +#define CHIP_VP2 0x00000040u +#define CHIP_VP1 0x00000020u +#define CHIP_VP0 0x00000010u +#define CHIP_I2C 0x00000008u +#define CHIP_MCBSP1 0x00000004u +#define CHIP_MCBSP0 0x00000002u +#define CHIP_MCASP0 0x00000001u + +#define _CHIP_PERCFG_MASK 0x0000007Fu +#endif + +#if CHIP_DM641 +#define CHIP_VP1 0x00000020u +#define CHIP_VP0 0x00000010u +#define CHIP_I2C 0x00000008u +#define CHIP_MCBSP1 0x00000004u +#define CHIP_MCBSP0 0x00000002u +#define CHIP_MCASP0 0x00000001u + +#define _CHIP_PERCFG_MASK 0x0000003Fu +#endif + +#if CHIP_DM640 +#define CHIP_VP0 0x00000010u +#define CHIP_I2C 0x00000008u +#define CHIP_MCBSP1 0x00000004u +#define CHIP_MCBSP0 0x00000002u +#define CHIP_MCASP0 0x00000001u + +#define _CHIP_PERCFG_MASK 0x0000001Fu +#endif + +#if CHIP_6412 +#define CHIP_I2C 0x00000008u +#define CHIP_MCBSP1 0x00000004u +#define CHIP_MCBSP0 0x00000002u +#define _CHIP_PERCFG_MASK 0x0000000Eu +#endif + +#if (CHIP_6410 || CHIP_6413 || CHIP_6418) +#define CHIP_AFCMUX 0x00000600u +#define CHIP_MCASP1 0x00000100u +#define CHIP_I2C1 0x00000080u +#define CHIP_I2C0 0x00000008u +#define CHIP_MCBSP1 0x00000004u +#define CHIP_MCBSP0 0x00000002u +#define CHIP_MCASP0 0x00000001u + +#define _CHIP_PERCFG_MASK 0x0000078Fu +#endif + +/******************************************************************************\ +* global typedef declarations +\******************************************************************************/ +#if( CHIP_6711C || CHIP_6712C || CHIP_DA610 || CHIP_6713 ) +typedef struct{ + Uint32 devcfg; +} CHIP_Config; +#elif (CHIP_DM642 || CHIP_DM641 || CHIP_DM640 || CHIP_6412 || CHIP_6410 || CHIP_6413 || CHIP_6418) +typedef struct{ + Uint32 percfg; +} CHIP_Config; +#endif +/******************************************************************************\ +* global variable declarations +\******************************************************************************/ + + +/******************************************************************************\ +* global function declarations +\******************************************************************************/ + + +/******************************************************************************\ +* inline function declarations +\******************************************************************************/ +IDECL Uint32 CHIP_getCpuId(); +IDECL Uint32 CHIP_getRevId(); +IDECL Uint32 CHIP_getSiliconRevId(); +IDECL int CHIP_getEndian(); +IDECL int CHIP_getMapMode(); + +#if (CHIP_DM642 || CHIP_DM641 || CHIP_DM640 || CHIP_6412 || CHIP_6410 || CHIP_6413 || CHIP_6418) +IDECL void CHIP_config(CHIP_Config *config); +IDECL void CHIP_configArgs(Uint32 percfg); +IDECL void CHIP_getConfig(CHIP_Config *config); +#elif ( CHIP_6711C || CHIP_6712C || CHIP_DA610 || CHIP_6713 ) +IDECL void CHIP_config(CHIP_Config *config); +IDECL void CHIP_configArgs(Uint32 devcfg); +IDECL void CHIP_getConfig(CHIP_Config *config); +#endif + +/******************************************************************************\ +* inline function definitions +\******************************************************************************/ +#ifdef USEDEFS +/*----------------------------------------------------------------------------*/ +IDEF Uint32 CHIP_getCpuId() { + return CHIP_FGET(CSR,CPUID); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 CHIP_getRevId() { + return CHIP_FGET(CSR,REVID); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 CHIP_getSiliconRevId() { + return (( 0x000F0000 & REG32(0x01B00200))>>16); +} +/*----------------------------------------------------------------------------*/ +IDEF int CHIP_getEndian() { + return CHIP_FGET(CSR,EN); +} +/*----------------------------------------------------------------------------*/ +IDEF int CHIP_getMapMode() { + int mapmode = 0; + #if (!C11_SUPPORT && !C64_SUPPORT) + mapmode = EMIF_FGET(GBLCTL,MAP); + #endif + return mapmode; +} +/*----------------------------------------------------------------------------*/ +#if (CHIP_6713 || CHIP_DM642 || CHIP_DM641 || CHIP_DM640 || CHIP_DA610 || CHIP_6412 || CHIP_6711C || CHIP_6712C || CHIP_6410 || CHIP_6413 || CHIP_6418) +IDEF void CHIP_config(CHIP_Config *config) { + Uint32 gie = CHIP_FGET(CSR,GIE); + +#if( CHIP_6711C || CHIP_6712C || CHIP_DA610 || CHIP_6713 ) + volatile Uint32 *base = (volatile Uint32 *)(_CHIP_DEVCFG_ADDR); + register int x0; + CHIP_FSET(CSR,GIE,0); + x0 = config->devcfg; + base[_CHIP_DEVCFG_OFFSET] = x0; + CHIP_FSET(CSR,GIE,gie); + +#else + volatile Uint32 *base = (volatile Uint32 *)(_CHIP_PERCFG_ADDR); + register int x0; + CHIP_FSET(CSR,GIE,0); + CHIP_FSETS(PCFGLOCK,LOCK,UNLOCK); + x0 = config->percfg; + base[_CHIP_PERCFG_OFFSET] = x0; + CHIP_FSET(CSR,GIE,gie); + +#endif +} +#endif +/*----------------------------------------------------------------------------*/ +#if (CHIP_6713 || CHIP_DM642 || CHIP_DM641 || CHIP_DM640 || CHIP_DA610 || CHIP_6412 || CHIP_6711C || CHIP_6712C || CHIP_6410 || CHIP_6413 || CHIP_6418) +IDEF void CHIP_getConfig(CHIP_Config *config) { + Uint32 gie = CHIP_FGET(CSR,GIE); + +#if( CHIP_6711C || CHIP_6712C || CHIP_DA610 || CHIP_6713 ) + volatile Uint32 *base = (volatile Uint32 *)(_CHIP_DEVCFG_ADDR); + register int x0; + + CHIP_FSET(CSR,GIE,0); + + x0 = base[_CHIP_DEVCFG_OFFSET]; + config->devcfg=x0; + + CHIP_FSET(CSR,GIE,gie); + +#else + volatile Uint32 *base = (volatile Uint32 *)(_CHIP_PERCFG_ADDR); + register int x0; + + CHIP_FSET(CSR,GIE,0); + + x0 = base[_CHIP_PERCFG_OFFSET]; + config->percfg=x0; + + CHIP_FSET(CSR,GIE,gie); + +#endif +} +#endif +/*----------------------------------------------------------------------------*/ + +#if( CHIP_6711C || CHIP_6712C || CHIP_DA610 || CHIP_6713 ) + IDEF void CHIP_configArgs(Uint32 devcfg) { + Uint32 gie = CHIP_FGET(CSR,GIE); + volatile Uint32 *base = (volatile Uint32 *)(_CHIP_DEVCFG_ADDR); + CHIP_FSET(CSR,GIE,0); + base[_CHIP_DEVCFG_OFFSET]= devcfg; + CHIP_FSET(CSR,GIE,gie); +} +#elif (CHIP_DM642 || CHIP_DM641 || CHIP_DM640 || CHIP_6412 || CHIP_6410 || CHIP_6413 || CHIP_6418) + IDEF void CHIP_configArgs(Uint32 percfg) { + Uint32 gie = CHIP_FGET(CSR,GIE); + volatile Uint32 *base = (volatile Uint32 *)(_CHIP_PERCFG_ADDR); + + CHIP_FSET(CSR,GIE,0); + +#if(CHIP_DM642 || CHIP_6412) + CHIP_FSETS(PCFGLOCK,LOCK,UNLOCK); +#endif + + base[_CHIP_PERCFG_OFFSET]= percfg; + + CHIP_FSET(CSR,GIE,gie); +} +#endif + + +/*----------------------------------------------------------------------------*/ +#endif /* USEDEFS */ + + +#endif /* _CSL_CHIP_H_ */ +/******************************************************************************\ +* End of csl_chip.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_chiphal.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_chiphal.h new file mode 100644 index 0000000..37ace55 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_chiphal.h @@ -0,0 +1,1797 @@ +/******************************************************************************\ +* Copyright (C) 2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_chiphal.h +* DATE CREATED.. 14 Aug 2000 +* LAST MODIFIED. 14 Jan 2004 Adding support for DRI300 versions (6410, 6413) +* 05 Aug 2003 Removing external control cregisters EM,ER,IN,OUT and DIER. +* 26 Jun 2003 Added support for 6411 +* 17 Jun 2003 Added support for 6712C +* 28 May 2003 Added support for 6711C +* 05 Nov 2001 DM642 , 6411 remove 6400 +* 03 Oct 2001 - CHIP_6713 - MCASP_SUPPORT - IIC_SUPPORT +* - PERCFG register +* - redefinition of CHIP_RSET() / CHIP_RGET() +* - new CHIP_CRSET() / CHIP_CRGET() => modification of csl_irq.h +* 04 Apr 2004- Removing external control cregisters EM,ER,IN,OUT and DIER. +* 12 Jan 2005- Removing external control cregisters FMCR,FADCR,FAUCR and GFPGFR +* 06 Apr 2005- Removing the macros ATLEN,ATLMEN and ADIV according to data manual +* tms320c6410(13)-sprs247 dated: Feb26 2004 specifications. +* 26 Jul 2005- Added C++ support. +*------------------------------------------------------------------------------ +* REGISTERS +* +* CSR - control/status register +* IFR - interrupt flag register +* ISR - interrupt set register +* ICR - interrupt clear register +* IER - interrupt enable register +* ISTP - interrupt service table pointer register +* IRP - interrupt return pointer +* NRP - non-maskable interrupt return pointer +* AMR - addressing mode reister +* PERCFG - Device Configuration register (4) +* DEVSTAT - Device Status Register (5) +* JTAGID - JTAG ID register (5) +* +* (1) only supported on 67xx +* (2) only supported on floating point devices +* (3) only supported on 6411/14/15/16 devices +* (4) only supported on 6713/DA610/DM642/6412/6711C/6712C devices +* (5) only supported on DM642/6412/6410/6413 devices +* +\******************************************************************************/ +#ifndef _CSL_CHIPHAL_H_ +#define _CSL_CHIPHAL_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************************\ +* CHIP identification section +\******************************************************************************/ +#ifdef CHIP_BASELINE + #undef CHIP_BASELINE + #define CHIP_BASELINE 1 +#else + #define CHIP_BASELINE 0 +#endif + +#if (CHIP_BASELINE) + #define CHIP_6201 1 +#endif + +#ifdef CHIP_6201 + #undef CHIP_6201 + #define CHIP_6201 1 +#else + #define CHIP_6201 0 +#endif + +#ifdef CHIP_6202 + #undef CHIP_6202 + #define CHIP_6202 1 +#else + #define CHIP_6202 0 +#endif + +#ifdef CHIP_6203 + #undef CHIP_6203 + #define CHIP_6203 1 +#else + #define CHIP_6203 0 +#endif + +#ifdef CHIP_6204 + #undef CHIP_6204 + #define CHIP_6204 1 +#else + #define CHIP_6204 0 +#endif + +#ifdef CHIP_6205 + #undef CHIP_6205 + #define CHIP_6205 1 +#else + #define CHIP_6205 0 +#endif + +#ifdef CHIP_6211 + #undef CHIP_6211 + #define CHIP_6211 1 +#else + #define CHIP_6211 0 +#endif + +#ifdef CHIP_6701 + #undef CHIP_6701 + #define CHIP_6701 1 +#else + #define CHIP_6701 0 +#endif + +#ifdef CHIP_6711 + #undef CHIP_6711 + #define CHIP_6711 1 +#else + #define CHIP_6711 0 +#endif + +#ifdef CHIP_6712 + #undef CHIP_6712 + #define CHIP_6712 1 +#else + #define CHIP_6712 0 +#endif + + +#ifdef CHIP_6713 + #undef CHIP_6713 + #define CHIP_6713 1 +#else + #define CHIP_6713 0 +#endif + +#ifdef CHIP_DA610 + #undef CHIP_DA610 + #define CHIP_DA610 1 +#else + #define CHIP_DA610 0 +#endif + +#ifdef CHIP_DM642 + #undef CHIP_DM642 + #define CHIP_DM642 1 +#else + #define CHIP_DM642 0 +#endif + +#ifdef CHIP_DM641 + #undef CHIP_DM641 + #define CHIP_DM641 1 +#else + #define CHIP_DM641 0 +#endif + +#ifdef CHIP_DM640 + #undef CHIP_DM640 + #define CHIP_DM640 1 +#else + #define CHIP_DM640 0 +#endif + +#ifdef CHIP_6412 + #undef CHIP_6412 + #define CHIP_6412 1 +#else + #define CHIP_6412 0 +#endif + +#ifdef CHIP_6414 + #undef CHIP_6414 + #define CHIP_6414 1 +#else + #define CHIP_6414 0 +#endif + +#ifdef CHIP_6415 + #undef CHIP_6415 + #define CHIP_6415 1 +#else + #define CHIP_6415 0 +#endif + +#ifdef CHIP_6416 + #undef CHIP_6416 + #define CHIP_6416 1 +#else + #define CHIP_6416 0 +#endif + +#ifdef CHIP_6711C + #undef CHIP_6711C + #define CHIP_6711C 1 +#else + #define CHIP_6711C 0 +#endif + +#ifdef CHIP_6712C + #undef CHIP_6712C + #define CHIP_6712C 1 +#else + #define CHIP_6712C 0 +#endif + +#ifdef CHIP_6411 + #undef CHIP_6411 + #define CHIP_6411 1 +#else + #define CHIP_6411 0 +#endif + +/* next two are DRI300 versions */ +#ifdef CHIP_6410 + #undef CHIP_6410 + #define CHIP_6410 1 +#else + #define CHIP_6410 0 +#endif + +#ifdef CHIP_6413 + #undef CHIP_6413 + #define CHIP_6413 1 +#else + #define CHIP_6413 0 +#endif + +#ifdef CHIP_6418 + #undef CHIP_6418 + #define CHIP_6418 1 +#else + #define CHIP_6418 0 +#endif + +/* Adding for DM6446 */ +#ifdef CHIP_DM6446 + #undef CHIP_DM6446 + #define CHIP_DM6446 1 +#else + #define CHIP_DM6446 0 +#endif + + +#define CHIP_OROFALL (\ + CHIP_6201 | \ + CHIP_6202 | \ + CHIP_6203 | \ + CHIP_6204 | \ + CHIP_6205 | \ + CHIP_6211 | \ + CHIP_6701 | \ + CHIP_6711 | \ + CHIP_6712 | \ + CHIP_6713 | \ + CHIP_DA610 | \ + CHIP_DM642 | \ + CHIP_DM641 | \ + CHIP_DM640 | \ + CHIP_6412 | \ + CHIP_6414 | \ + CHIP_6415 | \ + CHIP_6416 | \ + CHIP_6711C | \ + CHIP_6712C | \ + CHIP_6411 |\ + CHIP_6410 |\ + CHIP_6413 |\ + CHIP_6418 \ +) + +#if (CHIP_OROFALL==0) + #error NO CHIP DEFINED (use -dCHIP_XXXX where XXXX is chip number, i.e. 6201) +#endif + +#define CHIP_NONE 0 + +#define CHIP_SUPPORT(c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16,c17,c18,c19,c20,c21,c22,c23,c24) ( \ + ( c0*CHIP_6201) | \ + ( c1*CHIP_6202) | \ + ( c2*CHIP_6203) | \ + ( c3*CHIP_6204) | \ + ( c4*CHIP_6205) | \ + ( c5*CHIP_6211) | \ + ( c6*CHIP_6701) | \ + ( c7*CHIP_6711) | \ + ( c8*CHIP_6712) | \ + ( c9*CHIP_6713) | \ + ( c10*CHIP_DA610)| \ + ( c11*CHIP_DM642)| \ + ( c12*CHIP_DM641)| \ + ( c13*CHIP_DM640)| \ + ( c14*CHIP_6412) | \ + ( c15*CHIP_6414) | \ + ( c16*CHIP_6415) | \ + ( c17*CHIP_6416) | \ + ( c18*CHIP_6711C) | \ + ( c19*CHIP_6712C) | \ + ( c20*CHIP_6411) | \ + ( c21*CHIP_6410) | \ + ( c22*CHIP_6413) | \ + ( c23*CHIP_6418) | \ + ( c24*CHIP_NONE) \ + ) + +/*---------------------------------------------------------------------------------------*/ +/* 6 6 6 6 6 6 6 6 6 6 D D D D 6 6 6 6 6 6 6 6 6 6 N */ +/* 2 2 2 2 2 2 7 7 7 7 A M M M 4 4 4 4 7 7 4 4 4 4 O */ +/* 0 0 0 0 0 1 0 1 1 1 6 6 6 6 1 1 1 1 1 1 1 1 1 1 N */ +/* 1 2 3 4 5 1 1 1 2 3 1 4 4 4 2 4 5 6 1 2 1 0 3 8 E */ +/* 0 2 1 0 C C */ +/*---------------------------------------------------------------------------------------*/ +#define CACHE_SUPPORT CHIP_SUPPORT(1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0) +#define DMA_SUPPORT CHIP_SUPPORT(1,1,1,1,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) +#define EDMA_SUPPORT CHIP_SUPPORT(0,0,0,0,0,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0) +#define EMIF_SUPPORT CHIP_SUPPORT(1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,0,0,0,0,0) +#define EMIFA_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,0,0,1,1,1,1,0) +#define EMIFB_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0) +#define GPIO_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0) +#define HPI_SUPPORT CHIP_SUPPORT(1,0,0,0,0,1,1,1,0,1,1,1,1,0,1,1,1,1,1,0,1,1,1,1,0) +#define I2C_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,0,0,0,0,0,1,1,1,0) +#define IRQ_SUPPORT CHIP_SUPPORT(1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0) +#define MCASP_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,0) +#define MCBSP_SUPPORT CHIP_SUPPORT(1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0) +#define PLL_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,1,1,0,0,0,0,0,0,0,1,1,0,0,0,0,0) +#define TIMER_SUPPORT CHIP_SUPPORT(1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0) +#define XBUS_SUPPORT CHIP_SUPPORT(0,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) +#define PCI_SUPPORT CHIP_SUPPORT(0,0,0,0,1,0,0,0,0,0,0,1,0,0,1,0,1,1,0,0,1,0,0,0,0) +/*---------------------------------------------------------------------------------------*/ +/* 6 6 6 6 6 6 6 6 6 6 D D D D 6 6 6 6 6 6 6 6 6 6 N */ +/* 2 2 2 2 2 2 7 7 7 7 A M M M 4 4 4 4 7 7 4 4 4 4 O */ +/* 0 0 0 0 0 1 0 1 1 1 6 6 6 6 1 1 1 1 1 1 1 1 1 1 N */ +/* 1 2 3 4 5 1 1 1 2 3 1 4 4 4 2 4 5 6 1 2 1 0 3 8 E */ +/* 0 2 1 0 C C */ +/*---------------------------------------------------------------------------------------*/ +#define VP_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0,0) +#define VIC_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0,0) +#define DAT_SUPPORT CHIP_SUPPORT(1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0) +#define PWR_SUPPORT CHIP_SUPPORT(1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0) +#define UTOP_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,0,0,0,0,0,0,0) +#define TCP_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0) +#define VCP_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,1,0) +#define EMAC_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,0,0,0,0,0,0,0,0,0,0) +#define MDIO_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,0,0,0,0,0,0,0,0,0,0) +#define EMU_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0) + +#define L2CACHE_SUPPORT CHIP_SUPPORT(0,0,0,0,0,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0) +#define TC_SUPPORT CHIP_SUPPORT(0,0,0,0,0,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0) +#define FPU_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,1,1,1,1,1,0,0,0,0,0,0,0,1,1,0,0,0,0,0) +#define C01_SUPPORT CHIP_SUPPORT(1,1,1,1,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) +#define C11_SUPPORT CHIP_SUPPORT(0,0,0,0,0,1,0,1,1,1,1,0,0,0,0,0,0,0,1,1,0,0,0,0,0) +#define C64_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,0,0,1,1,1,1,0) +#define ATL_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,0) + +#define CACHE_L2_SUPPORT L2CACHE_SUPPORT +/*----------------------------------------------------------------------*/ + + +/******************************************************************************\ +* module level register/field access macros +\******************************************************************************/ + + /* ----------------- */ + /* FIELD MAKE MACROS */ + /* ----------------- */ + + #define CHIP_FMK(REG,FIELD,x)\ + _PER_FMK(CHIP,##REG,##FIELD,x) + + #define CHIP_FMKS(REG,FIELD,SYM)\ + _PER_FMKS(CHIP,##REG,##FIELD,##SYM) + + + /* -------------------------------- */ + /* RAW REGISTER/FIELD ACCESS MACROS */ + /* -------------------------------- */ + + #define CHIP_CRGET(REG)\ + _PER_CRGET(CHIP,##REG) + + #define CHIP_CRSET(REG,x)\ + _PER_CRSET(CHIP,##REG,x) + + #define CHIP_RGET(REG)\ + _PER_RGET(_CHIP_##REG##_ADDR,CHIP,##REG) + + #define CHIP_RSET(REG,x)\ + _PER_RSET(_CHIP_##REG##_ADDR,CHIP,##REG,x) + + + #define CHIP_FGET(REG,FIELD)\ + _CHIP_##REG##_FGET(##FIELD) + + #define CHIP_FSET(REG,FIELD,x)\ + _CHIP_##REG##_FSET(##FIELD,x) + + #define CHIP_FSETS(REG,FIELD,SYM)\ + _CHIP_##REG##_FSETS(##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | C S R | +* |___________________| +* +* CSR - control/status register +* +* FIELDS (msb -> lsb) +* (r) CPUID +* (r) REVID +* (rw) PWRD +* (rc) SAT +* (r) EN +* (rw) PCC +* (rw) DCC +* (rw) PGIE +* (rw) GIE +* +\******************************************************************************/ + extern far cregister volatile unsigned int CSR; + + #define _CHIP_CSR_CPUID_MASK 0xFF000000u + #define _CHIP_CSR_CPUID_SHIFT 0x00000018u + #define CHIP_CSR_CPUID_DEFAULT 0x00000000u + #define CHIP_CSR_CPUID_OF(x) _VALUEOF(x) + #define CHIP_CSR_CPUID_C62X 0x00000000u + #define CHIP_CSR_CPUID_C67X 0x00000002u + #define CHIP_CSR_CPUID_C64X 0x00000004u + + #define _CHIP_CSR_REVID_MASK 0x00FF0000u + #define _CHIP_CSR_REVID_SHIFT 0x00000010u + #define CHIP_CSR_REVID_DEFAULT 0x00000000u + #define CHIP_CSR_REVID_OF(x) _VALUEOF(x) + #define CHIP_CSR_REVID_620120 0x00000001u + #define CHIP_CSR_REVID_620121 0x00000001u + #define CHIP_CSR_REVID_620130 0x00000002u + #define CHIP_CSR_REVID_670100 0x00000201u + #define CHIP_CSR_REVID_670110 0x00000202u + #define CHIP_CSR_REVID_621110 0x00000002u + #define CHIP_CSR_REVID_640010 0x00000801u + #define CHIP_CSR_REVID_6202 0x00000002u + #define CHIP_CSR_REVID_6202B 0x00000003u + #define CHIP_CSR_REVID_6711 0x00000002u + #define CHIP_CSR_REVID_6711C 0x00000003u + #define CHIP_CSR_REVID_6712 0x00000002u + #define CHIP_CSR_REVID_6712C 0x00000003u + + #define _CHIP_CSR_PWRD_MASK 0x0000FC00u + #define _CHIP_CSR_PWRD_SHIFT 0x0000000Au + #define CHIP_CSR_PWRD_DEFAULT 0x00000000u + #define CHIP_CSR_PWRD_OF(x) _VALUEOF(x) + #define CHIP_CSR_PWRD_NONE 0x00000000u + #define CHIP_CSR_PWRD_PD1A 0x00000009u + #define CHIP_CSR_PWRD_PD1B 0x00000011u + #define CHIP_CSR_PWRD_PD2 0x0000001Au + #define CHIP_CSR_PWRD_PD3 0x0000001Cu + + #define _CHIP_CSR_SAT_MASK 0x00000200u + #define _CHIP_CSR_SAT_SHIFT 0x00000009u + #define CHIP_CSR_SAT_DEFAULT 0x00000000u + #define CHIP_CSR_SAT_OF(x) _VALUEOF(x) + #define CHIP_CSR_SAT_0 0x00000000u + #define CHIP_CSR_SAT_1 0x00000001u + + #define _CHIP_CSR_EN_MASK 0x00000100u + #define _CHIP_CSR_EN_SHIFT 0x00000008u + #define CHIP_CSR_EN_DEFAULT 0x00000000u + #define CHIP_CSR_EN_OF(x) _VALUEOF(x) + #define CHIP_CSR_EN_BIG 0x00000000u + #define CHIP_CSR_EN_LITTLE 0x00000001u + + #define _CHIP_CSR_PCC_MASK 0x000000E0u + #define _CHIP_CSR_PCC_SHIFT 0x00000005u + #define CHIP_CSR_PCC_DEFAULT 0x00000000u + #define CHIP_CSR_PCC_OF(x) _VALUEOF(x) + #define CHIP_CSR_PCC_MAPPED 0x00000000u + #define CHIP_CSR_PCC_ENABLE 0x00000002u + #define CHIP_CSR_PCC_FREEZE 0x00000003u + #define CHIP_CSR_PCC_BYPASS 0x00000004u + + #define _CHIP_CSR_DCC_MASK 0x0000001Cu + #define _CHIP_CSR_DCC_SHIFT 0x00000002u + #define CHIP_CSR_DCC_DEFAULT 0x00000000u + #define CHIP_CSR_DCC_OF(x) _VALUEOF(x) + #define CHIP_CSR_DCC_MAPPED 0x00000000u + #define CHIP_CSR_DCC_ENABLE 0x00000002u + #define CHIP_CSR_DCC_FREEZE 0x00000003u + #define CHIP_CSR_DCC_BYPASS 0x00000004u + + #define _CHIP_CSR_PGIE_MASK 0x00000002u + #define _CHIP_CSR_PGIE_SHIFT 0x00000001u + #define CHIP_CSR_PGIE_DEFAULT 0x00000000u + #define CHIP_CSR_PGIE_OF(x) _VALUEOF(x) + #define CHIP_CSR_PGIE_0 0x00000000u + #define CHIP_CSR_PGIE_1 0x00000001u + + #define _CHIP_CSR_GIE_MASK 0x00000001u + #define _CHIP_CSR_GIE_SHIFT 0x00000000u + #define CHIP_CSR_GIE_DEFAULT 0x00000000u + #define CHIP_CSR_GIE_OF(x) _VALUEOF(x) + #define CHIP_CSR_GIE_0 0x00000000u + #define CHIP_CSR_GIE_1 0x00000001u + + #define CHIP_CSR_OF(x) _VALUEOF(x) + + #define CHIP_CSR_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CHIP,CSR,CPUID) \ + |_PER_FDEFAULT(CHIP,CSR,REVID) \ + |_PER_FDEFAULT(CHIP,CSR,PWRD) \ + |_PER_FDEFAULT(CHIP,CSR,SAT) \ + |_PER_FDEFAULT(CHIP,CSR,EN) \ + |_PER_FDEFAULT(CHIP,CSR,PCC) \ + |_PER_FDEFAULT(CHIP,CSR,DCC) \ + |_PER_FDEFAULT(CHIP,CSR,PGIE) \ + |_PER_FDEFAULT(CHIP,CSR,GIE) \ + ) + + #define CHIP_CSR_RMK(pwrd,pcc,dcc,pgie,gie) (Uint32)( \ + _PER_FMK(CHIP,CSR,PWRD,pwrd) \ + |_PER_FMK(CHIP,CSR,PCC,pcc) \ + |_PER_FMK(CHIP,CSR,DCC,dcc) \ + |_PER_FMK(CHIP,CSR,PGIE,pgie) \ + |_PER_FMK(CHIP,CSR,GIE,gie) \ + ) + + #define _CHIP_CSR_FGET(FIELD)\ + _PER_CFGET(CHIP,CSR,##FIELD) + + #define _CHIP_CSR_FSET(FIELD,field)\ + _PER_CFSET(CHIP,CSR,##FIELD,field) + + #define _CHIP_CSR_FSETS(FIELD,SYM)\ + _PER_CFSETS(CHIP,CSR,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | I F R | +* |___________________| +* +* IFR - interruppt flag register +* +* FIELDS (msb -> lsb) +* (rw) IF +* +\******************************************************************************/ + extern far cregister volatile unsigned int IFR; + + #define _CHIP_IFR_IF_MASK 0x0000FFFFu + #define _CHIP_IFR_IF_SHIFT 0x00000000u + #define CHIP_IFR_IF_DEFAULT 0x00000000u + #define CHIP_IFR_IF_OF(x) _VALUEOF(x) + + #define CHIP_IFR_OF(x) _VALUEOF(x) + + #define CHIP_IFR_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CHIP,IFR,IF)\ + ) + + #define CHIP_IFR_RMK(if) (Uint32)( \ + _PER_FMK(CHIP,IFR,IF,if)\ + ) + + #define _CHIP_IFR_FGET(FIELD)\ + _PER_CFGET(CHIP,IFR,##FIELD) + + #define _CHIP_IFR_FSET(FIELD,field)\ + _PER_CFSET(CHIP,IFR,##FIELD,field) + + #define _CHIP_IFR_FSETS(FIELD,SYM)\ + _PER_CFSETS(CHIP,IFR,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | I S R | +* |___________________| +* +* ISR - interruppt set register +* +* FIELDS (msb -> lsb) +* (w) IS +* +\******************************************************************************/ + extern far cregister volatile unsigned int ISR; + + #define _CHIP_ISR_IS_MASK 0x0000FFFFu + #define _CHIP_ISR_IS_SHIFT 0x00000000u + #define CHIP_ISR_IS_DEFAULT 0x00000000u + #define CHIP_ISR_IS_OF(x) _VALUEOF(x) + + #define CHIP_ISR_OF(x) _VALUEOF(x) + + #define CHIP_ISR_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CHIP,ISR,IS)\ + ) + + #define CHIP_ISR_RMK(is) (Uint32)( \ + _PER_FMK(CHIP,ISR,IS,is)\ + ) + + #define _CHIP_ISR_FGET(FIELD)\ + _PER_CFGET(CHIP,ISR,##FIELD) + + #define _CHIP_ISR_FSET(FIELD,field)\ + _PER_CFSET(CHIP,ISR,##FIELD,field) + + #define _CHIP_ISR_FSETS(FIELD,SYM)\ + _PER_CFSETS(CHIP,ISR,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | I C R | +* |___________________| +* +* ICR - interruppt clear register +* +* FIELDS (msb -> lsb) +* (w) IC +* +\******************************************************************************/ + extern far cregister volatile unsigned int ICR; + + #define _CHIP_ICR_IC_MASK 0x0000FFFFu + #define _CHIP_ICR_IC_SHIFT 0x00000000u + #define CHIP_ICR_IC_DEFAULT 0x00000000u + #define CHIP_ICR_IC_OF(x) _VALUEOF(x) + + #define CHIP_ICR_OF(x) _VALUEOF(x) + + #define CHIP_ICR_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CHIP,ICR,IC)\ + ) + + #define CHIP_ICR_RMK(ic) (Uint32)( \ + _PER_FMK(CHIP,ICR,IC,ic)\ + ) + + #define _CHIP_ICR_FGET(FIELD)\ + _PER_CFGET(CHIP,ICR,##FIELD) + + #define _CHIP_ICR_FSET(FIELD,field)\ + _PER_CFSET(CHIP,ICR,##FIELD,field) + + #define _CHIP_ICR_FSETS(FIELD,SYM)\ + _PER_CFSETS(CHIP,ICR,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | I E R | +* |___________________| +* +* IER - interruppt enable register +* +* FIELDS (msb -> lsb) +* (rw) IE +* +\******************************************************************************/ + extern far cregister volatile unsigned int IER; + + #define _CHIP_IER_IE_MASK 0x0000FFFFu + #define _CHIP_IER_IE_SHIFT 0x00000000u + #define CHIP_IER_IE_DEFAULT 0x00000000u + #define CHIP_IER_IE_OF(x) _VALUEOF(x) + + #define CHIP_IER_OF(x) _VALUEOF(x) + + #define CHIP_IER_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CHIP,IER,IE)\ + ) + + #define CHIP_IER_RMK(ie) (Uint32)( \ + _PER_FMK(CHIP,IER,IE,ie)\ + ) + + #define _CHIP_IER_FGET(FIELD)\ + _PER_CFGET(CHIP,IER,##FIELD) + + #define _CHIP_IER_FSET(FIELD,field)\ + _PER_CFSET(CHIP,IER,##FIELD,field) + + #define _CHIP_IER_FSETS(FIELD,SYM)\ + _PER_CFSETS(CHIP,IER,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | I S T P | +* |___________________| +* +* ISTP - interrupt service table pointer +* +* FIELDS (msb -> lsb) +* (r) HPEINT +* (rw) ISTB +* +\******************************************************************************/ + extern far cregister volatile unsigned int ISTP; + + #define _CHIP_ISTP_ISTB_MASK 0xFFFFFC00u + #define _CHIP_ISTP_ISTB_SHIFT 0x0000000Au + #define CHIP_ISTP_ISTB_DEFAULT 0x00000000u + #define CHIP_ISTP_ISTB_OF(x) _VALUEOF(x) + + #define _CHIP_ISTP_HPEINT_MASK 0x000003E0u + #define _CHIP_ISTP_HPEINT_SHIFT 0x00000005u + #define CHIP_ISTP_HPEINT_DEFAULT 0x00000000u + #define CHIP_ISTP_HPEINT_OF(x) _VALUEOF(x) + + #define CHIP_ISTP_OF(x) _VALUEOF(x) + + #define CHIP_ISTP_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CHIP,ISTP,ISTB)\ + |_PER_FDEFAULT(CHIP,ISTP,HPEINT)\ + ) + + #define CHIP_ISTP_RMK(istb) (Uint32)( \ + _PER_FMK(CHIP,ISTP,ISTB,istb)\ + ) + + #define _CHIP_ISTP_FGET(FIELD)\ + _PER_CFGET(CHIP,ISTP,##FIELD) + + #define _CHIP_ISTP_FSET(FIELD,field)\ + _PER_CFSET(CHIP,ISTP,##FIELD,field) + + #define _CHIP_ISTP_FSETS(FIELD,SYM)\ + _PER_CFSETS(CHIP,ISTP,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | I R P | +* |___________________| +* +* IRP - interrupt return pointer +* +* FIELDS (msb -> lsb) +* (rw) IRP +* +\******************************************************************************/ + extern far cregister volatile unsigned int IRP; + + #define _CHIP_IRP_IRP_MASK 0xFFFFFFFFu + #define _CHIP_IRP_IRP_SHIFT 0x00000000u + #define CHIP_IRP_IRP_DEFAULT 0x00000000u + #define CHIP_IRP_IRP_OF(x) _VALUEOF(x) + + #define CHIP_IRP_OF(x) _VALUEOF(x) + + #define CHIP_IRP_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CHIP,IRP,IRP)\ + ) + + #define CHIP_IRP_RMK(irp) (Uint32)( \ + _PER_FMK(CHIP,IRP,IRP,irp)\ + ) + + #define _CHIP_IRP_FGET(FIELD)\ + _PER_CFGET(CHIP,IRP,##FIELD) + + #define _CHIP_IRP_FSET(FIELD,field)\ + _PER_CFSET(CHIP,IRP,##FIELD,field) + + #define _CHIP_IRP_FSETS(FIELD,SYM)\ + _PER_CFSETS(CHIP,IRP,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | N R P | +* |___________________| +* +* NRP - non-maskable interrupt return pointer +* +* FIELDS (msb -> lsb) +* (rw) NRP +* +\******************************************************************************/ + extern far cregister volatile unsigned int NRP; + + #define _CHIP_NRP_NRP_MASK 0xFFFFFFFFu + #define _CHIP_NRP_NRP_SHIFT 0x00000000u + #define CHIP_NRP_NRP_DEFAULT 0x00000000u + #define CHIP_NRP_NRP_OF(x) _VALUEOF(x) + + #define CHIP_NRP_OF(x) _VALUEOF(x) + + #define CHIP_NRP_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CHIP,NRP,NRP)\ + ) + + #define CHIP_NRP_RMK(nrp) (Uint32)( \ + _PER_FMK(CHIP,NRP,NRP,nrp)\ + ) + + #define _CHIP_NRP_FGET(FIELD)\ + _PER_CFGET(CHIP,NRP,##FIELD) + + #define _CHIP_NRP_FSET(FIELD,field)\ + _PER_CFSET(CHIP,NRP,##FIELD,field) + + #define _CHIP_NRP_FSETS(FIELD,SYM)\ + _PER_CFSETS(CHIP,NRP,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | A M R | +* |___________________| +* +* AMR - addressing mode register +* +* FIELDS (msb -> lsb) +* (rw) BK1 +* (rw) BK0 +* (rw) B7MODE +* (rw) B6MODE +* (rw) B5MODE +* (rw) B4MODE +* (rw) A7MODE +* (rw) A6MODE +* (rw) A5MODE +* (rw) A4MODE +* +\******************************************************************************/ + extern far cregister volatile unsigned int AMR; + + #define _CHIP_AMR_BK1_MASK 0x02E00000u + #define _CHIP_AMR_BK1_SHIFT 0x00000015u + #define CHIP_AMR_BK1_DEFAULT 0x00000000u + #define CHIP_AMR_BK1_OF(x) _VALUEOF(x) + #define CHIP_AMR_BK1_2 0x00000000u + #define CHIP_AMR_BK1_4 0x00000001u + #define CHIP_AMR_BK1_8 0x00000002u + #define CHIP_AMR_BK1_16 0x00000003u + #define CHIP_AMR_BK1_32 0x00000004u + #define CHIP_AMR_BK1_64 0x00000005u + #define CHIP_AMR_BK1_128 0x00000006u + #define CHIP_AMR_BK1_256 0x00000007u + #define CHIP_AMR_BK1_512 0x00000008u + #define CHIP_AMR_BK1_1K 0x00000009u + #define CHIP_AMR_BK1_2K 0x0000000Au + #define CHIP_AMR_BK1_4K 0x0000000Bu + #define CHIP_AMR_BK1_8K 0x0000000Cu + #define CHIP_AMR_BK1_16K 0x0000000Du + #define CHIP_AMR_BK1_32K 0x0000000Eu + #define CHIP_AMR_BK1_64K 0x0000000Fu + #define CHIP_AMR_BK1_128K 0x00000010u + #define CHIP_AMR_BK1_256K 0x00000011u + #define CHIP_AMR_BK1_512K 0x00000012u + #define CHIP_AMR_BK1_1M 0x00000013u + #define CHIP_AMR_BK1_2M 0x00000014u + #define CHIP_AMR_BK1_4M 0x00000015u + #define CHIP_AMR_BK1_8M 0x00000016u + #define CHIP_AMR_BK1_16M 0x00000017u + #define CHIP_AMR_BK1_32M 0x00000018u + #define CHIP_AMR_BK1_64M 0x00000019u + #define CHIP_AMR_BK1_128M 0x0000001Au + #define CHIP_AMR_BK1_256M 0x0000001Bu + #define CHIP_AMR_BK1_512M 0x0000001Cu + #define CHIP_AMR_BK1_1G 0x0000001Du + #define CHIP_AMR_BK1_2G 0x0000001Eu + #define CHIP_AMR_BK1_4G 0x0000001Fu + + #define _CHIP_AMR_BK0_MASK 0x001F0000u + #define _CHIP_AMR_BK0_SHIFT 0x00000010u + #define CHIP_AMR_BK0_DEFAULT 0x00000000u + #define CHIP_AMR_BK0_OF(x) _VALUEOF(x) + #define CHIP_AMR_BK0_2 0x00000000u + #define CHIP_AMR_BK0_4 0x00000001u + #define CHIP_AMR_BK0_8 0x00000002u + #define CHIP_AMR_BK0_16 0x00000003u + #define CHIP_AMR_BK0_32 0x00000004u + #define CHIP_AMR_BK0_64 0x00000005u + #define CHIP_AMR_BK0_128 0x00000006u + #define CHIP_AMR_BK0_256 0x00000007u + #define CHIP_AMR_BK0_512 0x00000008u + #define CHIP_AMR_BK0_1K 0x00000009u + #define CHIP_AMR_BK0_2K 0x0000000Au + #define CHIP_AMR_BK0_4K 0x0000000Bu + #define CHIP_AMR_BK0_8K 0x0000000Cu + #define CHIP_AMR_BK0_16K 0x0000000Du + #define CHIP_AMR_BK0_32K 0x0000000Eu + #define CHIP_AMR_BK0_64K 0x0000000Fu + #define CHIP_AMR_BK0_128K 0x00000010u + #define CHIP_AMR_BK0_256K 0x00000011u + #define CHIP_AMR_BK0_512K 0x00000012u + #define CHIP_AMR_BK0_1M 0x00000013u + #define CHIP_AMR_BK0_2M 0x00000014u + #define CHIP_AMR_BK0_4M 0x00000015u + #define CHIP_AMR_BK0_8M 0x00000016u + #define CHIP_AMR_BK0_16M 0x00000017u + #define CHIP_AMR_BK0_32M 0x00000018u + #define CHIP_AMR_BK0_64M 0x00000019u + #define CHIP_AMR_BK0_128M 0x0000001Au + #define CHIP_AMR_BK0_256M 0x0000001Bu + #define CHIP_AMR_BK0_512M 0x0000001Cu + #define CHIP_AMR_BK0_1G 0x0000001Du + #define CHIP_AMR_BK0_2G 0x0000001Eu + #define CHIP_AMR_BK0_4G 0x0000001Fu + + + #define _CHIP_AMR_B7MODE_MASK 0x0000C000u + #define _CHIP_AMR_B7MODE_SHIFT 0x0000000Eu + #define CHIP_AMR_B7MODE_DEFAULT 0x00000000u + #define CHIP_AMR_B7MODE_OF(x) _VALUEOF(x) + #define CHIP_AMR_B7MODE_LINEAR 0x00000000u + #define CHIP_AMR_B7MODE_CIRCULAR0 0x00000001u + #define CHIP_AMR_B7MODE_CIRCULAR1 0x00000002u + + #define _CHIP_AMR_B6MODE_MASK 0x00003000u + #define _CHIP_AMR_B6MODE_SHIFT 0x0000000Cu + #define CHIP_AMR_B6MODE_DEFAULT 0x00000000u + #define CHIP_AMR_B6MODE_OF(x) _VALUEOF(x) + #define CHIP_AMR_B6MODE_LINEAR 0x00000000u + #define CHIP_AMR_B6MODE_CIRCULAR0 0x00000001u + #define CHIP_AMR_B6MODE_CIRCULAR1 0x00000002u + + #define _CHIP_AMR_B5MODE_MASK 0x00000C00u + #define _CHIP_AMR_B5MODE_SHIFT 0x0000000Au + #define CHIP_AMR_B5MODE_DEFAULT 0x00000000u + #define CHIP_AMR_B5MODE_OF(x) _VALUEOF(x) + #define CHIP_AMR_B5MODE_LINEAR 0x00000000u + #define CHIP_AMR_B5MODE_CIRCULAR0 0x00000001u + #define CHIP_AMR_B5MODE_CIRCULAR1 0x00000002u + + #define _CHIP_AMR_B4MODE_MASK 0x00000300u + #define _CHIP_AMR_B4MODE_SHIFT 0x00000008u + #define CHIP_AMR_B4MODE_DEFAULT 0x00000000u + #define CHIP_AMR_B4MODE_OF(x) _VALUEOF(x) + #define CHIP_AMR_B4MODE_LINEAR 0x00000000u + #define CHIP_AMR_B4MODE_CIRCULAR0 0x00000001u + #define CHIP_AMR_B4MODE_CIRCULAR1 0x00000002u + + #define _CHIP_AMR_A7MODE_MASK 0x000000C0u + #define _CHIP_AMR_A7MODE_SHIFT 0x00000006u + #define CHIP_AMR_A7MODE_DEFAULT 0x00000000u + #define CHIP_AMR_A7MODE_OF(x) _VALUEOF(x) + #define CHIP_AMR_A7MODE_LINEAR 0x00000000u + #define CHIP_AMR_A7MODE_CIRCULAR0 0x00000001u + #define CHIP_AMR_A7MODE_CIRCULAR1 0x00000002u + + #define _CHIP_AMR_A6MODE_MASK 0x00000030u + #define _CHIP_AMR_A6MODE_SHIFT 0x00000004u + #define CHIP_AMR_A6MODE_DEFAULT 0x00000000u + #define CHIP_AMR_A6MODE_OF(x) _VALUEOF(x) + #define CHIP_AMR_A6MODE_LINEAR 0x00000000u + #define CHIP_AMR_A6MODE_CIRCULAR0 0x00000001u + #define CHIP_AMR_A6MODE_CIRCULAR1 0x00000002u + + #define _CHIP_AMR_A5MODE_MASK 0x0000000Cu + #define _CHIP_AMR_A5MODE_SHIFT 0x00000002u + #define CHIP_AMR_A5MODE_DEFAULT 0x00000000u + #define CHIP_AMR_A5MODE_OF(x) _VALUEOF(x) + #define CHIP_AMR_A5MODE_LINEAR 0x00000000u + #define CHIP_AMR_A5MODE_CIRCULAR0 0x00000001u + #define CHIP_AMR_A5MODE_CIRCULAR1 0x00000002u + + #define _CHIP_AMR_A4MODE_MASK 0x00000003u + #define _CHIP_AMR_A4MODE_SHIFT 0x00000000u + #define CHIP_AMR_A4MODE_DEFAULT 0x00000000u + #define CHIP_AMR_A4MODE_OF(x) _VALUEOF(x) + #define CHIP_AMR_A4MODE_LINEAR 0x00000000u + #define CHIP_AMR_A4MODE_CIRCULAR0 0x00000001u + #define CHIP_AMR_A4MODE_CIRCULAR1 0x00000002u + + #define CHIP_AMR_OF(x) _VALUEOF(x) + + #define CHIP_AMR_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CHIP,AMR,BK1)\ + |_PER_FDEFAULT(CHIP,AMR,BK0)\ + |_PER_FDEFAULT(CHIP,AMR,B7MODE)\ + |_PER_FDEFAULT(CHIP,AMR,B6MODE)\ + |_PER_FDEFAULT(CHIP,AMR,B5MODE)\ + |_PER_FDEFAULT(CHIP,AMR,B4MODE)\ + |_PER_FDEFAULT(CHIP,AMR,A7MODE)\ + |_PER_FDEFAULT(CHIP,AMR,A6MODE)\ + |_PER_FDEFAULT(CHIP,AMR,A5MODE)\ + |_PER_FDEFAULT(CHIP,AMR,A4MODE)\ + ) + + #define CHIP_AMR_RMK(bk1,bk0,b7mode,b6mode,b5mode,b4mode,a7,ode,\ + a6mode,a5mode,a4mode) (Uint32)( \ + _PER_FMK(CHIP,AMR,BK1,bk1)\ + |_PER_FMK(CHIP,AMR,BK0,bk0)\ + |_PER_FMK(CHIP,AMR,B7MODE,b7mode)\ + |_PER_FMK(CHIP,AMR,B6MODE,b6mode)\ + |_PER_FMK(CHIP,AMR,B5MODE,b5mode)\ + |_PER_FMK(CHIP,AMR,B4MODE,b4mode)\ + |_PER_FMK(CHIP,AMR,A7MODE,a7mode)\ + |_PER_FMK(CHIP,AMR,A6MODE,a6mode)\ + |_PER_FMK(CHIP,AMR,A5MODE,a5mode)\ + |_PER_FMK(CHIP,AMR,A4MODE,a4mode)\ + ) + + #define _CHIP_AMR_FGET(FIELD)\ + _PER_CFGET(CHIP,AMR,##FIELD) + + #define _CHIP_AMR_FSET(FIELD,field)\ + _PER_CFSET(CHIP,AMR,##FIELD,field) + + #define _CHIP_AMR_FSETS(FIELD,SYM)\ + _PER_CFSETS(CHIP,AMR,##FIELD,##SYM) + + + +/******************************************************************************\ +* _____________________ +* | | +* | D E V C F G | +* |___________________| +* +* PERCFG - Device Configuration register (1) +* +* FIELDS (msb -> lsb) CHIP_6713/CHIP_DA610 +* (rw) EKSRC +* (rw) TOUT1SEL +* (rw) TOUT0SEL +* (rw) MCBSP0DIS +* (rw) MCBSP1DIS +* (rw) GPIO1EN (only for CHIP_DA610) +* +* FIELDS (msb -> lsb) CHIP_DM642 +* (rw) VP2EN +* (rw) VP1EN +* (rw) VP0EN +* (rw) I2C0EN +* (rw) MCBSP1EN +* (rw) MCBSP0EN +* (rw) MCASP0EN +* +* FIELDS (msb -> lsb) CHIP_6412 +* (rw) I2C0EN +* (rw) MCBSP1EN +* (rw) MCBSP0EN +* +* FIELDS (msb -> lsb) CHIP_6711C/CHIP_6712C +* (rw) EKSRC +* +* FIELDS (msb -> lsb) CHIP_6410/CHIP_6413/CHIP_6418 +* (rw) AFCMUX +* (rw) MCASP1EN +* (rw) I2C1EN +* (rw) I2C0EN +* (r) MCBSP1EN +* (r) MCBSP0EN +* (rw) MCASP0EN +* +\******************************************************************************/ + +#if (CHIP_DA610) + + #define _CHIP_DEVCFG_ADDR 0x019C0200u + #define _CHIP_DEVCFG_OFFSET 0 + + #define _CHIP_DEVCFG_GPIO1EN_MASK 0x00010000u + #define _CHIP_DEVCFG_GPIO1EN_SHIFT 0x0000000Fu + #define CHIP_DEVCFG_GPIO1EN_DEFAULT 0x00000000u + #define CHIP_DEVCFG_GPIO1EN_OF(x) _VALUEOF(x) + #define CHIP_DEVCFG_GPIO1EN_0 0x00000000u + #define CHIP_DEVCFG_GPIO1EN_1 0x00000001u + + #define _CHIP_DEVCFG_EKSRC_MASK 0x00000010u + #define _CHIP_DEVCFG_EKSRC_SHIFT 0x00000004u + #define CHIP_DEVCFG_EKSRC_DEFAULT 0x00000000u + #define CHIP_DEVCFG_EKSRC_OF(x) _VALUEOF(x) + #define CHIP_DEVCFG_EKSRC_SYSCLK3 0x00000000u + #define CHIP_DEVCFG_EKSRC_ECLKIN 0x00000001u + + #define _CHIP_DEVCFG_TOUT1SEL_MASK 0x00000008u + #define _CHIP_DEVCFG_TOUT1SEL_SHIFT 0x00000003u + #define CHIP_DEVCFG_TOUT1SEL_DEFAULT 0x00000000u + #define CHIP_DEVCFG_TOUT1SEL_OF(x) _VALUEOF(x) + #define CHIP_DEVCFG_TOUT1SEL_TOUT1PIN 0x00000000u + #define CHIP_DEVCFG_TOUT1SEL_MCASPPIN 0x00000001u + + #define _CHIP_DEVCFG_TOUT0SEL_MASK 0x00000004u + #define _CHIP_DEVCFG_TOUT0SEL_SHIFT 0x00000002u + #define CHIP_DEVCFG_TOUT0SEL_DEFAULT 0x00000000u + #define CHIP_DEVCFG_TOUT0SEL_OF(x) _VALUEOF(x) + #define CHIP_DEVCFG_TOUT0SEL_TOUT0PIN 0x00000000u + #define CHIP_DEVCFG_TOUT0SEL_MCASPPIN 0x00000001u + + #define _CHIP_DEVCFG_MCBSP0DIS_MASK 0x00000002u + #define _CHIP_DEVCFG_MCBSP0DIS_SHIFT 0x00000001u + #define CHIP_DEVCFG_MCBSP0DIS_DEFAULT 0x00000000u + #define CHIP_DEVCFG_MCBSP0DIS_OF(x) _VALUEOF(x) + #define CHIP_DEVCFG_MCBSP0DIS_0 0x00000000u + #define CHIP_DEVCFG_MCBSP0DIS_1 0x00000001u + + #define _CHIP_DEVCFG_MCBSP1DIS_MASK 0x00000001u + #define _CHIP_DEVCFG_MCBSP1DIS_SHIFT 0x00000000u + #define CHIP_DEVCFG_MCBSP1DIS_DEFAULT 0x00000000u + #define CHIP_DEVCFG_MCBSP1DIS_OF(x) _VALUEOF(x) + #define CHIP_DEVCFG_MCBSP1DIS_0 0x00000000u + #define CHIP_DEVCFG_MCBSP1DIS_1 0x00000001u + + + #define CHIP_DEVCFG_OF(x) _VALUEOF(x) + + #define CHIP_DEVCFG_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CHIP,DEVCFG,EKSRC) \ + |_PER_FDEFAULT(CHIP,DEVCFG,TOUT1SEL) \ + |_PER_FDEFAULT(CHIP,DEVCFG,TOUT0SEL) \ + |_PER_FDEFAULT(CHIP,DEVCFG,MCBSP0DIS) \ + |_PER_FDEFAULT(CHIP,DEVCFG,MCBSP1DIS) \ + |_PER_FDEFAULT(CHIP,DEVCFG,GPIO1EN) \ + ) + + #define CHIP_DEVCFG_RMK(eksrc,tout1sel,tout0sel,mcbsp0dis,mcbsp1dis,\ + gpio1en ) (Uint32)( \ + _PER_FMK(CHIP,DEVCFG,EKSRC,eksrc) \ + |_PER_FMK(CHIP,DEVCFG,TOUT1SEL,tout1sel) \ + |_PER_FMK(CHIP,DEVCFG,TOUT0SEL,tout0sel) \ + |_PER_FMK(CHIP,DEVCFG,MCBSP0DIS,mcbsp0dis) \ + |_PER_FMK(CHIP,DEVCFG,MCBSP1DIS,mcbsp1dis) \ + |_PER_FMK(CHIP,DEVCFG,GPIO1EN,gpio1en) \ +) +#elif (CHIP_6713) + #define _CHIP_DEVCFG_ADDR 0x019C0200u + #define _CHIP_DEVCFG_OFFSET 0 + + #define _CHIP_DEVCFG_EKSRC_MASK 0x00000010u + #define _CHIP_DEVCFG_EKSRC_SHIFT 0x00000004u + #define CHIP_DEVCFG_EKSRC_DEFAULT 0x00000000u + #define CHIP_DEVCFG_EKSRC_OF(x) _VALUEOF(x) + #define CHIP_DEVCFG_EKSRC_SYSCLK3 0x00000000u + #define CHIP_DEVCFG_EKSRC_ECLKIN 0x00000001u + + #define _CHIP_DEVCFG_TOUT1SEL_MASK 0x00000008u + #define _CHIP_DEVCFG_TOUT1SEL_SHIFT 0x00000003u + #define CHIP_DEVCFG_TOUT1SEL_DEFAULT 0x00000000u + #define CHIP_DEVCFG_TOUT1SEL_OF(x) _VALUEOF(x) + #define CHIP_DEVCFG_TOUT1SEL_TOUT1PIN 0x00000000u + #define CHIP_DEVCFG_TOUT1SEL_MCASPPIN 0x00000001u + + #define _CHIP_DEVCFG_TOUT0SEL_MASK 0x00000004u + #define _CHIP_DEVCFG_TOUT0SEL_SHIFT 0x00000002u + #define CHIP_DEVCFG_TOUT0SEL_DEFAULT 0x00000000u + #define CHIP_DEVCFG_TOUT0SEL_OF(x) _VALUEOF(x) + #define CHIP_DEVCFG_TOUT0SEL_TOUT0PIN 0x00000000u + #define CHIP_DEVCFG_TOUT0SEL_MCASPPIN 0x00000001u + + #define _CHIP_DEVCFG_MCBSP0DIS_MASK 0x00000002u + #define _CHIP_DEVCFG_MCBSP0DIS_SHIFT 0x00000001u + #define CHIP_DEVCFG_MCBSP0DIS_DEFAULT 0x00000000u + #define CHIP_DEVCFG_MCBSP0DIS_OF(x) _VALUEOF(x) + #define CHIP_DEVCFG_MCBSP0DIS_0 0x00000000u + #define CHIP_DEVCFG_MCBSP0DIS_1 0x00000001u + + #define _CHIP_DEVCFG_MCBSP1DIS_MASK 0x00000001u + #define _CHIP_DEVCFG_MCBSP1DIS_SHIFT 0x00000000u + #define CHIP_DEVCFG_MCBSP1DIS_DEFAULT 0x00000000u + #define CHIP_DEVCFG_MCBSP1DIS_OF(x) _VALUEOF(x) + #define CHIP_DEVCFG_MCBSP1DIS_0 0x00000000u + #define CHIP_DEVCFG_MCBSP1DIS_1 0x00000001u + + + #define CHIP_DEVCFG_OF(x) _VALUEOF(x) + + #define CHIP_DEVCFG_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CHIP,DEVCFG,EKSRC) \ + |_PER_FDEFAULT(CHIP,DEVCFG,TOUT1SEL) \ + |_PER_FDEFAULT(CHIP,DEVCFG,TOUT0SEL) \ + |_PER_FDEFAULT(CHIP,DEVCFG,MCBSP0DIS) \ + |_PER_FDEFAULT(CHIP,DEVCFG,MCBSP1DIS) \ + ) + + #define CHIP_DEVCFG_RMK(eksrc,tout1sel,tout0sel,mcbsp0dis,mcbsp1dis\ + ) (Uint32)( \ + _PER_FMK(CHIP,DEVCFG,EKSRC,eksrc) \ + |_PER_FMK(CHIP,DEVCFG,TOUT1SEL,tout1sel) \ + |_PER_FMK(CHIP,DEVCFG,TOUT0SEL,tout0sel) \ + |_PER_FMK(CHIP,DEVCFG,MCBSP0DIS,mcbsp0dis) \ + |_PER_FMK(CHIP,DEVCFG,MCBSP1DIS,mcbsp1dis) \ +) + +#endif + +#if (CHIP_DM642 || CHIP_DM641 || CHIP_DM640 || CHIP_6412) + + #define _CHIP_PERCFG_ADDR 0x01B3F000u + #define _CHIP_PERCFG_OFFSET 0 + +#if (CHIP_DM642) + #define _CHIP_PERCFG_VP2EN_MASK 0x00000040u + #define _CHIP_PERCFG_VP2EN_SHIFT 0x00000006u + #define CHIP_PERCFG_VP2EN_DEFAULT 0x00000000u + #define CHIP_PERCFG_VP2EN_OF(x) _VALUEOF(x) + #define CHIP_PERCFG_VP2EN_DISABLE 0x00000000u + #define CHIP_PERCFG_VP2EN_ENABLE 0x00000001u +#endif + +#if (CHIP_DM642 | CHIP_DM641) + #define _CHIP_PERCFG_VP1EN_MASK 0x00000020u + #define _CHIP_PERCFG_VP1EN_SHIFT 0x00000005u + #define CHIP_PERCFG_VP1EN_DEFAULT 0x00000000u + #define CHIP_PERCFG_VP1EN_OF(x) _VALUEOF(x) + #define CHIP_PERCFG_VP1EN_DISABLE 0x00000000u + #define CHIP_PERCFG_VP1EN_ENABLE 0x00000001u +#endif + +#if (CHIP_DM642 | CHIP_DM641 | CHIP_DM640) + #define _CHIP_PERCFG_VP0EN_MASK 0x00000010u + #define _CHIP_PERCFG_VP0EN_SHIFT 0x00000004u + #define CHIP_PERCFG_VP0EN_DEFAULT 0x00000000u + #define CHIP_PERCFG_VP0EN_OF(x) _VALUEOF(x) + #define CHIP_PERCFG_VP0EN_DISABLE 0x00000000u + #define CHIP_PERCFG_VP0EN_ENABLE 0x00000001u +#endif + + #define _CHIP_PERCFG_I2C0EN_MASK 0x00000008u + #define _CHIP_PERCFG_I2C0EN_SHIFT 0x00000003u + #define CHIP_PERCFG_I2C0EN_DEFAULT 0x00000000u + #define CHIP_PERCFG_I2C0EN_OF(x) _VALUEOF(x) + #define CHIP_PERCFG_I2C0EN_DISABLE 0x00000000u + #define CHIP_PERCFG_I2C0EN_ENABLE 0x00000001u + + #define _CHIP_PERCFG_MCBSP1EN_MASK 0x00000004u + #define _CHIP_PERCFG_MCBSP1EN_SHIFT 0x00000002u + #define CHIP_PERCFG_MCBSP1EN_DEFAULT 0x00000001u + #define CHIP_PERCFG_MCBSP1EN_OF(x) _VALUEOF(x) + #define CHIP_PERCFG_MCBSP1EN_DISABLE 0x00000000u + #define CHIP_PERCFG_MCBSP1EN_ENABLE 0x00000001u + + #define _CHIP_PERCFG_MCBSP0EN_MASK 0x00000002u + #define _CHIP_PERCFG_MCBSP0EN_SHIFT 0x00000001u + #define CHIP_PERCFG_MCBSP0EN_DEFAULT 0x00000001u + #define CHIP_PERCFG_MCBSP0EN_OF(x) _VALUEOF(x) + #define CHIP_PERCFG_MCBSP0EN_DISABLE 0x00000000u + #define CHIP_PERCFG_MCBSP0EN_ENABLE 0x00000001u + +#if (CHIP_DM642 | CHIP_DM641 | CHIP_DM640) + #define _CHIP_PERCFG_MCASP0EN_MASK 0x00000001u + #define _CHIP_PERCFG_MCASP0EN_SHIFT 0x00000000u + #define CHIP_PERCFG_MCASP0EN_DEFAULT 0x00000000u + #define CHIP_PERCFG_MCASP0EN_OF(x) _VALUEOF(x) + #define CHIP_PERCFG_MCASP0EN_DISABLE 0x00000000u + #define CHIP_PERCFG_MCASP0EN_ENABLE 0x00000001u +#endif + + + #define CHIP_PERCFG_OF(x) _VALUEOF(x) + +#if (CHIP_DM642) + #define CHIP_PERCFG_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CHIP,PERCFG,VP2EN) \ + |_PER_FDEFAULT(CHIP,PERCFG,VP1EN) \ + |_PER_FDEFAULT(CHIP,PERCFG,VP0EN) \ + |_PER_FDEFAULT(CHIP,PERCFG,I2C0EN) \ + |_PER_FDEFAULT(CHIP,PERCFG,MCBSP1EN) \ + |_PER_FDEFAULT(CHIP,PERCFG,MCBSP0EN) \ + |_PER_FDEFAULT(CHIP,PERCFG,MCASP0EN) \ + ) + + + #define CHIP_PERCFG_RMK(vp2en,vp1en,vp0en,i2c0en,mcbsp1en,mcbsp0en,mcasp0en) (Uint32)( \ + _PER_FMK(CHIP,PERCFG,VP2EN,vp2en) \ + |_PER_FMK(CHIP,PERCFG,VP1EN,vp1en) \ + |_PER_FMK(CHIP,PERCFG,VP0EN,vp0en) \ + |_PER_FMK(CHIP,PERCFG,I2C0EN,i2c0en) \ + |_PER_FMK(CHIP,PERCFG,MCBSP1EN,mcbsp1en) \ + |_PER_FMK(CHIP,PERCFG,MCBSP0EN,mcbsp0en) \ + |_PER_FMK(CHIP,PERCFG,MCASP0EN,mcasp0en) \ + ) +#endif + +#if (CHIP_DM641) + #define CHIP_PERCFG_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CHIP,PERCFG,VP1EN) \ + |_PER_FDEFAULT(CHIP,PERCFG,VP0EN) \ + |_PER_FDEFAULT(CHIP,PERCFG,I2C0EN) \ + |_PER_FDEFAULT(CHIP,PERCFG,MCBSP1EN) \ + |_PER_FDEFAULT(CHIP,PERCFG,MCBSP0EN) \ + |_PER_FDEFAULT(CHIP,PERCFG,MCASP0EN) \ + ) + + + #define CHIP_PERCFG_RMK(vp1en,vp0en,i2c0en,mcbsp1en,mcbsp0en,mcasp0en) (Uint32)( \ + _PER_FMK(CHIP,PERCFG,VP1EN,vp1en) \ + |_PER_FMK(CHIP,PERCFG,VP0EN,vp0en) \ + |_PER_FMK(CHIP,PERCFG,I2C0EN,i2c0en) \ + |_PER_FMK(CHIP,PERCFG,MCBSP1EN,mcbsp1en) \ + |_PER_FMK(CHIP,PERCFG,MCBSP0EN,mcbsp0en) \ + |_PER_FMK(CHIP,PERCFG,MCASP0EN,mcasp0en) \ + ) +#endif + +#if (CHIP_DM640) + #define CHIP_PERCFG_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CHIP,PERCFG,VP0EN) \ + |_PER_FDEFAULT(CHIP,PERCFG,I2C0EN) \ + |_PER_FDEFAULT(CHIP,PERCFG,MCBSP1EN) \ + |_PER_FDEFAULT(CHIP,PERCFG,MCBSP0EN) \ + |_PER_FDEFAULT(CHIP,PERCFG,MCASP0EN) \ + ) + + + #define CHIP_PERCFG_RMK(vp0en,i2c0en,mcbsp1en,mcbsp0en,mcasp0en) (Uint32)( \ + _PER_FMK(CHIP,PERCFG,VP0EN,vp0en) \ + |_PER_FMK(CHIP,PERCFG,I2C0EN,i2c0en) \ + |_PER_FMK(CHIP,PERCFG,MCBSP1EN,mcbsp1en) \ + |_PER_FMK(CHIP,PERCFG,MCBSP0EN,mcbsp0en) \ + |_PER_FMK(CHIP,PERCFG,MCASP0EN,mcasp0en) \ + ) +#endif + +#if (CHIP_6412) + #define CHIP_PERCFG_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CHIP,PERCFG,I2C0EN) \ + |_PER_FDEFAULT(CHIP,PERCFG,MCBSP1EN) \ + |_PER_FDEFAULT(CHIP,PERCFG,MCBSP0EN) \ + ) + + + #define CHIP_PERCFG_RMK(i2c0en,mcbsp1en,mcbsp0en) (Uint32)( \ + |_PER_FMK(CHIP,PERCFG,I2C0EN,i2c0en) \ + |_PER_FMK(CHIP,PERCFG,MCBSP1EN,mcbsp1en) \ + |_PER_FMK(CHIP,PERCFG,MCBSP0EN,mcbsp0en) \ + ) +#endif + +#endif /* CHIP_DM642 || CHIP_6412 */ + +#if (CHIP_6410 || CHIP_6413 || CHIP_6418) + + #define _CHIP_PERCFG_ADDR 0x01B3F000u + #define _CHIP_PERCFG_OFFSET 0 + + #define _CHIP_PERCFG_AFCMUX_MASK 0x00000600u + #define _CHIP_PERCFG_AFCMUX_SHIFT 0x00000009u + #define CHIP_PERCFG_AFCMUX_DEFAULT 0x00000000u + #define CHIP_PERCFG_AFCMUX_OF(x) _VALUEOF(x) + #define CHIP_PERCFG_AFCMUX_PIN0 0x00000000u + #define CHIP_PERCFG_AFCMUX_PIN1 0x00000001u + #define CHIP_PERCFG_AFCMUX_PIN2 0x00000002u + #define CHIP_PERCFG_AFCMUX_PIN3 0x00000003u + + #define _CHIP_PERCFG_MCASP1EN_MASK 0x00000100u + #define _CHIP_PERCFG_MCASP1EN_SHIFT 0x00000008u + #define CHIP_PERCFG_MCASP1EN_DEFAULT 0x00000000u + #define CHIP_PERCFG_MCASP1EN_OF(x) _VALUEOF(x) + #define CHIP_PERCFG_MCASP1EN_DISABLE 0x00000000u + #define CHIP_PERCFG_MCASP1EN_ENABLE 0x00000001u + + #define _CHIP_PERCFG_I2C1EN_MASK 0x00000080u + #define _CHIP_PERCFG_I2C1EN_SHIFT 0x00000007u + #define CHIP_PERCFG_I2C1EN_DEFAULT 0x00000000u + #define CHIP_PERCFG_I2C1EN_OF(x) _VALUEOF(x) + #define CHIP_PERCFG_I2C1EN_DISABLE 0x00000000u + #define CHIP_PERCFG_I2C1EN_ENABLE 0x00000001u + + #define _CHIP_PERCFG_I2C0EN_MASK 0x00000008u + #define _CHIP_PERCFG_I2C0EN_SHIFT 0x00000003u + #define CHIP_PERCFG_I2C0EN_DEFAULT 0x00000000u + #define CHIP_PERCFG_I2C0EN_OF(x) _VALUEOF(x) + #define CHIP_PERCFG_I2C0EN_DISABLE 0x00000000u + #define CHIP_PERCFG_I2C0EN_ENABLE 0x00000001u + + #define _CHIP_PERCFG_MCBSP1EN_MASK 0x00000004u + #define _CHIP_PERCFG_MCBSP1EN_SHIFT 0x00000002u + #define CHIP_PERCFG_MCBSP1EN_DEFAULT 0x00000001u + #define CHIP_PERCFG_MCBSP1EN_OF(x) _VALUEOF(x) + #define CHIP_PERCFG_MCBSP1EN_DISABLE 0x00000000u + #define CHIP_PERCFG_MCBSP1EN_ENABLE 0x00000001u + + #define _CHIP_PERCFG_MCBSP0EN_MASK 0x00000002u + #define _CHIP_PERCFG_MCBSP0EN_SHIFT 0x00000001u + #define CHIP_PERCFG_MCBSP0EN_DEFAULT 0x00000001u + #define CHIP_PERCFG_MCBSP0EN_OF(x) _VALUEOF(x) + #define CHIP_PERCFG_MCBSP0EN_DISABLE 0x00000000u + #define CHIP_PERCFG_MCBSP0EN_ENABLE 0x00000001u + + #define _CHIP_PERCFG_MCASP0EN_MASK 0x00000001u + #define _CHIP_PERCFG_MCASP0EN_SHIFT 0x00000000u + #define CHIP_PERCFG_MCASP0EN_DEFAULT 0x00000000u + #define CHIP_PERCFG_MCASP0EN_OF(x) _VALUEOF(x) + #define CHIP_PERCFG_MCASP0EN_DISABLE 0x00000000u + #define CHIP_PERCFG_MCASP0EN_ENABLE 0x00000001u + + #define CHIP_PERCFG_OF(x) _VALUEOF(x) + + #define CHIP_PERCFG_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CHIP,PERCFG,AFCMUX) \ + |_PER_FDEFAULT(CHIP,PERCFG,MCASP1EN) \ + |_PER_FDEFAULT(CHIP,PERCFG,I2C1EN) \ + |_PER_FDEFAULT(CHIP,PERCFG,I2C0EN) \ + |_PER_FDEFAULT(CHIP,PERCFG,MCBSP1EN) \ + |_PER_FDEFAULT(CHIP,PERCFG,MCBSP0EN) \ + |_PER_FDEFAULT(CHIP,PERCFG,MCASP0EN) \ + ) + + + #define CHIP_PERCFG_RMK(afcmux,mcasp1en,i2c1en,i2c0en,mcasp0en) (Uint32)( \ + _PER_FMK(CHIP,PERCFG,AFCMUX,afcmux) \ + |_PER_FMK(CHIP,PERCFG,MCASP1EN,mcasp1en) \ + |_PER_FMK(CHIP,PERCFG,I2C1EN,i2c1en) \ + |_PER_FMK(CHIP,PERCFG,I2C0EN,i2c0en) \ + |_PER_FMK(CHIP,PERCFG,MCASP0EN,mcasp0en) \ + ) + +#endif /* CHIP_6410 || CHIP_6413 || CHIP_6418 */ + +#if (CHIP_6711C || CHIP_6712C) + #define _CHIP_DEVCFG_ADDR 0x019C0200u + #define _CHIP_DEVCFG_OFFSET 0 + + #define _CHIP_DEVCFG_EKSRC_MASK 0x00000010u + #define _CHIP_DEVCFG_EKSRC_SHIFT 0x00000004u + #define CHIP_DEVCFG_EKSRC_DEFAULT 0x00000000u + #define CHIP_DEVCFG_EKSRC_OF(x) _VALUEOF(x) + #define CHIP_DEVCFG_EKSRC_SYSCLK3 0x00000000u + #define CHIP_DEVCFG_EKSRC_ECLKIN 0x00000001u + + #define CHIP_DEVCFG_OF(x) _VALUEOF(x) + + #define CHIP_DEVCFG_DEFAULT (Uint32)( \ + _PER_FDEFAULT(CHIP,DEVCFG,EKSRC) \ + ) + + #define CHIP_PERCFG_RMK(eksrc) (Uint32)( \ + _PER_FMK(CHIP,PERCFG,EKSRC,eksrc) \ +) + +#endif /* CHIP_6711C || CHIP_6712C */ + +#if (CHIP_6711C || CHIP_6712C || CHIP_DA610 || CHIP_6713) + #define _CHIP_DEVCFG_FGET(FIELD)\ + _PER_FGET(_CHIP_DEVCFG_ADDR,CHIP,DEVCFG,##FIELD) + + #define _CHIP_DEVCFG_FSET(FIELD,field)\ + _PER_FSET(_CHIP_DEVCFG_ADDR,CHIP,DEVCFG,##FIELD,field) + + #define _CHIP_DEVCFG_FSETS(FIELD,SYM)\ + _PER_FSETS(_CHIP_DEVCFG_ADDR,CHIP,DEVCFG,##FIELD,##SYM) + +#else + + #define _CHIP_PERCFG_FGET(FIELD)\ + _PER_FGET(_CHIP_PERCFG_ADDR,CHIP,PERCFG,##FIELD) + + #define _CHIP_PERCFG_FSET(FIELD,field)\ + _PER_FSET(_CHIP_PERCFG_ADDR,CHIP,PERCFG,##FIELD,field) + + #define _CHIP_PERCFG_FSETS(FIELD,SYM)\ + _PER_FSETS(_CHIP_PERCFG_ADDR,CHIP,PERCFG,##FIELD,##SYM) +#endif + +/*----------------------------------------------------------------------------*/ +/******************************************************************************\ +* _____________________ +* | | +* | D E V S T A T | +* |___________________| +* +* DEVSTAT - Device Status Register (1) +* +* FIELDS (msb -> lsb) +* DM642 +* (r) MACEN +* (r) HPIWIDTH +* (r) PCIEEAI +* (r) PCIEN +* (r) CLKMODE +* (r) LENDIAN +* (r) BOOTMODE +* (r) AECLKINSEL +* +* DRI300 +* (r) PLLM +* (r) OSCEXTRES +* (r) CLKINSEL +* (r) CLKMODE3 +* (r) HPIWIDTH +* (r) HPIENZ +* (r) CLKMODE2 +* (r) CLKMODE1 +* (r) CLKMODE0 +* (r) LENDIAN +* (r) BOOTMODE +* (r) AECLKINSEL +* +* +\******************************************************************************/ +#if (CHIP_DM642 | CHIP_DM641 | CHIP_DM640 | CHIP_6412) + + #define _CHIP_DEVSTAT_ADDR 0x01B3F004u + #define _CHIP_DEVSTAT_OFFSET 0 + + #define _CHIP_DEVSTAT_MACEN_MASK 0x00000800u + #define _CHIP_DEVSTAT_MACEN_SHIFT 0x0000000Bu + #define CHIP_DEVSTAT_MACEN_DEFAULT 0x00000000u + #define CHIP_DEVSTAT_MACEN_OF(x) _VALUEOF(x) + #define CHIP_DEVSTAT_MACEN_DISABLE 0x00000000u + #define CHIP_DEVSTAT_MACEN_ENABLE 0x00000001u + + #if !(CHIP_DM640) + #define _CHIP_DEVSTAT_HPIWIDTH_MASK 0x00000400u + #define _CHIP_DEVSTAT_HPIWIDTH_SHIFT 0x0000000Au + #define CHIP_DEVSTAT_HPIWIDTH_DEFAULT 0x00000000u + #define CHIP_DEVSTAT_HPIWIDTH_OF(x) _VALUEOF(x) + #define CHIP_DEVSTAT_HPIWIDTH_16 0x00000000u + #define CHIP_DEVSTAT_HPIWIDTH_32 0x00000001u + #endif + + #if !(CHIP_DM641 | CHIP_DM640) + #define _CHIP_DEVSTAT_PCIEEAI_MASK 0x00000200u + #define _CHIP_DEVSTAT_PCIEEAI_SHIFT 0x00000009u + #define CHIP_DEVSTAT_PCIEEAI_DEFAULT 0x00000000u + #define CHIP_DEVSTAT_PCIEEAI_OF(x) _VALUEOF(x) + #define CHIP_DEVSTAT_PCIEEAI_NONE 0x00000000u + #define CHIP_DEVSTAT_PCIEEAI_INIT 0x00000001u + + #define _CHIP_DEVSTAT_PCIEN_MASK 0x00000100u + #define _CHIP_DEVSTAT_PCIEN_SHIFT 0x00000008u + #define CHIP_DEVSTAT_PCIEN_DEFAULT 0x00000000u + #define CHIP_DEVSTAT_PCIEN_OF(x) _VALUEOF(x) + #define CHIP_DEVSTAT_PCIEN_DISABLE 0x00000000u + #define CHIP_DEVSTAT_PCIEN_ENABLE 0x00000001u + #endif + + #define _CHIP_DEVSTAT_CLKMODE_MASK 0x00000060u + #define _CHIP_DEVSTAT_CLKMODE_SHIFT 0x00000005u + #define CHIP_DEVSTAT_CLKMODE_DEFAULT 0x00000001u + #define CHIP_DEVSTAT_CLKMODE_OF(x) _VALUEOF(x) + #define CHIP_DEVSTAT_CLKMODE_X1 0x00000000u + #define CHIP_DEVSTAT_CLKMODE_X6 0x00000001u + #define CHIP_DEVSTAT_CLKMODE_X12 0x00000002u + #define CHIP_DEVSTAT_CLKMODE_X20 0x00000003u + + #define _CHIP_DEVSTAT_LENDIAN_MASK 0x00000010u + #define _CHIP_DEVSTAT_LENDIAN_SHIFT 0x00000004u + #define CHIP_DEVSTAT_LENDIAN_DEFAULT 0x00000001u + #define CHIP_DEVSTAT_LENDIAN_OF(x) _VALUEOF(x) + #define CHIP_DEVSTAT_LENDIAN_BIG 0x00000000u + #define CHIP_DEVSTAT_LENDIAN_LITTLE 0x00000001u + + #define _CHIP_DEVSTAT_BOOTMODE_MASK 0x0000000Cu + #define _CHIP_DEVSTAT_BOOTMODE_SHIFT 0x00000002u + #define CHIP_DEVSTAT_BOOTMODE_DEFAULT 0x00000000u + #define CHIP_DEVSTAT_BOOTMODE_OF(x) _VALUEOF(x) + #define CHIP_DEVSTAT_BOOTMODE_NONE 0x00000000u + #define CHIP_DEVSTAT_BOOTMODE_HPIPCI 0x00000001u + #define CHIP_DEVSTAT_BOOTMODE_EMIFA 0x00000003u + + #define _CHIP_DEVSTAT_AECLKINSEL_MASK 0x00000003u + #define _CHIP_DEVSTAT_AECLKINSEL_SHIFT 0x00000000u + #define CHIP_DEVSTAT_AECLKINSEL_DEFAULT 0x00000000u + #define CHIP_DEVSTAT_AECLKINSEL_OF(x) _VALUEOF(x) + #define CHIP_DEVSTAT_AECLKINSEL_ECLKIN 0x00000000u + #define CHIP_DEVSTAT_AECLKINSEL_CLKOUT4 0x00000001u + #define CHIP_DEVSTAT_AECLKINSEL_CLKOUT6 0x00000002u + #define CHIP_DEVSTAT_OF(x) _VALUEOF(x) + + #define CHIP_DEVSTAT_OF(x) _VALUEOF(x) + + /* Read only Register */ + + #define _CHIP_DEVSTAT_FGET(FIELD)\ + _PER_FGET(_CHIP_DEVSTAT_ADDR,CHIP,DEVSTAT,##FIELD) + + +#endif /* CHIP_DM642 | CHIP_6412 */ + +#if (CHIP_6410 || CHIP_6413 || CHIP_6418) + + #define _CHIP_DEVSTAT_ADDR 0x01B3F004u + #define _CHIP_DEVSTAT_OFFSET 0 + + #define _CHIP_DEVSTAT_PLLM_MASK 0x00F10000u + #define _CHIP_DEVSTAT_PLLM_SHIFT 0x00000013u + #define CHIP_DEVSTAT_PLLM_DEFAULT 0x00000000u + #define CHIP_DEVSTAT_PLLM_OF(x) _VALUEOF(x) + #define CHIP_DEVSTAT_PLLM_BYPASS 0x00000000u + #define CHIP_DEVSTAT_PLLM_5 0x00000001u + #define CHIP_DEVSTAT_PLLM_6 0x00000002u + #define CHIP_DEVSTAT_PLLM_7 0x00000003u + #define CHIP_DEVSTAT_PLLM_8 0x00000004u + #define CHIP_DEVSTAT_PLLM_9 0x00000005u + #define CHIP_DEVSTAT_PLLM_10 0x00000006u + #define CHIP_DEVSTAT_PLLM_11 0x00000007u + #define CHIP_DEVSTAT_PLLM_12 0x00000008u + #define CHIP_DEVSTAT_PLLM_16 0x00000009u + #define CHIP_DEVSTAT_PLLM_18 0x0000000Au + #define CHIP_DEVSTAT_PLLM_19 0x0000000Bu + #define CHIP_DEVSTAT_PLLM_20 0x0000000Cu + #define CHIP_DEVSTAT_PLLM_21 0x0000000Du + #define CHIP_DEVSTAT_PLLM_22 0x0000000Eu + #define CHIP_DEVSTAT_PLLM_24 0x0000000Fu + + #define _CHIP_DEVSTAT_OSCEXTRES_MASK 0x00020000u + #define _CHIP_DEVSTAT_OSCEXTRES_SHIFT 0x00000011u + #define CHIP_DEVSTAT_OSCEXTRES_DEFAUL 0x00000001u + #define CHIP_DEVSTAT_OSCEXTRES_OF(x) _VALUEOF(x) + #define CHIP_DEVSTAT_OSCEXTRES_DISABL 0x00000000u + #define CHIP_DEVSTAT_OSCEXTRES_ENABLE 0x00000001u + + #define _CHIP_DEVSTAT_CLKINSEL_MASK 0x00010000u + #define _CHIP_DEVSTAT_CLKINSEL_SHIFT 0x00000010u + #define CHIP_DEVSTAT_CLKINSEL_DEFAULT 0x00000000u + #define CHIP_DEVSTAT_CLKINSEL_OF(x) _VALUEOF(x) + #define CHIP_DEVSTAT_CLKINSEL_DISABLE 0x00000000u + #define CHIP_DEVSTAT_CLKINSEL_ENABLE 0x00000001u + + #define _CHIP_DEVSTAT_HPIWIDTH_MASK 0x00000400u + #define _CHIP_DEVSTAT_HPIWIDTH_SHIFT 0x0000000Au + #define CHIP_DEVSTAT_HPIWIDTH_DEFAUL 0x00000000u + #define CHIP_DEVSTAT_HPIWIDTH_OF(x) _VALUEOF(x) + #define CHIP_DEVSTAT_HPIWIDTH_16 0x00000000u + #define CHIP_DEVSTAT_HPIWIDTH_32 0x00000001u + + #define _CHIP_DEVSTAT_HPIENZ_MASK 0x00000100u + #define _CHIP_DEVSTAT_HPIENZ_SHIFT 0x00000008u + #define CHIP_DEVSTAT_HPIENZ_DEFAULT 0x00000000u + #define CHIP_DEVSTAT_HPIENZ_OF(x) _VALUEOF(x) + #define CHIP_DEVSTAT_HPIENZ_ENABLE 0x00000000u + #define CHIP_DEVSTAT_HPIENZ_DISABLE 0x00000001u + + #define _CHIP_DEVSTAT_CLKMODE_MASK 0x000010E0u + #define _CHIP_DEVSTAT_CLKMODE_SHIFT 0x00000005u + #define CHIP_DEVSTAT_CLKMODE_DEFAULT 0x00000001u + #define CHIP_DEVSTAT_CLKMODE_OF(x) _VALUEOF(x) + #define CHIP_DEVSTAT_CLKMODE_0 0x00000000u + #define CHIP_DEVSTAT_CLKMODE_1 0x00000001u + #define CHIP_DEVSTAT_CLKMODE_2 0x00000002u + #define CHIP_DEVSTAT_CLKMODE_3 0x00000003u + #define CHIP_DEVSTAT_CLKMODE_4 0x00000004u + #define CHIP_DEVSTAT_CLKMODE_5 0x00000005u + #define CHIP_DEVSTAT_CLKMODE_6 0x00000006u + #define CHIP_DEVSTAT_CLKMODE_7 0x00000007u + #define CHIP_DEVSTAT_CLKMODE_8 0x00000080u + #define CHIP_DEVSTAT_CLKMODE_9 0x00000081u + #define CHIP_DEVSTAT_CLKMODE_10 0x00000082u + #define CHIP_DEVSTAT_CLKMODE_11 0x00000083u + #define CHIP_DEVSTAT_CLKMODE_12 0x00000084u + #define CHIP_DEVSTAT_CLKMODE_13 0x00000085u + #define CHIP_DEVSTAT_CLKMODE_14 0x00000086u + #define CHIP_DEVSTAT_CLKMODE_15 0x00000087u + + #define _CHIP_DEVSTAT_LENDIAN_MASK 0x00000010u + #define _CHIP_DEVSTAT_LENDIAN_SHIFT 0x00000004u + #define CHIP_DEVSTAT_LENDIAN_DEFAULT 0x00000001u + #define CHIP_DEVSTAT_LENDIAN_OF(x) _VALUEOF(x) + #define CHIP_DEVSTAT_LENDIAN_BIG 0x00000000u + #define CHIP_DEVSTAT_LENDIAN_LITTLE 0x00000001u + + #define _CHIP_DEVSTAT_BOOTMODE_MASK 0x0000000Cu + #define _CHIP_DEVSTAT_BOOTMODE_SHIFT 0x00000002u + #define CHIP_DEVSTAT_BOOTMODE_DEFAULT 0x00000000u + #define CHIP_DEVSTAT_BOOTMODE_OF(x) _VALUEOF(x) + #define CHIP_DEVSTAT_BOOTMODE_NONE 0x00000000u + #define CHIP_DEVSTAT_BOOTMODE_HPI 0x00000001u + #define CHIP_DEVSTAT_BOOTMODE_EMIFA 0x00000003u + + #define _CHIP_DEVSTAT_AECLKINSEL_MASK 0x00000003u + #define _CHIP_DEVSTAT_AECLKINSEL_SHIFT 0x00000000u + #define CHIP_DEVSTAT_AECLKINSEL_DEFAULT 0x00000000u + #define CHIP_DEVSTAT_AECLKINSEL_OF(x) _VALUEOF(x) + #define CHIP_DEVSTAT_AECLKINSEL_ECLKIN 0x00000000u + #define CHIP_DEVSTAT_AECLKINSEL_CLKOUT4 0x00000001u + #define CHIP_DEVSTAT_AECLKINSEL_CLKOUT6 0x00000002u + + #define CHIP_DEVSTAT_OF(x) _VALUEOF(x) + + /* Read only Register */ + + #define _CHIP_DEVSTAT_FGET(FIELD)\ + _PER_FGET(_CHIP_DEVSTAT_ADDR,CHIP,DEVSTAT,##FIELD) + + +#endif /* CHIP_6410 || CHIP_6413 || CHIP_6418 */ + +/******************************************************************************\ +* _____________________ +* | | +* | J T A G I D | +* |___________________| +* +* JTAGID - JTAG ID register (1) +* +* FIELDS (msb -> lsb) +* (r) VARIANT +* (r) PART +* (r) MANNUFACTURE +* (r) LSB +* +* (1) Only for DM642 +* +\******************************************************************************/ + + +#if (CHIP_DM642 || CHIP_DM641 || CHIP_DM640 || CHIP_6412 ) + + #define _CHIP_JTAGID_ADDR 0x01B3F008u + #define _CHIP_JTAGID_OFFSET 0 + + #define _CHIP_JTAGID_VARIANT_MASK 0xF0000000u + #define _CHIP_JTAGID_VARIANT_SHIFT 0x0000001Cu + #define CHIP_JTAGID_VARIANT_DEFAULT 0x00000000u + #define CHIP_JTAGID_VARIANT_OF(x) _VALUEOF(x) + + #define _CHIP_JTAGID_PART_MASK 0x0FFFF000u + #define _CHIP_JTAGID_PART_SHIFT 0x0000000Cu + #define CHIP_JTAGID_PART_DEFAULT 0x00000079u + #define CHIP_JTAGID_PART_OF(x) _VALUEOF(x) + + #define _CHIP_JTAGID_MANUFACTURE_MASK 0x00000FFEu + #define _CHIP_JTAGID_MANUFACTURE_SHIFT 0x00000001u + #define CHIP_JTAGID_MANUFACTURE_DEFAULT 0x00000017u + #define CHIP_JTAGID_MANUFACTURE_OF(x) _VALUEOF(x) + + #define _CHIP_JTAGID_LSB_MASK 0x00000001u + #define _CHIP_JTAGID_LSB_SHIFT 0x00000000u + #define CHIP_JTAGID_LSB_DEFAULT 0x00000001u + #define CHIP_JTAGID_LSB_OF(x) _VALUEOF(x) + + #define CHIP_JTAGID_OF(x) _VALUEOF(x) + + #define _CHIP_JTAGID_FGET(FIELD)\ + _PER_FGET(_CHIP_JTAGID_ADDR,CHIP,JTAGID,##FIELD) + +#endif /* CHIP_DM642 || CHIP_6412 */ + +/******************************************************************************\ +* _____________________ +* | | +* | P C F G L O C K | +* |___________________| +* +* PCFGLOCK - Peripheral Configuration Lock register (1) +* +* FIELDS (msb -> lsb) +* (r) LOCKSTAT +* (w) LOCK +* +* (1) Only for DM642 +* +\******************************************************************************/ + +#if (CHIP_DM642 || CHIP_DM641 || CHIP_DM640 || CHIP_6412 || CHIP_6410 || CHIP_6413 || CHIP_6418) + + #define _CHIP_PCFGLOCK_ADDR 0x01B3F018u + #define _CHIP_PCFGLOCK_OFFSET 0 + + #define _CHIP_PCFGLOCK_LOCKSTAT_MASK 0x00000001u + #define _CHIP_PCFGLOCK_LOCKSTAT_SHIFT 0x00000000u + #define CHIP_PCFGLOCK_LOCKSTAT_DEFAULT 0x00000001u + #define CHIP_PCFGLOCK_LOCKSTAT_OF(x) _VALUEOF(x) + #define CHIP_PCFGLOCK_LOCKSTAT_UNLOCK 0x00000000u + #define CHIP_PCFGLOCK_LOCKSTAT_LOCK 0x00000001u + + #define _CHIP_PCFGLOCK_LOCK_MASK 0xFFFFFFFFu + #define _CHIP_PCFGLOCK_LOCK_SHIFT 0x00000000u + #define CHIP_PCFGLOCK_LOCK_DEFAULT 0x00000000u + #define CHIP_PCFGLOCK_LOCK_OF(x) _VALUEOF(x) + #define CHIP_PCFGLOCK_LOCK_UNLOCK 0x10C0010Cu + #define CHIP_PCFGLOCK_LOCK_DISABLE 0x10C0010Cu + + #define CHIP_PCFGLOCK_OF(x) _VALUEOF(x) + + #define _CHIP_PCFGLOCK_FGET(FIELD)\ + _PER_FGET(_CHIP_PCFGLOCK_ADDR,CHIP,PCFGLOCK,##FIELD) + + #define _CHIP_PCFGLOCK_FSET(FIELD,field)\ + _PER_FSET(_CHIP_PCFGLOCK_ADDR,CHIP,PCFGLOCK,##FIELD,field) + + #define _CHIP_PCFGLOCK_FSETS(FIELD,SYM)\ + _PER_FSETS(_CHIP_PCFGLOCK_ADDR,CHIP,PCFGLOCK,##FIELD,##SYM) + + +#endif /* CHIP_DM642 || CHIP_DM641 || CHIP_DM640 || CHIP_6412 || CHIP_6410 || CHIP_6413 || CHIP_6418*/ + +#ifdef __cplusplus +} +#endif + +/*----------------------------------------------------------------------------*/ +#endif /* _CSL_CHIPHAL_H_ */ +/******************************************************************************\ +* End of csl_chiphal.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_dat.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_dat.h new file mode 100644 index 0000000..eea2ff6 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_dat.h @@ -0,0 +1,161 @@ +/******************************************************************************\ +* Copyright (C) 1999-2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_dat.h +* DATE CREATED.. 11/11/1999 +* LAST MODIFIED. 10/03/2000 +\******************************************************************************/ +#ifndef _CSL_DAT_H_ +#define _CSL_DAT_H_ + +#if 0 +#include +#include +#include +#include +#endif + +#include + +#if (DAT_SUPPORT) +/******************************************************************************\ +* scope and inline control macros +\******************************************************************************/ +#ifdef __cplusplus +#define CSLAPI extern "C" far +#else +#define CSLAPI extern far +#endif + +#undef USEDEFS +#undef IDECL +#undef IDEF + +#ifdef _DAT_MOD_ + #define IDECL CSLAPI + #define USEDEFS + #define IDEF +#else + #ifdef _INLINE + #define IDECL static inline + #define USEDEFS + #define IDEF static inline + #else + #define IDECL CSLAPI + #endif +#endif + + +/******************************************************************************\ +* global macro declarations +\******************************************************************************/ +#if (DMA_SUPPORT) + #define DAT_CHAANY DMA_CHAANY + #define DAT_CHA0 DMA_CHA0 + #define DAT_CHA1 DMA_CHA1 + #define DAT_CHA2 DMA_CHA2 + #define DAT_CHA3 DMA_CHA3 + #define DAT_PRI_LOW DMA_PRICTL_PRI_CPU + #define DAT_PRI_HIGH DMA_PRICTL_PRI_DMA + + #define DAT_1D2D 0x000000D0 + #define DAT_2D1D 0x00000070 + #define DAT_2D2D 0x000000F0 + +#elif (EDMA_SUPPORT) + #define DAT_CHAANY 0 + #define DAT_CHA0 0 + #define DAT_CHA1 0 + #define DAT_CHA2 0 + #define DAT_CHA3 0 + #define DAT_PRI_LOW EDMA_OPT_PRI_LOW + #define DAT_PRI_HIGH EDMA_OPT_PRI_HIGH + + #define DAT_1D2D 0x01A00001 + #define DAT_2D1D 0x05200001 + #define DAT_2D2D 0x05A00001 +#endif + +/* open flags */ +#define DAT_OPEN_2D 1 + +/* special magic transfer IDs */ +#define DAT_XFRID_WAITALL 0xFFFFFFFF +#define DAT_XFRID_WAITNONE 0xFFFF0010 + + +/******************************************************************************\ +* global typedef declarations +\******************************************************************************/ +#if (DMA_SUPPORT) + typedef struct { + Uint32 useMask; + Uint32 baseAddr; + Uint32 gblcntAddr; + Uint32 gblidxAddr; + Uint32 initPrictl; + } _DAT_StateStruct; +#endif + +#if (EDMA_SUPPORT) + typedef struct { + Uint32 useMask; + Uint32 baseAddr; + Uint32 initOpt; + } _DAT_StateStruct; +#endif + + +/******************************************************************************\ +* global variable declarations +\******************************************************************************/ +extern far _DAT_StateStruct _DAT_stateStruct; + + +/******************************************************************************\ +* global function declarations +\******************************************************************************/ +CSLAPI int DAT_open(int chaNum, int priority, Uint32 flags); +CSLAPI void DAT_close(); + +CSLAPI Uint32 DAT_copy(void *src , void *dst , Uint16 byteCnt); +CSLAPI Uint32 DAT_fill(void *dst , Uint16 byteCnt, Uint32 *value); +CSLAPI void DAT_wait(Uint32 id); +CSLAPI int DAT_busy(Uint32 id); + +CSLAPI Uint32 DAT_copy2d(Uint32 type, void *src, void *dst, Uint16 lineLen, Uint16 lineCnt, Uint16 linePitch); + + +/******************************************************************************\ +* inline function declarations +\******************************************************************************/ +IDECL void DAT_setPriority(int priority); + + +/******************************************************************************\ +* inline function definitions +\******************************************************************************/ +#ifdef USEDEFS +/*----------------------------------------------------------------------------*/ +IDEF void DAT_setPriority(int priority) { + #if (DMA_SUPPORT) + DMA_FSETA(&(_DAT_stateStruct.initPrictl), PRICTL, PRI, priority); + #endif + +#if 0 + #if (EDMA_SUPPORT) + EDMA_FSETA(&(_DAT_stateStruct.initOpt), OPT, PRI, priority); + #endif +#endif +} +/*----------------------------------------------------------------------------*/ +#endif /* USEDEFS */ + + +#endif /* DAT_SUPPORT */ +#endif /* _CSL_DAT_H_ */ +/******************************************************************************\ +* End of csl_dat.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_dma.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_dma.h new file mode 100644 index 0000000..51d1b2b --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_dma.h @@ -0,0 +1,392 @@ +/******************************************************************************\ +* Copyright (C) 1999-2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_dma.h +* DATE CREATED.. 06/11/1999 +* LAST MODIFIED. 09/20/2000 +* +\******************************************************************************/ +#ifndef _CSL_DMA_H_ +#define _CSL_DMA_H_ + +#include +#include +#include + + +#if (DMA_SUPPORT) +/******************************************************************************\ +* scope and inline control macros +\******************************************************************************/ +#ifdef __cplusplus +#define CSLAPI extern "C" far +#else +#define CSLAPI extern far +#endif + +#undef USEDEFS +#undef IDECL +#undef IDEF + +#ifdef _DMA_MOD_ + #define IDECL CSLAPI + #define USEDEFS + #define IDEF +#else + #ifdef _INLINE + #define IDECL static inline + #define USEDEFS + #define IDEF static inline + #else + #define IDECL CSLAPI + #endif +#endif + + +/******************************************************************************\ +* global macro declarations +\******************************************************************************/ +#define DMA_CHA_CNT 4 + +/* DMA_open() flags */ +#define DMA_OPEN_RESET 0x00000001u + +/* channel identifiers for DMA_open() */ +#define DMA_CHAANY (-1) +#define DMA_CHA0 (0) +#define DMA_CHA1 (1) +#define DMA_CHA2 (2) +#define DMA_CHA3 (3) + +/* DMA status state */ +#define DMA_STATUS_STOPPED DMA_PRICTL_STATUS_STOPPED +#define DMA_STATUS_RUNNING DMA_PRICTL_STATUS_RUNNING +#define DMA_STATUS_PAUSED DMA_PRICTL_STATUS_PAUSED +#define DMA_STATUS_AUTORUNNING DMA_PRICTL_STATUS_AUTORUNNING + +/* predefined global register IDs */ +#define DMA_GBL_ADDRRLDB 0x00000001u +#define DMA_GBL_ADDRRLDC 0x00000002u +#define DMA_GBL_ADDRRLDD 0x00000003u +#define DMA_GBL_INDEXA 0x00000004u +#define DMA_GBL_INDEXB 0x00000005u +#define DMA_GBL_CNTRLDA 0x00000008u +#define DMA_GBL_CNTRLDB 0x00000009u +#define DMA_GBL_SPLITA 0x0000000Du +#define DMA_GBL_SPLITB 0x0000000Eu +#define DMA_GBL_SPLITC 0x0000000Fu + +#define DMA_GBLADDRA 0x00000001u +#define DMA_GBLADDRB 0x00000002u +#define DMA_GBLADDRC 0x00000004u +#define DMA_GBLADDRD 0x00000008u +#define DMA_GBLIDXA 0x00000010u +#define DMA_GBLIDXB 0x00000020u +#define DMA_GBLCNTA 0x00000040u +#define DMA_GBLCNTB 0x00000080u + +#define _DMA_GBLREG_CNT 16 +#define _DMA_GBLREG_MASK (_DMA_GBLREG_CNT-1) + +/****************************************************************/ +/* The two following macros are used to get/clear the condition */ +/* flags of the DMA SECCTL register in a safe manner. */ +/* */ +/* The X argument MUST be one of the following: */ +/* DMA_SECCTL_SXCOND */ +/* DMA_SECCTL_FRAMECOND */ +/* DMA_SECCTL_LASTCOND */ +/* DMA_SECCTL_BLOCKCOND */ +/* DMA_SECCTL_RDROPCOND */ +/* DMA_SECCTL_WDROPCOND */ +/****************************************************************/ + +#define DMA_GET_CONDITION(hDma,X) \ + ((DMA_RGETH(hDma,SECCTL)&_##X##_MASK)>>_##X##_SHIFT) + +#define DMA_CLEAR_CONDITION(hDma,X) \ + _PER_RAOI(DMA_ADDRH(hDma,SECCTL),DMA,SECCTL,\ + (0xFFFF0AAA&~_##X##_MASK),\ + (0x00000555&~_##X##_MASK),\ + 0x00000000\ + ) + + +/******************************************************************************\ +* global typedef declarations +\******************************************************************************/ + +/* private object, not to be used by application code */ +typedef struct { + Uint32 allocated; + Uint32 eventId; + Uint32 volatile *baseAddr; +} DMA_Obj,*DMA_Handle; + +/* channel configuration structure */ +typedef struct { + Uint32 prictl; + Uint32 secctl; + Uint32 src; + Uint32 dst; + Uint32 xfrcnt; +} DMA_Config; + +typedef enum { + DMA_GBL_ADDRRLD = 0x00, + DMA_GBL_INDEX = 0x04, + DMA_GBL_CNTRLD = 0x08, + DMA_GBL_SPLIT = 0x0C +} DMA_Gbl; + +typedef struct { + Uint32 addrA; + Uint32 addrB; + Uint32 addrC; + Uint32 addrD; + Uint32 idxA; + Uint32 idxB; + Uint32 cntA; + Uint32 cntB; +} DMA_GlobalConfig; + + +/******************************************************************************\ +* global variable declarations +\******************************************************************************/ +extern far Uint32 _DMA_gblRegTbl[_DMA_GBLREG_CNT]; + +/* Predefined channel handles, these are only here for legacy */ +/* purposes and should not be used. */ +extern far DMA_Handle _DMA_hCha0; +extern far DMA_Handle _DMA_hCha1; +extern far DMA_Handle _DMA_hCha2; +extern far DMA_Handle _DMA_hCha3; + + +/******************************************************************************\ +* global function declarations +\******************************************************************************/ +CSLAPI void DMA_reset(DMA_Handle hDma); + +CSLAPI DMA_Handle DMA_open(int chaNum, Uint32 flags); +CSLAPI void DMA_close(DMA_Handle hDma); + +CSLAPI Uint32 DMA_allocGlobalReg(DMA_Gbl regType, Uint32 initVal); +CSLAPI void DMA_freeGlobalReg(Uint32 regId); + +CSLAPI Uint32 DMA_globalAlloc(Uint32 regs); +CSLAPI void DMA_globalFree(Uint32 regs); + + +/******************************************************************************\ +* inline function declarations +\******************************************************************************/ +IDECL Uint32 DMA_getEventId(DMA_Handle hDma); +IDECL Uint32 DMA_getStatus(DMA_Handle hDma); +IDECL void DMA_restoreStatus(DMA_Handle hDma,Uint32 status); + +IDECL void DMA_start(DMA_Handle hDma); +IDECL void DMA_stop(DMA_Handle hDma); +IDECL void DMA_pause(DMA_Handle hDma); +IDECL void DMA_autoStart(DMA_Handle hDma); +IDECL void DMA_wait(DMA_Handle hDma); + +IDECL void DMA_setAuxCtl(Uint32 auxCtl); + +IDECL Uint32 DMA_getGlobalRegAddr(Uint32 regId); +IDECL Uint32 DMA_getGlobalReg(Uint32 regId); +IDECL void DMA_setGlobalReg(Uint32 regId, Uint32 val); + +IDECL void DMA_config(DMA_Handle hDma, DMA_Config *config); +IDECL void DMA_configArgs(DMA_Handle hDma, Uint32 prictl, Uint32 secctl, + Uint32 src, Uint32 dst, Uint32 xfrcnt); +IDECL void DMA_getConfig(DMA_Handle hDma, DMA_Config *config); + +IDECL void DMA_globalConfig(Uint32 regs, DMA_GlobalConfig *cfg); +IDECL void DMA_globalConfigArgs(Uint32 regs, Uint32 addrA, Uint32 addrB, + Uint32 addrC,Uint32 addrD,Uint32 idxA,Uint32 idxB,Uint32 cntA,Uint32 cntB); +IDECL void DMA_globalGetConfig(Uint32 regs, DMA_GlobalConfig *cfg); + + +/******************************************************************************\ +* inline function definitions +\******************************************************************************/ +#ifdef USEDEFS +/*----------------------------------------------------------------------------*/ +IDEF Uint32 DMA_getEventId(DMA_Handle hDma) { + return (Uint32)(hDma->eventId); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 DMA_getStatus(DMA_Handle hDma) { + return (Uint32)DMA_FGETH(hDma,PRICTL,STATUS); +} +/*----------------------------------------------------------------------------*/ +IDEF void DMA_restoreStatus(DMA_Handle hDma,Uint32 status) { + DMA_FSETH(hDma,PRICTL,START,status); +} +/*----------------------------------------------------------------------------*/ +IDEF void DMA_start(DMA_Handle hDma) { + DMA_FSETSH(hDma,PRICTL,START,NORMAL); +} +/*----------------------------------------------------------------------------*/ +IDEF void DMA_stop(DMA_Handle hDma) { + DMA_FSETSH(hDma,PRICTL,START,STOP); +} +/*----------------------------------------------------------------------------*/ +IDEF void DMA_pause(DMA_Handle hDma) { + DMA_FSETSH(hDma,PRICTL,START,PAUSE); +} +/*----------------------------------------------------------------------------*/ +IDEF void DMA_autoStart(DMA_Handle hDma) { + DMA_FSETSH(hDma,PRICTL,START,AUTOINIT); +} +/*----------------------------------------------------------------------------*/ +IDEF void DMA_wait(DMA_Handle hDma) { + while (DMA_getStatus(hDma) & DMA_STATUS_RUNNING); +} +/*----------------------------------------------------------------------------*/ +IDEF void DMA_setAuxCtl(Uint32 auxCtl) { + DMA_RSET(AUXCTL,auxCtl); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 DMA_getGlobalRegAddr(Uint32 regId) { + return _DMA_gblRegTbl[regId&_DMA_GBLREG_MASK]; +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 DMA_getGlobalReg(Uint32 regId) { + return DMA_RGETA(_DMA_gblRegTbl[regId&_DMA_GBLREG_MASK],REG); +} +/*----------------------------------------------------------------------------*/ +IDEF void DMA_setGlobalReg(Uint32 regId, Uint32 val) { + DMA_RSETA(_DMA_gblRegTbl[regId&_DMA_GBLREG_MASK],REG,val); +} +/*----------------------------------------------------------------------------*/ +IDEF void DMA_config(DMA_Handle hDma, DMA_Config *config) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)(hDma->baseAddr); + register int prictl,secctl,src,dst,xfrcnt; + + gie = IRQ_globalDisable(); + + /* the compiler generates more efficient code if the loads */ + /* and stores are grouped together rather than intermixed */ + prictl = config->prictl; + secctl = config->secctl; + src = config->src; + dst = config->dst; + xfrcnt = config->xfrcnt; + + base[_DMA_PRICTL_OFFSET] = 0x00000000; + base[_DMA_SECCTL_OFFSET] = secctl; + base[_DMA_SRC_OFFSET] = src; + base[_DMA_DST_OFFSET] = dst; + base[_DMA_XFRCNT_OFFSET] = xfrcnt; + base[_DMA_PRICTL_OFFSET] = prictl; + + IRQ_globalRestore(gie); +} +/*----------------------------------------------------------------------------*/ +IDEF void DMA_configArgs(DMA_Handle hDma, Uint32 prictl, Uint32 secctl, + Uint32 src, Uint32 dst, Uint32 xfrcnt) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)(hDma->baseAddr); + + gie = IRQ_globalDisable(); + base[_DMA_PRICTL_OFFSET] = 0x00000000; + base[_DMA_SECCTL_OFFSET] = secctl; + base[_DMA_SRC_OFFSET] = src; + base[_DMA_DST_OFFSET] = dst; + base[_DMA_XFRCNT_OFFSET] = xfrcnt; + base[_DMA_PRICTL_OFFSET] = prictl; + IRQ_globalRestore(gie); +} +/*----------------------------------------------------------------------------*/ +IDEF void DMA_getConfig(DMA_Handle hDma, DMA_Config *config) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)(hDma->baseAddr); + volatile DMA_Config*cfg = (volatile DMA_Config*)config; + register int prictl,secctl,src,dst,xfrcnt; + + gie = IRQ_globalDisable(); + + /* the compiler generates more efficient code if the loads */ + /* and stores are grouped together rather than intermixed */ + prictl = base[_DMA_PRICTL_OFFSET]; + secctl = base[_DMA_SECCTL_OFFSET]; + src = base[_DMA_SRC_OFFSET]; + dst = base[_DMA_DST_OFFSET]; + xfrcnt = base[_DMA_XFRCNT_OFFSET]; + + cfg->prictl = prictl; + cfg->secctl = secctl; + cfg->src = src; + cfg->dst = dst; + cfg->xfrcnt = xfrcnt; + + IRQ_globalRestore(gie); +} +/*----------------------------------------------------------------------------*/ +IDEF void DMA_globalConfig(Uint32 regs, DMA_GlobalConfig *cfg) { + + Uint32 gie; + gie = IRQ_globalDisable(); + if (regs & DMA_GBLADDRA) DMA_RSET(GBLADDRA,cfg->addrA); + if (regs & DMA_GBLADDRB) DMA_RSET(GBLADDRB,cfg->addrB); + if (regs & DMA_GBLADDRC) DMA_RSET(GBLADDRC,cfg->addrC); + if (regs & DMA_GBLADDRD) DMA_RSET(GBLADDRD,cfg->addrD); + if (regs & DMA_GBLIDXA) DMA_RSET(GBLIDXA,cfg->idxA); + if (regs & DMA_GBLIDXB) DMA_RSET(GBLIDXB,cfg->idxB); + if (regs & DMA_GBLCNTA) DMA_RSET(GBLCNTA,cfg->cntA); + if (regs & DMA_GBLCNTB) DMA_RSET(GBLCNTB,cfg->cntB); + IRQ_globalRestore(gie); +} + +/*----------------------------------------------------------------------------*/ +IDEF void DMA_globalConfigArgs(Uint32 regs, Uint32 addrA, Uint32 addrB, + Uint32 addrC,Uint32 addrD,Uint32 idxA,Uint32 idxB,Uint32 cntA,Uint32 cntB) { + + Uint32 gie; + gie = IRQ_globalDisable(); + if (regs & DMA_GBLADDRA) DMA_RSET(GBLADDRA,addrA); + if (regs & DMA_GBLADDRB) DMA_RSET(GBLADDRB,addrB); + if (regs & DMA_GBLADDRC) DMA_RSET(GBLADDRC,addrC); + if (regs & DMA_GBLADDRD) DMA_RSET(GBLADDRD,addrD); + if (regs & DMA_GBLIDXA) DMA_RSET(GBLIDXA,idxA); + if (regs & DMA_GBLIDXB) DMA_RSET(GBLIDXB,idxB); + if (regs & DMA_GBLCNTA) DMA_RSET(GBLCNTA,cntA); + if (regs & DMA_GBLCNTB) DMA_RSET(GBLCNTB,cntB); + IRQ_globalRestore(gie); +} + +/*----------------------------------------------------------------------------*/ +IDEF void DMA_globalGetConfig(Uint32 regs, DMA_GlobalConfig *config) { + + Uint32 gie; + volatile DMA_GlobalConfig* cfg = (volatile DMA_GlobalConfig*)config; + + gie = IRQ_globalDisable(); + if (regs & DMA_GBLADDRA) cfg->addrA = DMA_RGET(GBLADDRA); + if (regs & DMA_GBLADDRB) cfg->addrB = DMA_RGET(GBLADDRB); + if (regs & DMA_GBLADDRC) cfg->addrC = DMA_RGET(GBLADDRC); + if (regs & DMA_GBLADDRD) cfg->addrD = DMA_RGET(GBLADDRD); + if (regs & DMA_GBLIDXA) cfg->idxA = DMA_RGET(GBLIDXA); + if (regs & DMA_GBLIDXB) cfg->idxB = DMA_RGET(GBLIDXB); + if (regs & DMA_GBLCNTA) cfg->cntA = DMA_RGET(GBLCNTA); + if (regs & DMA_GBLCNTB) cfg->cntB = DMA_RGET(GBLCNTB); + IRQ_globalRestore(gie); +} +/*----------------------------------------------------------------------------*/ +#endif /* USEDEFS */ + + +#endif /* DMA_SUPPORT */ +#endif /* _CSL_DMA_H_ */ +/******************************************************************************\ +* End of csl_dma.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_dmahal.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_dmahal.h new file mode 100644 index 0000000..47576ee --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_dmahal.h @@ -0,0 +1,1197 @@ +/******************************************************************************\ +* Copyright (C) 1999-2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_dmahal.h +* DATE CREATED.. 03/12/1999 +* LAST MODIFIED. 02/05/2002 added 6204/6205 to DMA_COND1 +*------------------------------------------------------------------------------ +* REGISTERS +* +* AUXCTL - auxiliary control register +* PRICTL0 - channel primary control register 0 +* PRICTL1 - channel primary control register 1 +* PRICTL2 - channel primary control register 2 +* PRICTL3 - channel primary control register 3 +* SECCTL0 - channel seccondary control register 0 +* SECCTL1 - channel seccondary control register 1 +* SECCTL2 - channel seccondary control register 2 +* SECCTL3 - channel seccondary control register 3 +* SRC0 - channel src address register 0 +* SRC1 - channel src address register 1 +* SRC2 - channel src address register 2 +* SRC3 - channel src address register 3 +* DST0 - channel destination address register 0 +* DST1 - channel destination address register 1 +* DST2 - channel destination address register 2 +* DST3 - channel destination address register 3 +* XFRCNT0 - channel transfer count register 0 +* XFRCNT1 - channel transfer count register 1 +* XFRCNT2 - channel transfer count register 2 +* XFRCNT3 - channel transfer count register 3 +* GBLCNTA - global count reload register A +* GBLCNTB - global count reload register B +* GBLIDXA - global index register A +* GBLIDXB - global index register B +* GBLADDRA - global address reload register A +* GBLADDRB - global address reload register B +* GBLADDRC - global address reload register C +* GBLADDRD - global address reload register D +* +\******************************************************************************/ +#ifndef _CSL_DMAHAL_H_ +#define _CSL_DMAHAL_H_ + +#include +#include + +#if (DMA_SUPPORT) +/******************************************************************************\ +* MISC section +\******************************************************************************/ + + #define _DMA_COND1 (CHIP_6202|CHIP_6203|CHIP_6204|CHIP_6205) + + #define _DMA_BASE_CHA0 0x01840000u + #define _DMA_BASE_CHA1 0x01840040u + #define _DMA_BASE_CHA2 0x01840004u + #define _DMA_BASE_CHA3 0x01840044u + + +/******************************************************************************\ +* module level register/field access macros +\******************************************************************************/ + + /* ----------------- */ + /* FIELD MAKE MACROS */ + /* ----------------- */ + + #define DMA_FMK(REG,FIELD,x)\ + _PER_FMK(DMA,##REG,##FIELD,x) + + #define DMA_FMKS(REG,FIELD,SYM)\ + _PER_FMKS(DMA,##REG,##FIELD,##SYM) + + + /* -------------------------------- */ + /* RAW REGISTER/FIELD ACCESS MACROS */ + /* -------------------------------- */ + + #define DMA_ADDR(REG)\ + _DMA_##REG##_ADDR + + #define DMA_RGET(REG)\ + _PER_RGET(_DMA_##REG##_ADDR,DMA,##REG) + + #define DMA_RSET(REG,x)\ + _PER_RSET(_DMA_##REG##_ADDR,DMA,##REG,x) + + #define DMA_FGET(REG,FIELD)\ + _DMA_##REG##_FGET(##FIELD) + + #define DMA_FSET(REG,FIELD,x)\ + _DMA_##REG##_FSET(##FIELD,##x) + + #define DMA_FSETS(REG,FIELD,SYM)\ + _DMA_##REG##_FSETS(##FIELD,##SYM) + + + /* ------------------------------------------ */ + /* ADDRESS BASED REGISTER/FIELD ACCESS MACROS */ + /* ------------------------------------------ */ + + #define DMA_RGETA(addr,REG)\ + _PER_RGET(addr,DMA,##REG) + + #define DMA_RSETA(addr,REG,x)\ + _PER_RSET(addr,DMA,##REG,x) + + #define DMA_FGETA(addr,REG,FIELD)\ + _PER_FGET(addr,DMA,##REG,##FIELD) + + #define DMA_FSETA(addr,REG,FIELD,x)\ + _PER_FSET(addr,DMA,##REG,##FIELD,x) + + #define DMA_FSETSA(addr,REG,FIELD,SYM)\ + _PER_FSETS(addr,DMA,##REG,##FIELD,##SYM) + + + /* ----------------------------------------- */ + /* HANDLE BASED REGISTER/FIELD ACCESS MACROS */ + /* ----------------------------------------- */ + + #define DMA_ADDRH(h,REG)\ + (Uint32)(&((h)->baseAddr[_DMA_##REG##_OFFSET])) + + #define DMA_RGETH(h,REG)\ + DMA_RGETA(DMA_ADDRH(h,##REG),##REG) + + + #define DMA_RSETH(h,REG,x)\ + DMA_RSETA(DMA_ADDRH(h,##REG),##REG,x) + + + #define DMA_FGETH(h,REG,FIELD)\ + DMA_FGETA(DMA_ADDRH(h,##REG),##REG,##FIELD) + + + #define DMA_FSETH(h,REG,FIELD,x)\ + DMA_FSETA(DMA_ADDRH(h,##REG),##REG,##FIELD,x) + + + #define DMA_FSETSH(h,REG,FIELD,SYM)\ + DMA_FSETSA(DMA_ADDRH(h,##REG),##REG,##FIELD,##SYM) + + + +/******************************************************************************\ +* _____________________ +* | | +* | A U X C T L | +* |___________________| +* +* AUXCTL - auxiliary control register +* +* FIELDS (msb -> lsb) +* (rw) AUXPRI +* (rw) CHPRI +* +\******************************************************************************/ + #define _DMA_AUXCTL_ADDR 0x01840070u + + #define _DMA_AUXCTL_AUXPRI_MASK 0x00000010u + #define _DMA_AUXCTL_AUXPRI_SHIFT 0x00000004u + #define DMA_AUXCTL_AUXPRI_DEFAULT 0x00000000u + #define DMA_AUXCTL_AUXPRI_OF(x) _VALUEOF(x) + #define DMA_AUXCTL_AUXPRI_CPU 0x00000000u + #define DMA_AUXCTL_AUXPRI_DMA 0x00000001u + + #define _DMA_AUXCTL_CHPRI_MASK 0x0000000Fu + #define _DMA_AUXCTL_CHPRI_SHIFT 0x00000000u + #define DMA_AUXCTL_CHPRI_DEFAULT 0x00000000u + #define DMA_AUXCTL_CHPRI_OF(x) _VALUEOF(x) + #define DMA_AUXCTL_CHPRI_HIGHEST 0x00000000u + #define DMA_AUXCTL_CHPRI_2ND 0x00000001u + #define DMA_AUXCTL_CHPRI_3RD 0x00000002u + #define DMA_AUXCTL_CHPRI_4TH 0x00000003u + #define DMA_AUXCTL_CHPRI_LOWEST 0x00000004u + + #define DMA_AUXCTL_OF(x) _VALUEOF(x) + + #define DMA_AUXCTL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(DMA,AUXCTL,AUXPRI) \ + |_PER_FDEFAULT(DMA,AUXCTL,CHPRI) \ + ) + + #define DMA_AUXCTL_RMK(auxpri,chpri) (Uint32)( \ + _PER_FMK(DMA,AUXCTL,AUXPRI,auxpri) \ + |_PER_FMK(DMA,AUXCTL,CHPRI,chpri) \ + ) + + #define _DMA_AUXCTL_FGET(FIELD)\ + _PER_FGET(_DMA_AUXCTL_ADDR,DMA,AUXCTL,##FIELD) + + #define _DMA_AUXCTL_FSET(FIELD,field)\ + _PER_FSET(_DMA_AUXCTL_ADDR,DMA,AUXCTL,##FIELD,field) + + #define _DMA_AUXCTL_FSETS(FIELD,SYM)\ + _PER_FSETS(_DMA_AUXCTL_ADDR,DMA,AUXCTL,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | P R I C T L | +* |___________________| +* +* PRICTL0 - channel primary control register 0 +* PRICTL1 - channel primary control register 1 +* PRICTL2 - channel primary control register 2 +* PRICTL3 - channel primary control register 3 +* +* FIELDS (msb -> lsb) +* (rw) DSTRLD +* (rw) SRCRLD +* (rw) EMOD +* (rw) FS +* (rw) TCINT +* (rw) PRI +* (rw) WSYNC +* (rw) RSYNC +* (rw) INDEX +* (rw) CNTRLD +* (rw) SPLIT +* (rw) ESIZE +* (rw) DSTDIR +* (rw) SRCDIR +* (r) STATUS +* (rw) START +* +\******************************************************************************/ + #define _DMA_PRICTL_OFFSET 0 + + #define _DMA_PRICTL0_ADDR 0x01840000u + #define _DMA_PRICTL1_ADDR 0x01840040u + #define _DMA_PRICTL2_ADDR 0x01840004u + #define _DMA_PRICTL3_ADDR 0x01840044u + + #define _DMA_PRICTL_DSTRLD_MASK 0xC0000000u + #define _DMA_PRICTL_DSTRLD_SHIFT 0x0000001Eu + #define DMA_PRICTL_DSTRLD_DEFAULT 0x00000000u + #define DMA_PRICTL_DSTRLD_OF(x) _VALUEOF(x) + #define DMA_PRICTL_DSTRLD_NONE 0x00000000u + #define DMA_PRICTL_DSTRLD_B 0x00000001u + #define DMA_PRICTL_DSTRLD_C 0x00000002u + #define DMA_PRICTL_DSTRLD_D 0x00000003u + + #define _DMA_PRICTL_SRCRLD_MASK 0x30000000u + #define _DMA_PRICTL_SRCRLD_SHIFT 0x0000001Cu + #define DMA_PRICTL_SRCRLD_DEFAULT 0x00000000u + #define DMA_PRICTL_SRCRLD_OF(x) _VALUEOF(x) + #define DMA_PRICTL_SRCRLD_NONE 0x00000000u + #define DMA_PRICTL_SRCRLD_B 0x00000001u + #define DMA_PRICTL_SRCRLD_C 0x00000002u + #define DMA_PRICTL_SRCRLD_D 0x00000003u + + #define _DMA_PRICTL_EMOD_MASK 0x08000000u + #define _DMA_PRICTL_EMOD_SHIFT 0x0000001Bu + #define DMA_PRICTL_EMOD_DEFAULT 0x00000000u + #define DMA_PRICTL_EMOD_OF(x) _VALUEOF(x) + #define DMA_PRICTL_EMOD_NOHALT 0x00000000u + #define DMA_PRICTL_EMOD_HALT 0x00000001u + + #define _DMA_PRICTL_FS_MASK 0x04000000u + #define _DMA_PRICTL_FS_SHIFT 0x0000001Au + #define DMA_PRICTL_FS_DEFAULT 0x00000000u + #define DMA_PRICTL_FS_OF(x) _VALUEOF(x) + #define DMA_PRICTL_FS_DISABLE 0x00000000u + #define DMA_PRICTL_FS_RSYNC 0x00000001u + + #define _DMA_PRICTL_TCINT_MASK 0x02000000u + #define _DMA_PRICTL_TCINT_SHIFT 0x00000019u + #define DMA_PRICTL_TCINT_DEFAULT 0x00000000u + #define DMA_PRICTL_TCINT_OF(x) _VALUEOF(x) + #define DMA_PRICTL_TCINT_DISABLE 0x00000000u + #define DMA_PRICTL_TCINT_ENABLE 0x00000001u + + #define _DMA_PRICTL_PRI_MASK 0x01000000u + #define _DMA_PRICTL_PRI_SHIFT 0x00000018u + #define DMA_PRICTL_PRI_DEFAULT 0x00000000u + #define DMA_PRICTL_PRI_OF(x) _VALUEOF(x) + #define DMA_PRICTL_PRI_CPU 0x00000000u + #define DMA_PRICTL_PRI_DMA 0x00000001u + + #define _DMA_PRICTL_WSYNC_MASK 0x00F80000u + #define _DMA_PRICTL_WSYNC_SHIFT 0x00000013u + #define DMA_PRICTL_WSYNC_DEFAULT 0x00000000u + #define DMA_PRICTL_WSYNC_OF(x) _VALUEOF(x) + #define DMA_PRICTL_WSYNC_NONE 0x00000000u + #define DMA_PRICTL_WSYNC_TINT0 0x00000001u + #define DMA_PRICTL_WSYNC_TINT1 0x00000002u + #define DMA_PRICTL_WSYNC_SDINT 0x00000003u + #define DMA_PRICTL_WSYNC_EXTINT4 0x00000004u + #define DMA_PRICTL_WSYNC_EXTINT5 0x00000005u + #define DMA_PRICTL_WSYNC_EXTINT6 0x00000006u + #define DMA_PRICTL_WSYNC_EXTINT7 0x00000007u + #define DMA_PRICTL_WSYNC_DMAINT0 0x00000008u + #define DMA_PRICTL_WSYNC_DMAINT1 0x00000009u + #define DMA_PRICTL_WSYNC_DMAINT2 0x0000000Au + #define DMA_PRICTL_WSYNC_DMAINT3 0x0000000Bu + #define DMA_PRICTL_WSYNC_XEVT0 0x0000000Cu + #define DMA_PRICTL_WSYNC_REVT0 0x0000000Du + #define DMA_PRICTL_WSYNC_XEVT1 0x0000000Eu + #define DMA_PRICTL_WSYNC_REVT1 0x0000000Fu + #define DMA_PRICTL_WSYNC_DSPINT 0x00000010u + #define DMA_PRICTL_WSYNC_XEVT2 0x00000011u + #define DMA_PRICTL_WSYNC_REVT2 0x00000012u + + #define _DMA_PRICTL_RSYNC_MASK 0x0007C000u + #define _DMA_PRICTL_RSYNC_SHIFT 0x0000000Eu + #define DMA_PRICTL_RSYNC_DEFAULT 0x00000000u + #define DMA_PRICTL_RSYNC_OF(x) _VALUEOF(x) + #define DMA_PRICTL_RSYNC_NONE 0x00000000u + #define DMA_PRICTL_RSYNC_TINT0 0x00000001u + #define DMA_PRICTL_RSYNC_TINT1 0x00000002u + #define DMA_PRICTL_RSYNC_SDINT 0x00000003u + #define DMA_PRICTL_RSYNC_EXTINT4 0x00000004u + #define DMA_PRICTL_RSYNC_EXTINT5 0x00000005u + #define DMA_PRICTL_RSYNC_EXTINT6 0x00000006u + #define DMA_PRICTL_RSYNC_EXTINT7 0x00000007u + #define DMA_PRICTL_RSYNC_DMAINT0 0x00000008u + #define DMA_PRICTL_RSYNC_DMAINT1 0x00000009u + #define DMA_PRICTL_RSYNC_DMAINT2 0x0000000Au + #define DMA_PRICTL_RSYNC_DMAINT3 0x0000000Bu + #define DMA_PRICTL_RSYNC_XEVT0 0x0000000Cu + #define DMA_PRICTL_RSYNC_REVT0 0x0000000Du + #define DMA_PRICTL_RSYNC_XEVT1 0x0000000Eu + #define DMA_PRICTL_RSYNC_REVT1 0x0000000Fu + #define DMA_PRICTL_RSYNC_DSPINT 0x00000010u + #define DMA_PRICTL_RSYNC_XEVT2 0x00000011u + #define DMA_PRICTL_RSYNC_REVT2 0x00000012u + + #define _DMA_PRICTL_INDEX_MASK 0x00002000u + #define _DMA_PRICTL_INDEX_SHIFT 0x0000000Du + #define DMA_PRICTL_INDEX_DEFAULT 0x00000000u + #define DMA_PRICTL_INDEX_OF(x) _VALUEOF(x) + #define DMA_PRICTL_INDEX_NA 0x00000000u + #define DMA_PRICTL_INDEX_A 0x00000000u + #define DMA_PRICTL_INDEX_B 0x00000001u + + #define _DMA_PRICTL_CNTRLD_MASK 0x00001000u + #define _DMA_PRICTL_CNTRLD_SHIFT 0x0000000Cu + #define DMA_PRICTL_CNTRLD_DEFAULT 0x00000000u + #define DMA_PRICTL_CNTRLD_OF(x) _VALUEOF(x) + #define DMA_PRICTL_CNTRLD_NA 0x00000000u + #define DMA_PRICTL_CNTRLD_A 0x00000000u + #define DMA_PRICTL_CNTRLD_B 0x00000001u + + #define _DMA_PRICTL_SPLIT_MASK 0x00000C00u + #define _DMA_PRICTL_SPLIT_SHIFT 0x0000000Au + #define DMA_PRICTL_SPLIT_DEFAULT 0x00000000u + #define DMA_PRICTL_SPLIT_OF(x) _VALUEOF(x) + #define DMA_PRICTL_SPLIT_DISABLE 0x00000000u + #define DMA_PRICTL_SPLIT_A 0x00000001u + #define DMA_PRICTL_SPLIT_B 0x00000002u + #define DMA_PRICTL_SPLIT_C 0x00000003u + + #define _DMA_PRICTL_ESIZE_MASK 0x00000300u + #define _DMA_PRICTL_ESIZE_SHIFT 0x00000008u + #define DMA_PRICTL_ESIZE_DEFAULT 0x00000000u + #define DMA_PRICTL_ESIZE_OF(x) _VALUEOF(x) + #define DMA_PRICTL_ESIZE_32BIT 0x00000000u + #define DMA_PRICTL_ESIZE_16BIT 0x00000001u + #define DMA_PRICTL_ESIZE_8BIT 0x00000002u + + #define _DMA_PRICTL_DSTDIR_MASK 0x000000C0u + #define _DMA_PRICTL_DSTDIR_SHIFT 0x00000006u + #define DMA_PRICTL_DSTDIR_DEFAULT 0x00000000u + #define DMA_PRICTL_DSTDIR_OF(x) _VALUEOF(x) + #define DMA_PRICTL_DSTDIR_NONE 0x00000000u + #define DMA_PRICTL_DSTDIR_INC 0x00000001u + #define DMA_PRICTL_DSTDIR_DEC 0x00000002u + #define DMA_PRICTL_DSTDIR_IDX 0x00000003u + + #define _DMA_PRICTL_SRCDIR_MASK 0x00000030u + #define _DMA_PRICTL_SRCDIR_SHIFT 0x00000004u + #define DMA_PRICTL_SRCDIR_DEFAULT 0x00000000u + #define DMA_PRICTL_SRCDIR_OF(x) _VALUEOF(x) + #define DMA_PRICTL_SRCDIR_NONE 0x00000000u + #define DMA_PRICTL_SRCDIR_INC 0x00000001u + #define DMA_PRICTL_SRCDIR_DEC 0x00000002u + #define DMA_PRICTL_SRCDIR_IDX 0x00000003u + + #define _DMA_PRICTL_STATUS_MASK 0x0000000Cu + #define _DMA_PRICTL_STATUS_SHIFT 0x00000002u + #define DMA_PRICTL_STATUS_DEFAULT 0x00000000u + #define DMA_PRICTL_STATUS_OF(x) _VALUEOF(x) + #define DMA_PRICTL_STATUS_STOPPED 0x00000000u + #define DMA_PRICTL_STATUS_RUNNING 0x00000001u + #define DMA_PRICTL_STATUS_PAUSED 0x00000002u + #define DMA_PRICTL_STATUS_AUTORUNNING 0x00000003u + + #define _DMA_PRICTL_START_MASK 0x00000003u + #define _DMA_PRICTL_START_SHIFT 0x00000000u + #define DMA_PRICTL_START_DEFAULT 0x00000000u + #define DMA_PRICTL_START_OF(x) _VALUEOF(x) + #define DMA_PRICTL_START_STOP 0x00000000u + #define DMA_PRICTL_START_NORMAL 0x00000001u + #define DMA_PRICTL_START_PAUSE 0x00000002u + #define DMA_PRICTL_START_AUTOINIT 0x00000003u + + #define DMA_PRICTL_OF(x) _VALUEOF(x) + + #define DMA_PRICTL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(DMA,PRICTL,DSTRLD)\ + |_PER_FDEFAULT(DMA,PRICTL,SRCRLD)\ + |_PER_FDEFAULT(DMA,PRICTL,EMOD)\ + |_PER_FDEFAULT(DMA,PRICTL,FS)\ + |_PER_FDEFAULT(DMA,PRICTL,TCINT)\ + |_PER_FDEFAULT(DMA,PRICTL,PRI)\ + |_PER_FDEFAULT(DMA,PRICTL,WSYNC)\ + |_PER_FDEFAULT(DMA,PRICTL,RSYNC)\ + |_PER_FDEFAULT(DMA,PRICTL,INDEX)\ + |_PER_FDEFAULT(DMA,PRICTL,CNTRLD)\ + |_PER_FDEFAULT(DMA,PRICTL,SPLIT)\ + |_PER_FDEFAULT(DMA,PRICTL,ESIZE)\ + |_PER_FDEFAULT(DMA,PRICTL,DSTDIR)\ + |_PER_FDEFAULT(DMA,PRICTL,SRCDIR)\ + |_PER_FDEFAULT(DMA,PRICTL,STATUS)\ + |_PER_FDEFAULT(DMA,PRICTL,START)\ + ) + + #define DMA_PRICTL_RMK(dstrld,srcrld,emod,fs,tcint,pri,wsync,rsync,index,\ + cntrld,split,esize,dstdir,srcdir,start) (Uint32)( \ + _PER_FMK(DMA,PRICTL,DSTRLD,dstrld)\ + |_PER_FMK(DMA,PRICTL,SRCRLD,srcrld)\ + |_PER_FMK(DMA,PRICTL,EMOD,emod)\ + |_PER_FMK(DMA,PRICTL,FS,fs)\ + |_PER_FMK(DMA,PRICTL,TCINT,tcint)\ + |_PER_FMK(DMA,PRICTL,PRI,pri)\ + |_PER_FMK(DMA,PRICTL,WSYNC,wsync)\ + |_PER_FMK(DMA,PRICTL,RSYNC,rsync)\ + |_PER_FMK(DMA,PRICTL,INDEX,index)\ + |_PER_FMK(DMA,PRICTL,CNTRLD,cntrld)\ + |_PER_FMK(DMA,PRICTL,SPLIT,split)\ + |_PER_FMK(DMA,PRICTL,ESIZE,esize)\ + |_PER_FMK(DMA,PRICTL,DSTDIR,dstdir)\ + |_PER_FMK(DMA,PRICTL,SRCDIR,srcdir)\ + |_PER_FMK(DMA,PRICTL,START,start)\ + ) + + #define _DMA_PRICTL_FGET(N,FIELD)\ + _PER_FGET(_DMA_PRICTL##N##_ADDR,DMA,PRICTL,##FIELD) + + #define _DMA_PRICTL_FSET(N,FIELD,field)\ + _PER_FSET(_DMA_PRICTL##N##_ADDR,DMA,PRICTL,##FIELD,field) + + #define _DMA_PRICTL_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_DMA_PRICTL##N##_ADDR,DMA,PRICTL,##FIELD,##SYM) + + #define _DMA_PRICTL0_FGET(FIELD) _DMA_PRICTL_FGET(0,##FIELD) + #define _DMA_PRICTL1_FGET(FIELD) _DMA_PRICTL_FGET(1,##FIELD) + #define _DMA_PRICTL2_FGET(FIELD) _DMA_PRICTL_FGET(2,##FIELD) + #define _DMA_PRICTL3_FGET(FIELD) _DMA_PRICTL_FGET(3,##FIELD) + + #define _DMA_PRICTL0_FSET(FIELD,f) _DMA_PRICTL_FSET(0,##FIELD,f) + #define _DMA_PRICTL1_FSET(FIELD,f) _DMA_PRICTL_FSET(1,##FIELD,f) + #define _DMA_PRICTL2_FSET(FIELD,f) _DMA_PRICTL_FSET(2,##FIELD,f) + #define _DMA_PRICTL3_FSET(FIELD,f) _DMA_PRICTL_FSET(3,##FIELD,f) + + #define _DMA_PRICTL0_FSETS(FIELD,SYM) _DMA_PRICTL_FSETS(0,##FIELD,##SYM) + #define _DMA_PRICTL1_FSETS(FIELD,SYM) _DMA_PRICTL_FSETS(1,##FIELD,##SYM) + #define _DMA_PRICTL2_FSETS(FIELD,SYM) _DMA_PRICTL_FSETS(2,##FIELD,##SYM) + #define _DMA_PRICTL3_FSETS(FIELD,SYM) _DMA_PRICTL_FSETS(3,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | S E C C T L | +* |___________________| +* +* SECCTL0 - channel seccondary control register 0 +* SECCTL1 - channel seccondary control register 1 +* SECCTL2 - channel seccondary control register 2 +* SECCTL3 - channel seccondary control register 3 +* +* FIELDS (msb -> lsb) +* (rw) WSPOL (1) +* (rw) RSPOL (1) +* (rw) FSIG (1) +* (rw) DMACEN +* (rw) WSYNCCLR +* (rw) WSYNCSTAT +* (rw) RSYNCCLR +* (rw) RSYNCSTAT +* (rw) WDROPIE +* (rw) WDROPCOND +* (rw) RDROPIE +* (rw) RDROPCOND +* (rw) BLOCKIE +* (rw) BLOCKCOND +* (rw) LASTIE +* (rw) LASTCOND +* (rw) FRAMEIE +* (rw) FRAMECOND +* (rw) SXIE +* (rw) SXCOND +* +* (1) only on 6202 / 6203 /6204 /6205 devices +* +\******************************************************************************/ + #define _DMA_SECCTL_OFFSET 2 + + #define _DMA_SECCTL0_ADDR 0x01840008u + #define _DMA_SECCTL1_ADDR 0x01840048u + #define _DMA_SECCTL2_ADDR 0x0184000Cu + #define _DMA_SECCTL3_ADDR 0x0184004Cu + +#if (_DMA_COND1) + #define _DMA_SECCTL_WSPOL_MASK 0x00200000u + #define _DMA_SECCTL_WSPOL_SHIFT 0x00000015u + #define DMA_SECCTL_WSPOL_DEFAULT 0x00000000u + #define DMA_SECCTL_WSPOL_OF(x) _VALUEOF(x) + #define DMA_SECCTL_WSPOL_NA 0x00000000u + #define DMA_SECCTL_WSPOL_ACTIVEHIGH 0x00000000u + #define DMA_SECCTL_WSPOL_ACTIVELOW 0x00000001u + + #define _DMA_SECCTL_RSPOL_MASK 0x00100000u + #define _DMA_SECCTL_RSPOL_SHIFT 0x00000014u + #define DMA_SECCTL_RSPOL_DEFAULT 0x00000000u + #define DMA_SECCTL_RSPOL_OF(x) _VALUEOF(x) + #define DMA_SECCTL_RSPOL_NA 0x00000000u + #define DMA_SECCTL_RSPOL_ACTIVEHIGH 0x00000000u + #define DMA_SECCTL_RSPOL_ACTIVELOW 0x00000001u + + #define _DMA_SECCTL_FSIG_MASK 0x00080000u + #define _DMA_SECCTL_FSIG_SHIFT 0x00000013u + #define DMA_SECCTL_FSIG_DEFAULT 0x00000000u + #define DMA_SECCTL_FSIG_OF(x) _VALUEOF(x) + #define DMA_SECCTL_FSIG_NA 0x00000000u + #define DMA_SECCTL_FSIG_NORMAL 0x00000000u + #define DMA_SECCTL_FSIG_IGNORE 0x00000001u +#endif + + #define _DMA_SECCTL_DMACEN_MASK 0x00070000u + #define _DMA_SECCTL_DMACEN_SHIFT 0x00000010u + #define DMA_SECCTL_DMACEN_DEFAULT 0x00000000u + #define DMA_SECCTL_DMACEN_OF(x) _VALUEOF(x) + #define DMA_SECCTL_DMACEN_LOW 0x00000000u + #define DMA_SECCTL_DMACEN_HIGH 0x00000001u + #define DMA_SECCTL_DMACEN_RSYNCSTAT 0x00000002u + #define DMA_SECCTL_DMACEN_WSYNCSTAT 0x00000003u + #define DMA_SECCTL_DMACEN_FRAMECOND 0x00000004u + #define DMA_SECCTL_DMACEN_BLOCKCOND 0x00000005u + + #define _DMA_SECCTL_WSYNCCLR_MASK 0x00008000u + #define _DMA_SECCTL_WSYNCCLR_SHIFT 0x0000000Fu + #define DMA_SECCTL_WSYNCCLR_DEFAULT 0x00000000u + #define DMA_SECCTL_WSYNCCLR_OF(x) _VALUEOF(x) + #define DMA_SECCTL_WSYNCCLR_NOTHING 0x00000000u + #define DMA_SECCTL_WSYNCCLR_CLEAR 0x00000001u + + #define _DMA_SECCTL_WSYNCSTAT_MASK 0x00004000u + #define _DMA_SECCTL_WSYNCSTAT_SHIFT 0x0000000Eu + #define DMA_SECCTL_WSYNCSTAT_DEFAULT 0x00000000u + #define DMA_SECCTL_WSYNCSTAT_OF(x) _VALUEOF(x) + #define DMA_SECCTL_WSYNCSTAT_CLEAR 0x00000000u + #define DMA_SECCTL_WSYNCSTAT_SET 0x00000001u + + #define _DMA_SECCTL_RSYNCCLR_MASK 0x00002000u + #define _DMA_SECCTL_RSYNCCLR_SHIFT 0x0000000Du + #define DMA_SECCTL_RSYNCCLR_DEFAULT 0x00000000u + #define DMA_SECCTL_RSYNCCLR_OF(x) _VALUEOF(x) + #define DMA_SECCTL_RSYNCCLR_NOTHING 0x00000000u + #define DMA_SECCTL_RSYNCCLR_CLEAR 0x00000001u + + #define _DMA_SECCTL_RSYNCSTAT_MASK 0x00001000u + #define _DMA_SECCTL_RSYNCSTAT_SHIFT 0x0000000Cu + #define DMA_SECCTL_RSYNCSTAT_DEFAULT 0x00000000u + #define DMA_SECCTL_RSYNCSTAT_OF(x) _VALUEOF(x) + #define DMA_SECCTL_RSYNCSTAT_CLEAR 0x00000000u + #define DMA_SECCTL_RSYNCSTAT_SET 0x00000001u + + #define _DMA_SECCTL_WDROPIE_MASK 0x00000800u + #define _DMA_SECCTL_WDROPIE_SHIFT 0x0000000Bu + #define DMA_SECCTL_WDROPIE_DEFAULT 0x00000000u + #define DMA_SECCTL_WDROPIE_OF(x) _VALUEOF(x) + #define DMA_SECCTL_WDROPIE_DISABLE 0x00000000u + #define DMA_SECCTL_WDROPIE_ENABLE 0x00000001u + + #define _DMA_SECCTL_WDROPCOND_MASK 0x00000400u + #define _DMA_SECCTL_WDROPCOND_SHIFT 0x0000000Au + #define DMA_SECCTL_WDROPCOND_DEFAULT 0x00000000u + #define DMA_SECCTL_WDROPCOND_OF(x) _VALUEOF(x) + #define DMA_SECCTL_WDROPCOND_CLEAR 0x00000000u + #define DMA_SECCTL_WDROPCOND_SET 0x00000001u + + #define _DMA_SECCTL_RDROPIE_MASK 0x00000200u + #define _DMA_SECCTL_RDROPIE_SHIFT 0x00000009u + #define DMA_SECCTL_RDROPIE_DEFAULT 0x00000000u + #define DMA_SECCTL_RDROPIE_OF(x) _VALUEOF(x) + #define DMA_SECCTL_RDROPIE_DISABLE 0x00000000u + #define DMA_SECCTL_RDROPIE_ENABLE 0x00000001u + + #define _DMA_SECCTL_RDROPCOND_MASK 0x00000100u + #define _DMA_SECCTL_RDROPCOND_SHIFT 0x00000008u + #define DMA_SECCTL_RDROPCOND_DEFAULT 0x00000000u + #define DMA_SECCTL_RDROPCOND_OF(x) _VALUEOF(x) + #define DMA_SECCTL_RDROPCOND_CLEAR 0x00000000u + #define DMA_SECCTL_RDROPCOND_SET 0x00000001u + + #define _DMA_SECCTL_BLOCKIE_MASK 0x00000080u + #define _DMA_SECCTL_BLOCKIE_SHIFT 0x00000007u + #define DMA_SECCTL_BLOCKIE_DEFAULT 0x00000001u + #define DMA_SECCTL_BLOCKIE_OF(x) _VALUEOF(x) + #define DMA_SECCTL_BLOCKIE_DISABLE 0x00000000u + #define DMA_SECCTL_BLOCKIE_ENABLE 0x00000001u + + #define _DMA_SECCTL_BLOCKCOND_MASK 0x00000040u + #define _DMA_SECCTL_BLOCKCOND_SHIFT 0x00000006u + #define DMA_SECCTL_BLOCKCOND_DEFAULT 0x00000000u + #define DMA_SECCTL_BLOCKCOND_OF(x) _VALUEOF(x) + #define DMA_SECCTL_BLOCKCOND_CLEAR 0x00000000u + #define DMA_SECCTL_BLOCKCOND_SET 0x00000001u + + #define _DMA_SECCTL_LASTIE_MASK 0x00000020u + #define _DMA_SECCTL_LASTIE_SHIFT 0x00000005u + #define DMA_SECCTL_LASTIE_DEFAULT 0x00000000u + #define DMA_SECCTL_LASTIE_OF(x) _VALUEOF(x) + #define DMA_SECCTL_LASTIE_DISABLE 0x00000000u + #define DMA_SECCTL_LASTIE_ENABLE 0x00000001u + + #define _DMA_SECCTL_LASTCOND_MASK 0x00000010u + #define _DMA_SECCTL_LASTCOND_SHIFT 0x00000004u + #define DMA_SECCTL_LASTCOND_DEFAULT 0x00000000u + #define DMA_SECCTL_LASTCOND_OF(x) _VALUEOF(x) + #define DMA_SECCTL_LASTCOND_CLEAR 0x00000000u + #define DMA_SECCTL_LASTCOND_SET 0x00000001u + + #define _DMA_SECCTL_FRAMEIE_MASK 0x00000008u + #define _DMA_SECCTL_FRAMEIE_SHIFT 0x00000003u + #define DMA_SECCTL_FRAMEIE_DEFAULT 0x00000000u + #define DMA_SECCTL_FRAMEIE_OF(x) _VALUEOF(x) + #define DMA_SECCTL_FRAMEIE_DISABLE 0x00000000u + #define DMA_SECCTL_FRAMEIE_ENABLE 0x00000001u + + #define _DMA_SECCTL_FRAMECOND_MASK 0x00000004u + #define _DMA_SECCTL_FRAMECOND_SHIFT 0x00000002u + #define DMA_SECCTL_FRAMECOND_DEFAULT 0x00000000u + #define DMA_SECCTL_FRAMECOND_OF(x) _VALUEOF(x) + #define DMA_SECCTL_FRAMECOND_CLEAR 0x00000000u + #define DMA_SECCTL_FRAMECOND_SET 0x00000001u + + #define _DMA_SECCTL_SXIE_MASK 0x00000002u + #define _DMA_SECCTL_SXIE_SHIFT 0x00000001u + #define DMA_SECCTL_SXIE_DEFAULT 0x00000000u + #define DMA_SECCTL_SXIE_OF(x) _VALUEOF(x) + #define DMA_SECCTL_SXIE_DISABLE 0x00000000u + #define DMA_SECCTL_SXIE_ENABLE 0x00000001u + + #define _DMA_SECCTL_SXCOND_MASK 0x00000001u + #define _DMA_SECCTL_SXCOND_SHIFT 0x00000000u + #define DMA_SECCTL_SXCOND_DEFAULT 0x00000000u + #define DMA_SECCTL_SXCOND_OF(x) _VALUEOF(x) + #define DMA_SECCTL_SXCOND_CLEAR 0x00000000u + #define DMA_SECCTL_SXCOND_SET 0x00000001u + + #define DMA_SECCTL_OF(x) _VALUEOF(x) + +#if (_DMA_COND1) + #define DMA_SECCTL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(DMA,SECCTL,WSPOL)\ + |_PER_FDEFAULT(DMA,SECCTL,RSPOL)\ + |_PER_FDEFAULT(DMA,SECCTL,FSIG)\ + |_PER_FDEFAULT(DMA,SECCTL,DMACEN)\ + |_PER_FDEFAULT(DMA,SECCTL,WSYNCCLR)\ + |_PER_FDEFAULT(DMA,SECCTL,WSYNCSTAT)\ + |_PER_FDEFAULT(DMA,SECCTL,RSYNCCLR)\ + |_PER_FDEFAULT(DMA,SECCTL,RSYNCSTAT)\ + |_PER_FDEFAULT(DMA,SECCTL,WDROPIE)\ + |_PER_FDEFAULT(DMA,SECCTL,WDROPCOND)\ + |_PER_FDEFAULT(DMA,SECCTL,RDROPIE)\ + |_PER_FDEFAULT(DMA,SECCTL,RDROPCOND)\ + |_PER_FDEFAULT(DMA,SECCTL,BLOCKIE)\ + |_PER_FDEFAULT(DMA,SECCTL,BLOCKCOND)\ + |_PER_FDEFAULT(DMA,SECCTL,LASTIE)\ + |_PER_FDEFAULT(DMA,SECCTL,LASTCOND)\ + |_PER_FDEFAULT(DMA,SECCTL,FRAMEIE)\ + |_PER_FDEFAULT(DMA,SECCTL,FRAMECOND)\ + |_PER_FDEFAULT(DMA,SECCTL,SXIE)\ + |_PER_FDEFAULT(DMA,SECCTL,SXCOND)\ + ) + + #define DMA_SECCTL_RMK(wspol,rspol,fsig,dmacen,wsyncclr,wsyncstat,rsyncclr,\ + rsyncstat,wdropie,wdropcond,rdropie,rdropcond,blockie,blockcond,\ + lastie,lastcond,frameie,framecond,sxie,sxcond) (Uint32)( \ + _PER_FMK(DMA,SECCTL,WSPOL,wspol)\ + |_PER_FMK(DMA,SECCTL,RSPOL,rspol)\ + |_PER_FMK(DMA,SECCTL,FSIG,fsig)\ + |_PER_FMK(DMA,SECCTL,DMACEN,dmacen)\ + |_PER_FMK(DMA,SECCTL,WSYNCCLR,wsyncclr)\ + |_PER_FMK(DMA,SECCTL,WSYNCSTAT,wsyncstat)\ + |_PER_FMK(DMA,SECCTL,RSYNCCLR,rsyncclr)\ + |_PER_FMK(DMA,SECCTL,RSYNCSTAT,rsyncstat)\ + |_PER_FMK(DMA,SECCTL,WDROPIE,wdropie)\ + |_PER_FMK(DMA,SECCTL,WDROPCOND,wdropcond)\ + |_PER_FMK(DMA,SECCTL,RDROPIE,rdropie)\ + |_PER_FMK(DMA,SECCTL,RDROPCOND,rdropcond)\ + |_PER_FMK(DMA,SECCTL,BLOCKIE,blockie)\ + |_PER_FMK(DMA,SECCTL,BLOCKCOND,blockcond)\ + |_PER_FMK(DMA,SECCTL,LASTIE,lastie)\ + |_PER_FMK(DMA,SECCTL,LASTCOND,lastcond)\ + |_PER_FMK(DMA,SECCTL,FRAMEIE,frameie)\ + |_PER_FMK(DMA,SECCTL,FRAMECOND,framecond)\ + |_PER_FMK(DMA,SECCTL,SXIE,sxie)\ + |_PER_FMK(DMA,SECCTL,SXCOND,sxcond)\ + ) +#endif + +#if (!_DMA_COND1) + #define DMA_SECCTL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(DMA,SECCTL,DMACEN)\ + |_PER_FDEFAULT(DMA,SECCTL,WSYNCCLR)\ + |_PER_FDEFAULT(DMA,SECCTL,WSYNCSTAT)\ + |_PER_FDEFAULT(DMA,SECCTL,RSYNCCLR)\ + |_PER_FDEFAULT(DMA,SECCTL,RSYNCSTAT)\ + |_PER_FDEFAULT(DMA,SECCTL,WDROPIE)\ + |_PER_FDEFAULT(DMA,SECCTL,WDROPCOND)\ + |_PER_FDEFAULT(DMA,SECCTL,RDROPIE)\ + |_PER_FDEFAULT(DMA,SECCTL,RDROPCOND)\ + |_PER_FDEFAULT(DMA,SECCTL,BLOCKIE)\ + |_PER_FDEFAULT(DMA,SECCTL,BLOCKCOND)\ + |_PER_FDEFAULT(DMA,SECCTL,LASTIE)\ + |_PER_FDEFAULT(DMA,SECCTL,LASTCOND)\ + |_PER_FDEFAULT(DMA,SECCTL,FRAMEIE)\ + |_PER_FDEFAULT(DMA,SECCTL,FRAMECOND)\ + |_PER_FDEFAULT(DMA,SECCTL,SXIE)\ + |_PER_FDEFAULT(DMA,SECCTL,SXCOND)\ + ) + + #define DMA_SECCTL_RMK(dmacen,wsyncclr,wsyncstat,rsyncclr,\ + rsyncstat,wdropie,wdropcond,rdropie,rdropcond,blockie,blockcond,\ + lastie,lastcond,frameie,framecond,sxie,sxcond) (Uint32)( \ + _PER_FMK(DMA,SECCTL,DMACEN,dmacen)\ + |_PER_FMK(DMA,SECCTL,WSYNCCLR,wsyncclr)\ + |_PER_FMK(DMA,SECCTL,WSYNCSTAT,wsyncstat)\ + |_PER_FMK(DMA,SECCTL,RSYNCCLR,rsyncclr)\ + |_PER_FMK(DMA,SECCTL,RSYNCSTAT,rsyncstat)\ + |_PER_FMK(DMA,SECCTL,WDROPIE,wdropie)\ + |_PER_FMK(DMA,SECCTL,WDROPCOND,wdropcond)\ + |_PER_FMK(DMA,SECCTL,RDROPIE,rdropie)\ + |_PER_FMK(DMA,SECCTL,RDROPCOND,rdropcond)\ + |_PER_FMK(DMA,SECCTL,BLOCKIE,blockie)\ + |_PER_FMK(DMA,SECCTL,BLOCKCOND,blockcond)\ + |_PER_FMK(DMA,SECCTL,LASTIE,lastie)\ + |_PER_FMK(DMA,SECCTL,LASTCOND,lastcond)\ + |_PER_FMK(DMA,SECCTL,FRAMEIE,frameie)\ + |_PER_FMK(DMA,SECCTL,FRAMECOND,framecond)\ + |_PER_FMK(DMA,SECCTL,SXIE,sxie)\ + |_PER_FMK(DMA,SECCTL,SXCOND,sxcond)\ + ) +#endif + + #define _DMA_SECCTL_COND_MASK (\ + _DMA_SECCTL_WDROPCOND_MASK\ + |_DMA_SECCTL_RDROPCOND_MASK\ + |_DMA_SECCTL_BLOCKCOND_MASK\ + |_DMA_SECCTL_LASTCOND_MASK\ + |_DMA_SECCTL_FRAMECOND_MASK\ + |_DMA_SECCTL_SXCOND_MASK\ + ) + + #define _DMA_SECCTL_IE_MASK (\ + _DMA_SECCTL_WDROPIE_MASK\ + |_DMA_SECCTL_RDROPIE_MASK\ + |_DMA_SECCTL_BLOCKIE_MASK\ + |_DMA_SECCTL_LASTIE_MASK\ + |_DMA_SECCTL_FRAMEIE_MASK\ + |_DMA_SECCTL_SXIE_MASK\ + ) + + #define _DMA_SECCTL_STAT_MASK (\ + _DMA_SECCTL_WSYNCSTAT_MASK\ + |_DMA_SECCTL_RSYNCSTAT_MASK\ + ) + + #define _DMA_SECCTL_CLR_MASK (\ + _DMA_SECCTL_WSYNCCLR_MASK\ + |_DMA_SECCTL_RSYNCCLR_MASK\ + ) + + #define _DMA_SECCTL_FGET(N,FIELD)\ + _PER_FGET(_DMA_SECCTL##N##_ADDR,DMA,SECCTL,##FIELD) + + #define _DMA_SECCTL_FSET(N,FIELD,field)\ + _PER_RAOI(_DMA_SECCTL##N##_ADDR,DMA,SECCTL,\ + (0xFFFF0AAA&~_DMA_SECCTL_##FIELD##_MASK),\ + (0x00000555&~_DMA_SECCTL_##FIELD##_MASK)\ + |_PER_FMK(DMA,SECCTL,##FIELD,field),\ + 0x00000000\ + ) + + #define _DMA_SECCTL_FSETS(N,FIELD,SYM)\ + _PER_RAOI(_DMA_SECCTL##N##_ADDR,DMA,SECCTL,\ + (0xFFFF0AAA&~_DMA_SECCTL_##FIELD##_MASK),\ + (0x00000555&~_DMA_SECCTL_##FIELD##_MASK)\ + |_PER_FMKS(DMA,SECCTL,##FIELD,##SYM),\ + 0x00000000\ + ) + + #define _DMA_SECCTL0_FGET(FIELD) _DMA_SECCTL_FGET(0,##FIELD) + #define _DMA_SECCTL1_FGET(FIELD) _DMA_SECCTL_FGET(1,##FIELD) + #define _DMA_SECCTL2_FGET(FIELD) _DMA_SECCTL_FGET(2,##FIELD) + #define _DMA_SECCTL3_FGET(FIELD) _DMA_SECCTL_FGET(3,##FIELD) + + #define _DMA_SECCTL0_FSET(FIELD,f) _DMA_SECCTL_FSET(0,##FIELD,f) + #define _DMA_SECCTL1_FSET(FIELD,f) _DMA_SECCTL_FSET(1,##FIELD,f) + #define _DMA_SECCTL2_FSET(FIELD,f) _DMA_SECCTL_FSET(2,##FIELD,f) + #define _DMA_SECCTL3_FSET(FIELD,f) _DMA_SECCTL_FSET(3,##FIELD,f) + + #define _DMA_SECCTL0_FSETS(FIELD,SYM) _DMA_SECCTL_FSETS(0,##FIELD,##SYM) + #define _DMA_SECCTL1_FSETS(FIELD,SYM) _DMA_SECCTL_FSETS(1,##FIELD,##SYM) + #define _DMA_SECCTL2_FSETS(FIELD,SYM) _DMA_SECCTL_FSETS(2,##FIELD,##SYM) + #define _DMA_SECCTL3_FSETS(FIELD,SYM) _DMA_SECCTL_FSETS(3,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | S R C | +* |___________________| +* +* SRC0 - channel src address register 0 +* SRC1 - channel src address register 1 +* SRC2 - channel src address register 2 +* SRC3 - channel src address register 3 +* +* FIELDS (msb -> lsb) +* (rw) SRC +* +\******************************************************************************/ + #define _DMA_SRC_OFFSET 4 + + #define _DMA_SRC0_ADDR 0x01840010u + #define _DMA_SRC1_ADDR 0x01840050u + #define _DMA_SRC2_ADDR 0x01840014u + #define _DMA_SRC3_ADDR 0x01840054u + + #define _DMA_SRC_SRC_MASK 0xFFFFFFFFu + #define _DMA_SRC_SRC_SHIFT 0x00000000u + #define DMA_SRC_SRC_DEFAULT 0x00000000u + #define DMA_SRC_SRC_OF(x) _VALUEOF(x) + + #define DMA_SRC_OF(x) _VALUEOF(x) + + #define DMA_SRC_DEFAULT (Uint32)( \ + _PER_FDEFAULT(DMA,SRC,SRC) \ + ) + + #define DMA_SRC_RMK(src) (Uint32)( \ + _PER_FMK(DMA,SRC,SRC,src) \ + ) + + #define _DMA_SRC_FGET(N,FIELD)\ + _PER_FGET(_DMA_SRC##N##_ADDR,DMA,SRC,##FIELD) + + #define _DMA_SRC_FSET(N,FIELD,field)\ + _PER_FSET(_DMA_SRC##N##_ADDR,DMA,SRC,##FIELD,field) + + #define _DMA_SRC_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_DMA_SRC##N##_ADDR,DMA,SRC,##FIELD,##SYM) + + #define _DMA_SRC0_FGET(FIELD) _DMA_SRC_FGET(0,##FIELD) + #define _DMA_SRC1_FGET(FIELD) _DMA_SRC_FGET(1,##FIELD) + #define _DMA_SRC2_FGET(FIELD) _DMA_SRC_FGET(2,##FIELD) + #define _DMA_SRC3_FGET(FIELD) _DMA_SRC_FGET(3,##FIELD) + + #define _DMA_SRC0_FSET(FIELD,f) _DMA_SRC_FSET(0,##FIELD,f) + #define _DMA_SRC1_FSET(FIELD,f) _DMA_SRC_FSET(1,##FIELD,f) + #define _DMA_SRC2_FSET(FIELD,f) _DMA_SRC_FSET(2,##FIELD,f) + #define _DMA_SRC3_FSET(FIELD,f) _DMA_SRC_FSET(3,##FIELD,f) + + #define _DMA_SRC0_FSETS(FIELD,SYM) _DMA_SRC_FSETS(0,##FIELD,##SYM) + #define _DMA_SRC1_FSETS(FIELD,SYM) _DMA_SRC_FSETS(1,##FIELD,##SYM) + #define _DMA_SRC2_FSETS(FIELD,SYM) _DMA_SRC_FSETS(2,##FIELD,##SYM) + #define _DMA_SRC3_FSETS(FIELD,SYM) _DMA_SRC_FSETS(3,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | D S T | +* |___________________| +* +* DST0 - channel destination address register 0 +* DST1 - channel destination address register 1 +* DST2 - channel destination address register 2 +* DST3 - channel destination address register 3 +* +* * - handle based +* +* FIELDS (msb -> lsb) +* (rw) DST +* +\******************************************************************************/ + #define _DMA_DST_OFFSET 6 + + #define _DMA_DST0_ADDR 0x01840018u + #define _DMA_DST1_ADDR 0x01840058u + #define _DMA_DST2_ADDR 0x0184001Cu + #define _DMA_DST3_ADDR 0x0184005Cu + + #define _DMA_DST_DST_MASK 0xFFFFFFFFu + #define _DMA_DST_DST_SHIFT 0x00000000u + #define DMA_DST_DST_DEFAULT 0x00000000u + #define DMA_DST_DST_OF(x) _VALUEOF(x) + + #define DMA_DST_OF(x) _VALUEOF(x) + + #define DMA_DST_DEFAULT (Uint32)( \ + _PER_FDEFAULT(DMA,DST,DST) \ + ) + + #define DMA_DST_RMK(dst) (Uint32)( \ + _PER_FMK(DMA,DST,DST,dst) \ + ) + + #define _DMA_DST_FGET(N,FIELD)\ + _PER_FGET(_DMA_DST##N##_ADDR,DMA,DST,##FIELD) + + #define _DMA_DST_FSET(N,FIELD,field)\ + _PER_FSET(_DMA_DST##N##_ADDR,DMA,DST,##FIELD,field) + + #define _DMA_DST_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_DMA_DST##N##_ADDR,DMA,DST,##FIELD,##SYM) + + #define _DMA_DST0_FGET(FIELD) _DMA_DST_FGET(0,##FIELD) + #define _DMA_DST1_FGET(FIELD) _DMA_DST_FGET(1,##FIELD) + #define _DMA_DST2_FGET(FIELD) _DMA_DST_FGET(2,##FIELD) + #define _DMA_DST3_FGET(FIELD) _DMA_DST_FGET(3,##FIELD) + + #define _DMA_DST0_FSET(FIELD,f) _DMA_DST_FSET(0,##FIELD,f) + #define _DMA_DST1_FSET(FIELD,f) _DMA_DST_FSET(1,##FIELD,f) + #define _DMA_DST2_FSET(FIELD,f) _DMA_DST_FSET(2,##FIELD,f) + #define _DMA_DST3_FSET(FIELD,f) _DMA_DST_FSET(3,##FIELD,f) + + #define _DMA_DST0_FSETS(FIELD,SYM) _DMA_DST_FSETS(0,##FIELD,##SYM) + #define _DMA_DST1_FSETS(FIELD,SYM) _DMA_DST_FSETS(1,##FIELD,##SYM) + #define _DMA_DST2_FSETS(FIELD,SYM) _DMA_DST_FSETS(2,##FIELD,##SYM) + #define _DMA_DST3_FSETS(FIELD,SYM) _DMA_DST_FSETS(3,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | X F R C N T | +* |___________________| +* +* XFRCNT0 - channel transfer count register 0 +* XFRCNT1 - channel transfer count register 1 +* XFRCNT2 - channel transfer count register 2 +* XFRCNT3 - channel transfer count register 3 +* +* * - handle based +* +* FIELDS (msb -> lsb) +* (rw) FRMCNT +* (rw) ELECNT +* +\******************************************************************************/ + #define _DMA_XFRCNT_OFFSET 8 + + #define _DMA_XFRCNT0_ADDR 0x01840020u + #define _DMA_XFRCNT1_ADDR 0x01840060u + #define _DMA_XFRCNT2_ADDR 0x01840024u + #define _DMA_XFRCNT3_ADDR 0x01840064u + + #define _DMA_XFRCNT_FRMCNT_MASK 0xFFFF0000u + #define _DMA_XFRCNT_FRMCNT_SHIFT 0x00000010u + #define DMA_XFRCNT_FRMCNT_DEFAULT 0x00000000u + #define DMA_XFRCNT_FRMCNT_OF(x) _VALUEOF(x) + + #define _DMA_XFRCNT_ELECNT_MASK 0x0000FFFFu + #define _DMA_XFRCNT_ELECNT_SHIFT 0x00000000u + #define DMA_XFRCNT_ELECNT_DEFAULT 0x00000000u + #define DMA_XFRCNT_ELECNT_OF(x) _VALUEOF(x) + + #define DMA_XFRCNT_OF(x) _VALUEOF(x) + + #define DMA_XFRCNT_DEFAULT (Uint32)( \ + _PER_FDEFAULT(DMA,XFRCNT,FRMCNT) \ + |_PER_FDEFAULT(DMA,XFRCNT,ELECNT) \ + ) + + #define DMA_XFRCNT_RMK(frmcnt,elecnt) (Uint32)( \ + _PER_FMK(DMA,XFRCNT,FRMCNT,frmcnt) \ + |_PER_FMK(DMA,XFRCNT,ELECNT,elecnt) \ + ) + + #define _DMA_XFRCNT_FGET(N,FIELD)\ + _PER_FGET(_DMA_XFRCNT##N##_ADDR,DMA,XFRCNT,##FIELD) + + #define _DMA_XFRCNT_FSET(N,FIELD,field)\ + _PER_FSET(_DMA_XFRCNT##N##_ADDR,DMA,XFRCNT,##FIELD,field) + + #define _DMA_XFRCNT_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_DMA_XFRCNT##N##_ADDR,DMA,XFRCNT,##FIELD,##SYM) + + #define _DMA_XFRCNT0_FGET(FIELD) _DMA_XFRCNT_FGET(0,##FIELD) + #define _DMA_XFRCNT1_FGET(FIELD) _DMA_XFRCNT_FGET(1,##FIELD) + #define _DMA_XFRCNT2_FGET(FIELD) _DMA_XFRCNT_FGET(2,##FIELD) + #define _DMA_XFRCNT3_FGET(FIELD) _DMA_XFRCNT_FGET(3,##FIELD) + + #define _DMA_XFRCNT0_FSET(FIELD,f) _DMA_XFRCNT_FSET(0,##FIELD,f) + #define _DMA_XFRCNT1_FSET(FIELD,f) _DMA_XFRCNT_FSET(1,##FIELD,f) + #define _DMA_XFRCNT2_FSET(FIELD,f) _DMA_XFRCNT_FSET(2,##FIELD,f) + #define _DMA_XFRCNT3_FSET(FIELD,f) _DMA_XFRCNT_FSET(3,##FIELD,f) + + #define _DMA_XFRCNT0_FSETS(FIELD,SYM) _DMA_XFRCNT_FSETS(0,##FIELD,##SYM) + #define _DMA_XFRCNT1_FSETS(FIELD,SYM) _DMA_XFRCNT_FSETS(1,##FIELD,##SYM) + #define _DMA_XFRCNT2_FSETS(FIELD,SYM) _DMA_XFRCNT_FSETS(2,##FIELD,##SYM) + #define _DMA_XFRCNT3_FSETS(FIELD,SYM) _DMA_XFRCNT_FSETS(3,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | G B L C N T | +* |___________________| +* +* GBLCNTA - global count reload register A +* GBLCNTB - global count reload register B +* +* FIELDS (msb -> lsb) +* (rw) FRMCNT +* (rw) ELECNT +* +\******************************************************************************/ + #define _DMA_GBLCNTA_ADDR 0x01840028u + #define _DMA_GBLCNTB_ADDR 0x0184002Cu + + #define _DMA_GBLCNT_FRMCNT_MASK 0xFFFF0000u + #define _DMA_GBLCNT_FRMCNT_SHIFT 0x00000010u + #define DMA_GBLCNT_FRMCNT_DEFAULT 0x00000000u + #define DMA_GBLCNT_FRMCNT_OF(x) _VALUEOF(x) + + #define _DMA_GBLCNT_ELECNT_MASK 0x0000FFFFu + #define _DMA_GBLCNT_ELECNT_SHIFT 0x00000000u + #define DMA_GBLCNT_ELECNT_DEFAULT 0x00000000u + #define DMA_GBLCNT_ELECNT_OF(x) _VALUEOF(x) + + #define DMA_GBLCNT_OF(x) _VALUEOF(x) + + #define DMA_GBLCNT_DEFAULT (Uint32)( \ + _PER_FDEFAULT(DMA,GBLCNT,FRMCNT) \ + |_PER_FDEFAULT(DMA,GBLCNT,ELECNT) \ + ) + + #define DMA_GBLCNT_RMK(frmcnt,elecnt) (Uint32)( \ + _PER_FMK(DMA,GBLCNT,FRMCNT,frmcnt) \ + |_PER_FMK(DMA,GBLCNT,ELECNT,elecnt) \ + ) + + #define _DMA_GBLCNT_FGET(N,FIELD)\ + _PER_FGET(_DMA_GBLCNT##N##_ADDR,DMA,GBLCNT,##FIELD) + + #define _DMA_GBLCNT_FSET(N,FIELD,field)\ + _PER_FSET(_DMA_GBLCNT##N##_ADDR,DMA,GBLCNT,##FIELD,field) + + #define _DMA_GBLCNT_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_DMA_GBLCNT##N##_ADDR,DMA,GBLCNT,##FIELD,##SYM) + + #define _DMA_GBLCNTA_FGET(FIELD) _DMA_GBLCNT_FGET(A,FIELD) + #define _DMA_GBLCNTB_FGET(FIELD) _DMA_GBLCNT_FGET(B,FIELD) + + #define _DMA_GBLCNTA_FSET(FIELD,f) _DMA_GBLCNT_FSET(A,FIELD,f) + #define _DMA_GBLCNTB_FSET(FIELD,f) _DMA_GBLCNT_FSET(B,FIELD,f) + + #define _DMA_GBLCNTA_FSETS(FIELD,SYM) _DMA_GBLCNT_FSETS(A,FIELD,SYM) + #define _DMA_GBLCNTB_FSETS(FIELD,SYM) _DMA_GBLCNT_FSETS(B,FIELD,SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | G B L I D X | +* |___________________| +* +* GBLIDXA - global index register A +* GBLIDXB - global index register B +* +* FIELDS (msb -> lsb) +* (rw) FRMIDX +* (rw) ELEIDX +* +\******************************************************************************/ + #define _DMA_GBLIDXA_ADDR 0x01840030u + #define _DMA_GBLIDXB_ADDR 0x01840034u + + #define _DMA_GBLIDX_FRMIDX_MASK 0xFFFF0000u + #define _DMA_GBLIDX_FRMIDX_SHIFT 0x00000010u + #define DMA_GBLIDX_FRMIDX_DEFAULT 0x00000000u + #define DMA_GBLIDX_FRMIDX_OF(x) _VALUEOF(x) + + #define _DMA_GBLIDX_ELEIDX_MASK 0x0000FFFFu + #define _DMA_GBLIDX_ELEIDX_SHIFT 0x00000000u + #define DMA_GBLIDX_ELEIDX_DEFAULT 0x00000000u + #define DMA_GBLIDX_ELEIDX_OF(x) _VALUEOF(x) + + #define DMA_GBLIDX_OF(x) _VALUEOF(x) + + #define DMA_GBLIDX_DEFAULT (Uint32)( \ + _PER_FDEFAULT(DMA,GBLIDX,FRMIDX) \ + |_PER_FDEFAULT(DMA,GBLIDX,ELEIDX) \ + ) + + #define DMA_GBLIDX_RMK(frmidx,eleidx) (Uint32)( \ + _PER_FMK(DMA,GBLIDX,FRMIDX,frmidx) \ + |_PER_FMK(DMA,GBLIDX,ELEIDX,eleidx) \ + ) + + #define _DMA_GBLIDX_FGET(N,FIELD)\ + _PER_FGET(_DMA_GBLIDX##N##_ADDR,DMA,GBLIDX,##FIELD) + + #define _DMA_GBLIDX_FSET(N,FIELD,field)\ + _PER_FSET(_DMA_GBLIDX##N##_ADDR,DMA,GBLIDX,##FIELD,field) + + #define _DMA_GBLIDX_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_DMA_GBLIDX##N##_ADDR,DMA,GBLIDX,##FIELD,##SYM) + + #define _DMA_GBLIDXA_FGET(FIELD) _DMA_GBLIDX_FGET(A,FIELD) + #define _DMA_GBLIDXB_FGET(FIELD) _DMA_GBLIDX_FGET(B,FIELD) + + #define _DMA_GBLIDXA_FSET(FIELD,f) _DMA_GBLIDX_FSET(A,FIELD,f) + #define _DMA_GBLIDXB_FSET(FIELD,f) _DMA_GBLIDX_FSET(B,FIELD,f) + + #define _DMA_GBLIDXA_FSETS(FIELD,SYM) _DMA_GBLIDX_FSETS(A,FIELD,SYM) + #define _DMA_GBLIDXB_FSETS(FIELD,SYM) _DMA_GBLIDX_FSETS(B,FIELD,SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | G B L A D D R | +* |___________________| +* +* GBLADDRA - global address reload register A +* GBLADDRB - global address reload register B +* GBLADDRC - global address reload register C +* GBLADDRD - global address reload register D +* +* FIELDS (msb -> lsb) +* (rw) GBLADDR +* +\******************************************************************************/ + #define _DMA_GBLADDRA_ADDR 0x01840038u + #define _DMA_GBLADDRB_ADDR 0x0184003Cu + #define _DMA_GBLADDRC_ADDR 0x01840068u + #define _DMA_GBLADDRD_ADDR 0x0184006Cu + + #define _DMA_GBLADDR_GBLADDR_MASK 0xFFFFFFFFu + #define _DMA_GBLADDR_GBLADDR_SHIFT 0x00000000u + #define DMA_GBLADDR_GBLADDR_DEFAULT 0x00000000u + #define DMA_GBLADDR_GBLADDR_OF(x) _VALUEOF(x) + + #define DMA_GBLADDR_OF(x) _VALUEOF(x) + + #define DMA_GBLADDR_DEFAULT (Uint32)( \ + _PER_FDEFAULT(DMA,GBLADDR,GBLADDR) \ + ) + + #define DMA_GBLADDR_RMK(gbladdr) (Uint32)( \ + _PER_FMK(DMA,GBLADDR,GBLADDR,gbladdr) \ + ) + + #define _DMA_GBLADDR_FGET(N,FIELD)\ + _PER_FGET(_DMA_GBLADDR##N##_ADDR,DMA,GBLADDR,##FIELD) + + #define _DMA_GBLADDR_FSET(N,FIELD,field)\ + _PER_FSET(_DMA_GBLADDR##N##_ADDR,DMA,GBLADDR,##FIELD,field) + + #define _DMA_GBLADDR_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_DMA_GBLADDR##N##_ADDR,DMA,GBLADDR,##FIELD,##SYM) + + #define _DMA_GBLADDRA_FGET(FIELD) _DMA_GBLADDR_FGET(A,FIELD) + #define _DMA_GBLADDRB_FGET(FIELD) _DMA_GBLADDR_FGET(B,FIELD) + #define _DMA_GBLADDRC_FGET(FIELD) _DMA_GBLADDR_FGET(C,FIELD) + #define _DMA_GBLADDRD_FGET(FIELD) _DMA_GBLADDR_FGET(D,FIELD) + + #define _DMA_GBLADDRA_FSET(FIELD,f) _DMA_GBLADDR_FSET(A,FIELD,f) + #define _DMA_GBLADDRB_FSET(FIELD,f) _DMA_GBLADDR_FSET(B,FIELD,f) + #define _DMA_GBLADDRC_FSET(FIELD,f) _DMA_GBLADDR_FSET(C,FIELD,f) + #define _DMA_GBLADDRD_FSET(FIELD,f) _DMA_GBLADDR_FSET(D,FIELD,f) + + #define _DMA_GBLADDRA_FSETS(FIELD,SYM) _DMA_GBLADDR_FSETS(A,FIELD,SYM) + #define _DMA_GBLADDRB_FSETS(FIELD,SYM) _DMA_GBLADDR_FSETS(B,FIELD,SYM) + #define _DMA_GBLADDRC_FSETS(FIELD,SYM) _DMA_GBLADDR_FSETS(C,FIELD,SYM) + #define _DMA_GBLADDRD_FSETS(FIELD,SYM) _DMA_GBLADDR_FSETS(D,FIELD,SYM) + + +/*----------------------------------------------------------------------------*/ + +#endif /* DMA_SUPPORT */ +#endif /* _CSL_DMAHAL_H_ */ +/******************************************************************************\ +* End of csl_dmahal.h +\******************************************************************************/ diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_edma.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_edma.h new file mode 100644 index 0000000..c972bd8 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_edma.h @@ -0,0 +1,891 @@ +/******************************************************************************\ +* Copyright (C) 1999-2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_edma.h +* DATE CREATED.. 06/11/1999 +* LAST MODIFIED. 14/9/2005 Modified EDMA_getChannel and EDMA_setEvtPolarity to return +* proper values and can set polarities properly respectively. +* 08/13/2004 Modified tccAllocTable type from static to global fn. +* 08/02/2004 - Adding support for C6418 +* 04/16/2004 Modified tccAllocTable[0] entry to 0. +* 02/09/2004 Removed volatile variable type from EDMA_chain inline fn. +* 06/17/2003 added support for 6712C +* 05/28/2003 added support for 6711C +* 02/15/2002 added EDMA channel events 6713/DM642 - EDMA_map() +* 04/16/2001 +\******************************************************************************/ +#ifndef _CSL_EDMA_H_ +#define _CSL_EDMA_H_ + +#include +#include +#include + + +#if (EDMA_SUPPORT) +/******************************************************************************\ +* scope and inline control macros +\******************************************************************************/ +#ifdef __cplusplus +#define CSLAPI extern "C" far +#else +#define CSLAPI extern far +#endif + +#undef USEDEFS +#undef IDECL +#undef IDEF + +#ifdef _EDMA_MOD_ + #define IDECL CSLAPI + #define USEDEFS + #define IDEF +#else + #ifdef _INLINE + #define IDECL static inline + #define USEDEFS + #define IDEF static inline + #else + #define IDECL CSLAPI + #endif +#endif + + +/******************************************************************************\ +* global macro declarations +\******************************************************************************/ +#define EDMA_CHA_CNT (_EDMA_CHA_CNT) +#define EDMA_TABLE_CNT (_EDMA_LINK_CNT) +#define EDMA_ALLOC_ANY (-1) + +#define EDMA_OPEN_RESET (0x00000001) +#define EDMA_OPEN_ENABLE (0x00000002) + + +#if(CHIP_6201|CHIP_6202|CHIP_6203|CHIP_6204|CHIP_6205|CHIP_6701|C11_SUPPORT) + #define EDMA_CHA_ANY -1 + #define EDMA_CHA_DSPINT 0 + #define EDMA_CHA_TINT0 1 + #define EDMA_CHA_TINT1 2 + #define EDMA_CHA_SDINT 3 + #define EDMA_CHA_EXTINT4 4 + #define EDMA_CHA_EXTINT5 5 + #define EDMA_CHA_EXTINT6 6 + #define EDMA_CHA_EXTINT7 7 + #define EDMA_CHA_TCC8 8 + #define EDMA_CHA_TCC9 9 + #define EDMA_CHA_TCC10 10 + #define EDMA_CHA_TCC11 11 + #define EDMA_CHA_XEVT0 12 + #define EDMA_CHA_REVT0 13 + #define EDMA_CHA_XEVT1 14 + #define EDMA_CHA_REVT1 15 +#endif +#if (CHIP_6711C || CHIP_6712C) + #define EDMA_CHA_GPINT4 4 + #define EDMA_CHA_GPINT5 5 + #define EDMA_CHA_GPINT6 6 + #define EDMA_CHA_GPINT7 7 + #define EDMA_CHA_GPINT2 10 +#endif + +#if (CHIP_6713 | CHIP_DA610 | CHIP_6414 | CHIP_6415 | CHIP_6416 | \ + CHIP_6411 | CHIP_6410 | CHIP_6413 | CHIP_6418) + #define EDMA_CHA_ANY -1 + #define EDMA_CHA_DSPINT 0 + #define EDMA_CHA_TINT0 1 + #define EDMA_CHA_TINT1 2 + #define EDMA_CHA_SDINT 3 + #define EDMA_CHA_EXTINT4 4 + #define EDMA_CHA_GPINT4 4 + #define EDMA_CHA_EXTINT5 5 + #define EDMA_CHA_GPINT5 5 + #define EDMA_CHA_EXTINT6 6 + #define EDMA_CHA_GPINT6 6 + #define EDMA_CHA_EXTINT7 7 + #define EDMA_CHA_GPINT7 7 + #define EDMA_CHA_TCC8 8 + #define EDMA_CHA_GPINT0 8 + #define EDMA_CHA_TCC9 9 + #define EDMA_CHA_GPINT1 9 + #define EDMA_CHA_TCC10 10 + #define EDMA_CHA_GPINT2 10 + #define EDMA_CHA_TCC11 11 + #define EDMA_CHA_GPINT3 11 + #define EDMA_CHA_XEVT0 12 + #define EDMA_CHA_REVT0 13 + #define EDMA_CHA_XEVT1 14 + #define EDMA_CHA_REVT1 15 + +/* Individual mappings for next few events are specified under #ifdefs below. */ + + #define EDMA_CHA_GPINT8 48 + #define EDMA_CHA_GPINT9 49 + #define EDMA_CHA_GPINT10 50 + #define EDMA_CHA_GPINT11 51 + #define EDMA_CHA_GPINT12 52 + #define EDMA_CHA_GPINT13 53 + #define EDMA_CHA_GPINT14 54 + #define EDMA_CHA_GPINT15 55 +#endif + + +/* 3rd MCBSP/ PCI / UTOPIA / VCP / TCP channel numbers for EDMA_open() */ +#if (CHIP_6414 || CHIP_6415 || CHIP_6416 ) + #define EDMA_CHA_XEVT2 17 + #define EDMA_CHA_REVT2 18 + #define EDMA_CHA_TINT2 19 + #define EDMA_CHA_SDINTB 20 + #define EDMA_CHA_PCI 21 + #define EDMA_CHA_VCPREVT 28 + #define EDMA_CHA_VCPXEVT 29 + #define EDMA_CHA_TCPREVT 30 + #define EDMA_CHA_TCPXEVT 31 + #define EDMA_CHA_UREVT 32 + #define EDMA_CHA_UREVT0 32 + #define EDMA_CHA_UREVT1 33 + #define EDMA_CHA_UREVT2 34 + #define EDMA_CHA_UREVT3 35 + #define EDMA_CHA_UREVT4 36 + #define EDMA_CHA_UREVT5 37 + #define EDMA_CHA_UREVT6 38 + #define EDMA_CHA_UREVT7 39 + #define EDMA_CHA_UXEVT 40 + #define EDMA_CHA_UXEVT0 40 + #define EDMA_CHA_UXEVT1 41 + #define EDMA_CHA_UXEVT2 42 + #define EDMA_CHA_UXEVT3 43 + #define EDMA_CHA_UXEVT4 44 + #define EDMA_CHA_UXEVT5 45 + #define EDMA_CHA_UXEVT6 46 + #define EDMA_CHA_UXEVT7 47 +#endif + +/* 2 MCASPs - 2 I2Cs channels */ +#if (CHIP_6713 || CHIP_DA610) + #define EDMA_CHA_AXEVTE0 32 + #define EDMA_CHA_AXEVTO0 33 + #define EDMA_CHA_AXEVT0 34 + #define EDMA_CHA_AREVTE0 35 + #define EDMA_CHA_AREVTO0 36 + #define EDMA_CHA_AREVT0 37 + #define EDMA_CHA_AXEVTE1 38 + #define EDMA_CHA_AXEVTO1 39 + #define EDMA_CHA_AXEVT1 40 + #define EDMA_CHA_AREVTE1 41 + #define EDMA_CHA_AREVTO1 42 + #define EDMA_CHA_AREVT1 43 + #define EDMA_CHA_ICREVT0 44 + #define EDMA_CHA_ICXEVT0 45 + #define EDMA_CHA_ICREVT1 46 + #define EDMA_CHA_ICXEVT1 47 +#endif + +#if (CHIP_6410 || CHIP_6413| CHIP_6418) + #define EDMA_CHA_TINT2 19 + + #if (CHIP_6418) + #define EDMA_CHA_VCPREVT0 28 + #define EDMA_CHA_VCPXEVT0 29 + #endif + + #define EDMA_CHA_AXEVTE0 32 + #define EDMA_CHA_AXEVTO0 33 + #define EDMA_CHA_AXEVT0 34 + #define EDMA_CHA_AREVTE0 35 + #define EDMA_CHA_AREVTO0 36 + #define EDMA_CHA_AREVT0 37 + #define EDMA_CHA_AXEVTE1 38 + #define EDMA_CHA_AXEVTO1 39 + #define EDMA_CHA_AXEVT1 40 + #define EDMA_CHA_AREVTE1 41 + #define EDMA_CHA_AREVTO1 42 + #define EDMA_CHA_AREVT1 43 + #define EDMA_CHA_ICREVT0 44 + #define EDMA_CHA_ICXEVT0 45 + #define EDMA_CHA_ICREVT1 46 + #define EDMA_CHA_ICXEVT1 47 +#endif + +#if (CHIP_DM642 || CHIP_DM641 || CHIP_DM640 || CHIP_6412) + #define EDMA_CHA_ANY -1 + + #if !(CHIP_DM640) + #define EDMA_CHA_DSPINT 0 + #endif + + #define EDMA_CHA_TINT0 1 + #define EDMA_CHA_TINT1 2 + #define EDMA_CHA_SDINT 3 + #define EDMA_CHA_EXTINT4 4 + #define EDMA_CHA_GPINT4 4 + #define EDMA_CHA_EXTINT5 5 + #define EDMA_CHA_GPINT5 5 + #define EDMA_CHA_EXTINT6 6 + #define EDMA_CHA_GPINT6 6 + #define EDMA_CHA_EXTINT7 7 + #define EDMA_CHA_GPINT7 7 + #define EDMA_CHA_GPINT0 8 + #define EDMA_CHA_TCC8 8 + #define EDMA_CHA_GPINT1 9 + #define EDMA_CHA_TCC9 9 + #define EDMA_CHA_GPINT2 10 + #define EDMA_CHA_TCC10 10 + #define EDMA_CHA_GPINT3 11 + #define EDMA_CHA_TCC11 11 + #define EDMA_CHA_XEVT0 12 + #define EDMA_CHA_REVT0 13 + #define EDMA_CHA_XEVT1 14 + #define EDMA_CHA_REVT1 15 + +/* Note: EDMA_CHA_TCC8, EDMA_CHA_TCC9, EDMA_CHA_TCC10 and EDMA_CHA_TCC11 are + NOT defined here, but they are included here for C64x consistency purposes */ + + #if (CHIP_DM642 | CHIP_DM641 | CHIP_DM640) + #define EDMA_CHA_VP0EVTYA 16 + #define EDMA_CHA_VP0EVTUA 17 + #define EDMA_CHA_VP0EVTVA 18 + #endif + + #define EDMA_CHA_TINT2 19 + + #if (CHIP_DM642) + #define EDMA_CHA_VP0EVTYB 24 + #define EDMA_CHA_VP0EVTUB 25 + #define EDMA_CHA_VP0EVTVB 26 + #endif + + #if !(CHIP_6412) + #define EDMA_CHA_AXEVTE0 32 + #define EDMA_CHA_AXEVTO0 33 + #define EDMA_CHA_AXEVT0 34 + #define EDMA_CHA_AREVTE0 35 + #define EDMA_CHA_AREVTO0 36 + #define EDMA_CHA_AREVT0 37 + #endif + + #if (CHIP_DM642) + #define EDMA_CHA_VP1EVTYB 38 + #define EDMA_CHA_VP1EVTUB 39 + #define EDMA_CHA_VP1EVTVB 40 + #define EDMA_CHA_VP2EVTYB 41 + #define EDMA_CHA_VP2EVTUB 42 + #define EDMA_CHA_VP2EVTVB 43 + #endif + + #define EDMA_CHA_ICREVT0 44 + #define EDMA_CHA_ICXEVT0 45 + + #define EDMA_CHA_GPINT8 48 + #define EDMA_CHA_GPINT9 49 + #define EDMA_CHA_GPINT10 50 + #define EDMA_CHA_GPINT11 51 + #define EDMA_CHA_GPINT12 52 + #define EDMA_CHA_GPINT13 53 + #define EDMA_CHA_GPINT14 54 + #define EDMA_CHA_GPINT15 55 + + + #if (CHIP_DM642 | CHIP_DM641) + #define EDMA_CHA_VP1EVTYA 56 + #define EDMA_CHA_VP1EVTUA 57 + #define EDMA_CHA_VP1EVTVA 58 + #endif + + #if (CHIP_DM642) + #define EDMA_CHA_VP2EVTYA 59 + #define EDMA_CHA_VP2EVTUA 60 + #define EDMA_CHA_VP2EVTVA 61 + #endif + +#endif + +#define _EDMA_TYPE_C (0x80000000) +#define _EDMA_TYPE_T (0x40000000) +#define _EDMA_TYPE_Q (0x20000000) +#define _EDMA_TYPE_S (0x10000000) + + +#define _EDMA_MK_HANDLE(base,index,flags) (EDMA_Handle)(\ + ((base)&0x0000FFFF)|(((index)<<16)&0x00FF0000)|((flags)&0xFF000000)\ +) + +#define EDMA_HQDMA _EDMA_MK_HANDLE(0x00000000,0,_EDMA_TYPE_Q) +#define EDMA_HQSDMA _EDMA_MK_HANDLE(0x00000000,0,_EDMA_TYPE_S) +#define EDMA_HINV _EDMA_MK_HANDLE(0x00000000,0,0) + +#define EDMA_HNULL _EDMA_MK_HANDLE(_EDMA_NULL_PARAM,0,_EDMA_TYPE_T) +#define NULL_FUNC 0 + +/* Priority Queues */ +#define EDMA_Q0 0 +#define EDMA_Q1 1 +#define EDMA_Q2 2 +#define EDMA_Q3 3 + +/* Event Polarity */ +#define EDMA_EVT_LOWHIGH 0 +#define EDMA_EVT_HIGHLOW 1 + +/* Chaining Flag */ +#define EDMA_TCC_SET 1 +#define EDMA_ATCC_SET 1 + +/******************************************************************************\ +* global typedef declarations +\******************************************************************************/ +typedef Uint32 EDMA_Handle; + +typedef struct { + Uint32 opt; + Uint32 src; + Uint32 cnt; + Uint32 dst; + Uint32 idx; + Uint32 rld; +} EDMA_Config; + +typedef void (*EDMA_IntHandler)(int tccNum); + +/******************************************************************************\ +* global variable declarations +\******************************************************************************/ +#define EDMA_hNull EDMA_HNULL + +extern far Uint8 tccAllocTable[64]; + +/******************************************************************************\ +* global function declarations +\******************************************************************************/ +CSLAPI void EDMA_reset(EDMA_Handle hEdma); +CSLAPI void EDMA_resetAll(); + +CSLAPI EDMA_Handle EDMA_open(int chaNum, Uint32 flags); +CSLAPI void EDMA_close(EDMA_Handle hEdma); +CSLAPI EDMA_Handle EDMA_allocTable(int tableNum); +CSLAPI void EDMA_freeTable(EDMA_Handle hEdma); + +CSLAPI int EDMA_allocTableEx(int cnt, EDMA_Handle *array); +CSLAPI void EDMA_freeTableEx(int cnt, EDMA_Handle *array); + +CSLAPI void EDMA_clearPram(Uint32 val); + +CSLAPI int EDMA_intAlloc(int tcc); +CSLAPI void EDMA_intFree(int tcc); +/* 6713? */ + +#if (CHIP_6713 || CHIP_DA610 || CHIP_6711C || CHIP_6712C) +CSLAPI int EDMA_map(int eventNum,int chaNum); +#endif + +CSLAPI EDMA_IntHandler EDMA_intHook(int tccNum, EDMA_IntHandler funcAddr); +CSLAPI void EDMA_intDefaultHandler(int tccNum); +CSLAPI void EDMA_intDispatcher(); + +/******************************************************************************\ +* inline function declarations +\******************************************************************************/ +IDECL Uint32 EDMA_getScratchAddr(); +IDECL Uint32 EDMA_getScratchSize(); +IDECL Uint32 EDMA_getPriQStatus(); +#if (C64_SUPPORT) +IDECL void EDMA_setPriQLength(Uint32 priNum, Uint32 length); +IDECL void EDMA_resetPriQLength(Uint32 priNum); +#endif + +IDECL void EDMA_enableChannel(EDMA_Handle hEdma); +IDECL void EDMA_disableChannel(EDMA_Handle hEdma); +IDECL void EDMA_setChannel(EDMA_Handle hEdma); +IDECL Uint32 EDMA_getChannel(EDMA_Handle hEdma); +IDECL void EDMA_clearChannel(EDMA_Handle hEdma); +#if (C64_SUPPORT) +IDECL void EDMA_setEvtPolarity(EDMA_Handle hEdma,int polarity); +#endif +IDECL Uint32 EDMA_getTableAddress(EDMA_Handle hEdma); + +IDECL void EDMA_intEnable(Uint32 tccIntNum); +IDECL void EDMA_intDisable(Uint32 tccIntNum); +IDECL void EDMA_intClear(Uint32 tccIntNum); +IDECL Uint32 EDMA_intTest(Uint32 tccIntNum); +IDECL void EDMA_intReset(Uint32 tccIntNum); +IDECL void EDMA_intResetAll(); + +IDECL void EDMA_link(EDMA_Handle parent, EDMA_Handle child); + +IDECL void EDMA_config(EDMA_Handle hEdma, EDMA_Config *config); +IDECL void EDMA_configArgs(EDMA_Handle hEdma, Uint32 opt, Uint32 src, + Uint32 cnt, Uint32 dst, Uint32 idx, Uint32 rld); +IDECL void EDMA_getConfig(EDMA_Handle hEdma, EDMA_Config *config); + +IDECL void EDMA_qdmaConfig(EDMA_Config *config); +IDECL void EDMA_qdmaConfigArgs(Uint32 opt, Uint32 src, Uint32 cnt, Uint32 dst, + Uint32 idx); +IDECL void EDMA_qdmaGetConfig(EDMA_Config *config); + +IDECL void EDMA_enableChaining(EDMA_Handle hEdma); +IDECL void EDMA_disableChaining(EDMA_Handle hEdma); +IDECL void EDMA_chain(EDMA_Handle parent, EDMA_Handle nextChannel,int tccflag, int atccflag); + +/******************************************************************************\ +* inline function definitions +\******************************************************************************/ +#ifdef USEDEFS +/*----------------------------------------------------------------------------*/ +IDEF Uint32 EDMA_getScratchAddr() { + return (Uint32)_EDMA_SCRATCH_START; +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 EDMA_getScratchSize() { + return (Uint32)_EDMA_SCRATCH_SIZE; +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 EDMA_getPriQStatus() { + return (Uint32)EDMA_RGET(PQSR); +} +/*----------------------------------------------------------------------------*/ +#if (C64_SUPPORT) +IDEF void EDMA_setPriQLength(Uint32 priNum, Uint32 length) { + if (priNum == 0x0) { + EDMA_RSET(PQAR0,(0x00000007 & length)); + } else { + if (priNum == 0x1) { + EDMA_RSET(PQAR1,(0x00000007 & length)); + }else { + if (priNum == 0x2) { + EDMA_RSET(PQAR2,(0x00000007 & length)); + } else { + if (priNum == 0x3) { + EDMA_RSET(PQAR3,(0x00000007 & length)); + } + } + } + } +} +/*----------------------------------------------------------------------------*/ + +IDEF void EDMA_resetPriQLength(Uint32 priNum) { + if (priNum == 0x0) { + EDMA_FSET(PQAR0,PQA,EDMA_PQAR0_PQA_DEFAULT); + } else { + if (priNum == 0x1) { + EDMA_FSET(PQAR1,PQA,EDMA_PQAR1_PQA_DEFAULT); + } else { + if (priNum == 0x2) { + EDMA_FSET(PQAR2,PQA,EDMA_PQAR2_PQA_DEFAULT); + }else { + if (priNum == 0x3) { + EDMA_FSET(PQAR3,PQA,EDMA_PQAR3_PQA_DEFAULT); + } + } + } + } +} +#endif +/*----------------------------------------------------------------------------*/ +IDEF void EDMA_enableChannel(EDMA_Handle hEdma) { + + int gie; + int chaNum = (hEdma & 0x00FF0000)>>16; + + gie = IRQ_globalDisable(); + #if (C64_SUPPORT) + if (chaNum < 32) EDMA_RSET(EERL,EDMA_RGET(EERL) | (1<>16; + + gie = IRQ_globalDisable(); + #if (C64_SUPPORT) + if (chaNum < 32) EDMA_RSET(CCERL,EDMA_RGET(CCERL) | (1<>16; + int gie; + + gie = IRQ_globalDisable(); + + if (tccflag) { + #if (C64_SUPPORT) /* SET TCCM and TCC fields */ + if (TccNum < 16) { tccm = 0 ; tcc = TccNum;} + else { + if ( TccNum > 15 && TccNum < 32 ) { tccm = 1 ; tcc = TccNum-16;} + else { + if ( TccNum > 31 && TccNum < 48 ) { tccm = 2 ; tcc = TccNum-32;} + else { /* channel > 47 */ + tccm = 3 ; tcc = TccNum-48; + } + } + } + EDMA_FSETH(parent,OPT,TCCM,tccm); + EDMA_FSETH(parent,OPT,TCC,tcc); + EDMA_FSETH(parent,OPT,TCINT,1); + #else + EDMA_FSETH(parent,OPT,TCC,TccNum); + EDMA_FSETH(parent,OPT,TCINT,1); + #endif +} +/* ATCC */ +if (atccflag) { + #if C64_SUPPORT + EDMA_FSETH(parent,OPT,ATCC,TccNum); + EDMA_FSETH(parent,OPT,ATCINT,1); + #endif +} + tccAllocTable[TccNum] = 1; + IRQ_globalRestore(gie); +} +/*----------------------------------------------------------------------------*/ +IDEF void EDMA_disableChannel(EDMA_Handle hEdma) { + + int chaNum = (hEdma & 0x00FF0000)>>16; + int gie; + + gie = IRQ_globalDisable(); + + #if (C64_SUPPORT) + if (chaNum < 32) EDMA_RSET(EERL,EDMA_RGET(EERL) & ~(1<>16; + int gie; + + gie = IRQ_globalDisable(); + #if (C64_SUPPORT) + if (chaNum < 32) EDMA_RSET(CCERL,EDMA_RGET(CCERL) & ~(1<>16; + + #if (C64_SUPPORT) + if (chaNum < 32) EDMA_RSET(ESRL,1<>16; + + #if (C64_SUPPORT) + if (chaNum < 32) return (Uint32)(((EDMA_RGET(ERL) >> chaNum) & 1)==1); + else return (Uint32)(((EDMA_RGET(ERH) >> (chaNum-32)) & 1)==1); + + #else + return (Uint32)(((EDMA_RGET(ER) >>chaNum) & 1)==1); + #endif +} +/*----------------------------------------------------------------------------*/ +IDEF void EDMA_clearChannel(EDMA_Handle hEdma) { + + int chaNum = (hEdma & 0x00FF0000)>>16; + + #if (C64_SUPPORT) + if (chaNum < 32) EDMA_RSET(ECRL,1<>16; + + #if (C64_SUPPORT) + if (chaNum < 32) EDMA_RSET(EPRL,(polarity<opt; + x1 = config->src; + x2 = config->cnt; + x3 = config->dst; + x4 = config->idx; + x5 = config->rld; + + base = (volatile Uint32 *)((hEdma&0x0000FFFF)+_EDMA_PRAM_START); + base[_EDMA_OPT_OFFSET] = 0x00000000; + base[_EDMA_SRC_OFFSET] = x1; + base[_EDMA_CNT_OFFSET] = x2; + base[_EDMA_DST_OFFSET] = x3; + base[_EDMA_IDX_OFFSET] = x4; + base[_EDMA_RLD_OFFSET] = x5; + base[_EDMA_OPT_OFFSET] = x0; + IRQ_globalRestore(gie); + } +} +/*----------------------------------------------------------------------------*/ +IDEF void EDMA_configArgs(EDMA_Handle hEdma, Uint32 opt, Uint32 src, + Uint32 cnt, Uint32 dst, Uint32 idx, Uint32 rld) { + + Uint32 gie; + volatile Uint32 *base; + /* Test if QDMA handle was passed with CCS 1.2 */ + if ( hEdma == (0x20000000) || hEdma == (0x10000000)) { + EDMA_qdmaConfigArgs(opt, src, cnt, dst, idx); + }else{ + gie = IRQ_globalDisable(); + base = (volatile Uint32*)((hEdma&0x0000FFFF)+_EDMA_PRAM_START); + base[_EDMA_OPT_OFFSET] = 0x00000000; + base[_EDMA_SRC_OFFSET] = src; + base[_EDMA_CNT_OFFSET] = cnt; + base[_EDMA_DST_OFFSET] = dst; + base[_EDMA_IDX_OFFSET] = idx; + base[_EDMA_RLD_OFFSET] = rld; + base[_EDMA_OPT_OFFSET] = opt; + IRQ_globalRestore(gie); + } +} +/*----------------------------------------------------------------------------*/ +IDEF void EDMA_getConfig(EDMA_Handle hEdma, EDMA_Config *config) { + + Uint32 gie; + volatile Uint32 *base; + register Uint32 x0,x1,x2,x3,x4,x5; + + gie = IRQ_globalDisable(); + + base = (volatile Uint32 *)((hEdma&0x0000FFFF)+_EDMA_PRAM_START); + x0 = base[_EDMA_OPT_OFFSET]; + x1 = base[_EDMA_SRC_OFFSET]; + x2 = base[_EDMA_CNT_OFFSET]; + x3 = base[_EDMA_DST_OFFSET]; + x4 = base[_EDMA_IDX_OFFSET]; + x5 = base[_EDMA_RLD_OFFSET]; + + config->opt = x0; + config->src = x1; + config->cnt = x2; + config->dst = x3; + config->idx = x4; + config->rld = x5; + + IRQ_globalRestore(gie); +} +/*----------------------------------------------------------------------------*/ +IDEF void EDMA_qdmaConfig(EDMA_Config *config) { + + Uint32 gie; + volatile Uint32 *base; + register Uint32 x0,x1,x2,x3,x4; + + gie = IRQ_globalDisable(); + + x0 = config->opt; + x1 = config->src; + x2 = config->cnt; + x3 = config->dst; + x4 = config->idx; + + base = (volatile Uint32 *)(_EDMA_QOPT_ADDR); + base[_EDMA_QSRC_OFFSET] = x1; + base[_EDMA_QCNT_OFFSET] = x2; + base[_EDMA_QDST_OFFSET] = x3; + base[_EDMA_QIDX_OFFSET] = x4; + base[_EDMA_QSOPT_OFFSET] = x0; + + IRQ_globalRestore(gie); +} +/*----------------------------------------------------------------------------*/ +IDEF void EDMA_qdmaConfigArgs(Uint32 opt, Uint32 src, Uint32 cnt, Uint32 dst, + Uint32 idx) { + + Uint32 gie; + volatile Uint32 *base; + + gie = IRQ_globalDisable(); + + base = (volatile Uint32*)(_EDMA_QOPT_ADDR); + base[_EDMA_QSRC_OFFSET] = src; + base[_EDMA_QCNT_OFFSET] = cnt; + base[_EDMA_QDST_OFFSET] = dst; + base[_EDMA_QIDX_OFFSET] = idx; + base[_EDMA_QSOPT_OFFSET] = opt; + + IRQ_globalRestore(gie); +} +/*----------------------------------------------------------------------------*/ +IDEF void EDMA_qdmaGetConfig(EDMA_Config *config) { + + Uint32 gie; + volatile Uint32 *base; + volatile EDMA_Config* cfg = (volatile EDMA_Config*)config; + register Uint32 x0,x1,x2,x3,x4; + + gie = IRQ_globalDisable(); + + base = (volatile Uint32 *)(_EDMA_QOPT_ADDR); + x0 = base[_EDMA_QOPT_OFFSET]; + x1 = base[_EDMA_QSRC_OFFSET]; + x2 = base[_EDMA_QCNT_OFFSET]; + x3 = base[_EDMA_QDST_OFFSET]; + x4 = base[_EDMA_QIDX_OFFSET]; + + cfg->opt = x0; + cfg->src = x1; + cfg->cnt = x2; + cfg->dst = x3; + cfg->idx = x4; + cfg->rld = 0x00000000; + + IRQ_globalRestore(gie); +} +/*----------------------------------------------------------------------------*/ +#endif /* USEDEFS */ + + +#endif /* EDMA_SUPPORT */ +#endif /* _CSL_EDMA_H_ */ +/******************************************************************************\ +* End of csl_edma.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_edmahal.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_edmahal.h new file mode 100644 index 0000000..de0d763 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_edmahal.h @@ -0,0 +1,2226 @@ +/*****************************************************************************\ +* Copyright (C) 1999-2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_edmahal.h +* DATE CREATED.. 12 Jun 1999 +* LAST MODIFIED. 02 Aug 2004 Adding support for C6418 +* 17 Jun 2003 6712C +* 28 May 2003 6711C +* 22 Feb 2002 DM642 +*------------------------------------------------------------------------------ +* REGISTERS/PARAMETERS +* +* OPT - options parameter +* SRC - source address parameter +* CNT - transfer count parameter +* DST - destination address parameter +* IDX - index parameter +* RLD - count reload + link parameter +* QOPT - QDMA options register +* QSRC - QDMA source address register +* QCNT - QDMA transfer count register +* QDST - QDMA destination address register +* QIDX - QDMA index register +* QSOPT - QDMA options pseudo register +* QSSRC - QDMA source address pseudo register +* QSCNT - QDMA transfer count pseudo register +* QSDST - QDMA destination address pseudo register +* QSIDX - QDMA index pseudo register +* PQSR - priority queue status register +* PQAR0 - priority queue allocation register 0 +* PQAR1 - priority queue allocation register 1 +* PQAR2 - priority queue allocation register 2 +* PQAR3 - priority queue allocation register 3 +* CIPR - channel interrupt pending register +* CIPRL - channel interrupt pending register, low half (1) +* CIPRH - channel interrupt pending register, high half (1) +* CIER - channel interrupt enable register +* CIERL - channel interrupt enable register, low half (1) +* CIERH - channel interrupt enable register, high half (1) +* CCER - channel chain enable register +* CCERL - channel chain enable register, low half (1) +* CCERH - channel chain enable register, high half (1) +* ER - event register +* ERL - event register, low half (1) +* ERH - event register, high half (1) +* EER - event enable register +* EERL - event enable register, low half (1) +* EERH - event enable register, high half (1) +* EPRL - event polarity register, low half (1) +* EPRH - event polarity register, high half (1) +* ECR - event clear register +* ECRL - event clear register, low half (1) +* ECRH - event clear register, high half (1) +* ESR - event set register +* ESRL - event set register, low half (1) +* ESRH - event set register, high half (1) +* +* +* CHIP_6713, CHIP_DA610, CHIP_6711C and CHIP_6712C +* ESEL0 - event selection register 0 (2) +* ESEL1 - event selection register 1 (2) +* ESEL2 - event selection register 2 (2) (3) +* ESEL3 - event selection register 3 (2) +* +* (1) - only supported on C64x devices +* (2) - only supported on C6713, DA610, 6711C and 6712C +* (3) - the whole register is reserved +\******************************************************************************/ +#ifndef _CSL_EDMAHAL_H +#define _CSL_EDMAHAL_H_ + +#include +#include + +#if (EDMA_SUPPORT) +/******************************************************************************\ +* MISC section +\******************************************************************************/ + +#if (CHIP_6414 | CHIP_6415 | CHIP_6416 | CHIP_6411 ) + #define _EDMA_CHA_CNT 64 + #define _EDMA_BASE_PRAM 0x01A00000u + #define _EDMA_PRAM_START _EDMA_BASE_PRAM + #define _EDMA_PRAM_SIZE 0x00000800u + #define _EDMA_PRAM_ERASE 0x00000600u +#endif + +#if (CHIP_DM642 | CHIP_DM641 | CHIP_DM640 | CHIP_6412 | CHIP_6410 | CHIP_6413 | CHIP_6418) + #define _EDMA_CHA_CNT 64 + #define _EDMA_BASE_PRAM 0x01A00000u + #define _EDMA_PRAM_START _EDMA_BASE_PRAM + #define _EDMA_PRAM_SIZE 0x00001400u + #define _EDMA_PRAM_ERASE 0x00000600u +#endif + +#if (CHIP_6211 | CHIP_6711 | CHIP_6712 | CHIP_6713 | CHIP_DA610 | CHIP_6711C | CHIP_6712C) + #define _EDMA_CHA_CNT 16 + #define _EDMA_BASE_PRAM 0x01A00000u + #define _EDMA_PRAM_START _EDMA_BASE_PRAM + #define _EDMA_PRAM_SIZE 0x00000800u + #define _EDMA_PRAM_ERASE 0x00000180u +#endif + + #define _EDMA_ENTRY_SIZE 0x00000018u + #define _EDMA_NULL_PARAM (_EDMA_PRAM_START+_EDMA_ENTRY_SIZE*_EDMA_CHA_CNT) + #define _EDMA_RSVD_PARAM (_EDMA_NULL_PARAM+_EDMA_ENTRY_SIZE) + #define _EDMA_LINK_START (_EDMA_RSVD_PARAM+_EDMA_ENTRY_SIZE) + #define _EDMA_LINK_CNT ((_EDMA_PRAM_SIZE/_EDMA_ENTRY_SIZE)-(_EDMA_CHA_CNT+2)) + #define _EDMA_SCRATCH_START (_EDMA_LINK_START+_EDMA_LINK_CNT*_EDMA_ENTRY_SIZE) + #define _EDMA_SCRATCH_SIZE (_EDMA_PRAM_START+_EDMA_PRAM_SIZE-_EDMA_SCRATCH_START) + +/******************************************************************************\ +* module level register/field access macros +\******************************************************************************/ + + /* ----------------- */ + /* FIELD MAKE MACROS */ + /* ----------------- */ + + #define EDMA_FMK(REG,FIELD,x)\ + _PER_FMK(EDMA,##REG,##FIELD,x) + + #define EDMA_FMKS(REG,FIELD,SYM)\ + _PER_FMKS(EDMA,##REG,##FIELD,##SYM) + + + /* -------------------------------- */ + /* RAW REGISTER/FIELD ACCESS MACROS */ + /* -------------------------------- */ + + #define EDMA_REG(REG) (*(volatile Uint32*)(_EDMA_##REG##_ADDR)) + + #define EDMA_ADDR(REG)\ + _EDMA_##REG##_ADDR + + #define EDMA_RGET(REG)\ + _PER_RGET(_EDMA_##REG##_ADDR,EDMA,##REG) + + #define EDMA_RSET(REG,x)\ + _PER_RSET(_EDMA_##REG##_ADDR,EDMA,##REG,x) + + #define EDMA_FGET(REG,FIELD)\ + _EDMA_##REG##_FGET(##FIELD) + + #define EDMA_FSET(REG,FIELD,x)\ + _EDMA_##REG##_FSET(##FIELD,##x) + + #define EDMA_FSETS(REG,FIELD,SYM)\ + _EDMA_##REG##_FSETS(##FIELD,##SYM) + + + /* ------------------------------------------ */ + /* ADDRESS BASED REGISTER/FIELD ACCESS MACROS */ + /* ------------------------------------------ */ + + #define EDMA_RGETA(addr,REG)\ + _PER_RGET(addr,EDMA,##REG) + + #define EDMA_RSETA(addr,REG,x)\ + _PER_RSET(addr,EDMA,##REG,x) + + #define EDMA_FGETA(addr,REG,FIELD)\ + _PER_FGET(addr,EDMA,##REG,##FIELD) + + #define EDMA_FSETA(addr,REG,FIELD,x)\ + _PER_FSET(addr,EDMA,##REG,##FIELD,x) + + #define EDMA_FSETSA(addr,REG,FIELD,SYM)\ + _PER_FSETS(addr,EDMA,##REG,##FIELD,##SYM) + + + /* ----------------------------------------- */ + /* HANDLE BASED REGISTER/FIELD ACCESS MACROS */ + /* ----------------------------------------- */ + + #define EDMA_ADDRH(h,REG)\ + ((((Uint32)(h))&0x0000FFFF)+_EDMA_PRAM_START+(_EDMA_##REG##_OFFSET<<2)) + + #define EDMA_RGETH(h,REG)\ + EDMA_RGETA(EDMA_ADDRH(h,##REG),##REG) + + + #define EDMA_RSETH(h,REG,x)\ + EDMA_RSETA(EDMA_ADDRH(h,##REG),##REG,x) + + + #define EDMA_FGETH(h,REG,FIELD)\ + EDMA_FGETA(EDMA_ADDRH(h,##REG),##REG,##FIELD) + + + #define EDMA_FSETH(h,REG,FIELD,x)\ + EDMA_FSETA(EDMA_ADDRH(h,##REG),##REG,##FIELD,x) + + + #define EDMA_FSETSH(h,REG,FIELD,SYM)\ + EDMA_FSETSA(EDMA_ADDRH(h,##REG),##REG,##FIELD,##SYM) + + + +/******************************************************************************\ +* _____________________ +* | | +* | O P T | +* | Q O P T | +* | Q S O P T | +* |___________________| +* +* OPT - options parameter +* QOPT - QDMA options register +* QSOPT - QDMA options pseudo register +* +* FIELDS (msb -> lsb) +* (rw) PRI +* (rw) ESIZE +* (rw) 2DS +* (rw) SUM +* (rw) 2DD +* (rw) DUM +* (rw) TCINT +* (rw) TCC +* (rw) TCCM (1) +* (rw) ATCINT (1) +* (rw) ATCC (1) +* (rw) PDTS (1) +* (rw) PDTD (1) +* (rw) LINK +* (rw) FS +* +* (1) - only supported on C64x devices +* +\******************************************************************************/ + #define _EDMA_OPT_OFFSET 0 + #define _EDMA_QOPT_OFFSET 0 + #define _EDMA_QSOPT_OFFSET 8 + + #define _EDMA_QOPT_ADDR 0x02000000u + #define _EDMA_QSOPT_ADDR 0x02000020u + + #define EDMA_QOPT EDMA_REG(QOPT) + #define EDMA_QSOPT EDMA_REG(QSOPT) + + #define _EDMA_OPT_PRI_MASK 0xE0000000u + #define _EDMA_OPT_PRI_SHIFT 0x0000001Du + #define EDMA_OPT_PRI_DEFAULT 0x00000000u + #define EDMA_OPT_PRI_OF(x) _VALUEOF(x) + #if (C64_SUPPORT) + #define EDMA_OPT_PRI_URGENT 0x00000000u + #define EDMA_OPT_PRI_HIGH 0x00000001u + #define EDMA_OPT_PRI_MEDIUM 0x00000002u + #define EDMA_OPT_PRI_LOW 0x00000003u + #else + #define EDMA_OPT_PRI_HIGH 0x00000001u + #define EDMA_OPT_PRI_LOW 0x00000002u + #endif + + #define _EDMA_OPT_ESIZE_MASK 0x18000000u + #define _EDMA_OPT_ESIZE_SHIFT 0x0000001Bu + #define EDMA_OPT_ESIZE_DEFAULT 0x00000000u + #define EDMA_OPT_ESIZE_OF(x) _VALUEOF(x) + #define EDMA_OPT_ESIZE_32BIT 0x00000000u + #define EDMA_OPT_ESIZE_16BIT 0x00000001u + #define EDMA_OPT_ESIZE_8BIT 0x00000002u + + #define _EDMA_OPT_2DS_MASK 0x04000000u + #define _EDMA_OPT_2DS_SHIFT 0x0000001Au + #define EDMA_OPT_2DS_DEFAULT 0x00000000u + #define EDMA_OPT_2DS_OF(x) _VALUEOF(x) + #define EDMA_OPT_2DS_NO 0x00000000u + #define EDMA_OPT_2DS_YES 0x00000001u + + #define _EDMA_OPT_SUM_MASK 0x03000000u + #define _EDMA_OPT_SUM_SHIFT 0x00000018u + #define EDMA_OPT_SUM_DEFAULT 0x00000000u + #define EDMA_OPT_SUM_OF(x) _VALUEOF(x) + #define EDMA_OPT_SUM_NONE 0x00000000u + #define EDMA_OPT_SUM_INC 0x00000001u + #define EDMA_OPT_SUM_DEC 0x00000002u + #define EDMA_OPT_SUM_IDX 0x00000003u + + #define _EDMA_OPT_2DD_MASK 0x00800000u + #define _EDMA_OPT_2DD_SHIFT 0x00000017u + #define EDMA_OPT_2DD_DEFAULT 0x00000000u + #define EDMA_OPT_2DD_OF(x) _VALUEOF(x) + #define EDMA_OPT_2DD_NO 0x00000000u + #define EDMA_OPT_2DD_YES 0x00000001u + + #define _EDMA_OPT_DUM_MASK 0x00600000u + #define _EDMA_OPT_DUM_SHIFT 0x00000015u + #define EDMA_OPT_DUM_DEFAULT 0x00000000u + #define EDMA_OPT_DUM_OF(x) _VALUEOF(x) + #define EDMA_OPT_DUM_NONE 0x00000000u + #define EDMA_OPT_DUM_INC 0x00000001u + #define EDMA_OPT_DUM_DEC 0x00000002u + #define EDMA_OPT_DUM_IDX 0x00000003u + + #define _EDMA_OPT_TCINT_MASK 0x00100000u + #define _EDMA_OPT_TCINT_SHIFT 0x00000014u + #define EDMA_OPT_TCINT_DEFAULT 0x00000000u + #define EDMA_OPT_TCINT_OF(x) _VALUEOF(x) + #define EDMA_OPT_TCINT_NO 0x00000000u + #define EDMA_OPT_TCINT_YES 0x00000001u + + #define _EDMA_OPT_TCC_MASK 0x000F0000u + #define _EDMA_OPT_TCC_SHIFT 0x00000010u + #define EDMA_OPT_TCC_DEFAULT 0x00000000u + #define EDMA_OPT_TCC_OF(x) _VALUEOF(x) + +#if (C64_SUPPORT) + #define _EDMA_OPT_TCCM_MASK 0x00006000u + #define _EDMA_OPT_TCCM_SHIFT 0x0000000Du + #define EDMA_OPT_TCCM_DEFAULT 0x00000000u + #define EDMA_OPT_TCCM_OF(x) _VALUEOF(x) + + #define _EDMA_OPT_ATCINT_MASK 0x00001000u + #define _EDMA_OPT_ATCINT_SHIFT 0x0000000Cu + #define EDMA_OPT_ATCINT_DEFAULT 0x00000000u + #define EDMA_OPT_ATCINT_OF(x) _VALUEOF(x) + #define EDMA_OPT_ATCINT_NO 0x00000000u + #define EDMA_OPT_ATCINT_YES 0x00000001u + + #define _EDMA_OPT_ATCC_MASK 0x000007E0u + #define _EDMA_OPT_ATCC_SHIFT 0x00000005u + #define EDMA_OPT_ATCC_DEFAULT 0x00000000u + #define EDMA_OPT_ATCC_OF(x) _VALUEOF(x) + + #define _EDMA_OPT_PDTS_MASK 0x00000008u + #define _EDMA_OPT_PDTS_SHIFT 0x00000003u + #define EDMA_OPT_PDTS_DEFAULT 0x00000000u + #define EDMA_OPT_PDTS_OF(x) _VALUEOF(x) + #define EDMA_OPT_PDTS_DISABLE 0x00000000u + #define EDMA_OPT_PDTS_ENABLE 0x00000001u + + #define _EDMA_OPT_PDTD_MASK 0x00000004u + #define _EDMA_OPT_PDTD_SHIFT 0x00000002u + #define EDMA_OPT_PDTD_DEFAULT 0x00000000u + #define EDMA_OPT_PDTD_OF(x) _VALUEOF(x) + #define EDMA_OPT_PDTD_DISABLE 0x00000000u + #define EDMA_OPT_PDTD_ENABLE 0x00000001u +#endif + + #define _EDMA_OPT_LINK_MASK 0x00000002u + #define _EDMA_OPT_LINK_SHIFT 0x00000001u + #define EDMA_OPT_LINK_DEFAULT 0x00000000u + #define EDMA_OPT_LINK_OF(x) _VALUEOF(x) + #define EDMA_OPT_LINK_NA 0x00000000u + #define EDMA_OPT_LINK_NO 0x00000000u + #define EDMA_OPT_LINK_YES 0x00000001u + + #define _EDMA_OPT_FS_MASK 0x00000001u + #define _EDMA_OPT_FS_SHIFT 0x00000000u + #define EDMA_OPT_FS_DEFAULT 0x00000000u + #define EDMA_OPT_FS_OF(x) _VALUEOF(x) + #define EDMA_OPT_FS_NO 0x00000000u + #define EDMA_OPT_FS_YES 0x00000001u + + #define EDMA_OPT_OF(x) _VALUEOF(x) + +#if (C64_SUPPORT) + #define EDMA_OPT_DEFAULT (Uint32)(\ + _PER_FDEFAULT(EDMA,OPT,PRI)\ + |_PER_FDEFAULT(EDMA,OPT,ESIZE)\ + |_PER_FDEFAULT(EDMA,OPT,2DS)\ + |_PER_FDEFAULT(EDMA,OPT,SUM)\ + |_PER_FDEFAULT(EDMA,OPT,2DD)\ + |_PER_FDEFAULT(EDMA,OPT,DUM)\ + |_PER_FDEFAULT(EDMA,OPT,TCINT)\ + |_PER_FDEFAULT(EDMA,OPT,TCC)\ + |_PER_FDEFAULT(EDMA,OPT,TCCM)\ + |_PER_FDEFAULT(EDMA,OPT,ATCINT) \ + |_PER_FDEFAULT(EDMA,OPT,ATCC) \ + |_PER_FDEFAULT(EDMA,OPT,PDTS) \ + |_PER_FDEFAULT(EDMA,OPT,PDTD) \ + |_PER_FDEFAULT(EDMA,OPT,LINK)\ + |_PER_FDEFAULT(EDMA,OPT,FS)\ + ) + + #define EDMA_OPT_RMK(pri,esize,ds2,sum,dd2,dum,tcint,tcc,tccm,atcint,atcc,\ + pdts,pdtd,link,fs) (Uint32)(\ + _PER_FMK(EDMA,OPT,PRI,pri) \ + |_PER_FMK(EDMA,OPT,ESIZE,esize) \ + |_PER_FMK(EDMA,OPT,2DS,ds2) \ + |_PER_FMK(EDMA,OPT,SUM,sum) \ + |_PER_FMK(EDMA,OPT,2DD,dd2) \ + |_PER_FMK(EDMA,OPT,DUM,dum) \ + |_PER_FMK(EDMA,OPT,TCINT,tcint) \ + |_PER_FMK(EDMA,OPT,TCC,tcc) \ + |_PER_FMK(EDMA,OPT,TCCM,tccm) \ + |_PER_FMK(EDMA,OPT,ATCINT,atcint) \ + |_PER_FMK(EDMA,OPT,ATCC,atcc) \ + |_PER_FMK(EDMA,OPT,PDTS,pdts) \ + |_PER_FMK(EDMA,OPT,PDTD,pdtd) \ + |_PER_FMK(EDMA,OPT,LINK,link) \ + |_PER_FMK(EDMA,OPT,FS,fs) \ + ) +#endif + +#if (!C64_SUPPORT) + #define EDMA_OPT_DEFAULT (Uint32)(\ + _PER_FDEFAULT(EDMA,OPT,PRI)\ + |_PER_FDEFAULT(EDMA,OPT,ESIZE)\ + |_PER_FDEFAULT(EDMA,OPT,2DS)\ + |_PER_FDEFAULT(EDMA,OPT,SUM)\ + |_PER_FDEFAULT(EDMA,OPT,2DD)\ + |_PER_FDEFAULT(EDMA,OPT,DUM)\ + |_PER_FDEFAULT(EDMA,OPT,TCINT)\ + |_PER_FDEFAULT(EDMA,OPT,TCC)\ + |_PER_FDEFAULT(EDMA,OPT,LINK)\ + |_PER_FDEFAULT(EDMA,OPT,FS)\ + ) + + #define EDMA_OPT_RMK(pri,esize,ds2,sum,dd2,dum,tcint,tcc,link,fs) (Uint32)(\ + _PER_FMK(EDMA,OPT,PRI,pri) \ + |_PER_FMK(EDMA,OPT,ESIZE,esize) \ + |_PER_FMK(EDMA,OPT,2DS,ds2) \ + |_PER_FMK(EDMA,OPT,SUM,sum) \ + |_PER_FMK(EDMA,OPT,2DD,dd2) \ + |_PER_FMK(EDMA,OPT,DUM,dum) \ + |_PER_FMK(EDMA,OPT,TCINT,tcint) \ + |_PER_FMK(EDMA,OPT,TCC,tcc) \ + |_PER_FMK(EDMA,OPT,LINK,link) \ + |_PER_FMK(EDMA,OPT,FS,fs) \ + ) +#endif + + #define _EDMA_QOPT_FGET(FIELD)\ + _PER_FGET(_EDMA_QOPT_ADDR,EDMA,OPT,##FIELD) + + #define _EDMA_QOPT_FSET(FIELD,field)\ + _PER_FSET(_EDMA_QOPT_ADDR,EDMA,OPT,##FIELD,field) + + #define _EDMA_QOPT_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_QOPT_ADDR,EDMA,OPT,##FIELD,##SYM) + + #define _EDMA_QSOPT_FGET(FIELD)\ + _PER_FGET(_EDMA_QSOPT_ADDR,EDMA,OPT,##FIELD) + + #define _EDMA_QSOPT_FSET(FIELD,field)\ + _PER_FSET(_EDMA_QSOPT_ADDR,EDMA,OPT,##FIELD,field) + + #define _EDMA_QSOPT_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_QSOPT_ADDR,EDMA,OPT,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | S R C | +* | Q S R C | +* | Q S S R C | +* |___________________| +* +* SRC - source address parameter +* QSRC - QDMA source address register +* QSSRC - QDMA source address pseudo register +* +* FIELDS (msb -> lsb) +* (rw) SRC +* +\******************************************************************************/ + #define _EDMA_SRC_OFFSET 1 + #define _EDMA_QSRC_OFFSET 1 + #define _EDMA_QSSRC_OFFSET 9 + + #define _EDMA_QSRC_ADDR 0x02000004u + #define _EDMA_QSSRC_ADDR 0x02000024u + + #define EDMA_QSRC EDMA_REG(QSRC) + #define EDMA_QSSRC EDMA_REG(QSSRC) + + #define _EDMA_SRC_SRC_MASK 0xFFFFFFFFu + #define _EDMA_SRC_SRC_SHIFT 0x00000000u + #define EDMA_SRC_SRC_DEFAULT 0x00000000u + #define EDMA_SRC_SRC_OF(x) _VALUEOF(x) + + #define EDMA_SRC_OF(x) _VALUEOF(x) + + #define EDMA_SRC_DEFAULT (Uint32)(\ + _PER_FDEFAULT(EDMA,SRC,SRC)\ + ) + + #define EDMA_SRC_RMK(src) (Uint32)(\ + _PER_FMK(EDMA,SRC,SRC,src) \ + ) + + #define _EDMA_QSRC_FGET(FIELD)\ + _PER_FGET(_EDMA_QSRC_ADDR,EDMA,SRC,##FIELD) + + #define _EDMA_QSRC_FSET(FIELD,field)\ + _PER_FSET(_EDMA_QSRC_ADDR,EDMA,SRC,##FIELD,field) + + #define _EDMA_QSRC_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_QSRC_ADDR,EDMA,SRC,##FIELD,##SYM) + + #define _EDMA_QSSRC_FGET(FIELD)\ + _PER_FGET(_EDMA_QSSRC_ADDR,EDMA,SRC,##FIELD) + + #define _EDMA_QSSRC_FSET(FIELD,field)\ + _PER_FSET(_EDMA_QSSRC_ADDR,EDMA,SRC,##FIELD,field) + + #define _EDMA_QSSRC_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_QSSRC_ADDR,EDMA,SRC,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | C N T | +* | Q C N T | +* | Q S C N T | +* |___________________| +* +* CNT - transfer count parameter +* QCNT - QDMA transfer count register +* QSCNT - QDMA transfer count pseudo register +* +* FIELDS (msb -> lsb) +* (rw) FRMCNT +* (rw) ELECNT +* +\******************************************************************************/ + #define _EDMA_CNT_OFFSET 2 + #define _EDMA_QCNT_OFFSET 2 + #define _EDMA_QSCNT_OFFSET 10 + + #define _EDMA_QCNT_ADDR 0x02000008u + #define _EDMA_QSCNT_ADDR 0x02000028u + + #define EDMA_QCNT EDMA_REG(QCNT) + #define EDMA_QSCNT EDMA_REG(QSCNT) + + #define _EDMA_CNT_FRMCNT_MASK 0xFFFF0000u + #define _EDMA_CNT_FRMCNT_SHIFT 0x00000010u + #define EDMA_CNT_FRMCNT_DEFAULT 0x00000000u + #define EDMA_CNT_FRMCNT_OF(x) _VALUEOF(x) + + #define _EDMA_CNT_ELECNT_MASK 0x0000FFFFu + #define _EDMA_CNT_ELECNT_SHIFT 0x00000000u + #define EDMA_CNT_ELECNT_DEFAULT 0x00000000u + #define EDMA_CNT_ELECNT_OF(x) _VALUEOF(x) + + #define EDMA_CNT_OF(x) _VALUEOF(x) + + #define EDMA_CNT_DEFAULT (Uint32)(\ + _PER_FDEFAULT(EDMA,CNT,FRMCNT)\ + |_PER_FDEFAULT(EDMA,CNT,ELECNT)\ + ) + + #define EDMA_CNT_RMK(frmcnt,elecnt) (Uint32)(\ + _PER_FMK(EDMA,CNT,FRMCNT,frmcnt) \ + |_PER_FMK(EDMA,CNT,ELECNT,elecnt) \ + ) + + #define _EDMA_QCNT_FGET(FIELD)\ + _PER_FGET(_EDMA_QCNT_ADDR,EDMA,CNT,##FIELD) + + #define _EDMA_QCNT_FSET(FIELD,field)\ + _PER_FSET(_EDMA_QCNT_ADDR,EDMA,CNT,##FIELD,field) + + #define _EDMA_QCNT_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_QCNT_ADDR,EDMA,CNT,##FIELD,##SYM) + + #define _EDMA_QSCNT_FGET(FIELD)\ + _PER_FGET(_EDMA_QSCNT_ADDR,EDMA,CNT,##FIELD) + + #define _EDMA_QSCNT_FSET(FIELD,field)\ + _PER_FSET(_EDMA_QSCNT_ADDR,EDMA,CNT,##FIELD,field) + + #define _EDMA_QSCNT_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_QSCNT_ADDR,EDMA,CNT,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | D S T | +* | Q D S T | +* | Q S D S T | +* |___________________| +* +* DST - destination address parameter +* QDST - QDMA destination address register +* QSDST - QDMA destination address pseudo register +* +* FIELDS (msb -> lsb) +* (rw) DST +* +\******************************************************************************/ + #define _EDMA_DST_OFFSET 3 + #define _EDMA_QDST_OFFSET 3 + #define _EDMA_QSDST_OFFSET 11 + + #define _EDMA_QDST_ADDR 0x0200000Cu + #define _EDMA_QSDST_ADDR 0x0200002Cu + + #define EDMA_QDST EDMA_REG(QDST) + #define EDMA_QSDST EDMA_REG(QSDST) + + #define _EDMA_DST_DST_MASK 0xFFFFFFFFu + #define _EDMA_DST_DST_SHIFT 0x00000000u + #define EDMA_DST_DST_DEFAULT 0x00000000u + #define EDMA_DST_DST_OF(x) _VALUEOF(x) + + #define EDMA_DST_OF(x) _VALUEOF(x) + + #define EDMA_DST_DEFAULT (Uint32)(\ + _PER_FDEFAULT(EDMA,DST,DST)\ + ) + + #define EDMA_DST_RMK(dst) (Uint32)(\ + _PER_FMK(EDMA,DST,DST,dst) \ + ) + + #define _EDMA_QDST_FGET(FIELD)\ + _PER_FGET(_EDMA_QDST_ADDR,EDMA,DST,##FIELD) + + #define _EDMA_QDST_FSET(FIELD,field)\ + _PER_FSET(_EDMA_QDST_ADDR,EDMA,DST,##FIELD,field) + + #define _EDMA_QDST_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_QDST_ADDR,EDMA,DST,##FIELD,##SYM) + + #define _EDMA_QSDST_FGET(FIELD)\ + _PER_FGET(_EDMA_QSDST_ADDR,EDMA,DST,##FIELD) + + #define _EDMA_QSDST_FSET(FIELD,field)\ + _PER_FSET(_EDMA_QSDST_ADDR,EDMA,DST,##FIELD,field) + + #define _EDMA_QSDST_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_QSDST_ADDR,EDMA,DST,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | I D X | +* | Q I D X | +* | Q S I D X | +* |___________________| +* +* IDX - index parameter +* QIDX - QDMA index register +* QSIDX - QDMA index pseudo register +* +* FIELDS (msb -> lsb) +* (rw) FRMIDX +* (rw) ELEIDX +* +\******************************************************************************/ + #define _EDMA_IDX_OFFSET 4 + #define _EDMA_QIDX_OFFSET 4 + #define _EDMA_QSIDX_OFFSET 12 + + #define _EDMA_QIDX_ADDR 0x02000010u + #define _EDMA_QSIDX_ADDR 0x02000030u + + #define EDMA_QIDX EDMA_REG(QIDX) + #define EDMA_QSIDX EDMA_REG(QSIDX) + + #define _EDMA_IDX_FRMIDX_MASK 0xFFFF0000u + #define _EDMA_IDX_FRMIDX_SHIFT 0x00000010u + #define EDMA_IDX_FRMIDX_DEFAULT 0x00000000u + #define EDMA_IDX_FRMIDX_OF(x) _VALUEOF(x) + + #define _EDMA_IDX_ELEIDX_MASK 0x0000FFFFu + #define _EDMA_IDX_ELEIDX_SHIFT 0x00000000u + #define EDMA_IDX_ELEIDX_DEFAULT 0x00000000u + #define EDMA_IDX_ELEIDX_OF(x) _VALUEOF(x) + + #define EDMA_IDX_OF(x) _VALUEOF(x) + + #define EDMA_IDX_DEFAULT (Uint32)(\ + _PER_FDEFAULT(EDMA,IDX,FRMIDX)\ + |_PER_FDEFAULT(EDMA,IDX,ELEIDX)\ + ) + + #define EDMA_IDX_RMK(frmidx,eleidx) (Uint32)(\ + _PER_FMK(EDMA,IDX,FRMIDX,frmidx) \ + |_PER_FMK(EDMA,IDX,ELEIDX,eleidx) \ + ) + + #define _EDMA_QIDX_FGET(FIELD)\ + _PER_FGET(_EDMA_QIDX_ADDR,EDMA,IDX,##FIELD) + + #define _EDMA_QIDX_FSET(FIELD,field)\ + _PER_FSET(_EDMA_QIDX_ADDR,EDMA,IDX,##FIELD,field) + + #define _EDMA_QIDX_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_QIDX_ADDR,EDMA,IDX,##FIELD,##SYM) + + #define _EDMA_QSIDX_FGET(FIELD)\ + _PER_FGET(_EDMA_QSIDX_ADDR,EDMA,IDX,##FIELD) + + #define _EDMA_QSIDX_FSET(FIELD,field)\ + _PER_FSET(_EDMA_QSIDX_ADDR,EDMA,IDX,##FIELD,field) + + #define _EDMA_QSIDX_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_QSIDX_ADDR,EDMA,IDX,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | R L D | +* | Q R L D | +* | Q S R L D | +* |___________________| +* +* RLD - count reload/link parameter +* +* FIELDS (msb -> lsb) +* (rw) ELECNT +* (rw) LINK +* +\******************************************************************************/ + #define _EDMA_RLD_OFFSET 5 + #define _EDMA_QRLD_OFFSET 5 + #define _EDMA_QSRLD_OFFSET 13 + + #define _EDMA_QRLD_ADDR 0x02000014u + #define _EDMA_QSRLD_ADDR 0x02000034u + + #define EDMA_QRLD EDMA_REG(QRLD) + #define EDMA_QSRLD EDMA_REG(QSRLD) + + #define _EDMA_RLD_ELERLD_MASK 0xFFFF0000u + #define _EDMA_RLD_ELERLD_SHIFT 0x00000010u + #define EDMA_RLD_ELERLD_DEFAULT 0x00000000u + #define EDMA_RLD_ELERLD_OF(x) _VALUEOF(x) + + #define _EDMA_RLD_LINK_MASK 0x0000FFFFu + #define _EDMA_RLD_LINK_SHIFT 0x00000000u + #define EDMA_RLD_LINK_DEFAULT 0x00000000u + #define EDMA_RLD_LINK_OF(x) _VALUEOF(x) + + #define EDMA_RLD_OF(x) _VALUEOF(x) + + #define EDMA_RLD_DEFAULT (Uint32)(\ + _PER_FDEFAULT(EDMA,RLD,ELERLD)\ + |_PER_FDEFAULT(EDMA,RLD,LINK)\ + ) + + #define EDMA_RLD_RMK(elerld,link) (Uint32)(\ + _PER_FMK(EDMA,RLD,ELERLD,elerld) \ + |_PER_FMK(EDMA,RLD,LINK,link) \ + ) + + #define _EDMA_QRLD_FGET(FIELD)\ + _PER_FGET(_EDMA_QRLD_ADDR,EDMA,RLD,##FIELD) + + #define _EDMA_QRLD_FSET(FIELD,field)\ + _PER_FSET(_EDMA_QRLD_ADDR,EDMA,RLD,##FIELD,field) + + #define _EDMA_QRLD_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_QRLD_ADDR,EDMA,RLD,##FIELD,##SYM) + + #define _EDMA_QSRLD_FGET(FIELD)\ + _PER_FGET(_EDMA_QSRLD_ADDR,EDMA,RLD,##FIELD) + + #define _EDMA_QSRLD_FSET(FIELD,field)\ + _PER_FSET(_EDMA_QSRLD_ADDR,EDMA,RLD,##FIELD,field) + + #define _EDMA_QSRLD_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_QSRLD_ADDR,EDMA,RLD,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | P Q S R | +* |___________________| +* +* PQSR - priority queue status register +* +* FIELDS (msb -> lsb) +* (r) PQ +* +\******************************************************************************/ + #define _EDMA_PQSR_ADDR 0x01A0FFE0u + + #define EDMA_PQSR EDMA_REG(PQSR) + +#if (C64_SUPPORT) + #define _EDMA_PQSR_PQ_MASK 0x0000000Fu + #define _EDMA_PQSR_PQ_SHIFT 0x00000000u + #define EDMA_PQSR_PQ_DEFAULT 0x0000000Fu + #define EDMA_PQSR_PQ_OF(x) _VALUEOF(x) +#else + #define _EDMA_PQSR_PQ_MASK 0x00000007u + #define _EDMA_PQSR_PQ_SHIFT 0x00000000u + #define EDMA_PQSR_PQ_DEFAULT 0x00000007u + #define EDMA_PQSR_PQ_OF(x) _VALUEOF(x) +#endif + + #define EDMA_PQSR_OF(x) _VALUEOF(x) + + #define EDMA_PQSR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(EDMA,PQSR,PQ)\ + ) + #if (!(CHIP_6410 | CHIP_6413 | CHIP_6418)) + #define EDMA_PQSR_RMK(pq) (Uint32)(\ + _PER_FMK(EDMA,PQSR,PQ,pq)\ + ) + #endif + + #define _EDMA_PQSR_FGET(FIELD)\ + _PER_FGET(_EDMA_PQSR_ADDR,EDMA,PQSR,##FIELD) + + #define _EDMA_PQSR_FSET(FIELD,field)\ + _PER_FSET(_EDMA_PQSR_ADDR,EDMA,PQSR,##FIELD,field) + + #define _EDMA_PQSR_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_PQSR_ADDR,EDMA,PQSR,##FIELD,##SYM) + +/******************************************************************************\ +* _____________________ +* | | +* | P Q A R 0 | +* |___________________| +* +* PQAR0 - priority queue allocation register 0 +* +* FIELDS (msb -> lsb) +* (r) PQA +* +\******************************************************************************/ + #if (C64_SUPPORT) + #define _EDMA_PQAR0_ADDR 0x01A0FFC0u + + #define EDMA_PQAR0 EDMA_REG(PQAR0) + + #define _EDMA_PQAR0_PQA_MASK 0x00000007u + #define _EDMA_PQAR0_PQA_SHIFT 0x00000000u + #define EDMA_PQAR0_PQA_DEFAULT 0x00000002u + #define EDMA_PQAR0_PQA_OF(x) _VALUEOF(x) + + #define EDMA_PQAR0_OF(x) _VALUEOF(x) + + #define EDMA_PQAR0_DEFAULT (Uint32)(\ + _PER_FDEFAULT(EDMA,PQAR0,PQA)\ + ) + + #if (!(CHIP_6413 | CHIP_6418 | CHIP_6410)) + #define EDMA_PQAR0_RMK(pqa) (Uint32)(\ + _PER_FMK(EDMA,PQAR0,PQA,pqa)\ + ) + #endif + + #define _EDMA_PQAR0_FSET(FIELD,field)\ + _PER_FSET(_EDMA_PQAR0_ADDR,EDMA,PQAR0,FIELD,field) + + #define _EDMA_PQAR0_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_PQAR0_ADDR,EDMA,PQAR0,FIELD,##SYM) + + #define _EDMA_PQAR0_FGET(FIELD)\ + _PER_FGET(_EDMA_PQAR0_ADDR,EDMA,PQAR0,FIELD) + +#endif + +/******************************************************************************\ +* _____________________ +* | | +* | P Q A R 1 | +* |___________________| +* +* PQAR1 - priority queue allocation register 1 +* +* FIELDS (msb -> lsb) +* (r) PQA +* +\******************************************************************************/ + #if (C64_SUPPORT) + #define _EDMA_PQAR1_ADDR 0x01A0FFC4u + + #define EDMA_PQAR1 EDMA_REG(PQAR1) + + #define _EDMA_PQAR1_PQA_MASK 0x00000007u + #define _EDMA_PQAR1_PQA_SHIFT 0x00000000u + #define EDMA_PQAR1_PQA_DEFAULT 0x00000006u + #define EDMA_PQAR1_PQA_OF(x) _VALUEOF(x) + + #define EDMA_PQAR1_OF(x) _VALUEOF(x) + + #if (!(CHIP_6413 | CHIP_6418 | CHIP_6410)) + #define EDMA_PQAR1_RMK(pqa) (Uint32)(\ + _PER_FMK(EDMA,PQAR1,PQA,pqa)\ + ) + #endif + + #define EDMA_PQAR1_DEFAULT (Uint32)(\ + _PER_FDEFAULT(EDMA,PQAR1,PQA)\ + ) + + #define _EDMA_PQAR1_FGET(FIELD)\ + _PER_FGET(_EDMA_PQAR1_ADDR,EDMA,PQAR1,FIELD) + + #define _EDMA_PQAR1_FSET(FIELD,field)\ + _PER_FSET(_EDMA_PQAR1_ADDR,EDMA,PQAR1,FIELD,field) + + #define _EDMA_PQAR1_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_PQAR1_ADDR,EDMA,PQAR1,FIELD,##SYM) + +#endif + +/******************************************************************************\ +* _____________________ +* | | +* | P Q A R 2 | +* |___________________| +* +* PQAR2 - priority queue allocation register 2 +* +* FIELDS (msb -> lsb) +* (r) PQA +* +\******************************************************************************/ + #if (C64_SUPPORT) + #define _EDMA_PQAR2_ADDR 0x01A0FFC8u + + #define EDMA_PQAR2 EDMA_REG(PQAR2) + + #define _EDMA_PQAR2_PQA_MASK 0x00000007u + #define _EDMA_PQAR2_PQA_SHIFT 0x00000000u + #define EDMA_PQAR2_PQA_DEFAULT 0x00000002u + #define EDMA_PQAR2_PQA_OF(x) _VALUEOF(x) + + #define EDMA_PQAR2_OF(x) _VALUEOF(x) + + #define EDMA_PQAR2_DEFAULT (Uint32)(\ + _PER_FDEFAULT(EDMA,PQAR2,PQA)\ + ) + + #if (!(CHIP_6413 | CHIP_6418 | CHIP_6410)) + #define EDMA_PQAR2_RMK(pqa) (Uint32)(\ + _PER_FMK(EDMA,PQAR2,PQA,pqa)\ + ) + #endif + + #define _EDMA_PQAR2_FGET(FIELD)\ + _PER_FGET(_EDMA_PQAR2_ADDR,EDMA,PQAR2,FIELD) + + #define _EDMA_PQAR2_FSET(FIELD,field)\ + _PER_FSET(_EDMA_PQAR2_ADDR,EDMA,PQAR2,FIELD,field) + + #define _EDMA_PQAR2_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_PQAR2_ADDR,EDMA,PQAR2,FIELD,##SYM) + +#endif + +/******************************************************************************\ +* _____________________ +* | | +* | P Q A R 3 | +* |___________________| +* +* PQAR3 - priority queue allocation register 3 +* +* FIELDS (msb -> lsb) +* (r) PQA +* +\******************************************************************************/ + #if (C64_SUPPORT) + #define _EDMA_PQAR3_ADDR 0x01A0FFCCu + + #define EDMA_PQAR3 EDMA_REG(PQAR3) + + #define _EDMA_PQAR3_PQA_MASK 0x00000007u + #define _EDMA_PQAR3_PQA_SHIFT 0x00000000u + #define EDMA_PQAR3_PQA_DEFAULT 0x00000006u + #define EDMA_PQAR3_PQA_OF(x) _VALUEOF(x) + + #define EDMA_PQAR3_OF(x) _VALUEOF(x) + + #define EDMA_PQAR3_DEFAULT (Uint32)(\ + _PER_FDEFAULT(EDMA,PQAR3,PQA)\ + ) + + #if (!(CHIP_6413 | CHIP_6418 | CHIP_6410)) + #define EDMA_PQAR3_RMK(pqa) (Uint32)(\ + _PER_FMK(EDMA,PQAR3,PQA,pqa)\ + ) + #endif + + #define _EDMA_PQAR3_FGET(FIELD)\ + _PER_FGET(_EDMA_PQAR3_ADDR,EDMA,PQAR3,FIELD) + + #define _EDMA_PQAR3_FSET(FIELD,field)\ + _PER_FSET(_EDMA_PQAR3_ADDR,EDMA,PQAR3,FIELD,field) + + #define _EDMA_PQAR3_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_PQAR3_ADDR,EDMA,PQAR3,FIELD,##SYM) + +#endif + +/******************************************************************************\ +* _____________________ +* | | +* | C I P R | +* |___________________| +* +* CIPR - channel interrupt pending register +* +* FIELDS (msb -> lsb) +* (rw) CIP +* +\******************************************************************************/ + #define _EDMA_CIPR_ADDR 0x01A0FFE4u + + #define EDMA_CIPR EDMA_REG(CIPR) + +#if (C64_SUPPORT) + #define _EDMA_CIPR_CIP_MASK 0xFFFFFFFFu + #define _EDMA_CIPR_CIP_SHIFT 0x00000000u + #define EDMA_CIPR_CIP_DEFAULT 0x00000000u + #define EDMA_CIPR_CIP_OF(x) _VALUEOF(x) +#else + #define _EDMA_CIPR_CIP_MASK 0x0000FFFFu + #define _EDMA_CIPR_CIP_SHIFT 0x00000000u + #define EDMA_CIPR_CIP_DEFAULT 0x00000000u + #define EDMA_CIPR_CIP_OF(x) _VALUEOF(x) +#endif + + #define EDMA_CIPR_OF(x) _VALUEOF(x) + + #define EDMA_CIPR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(EDMA,CIPR,CIP)\ + ) + + #define EDMA_CIPR_RMK(cip) (Uint32)(\ + _PER_FMK(EDMA,CIPR,CIP,cip)\ + ) + + #define _EDMA_CIPR_FGET(FIELD)\ + _PER_FGET(_EDMA_CIPR_ADDR,EDMA,CIPR,##FIELD) + + #define _EDMA_CIPR_FSET(FIELD,field)\ + _PER_FSET(_EDMA_CIPR_ADDR,EDMA,CIPR,##FIELD,field) + + #define _EDMA_CIPR_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_CIPR_ADDR,EDMA,CIPR,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | C I P R L | +* |___________________| +* +* CIPRL - channel interrupt pending register, low half (1) +* +* (1) - C64x devices only +* +* FIELDS (msb -> lsb) +* (rw) CIP +* +\******************************************************************************/ +#if (C64_SUPPORT) + #define _EDMA_CIPRL_ADDR 0x01A0FFE4u + + #define EDMA_CIPRL EDMA_REG(CIPRL) + + #define _EDMA_CIPRL_CIP_MASK 0xFFFFFFFFu + #define _EDMA_CIPRL_CIP_SHIFT 0x00000000u + #define EDMA_CIPRL_CIP_DEFAULT 0x00000000u + #define EDMA_CIPRL_CIP_OF(x) _VALUEOF(x) + + #define EDMA_CIPRL_OF(x) _VALUEOF(x) + + #define EDMA_CIPRL_DEFAULT (Uint32)(\ + _PER_FDEFAULT(EDMA,CIPRL,CIP)\ + ) + + #define EDMA_CIPRL_RMK(cip) (Uint32)(\ + _PER_FMK(EDMA,CIPRL,CIP,cip)\ + ) + + #define _EDMA_CIPRL_FGET(FIELD)\ + _PER_FGET(_EDMA_CIPRL_ADDR,EDMA,CIPRL,##FIELD) + + #define _EDMA_CIPRL_FSET(FIELD,field)\ + _PER_FSET(_EDMA_CIPRL_ADDR,EDMA,CIPRL,##FIELD,field) + + #define _EDMA_CIPRL_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_CIPRL_ADDR,EDMA,CIPRL,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* _____________________ +* | | +* | C I P R H | +* |___________________| +* +* CIPRH - channel interrupt pending register, high half (1) +* +* (1) - C64x devices only +* +* FIELDS (msb -> lsb) +* (rw) CIP +* +\******************************************************************************/ +#if (C64_SUPPORT) + #define _EDMA_CIPRH_ADDR 0x01A0FFA4u + + #define EDMA_CIPRH EDMA_REG(CIPRH) + + #define _EDMA_CIPRH_CIP_MASK 0xFFFFFFFFu + #define _EDMA_CIPRH_CIP_SHIFT 0x00000000u + #define EDMA_CIPRH_CIP_DEFAULT 0x00000000u + #define EDMA_CIPRH_CIP_OF(x) _VALUEOF(x) + + #define EDMA_CIPRH_OF(x) _VALUEOF(x) + + #define EDMA_CIPRH_DEFAULT (Uint32)(\ + _PER_FDEFAULT(EDMA,CIPRH,CIP)\ + ) + + #define EDMA_CIPRH_RMK(cip) (Uint32)(\ + _PER_FMK(EDMA,CIPRH,CIP,cip)\ + ) + + #define _EDMA_CIPRH_FGET(FIELD)\ + _PER_FGET(_EDMA_CIPRH_ADDR,EDMA,CIPRH,##FIELD) + + #define _EDMA_CIPRH_FSET(FIELD,field)\ + _PER_FSET(_EDMA_CIPRH_ADDR,EDMA,CIPRH,##FIELD,field) + + #define _EDMA_CIPRH_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_CIPRH_ADDR,EDMA,CIPRH,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* _____________________ +* | | +* | C I E R | +* |___________________| +* +* CIER - channel interrupt enable register +* +* FIELDS (msb -> lsb) +* (rw) CIE +* +\******************************************************************************/ + #define _EDMA_CIER_ADDR 0x01A0FFE8u + + #define EDMA_CIER EDMA_REG(CIER) + +#if (C64_SUPPORT) + #define _EDMA_CIER_CIE_MASK 0xFFFFFFFFu + #define _EDMA_CIER_CIE_SHIFT 0x00000000u + #define EDMA_CIER_CIE_DEFAULT 0x00000000u + #define EDMA_CIER_CIE_OF(x) _VALUEOF(x) +#else + #define _EDMA_CIER_CIE_MASK 0x0000FFFFu + #define _EDMA_CIER_CIE_SHIFT 0x00000000u + #define EDMA_CIER_CIE_DEFAULT 0x00000000u + #define EDMA_CIER_CIE_OF(x) _VALUEOF(x) +#endif + + #define EDMA_CIER_OF(x) _VALUEOF(x) + + #define EDMA_CIER_DEFAULT (Uint32)(\ + _PER_FDEFAULT(EDMA,CIER,CIE)\ + ) + + #define EDMA_CIER_RMK(cie) (Uint32)(\ + _PER_FMK(EDMA,CIER,CIE,cie)\ + ) + + #define _EDMA_CIER_FGET(FIELD)\ + _PER_FGET(_EDMA_CIER_ADDR,EDMA,CIER,##FIELD) + + #define _EDMA_CIER_FSET(FIELD,field)\ + _PER_FSET(_EDMA_CIER_ADDR,EDMA,CIER,##FIELD,field) + + #define _EDMA_CIER_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_CIER_ADDR,EDMA,CIER,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | C I E R L | +* |___________________| +* +* CIERL - channel interrupt enable register, low half (1) +* +* (1) - C64x devices only +* +* FIELDS (msb -> lsb) +* (rw) CIE +* +\******************************************************************************/ +#if (C64_SUPPORT) + #define _EDMA_CIERL_ADDR 0x01A0FFE8u + + #define EDMA_CIERL EDMA_REG(CIERL) + + #define _EDMA_CIERL_CIE_MASK 0xFFFFFFFFu + #define _EDMA_CIERL_CIE_SHIFT 0x00000000u + #define EDMA_CIERL_CIE_DEFAULT 0x00000000u + #define EDMA_CIERL_CIE_OF(x) _VALUEOF(x) + + #define EDMA_CIERL_OF(x) _VALUEOF(x) + + #define EDMA_CIERL_DEFAULT (Uint32)(\ + _PER_FDEFAULT(EDMA,CIERL,CIE)\ + ) + + #define EDMA_CIERL_RMK(cie) (Uint32)(\ + _PER_FMK(EDMA,CIERL,CIE,cie)\ + ) + + #define _EDMA_CIERL_FGET(FIELD)\ + _PER_FGET(_EDMA_CIERL_ADDR,EDMA,CIERL,##FIELD) + + #define _EDMA_CIERL_FSET(FIELD,field)\ + _PER_FSET(_EDMA_CIERL_ADDR,EDMA,CIERL,##FIELD,field) + + #define _EDMA_CIERL_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_CIERL_ADDR,EDMA,CIERL,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* _____________________ +* | | +* | C I E R H | +* |___________________| +* +* CIERL - channel interrupt enable register, high half (1) +* +* (1) - C64x devices only +* +* FIELDS (msb -> lsb) +* (rw) CIE +* +\******************************************************************************/ +#if (C64_SUPPORT) + #define _EDMA_CIERH_ADDR 0x01A0FFA8u + + #define EDMA_CIERH EDMA_REG(CIERH) + + #define _EDMA_CIERH_CIE_MASK 0xFFFFFFFFu + #define _EDMA_CIERH_CIE_SHIFT 0x00000000u + #define EDMA_CIERH_CIE_DEFAULT 0x00000000u + #define EDMA_CIERH_CIE_OF(x) _VALUEOF(x) + + #define EDMA_CIERH_OF(x) _VALUEOF(x) + + #define EDMA_CIERH_DEFAULT (Uint32)(\ + _PER_FDEFAULT(EDMA,CIERH,CIE)\ + ) + + #define EDMA_CIERH_RMK(cie) (Uint32)(\ + _PER_FMK(EDMA,CIERH,CIE,cie)\ + ) + + #define _EDMA_CIERH_FGET(FIELD)\ + _PER_FGET(_EDMA_CIERH_ADDR,EDMA,CIERH,##FIELD) + + #define _EDMA_CIERH_FSET(FIELD,field)\ + _PER_FSET(_EDMA_CIERH_ADDR,EDMA,CIERH,##FIELD,field) + + #define _EDMA_CIERH_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_CIERH_ADDR,EDMA,CIERH,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* _____________________ +* | | +* | C C E R | +* |___________________| +* +* CCER - channel chain enable register +* +* FIELDS (msb -> lsb) +* (rw) CCE +* +\******************************************************************************/ + #define _EDMA_CCER_ADDR 0x01A0FFECu + + #define EDMA_CCER EDMA_REG(CCER) + +#if (C64_SUPPORT) + #define _EDMA_CCER_CCE_MASK 0xFFFFFFFFu + #define _EDMA_CCER_CCE_SHIFT 0x00000000u + #define EDMA_CCER_CCE_DEFAULT 0x00000000u + #define EDMA_CCER_CCE_OF(x) _VALUEOF(x) +#else + #define _EDMA_CCER_CCE_MASK 0x00000F00u + #define _EDMA_CCER_CCE_SHIFT 0x00000008u + #define EDMA_CCER_CCE_DEFAULT 0x00000000u + #define EDMA_CCER_CCE_OF(x) _VALUEOF(x) +#endif + + #define EDMA_CCER_OF(x) _VALUEOF(x) + + #define EDMA_CCER_DEFAULT (Uint32)(\ + _PER_FDEFAULT(EDMA,CCER,CCE)\ + ) + + #define EDMA_CCER_RMK(cce) (Uint32)(\ + _PER_FMK(EDMA,CCER,CCE,cce)\ + ) + + #define _EDMA_CCER_FGET(FIELD)\ + _PER_FGET(_EDMA_CCER_ADDR,EDMA,CCER,##FIELD) + + #define _EDMA_CCER_FSET(FIELD,field)\ + _PER_FSET(_EDMA_CCER_ADDR,EDMA,CCER,##FIELD,field) + + #define _EDMA_CCER_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_CCER_ADDR,EDMA,CCER,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | C C E R L | +* |___________________| +* +* CCERL - channel chain enable register, low half (1) +* +* (1) - C64x devices only +* +* FIELDS (msb -> lsb) +* (rw) CCE +* +\******************************************************************************/ +#if (C64_SUPPORT) + #define _EDMA_CCERL_ADDR 0x01A0FFECu + + #define EDMA_CCERL EDMA_REG(CCERL) + + #define _EDMA_CCERL_CCE_MASK 0xFFFFFFFFu + #define _EDMA_CCERL_CCE_SHIFT 0x00000000u + #define EDMA_CCERL_CCE_DEFAULT 0x00000000u + #define EDMA_CCERL_CCE_OF(x) _VALUEOF(x) + + #define EDMA_CCERL_OF(x) _VALUEOF(x) + + #define EDMA_CCERL_DEFAULT (Uint32)(\ + _PER_FDEFAULT(EDMA,CCERL,CCE)\ + ) + + #define EDMA_CCERL_RMK(cce) (Uint32)(\ + _PER_FMK(EDMA,CCERL,CCE,cce)\ + ) + + #define _EDMA_CCERL_FGET(FIELD)\ + _PER_FGET(_EDMA_CCERL_ADDR,EDMA,CCERL,##FIELD) + + #define _EDMA_CCERL_FSET(FIELD,field)\ + _PER_FSET(_EDMA_CCERL_ADDR,EDMA,CCERL,##FIELD,field) + + #define _EDMA_CCERL_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_CCERL_ADDR,EDMA,CCERL,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* _____________________ +* | | +* | C C E R H | +* |___________________| +* +* CCERH - channel chain enable register, high half (1) +* +* (1) - C64x devices only +* +* FIELDS (msb -> lsb) +* (rw) CCE +* +\******************************************************************************/ +#if (C64_SUPPORT) + #define _EDMA_CCERH_ADDR 0x01A0FFACu + + #define EDMA_CCERH EDMA_REG(CCERH) + + #define _EDMA_CCERH_CCE_MASK 0xFFFFFFFFu + #define _EDMA_CCERH_CCE_SHIFT 0x00000000u + #define EDMA_CCERH_CCE_DEFAULT 0x00000000u + #define EDMA_CCERH_CCE_OF(x) _VALUEOF(x) + + #define EDMA_CCERH_OF(x) _VALUEOF(x) + + #define EDMA_CCERH_DEFAULT (Uint32)(\ + _PER_FDEFAULT(EDMA,CCERH,CCE)\ + ) + + #define EDMA_CCERH_RMK(cce) (Uint32)(\ + _PER_FMK(EDMA,CCERH,CCE,cce)\ + ) + + #define _EDMA_CCERH_FGET(FIELD)\ + _PER_FGET(_EDMA_CCERH_ADDR,EDMA,CCERH,##FIELD) + + #define _EDMA_CCERH_FSET(FIELD,field)\ + _PER_FSET(_EDMA_CCERH_ADDR,EDMA,CCERH,##FIELD,field) + + #define _EDMA_CCERH_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_CCERH_ADDR,EDMA,CCERH,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* _____________________ +* | | +* | E R | +* |___________________| +* +* ER - event register +* +* FIELDS (msb -> lsb) +* (r) EVT +* +\******************************************************************************/ + #define _EDMA_ER_ADDR 0x01A0FFF0u + + #define EDMA_ER EDMA_REG(ER) + +#if (C64_SUPPORT) + #define _EDMA_ER_EVT_MASK 0xFFFFFFFFu + #define _EDMA_ER_EVT_SHIFT 0x00000000u + #define EDMA_ER_EVT_DEFAULT 0x00000000u + #define EDMA_ER_EVT_OF(x) _VALUEOF(x) +#else + #define _EDMA_ER_EVT_MASK 0x0000FFFFu + #define _EDMA_ER_EVT_SHIFT 0x00000000u + #define EDMA_ER_EVT_DEFAULT 0x00000000u + #define EDMA_ER_EVT_OF(x) _VALUEOF(x) +#endif + + #define EDMA_ER_OF(x) _VALUEOF(x) + + #define EDMA_ER_DEFAULT (Uint32)(\ + _PER_FDEFAULT(EDMA,ER,EVT)\ + ) + + #define _EDMA_ER_FGET(FIELD)\ + _PER_FGET(_EDMA_ER_ADDR,EDMA,ER,##FIELD) + +/******************************************************************************\ +* _____________________ +* | | +* | E R L | +* |___________________| +* +* ERL - event register, low half (1) +* +* (1) - C64x devices only +* +* FIELDS (msb -> lsb) +* (r) EVT +* +\******************************************************************************/ +#if (C64_SUPPORT) + #define _EDMA_ERL_ADDR 0x01A0FFF0u + + #define EDMA_ERL EDMA_REG(ERL) + + #define _EDMA_ERL_EVT_MASK 0xFFFFFFFFu + #define _EDMA_ERL_EVT_SHIFT 0x00000000u + #define EDMA_ERL_EVT_DEFAULT 0x00000000u + #define EDMA_ERL_EVT_OF(x) _VALUEOF(x) + + #define EDMA_ERL_OF(x) _VALUEOF(x) + + #define EDMA_ERL_DEFAULT (Uint32)(\ + _PERL_FDEFAULT(EDMA,ERL,EVT)\ + ) + + #define _EDMA_ERL_FGET(FIELD)\ + _PERL_FGET(_EDMA_ERL_ADDR,EDMA,ERL,FIELD) + +#endif + + +/******************************************************************************\ +* _____________________ +* | | +* | E R H | +* |___________________| +* +* ERH - event register, high half (1) +* +* (1) - C64x devices only +* +* FIELDS (msb -> lsb) +* (r) EVT +* +\******************************************************************************/ +#if (C64_SUPPORT) + #define _EDMA_ERH_ADDR 0x01A0FFB0u + + #define EDMA_ERH EDMA_REG(ERH) + + #define _EDMA_ERH_EVT_MASK 0xFFFFFFFFu + #define _EDMA_ERH_EVT_SHIFT 0x00000000u + #define EDMA_ERH_EVT_DEFAULT 0x00000000u + #define EDMA_ERH_EVT_OF(x) _VALUEOF(x) + + #define EDMA_ERH_OF(x) _VALUEOF(x) + + #define EDMA_ERH_DEFAULT (Uint32)(\ + _PERH_FDEFAULT(EDMA,ERH,EVT)\ + ) + + #define _EDMA_ERH_FGET(FIELD)\ + _PERH_FGET(_EDMA_ERH_ADDR,EDMA,ERH,FIELD) + +#endif + + +/******************************************************************************\ +* _____________________ +* | | +* | E E R | +* |___________________| +* +* EER - event enable register +* +* FIELDS (msb -> lsb) +* (rw) EE +* +\******************************************************************************/ + #define _EDMA_EER_ADDR 0x01A0FFF4u + + #define EDMA_EER EDMA_REG(EER) + +#if (C64_SUPPORT) + #define _EDMA_EER_EE_MASK 0xFFFFFFFFu + #define _EDMA_EER_EE_SHIFT 0x00000000u + #define EDMA_EER_EE_DEFAULT 0x00000000u + #define EDMA_EER_EE_OF(x) _VALUEOF(x) +#else + #define _EDMA_EER_EE_MASK 0x0000FFFFu + #define _EDMA_EER_EE_SHIFT 0x00000000u + #define EDMA_EER_EE_DEFAULT 0x00000000u + #define EDMA_EER_EE_OF(x) _VALUEOF(x) +#endif + + #define EDMA_EER_OF(x) _VALUEOF(x) + + #define EDMA_EER_DEFAULT (Uint32)(\ + _PER_FDEFAULT(EDMA,EER,EE)\ + ) + + #define EDMA_EER_RMK(ee) (Uint32)(\ + _PER_FMK(EDMA,EER,EE,ee)\ + ) + + #define _EDMA_EER_FGET(FIELD)\ + _PER_FGET(_EDMA_EER_ADDR,EDMA,EER,##FIELD) + + #define _EDMA_EER_FSET(FIELD,field)\ + _PER_FSET(_EDMA_EER_ADDR,EDMA,EER,##FIELD,field) + + #define _EDMA_EER_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_EER_ADDR,EDMA,EER,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | E E R L | +* |___________________| +* +* EERL - event enable register, low half (1) +* +* (1) - C64x devices only +* +* FIELDS (msb -> lsb) +* (rw) EE +* +\******************************************************************************/ +#if (C64_SUPPORT) + #define _EDMA_EERL_ADDR 0x01A0FFF4u + + #define EDMA_EERL EDMA_REG(EERL) + + #define _EDMA_EERL_EE_MASK 0xFFFFFFFFu + #define _EDMA_EERL_EE_SHIFT 0x00000000u + #define EDMA_EERL_EE_DEFAULT 0x00000000u + #define EDMA_EERL_EE_OF(x) _VALUEOF(x) + + #define EDMA_EERL_OF(x) _VALUEOF(x) + + #define EDMA_EERL_DEFAULT (Uint32)(\ + _PER_FDEFAULT(EDMA,EERL,EE)\ + ) + + #define EDMA_EERL_RMK(ee) (Uint32)(\ + _PER_FMK(EDMA,EERL,EE,ee)\ + ) + + #define _EDMA_EERL_FGET(FIELD)\ + _PER_FGET(_EDMA_EERL_ADDR,EDMA,EERL,##FIELD) + + #define _EDMA_EERL_FSET(FIELD,field)\ + _PER_FSET(_EDMA_EERL_ADDR,EDMA,EERL,##FIELD,field) + + #define _EDMA_EERL_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_EERL_ADDR,EDMA,EERL,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* _____________________ +* | | +* | E E R H | +* |___________________| +* +* EERH - event enable register, high half (1) +* +* (1) - C64x devices only +* +* FIELDS (msb -> lsb) +* (rw) EE +* +\******************************************************************************/ +#if (C64_SUPPORT) + #define _EDMA_EERH_ADDR 0x01A0FFB4u + + #define EDMA_EERH EDMA_REG(EERH) + + #define _EDMA_EERH_EE_MASK 0xFFFFFFFFu + #define _EDMA_EERH_EE_SHIFT 0x00000000u + #define EDMA_EERH_EE_DEFAULT 0x00000000u + #define EDMA_EERH_EE_OF(x) _VALUEOF(x) + + #define EDMA_EERH_OF(x) _VALUEOF(x) + + #define EDMA_EERH_DEFAULT (Uint32)(\ + _PER_FDEFAULT(EDMA,EERH,EE)\ + ) + + #define EDMA_EERH_RMK(ee) (Uint32)(\ + _PER_FMK(EDMA,EERH,EE,ee)\ + ) + + #define _EDMA_EERH_FGET(FIELD)\ + _PER_FGET(_EDMA_EERH_ADDR,EDMA,EERH,##FIELD) + + #define _EDMA_EERH_FSET(FIELD,field)\ + _PER_FSET(_EDMA_EERH_ADDR,EDMA,EERH,##FIELD,field) + + #define _EDMA_EERH_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_EERH_ADDR,EDMA,EERH,##FIELD,##SYM) +#endif + +/******************************************************************************\ +* _____________________ +* | | +* | E P R L | +* |___________________| +* +* EPRL - event polarity register, low half (1) +* +* (1) - C64x devices only +* +* FIELDS (msb -> lsb) +* (rw) EP +* +\******************************************************************************/ +#if (C64_SUPPORT) + #define _EDMA_EPRL_ADDR 0x01A0FFDCu + + #define EDMA_EPRL EDMA_REG(EPRL) + + #define _EDMA_EPRL_EP_MASK 0xFFFFFFFFu + #define _EDMA_EPRL_EP_SHIFT 0x00000000u + #define EDMA_EPRL_EP_DEFAULT 0x00000000u + #define EDMA_EPRL_EP_OF(x) _VALUEOF(x) + + #define EDMA_EPRL_OF(x) _VALUEOF(x) + + #define EDMA_EPRL_DEFAULT (Uint32)(\ + _PER_FDEFAULT(EDMA,EPRL,EP)\ + ) + + #define EDMA_EPRL_RMK(ep) (Uint32)(\ + _PER_FMK(EDMA,EPRL,EP,ep)\ + ) + + #define _EDMA_EPRL_FGET(FIELD)\ + _PER_FGET(_EDMA_EPRL_ADDR,EDMA,EPRL,##FIELD) + + #define _EDMA_EPRL_FSET(FIELD,field)\ + _PER_FSET(_EDMA_EPRL_ADDR,EDMA,EPRL,##FIELD,field) + + #define _EDMA_EPRL_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_EPRL_ADDR,EDMA,EPRL,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* _____________________ +* | | +* | E E R H | +* |___________________| +* +* EPRH - event enable register, high half (1) +* +* (1) - C64x devices only +* +* FIELDS (msb -> lsb) +* (rw) EP +* +\******************************************************************************/ +#if (C64_SUPPORT) + #define _EDMA_EPRH_ADDR 0x01A0FF9Cu + + #define EDMA_EPRH EDMA_REG(EPRH) + + #define _EDMA_EPRH_EP_MASK 0xFFFFFFFFu + #define _EDMA_EPRH_EP_SHIFT 0x00000000u + #define EDMA_EPRH_EP_DEFAULT 0x00000000u + #define EDMA_EPRH_EP_OF(x) _VALUEOF(x) + + #define EDMA_EPRH_OF(x) _VALUEOF(x) + + #define EDMA_EPRH_DEFAULT (Uint32)(\ + _PER_FDEFAULT(EDMA,EPRH,EP)\ + ) + + #define EDMA_EPRH_RMK(ep) (Uint32)(\ + _PER_FMK(EDMA,EPRH,EP,ep)\ + ) + + #define _EDMA_EPRH_FGET(FIELD)\ + _PER_FGET(_EDMA_EPRH_ADDR,EDMA,EPRH,##FIELD) + + #define _EDMA_EPRH_FSET(FIELD,field)\ + _PER_FSET(_EDMA_EPRH_ADDR,EDMA,EPRH,##FIELD,field) + + #define _EDMA_EPRH_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_EPRH_ADDR,EDMA,EPRH,##FIELD,##SYM) +#endif + +/******************************************************************************\ +* _____________________ +* | | +* | E C R | +* |___________________| +* +* ECR - event clear register +* +* FIELDS (msb -> lsb) +* (rw) EC +* +\******************************************************************************/ + #define _EDMA_ECR_ADDR 0x01A0FFF8u + + #define EDMA_ECR EDMA_REG(ECR) + +#if (C64_SUPPORT) + #define _EDMA_ECR_EC_MASK 0xFFFFFFFFu + #define _EDMA_ECR_EC_SHIFT 0x00000000u + #define EDMA_ECR_EC_DEFAULT 0x00000000u + #define EDMA_ECR_EC_OF(x) _VALUEOF(x) +#else + #define _EDMA_ECR_EC_MASK 0x0000FFFFu + #define _EDMA_ECR_EC_SHIFT 0x00000000u + #define EDMA_ECR_EC_DEFAULT 0x00000000u + #define EDMA_ECR_EC_OF(x) _VALUEOF(x) +#endif + + #define EDMA_EPR_OF(x) _VALUEOF(x) + + #define EDMA_ECR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(EDMA,ECR,EC)\ + ) + + #define EDMA_ECR_RMK(ec) (Uint32)(\ + _PER_FMK(EDMA,ECR,EC,ec)\ + ) + + #define _EDMA_ECR_FGET(FIELD)\ + _PER_FGET(_EDMA_ECR_ADDR,EDMA,ECR,##FIELD) + + #define _EDMA_ECR_FSET(FIELD,field)\ + _PER_FSET(_EDMA_ECR_ADDR,EDMA,ECR,##FIELD,field) + + #define _EDMA_ECR_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_ECR_ADDR,EDMA,ECR,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | E C R L | +* |___________________| +* +* ECRL - event clear register, low half (1) +* +* (1) - C64x devices only +* +* FIELDS (msb -> lsb) +* (rw) EC +* +\******************************************************************************/ +#if (C64_SUPPORT) + #define _EDMA_ECRL_ADDR 0x01A0FFF8u + + #define EDMA_ECRL EDMA_REG(ECRL) + + #define _EDMA_ECRL_EC_MASK 0xFFFFFFFFu + #define _EDMA_ECRL_EC_SHIFT 0x00000000u + #define EDMA_ECRL_EC_DEFAULT 0x00000000u + #define EDMA_ECRL_EC_OF(x) _VALUEOF(x) + + #define EDMA_EER_OF(x) _VALUEOF(x) + + #define EDMA_ECRL_DEFAULT (Uint32)(\ + _PER_FDEFAULT(EDMA,ECRL,EC)\ + ) + + #define EDMA_ECRL_RMK(ec) (Uint32)(\ + _PER_FMK(EDMA,ECRL,EC,ec)\ + ) + + #define _EDMA_ECRL_FGET(FIELD)\ + _PER_FGET(_EDMA_ECRL_ADDR,EDMA,ECRL,##FIELD) + + #define _EDMA_ECRL_FSET(FIELD,field)\ + _PER_FSET(_EDMA_ECRL_ADDR,EDMA,ECRL,##FIELD,field) + + #define _EDMA_ECRL_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_ECRL_ADDR,EDMA,ECRL,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* _____________________ +* | | +* | E C R H | +* |___________________| +* +* ECRH - event clear register, high half (1) +* +* (1) - C64x devices only +* +* FIELDS (msb -> lsb) +* (rw) EC +* +\******************************************************************************/ +#if (C64_SUPPORT) + #define _EDMA_ECRH_ADDR 0x01A0FFB8u + + #define EDMA_ECRH EDMA_REG(ECRH) + + #define _EDMA_ECRH_EC_MASK 0xFFFFFFFFu + #define _EDMA_ECRH_EC_SHIFT 0x00000000u + #define EDMA_ECRH_EC_DEFAULT 0x00000000u + #define EDMA_ECRH_EC_OF(x) _VALUEOF(x) + + #define EDMA_EER_OF(x) _VALUEOF(x) + + #define EDMA_ECRH_DEFAULT (Uint32)(\ + _PER_FDEFAULT(EDMA,ECRH,EC)\ + ) + + #define EDMA_ECRH_RMK(ec) (Uint32)(\ + _PER_FMK(EDMA,ECRH,EC,ec)\ + ) + + #define _EDMA_ECRH_FGET(FIELD)\ + _PER_FGET(_EDMA_ECRH_ADDR,EDMA,ECRH,##FIELD) + + #define _EDMA_ECRH_FSET(FIELD,field)\ + _PER_FSET(_EDMA_ECRH_ADDR,EDMA,ECRH,##FIELD,field) + + #define _EDMA_ECRH_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_ECRH_ADDR,EDMA,ECRH,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* _____________________ +* | | +* | E S R | +* |___________________| +* +* ESR - event set register +* +* FIELDS (msb -> lsb) +* (rw) ES +* +\******************************************************************************/ + #define _EDMA_ESR_ADDR 0x01A0FFFCu + + #define EDMA_ESR EDMA_REG(ESR) + +#if (C64_SUPPORT) + #define _EDMA_ESR_ES_MASK 0xFFFFFFFFu + #define _EDMA_ESR_ES_SHIFT 0x00000000u + #define EDMA_ESR_ES_DEFAULT 0x00000000u + #define EDMA_ESR_ES_OF(x) _VALUEOF(x) +#else + #define _EDMA_ESR_ES_MASK 0x0000FFFFu + #define _EDMA_ESR_ES_SHIFT 0x00000000u + #define EDMA_ESR_ES_DEFAULT 0x00000000u + #define EDMA_ESR_ES_OF(x) _VALUEOF(x) +#endif + + #define EDMA_ESR_OF(x) _VALUEOF(x) + + #define EDMA_ESR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(EDMA,ESR,ES)\ + ) + + #define EDMA_ESR_RMK(es) (Uint32)(\ + _PER_FMK(EDMA,ESR,ES,es)\ + ) + + #define _EDMA_ESR_FGET(FIELD)\ + _PER_FGET(_EDMA_ESR_ADDR,EDMA,ESR,##FIELD) + + #define _EDMA_ESR_FSET(FIELD,field)\ + _PER_FSET(_EDMA_ESR_ADDR,EDMA,ESR,##FIELD,field) + + #define _EDMA_ESR_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_ESR_ADDR,EDMA,ESR,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | E S R L | +* |___________________| +* +* ESRL - event set register, low half (1) +* +* (1) - C64x devices only +* +* FIELDS (msb -> lsb) +* (rw) ES +* +\******************************************************************************/ +#if (C64_SUPPORT) + #define _EDMA_ESRL_ADDR 0x01A0FFFCu + + #define EDMA_ESRL EDMA_REG(ESRL) + + #define _EDMA_ESRL_ES_MASK 0xFFFFFFFFu + #define _EDMA_ESRL_ES_SHIFT 0x00000000u + #define EDMA_ESRL_ES_DEFAULT 0x00000000u + #define EDMA_ESRL_ES_OF(x) _VALUEOF(x) + + #define EDMA_ESRL_OF(x) _VALUEOF(x) + + #define EDMA_ESRL_DEFAULT (Uint32)(\ + _PER_FDEFAULT(EDMA,ESRL,ES)\ + ) + + #define EDMA_ESRL_RMK(es) (Uint32)(\ + _PER_FMK(EDMA,ESRL,ES,es)\ + ) + + #define _EDMA_ESRL_FGET(FIELD)\ + _PER_FGET(_EDMA_ESRL_ADDR,EDMA,ESRL,##FIELD) + + #define _EDMA_ESRL_FSET(FIELD,field)\ + _PER_FSET(_EDMA_ESRL_ADDR,EDMA,ESRL,##FIELD,field) + + #define _EDMA_ESRL_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_ESRL_ADDR,EDMA,ESRL,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* _____________________ +* | | +* | E S R H | +* |___________________| +* +* ESRH - event set register, high half (1) +* +* (1) - C64x devices only +* +* FIELDS (msb -> lsb) +* (rw) ES +* +\******************************************************************************/ +#if (C64_SUPPORT) + #define _EDMA_ESRH_ADDR 0x01A0FFBCu + + #define EDMA_ESRH EDMA_REG(ESRH) + + #define _EDMA_ESRH_ES_MASK 0xFFFFFFFFu + #define _EDMA_ESRH_ES_SHIFT 0x00000000u + #define EDMA_ESRH_ES_DEFAULT 0x00000000u + #define EDMA_ESRH_ES_OF(x) _VALUEOF(x) + + #define EDMA_ESRH_OF(x) _VALUEOF(x) + + #define EDMA_ESRH_DEFAULT (Uint32)(\ + _PER_FDEFAULT(EDMA,ESRH,ES)\ + ) + + #define EDMA_ESRH_RMK(es) (Uint32)(\ + _PER_FMK(EDMA,ESRH,ES,es)\ + ) + + #define _EDMA_ESRH_FGET(FIELD)\ + _PER_FGET(_EDMA_ESRH_ADDR,EDMA,ESRH,##FIELD) + + #define _EDMA_ESRH_FSET(FIELD,field)\ + _PER_FSET(_EDMA_ESRH_ADDR,EDMA,ESRH,##FIELD,field) + + #define _EDMA_ESRH_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_ESRH_ADDR,EDMA,ESRH,##FIELD,##SYM) +#endif + +/******************************************************************************\ +* _____________________ +* | | +* | E S E L 0 | +* |___________________| +* +* ESEL0 - event selection register 0 +* +* FIELDS (msb -> lsb) +* (rw) EVTSEL3 +* (rw) EVTSEL2 +* (rw) EVTSEL1 +* (rw) EVTSEL0 +* +\******************************************************************************/ +#if (CHIP_6713 || CHIP_DA610 || CHIP_6711C || CHIP_6712C) + #define _EDMA_ESEL0_ADDR 0x01A0FF00u + + #define EDMA_ESEL0 EDMA_REG(ESEL0) + + #define _EDMA_ESEL0_EVTSEL0_MASK 0x0000003Fu + #define _EDMA_ESEL0_EVTSEL0_SHIFT 0x00000000u + #define EDMA_ESEL0_EVTSEL0_DEFAULT 0x00000000u + #define EDMA_ESEL0_EVTSEL0_OF(x) _VALUEOF(x) + + #define _EDMA_ESEL0_EVTSEL1_MASK 0x00003F00u + #define _EDMA_ESEL0_EVTSEL1_SHIFT 0x00000008u + #define EDMA_ESEL0_EVTSEL1_DEFAULT 0x00000001u + #define EDMA_ESEL0_EVTSEL1_OF(x) _VALUEOF(x) + + #define _EDMA_ESEL0_EVTSEL2_MASK 0x003F0000u + #define _EDMA_ESEL0_EVTSEL2_SHIFT 0x00000010u + #define EDMA_ESEL0_EVTSEL2_DEFAULT 0x00000002u + #define EDMA_ESEL0_EVTSEL2_OF(x) _VALUEOF(x) + + #define _EDMA_ESEL0_EVTSEL3_MASK 0x3F000000u + #define _EDMA_ESEL0_EVTSEL3_SHIFT 0x00000018u + #define EDMA_ESEL0_EVTSEL3_DEFAULT 0x00000003u + #define EDMA_ESEL0_EVTSEL3_OF(x) _VALUEOF(x) + + #define EDMA_ESEL0_OF(x) _VALUEOF(x) + + #define EDMA_ESEL0_DEFAULT (Uint32)(\ + _PER_FDEFAULT(EDMA,ESEL0,EVTSEL0)\ + |_PER_FDEFAULT(EDMA,ESEL0,EVTSEL1)\ + |_PER_FDEFAULT(EDMA,ESEL0,EVTSEL2)\ + |_PER_FDEFAULT(EDMA,ESEL0,EVTSEL3)\ + ) + + #define EDMA_ESEL0_RMK(evtsel0, evtsel1, evtsel2, evtsel3) (Uint32)(\ + _PER_FMK(EDMA,ESEL0,EVTSEL0,evtsel0)\ + |_PER_FMK(EDMA,ESEL0,EVTSEL1,evtsel1)\ + |_PER_FMK(EDMA,ESEL0,EVTSEL2,evtsel2)\ + |_PER_FMK(EDMA,ESEL0,EVTSEL3,evtsel3)\ + ) + + #define _EDMA_ESEL0_FGET(FIELD)\ + _PER_FGET(_EDMA_ESEL0_ADDR,EDMA,ESEL0,##FIELD) + + #define _EDMA_ESEL0_FSET(FIELD,field)\ + _PER_FSET(_EDMA_ESEL0_ADDR,EDMA,ESEL0,##FIELD,field) + + #define _EDMA_ESEL0_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_ESEL0_ADDR,EDMA,ESEL0,##FIELD,##SYM) + +#endif + +/******************************************************************************\ +* _____________________ +* | | +* | E S E L 1 | +* |___________________| +* +* ESEL1 - event selection register 1 +* +* FIELDS (msb -> lsb) +* (rw) EVTSEL7 +* (rw) EVTSEL6 +* (rw) EVTSEL5 +* (rw) EVTSEL4 +* +\******************************************************************************/ +#if (CHIP_6713 || CHIP_DA610 || CHIP_6711C || CHIP_6712C) + #define _EDMA_ESEL1_ADDR 0x01A0FF04u + + #define EDMA_ESEL1 EDMA_REG(ESEL1) + + #define _EDMA_ESEL1_EVTSEL4_MASK 0x0000003Fu + #define _EDMA_ESEL1_EVTSEL4_SHIFT 0x00000000u + #define EDMA_ESEL1_EVTSEL4_DEFAULT 0x00000004u + #define EDMA_ESEL1_EVTSEL4_OF(x) _VALUEOF(x) + + #define _EDMA_ESEL1_EVTSEL5_MASK 0x00003F00u + #define _EDMA_ESEL1_EVTSEL5_SHIFT 0x00000008u + #define EDMA_ESEL1_EVTSEL5_DEFAULT 0x00000005u + #define EDMA_ESEL1_EVTSEL5_OF(x) _VALUEOF(x) + + #define _EDMA_ESEL1_EVTSEL6_MASK 0x003F0000u + #define _EDMA_ESEL1_EVTSEL6_SHIFT 0x00000010u + #define EDMA_ESEL1_EVTSEL6_DEFAULT 0x00000006u + #define EDMA_ESEL1_EVTSEL6_OF(x) _VALUEOF(x) + + #define _EDMA_ESEL1_EVTSEL7_MASK 0x3F000000u + #define _EDMA_ESEL1_EVTSEL7_SHIFT 0x00000018u + #define EDMA_ESEL1_EVTSEL7_DEFAULT 0x00000007u + #define EDMA_ESEL1_EVTSEL7_OF(x) _VALUEOF(x) + + #define EDMA_ESEL1_OF(x) _VALUEOF(x) + + #define EDMA_ESEL1_DEFAULT (Uint32)(\ + _PER_FDEFAULT(EDMA,ESEL1,EVTSEL4)\ + |_PER_FDEFAULT(EDMA,ESEL1,EVTSEL5)\ + |_PER_FDEFAULT(EDMA,ESEL1,EVTSEL6)\ + |_PER_FDEFAULT(EDMA,ESEL1,EVTSEL7)\ + ) + + #define EDMA_ESEL1_RMK(evtsel4, evtsel5, evtsel6, evtsel7) (Uint32)(\ + _PER_FMK(EDMA,ESEL1,EVTSEL4,evtsel4)\ + |_PER_FMK(EDMA,ESEL1,EVTSEL5,evtsel5)\ + |_PER_FMK(EDMA,ESEL1,EVTSEL6,evtsel6)\ + |_PER_FMK(EDMA,ESEL1,EVTSEL7,evtsel7)\ + ) + + #define _EDMA_ESEL1_FGET(FIELD)\ + _PER_FGET(_EDMA_ESEL1_ADDR,EDMA,ESEL1,##FIELD) + + #define _EDMA_ESEL1_FSET(FIELD,field)\ + _PER_FSET(_EDMA_ESEL1_ADDR,EDMA,ESEL1,##FIELD,field) + + #define _EDMA_ESEL1_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_ESEL1_ADDR,EDMA,ESEL1,##FIELD,##SYM) + +#endif + +/******************************************************************************\ +* _____________________ +* | | +* | E S E L 3 | +* |___________________| +* +* ESEL3 - event selection register 3 +* +* FIELDS (msb -> lsb) +* (rw) EVTSEL15 +* (rw) EVTSEL14 +* (rw) EVTSEL13 +* (rw) EVTSEL12 +* +\******************************************************************************/ +#if (CHIP_6713 || CHIP_DA610 || CHIP_6711C || CHIP_6712C) + #define _EDMA_ESEL3_ADDR 0x01A0FF0Cu + + #define EDMA_ESEL3 EDMA_REG(ESEL3) + + #define _EDMA_ESEL3_EVTSEL12_MASK 0x0000003Fu + #define _EDMA_ESEL3_EVTSEL12_SHIFT 0x00000000u + #define EDMA_ESEL3_EVTSEL12_DEFAULT 0x0000000Cu + #define EDMA_ESEL3_EVTSEL12_OF(x) _VALUEOF(x) + + #define _EDMA_ESEL3_EVTSEL13_MASK 0x00003F00u + #define _EDMA_ESEL3_EVTSEL13_SHIFT 0x00000008u + #define EDMA_ESEL3_EVTSEL13_DEFAULT 0x0000000Du + #define EDMA_ESEL3_EVTSEL13_OF(x) _VALUEOF(x) + + #define _EDMA_ESEL3_EVTSEL14_MASK 0x003F0000u + #define _EDMA_ESEL3_EVTSEL14_SHIFT 0x00000010u + #define EDMA_ESEL3_EVTSEL14_DEFAULT 0x0000000Eu + #define EDMA_ESEL3_EVTSEL14_OF(x) _VALUEOF(x) + + #define _EDMA_ESEL3_EVTSEL15_MASK 0x3F000000u + #define _EDMA_ESEL3_EVTSEL15_SHIFT 0x00000018u + #define EDMA_ESEL3_EVTSEL15_DEFAULT 0x0000000Fu + #define EDMA_ESEL3_EVTSEL15_OF(x) _VALUEOF(x) + + #define EDMA_ESEL3_OF(x) _VALUEOF(x) + + #define EDMA_ESEL3_DEFAULT (Uint32)(\ + _PER_FDEFAULT(EDMA,ESEL3,EVTSEL12)\ + |_PER_FDEFAULT(EDMA,ESEL3,EVTSEL13)\ + |_PER_FDEFAULT(EDMA,ESEL3,EVTSEL14)\ + |_PER_FDEFAULT(EDMA,ESEL3,EVTSEL15)\ + ) + + #define EDMA_ESEL3_RMK(evtsel12, evtsel13, evtsel14, evtsel15) (Uint32)(\ + _PER_FMK(EDMA,ESEL3,EVTSEL12,evtsel12)\ + |_PER_FMK(EDMA,ESEL3,EVTSEL13,evtsel13)\ + |_PER_FMK(EDMA,ESEL3,EVTSEL14,evtsel14)\ + |_PER_FMK(EDMA,ESEL3,EVTSEL15,evtsel15)\ + ) + + #define _EDMA_ESEL3_FGET(FIELD)\ + _PER_FGET(_EDMA_ESEL3_ADDR,EDMA,ESEL3,##FIELD) + + #define _EDMA_ESEL3_FSET(FIELD,field)\ + _PER_FSET(_EDMA_ESEL3_ADDR,EDMA,ESEL3,##FIELD,field) + + #define _EDMA_ESEL3_FSETS(FIELD,SYM)\ + _PER_FSETS(_EDMA_ESEL3_ADDR,EDMA,ESEL3,##FIELD,##SYM) + +#endif + +/*----------------------------------------------------------------------------*/ + +#endif /* (EDMA_SUPPORT) */ +#endif /* _CSL_EDMAHAL_H_ */ +/******************************************************************************\ +* End of csl_edmahal.h +\******************************************************************************/ diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_emac.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_emac.h new file mode 100644 index 0000000..9c9c710 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_emac.h @@ -0,0 +1,598 @@ +/*****************************************************************************\ +* Copyright (C) 1999-2003 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_emac.h +* DATE CREATED.. 02/08/2002 +* LAST MODIFIED. 04/24/2003 +*------------------------------------------------------------------------------ +* NOTE: +* When used in an multitasking environment, no EMAC function may be +* called while another EMAC function is operating on the same device +* handle in another thread. It is the responsibility of the application +* to assure adherence to this restriction. +* +\******************************************************************************/ +#ifndef _CSL_EMAC_H +#define _CSL_EMAC_H_ + +/* Include the main CSL file */ +#include + +#include + +#if (EMAC_SUPPORT) +/*-----------------------------------------------------------------------*\ +* NEW TYPES +\*-----------------------------------------------------------------------*/ +#ifndef _CSL_EMAC_TYPES +#define _CSL_EMAC_TYPES +typedef unsigned int uint; +typedef void * Handle; +#endif + +/*-----------------------------------------------------------------------*\ +* STANDARD DATA STRUCTURES +\*-----------------------------------------------------------------------*/ + +/*-----------------------------------------------------------------------*\ +* EMAC_Pkt +* +* The packet structure defines the basic unit of memory used to hold data +* packets for the EMAC device. +* +* A packet is comprised of one or more packet buffers. Each packet buffer +* contains a packet buffer header, and a pointer to the buffer data. +* The EMAC_Pkt structure defines the packet buffer header. +* +* The pDataBuffer field points to the packet data. This is set when the +* buffer is allocated, and is not altered. +* +* BufferLen holds the the total length of the data buffer that is used to +* store the packet (or packet fragment). This size is set by the entity +* that originally allocates the buffer, and is not altered. +* +* The Flags field contains additional information about the packet +* +* ValidLen holds the length of the valid data currently contained in the +* data buffer. +* +* DataOffset is the byte offset from the start of the data buffer to the +* first byte of valid data. Thus (ValidLen+DataOffet)<=BufferLen. +* +* Note that for receive buffer packets, the DataOffset field may be +* assigned before there is any valid data in the packet buffer. This allows +* the application to reserve space at the top of data buffer for private +* use. In all instances, the DataOffset field must be valid for all packets +* handled by EMAC. +* +* The data portion of the packet buffer represents a packet or a fragment +* of a larger packet. This is determined by the Flags parameter. At the +* start of every packet, the SOP bit is set in Flags. If the EOP bit is +* also set, then the packet is not fragmented. Otherwise; the next packet +* structure pointed to by the pNext field will contain the next fragment in +* the packet. On either type of buffer, when the SOP bit is set in Flags, +* then the PktChannel, PktLength, and PktFrags fields must also be valid. +* These fields contain additional information about the packet. +* +* The PktChannel field detetmines what channel the packet has arrived on, +* or what channel it should be transmitted on. The EMAC library supports +* only a single receive channel, but allows for up to eight transmit +* channels. Transmit channels can be treated as round-robin or priority +* queues. +* +* The PktLength field holds the size of the entire packet. On single frag +* packets (both SOP and EOP set in BufFlags), PktLength and ValidLen will +* be equal. +* +* The PktFrags field holds the number of fragments (EMAC_Pkt records) used +* to describe the packet. If more than 1 frag is present, the first record +* must have EMAC_PKT_FLAGS_SOP flag set, with corresponding fields validated. +* Each frag/record must be linked list using the pNext field, and the final +* frag/record must have EMAC_PKT_FLAGS_EOP flag set and pNext=0. +* +* In systems where the packet resides in cacheable memory, the data buffer +* must start on a cache line boundary and be an even multiple of cache +* lines in size. The EMAC_Pkt header must not appear in the same cache line +* as the data portion of the packet. On multi-fragment packets, some packet +* fragments may reside in cacheable memory where others do not. +* +* ** NOTE: It is up to the caller to assure that all packet buffers ** +* ** residing in cacheable memory are not currently stored in L1 or L2 ** +* ** cache when passed to any EMAC function ** +* +* Some of the packet Flags can only be set if the device is in the +* proper configuration to receive the corresponding frames. In order to +* enable these flags, the following modes must be set: +* RxCrc Flag : RXCRC Mode in EMAC_Config +* RxErr Flags : PASSERROR Mode in EMAC_Config +* RxCtl Flags : PASSCONTROL Mode in EMAC_Config +* RxPrm Flag : EMAC_RXFILTER_ALL in EMAC_setReceiveFilter() +* +\*-----------------------------------------------------------------------*/ +typedef struct _EMAC_Pkt { + Uint32 AppPrivate; /* For use by the application */ + struct _EMAC_Pkt *pPrev; /* Previous record */ + struct _EMAC_Pkt *pNext; /* Next record */ + Uint8 *pDataBuffer; /* Pointer to Data Buffer (read only) */ + Uint32 BufferLen; /* Physical Length of buffer (read only) */ + Uint32 Flags; /* Packet Flags */ + Uint32 ValidLen; /* Length of valid data in buffer */ + Uint32 DataOffset; /* Byte offset to valid data */ + Uint32 PktChannel; /* Tx/Rx Channel/Priority 0-7 (SOP only) */ + Uint32 PktLength; /* Length of Packet (SOP only) */ + /* (same as ValidLen on single frag Pkt) */ + Uint32 PktFrags; /* Number of frags in packet (SOP only) */ + /* (frag is EMAC_Pkt record - normally 1)*/ + } EMAC_Pkt; + +/* +// Packet Buffer Flags set in Flags +*/ +#define EMAC_PKT_FLAGS_SOP 0x80000000u /* Start of packet */ +#define EMAC_PKT_FLAGS_EOP 0x40000000u /* End of packet */ + +/* +// The Following Packet flags are set in Flags on RX packets only +*/ +#define EMAC_PKT_FLAGS_HASCRC 0x04000000u /* RxCrc: PKT has 4byte CRC */ +#define EMAC_PKT_FLAGS_JABBER 0x02000000u /* RxErr: Jabber */ +#define EMAC_PKT_FLAGS_OVERSIZE 0x01000000u /* RxErr: Oversize */ +#define EMAC_PKT_FLAGS_FRAGMENT 0x00800000u /* RxErr: Fragment */ +#define EMAC_PKT_FLAGS_UNDERSIZED 0x00400000u /* RxErr: Undersized */ +#define EMAC_PKT_FLAGS_CONTROL 0x00200000u /* RxCtl: Control Frame */ +#define EMAC_PKT_FLAGS_OVERRUN 0x00100000u /* RxErr: Overrun */ +#define EMAC_PKT_FLAGS_CODEERROR 0x00080000u /* RxErr: Code Error */ +#define EMAC_PKT_FLAGS_ALIGNERROR 0x00040000u /* RxErr: Alignment Error */ +#define EMAC_PKT_FLAGS_CRCERROR 0x00020000u /* RxErr: Bad CRC */ +#define EMAC_PKT_FLAGS_NOMATCH 0x00010000u /* RxPrm: No Match */ + + +/*-----------------------------------------------------------------------*\ +* EMAC_Config +* +* The config structure defines how the EMAC device should operate. It is +* passed to the device when the device is opened, and remains in effect +* until the device is closed. +* +* The following is a short description of the configuration fields: +* +* ModeFlags - Specify the Fixed Operating Mode of the Device +* EMAC_CONFIG_MODEFLG_CHPRIORITY - Treat TX channels as Priority Levels +* (Channel 7 is highest, 0 is lowest) +* EMAC_CONFIG_MODEFLG_MACLOOPBACK - Set MAC in Internal Loopback for Testing +* EMAC_CONFIG_MODEFLG_RXCRC - Include the 4 byte EtherCRC in RX frames +* EMAC_CONFIG_MODEFLG_TXCRC - Assume TX Frames Include 4 byte EtherCRC +* EMAC_CONFIG_MODEFLG_PASSERROR - Receive Error Frames for Testing +* EMAC_CONFIG_MODEFLG_PASSCONTROL - Receive Control Frames for Testing +* +* MdioModeFlags - Specify the MDIO/PHY Operation (See EMACMDIO.H) +* +* TxChannels - Number of TX Channels to use (1-8, usually 1) +* +* MacAddr - Device MAC address +* +* RxMaxPktPool - Max Rx packet buffers to get from pool +* (Must be in the range of 8 to 192) +* +* A list of callback functions is used to register callback functions with +* a particular instance of the EMAC peripheral. Callback functions are +* used by EMAC to communicate with the application. These functions are +* REQUIRED for operation. The same callback table can be used for multiple +* driver instances. +* +* The callback functions can be used by EMAC during any EMAC function, but +* mostly occur during calls to EMAC_statusIsr() and EMAC_statusPoll(). +* +* pfcbGetPacket - Called by EMAC to get a free packet buffer from the +* application layer for receive data. This function +* should return NULL is no free packets are available. +* The size of the packet buffer must be large enough +* to accommodate a full sized packet (1514 or 1518 +* depending on the EMAC_CONFIG_MODEFLG_RXCRC flag), plus +* any application buffer padding (DataOffset). +* +* pfcbFreePacket - Called by EMAC to give a free packet buffer back to +* the application layer. This function is used to +* return transmit packets. Note that at the time of the +* call, structure fields other than pDataBuffer and +* BufferLen are in an undefined state. +* +* pfcbRxPacket - Called to give a received data packet to the application +* layer. The applicaiton must accept the packet. +* When the application is finished with the packet, it +* can return it to its own free queue. +* +* This function also returns a pointer to a free packet to +* replace the received packet on the EMAC free list. It +* returns NULL when no free packets are available. The +* return packet is the same as would be returned by +* pfcbGetPacket. +* +* Thus if a newly received packet is not desired, it can +* simply be returned to EMAC via the return value. +* +* pfcbStatus - Called to indicate to the application that it +* should call EMAC_getStatus() to read the current +* device status. This call is made when device status +* changes. +* +* pfcbStatistics - Called to indicate to the application that it +* should call EMAC_getStatistics() to read the +* current Ethernet statistics. Called when the +* statistic counters are to the point of overflow. +* +* The hApplication calling calling argument is the application's handle +* as supplied to the EMAC device in the EMAC_open() function. +\*-----------------------------------------------------------------------*/ +typedef struct _EMAC_Config { + uint ModeFlags; /* Configuation Mode Flags */ + uint MdioModeFlags; /* CSL_MDIO Mode Flags (see CSL_MDIO.H) */ + uint TxChannels; /* Number of Tx Channels to use (1-8) */ + Uint8 MacAddr[6]; /* Mac Address */ + uint RxMaxPktPool; /* Max Rx packet buffers to get from pool */ + EMAC_Pkt * (*pfcbGetPacket)(Handle hApplication); + void (*pfcbFreePacket)(Handle hApplication, EMAC_Pkt *pPacket); + EMAC_Pkt * (*pfcbRxPacket)(Handle hApplication, EMAC_Pkt *pPacket); + void (*pfcbStatus)(Handle hApplication); + void (*pfcbStatistics)(Handle hApplication); +} EMAC_Config; + +/* +// Configuration Mode Flags +*/ +#define EMAC_CONFIG_MODEFLG_CHPRIORITY 0x0001 /* Use Tx channel priority */ +#define EMAC_CONFIG_MODEFLG_MACLOOPBACK 0x0002 /* MAC internal loopback */ +#define EMAC_CONFIG_MODEFLG_RXCRC 0x0004 /* Include CRC in RX frames */ +#define EMAC_CONFIG_MODEFLG_TXCRC 0x0008 /* Tx frames include CRC */ +#define EMAC_CONFIG_MODEFLG_PASSERROR 0x0010 /* Pass error frames */ +#define EMAC_CONFIG_MODEFLG_PASSCONTROL 0x0020 /* Pass control frames */ + +/*-----------------------------------------------------------------------*\ +* EMAC_Status +* +* The status structure contains information about the MAC's run-time +* status. +* +* The following is a short description of the configuration fields: +* +* MdioLinkStatus - Current link status (non-zero on link) (see CSL_MDIO.H) +* +* PhyDev - Current PHY device in use (0-31) +* +* RxPktHeld - Current number of Rx packets held by the EMAC device +* +* TxPktHeld - Current number of Tx packets held by the EMAC device +* +* FatalError - Fatal Error Code (TBD) +\*-----------------------------------------------------------------------*/ +typedef struct _EMAC_Status { + uint MdioLinkStatus; /* CSL_MDIO Link status (see CSL_MDIO.H) */ + uint PhyDev; /* Current PHY device in use (0-31) */ + uint RxPktHeld; /* Number of packets held for Rx */ + uint TxPktHeld; /* Number of packets held for Tx */ + uint FatalError; /* Fatal Error when non-zero */ +} EMAC_Status; + + +/*-----------------------------------------------------------------------*\ +* EMAC_Statistics +* +* The statistics structure is the used to retrieve the current count +* of various packet events in the system. These values represent the +* delta values from the last time the statistics were read. +\*-----------------------------------------------------------------------*/ +typedef struct _EMAC_Statistics { + Uint32 RxGoodFrames; /* Good Frames Received */ + Uint32 RxBCastFrames; /* Good Broadcast Frames Received */ + Uint32 RxMCastFrames; /* Good Multicast Frames Received */ + Uint32 RxPauseFrames; /* PauseRx Frames Received */ + Uint32 RxCRCErrors; /* Frames Received with CRC Errors */ + Uint32 RxAlignCodeErrors;/* Frames Received with Alignment/Code Errors */ + Uint32 RxOversized; /* Oversized Frames Received */ + Uint32 RxJabber; /* Jabber Frames Received */ + Uint32 RxUndersized; /* Undersized Frames Received */ + Uint32 RxFragments; /* Rx Frame Fragments Received */ + Uint32 RxFiltered; /* Rx Frames Filtered Based on Address */ + Uint32 RxQOSFiltered; /* Rx Frames Filtered Based on QoS Filtering */ + Uint32 RxOctets; /* Total Received Bytes in Good Frames */ + Uint32 TxGoodFrames; /* Good Frames Sent */ + Uint32 TxBCastFrames; /* Good Broadcast Frames Sent */ + Uint32 TxMCastFrames; /* Good Multicast Frames Sent */ + Uint32 TxPauseFrames; /* PauseTx Frames Sent */ + Uint32 TxDeferred; /* Frames Where Transmission was Deferred */ + Uint32 TxCollision; /* Total Frames Sent With Collision */ + Uint32 TxSingleColl; /* Frames Sent with Exactly One Collision */ + Uint32 TxMultiColl; /* Frames Sent with Multiple Colisions */ + Uint32 TxExcessiveColl; /* Tx Frames Lost Due to Excessive Collisions */ + Uint32 TxLateColl; /* Tx Frames Lost Due to a Late Collision */ + Uint32 TxUnderrun; /* Tx Frames Lost with Transmit Underrun Error */ + Uint32 TxCarrierSLoss; /* Tx Frames Lost Due to Carrier Sense Loss */ + Uint32 TxOctets; /* Total Transmitted Bytes in Good Frames */ + Uint32 Frame64; /* Total Tx&Rx with Octet Size of 64 */ + Uint32 Frame65t127; /* Total Tx&Rx with Octet Size of 65 to 127 */ + Uint32 Frame128t255; /* Total Tx&Rx with Octet Size of 128 to 255 */ + Uint32 Frame256t511; /* Total Tx&Rx with Octet Size of 256 to 511 */ + Uint32 Frame512t1023; /* Total Tx&Rx with Octet Size of 512 to 1023 */ + Uint32 Frame1024tUp; /* Total Tx&Rx with Octet Size of >=1024 */ + Uint32 NetOctets; /* Sum of all Octets Tx or Rx on the Network */ + Uint32 RxSOFOverruns; /* Total Rx Start of Frame Overruns */ + Uint32 RxMOFOverruns; /* Total Rx Middle of Frame Overruns */ + Uint32 RxDMAOverruns; /* Total Rx DMA Overruns */ +} EMAC_Statistics; + + +/*-----------------------------------------------------------------------*\ +* Packet Filtering +* +* Packet Filtering Settings (cumulative) +\*-----------------------------------------------------------------------*/ +#define EMAC_RXFILTER_NOTHING 0 +#define EMAC_RXFILTER_DIRECT 1 +#define EMAC_RXFILTER_BROADCAST 2 +#define EMAC_RXFILTER_MULTICAST 3 +#define EMAC_RXFILTER_ALLMULTICAST 4 +#define EMAC_RXFILTER_ALL 5 + +/*-----------------------------------------------------------------------*\ +* STANDARD ERROR CODES +\*-----------------------------------------------------------------------*/ +#define EMAC_ERROR_ALREADY 1 /* Operation has already been started */ +#define EMAC_ERROR_NOTREADY 2 /* Device is not open or not ready */ +#define EMAC_ERROR_DEVICE 3 /* Device hardware error */ +#define EMAC_ERROR_INVALID 4 /* Function or calling parameter is invalid */ +#define EMAC_ERROR_BADPACKET 5 /* Supplied packet was invalid */ +#define EMAC_ERROR_MACFATAL 6 /* Fatal Error in MAC - EMAC_close() required */ + +/*-----------------------------------------------------------------------*\ +* STANDARD API FUNCTIONS +* +* IMPORTANT NOTE +* -------------- +* The application is charged with verifying that only one of the +* following API calls may only be executing at a given time across +* all threads and all interrupt functions. +* +\*-----------------------------------------------------------------------*/ + +/*-----------------------------------------------------------------------*\ +* EMAC_enumerate() +* +* Enumerates the EMAC peripherals installed in the system and returns an +* integer count. The EMAC devices are enumerated in a consistent +* fashion so that each device can be later referenced by its physical +* index value ranging from "1" to "n" where "n" is the count returned +* by this function. +\*-----------------------------------------------------------------------*/ +CSLAPI uint EMAC_enumerate( void ); + + +/*-----------------------------------------------------------------------*\ +* EMAC_open() +* +* Opens the EMAC peripheral at the given physical index and initializes +* it to an embryonic state. +* +* The calling application must supply a operating configuration that +* includes a callback function table. Data from this config structure is +* copied into the device's internal instance structure so the structure +* may be discarded after EMAC_open() returns. In order to change an item +* in the configuration, the the EMAC device must be closed and then +* re-opened with the new configuration. +* +* The application layer may pass in an hApplication callback handle, +* that will be supplied by the EMAC device when making calls to the +* application callback functions. +* +* An EMAC device handle is written to phEMAC. This handle must be saved +* by the caller and then passed to other EMAC device functions. +* +* The default receive filter prevents normal packets from being received +* until the receive filter is specified by calling EMAC_receiveFilter(). +* +* A device reset is achieved by calling EMAC_close() followed by EMAC_open(). +* +* The function returns zero on success, or an error code on failure. +* +* Possible error codes include: +* EMAC_ERROR_ALREADY - The device is already open +* EMAC_ERROR_INVALID - A calling parameter is invalid +* +\*-----------------------------------------------------------------------*/ +CSLAPI uint EMAC_open( int physicalIndex, Handle hApplication, + EMAC_Config *pEMACConfig, Handle *phEMAC ); + + +/*-----------------------------------------------------------------------*\ +* EMAC_close() +* +* Closed the EMAC peripheral indicated by the supplied instance handle. +* When called, the EMAC device will shutdown both send and receive +* operations, and free all pending transmit and receive packets. +* +* The function returns zero on success, or an error code on failure. +* +* Possible error code include: +* EMAC_ERROR_INVALID - A calling parameter is invalid +* +\*-----------------------------------------------------------------------*/ +CSLAPI uint EMAC_close( Handle hEMAC ); + + +/*-----------------------------------------------------------------------*\ +* EMAC_getStatus() +* +* Called to get the current status of the device. The device status +* is copied into the supplied data structure. +* +* The function returns zero on success, or an error code on failure. +* +* Possible error code include: +* EMAC_ERROR_INVALID - A calling parameter is invalid +* +\*-----------------------------------------------------------------------*/ +CSLAPI uint EMAC_getStatus( Handle hEMAC, EMAC_Status *pStatus ); + + +/*-----------------------------------------------------------------------*\ +* EMAC_setReceiveFilter() +* +* Called to set the packet filter for received packets. The filtering +* level is inclusive, so BROADCAST would include both BROADCAST and +* DIRECTED (UNICAST) packets. +* +* Available filtering modes include the following: +* EMAC_RXFILTER_NOTHING - Receive nothing +* EMAC_RXFILTER_DIRECT - Receive only Unicast to local MAC addr +* EMAC_RXFILTER_BROADCAST - Receive direct and Broadcast +* EMAC_RXFILTER_MULTICAST - Receive above plus multicast in mcast list +* EMAC_RXFILTER_ALLMULTICAST - Receive above plus all multicast +* EMAC_RXFILTER_ALL - Receive all packets +* +* Note that if error frames and control frames are desired, reception of +* these must be specified in the device configuration. +* +* The function returns zero on success, or an error code on failure. +* +* Possible error code include: +* EMAC_ERROR_INVALID - A calling parameter is invalid +* +\*-----------------------------------------------------------------------*/ +CSLAPI uint EMAC_setReceiveFilter( Handle hEMAC, uint ReceiveFilter ); + + +/*-----------------------------------------------------------------------*\ +* EMAC_getReceiveFilter() +* +* Called to get the current packet filter setting for received packets. +* The filter values are the same as those used in EMAC_setReceiveFilter(). +* +* The current filter value is writter to the pointer supplied in +* pReceiveFilter. +* +* The function returns zero on success, or an error code on failure. +* +* Possible error code include: +* EMAC_ERROR_INVALID - A calling parameter is invalid +* +\*-----------------------------------------------------------------------*/ +CSLAPI uint EMAC_getReceiveFilter( Handle hEMAC, uint *pReceiveFilter ); + + +/*-----------------------------------------------------------------------*\ +* EMAC_getStatistics() +* +* Called to get the current device statistics. The statistics structure +* contains a collection of event counts for various packet sent and +* receive properties. Reading the statistics also clears the current +* statistic counters, so the values read represent a delta from the last +* call. +* +* The statistics information is copied into the structure pointed to +* by the pStatistics argument. +* +* The function returns zero on success, or an error code on failure. +* +* Possible error code include: +* EMAC_ERROR_INVALID - A calling parameter is invalid +* +\*-----------------------------------------------------------------------*/ +CSLAPI uint EMAC_getStatistics( Handle hEMAC, EMAC_Statistics *pStatistics ); + + +/*-----------------------------------------------------------------------*\ +* EMAC_setMulticast() +* +* This function is called to install a list of multicast addresses for +* use in multicast address filtering. Each time this function is called, +* any current multicast configuration is discarded in favor of the new +* list. Thus a set with a list size of zero will remove all multicast +* addresses from the device. +* +* Note that the multicast list configuration is stateless in that the +* list of multicast addresses used to build the configuration is not +* retained. Thus it is impossible to examine a list of currently installed +* addresses. +* +* The addresses to install are pointed to by pMCastList. The length of +* this list in bytes is 6 times the value of AddrCnt. When AddrCnt is +* zero, the pMCastList parameter can be NULL. +* +* The function returns zero on success, or an error code on failure. +* The multicast list settings are not altered in the event of a failure +* code. +* +* Possible error code include: +* EMAC_ERROR_INVALID - A calling parameter is invalid +* +\*-----------------------------------------------------------------------*/ +CSLAPI uint EMAC_setMulticast( Handle hEMAC, uint AddrCnt, Uint8 *pMCastList ); + + + +/*-----------------------------------------------------------------------*\ +* EMAC_sendPacket() +* +* Sends a Ethernet data packet out the EMAC device. On a non-error return, +* the EMAC device takes ownership of the packet. The packet is returned +* to the application's free pool once it has been transmitted. +* +* The function returns zero on success, or an error code on failure. +* When an error code is returned, the EMAC device has not taken ownership +* of the packet. +* +* Possible error codes include: +* EMAC_ERROR_INVALID - A calling parameter is invalid +* EMAC_ERROR_BADPACKET - The packet structure is invalid +* +\*-----------------------------------------------------------------------*/ +CSLAPI uint EMAC_sendPacket( Handle hEMAC, EMAC_Pkt *pPacket ); + + +/*-----------------------------------------------------------------------*\ +* EMAC_serviceCheck() +* +* This function should be called every time there is an EMAC device +* interrupt. It maintains the status the EMAC. +* +* Note that the application has the responsibility for mapping the +* physical device index to the correct EMAC_serviceCheck() function. If +* more than one EMAC device is on the same interrupt, the function must be +* called for each device. +* +* Possible error codes include: +* EMAC_ERROR_INVALID - A calling parameter is invalid +* EMAC_ERROR_MACFATAL - Fatal error in the MAC - Call EMAC_close() +* +\*-----------------------------------------------------------------------*/ +CSLAPI uint EMAC_serviceCheck( Handle hEMAC ); + + +/*-----------------------------------------------------------------------*\ +* EMAC_timerTick() +* +* This function should be called for each device in the system on a +* periodic basis of 100mS (10 times a second). It is used to check the +* status of the EMAC and MDIO device, and to potentially recover from +* low Rx buffer conditions. +* +* Strict timing is not required, but the application should make a +* reasonable attempt to adhere to the 100mS mark. A missed call should +* not be "made up" by making mulitple sequential calls. +* +* A "polling" driver (one that calls EMAC_serviceCheck() in a tight loop), +* must also adhere to the 100mS timing on this function. +* +* Possible error codes include: +* EMAC_ERROR_INVALID - A calling parameter is invalid +* +\*-----------------------------------------------------------------------*/ +CSLAPI uint EMAC_timerTick( Handle hEMAC ); + +#endif /* EMAC_SUPPORT */ +#endif /* _CSL_EMAC_H_ */ + +/******************************************************************************\ +* End of emi.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_emachal.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_emachal.h new file mode 100644 index 0000000..d229339 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_emachal.h @@ -0,0 +1,2516 @@ +/*****************************************************************************\ +* Copyright (C) 1999-2003 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_emachal.h +* DATE CREATED.. 02/04/2002 +* LAST MODIFIED. 03/05/2003 +*------------------------------------------------------------------------------ +* REGISTERS/PARAMETERS +* +* TXIDVER - TX Identification and Version Register +* TXCONTROL - TX Control Register +* TXTEARDOWN - TX Teardown Register +* RXIDVER - RX Identification and Version Register +* RXCONTROL - RX Control Register +* RXTEARDOWN - RX Teardown Register +* RXMBPENABLE - RX Mulicast/Bcast/Promisc Channel Enable Register +* RXUNICASTSET - RX Unicast Set Register +* RXUNICASTCLEAR - RX Unicast Clear Register +* RXMAXLEN - RX Maximum Length Register +* RXBUFFEROFFSET - RX Buffer Offset Register +* RXFILTERLOWTHRESH - RX Filer Low Priority Packets Threshhold +* RX0FLOWTHRESH - RX Channel 0 Flow Control Threshhold +* RX1FLOWTHRESH - RX Channel 1 Flow Control Threshhold +* RX2FLOWTHRESH - RX Channel 2 Flow Control Threshhold +* RX3FLOWTHRESH - RX Channel 3 Flow Control Threshhold +* RX4FLOWTHRESH - RX Channel 4 Flow Control Threshhold +* RX5FLOWTHRESH - RX Channel 5 Flow Control Threshhold +* RX6FLOWTHRESH - RX Channel 6 Flow Control Threshhold +* RX7FLOWTHRESH - RX Channel 7 Flow Control Threshhold +* RX0FREEBUFFER - RX Channel 0 Free Buffer Count Register +* RX1FREEBUFFER - RX Channel 1 Free Buffer Count Register +* RX2FREEBUFFER - RX Channel 2 Free Buffer Count Register +* RX3FREEBUFFER - RX Channel 3 Free Buffer Count Register +* RX4FREEBUFFER - RX Channel 4 Free Buffer Count Register +* RX5FREEBUFFER - RX Channel 5 Free Buffer Count Register +* RX6FREEBUFFER - RX Channel 6 Free Buffer Count Register +* RX7FREEBUFFER - RX Channel 7 Free Buffer Count Register +* MACCONTROL - MAC Control Register +* MACSTATUS - MAC Status Register +* EMCONTROL - Emulation Control Register +* TXINTSTATRAW - TX Interrupt Status Register (Unmasked) +* TXINTSTATMASKED - TX Interrupt Status Register (Masked) +* TXINTMASKSET - TX Interrupt Mask Set Register +* TXINTMASKCLEAR - TX Interrupt Mask Clear Register +* MACINVECTOR - MAC Input Vector +* MACEOIVECTOR - MAC EOI Vector +* RXINTSTATRAW - RX Interrupt Status Register (Unmasked) +* RXINTSTATMASKED - RX Interrupt Status Register (Masked) +* RXINTMASKSET - RX Interrupt Mask Set Register +* RXINTMASKCLEAR - RX Interrupt Mask Clear Register +* MACINTSTATRAW - MAC Interrupt Status Register (Unmasked) +* MACINTSTATMASKED - MAC Interrupt Status Register (Masked) +* MACINTMASKSET - MAC Interrupt Mask Set Register +* MACINTMASKCLEAR - MAC Interrupt Mask Clear Register +* MACADDRL0 - MAC Address Channel 0 Lower Byte Register +* MACADDRL1 - MAC Address Channel 1 Lower Byte Register +* MACADDRL2 - MAC Address Channel 2 Lower Byte Register +* MACADDRL3 - MAC Address Channel 3 Lower Byte Register +* MACADDRL4 - MAC Address Channel 4 Lower Byte Register +* MACADDRL5 - MAC Address Channel 5 Lower Byte Register +* MACADDRL6 - MAC Address Channel 6 Lower Byte Register +* MACADDRL7 - MAC Address Channel 7 Lower Byte Register +* MACADDRM - MAC Address Middle Byte Register +* MACADDRH - MAC Address High Bytes Register +* MACHASH1 - MAC Address Hash 1 Register +* MACHASH2 - MAC Address Hash 2 Register +* BOFFTEST - Backoff Test Register +* TPACETEST - Transmit Pacing Test Register +* RXPAUSE - Receive Pause Timer Register +* TXPAUSE - Transmit Pause Timer Register +* RXGOODFRAMES - Number of Good Frames Received +* RXBCASTFRAMES - Number of Good Broadcast Frames Received +* RXMCASTFRAMES - Number of Good Multicast Frames Received +* RXPAUSEFRAMES - Number of PauseRX Frames Received +* RXCRCERRORS - Number of Frames Received with CRC Errors +* RXALIGNCODEERRORS - Number of Frames Received with Alignment/Code Errors +* RXOVERSIZED - Number of Oversized Frames Received +* RXJABBER - Number of Jabber Frames Received +* RXUNDERSIZED - Number of Undersized Frames Received +* RXFRAGMENTS - Number of RX Frame Fragments Received +* RXFILTERED - Number of RX Frames Filtered Based on Address +* RXQOSFILTERED - Number of RX Frames Filtered Based on QoS Filtering +* RXOCTETS - Total Number of Received Bytes in Good Frames +* TXGOODFRAMES - Number of Good Frames Sent +* TXBCASTFRAMES - Number of Good Broadcast Frames Sent +* TXMCASTFRAMES - Number of Good Multicast Frames Sent +* TXPAUSEFRAMES - Number of PauseTX Frames Sent +* TXDEFERRED - Number of Frames Where Transmission was Deferred +* TXCOLLISION - Total Number of Frames Sent That Experienced a Collision +* TXSINGLECOLL - Number of Frames Sent with Exactly One Collision +* TXMULTICOLL - Number of Frames Sent with Multiple Colisions +* TXEXCESSIVECOLL - Number of TX Frames Lost Due to Excessive Collisions +* TXLATECOLL - Number of TX Frames Lost Due to a Late Collision +* TXUNDERRUN - Number of TX Frames Lost with Transmit Underrun Error +* TXCARRIERSLOSS - Numebr of TX Frames Lost Due to Carrier Sense Loss +* TXOCTETS - Total Nu,ber of Transmitted Bytes in Good Frames +* FRAME64 - Total TX & RX Frames with Octet Size of 64 +* FRAME65T127 - Total TX & RX Frames with Octet Size of 65 to 127 +* FRAME128T255 - Total TX & RX Frames with Octet Size of 128 to 255 +* FRAME256T511 - Total TX & RX Frames with Octet Size of 256 to 511 +* FRAME512T1023 - Total TX & RX Frames with Octet Size of 512 to 1023 +* FRAME1024TUP - Total TX & RX Frames with Octet Size of 1024 or above +* NETOCTETS - Sum of all Octets Sent or Received on the Network +* RXSOFOVERRUNS - Total RX Start of Frame Overruns (FIFO or DMA) +* RXMOFOVERRUNS - Total RX Middle of Frame Overruns (FIFO or DMA) +* RXDMAOVERRUNS - Total RX DMA Overruns +* TX0HDP - TX Channel 0 DMA Head Descriptor Pointer Register +* TX1HDP - TX Channel 1 DMA Head Descriptor Pointer Register +* TX2HDP - TX Channel 2 DMA Head Descriptor Pointer Register +* TX3HDP - TX Channel 3 DMA Head Descriptor Pointer Register +* TX4HDP - TX Channel 4 DMA Head Descriptor Pointer Register +* TX5HDP - TX Channel 5 DMA Head Descriptor Pointer Register +* TX6HDP - TX Channel 6 DMA Head Descriptor Pointer Register +* TX7HDP - TX Channel 7 DMA Head Descriptor Pointer Register +* RX0HDP - RX Channel 0 DMA Head Descriptor Pointer Register +* RX1HDP - RX Channel 1 DMA Head Descriptor Pointer Register +* RX2HDP - RX Channel 2 DMA Head Descriptor Pointer Register +* RX3HDP - RX Channel 3 DMA Head Descriptor Pointer Register +* RX4HDP - RX Channel 4 DMA Head Descriptor Pointer Register +* RX5HDP - RX Channel 5 DMA Head Descriptor Pointer Register +* RX6HDP - RX Channel 6 DMA Head Descriptor Pointer Register +* RX7HDP - RX Channel 7 DMA Head Descriptor Pointer Register +* TX0INTACK - TX Channel 0 Interrupt Acknowledge Register +* TX1INTACK - TX Channel 1 Interrupt Acknowledge Register +* TX2INTACK - TX Channel 2 Interrupt Acknowledge Register +* TX3INTACK - TX Channel 3 Interrupt Acknowledge Register +* TX4INTACK - TX Channel 4 Interrupt Acknowledge Register +* TX5INTACK - TX Channel 5 Interrupt Acknowledge Register +* TX6INTACK - TX Channel 6 Interrupt Acknowledge Register +* TX7INTACK - TX Channel 7 Interrupt Acknowledge Register +* RX0INTACK - RX Channel 0 Interrupt Acknowledge Register +* RX1INTACK - RX Channel 1 Interrupt Acknowledge Register +* RX2INTACK - RX Channel 2 Interrupt Acknowledge Register +* RX3INTACK - RX Channel 3 Interrupt Acknowledge Register +* RX4INTACK - RX Channel 4 Interrupt Acknowledge Register +* RX5INTACK - RX Channel 5 Interrupt Acknowledge Register +* RX6INTACK - RX Channel 6 Interrupt Acknowledge Register +* RX7INTACK - RX Channel 7 Interrupt Acknowledge Register +* +* +* WRAPPER REGISTERS +* +* INTCTL - Interrupt control register +* +* +* DESCRIPTOR FIELDS +* +* DSC_NEXTDSC - Pointer to Next Descriptor +* DSC_BUFFER - Pointer to Buffer +* DSC_OFFLEN - Buffer Offset and Length +* DSC_STATUS - Packet Status +* +*\******************************************************************************/ +#ifndef _CSL_EMACHAL_H +#define _CSL_EMACHAL_H_ + +#include +#include + + +#if (EMAC_SUPPORT) +/******************************************************************************\ +* EMAC Register section +\******************************************************************************/ + +#define _EMAC_BASE_ADDR 0x01c80000u + +/* ----------------- */ +/* FIELD MAKE MACROS */ +/* ----------------- */ + +/* User Supplied Value */ +#define EMAC_FMK(REG,FIELD,x)\ + ((x<<_EMAC_##REG##_##FIELD##_SHIFT)&_EMAC_##REG##_##FIELD##_MASK) + +/* Symbolic Value Name */ +#define EMAC_FMKS(REG,FIELD,SYM)\ + ((EMAC_##REG##_##FIELD##_##SYM<<_EMAC_##REG##_##FIELD##_SHIFT)\ + &_EMAC_##REG##_##FIELD##_MASK) + +/* Channel Flag */ +#define EMAC_FMKCHF(CHANNEL) (1u<<(CHANNEL)) + + +/* -------------------------------- */ +/* RAW REGISTER/FIELD ACCESS MACROS */ +/* -------------------------------- */ + +#define EMAC_ADDR(REG)\ + ((volatile Uint32 *)_EMAC_##REG##_ADDR) + +#define EMAC_REG(REG)\ + *(volatile Uint32*)(_EMAC_##REG##_ADDR) + +/* Standard Registers */ +#define EMAC_RGET(REG)\ + (*(volatile Uint32*)(_EMAC_##REG##_ADDR)) + +#define EMAC_RSET(REG,x)\ + (*(volatile Uint32*)(_EMAC_##REG##_ADDR)=(x)) + +#define EMAC_FGET(REG,FIELD)\ + ((EMAC_RGET(REG)&_EMAC_##REG##_##FIELD##_MASK)\ + >>_EMAC_##REG##_##FIELD##_SHIFT) + +#define EMAC_FSET(REG,FIELD,x)\ + EMAC_RSET(REG,(EMAC_RGET(REG)&~_EMAC_##REG##_##FIELD##_MASK)|\ + EMAC_FMK(REG,FIELD,x)) + +#define EMAC_FSETS(REG,FIELD,SYM)\ + EMAC_RSET(REG,(EMAC_RGET(REG)&~_EMAC_##REG##_##FIELD##_MASK)|\ + EMAC_FMKS(REG,FIELD,SYM)) + + +/* Index Based Registers */ +#define EMAC_RGETI(REGBASE,IDX)\ + (*(volatile Uint32*)(_EMAC_##REGBASE##_BASEADDR+((IDX)*sizeof(Uint32 *)))) + +#define EMAC_RSETI(REGBASE,IDX,x)\ + (*(volatile Uint32*)(_EMAC_##REGBASE##_BASEADDR+((IDX)*sizeof(Uint32 *)))=(x)) + +#define EMAC_FGETI(REGBASE,IDX,FIELD)\ + ((EMAC_RGETI(REGBASE,IDX)&_EMAC_##REGBASE##_##FIELD##_MASK)\ + >>_EMAC_##REGBASE##_##FIELD##_SHIFT) + +#define EMAC_FSETI(REGBASE,IDX,FIELD,x)\ + EMAC_RSETI(REGBASE,IDX,(EMAC_RGETI(REGBASE,IDX)&\ + ~_EMAC_##REGBASE##_##FIELD##_MASK)|EMAC_FMK(REGBASE,FIELD,x)) + +#define EMAC_FSETSI(REGBASE,IDX,FIELD,SYM)\ + EMAC_RSETI(REGBASE,IDX,(EMAC_RGETI(REGBASE,IDX)&\ + ~_EMAC_##REGBASE##_##FIELD##_MASK)|EMAC_FMKS(REGBASE,FIELD,SYM)) + + + +/******************************************************************************\ +* EMAC Descriptor section +\******************************************************************************/ + +#define _EMAC_DSC_BASE_ADDR 0x01c81000u + +/* EMAC Descriptor Size and Element Count */ +#define _EMAC_DSC_SIZE 4096 +#define _EMAC_DSC_ENTRY_SIZE 16 +#define _EDMA_DSC_ENTRY_COUNT (_EMAC_DSC_SIZE/_EMAC_DSC_ENTRY_SIZE) + + +/* +// EMAC Descriptor +// +// The following is the format of a single buffer descriptor +// on the EMAC. +*/ +typedef struct _EMAC_Desc { + struct _EMAC_Desc *pNext; /* Pointer to next descriptor in chain */ + Uint8 *pBuffer; /* Pointer to data buffer */ + Uint32 BufOffLen; /* Buffer Offset(MSW) and Length(LSW) */ + Uint32 PktFlgLen; /* Packet Flags(MSW) and Length(LSW) */ +} EMAC_Desc; + + +/* ------------------------ */ +/* DESCRIPTOR ACCESS MACROS */ +/* ------------------------ */ + +/* Packet Flags */ +#define EMAC_DSC_FLAG_SOP 0x80000000u +#define EMAC_DSC_FLAG_EOP 0x40000000u +#define EMAC_DSC_FLAG_OWNER 0x20000000u +#define EMAC_DSC_FLAG_EOQ 0x10000000u +#define EMAC_DSC_FLAG_TDOWNCMPLT 0x08000000u +#define EMAC_DSC_FLAG_PASSCRC 0x04000000u +#define EMAC_DSC_FLAG_JABBER 0x02000000u +#define EMAC_DSC_FLAG_OVERSIZE 0x01000000u +#define EMAC_DSC_FLAG_FRAGMENT 0x00800000u +#define EMAC_DSC_FLAG_UNDERSIZED 0x00400000u +#define EMAC_DSC_FLAG_CONTROL 0x00200000u +#define EMAC_DSC_FLAG_OVERRUN 0x00100000u +#define EMAC_DSC_FLAG_CODEERROR 0x00080000u +#define EMAC_DSC_FLAG_ALIGNERROR 0x00040000u +#define EMAC_DSC_FLAG_CRCERROR 0x00020000u +#define EMAC_DSC_FLAG_NOMATCH 0x00010000u + + +/******************************************************************************\ +* module level register/field access macros +\******************************************************************************/ + +/******************************************************************************\ +* _____________________ +* | | +* | TXIDVER | +* |___________________| +* +* TXIDVER - TX Identification and Version Register +* +* FIELDS (msb -> lsb) +* (r) TXIDENT +* (r) TXMAJORVER +* (r) TXMINORVER +* +* MACROS SUPPORTED +* EMAC_FMK y +* EMAC_FMKS . +* EMAC_FMKCHF . +* EMAC_ADDR y +* EMAC_REG y +* EMAC_RGET y +* EMAC_RSET y +* EMAC_FGET y +* EMAC_FSET y +* EMAC_FSETS . +* EMAC_RGETI . +* EMAC_RSETI . +* EMAC_FGETI . +* EMAC_FSETI . +* EMAC_FSETSI . +* +\******************************************************************************/ +#define _EMAC_TXIDVER_ADDR (_EMAC_BASE_ADDR+0x0000u) + +#define EMAC_TXIDVER EMAC_REG(TXIDVER) + +#define _EMAC_TXIDVER_TXIDENT_MASK 0xFFFF0000u +#define _EMAC_TXIDVER_TXIDENT_SHIFT 16u +#define EMAC_TXIDVER_TXIDENT_DEFAULT 0x00000004u + +#define _EMAC_TXIDVER_TXMAJORVER_MASK 0x0000FF00u +#define _EMAC_TXIDVER_TXMAJORVER_SHIFT 8u +#define EMAC_TXIDVER_TXMAJORVER_DEFAULT 0x00000000u + +#define _EMAC_TXIDVER_TXMINORVER_MASK 0x000000FFu +#define _EMAC_TXIDVER_TXMINORVER_SHIFT 0u +#define EMAC_TXIDVER_TXMINORVER_DEFAULT 0x00000000u + + + +/******************************************************************************\ +* _____________________ +* | | +* | TXCONTROL | +* |___________________| +* +* TXCONTROL - TX Control Register +* +* FIELDS (msb -> lsb) +* (rw) TXEN - Transmit Enable +* +* MACROS SUPPORTED +* EMAC_FMK y +* EMAC_FMKS y +* EMAC_FMKCHF . +* EMAC_ADDR y +* EMAC_REG y +* EMAC_RGET y +* EMAC_RSET y +* EMAC_FGET y +* EMAC_FSET y +* EMAC_FSETS . +* EMAC_RGETI . +* EMAC_RSETI . +* EMAC_FGETI . +* EMAC_FSETI . +* EMAC_FSETSI . +* +\******************************************************************************/ +#define _EMAC_TXCONTROL_ADDR (_EMAC_BASE_ADDR+0x0004u) + +#define EMAC_TXCONTROL EMAC_REG(TXCONTROL) + +#define _EMAC_TXCONTROL_TXEN_MASK 0x00000001u +#define _EMAC_TXCONTROL_TXEN_SHIFT 0u +#define EMAC_TXCONTROL_TXEN_DEFAULT 0x00000000u +#define EMAC_TXCONTROL_TXEN_DISABLE 0u +#define EMAC_TXCONTROL_TXEN_ENABLE 1u + + + +/******************************************************************************\ +* _____________________ +* | | +* | TXTEARDOWN | +* |___________________| +* +* TXTEARDOWN - TX Teardown Register +* +* FIELDS (msb -> lsb) +* (w) TXTDNCH - Teardown Channel Number +* +* MACROS SUPPORTED +* EMAC_FMK y +* EMAC_FMKS . +* EMAC_FMKCHF . +* EMAC_ADDR y +* EMAC_REG y +* EMAC_RGET y +* EMAC_RSET y +* EMAC_FGET y +* EMAC_FSET y +* EMAC_FSETS . +* EMAC_RGETI . +* EMAC_RSETI . +* EMAC_FGETI . +* EMAC_FSETI . +* EMAC_FSETSI . +* +\******************************************************************************/ +#define _EMAC_TXTEARDOWN_ADDR (_EMAC_BASE_ADDR+0x0008u) + +#define EMAC_TXTEARDOWN EMAC_REG(TXTEARDOWN) + +#define _EMAC_TXTEARDOWN_TXTDNCH_MASK 0x00000007u +#define _EMAC_TXTEARDOWN_TXTDNCH_SHIFT 0u +#define EMAC_TXTEARDOWN_TXTDNCH_DEFAULT 0x00000000u + + +/******************************************************************************\ +* _____________________ +* | | +* | RXIDVER | +* |___________________| +* +* RXIDVER - RX Identification and Version Register +* +* FIELDS (msb -> lsb) +* (r) RXIDENT +* (r) RXMAJORVER +* (r) RXMINORVER +* +* MACROS SUPPORTED +* EMAC_FMK y +* EMAC_FMKS . +* EMAC_FMKCHF . +* EMAC_ADDR y +* EMAC_REG y +* EMAC_RGET y +* EMAC_RSET y +* EMAC_FGET y +* EMAC_FSET y +* EMAC_FSETS . +* EMAC_RGETI . +* EMAC_RSETI . +* EMAC_FGETI . +* EMAC_FSETI . +* EMAC_FSETSI . +* +\******************************************************************************/ +#define _EMAC_RXIDVER_ADDR (_EMAC_BASE_ADDR+0x0010u) + +#define EMAC_RXIDVER EMAC_REG(RXIDVER) + +#define _EMAC_RXIDVER_RXIDENT_MASK 0xFFFF0000u +#define _EMAC_RXIDVER_RXIDENT_SHIFT 16u +#define EMAC_RXIDVER_RXIDENT_DEFAULT 0x00000004u + +#define _EMAC_RXIDVER_RXMAJORVER_MASK 0x0000FF00u +#define _EMAC_RXIDVER_RXMAJORVER_SHIFT 8u +#define EMAC_RXIDVER_RXMAJORVER_DEFAULT 0x00000000u + +#define _EMAC_RXIDVER_RXMINORVER_MASK 0x000000FFu +#define _EMAC_RXIDVER_RXMINORVER_SHIFT 0u +#define EMAC_RXIDVER_RXMINORVER_DEFAULT 0x00000000u + + +/******************************************************************************\ +* _____________________ +* | | +* | RXCONTROL | +* |___________________| +* +* RXCONTROL - RX Control Register +* +* FIELDS (msb -> lsb) +* (rw) RXEN - Receive Enable +* +* MACROS SUPPORTED +* EMAC_FMK y +* EMAC_FMKS y +* EMAC_FMKCHF . +* EMAC_ADDR y +* EMAC_REG y +* EMAC_RGET y +* EMAC_RSET y +* EMAC_FGET y +* EMAC_FSET y +* EMAC_FSETS y +* EMAC_RGETI . +* EMAC_RSETI . +* EMAC_FGETI . +* EMAC_FSETI . +* EMAC_FSETSI . +* +\******************************************************************************/ +#define _EMAC_RXCONTROL_ADDR (_EMAC_BASE_ADDR+0x0014u) + +#define EMAC_RXCONTROL EMAC_REG(RXCONTROL) + +#define _EMAC_RXCONTROL_RXEN_MASK 0x00000001u +#define _EMAC_RXCONTROL_RXEN_SHIFT 0u +#define EMAC_RXCONTROL_RXEN_DEFAULT 0x00000000u +#define EMAC_RXCONTROL_RXEN_DISABLE 0u +#define EMAC_RXCONTROL_RXEN_ENABLE 1u + + + +/******************************************************************************\ +* _____________________ +* | | +* | RXTEARDOWN | +* |___________________| +* +* RXTEARDOWN - RX Teardown Register +* +* FIELDS (msb -> lsb) +* (w) RXTDNCH - Teardown Channel Number +* +* MACROS SUPPORTED +* EMAC_FMK y +* EMAC_FMKS . +* EMAC_FMKCHF . +* EMAC_ADDR y +* EMAC_RGET y +* EMAC_RSET y +* EMAC_FGET y +* EMAC_FSET y +* EMAC_FSETS . +* EMAC_RGETI . +* EMAC_RSETI . +* EMAC_FGETI . +* EMAC_FSETI . +* EMAC_FSETSI . +* +\******************************************************************************/ +#define _EMAC_RXTEARDOWN_ADDR (_EMAC_BASE_ADDR+0x0018u) + +#define EMAC_RXTEARDOWN EMAC_REG(RXTEARDOWN) + +#define _EMAC_RXTEARDOWN_RXTDNCH_MASK 0x000000007u +#define _EMAC_RXTEARDOWN_RXTDNCH_SHIFT 0u +#define EMAC_RXTEARDOWN_RXTDNCH_DEFAULT 0x00000000u + + +/******************************************************************************\ +* _____________________ +* | | +* | RXMBPENABLE | +* |___________________| +* +* RXMBPENABLE - RX Mulicast/Bcast/Promisc Channel Enable Register +* +* FIELDS (msb -> lsb) +* (rw) RXPASSCRC - Pass Receive CRC +* (rw) RXQOSEN - RX QOS Enable +* (rw) RXNOCHAIN - RX No Buffer Chaining +* (rw) RXCMFEN - RX Copy MAC Control Frames Enable +* (rw) RXCSFEN - RX Copy Short Frames Enable +* (rw) RXCEFEN - RX Copy Error Frames Enable +* (rw) RXCAFEN - RX Copy All Frames Enable +* (rw) RXPROMCH - RX Promiscusous Channel Select +* (rw) RXBROADEN - RX Broadcast Frame Enable +* (rw) RXBROADCH - RX Broadcast Channel Select +* (rw) RXMULTEN - RX Multicast Enable +* (rw) RXMULTCH - RX Multicast Channel Select +* +* MACROS SUPPORTED +* EMAC_FMK y +* EMAC_FMKS y +* EMAC_FMKCHF . +* EMAC_ADDR y +* EMAC_REG y +* EMAC_RGET y +* EMAC_RSET y +* EMAC_FGET y +* EMAC_FSET y +* EMAC_FSETS y +* EMAC_RGETI . +* EMAC_RSETI . +* EMAC_FGETI . +* EMAC_FSETI . +* EMAC_FSETSI . +* +\******************************************************************************/ +#define _EMAC_RXMBPENABLE_ADDR (_EMAC_BASE_ADDR+0x0100u) + +#define EMAC_RXMBPENABLE EMAC_REG(RXMBPENABLE) + +#define _EMAC_RXMBPENABLE_RXPASSCRC_MASK 0x40000000u +#define _EMAC_RXMBPENABLE_RXPASSCRC_SHIFT 30u +#define EMAC_RXMBPENABLE_RXPASSCRC_DEFAULT 0x00000000u +#define EMAC_RXMBPENABLE_RXPASSCRC_DISCARD 0u +#define EMAC_RXMBPENABLE_RXPASSCRC_INCLUDE 1u + +#define _EMAC_RXMBPENABLE_RXQOSEN_MASK 0x20000000u +#define _EMAC_RXMBPENABLE_RXQOSEN_SHIFT 29u +#define EMAC_RXMBPENABLE_RXQOSEN_DEFAULT 0x00000000u +#define EMAC_RXMBPENABLE_RXQOSEN_DISABLE 0u +#define EMAC_RXMBPENABLE_RXQOSEN_ENABLE 1u + +#define _EMAC_RXMBPENABLE_RXNOCHAIN_MASK 0x10000000u +#define _EMAC_RXMBPENABLE_RXNOCHAIN_SHIFT 28u +#define EMAC_RXMBPENABLE_RXNOCHAIN_DEFAULT 0x00000000u +#define EMAC_RXMBPENABLE_RXNOCHAIN_DISABLE 0u +#define EMAC_RXMBPENABLE_RXNOCHAIN_ENABLE 1u + +#define _EMAC_RXMBPENABLE_RXCMFEN_MASK 0x01000000u +#define _EMAC_RXMBPENABLE_RXCMFEN_SHIFT 24u +#define EMAC_RXMBPENABLE_RXCMFEN_DEFAULT 0x00000000u +#define EMAC_RXMBPENABLE_RXCMFEN_DISABLE 0u +#define EMAC_RXMBPENABLE_RXCMFEN_ENABLE 1u + +#define _EMAC_RXMBPENABLE_RXCSFEN_MASK 0x00800000u +#define _EMAC_RXMBPENABLE_RXCSFEN_SHIFT 23u +#define EMAC_RXMBPENABLE_RXCSFEN_DEFAULT 0x00000000u +#define EMAC_RXMBPENABLE_RXCSFEN_DISABLE 0u +#define EMAC_RXMBPENABLE_RXCSFEN_ENABLE 1u + +#define _EMAC_RXMBPENABLE_RXCEFEN_MASK 0x00400000u +#define _EMAC_RXMBPENABLE_RXCEFEN_SHIFT 22u +#define EMAC_RXMBPENABLE_RXCEFEN_DEFAULT 0x00000000u +#define EMAC_RXMBPENABLE_RXCEFEN_DISABLE 0u +#define EMAC_RXMBPENABLE_RXCEFEN_ENABLE 1u + +#define _EMAC_RXMBPENABLE_RXCAFEN_MASK 0x00200000u +#define _EMAC_RXMBPENABLE_RXCAFEN_SHIFT 21u +#define EMAC_RXMBPENABLE_RXCAFEN_DEFAULT 0x00000000u +#define EMAC_RXMBPENABLE_RXCAFEN_DISABLE 0u +#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE 1u + +#define _EMAC_RXMBPENABLE_PROMCH_MASK 0x00070000u +#define _EMAC_RXMBPENABLE_PROMCH_SHIFT 16u +#define EMAC_RXMBPENABLE_PROMCH_DEFAULT 0x00000000u + +#define _EMAC_RXMBPENABLE_BROADEN_MASK 0x00002000u +#define _EMAC_RXMBPENABLE_BROADEN_SHIFT 13u +#define EMAC_RXMBPENABLE_BROADEN_DEFAULT 0x00000000u +#define EMAC_RXMBPENABLE_BROADEN_DISABLE 0u +#define EMAC_RXMBPENABLE_BROADEN_ENABLE 1u + +#define _EMAC_RXMBPENABLE_BROADCH_MASK 0x00000700u +#define _EMAC_RXMBPENABLE_BROADCH_SHIFT 8u +#define EMAC_RXMBPENABLE_BROADCH_DEFAULT 0x00000000u + +#define _EMAC_RXMBPENABLE_MULTEN_MASK 0x00000020u +#define _EMAC_RXMBPENABLE_MULTEN_SHIFT 5u +#define EMAC_RXMBPENABLE_MULTEN_DEFAULT 0x00000000u +#define EMAC_RXMBPENABLE_MULTEN_DISABLE 0u +#define EMAC_RXMBPENABLE_MULTEN_ENABLE 1u + +#define _EMAC_RXMBPENABLE_MULTCH_MASK 0x00000007u +#define _EMAC_RXMBPENABLE_MULTCH_SHIFT 0u +#define EMAC_RXMBPENABLE_MULTCH_DEFAULT 0x00000000u +/******************************************************************************\ +* _____________________ +* | | +* | RXUNICASTSET | +* | RXUNICASTCLEAR | +* |___________________| +* +* RXUNICASTSET - RX Unicast Set Register +* RXUNICASTCLEAR - RX Unicast Clear Register +* +* FIELDS (msb -> lsb) +* (r/ws)(r/wc) Channel Flags (use EMAC_FMKCHF) +* +* MACROS SUPPORTED +* EMAC_FMK . +* EMAC_FMKS . +* EMAC_FMKCHF y +* EMAC_ADDR y +* EMAC_REG y +* EMAC_RGET y +* EMAC_RSET y +* EMAC_FGET . +* EMAC_FSET . +* EMAC_FSETS . +* EMAC_RGETI . +* EMAC_RSETI . +* EMAC_FGETI . +* EMAC_FSETI . +* EMAC_FSETSI . +* +\******************************************************************************/ +#define _EMAC_RXUNICASTSET_ADDR (_EMAC_BASE_ADDR+0x0104u) +#define _EMAC_RXUNICASTCLEAR_ADDR (_EMAC_BASE_ADDR+0x0108u) + +#define EMAC_RXUNICASTSET EMAC_REG(RXUNICASTSET) +#define EMAC_RXUNICASTCLEAR EMAC_REG(RXUNICASTCLEAR) + + + +/******************************************************************************\ +* _____________________ +* | | +* | RXMAXLEN | +* |___________________| +* +* MAXLEN - RX Maximum Length Register +* +* FIELDS (msb -> lsb) +* (rw) RXMAXLEN +* +* MACROS SUPPORTED +* EMAC_FMK y +* EMAC_FMKS . +* EMAC_FMKCHF . +* EMAC_ADDR y +* EMAC_REG y +* EMAC_RGET y +* EMAC_RSET y +* EMAC_FGET y +* EMAC_FSET y +* EMAC_FSETS . +* EMAC_RGETI . +* EMAC_RSETI . +* EMAC_FGETI . +* EMAC_FSETI . +* EMAC_FSETSI . +* +\******************************************************************************/ +#define _EMAC_RXMAXLEN_ADDR (_EMAC_BASE_ADDR+0x010Cu) + +#define EMAC_RXMAXLEN EMAC_REG(RXMAXLEN) + +#define _EMAC_RXMAXLEN_MAXLEN_MASK 0x0000FFFFu +#define _EMAC_RXMAXLEN_MAXLEN_SHIFT 0u +#define EMAC_RXMAXLEN_MAXLEN_DEFAULT 0x000005EEu + +/******************************************************************************\ +* _____________________ +* | | +* | RXBUFFEROFFSET | +* |___________________| +* +* RXBUFFEROFFSET - RX Buffer Offset Register +* +* FIELDS (msb -> lsb) +* (rw) BUFFEROFFSET +* +* MACROS SUPPORTED +* EMAC_FMK y +* EMAC_FMKS . +* EMAC_FMKCHF . +* EMAC_ADDR y +* EMAC_REG y +* EMAC_RGET y +* EMAC_RSET y +* EMAC_FGET y +* EMAC_FSET y +* EMAC_FSETS . +* EMAC_RGETI . +* EMAC_RSETI . +* EMAC_FGETI . +* EMAC_FSETI . +* EMAC_FSETSI . +* +\******************************************************************************/ +#define _EMAC_RXBUFFEROFFSET_ADDR (_EMAC_BASE_ADDR+0x0110u) + +#define EMAC_RXBUFFEROFFSET EMAC_REG(RXBUFFEROFFSET) + +#define _EMAC_RXBUFFEROFFSET_BUFFEROFFSET_MASK 0x0000FFFFu +#define _EMAC_RXBUFFEROFFSET_BUFFEROFFSET_SHIFT 0u +#define EMAC_RXBUFFEROFFSET_BUFFEROFFSET_DEFAULT 0x00000000u +/******************************************************************************\ +* _____________________ +* | | +* | RXFILTERLOWTHRESH | +* |___________________| +* +* RXFILTERLOWTHRESH - RX Filer Low Priority Packets Threshhold +* +* FIELDS (msb -> lsb) +* (rw) FILTERTHRESH +* +* MACROS SUPPORTED +* EMAC_FMK y +* EMAC_FMKS . +* EMAC_FMKCHF . +* EMAC_ADDR y +* EMAC_REG y +* EMAC_RGET y +* EMAC_RSET y +* EMAC_FGET y +* EMAC_FSET y +* EMAC_FSETS . +* EMAC_RGETI . +* EMAC_RSETI . +* EMAC_FGETI . +* EMAC_FSETI . +* EMAC_FSETSI . +* +\******************************************************************************/ +#define _EMAC_RXFILTERLOWTHRESH_ADDR (_EMAC_BASE_ADDR+0x0114u) + +#define EMAC_RXFILTERLOWTHRESH EMAC_REG(RXFILTERLOWTHRESH) + +#define _EMAC_RXFILTERLOWTHRESH_FILTERTHRESH_MASK 0x000000FFu +#define _EMAC_RXFILTERLOWTHRESH_FILTERTHRESH_SHIFT 0u +#define EMAC_RXFILTERLOWTHRESH_FILTERTHRESH_DEFAULT 0x00000000u + + +/******************************************************************************\ +* _____________________ +* | | +* | RXFLOWTHRESH | +* | RXnFLOWTHRESH | +* |___________________| +* +* RXFLOWTHRESH - RX Flow Control Threshhold for RSETI/RGETI +* RX0FLOWTHRESH - RX Channel 0 Flow Control Threshhold +* RX1FLOWTHRESH - RX Channel 1 Flow Control Threshhold +* RX2FLOWTHRESH - RX Channel 2 Flow Control Threshhold +* RX3FLOWTHRESH - RX Channel 3 Flow Control Threshhold +* RX4FLOWTHRESH - RX Channel 4 Flow Control Threshhold +* RX5FLOWTHRESH - RX Channel 5 Flow Control Threshhold +* RX6FLOWTHRESH - RX Channel 6 Flow Control Threshhold +* RX7FLOWTHRESH - RX Channel 7 Flow Control Threshhold +* +* FIELDS (msb -> lsb) +* (rw) FLOWTHRESH +* +* MACROS SUPPORTED +* EMAC_FMK y +* EMAC_FMKS . +* EMAC_FMKCHF . +* EMAC_ADDR y +* EMAC_REG y +* EMAC_RGET y +* EMAC_RSET y +* EMAC_FGET y +* EMAC_FSET y +* EMAC_FSETS . +* EMAC_RGETI y +* EMAC_RSETI y +* EMAC_FGETI y +* EMAC_FSETI y +* EMAC_FSETSI . +* +\******************************************************************************/ +#define _EMAC_RXFLOWTHRESH_BASEADDR (_EMAC_BASE_ADDR+0x0120u) +#define _EMAC_RX0FLOWTHRESH_ADDR (_EMAC_BASE_ADDR+0x0120u) +#define _EMAC_RX1FLOWTHRESH_ADDR (_EMAC_BASE_ADDR+0x0124u) +#define _EMAC_RX2FLOWTHRESH_ADDR (_EMAC_BASE_ADDR+0x0128u) +#define _EMAC_RX3FLOWTHRESH_ADDR (_EMAC_BASE_ADDR+0x012Cu) +#define _EMAC_RX4FLOWTHRESH_ADDR (_EMAC_BASE_ADDR+0x0130u) +#define _EMAC_RX5FLOWTHRESH_ADDR (_EMAC_BASE_ADDR+0x0134u) +#define _EMAC_RX6FLOWTHRESH_ADDR (_EMAC_BASE_ADDR+0x0138u) +#define _EMAC_RX7FLOWTHRESH_ADDR (_EMAC_BASE_ADDR+0x013Cu) + +#define EMAC_RX0FLOWTHRESH EMAC_REG(RX0FLOWTHRESH) +#define EMAC_RX1FLOWTHRESH EMAC_REG(RX1FLOWTHRESH) +#define EMAC_RX2FLOWTHRESH EMAC_REG(RX2FLOWTHRESH) +#define EMAC_RX3FLOWTHRESH EMAC_REG(RX3FLOWTHRESH) +#define EMAC_RX4FLOWTHRESH EMAC_REG(RX4FLOWTHRESH) +#define EMAC_RX5FLOWTHRESH EMAC_REG(RX5FLOWTHRESH) +#define EMAC_RX6FLOWTHRESH EMAC_REG(RX6FLOWTHRESH) +#define EMAC_RX7FLOWTHRESH EMAC_REG(RX7FLOWTHRESH) + +#define _EMAC_RXFLOWTHRESH_FLOWTHRESH_MASK 0x000000FFu +#define _EMAC_RXFLOWTHRESH_FLOWTHRESH_SHIFT 0u +#define EMAC_RXFLOWTHRESH_FLOWTHRESH_DEFAULT 0x00000000u +#define _EMAC_RX0FLOWTHRESH_FLOWTHRESH_MASK 0x000000FFu +#define _EMAC_RX0FLOWTHRESH_FLOWTHRESH_SHIFT 0u +#define EMAC_RX0FLOWTHRESH_FLOWTHRESH_DEFAULT 0x00000000u +#define _EMAC_RX1FLOWTHRESH_FLOWTHRESH_MASK 0x000000FFu +#define _EMAC_RX1FLOWTHRESH_FLOWTHRESH_SHIFT 0u +#define EMAC_RX1FLOWTHRESH_FLOWTHRESH_DEFAULT 0x00000000u +#define _EMAC_RX2FLOWTHRESH_FLOWTHRESH_MASK 0x000000FFu +#define _EMAC_RX2FLOWTHRESH_FLOWTHRESH_SHIFT 0u +#define EMAC_RX2FLOWTHRESH_FLOWTHRESH_DEFAULT 0x00000000u +#define _EMAC_RX3FLOWTHRESH_FLOWTHRESH_MASK 0x000000FFu +#define _EMAC_RX3FLOWTHRESH_FLOWTHRESH_SHIFT 0u +#define EMAC_RX3FLOWTHRESH_FLOWTHRESH_DEFAULT 0x00000000u +#define _EMAC_RX4FLOWTHRESH_FLOWTHRESH_MASK 0x000000FFu +#define _EMAC_RX4FLOWTHRESH_FLOWTHRESH_SHIFT 0u +#define EMAC_RX4FLOWTHRESH_FLOWTHRESH_DEFAULT 0x00000000u +#define _EMAC_RX5FLOWTHRESH_FLOWTHRESH_MASK 0x000000FFu +#define _EMAC_RX5FLOWTHRESH_FLOWTHRESH_SHIFT 0u +#define EMAC_RX5FLOWTHRESH_FLOWTHRESH_DEFAULT 0x00000000u +#define _EMAC_RX6FLOWTHRESH_FLOWTHRESH_MASK 0x000000FFu +#define _EMAC_RX6FLOWTHRESH_FLOWTHRESH_SHIFT 0u +#define EMAC_RX6FLOWTHRESH_FLOWTHRESH_DEFAULT 0x00000000u +#define _EMAC_RX7FLOWTHRESH_FLOWTHRESH_MASK 0x000000FFu +#define _EMAC_RX7FLOWTHRESH_FLOWTHRESH_SHIFT 0u +#define EMAC_RX7FLOWTHRESH_FLOWTHRESH_DEFAULT 0x00000000u +/******************************************************************************\ +* _____________________ +* | | +* | RXFREEBUFFER | +* | RXnFREEBUFFER | +* |___________________| +* +* RXFREEBUFFER - RX Free Buffer Count for RSETI/RGETI +* RX0FREEBUFFER - RX Channel 0 Free Buffer Count Register +* RX1FREEBUFFER - RX Channel 1 Free Buffer Count Register +* RX2FREEBUFFER - RX Channel 2 Free Buffer Count Register +* RX3FREEBUFFER - RX Channel 3 Free Buffer Count Register +* RX4FREEBUFFER - RX Channel 4 Free Buffer Count Register +* RX5FREEBUFFER - RX Channel 5 Free Buffer Count Register +* RX6FREEBUFFER - RX Channel 6 Free Buffer Count Register +* RX7FREEBUFFER - RX Channel 7 Free Buffer Count Register +* +* FIELDS (msb -> lsb) +* (rw) FREEBUF +* +* MACROS SUPPORTED +* EMAC_FMK y +* EMAC_FMKS . +* EMAC_FMKCHF . +* EMAC_ADDR y +* EMAC_REG y +* EMAC_RGET y +* EMAC_RSET y +* EMAC_FGET y +* EMAC_FSET y +* EMAC_FSETS . +* EMAC_RGETI y +* EMAC_RSETI y +* EMAC_FGETI y +* EMAC_FSETI y +* EMAC_FSETSI . +* +\******************************************************************************/ +#define _EMAC_RXFREEBUFFER_BASEADDR (_EMAC_BASE_ADDR+0x0140u) +#define _EMAC_RX0FREEBUFFER_ADDR (_EMAC_BASE_ADDR+0x0140u) +#define _EMAC_RX1FREEBUFFER_ADDR (_EMAC_BASE_ADDR+0x0144u) +#define _EMAC_RX2FREEBUFFER_ADDR (_EMAC_BASE_ADDR+0x0148u) +#define _EMAC_RX3FREEBUFFER_ADDR (_EMAC_BASE_ADDR+0x014Cu) +#define _EMAC_RX4FREEBUFFER_ADDR (_EMAC_BASE_ADDR+0x0150u) +#define _EMAC_RX5FREEBUFFER_ADDR (_EMAC_BASE_ADDR+0x0154u) +#define _EMAC_RX6FREEBUFFER_ADDR (_EMAC_BASE_ADDR+0x0158u) +#define _EMAC_RX7FREEBUFFER_ADDR (_EMAC_BASE_ADDR+0x015Cu) + +#define EMAC_RX0FREEBUFFER EMAC_REG(RX0FREEBUFFER) +#define EMAC_RX1FREEBUFFER EMAC_REG(RX1FREEBUFFER) +#define EMAC_RX2FREEBUFFER EMAC_REG(RX2FREEBUFFER) +#define EMAC_RX3FREEBUFFER EMAC_REG(RX3FREEBUFFER) +#define EMAC_RX4FREEBUFFER EMAC_REG(RX4FREEBUFFER) +#define EMAC_RX5FREEBUFFER EMAC_REG(RX5FREEBUFFER) +#define EMAC_RX6FREEBUFFER EMAC_REG(RX6FREEBUFFER) +#define EMAC_RX7FREEBUFFER EMAC_REG(RX7FREEBUFFER) + +#define _EMAC_RXFREEBUFFER_FREEBUF_MASK 0x0000FFFFu +#define _EMAC_RXFREEBUFFER_FREEBUF_SHIFT 0u +#define EMAC_RXFREEBUFFER_FREEBUF_DEFAULT 0x00000000u +#define _EMAC_RX0FREEBUFFER_FREEBUF_MASK 0x0000FFFFu +#define _EMAC_RX0FREEBUFFER_FREEBUF_SHIFT 0u +#define EMAC_RX0FREEBUFFER_FREEBUF_DEFAULT 0x00000000u +#define _EMAC_RX1FREEBUFFER_FREEBUF_MASK 0x0000FFFFu +#define _EMAC_RX1FREEBUFFER_FREEBUF_SHIFT 0u +#define EMAC_RX1FREEBUFFER_FREEBUF_DEFAULT 0x00000000u +#define _EMAC_RX2FREEBUFFER_FREEBUF_MASK 0x0000FFFFu +#define _EMAC_RX2FREEBUFFER_FREEBUF_SHIFT 0u +#define EMAC_RX2FREEBUFFER_FREEBUF_DEFAULT 0x00000000u +#define _EMAC_RX3FREEBUFFER_FREEBUF_MASK 0x0000FFFFu +#define _EMAC_RX3FREEBUFFER_FREEBUF_SHIFT 0u +#define EMAC_RX3FREEBUFFER_FREEBUF_DEFAULT 0x00000000u +#define _EMAC_RX4FREEBUFFER_FREEBUF_MASK 0x0000FFFFu +#define _EMAC_RX4FREEBUFFER_FREEBUF_SHIFT 0u +#define EMAC_RX4FREEBUFFER_FREEBUF_DEFAULT 0x00000000u +#define _EMAC_RX5FREEBUFFER_FREEBUF_MASK 0x0000FFFFu +#define _EMAC_RX5FREEBUFFER_FREEBUF_SHIFT 0u +#define EMAC_RX5FREEBUFFER_FREEBUF_DEFAULT 0x00000000u +#define _EMAC_RX6FREEBUFFER_FREEBUF_MASK 0x0000FFFFu +#define _EMAC_RX6FREEBUFFER_FREEBUF_SHIFT 0u +#define EMAC_RX6FREEBUFFER_FREEBUF_DEFAULT 0x00000000u +#define _EMAC_RX7FREEBUFFER_FREEBUF_MASK 0x0000FFFFu +#define _EMAC_RX7FREEBUFFER_FREEBUF_SHIFT 0u +#define EMAC_RX7FREEBUFFER_FREEBUF_DEFAULT 0x00000000u + + +/******************************************************************************\ +* _____________________ +* | | +* | MACCONTROL | +* |___________________| +* +* MACCONTROL - MAC Control Register +* +* FIELDS (msb -> lsb) +* (rw) TXPTYPE - TX Priority Queue Type +* (rw) TXPACE - TX Pacing Enable +* (rw) MIIEN - MII Enable +* (rw) TXFLOWEN - TX Flow Control Enable +* (rw) RXFLOWEN - RX Flow Control Enable +* (rw) MTEST - Manufacturer's Test Enable +* (rw) LOOPBACK - Loopback Mode Enable +* (rw) FULLDUPLEX - Full Duplex Mode Enable +* +* MACROS SUPPORTED +* EMAC_FMK y +* EMAC_FMKS y +* EMAC_FMKCHF . +* EMAC_ADDR y +* EMAC_REG y +* EMAC_RGET y +* EMAC_RSET y +* EMAC_FGET y +* EMAC_FSET y +* EMAC_FSETS y +* EMAC_RGETI . +* EMAC_RSETI . +* EMAC_FGETI . +* EMAC_FSETI . +* EMAC_FSETSI . +* +\******************************************************************************/ +#define _EMAC_MACCONTROL_ADDR (_EMAC_BASE_ADDR+0x0160u) + +#define EMAC_MACCONTROL EMAC_REG(MACCONTROL) + +#define _EMAC_MACCONTROL_TXPTYPE_MASK 0x00000200u +#define _EMAC_MACCONTROL_TXPTYPE_SHIFT 9u +#define EMAC_MACCONTROL_TXPTYPE_DEFAULT 0x00000000u +#define EMAC_MACCONTROL_TXPTYPE_RROBIN 0u +#define EMAC_MACCONTROL_TXPTYPE_CHANNELPRI 1u + +#define _EMAC_MACCONTROL_TXPACE_MASK 0x00000040u +#define _EMAC_MACCONTROL_TXPACE_SHIFT 6u +#define EMAC_MACCONTROL_TXPACE_DEFAULT 0x00000000u +#define EMAC_MACCONTROL_TXPACE_DISABLE 0u +#define EMAC_MACCONTROL_TXPACE_ENABLE 1u + +#define _EMAC_MACCONTROL_MIIEN_MASK 0x00000020u +#define _EMAC_MACCONTROL_MIIEN_SHIFT 5u +#define EMAC_MACCONTROL_MIIEN_DEFAULT 0x00000000u +#define EMAC_MACCONTROL_MIIEN_DISABLE 0u +#define EMAC_MACCONTROL_MIIEN_ENABLE 1u + +#define _EMAC_MACCONTROL_TXFLOWEN_MASK 0x00000010u +#define _EMAC_MACCONTROL_TXFLOWEN_SHIFT 4u +#define EMAC_MACCONTROL_TXFLOWEN_DEFAULT 0x00000000u +#define EMAC_MACCONTROL_TXFLOWEN_DISABLE 0u +#define EMAC_MACCONTROL_TXFLOWEN_ENABLE 1u + +#define _EMAC_MACCONTROL_RXFLOWEN_MASK 0x00000008u +#define _EMAC_MACCONTROL_RXFLOWEN_SHIFT 3u +#define EMAC_MACCONTROL_RXFLOWEN_DEFAULT 0x00000000u +#define EMAC_MACCONTROL_RXFLOWEN_DISABLE 0u +#define EMAC_MACCONTROL_RXFLOWEN_ENABLE 1u + +#define _EMAC_MACCONTROL_MTEST_MASK 0x00000004u +#define _EMAC_MACCONTROL_MTEST_SHIFT 2u +#define EMAC_MACCONTROL_MTEST_DEFAULT 0x00000000u +#define EMAC_MACCONTROL_MTEST_DISABLE 0u +#define EMAC_MACCONTROL_MTEST_ENABLE 1u + +#define _EMAC_MACCONTROL_LOOPBACK_MASK 0x00000002u +#define _EMAC_MACCONTROL_LOOPBACK_SHIFT 1u +#define EMAC_MACCONTROL_LOOPBACK_DEFAULT 0x00000000u +#define EMAC_MACCONTROL_LOOPBACK_DISABLE 0u +#define EMAC_MACCONTROL_LOOPBACK_ENABLE 1u + +#define _EMAC_MACCONTROL_FULLDUPLEX_MASK 0x00000001u +#define _EMAC_MACCONTROL_FULLDUPLEX_SHIFT 0u +#define EMAC_MACCONTROL_FULLDUPLEX_DEFAULT 0x00000000u +#define EMAC_MACCONTROL_FULLDUPLEX_DISABLE 0u +#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE 1u + + + +/******************************************************************************\ +* _____________________ +* | | +* | MACSTATUS | +* |___________________| +* +* MACSTATUS - MAC Status Register +* +* FIELDS (msb -> lsb) +* (r) TXERRCODE - TX Host Error Code +* (r) THERRCH - TX Host Error Channel +* (r) RXERRCODE - RX Host Error Code +* (r) RXERRCH - RX Host Error Channel +* (r) RXQOSACT - RX QOS Service Currently Active +* (r) RXFLOWACT - RX Flow Control Currently Active +* (r) TXFLOWACT - TX Flow Control Currently Active +* +* MACROS SUPPORTED +* EMAC_FMK y +* EMAC_FMKS y +* EMAC_FMKCHF . +* EMAC_ADDR y +* EMAC_REG y +* EMAC_RGET y +* EMAC_RSET y +* EMAC_FGET y +* EMAC_FSET y +* EMAC_FSETS y +* EMAC_RGETI . +* EMAC_RSETI . +* EMAC_FGETI . +* EMAC_FSETI . +* EMAC_FSETSI . +* +\******************************************************************************/ +#define _EMAC_MACSTATUS_ADDR (_EMAC_BASE_ADDR+0x0164u) + +#define EMAC_MACSTATUS EMAC_REG(MACSTATUS) + +#define _EMAC_MACSTATUS_TXERRCODE_MASK 0x00F00000u +#define _EMAC_MACSTATUS_TXERRCODE_SHIFT 20u +#define EMAC_MACSTATUS_TXERRCODE_DEFAULT 0x00000000u +#define EMAC_MACSTATUS_TXERRCODE_NOERROR 0u +#define EMAC_MACSTATUS_TXERRCODE_SOPERROR 1u +#define EMAC_MACSTATUS_TXERRCODE_OWNERSHIP 2u +#define EMAC_MACSTATUS_TXERRCODE_NOEOP 3u +#define EMAC_MACSTATUS_TXERRCODE_NULLPTR 4u +#define EMAC_MACSTATUS_TXERRCODE_NULLLEN 5u +#define EMAC_MACSTATUS_TXERRCODE_LENRRROR 6u + +#define _EMAC_MACSTATUS_TXERRCH_MASK 0x00070000u +#define _EMAC_MACSTATUS_TXERRCH_SHIFT 16u +#define EMAC_MACSTATUS_TXERRCH_DEFAULT 0x00000000u + +#define _EMAC_MACSTATUS_RXERRCODE_MASK 0x0000F000u +#define _EMAC_MACSTATUS_RXERRCODE_SHIFT 12u +#define EMAC_MACSTATUS_RXERRCODE_DEFAULT 0x00000000u +#define EMAC_MACSTATUS_RXERRCODE_NOERROR 0u +#define EMAC_MACSTATUS_RXERRCODE_SOPERROR 1u +#define EMAC_MACSTATUS_RXERRCODE_OWNERSHIP 2u +#define EMAC_MACSTATUS_RXERRCODE_NOEOP 3u +#define EMAC_MACSTATUS_RXERRCODE_NULLPTR 4u +#define EMAC_MACSTATUS_RXERRCODE_NULLLEN 5u +#define EMAC_MACSTATUS_RXERRCODE_LENRRROR 6u + +#define _EMAC_MACSTATUS_RXERRCH_MASK 0x00000700u +#define _EMAC_MACSTATUS_RXERRCH_SHIFT 8u +#define EMAC_MACSTATUS_RXERRCH_DEFAULT 0x00000000u + +#define _EMAC_MACSTATUS_RXQOSACT_MASK 0x00000004u +#define _EMAC_MACSTATUS_RXQOSACT_SHIFT 2u +#define EMAC_MACSTATUS_RXQOSACT_DEFAULT 0x00000000u + +#define _EMAC_MACSTATUS_RXFLOWACT_MASK 0x00000002u +#define _EMAC_MACSTATUS_RXFLOWACT_SHIFT 1u +#define EMAC_MACSTATUS_RXFLOWACT_DEFAULT 0x00000000u + +#define _EMAC_MACSTATUS_TXFLOWACT_MASK 0x00000001u +#define _EMAC_MACSTATUS_TXFLOWACT_SHIFT 0u +#define EMAC_MACSTATUS_TXFLOWACT_DEFAULT 0x00000000u + +/******************************************************************************\ +* _____________________ +* | | +* | EMCONTROL | +* |___________________| +* +* EMCONTROL - Emulation Control Register +* +* FIELDS (msb -> lsb) +* (rw) SOFT - Emulation Soft Bit +* (rw) FREE - Emulation Free Bit +* +* MACROS SUPPORTED +* EMAC_FMK y +* EMAC_FMKS . +* EMAC_FMKCHF . +* EMAC_ADDR y +* EMAC_REG y +* EMAC_RGET y +* EMAC_RSET y +* EMAC_FGET y +* EMAC_FSET y +* EMAC_FSETS . +* EMAC_RGETI . +* EMAC_RSETI . +* EMAC_FGETI . +* EMAC_FSETI . +* EMAC_FSETSI . +* +\******************************************************************************/ +#define _EMAC_EMCONTROL_ADDR (_EMAC_BASE_ADDR+0x0168u) + +#define EMAC_EMCONTROL EMAC_REG(EMCONTROL) + +#define _EMAC_EMCONTROL_SOFT_MASK 0x00000002u +#define _EMAC_EMCONTROL_SOFT_SHIFT 1u + +#define _EMAC_EMCONTROL_FREE_MASK 0x00000001u +#define _EMAC_EMCONTROL_FREE_SHIFT 0u + + + +/******************************************************************************\ +* _____________________ +* | | +* | MACINVECTOR | +* |___________________| +* +* MACINVECTOR - MAC Input Vector +* +* FIELDS (msb -> lsb) +* (r) USERINT - MDIO User Interrupt +* (r) LINKINT - MDIO Link Change Interrupt +* (r) HOSTPEND - Host Pending Interrupt +* (r) STATPEND - Statistics Interrupt +* (r) RXPEND - RX Pending Interrupt Flags (7-0) +* (r) TXPEND - TX Pending Interrupt Falgs (7-0) +* +* MACROS SUPPORTED +* EMAC_FMK y +* EMAC_FMKS . +* EMAC_FMKCHF . +* EMAC_ADDR y +* EMAC_REG y +* EMAC_RGET y +* EMAC_RSET . +* EMAC_FGET y +* EMAC_FSET . +* EMAC_FSETS . +* EMAC_RGETI . +* EMAC_RSETI . +* EMAC_FGETI . +* EMAC_FSETI . +* EMAC_FSETSI . +* +\******************************************************************************/ +#define _EMAC_MACINVECTOR_ADDR (_EMAC_BASE_ADDR+0x0180u) + +#define EMAC_MACINVECTOR EMAC_REG(MACINVECTOR) + +#define _EMAC_MACINVECTOR_USERINT_MASK 0x80000000u +#define _EMAC_MACINVECTOR_USERINT_SHIFT 31u +#define EMAC_MACINVECTOR_USERINT_DEFAULT 0x00000000u +#define _EMAC_MACINVECTOR_LINKINT_MASK 0x40000000u +#define _EMAC_MACINVECTOR_LINKINT_SHIFT 30u +#define EMAC_MACINVECTOR_LINKINT_DEFAULT 0x00000000u +#define _EMAC_MACINVECTOR_HOSTPEND_MASK 0x00020000u +#define _EMAC_MACINVECTOR_HOSTPEND_SHIFT 17u +#define EMAC_MACINVECTOR_HOSTPEND_DEFAULT 0x00000000u +#define _EMAC_MACINVECTOR_STATPEND_MASK 0x00010000u +#define _EMAC_MACINVECTOR_STATPEND_SHIFT 16u +#define EMAC_MACINVECTOR_STATPEND_DEFAULT 0x00000000u +#define _EMAC_MACINVECTOR_RXPEND_MASK 0x0000FF00u +#define _EMAC_MACINVECTOR_RXPEND_SHIFT 8u +#define EMAC_MACINVECTOR_RXPEND_DEFAULT 0x00000000u +#define _EMAC_MACINVECTOR_TXPEND_MASK 0x000000FFu +#define _EMAC_MACINVECTOR_TXPEND_SHIFT 0u +#define EMAC_MACINVECTOR_TXPEND_DEFAULT 0x00000000u + + +/******************************************************************************\ +* _____________________ +* | | +* | MACEOIVECTOR | +* |___________________| +* +* MACEOIVECTOR - MAC EOI Vector +* +* FIELDS (msb -> lsb) +* (r/w) Flags +* +* MACROS SUPPORTED +* EMAC_FMK . +* EMAC_FMKS . +* EMAC_FMKCHF . +* EMAC_ADDR y +* EMAC_REG y +* EMAC_RGET y +* EMAC_RSET y +* EMAC_FGET . +* EMAC_FSET . +* EMAC_FSETS . +* EMAC_RGETI . +* EMAC_RSETI . +* EMAC_FGETI . +* EMAC_FSETI . +* EMAC_FSETSI . +* +\******************************************************************************/ +#define _EMAC_MACEOIVECTOR_ADDR (_EMAC_BASE_ADDR+0x0184u) + +#define EMAC_MACEOIVECTOR EMAC_REG(MACEOIVECTOR) + + +/******************************************************************************\ +* _____________________ +* | | +* | TXINTSTATRAW | +* | TXINTSTATMASKED | +* | TXINTMASKSET | +* | TXINTMASKCLEAR | +* | RXINTSTATRAW | +* | RXINTSTATMASKED | +* | RXINTMASKSET | +* | RXINTMASKCLEAR | +* |___________________| +* +* TXINTSTATRAW - TX Interrupt Status Register (Unmasked) +* TXINTSTATMASKED - TX Interrupt Status Register (Masked) +* TXINTMASKSET - TX Interrupt Mask Set Register +* TXINTMASKCLEAR - TX Interrupt Mask Clear Register +* RXINTSTATRAW - RX Interrupt Status Register (Unmasked) +* RXINTSTATMASKED - RX Interrupt Status Register (Masked) +* RXINTMASKSET - RX Interrupt Mask Set Register +* RXINTMASKCLEAR - RX Interrupt Mask Clear Register +* +* FIELDS (msb -> lsb) +* (r)(r/ws)(r/wc) Channel Flags (use EMAC_FMKCHF) +* +* MACROS SUPPORTED +* EMAC_FMK . +* EMAC_FMKS . +* EMAC_FMKCHF y +* EMAC_ADDR y +* EMAC_REG y +* EMAC_RGET y +* EMAC_RSET y +* EMAC_FGET . +* EMAC_FSET . +* EMAC_FSETS . +* EMAC_RGETI . +* EMAC_RSETI . +* EMAC_FGETI . +* EMAC_FSETI . +* EMAC_FSETSI . +* +\******************************************************************************/ +#define _EMAC_TXINTSTATRAW_ADDR (_EMAC_BASE_ADDR+0x0170u) +#define _EMAC_TXINTSTATMASKED_ADDR (_EMAC_BASE_ADDR+0x0174u) +#define _EMAC_TXINTMASKSET_ADDR (_EMAC_BASE_ADDR+0x0178u) +#define _EMAC_TXINTMASKCLEAR_ADDR (_EMAC_BASE_ADDR+0x017Cu) +#define _EMAC_RXINTSTATRAW_ADDR (_EMAC_BASE_ADDR+0x0190u) +#define _EMAC_RXINTSTATMASKED_ADDR (_EMAC_BASE_ADDR+0x0194u) +#define _EMAC_RXINTMASKSET_ADDR (_EMAC_BASE_ADDR+0x0198u) +#define _EMAC_RXINTMASKCLEAR_ADDR (_EMAC_BASE_ADDR+0x019Cu) + +#define EMAC_TXINTSTATRAW EMAC_REG(TXINTSTATRAW) +#define EMAC_TXINTSTATMASKED EMAC_REG(TXINTSTATMASKED) +#define EMAC_TXINTMASKSET EMAC_REG(TXINTMASKSET) +#define EMAC_TXINTMASKCLEAR EMAC_REG(TXINTMASKCLEAR) +#define EMAC_RXINTSTATRAW EMAC_REG(RXINTSTATRAW) +#define EMAC_RXINTSTATMASKED EMAC_REG(RXINTSTATMASKED) +#define EMAC_RXINTMASKSET EMAC_REG(RXINTMASKSET) +#define EMAC_RXINTMASKCLEAR EMAC_REG(RXINTMASKCLEAR) + + + +/******************************************************************************\ +* _____________________ +* | | +* | MACINTSTATRAW | +* | MACINTSTATMASKED | +* | MACINTMASKSET | +* | MACINTMASKCLEAR | +* |___________________| +* +* MACINTSTATRAW - MAC Interrupt Status Register (Unmasked) +* MACINTSTATMASKED - MAC Interrupt Status Register (Masked) +* MACINTMASKSET - MAC Interrupt Mask Set Register +* MACINTMASKCLEAR - MAC Interrupt Mask Clear Register +* +* FIELDS (msb -> lsb) +* (r)(r/ws)(r/wc) HOSTERRINT - Host Error Interrupt +* (r)(r/ws)(r/wc) STATINT - Statistics Interrupt +* +* MACROS SUPPORTED +* EMAC_FMK y +* EMAC_FMKS . +* EMAC_FMKCHF . +* EMAC_ADDR y +* EMAC_REG y +* EMAC_RGET y +* EMAC_RSET y +* EMAC_FGET y +* EMAC_FSET y +* EMAC_FSETS . +* EMAC_RGETI . +* EMAC_RSETI . +* EMAC_FGETI . +* EMAC_FSETI . +* EMAC_FSETSI . +* +\******************************************************************************/ +#define _EMAC_MACINTSTATRAW_ADDR (_EMAC_BASE_ADDR+0x01A0u) +#define _EMAC_MACINTSTATMASKED_ADDR (_EMAC_BASE_ADDR+0x01A4u) +#define _EMAC_MACINTMASKSET_ADDR (_EMAC_BASE_ADDR+0x01A8u) +#define _EMAC_MACINTMASKCLEAR_ADDR (_EMAC_BASE_ADDR+0x01ACu) + +#define EMAC_MACINTSTATRAW EMAC_REG(MACINTSTATRAW) +#define EMAC_MACINTSTATMASKED EMAC_REG(MACINTSTATMASKED) +#define EMAC_MACINTMASKSET EMAC_REG(MACINTMASKSET) +#define EMAC_MACINTMASKCLEAR EMAC_REG(MACINTMASKCLEAR) + +#define _EMAC_MACINTSTATRAW_HOSTERRINT_MASK 0x00000002u +#define _EMAC_MACINTSTATMASKED_HOSTERRINT_MASK 0x00000002u +#define _EMAC_MACINTMASKSET_HOSTERRINT_MASK 0x00000002u +#define _EMAC_MACINTMASKCLEAR_HOSTERRINT_MASK 0x00000002u +#define _EMAC_MACINTSTATRAW_HOSTERRINT_SHIFT 1u +#define EMAC_MACINTSTATRAW_HOSTERRINT_DEFAULT 0x00000000u +#define _EMAC_MACINTSTATMASKED_HOSTERRINT_SHIFT 1u +#define EMAC_MACINTSTATMASKED_HOSTERRINT_DEFAULT 0x00000000u +#define _EMAC_MACINTMASKSET_HOSTERRINT_SHIFT 1u +#define EMAC_MACINTMASKSET_HOSTERRINT_DEFAULT 0x00000000u +#define _EMAC_MACINTMASKCLEAR_HOSTERRINT_SHIFT 1u +#define EMAC_MACINTMASKCLEAR_HOSTERRINT_DEFAULT 0x00000000u + +#define _EMAC_MACINTSTATRAW_STATINT_MASK 0x00000001u +#define _EMAC_MACINTSTATMASKED_STATINT_MASK 0x00000001u +#define _EMAC_MACINTMASKSET_STATINT_MASK 0x00000001u +#define _EMAC_MACINTMASKCLEAR_STATINT_MASK 0x00000001u +#define _EMAC_MACINTSTATRAW_STATINT_SHIFT 0u +#define EMAC_MACINTSTATRAW_STATINT_DEFAULT 0x00000000u +#define _EMAC_MACINTSTATMASKED_STATINT_SHIFT 0u +#define EMAC_MACINTSTATMASKED_STATINT_DEFAULT 0x00000000u +#define _EMAC_MACINTMASKSET_STATINT_SHIFT 0u +#define EMAC_MACINTMASKSET_STATINT_DEFAULT 0x00000000u +#define _EMAC_MACINTMASKCLEAR_STATINT_SHIFT 0u +#define EMAC_MACINTMASKCLEAR_STATINT_DEFAULT 0x00000000u + +/******************************************************************************\ +* _____________________ +* | | +* | MACADDRL | +* | MACADDRLn | +* |___________________| +* +* MACADDRL - MAC Address Lower Byte Register for RSETI/RGETI +* MACADDRL0 - MAC Address Channel 0 Lower Byte Register +* MACADDRL1 - MAC Address Channel 1 Lower Byte Register +* MACADDRL2 - MAC Address Channel 2 Lower Byte Register +* MACADDRL3 - MAC Address Channel 3 Lower Byte Register +* MACADDRL4 - MAC Address Channel 4 Lower Byte Register +* MACADDRL5 - MAC Address Channel 5 Lower Byte Register +* MACADDRL6 - MAC Address Channel 6 Lower Byte Register +* MACADDRL7 - MAC Address Channel 7 Lower Byte Register +* +* FIELDS (msb -> lsb) +* (rw) MACADDR8 - 8 bits of MAC Address +* +* MACROS SUPPORTED +* EMAC_FMK y +* EMAC_FMKS . +* EMAC_FMKCHF . +* EMAC_ADDR y +* EMAC_REG y +* EMAC_RGET y +* EMAC_RSET y +* EMAC_FGET y +* EMAC_FSET y +* EMAC_FSETS . +* EMAC_RGETI y +* EMAC_RSETI y +* EMAC_FGETI y +* EMAC_FSETI y +* EMAC_FSETSI . +* +\******************************************************************************/ +#define _EMAC_MACADDRL_BASEADDR (_EMAC_BASE_ADDR+0x01B0u) +#define _EMAC_MACADDRL0_ADDR (_EMAC_BASE_ADDR+0x01B0u) +#define _EMAC_MACADDRL1_ADDR (_EMAC_BASE_ADDR+0x01B4u) +#define _EMAC_MACADDRL2_ADDR (_EMAC_BASE_ADDR+0x01B8u) +#define _EMAC_MACADDRL3_ADDR (_EMAC_BASE_ADDR+0x01BCu) +#define _EMAC_MACADDRL4_ADDR (_EMAC_BASE_ADDR+0x01C0u) +#define _EMAC_MACADDRL5_ADDR (_EMAC_BASE_ADDR+0x01C4u) +#define _EMAC_MACADDRL6_ADDR (_EMAC_BASE_ADDR+0x01C8u) +#define _EMAC_MACADDRL7_ADDR (_EMAC_BASE_ADDR+0x01CCu) + +#define EMAC_MACADDRL0 EMAC_REG(MACADDRL0) +#define EMAC_MACADDRL1 EMAC_REG(MACADDRL1) +#define EMAC_MACADDRL2 EMAC_REG(MACADDRL2) +#define EMAC_MACADDRL3 EMAC_REG(MACADDRL3) +#define EMAC_MACADDRL4 EMAC_REG(MACADDRL4) +#define EMAC_MACADDRL5 EMAC_REG(MACADDRL5) +#define EMAC_MACADDRL6 EMAC_REG(MACADDRL6) +#define EMAC_MACADDRL7 EMAC_REG(MACADDRL7) + +#define _EMAC_MACADDRL_MACADDR8_MASK 0x000000FFu +#define _EMAC_MACADDRL_MACADDR8_SHIFT 0u +#define EMAC_MACADDRL_MACADDR8_DEFAULT 0x00000000u +#define _EMAC_MACADDRL0_MACADDR8_MASK 0x000000FFu +#define _EMAC_MACADDRL0_MACADDR8_SHIFT 0u +#define EMAC_MACADDRL0_MACADDR8_DEFAULT 0x00000000u +#define _EMAC_MACADDRL1_MACADDR8_MASK 0x000000FFu +#define _EMAC_MACADDRL1_MACADDR8_SHIFT 0u +#define EMAC_MACADDRL1_MACADDR8_DEFAULT 0x00000000u +#define _EMAC_MACADDRL2_MACADDR8_MASK 0x000000FFu +#define _EMAC_MACADDRL2_MACADDR8_SHIFT 0u +#define EMAC_MACADDRL2_MACADDR8_DEFAULT 0x00000000u +#define _EMAC_MACADDRL3_MACADDR8_MASK 0x000000FFu +#define _EMAC_MACADDRL3_MACADDR8_SHIFT 0u +#define EMAC_MACADDRL3_MACADDR8_DEFAULT 0x00000000u +#define _EMAC_MACADDRL4_MACADDR8_MASK 0x000000FFu +#define _EMAC_MACADDRL4_MACADDR8_SHIFT 0u +#define EMAC_MACADDRL4_MACADDR8_DEFAULT 0x00000000u +#define _EMAC_MACADDRL5_MACADDR8_MASK 0x000000FFu +#define _EMAC_MACADDRL5_MACADDR8_SHIFT 0u +#define EMAC_MACADDRL5_MACADDR8_DEFAULT 0x00000000u +#define _EMAC_MACADDRL6_MACADDR8_MASK 0x000000FFu +#define _EMAC_MACADDRL6_MACADDR8_SHIFT 0u +#define EMAC_MACADDRL6_MACADDR8_DEFAULT 0x00000000u +#define _EMAC_MACADDRL7_MACADDR8_MASK 0x000000FFu +#define _EMAC_MACADDRL7_MACADDR8_SHIFT 0u +#define EMAC_MACADDRL7_MACADDR8_DEFAULT 0x00000000u + + +/******************************************************************************\ +* _____________________ +* | | +* | MACADDRM | +* |___________________| +* +* MACADDRM - MAC Address Byte 1 Register (bits 15:8) +* +* FIELDS (msb -> lsb) +* (rw) MACADDR8 - 8 bits of MAC Address +* +* MACROS SUPPORTED +* EMAC_FMK y +* EMAC_FMKS . +* EMAC_FMKCHF . +* EMAC_ADDR y +* EMAC_RGET y +* EMAC_RSET y +* EMAC_FGET y +* EMAC_FSET y +* EMAC_FSETS . +* EMAC_RGETI . +* EMAC_RSETI . +* EMAC_FGETI . +* EMAC_FSETI . +* EMAC_FSETSI . +* +\******************************************************************************/ +#define _EMAC_MACADDRM_ADDR (_EMAC_BASE_ADDR+0x01D0u) + +#define EMAC_MACADDRM EMAC_REG(MACADDRM) + +#define _EMAC_MACADDRM_MACADDR8_MASK 0x000000FFu +#define _EMAC_MACADDRM_MACADDR8_SHIFT 0u +#define EMAC_MACADDRM_MACADDR8_DEFAULT 0x00000000u + + + +/******************************************************************************\ +* _____________________ +* | | +* | MACADDRH | +* |___________________| +* +* MACADDRH - MAC Address High Bytes Register (bits 47:16) +* +* FIELDS (msb -> lsb) +* (rw) MACADDR32 - 32 bits of MAC Address +* +* MACROS SUPPORTED +* EMAC_FMK y +* EMAC_FMKS . +* EMAC_FMKCHF . +* EMAC_ADDR y +* EMAC_REG y +* EMAC_RGET y +* EMAC_RSET y +* EMAC_FGET y +* EMAC_FSET y +* EMAC_FSETS . +* EMAC_RGETI . +* EMAC_RSETI . +* EMAC_FGETI . +* EMAC_FSETI . +* EMAC_FSETSI . +* +\******************************************************************************/ +#define _EMAC_MACADDRH_ADDR (_EMAC_BASE_ADDR+0x01D4u) + +#define EMAC_MACADDRH EMAC_REG(MACADDRH) + +#define _EMAC_MACADDRH_MACADDR32_MASK 0xFFFFFFFFu +#define _EMAC_MACADDRH_MACADDR32_SHIFT 0u +#define EMAC_MACADDRH_MACADDR32_DEFAULT 0x00000000u + + + +/******************************************************************************\ +* _____________________ +* | | +* | MACHASH1 | +* | MACHASH2 | +* |___________________| +* +* MACHASH1 - MAC Address Hash 1 Register +* MACHASH2 - MAC Address Hash 2 Register +* +* FIELDS (msb -> lsb) +* (rw) HASHBITS - 32 Hash Bits +* +* MACROS SUPPORTED +* EMAC_FMK y +* EMAC_FMKS . +* EMAC_FMKCHF . +* EMAC_ADDR y +* EMAC_REG y +* EMAC_RGET y +* EMAC_RSET y +* EMAC_FGET y +* EMAC_FSET y +* EMAC_FSETS . +* EMAC_RGETI . +* EMAC_RSETI . +* EMAC_FGETI . +* EMAC_FSETI . +* EMAC_FSETSI . +* +\******************************************************************************/ +#define _EMAC_MACHASH1_ADDR (_EMAC_BASE_ADDR+0x01D8u) +#define _EMAC_MACHASH2_ADDR (_EMAC_BASE_ADDR+0x01DCu) + +#define EMAC_MACHASH1 EMAC_REG(MACHASH1) +#define EMAC_MACHASH2 EMAC_REG(MACHASH2) + +#define _EMAC_MACHASH1_HASHBITS_MASK 0xFFFFFFFFu +#define EMAC_MACHASH1_HASHBITS_DEFAULT 0x00000000u +#define _EMAC_MACHASH1_HASHBITS_SHIFT 0u +#define _EMAC_MACHASH2_HASHBITS_MASK 0xFFFFFFFFu +#define _EMAC_MACHASH2_HASHBITS_SHIFT 0u +#define EMAC_MACHASH2_HASHBITS_DEFAULT 0x00000000u + + + + +/******************************************************************************\ +* _____________________ +* | | +* | BOFFTEST | +* |___________________| +* +* BOFFTEST - Backoff Test Register +* +* FIELDS (msb -> lsb) +* (rw) BOFFHALT - Halt Random Number Generator +* (rw) ATTEMPT - Initial Collision Attempt Count +* (rw) BOFFRNG - Backoff Random Number Generator +* (rw) RETRYCOUNT - Retry Count +* (rw) BOFFCOUNT - Backoff Current Count +* +* MACROS SUPPORTED +* EMAC_FMK y +* EMAC_FMKS . +* EMAC_FMKCHF . +* EMAC_ADDR y +* EMAC_REG y +* EMAC_RGET y +* EMAC_RSET y +* EMAC_FGET y +* EMAC_FSET y +* EMAC_FSETS . +* EMAC_RGETI . +* EMAC_RSETI . +* EMAC_FGETI . +* EMAC_FSETI . +* EMAC_FSETSI . +* +\******************************************************************************/ +#define _EMAC_BOFFTEST_ADDR (_EMAC_BASE_ADDR+0x01E0u) + +#define EMAC_BOFFTEST EMAC_REG(BOFFTEST) + +#define _EMAC_BOFFTEST_BOFFHALT_MASK 0x8000000u +#define _EMAC_BOFFTEST_BOFFHALT_SHIFT 31u +#define EMAC_BOFFTEST_BOFFHALT_DEFAULT 0x00000000u + +#define _EMAC_BOFFTEST_ATTEMPT_MASK 0x78000000u +#define _EMAC_BOFFTEST_ATTEMPT_SHIFT 27u +#define EMAC_BOFFTEST_ATTEMPT_DEFAULT 0x00000000u + +#define _EMAC_BOFFTEST_BOFFRNG_MASK 0x07FF0000u +#define _EMAC_BOFFTEST_BOFFRNG_SHIFT 16u +#define EMAC_BOFFTEST_BOFFRNG_DEFAULT 0x00000000u + +#define _EMAC_BOFFTEST_RETRYCOUNT_MASK 0x0000F000u +#define _EMAC_BOFFTEST_RETRYCOUNT_SHIFT 12u +#define EMAC_BOFFTEST_RETRYCOUNT_DEFAULT 0x00000000u + +#define _EMAC_BOFFTEST_BOFFCOUNT_MASK 0x000003FFu +#define _EMAC_BOFFTEST_BOFFCOUNT_SHIFT 0u +#define EMAC_BOFFTEST_BOFFCOUNT_DEFAULT 0x00000000u + + +/******************************************************************************\ +* _____________________ +* | | +* | TPACETEST | +* |___________________| +* +* TPACETEST - Transmit Pacing Test Register +* +* FIELDS (msb -> lsb) +* (rw) PACEVAL - Pace Register Current Value +* (rw) PACEINIT - Pace Register Initial Value +* +* MACROS SUPPORTED +* EMAC_FMK y +* EMAC_FMKS . +* EMAC_FMKCHF . +* EMAC_ADDR y +* EMAC_REG y +* EMAC_RGET y +* EMAC_RSET y +* EMAC_FGET y +* EMAC_FSET y +* EMAC_FSETS . +* EMAC_RGETI . +* EMAC_RSETI . +* EMAC_FGETI . +* EMAC_FSETI . +* EMAC_FSETSI . +* +\******************************************************************************/ +#define _EMAC_TPACETEST_ADDR (_EMAC_BASE_ADDR+0x01E4u) + +#define EMAC_TPACETEST EMAC_REG(TPACETEST) + +#define _EMAC_TPACETEST_PACEVAL_MASK 0x0000001Fu +#define _EMAC_TPACETEST_PACEVAL_SHIFT 0u +#define EMAC_TPACETEST_PACEVAL_DEFAULT 0x00000000u + +/******************************************************************************\ +* _____________________ +* | | +* | RXPAUSE | +* | TXPAUSE | +* |___________________| +* +* RXPAUSE - Receive Pause Timer Register +* TXPAUSE - Transmit Pause Timer Register +* +* FIELDS (msb -> lsb) +* (rw) PAUSETIMER - Pause Timer +* +* MACROS SUPPORTED +* EMAC_FMK y +* EMAC_FMKS . +* EMAC_FMKCHF . +* EMAC_ADDR y +* EMAC_REG y +* EMAC_RGET y +* EMAC_RSET y +* EMAC_FGET y +* EMAC_FSET y +* EMAC_FSETS . +* EMAC_RGETI . +* EMAC_RSETI . +* EMAC_FGETI . +* EMAC_FSETI . +* EMAC_FSETSI . +* +\******************************************************************************/ +#define _EMAC_RXPAUSE_ADDR (_EMAC_BASE_ADDR+0x01E8u) +#define _EMAC_TXPAUSE_ADDR (_EMAC_BASE_ADDR+0x01ECu) + +#define EMAC_RXPAUSE EMAC_REG(RXPAUSE) +#define EMAC_TXPAUSE EMAC_REG(TXPAUSE) + +#define _EMAC_RXPAUSE_PAUSETIMER_MASK 0x0000FFFFu +#define _EMAC_RXPAUSE_PAUSETIMER_SHIFT 0u +#define EMAC_RXPAUSE_PAUSETIMER_DEFAULT 0x00000000u + +#define _EMAC_TXPAUSE_PAUSETIMER_MASK 0x0000FFFFu +#define _EMAC_TXPAUSE_PAUSETIMER_SHIFT 0u +#define EMAC_TXPAUSE_PAUSETIMER_DEFAULT 0x00000000u + +/******************************************************************************\ +* _____________________ +* | | +* | TXHDP | +* | TXnHDP | +* |___________________| +* +* TXHDP - TX DMA Head Descriptor Pointer Register for RSETI/RGETI +* TX0HDP - TX Channel 0 DMA Head Descriptor Pointer Register +* TX1HDP - TX Channel 1 DMA Head Descriptor Pointer Register +* TX2HDP - TX Channel 2 DMA Head Descriptor Pointer Register +* TX3HDP - TX Channel 3 DMA Head Descriptor Pointer Register +* TX4HDP - TX Channel 4 DMA Head Descriptor Pointer Register +* TX5HDP - TX Channel 5 DMA Head Descriptor Pointer Register +* TX6HDP - TX Channel 6 DMA Head Descriptor Pointer Register +* TX7HDP - TX Channel 7 DMA Head Descriptor Pointer Register +* +* FIELDS (msb -> lsb) +* (rw) DESCPTR - Descriptor Pointer +* +* MACROS SUPPORTED +* EMAC_FMK y +* EMAC_FMKS . +* EMAC_FMKCHF . +* EMAC_ADDR y +* EMAC_REG y +* EMAC_RGET y +* EMAC_RSET y +* EMAC_FGET y +* EMAC_FSET y +* EMAC_FSETS . +* EMAC_RGETI y +* EMAC_RSETI y +* EMAC_FGETI y +* EMAC_FSETI y +* EMAC_FSETSI . +* +\******************************************************************************/ +#define _EMAC_TXHDP_BASEADDR (_EMAC_BASE_ADDR+0x0600u) +#define _EMAC_TX0HDP_ADDR (_EMAC_BASE_ADDR+0x0600u) +#define _EMAC_TX1HDP_ADDR (_EMAC_BASE_ADDR+0x0604u) +#define _EMAC_TX2HDP_ADDR (_EMAC_BASE_ADDR+0x0608u) +#define _EMAC_TX3HDP_ADDR (_EMAC_BASE_ADDR+0x060Cu) +#define _EMAC_TX4HDP_ADDR (_EMAC_BASE_ADDR+0x0610u) +#define _EMAC_TX5HDP_ADDR (_EMAC_BASE_ADDR+0x0614u) +#define _EMAC_TX6HDP_ADDR (_EMAC_BASE_ADDR+0x0618u) +#define _EMAC_TX7HDP_ADDR (_EMAC_BASE_ADDR+0x061Cu) + +#define EMAC_TX0HDP EMAC_REG(TX0HDP) +#define EMAC_TX1HDP EMAC_REG(TX1HDP) +#define EMAC_TX2HDP EMAC_REG(TX2HDP) +#define EMAC_TX3HDP EMAC_REG(TX3HDP) +#define EMAC_TX4HDP EMAC_REG(TX4HDP) +#define EMAC_TX5HDP EMAC_REG(TX5HDP) +#define EMAC_TX6HDP EMAC_REG(TX6HDP) +#define EMAC_TX7HDP EMAC_REG(TX7HDP) + +#define _EMAC_TXHDP_DESCPTR_MASK 0xFFFFFFFFu +#define _EMAC_TXHDP_DESCPTR_SHIFT 0u +#define EMAC_TXHDP_DESCPTR_DEFAULT 0x00000000u +#define _EMAC_TX0HDP_DESCPTR_MASK 0xFFFFFFFFu +#define _EMAC_TX0HDP_DESCPTR_SHIFT 0u +#define EMAC_TX0HDP_DESCPTR_DEFAULT 0x00000000u +#define _EMAC_TX1HDP_DESCPTR_MASK 0xFFFFFFFFu +#define _EMAC_TX1HDP_DESCPTR_SHIFT 0u +#define EMAC_TX1HDP_DESCPTR_DEFAULT 0x00000000u +#define _EMAC_TX2HDP_DESCPTR_MASK 0xFFFFFFFFu +#define _EMAC_TX2HDP_DESCPTR_SHIFT 0u +#define EMAC_TX2HDP_DESCPTR_DEFAULT 0x00000000u +#define _EMAC_TX3HDP_DESCPTR_MASK 0xFFFFFFFFu +#define _EMAC_TX3HDP_DESCPTR_SHIFT 0u +#define EMAC_TX3HDP_DESCPTR_DEFAULT 0x00000000u +#define _EMAC_TX4HDP_DESCPTR_MASK 0xFFFFFFFFu +#define _EMAC_TX4HDP_DESCPTR_SHIFT 0u +#define EMAC_TX4HDP_DESCPTR_DEFAULT 0x00000000u +#define _EMAC_TX5HDP_DESCPTR_MASK 0xFFFFFFFFu +#define _EMAC_TX5HDP_DESCPTR_SHIFT 0u +#define EMAC_TX5HDP_DESCPTR_DEFAULT 0x00000000u +#define _EMAC_TX6HDP_DESCPTR_MASK 0xFFFFFFFFu +#define _EMAC_TX6HDP_DESCPTR_SHIFT 0u +#define EMAC_TX6HDP_DESCPTR_DEFAULT 0x00000000u +#define _EMAC_TX7HDP_DESCPTR_MASK 0xFFFFFFFFu +#define _EMAC_TX7HDP_DESCPTR_SHIFT 0u +#define EMAC_TX7HDP_DESCPTR_DEFAULT 0x00000000u + + +/******************************************************************************\ +* _____________________ +* | | +* | RXHDP | +* | RXnHDP | +* |___________________| +* +* RXHDP - RX DMA Head Descriptor Pointer Register for RSETI/RGETI +* RX0HDP - RX Channel 0 DMA Head Descriptor Pointer Register +* RX1HDP - RX Channel 1 DMA Head Descriptor Pointer Register +* RX2HDP - RX Channel 2 DMA Head Descriptor Pointer Register +* RX3HDP - RX Channel 3 DMA Head Descriptor Pointer Register +* RX4HDP - RX Channel 4 DMA Head Descriptor Pointer Register +* RX5HDP - RX Channel 5 DMA Head Descriptor Pointer Register +* RX6HDP - RX Channel 6 DMA Head Descriptor Pointer Register +* RX7HDP - RX Channel 7 DMA Head Descriptor Pointer Register +* +* FIELDS (msb -> lsb) +* (rw) DESCPTR - Descriptor Pointer +* +* MACROS SUPPORTED +* EMAC_FMK y +* EMAC_FMKS . +* EMAC_FMKCHF . +* EMAC_ADDR y +* EMAC_REG y +* EMAC_RGET y +* EMAC_RSET y +* EMAC_FGET y +* EMAC_FSET y +* EMAC_FSETS . +* EMAC_RGETI y +* EMAC_RSETI y +* EMAC_FGETI y +* EMAC_FSETI y +* EMAC_FSETSI . +* +\******************************************************************************/ +#define _EMAC_RXHDP_BASEADDR (_EMAC_BASE_ADDR+0x0620u) +#define _EMAC_RX0HDP_ADDR (_EMAC_BASE_ADDR+0x0620u) +#define _EMAC_RX1HDP_ADDR (_EMAC_BASE_ADDR+0x0624u) +#define _EMAC_RX2HDP_ADDR (_EMAC_BASE_ADDR+0x0628u) +#define _EMAC_RX3HDP_ADDR (_EMAC_BASE_ADDR+0x062Cu) +#define _EMAC_RX4HDP_ADDR (_EMAC_BASE_ADDR+0x0630u) +#define _EMAC_RX5HDP_ADDR (_EMAC_BASE_ADDR+0x0634u) +#define _EMAC_RX6HDP_ADDR (_EMAC_BASE_ADDR+0x0638u) +#define _EMAC_RX7HDP_ADDR (_EMAC_BASE_ADDR+0x063Cu) + +#define EMAC_RX0HDP EMAC_REG(RX0HDP) +#define EMAC_RX1HDP EMAC_REG(RX1HDP) +#define EMAC_RX2HDP EMAC_REG(RX2HDP) +#define EMAC_RX3HDP EMAC_REG(RX3HDP) +#define EMAC_RX4HDP EMAC_REG(RX4HDP) +#define EMAC_RX5HDP EMAC_REG(RX5HDP) +#define EMAC_RX6HDP EMAC_REG(RX6HDP) +#define EMAC_RX7HDP EMAC_REG(RX7HDP) + +#define _EMAC_RXHDP_DESCPTR_MASK 0xFFFFFFFFu +#define _EMAC_RXHDP_DESCPTR_SHIFT 0u +#define EMAC_RXHDP_DESCPTR_DEFAULT 0x00000000u +#define _EMAC_RX0HDP_DESCPTR_MASK 0xFFFFFFFFu +#define _EMAC_RX0HDP_DESCPTR_SHIFT 0u +#define EMAC_RX0HDP_DESCPTR_DEFAULT 0x00000000u +#define _EMAC_RX1HDP_DESCPTR_MASK 0xFFFFFFFFu +#define _EMAC_RX1HDP_DESCPTR_SHIFT 0u +#define EMAC_RX1HDP_DESCPTR_DEFAULT 0x00000000u +#define _EMAC_RX2HDP_DESCPTR_MASK 0xFFFFFFFFu +#define _EMAC_RX2HDP_DESCPTR_SHIFT 0u +#define EMAC_RX2HDP_DESCPTR_DEFAULT 0x00000000u +#define _EMAC_RX3HDP_DESCPTR_MASK 0xFFFFFFFFu +#define _EMAC_RX3HDP_DESCPTR_SHIFT 0u +#define EMAC_Rx3HDP_DESCPTR_DEFAULT 0x00000000u +#define _EMAC_RX4HDP_DESCPTR_MASK 0xFFFFFFFFu +#define _EMAC_RX4HDP_DESCPTR_SHIFT 0u +#define EMAC_RX4HDP_DESCPTR_DEFAULT 0x00000000u +#define _EMAC_RX5HDP_DESCPTR_MASK 0xFFFFFFFFu +#define _EMAC_RX5HDP_DESCPTR_SHIFT 0u +#define EMAC_RX5HDP_DESCPTR_DEFAULT 0x00000000u +#define _EMAC_RX6HDP_DESCPTR_MASK 0xFFFFFFFFu +#define _EMAC_RX6HDP_DESCPTR_SHIFT 0u +#define EMAC_RX6HDP_DESCPTR_DEFAULT 0x00000000u +#define _EMAC_RX7HDP_DESCPTR_MASK 0xFFFFFFFFu +#define _EMAC_RX7HDP_DESCPTR_SHIFT 0u +#define EMAC_RX7HDP_DESCPTR_DEFAULT 0x00000000u +/***************************************************************************************************************************\ +* ___________________ +* | TXINTACK | +* | TXnINTACK | +* |___________________| +* +* TXINTACK - TX Interrupt Ack Register for RSETI/RGETI +* TX0INTACK - TX Channel 0 Interrupt Acknowledge Register +* TX1INTACK - TX Channel 1 Interrupt Acknowledge Register +* TX2INTACK - TX Channel 2 Interrupt Acknowledge Register +* TX3INTACK - TX Channel 3 Interrupt Acknowledge Register +* TX4INTACK - TX Channel 4 Interrupt Acknowledge Register +* TX5INTACK - TX Channel 5 Interrupt Acknowledge Register +* TX6INTACK - TX Channel 6 Interrupt Acknowledge Register +* TX7INTACK - TX Channel 7 Interrupt Acknowledge Register +* +* FIELDS (msb -> lsb) +* (rw) DESCPTR - Descriptor Pointer +* +* MACROS SUPPORTED +* EMAC_FMK y +* EMAC_FMKS . +* EMAC_FMKCHF . +* EMAC_ADDR y +* EMAC_REG y +* EMAC_RGET y +* EMAC_RSET y +* EMAC_FGET y +* EMAC_FSET y +* EMAC_FSETS . +* EMAC_RGETI y +* EMAC_RSETI y +* EMAC_FGETI y +* EMAC_FSETI y +* EMAC_FSETSI . +* +\******************************************************************************/ +#define _EMAC_TXINTACK_BASEADDR (_EMAC_BASE_ADDR+0x0640u) +#define _EMAC_TX0INTACK_ADDR (_EMAC_BASE_ADDR+0x0640u) +#define _EMAC_TX1INTACK_ADDR (_EMAC_BASE_ADDR+0x0644u) +#define _EMAC_TX2INTACK_ADDR (_EMAC_BASE_ADDR+0x0648u) +#define _EMAC_TX3INTACK_ADDR (_EMAC_BASE_ADDR+0x064Cu) +#define _EMAC_TX4INTACK_ADDR (_EMAC_BASE_ADDR+0x0650u) +#define _EMAC_TX5INTACK_ADDR (_EMAC_BASE_ADDR+0x0654u) +#define _EMAC_TX6INTACK_ADDR (_EMAC_BASE_ADDR+0x0658u) +#define _EMAC_TX7INTACK_ADDR (_EMAC_BASE_ADDR+0x065Cu) + +#define EMAC_TX0INTACK EMAC_REG(TX0INTACK) +#define EMAC_TX1INTACK EMAC_REG(TX1INTACK) +#define EMAC_TX2INTACK EMAC_REG(TX2INTACK) +#define EMAC_TX3INTACK EMAC_REG(TX3INTACK) +#define EMAC_TX4INTACK EMAC_REG(TX4INTACK) +#define EMAC_TX5INTACK EMAC_REG(TX5INTACK) +#define EMAC_TX6INTACK EMAC_REG(TX6INTACK) +#define EMAC_TX7INTACK EMAC_REG(TX7INTACK) + +#define _EMAC_TXINTACK_DESCPTR_MASK 0xFFFFFFFFu +#define _EMAC_TXINTACK_DESCPTR_SHIFT 0u +#define EMAC_TXINTACK_DESCPTR_DEFAULT 0x00000000u +#define _EMAC_TX0INTACK_DESCPTR_MASK 0xFFFFFFFFu +#define _EMAC_TX0INTACK_DESCPTR_SHIFT 0u +#define EMAC_TX0INTACK_DESCPTR_DEFAULT 0x00000000u +#define _EMAC_TX1INTACK_DESCPTR_MASK 0xFFFFFFFFu +#define _EMAC_TX1INTACK_DESCPTR_SHIFT 0u +#define EMAC_TX1INTACK_DESCPTR_DEFAULT 0x00000000u +#define _EMAC_TX2INTACK_DESCPTR_MASK 0xFFFFFFFFu +#define _EMAC_TX2INTACK_DESCPTR_SHIFT 0u +#define EMAC_TX2INTACK_DESCPTR_DEFAULT 0x00000000u +#define _EMAC_TX3INTACK_DESCPTR_MASK 0xFFFFFFFFu +#define _EMAC_TX3INTACK_DESCPTR_SHIFT 0u +#define EMAC_TX3INTACK_DESCPTR_DEFAULT 0x00000000u +#define _EMAC_TX4INTACK_DESCPTR_MASK 0xFFFFFFFFu +#define _EMAC_TX4INTACK_DESCPTR_SHIFT 0u +#define EMAC_TX4INTACK_DESCPTR_DEFAULT 0x00000000u +#define _EMAC_TX5INTACK_DESCPTR_MASK 0xFFFFFFFFu +#define _EMAC_TX5INTACK_DESCPTR_SHIFT 0u +#define EMAC_TX5INTACK_DESCPTR_DEFAULT 0x00000000u +#define _EMAC_TX6INTACK_DESCPTR_MASK 0xFFFFFFFFu +#define _EMAC_TX6INTACK_DESCPTR_SHIFT 0u +#define EMAC_TX6INTACK_DESCPTR_DEFAULT 0x00000000u +#define _EMAC_TX7INTACK_DESCPTR_MASK 0xFFFFFFFFu +#define _EMAC_TX7INTACK_DESCPTR_SHIFT 0u +#define EMAC_TX7INTACK_DESCPTR_DEFAULT 0x00000000u + +/******************************************************************************\ +* _____________________ +* | | +* | RXINTACK | +* | RXnINTACK | +* |___________________| +* +* RXINTACK - RX Channel 0 Interrupt Ack Register for RSETI/RGETI +* RX0INTACK - RX Channel 0 Interrupt Acknowledge Register +* RX1INTACK - RX Channel 1 Interrupt Acknowledge Register +* RX2INTACK - RX Channel 2 Interrupt Acknowledge Register +* RX3INTACK - RX Channel 3 Interrupt Acknowledge Register +* RX4INTACK - RX Channel 4 Interrupt Acknowledge Register +* RX5INTACK - RX Channel 5 Interrupt Acknowledge Register +* RX6INTACK - RX Channel 6 Interrupt Acknowledge Register +* RX7INTACK - RX Channel 7 Interrupt Acknowledge Register +* +* FIELDS (msb -> lsb) +* (rw) DESCPTR - Descriptor Pointer +* +* MACROS SUPPORTED +* EMAC_FMK y +* EMAC_FMKS . +* EMAC_FMKCHF . +* EMAC_ADDR y +* EMAC_REG y +* EMAC_RGET y +* EMAC_RSET y +* EMAC_FGET y +* EMAC_FSET y +* EMAC_FSETS . +* EMAC_RGETI y +* EMAC_RSETI y +* EMAC_FGETI y +* EMAC_FSETI y +* EMAC_FSETSI . +* +\******************************************************************************/ +#define _EMAC_RXINTACK_BASEADDR (_EMAC_BASE_ADDR+0x0660u) +#define _EMAC_RX0INTACK_ADDR (_EMAC_BASE_ADDR+0x0660u) +#define _EMAC_RX1INTACK_ADDR (_EMAC_BASE_ADDR+0x0664u) +#define _EMAC_RX2INTACK_ADDR (_EMAC_BASE_ADDR+0x0668u) +#define _EMAC_RX3INTACK_ADDR (_EMAC_BASE_ADDR+0x066Cu) +#define _EMAC_RX4INTACK_ADDR (_EMAC_BASE_ADDR+0x0670u) +#define _EMAC_RX5INTACK_ADDR (_EMAC_BASE_ADDR+0x0674u) +#define _EMAC_RX6INTACK_ADDR (_EMAC_BASE_ADDR+0x0678u) +#define _EMAC_RX7INTACK_ADDR (_EMAC_BASE_ADDR+0x067Cu) + +#define EMAC_RX0INTACK EMAC_REG(RX0INTACK) +#define EMAC_RX1INTACK EMAC_REG(RX1INTACK) +#define EMAC_RX2INTACK EMAC_REG(RX2INTACK) +#define EMAC_RX3INTACK EMAC_REG(RX3INTACK) +#define EMAC_RX4INTACK EMAC_REG(RX4INTACK) +#define EMAC_RX5INTACK EMAC_REG(RX5INTACK) +#define EMAC_RX6INTACK EMAC_REG(RX6INTACK) +#define EMAC_RX7INTACK EMAC_REG(RX7INTACK) + +#define _EMAC_RXINTACK_DESCPTR_MASK 0xFFFFFFFFu +#define _EMAC_RXINTACK_DESCPTR_SHIFT 0u +#define EMAC_RXINTACK_DESCPTR_DEFAULT 0x00000000u +#define _EMAC_RX0INTACK_DESCPTR_MASK 0xFFFFFFFFu +#define _EMAC_RX0INTACK_DESCPTR_SHIFT 0u +#define EMAC_RX0INTACK_DESCPTR_DEFAULT 0x00000000u +#define _EMAC_RX1INTACK_DESCPTR_MASK 0xFFFFFFFFu +#define _EMAC_RX1INTACK_DESCPTR_SHIFT 0u +#define EMAC_RX1INTACK_DESCPTR_DEFAULT 0x00000000u +#define _EMAC_RX2INTACK_DESCPTR_MASK 0xFFFFFFFFu +#define _EMAC_RX2INTACK_DESCPTR_SHIFT 0u +#define EMAC_RX2INTACK_DESCPTR_DEFAULT 0x00000000u +#define _EMAC_RX3INTACK_DESCPTR_MASK 0xFFFFFFFFu +#define _EMAC_RX3INTACK_DESCPTR_SHIFT 0u +#define EMAC_RX3INTACK_DESCPTR_DEFAULT 0x00000000u +#define _EMAC_RX4INTACK_DESCPTR_MASK 0xFFFFFFFFu +#define _EMAC_RX4INTACK_DESCPTR_SHIFT 0u +#define EMAC_RX4INTACK_DESCPTR_DEFAULT 0x00000000u +#define _EMAC_RX5INTACK_DESCPTR_MASK 0xFFFFFFFFu +#define _EMAC_RX5INTACK_DESCPTR_SHIFT 0u +#define EMAC_RX5INTACK_DESCPTR_DEFAULT 0x00000000u +#define _EMAC_RX6INTACK_DESCPTR_MASK 0xFFFFFFFFu +#define _EMAC_RX6INTACK_DESCPTR_SHIFT 0u +#define EMAC_RX6INTACK_DESCPTR_DEFAULT 0x00000000u +#define _EMAC_RX7INTACK_DESCPTR_MASK 0xFFFFFFFFu +#define _EMAC_RX7INTACK_DESCPTR_SHIFT 0u +#define EMAC_RX7INTACK_DESCPTR_DEFAULT 0x00000000u + + +/******************************************************************************\ +* _____________________ +* | | +* | RXGOODFRAMES | +* | RXBCASTFRAMES | +* | RXMCASTFRAMES | +* | RXPAUSEFRAMES | +* | RXCRCERRORS | +* | RXALIGNCODEERRORS | +* | RXOVERSIZED | +* | RXJABBER | +* | RXUNDERSIZED | +* | RXFRAGMENTS | +* | RXFILTERED | +* | RXQOSFILTERED | +* | RXOCTETS | +* | TXGOODFRAMES | +* | TXBCASTFRAMES | +* | TXMCASTFRAMES | +* | TXPAUSEFRAMES | +* | TXDEFERRED | +* | TXCOLLISION | +* | TXSINGLECOLL | +* | TXMULTICOLL | +* | TXEXCESSIVECOLL | +* | TXLATECOLL | +* | TXUNDERRUN | +* | TXCARRIERSLOSS | +* | TXOCTETS | +* | FRAME64 | +* | FRAME65T127 | +* | FRAME128T255 | +* | FRAME256T511 | +* | FRAME512T1023 | +* | FRAME1024TUP | +* | NETOCTETS | +* | RXSOFOVERRUNS | +* | RXMOFOVERRUNS | +* | RXDMAOVERRUNS | +* |___________________| +* +* RXGOODFRAMES - Number of Good Frames Received +* RXBCASTFRAMES - Number of Good Broadcast Frames Received +* RXMCASTFRAMES - Number of Good Multicast Frames Received +* RXPAUSEFRAMES - Number of PauseRX Frames Received +* RXCRCERRORS - Number of Frames Received with CRC Errors +* RXALIGNCODEERRORS - Number of Frames Received with Alignment/Code Errors +* RXOVERSIZED - Number of Oversized Frames Received +* RXJABBER - Number of Jabber Frames Received +* RXUNDERSIZED - Number of Undersized Frames Received +* RXFRAGMENTS - Number of RX Frame Fragments Received +* RXFILTERED - Number of RX Frames Filtered Based on Address +* RXQOSFILTERED - Number of RX Frames Filtered Based on QoS Filtering +* RXOCTETS - Total Number of Received Bytes in Good Frames +* TXGOODFRAMES - Number of Good Frames Sent +* TXBCASTFRAMES - Number of Good Broadcast Frames Sent +* TXMCASTFRAMES - Number of Good Multicast Frames Sent +* TXPAUSEFRAMES - Number of PauseTX Frames Sent +* TXDEFERRED - Number of Frames Where Transmission was Deferred +* TXCOLLISION - Total Number of Frames Sent That Experienced a Collision +* TXSINGLECOLL - Number of Frames Sent with Exactly One Collision +* TXMULTICOLL - Number of Frames Sent with Multiple Colisions +* TXEXCESSIVECOLL - Number of TX Frames Lost Due to Excessive Collisions +* TXLATECOLL - Number of TX Frames Lost Due to a Late Collision +* TXUNDERRUN - Number of TX Frames Lost with Transmit Underrun Error +* TXCARRIERSLOSS - Numebr of TX Frames Lost Due to Carrier Sense Loss +* TXOCTETS - Total Nu,ber of Transmitted Bytes in Good Frames +* FRAME64 - Total TX & RX Frames with Octet Size of 64 +* FRAME65T127 - Total TX & RX Frames with Octet Size of 65 to 127 +* FRAME128T255 - Total TX & RX Frames with Octet Size of 128 to 255 +* FRAME256T511 - Total TX & RX Frames with Octet Size of 256 to 511 +* FRAME512T1023 - Total TX & RX Frames with Octet Size of 512 to 1023 +* FRAME1024TUP - Total TX & RX Frames with Octet Size of 1024 or above +* NETOCTETS - Sum of all Octets Sent or Received on the Network +* RXSOFOVERRUNS - Total RX Start of Frame Overruns (FIFO or DMA) +* RXMOFOVERRUNS - Total RX Middle of Frame Overruns (FIFO or DMA) +* RXDMAOVERRUNS - Total RX DMA Overruns +* +* FIELDS (msb -> lsb) +* (rw) COUNT - 32 bit count value +* +* MACROS SUPPORTED +* EMAC_FMK y +* EMAC_FMKS . +* EMAC_FMKCHF . +* EMAC_ADDR y +* EMAC_REG y +* EMAC_RGET y +* EMAC_RSET y +* EMAC_FGET y +* EMAC_FSET y +* EMAC_FSETS . +* EMAC_RGETI . +* EMAC_RSETI . +* EMAC_FGETI . +* EMAC_FSETI . +* EMAC_FSETSI . +* +\******************************************************************************/ +#define _EMAC_RXGOODFRAMES_ADDR (_EMAC_BASE_ADDR+0x0200u) +#define _EMAC_RXBCASTFRAMES_ADDR (_EMAC_BASE_ADDR+0x0204u) +#define _EMAC_RXMCASTFRAMES_ADDR (_EMAC_BASE_ADDR+0x0208u) +#define _EMAC_RXPAUSEFRAMES_ADDR (_EMAC_BASE_ADDR+0x020Cu) +#define _EMAC_RXCRCERRORS_ADDR (_EMAC_BASE_ADDR+0x0210u) +#define _EMAC_RXALIGNCODEERRORS_ADDR (_EMAC_BASE_ADDR+0x0214u) +#define _EMAC_RXOVERSIZED_ADDR (_EMAC_BASE_ADDR+0x0218u) +#define _EMAC_RXJABBER_ADDR (_EMAC_BASE_ADDR+0x021Cu) +#define _EMAC_RXUNDERSIZED_ADDR (_EMAC_BASE_ADDR+0x0220u) +#define _EMAC_RXFRAGMENTS_ADDR (_EMAC_BASE_ADDR+0x0224u) +#define _EMAC_RXFILTERED_ADDR (_EMAC_BASE_ADDR+0x0228u) +#define _EMAC_RXQOSFILTERED_ADDR (_EMAC_BASE_ADDR+0x022Cu) +#define _EMAC_RXOCTETS_ADDR (_EMAC_BASE_ADDR+0x0230u) +#define _EMAC_TXGOODFRAMES_ADDR (_EMAC_BASE_ADDR+0x0234u) +#define _EMAC_TXBCASTFRAMES_ADDR (_EMAC_BASE_ADDR+0x0238u) +#define _EMAC_TXMCASTFRAMES_ADDR (_EMAC_BASE_ADDR+0x023Cu) +#define _EMAC_TXPAUSEFRAMES_ADDR (_EMAC_BASE_ADDR+0x0240u) +#define _EMAC_TXDEFERRED_ADDR (_EMAC_BASE_ADDR+0x0244u) +#define _EMAC_TXCOLLISION_ADDR (_EMAC_BASE_ADDR+0x0248u) +#define _EMAC_TXSINGLECOLL_ADDR (_EMAC_BASE_ADDR+0x024Cu) +#define _EMAC_TXMULTICOLL_ADDR (_EMAC_BASE_ADDR+0x0250u) +#define _EMAC_TXEXCESSIVECOLL_ADDR (_EMAC_BASE_ADDR+0x0254u) +#define _EMAC_TXLATECOLL_ADDR (_EMAC_BASE_ADDR+0x0258u) +#define _EMAC_TXUNDERRUN_ADDR (_EMAC_BASE_ADDR+0x025Cu) +#define _EMAC_TXCARRIERSLOSS_ADDR (_EMAC_BASE_ADDR+0x0260u) +#define _EMAC_TXOCTETS_ADDR (_EMAC_BASE_ADDR+0x0264u) +#define _EMAC_FRAME64_ADDR (_EMAC_BASE_ADDR+0x0268u) +#define _EMAC_FRAME65T127_ADDR (_EMAC_BASE_ADDR+0x026Cu) +#define _EMAC_FRAME128T255_ADDR (_EMAC_BASE_ADDR+0x0270u) +#define _EMAC_FRAME256T511_ADDR (_EMAC_BASE_ADDR+0x0274u) +#define _EMAC_FRAME512T1023_ADDR (_EMAC_BASE_ADDR+0x0278u) +#define _EMAC_FRAME1024TUP_ADDR (_EMAC_BASE_ADDR+0x027Cu) +#define _EMAC_NETOCTETS_ADDR (_EMAC_BASE_ADDR+0x0280u) +#define _EMAC_RXSOFOVERRUNS_ADDR (_EMAC_BASE_ADDR+0x0284u) +#define _EMAC_RXMOFOVERRUNS_ADDR (_EMAC_BASE_ADDR+0x0288u) +#define _EMAC_RXDMAOVERRUNS_ADDR (_EMAC_BASE_ADDR+0x028Cu) + +#define EMAC_RXGOODFRAMES EMAC_REG(RXGOODFRAMES) +#define EMAC_RXBCASTFRAMES EMAC_REG(RXBCASTFRAMES) +#define EMAC_RXMCASTFRAMES EMAC_REG(RXMCASTFRAMES) +#define EMAC_RXPAUSEFRAMES EMAC_REG(RXPAUSEFRAMES) +#define EMAC_RXCRCERRORS EMAC_REG(RXCRCERRORS) +#define EMAC_RXALIGNCODEERRORS EMAC_REG(RXALIGNCODEERRORS) +#define EMAC_RXOVERSIZED EMAC_REG(RXOVERSIZED) +#define EMAC_RXJABBER EMAC_REG(RXJABBER) +#define EMAC_RXUNDERSIZED EMAC_REG(RXUNDERSIZED) +#define EMAC_RXFRAGMENTS EMAC_REG(RXFRAGMENTS) +#define EMAC_RXFILTERED EMAC_REG(RXFILTERED) +#define EMAC_RXQOSFILTERED EMAC_REG(RXQOSFILTERED) +#define EMAC_RXOCTETS EMAC_REG(RXOCTETS) +#define EMAC_TXGOODFRAMES EMAC_REG(TXGOODFRAMES) +#define EMAC_TXBCASTFRAMES EMAC_REG(TXBCASTFRAMES) +#define EMAC_TXMCASTFRAMES EMAC_REG(TXMCASTFRAMES) +#define EMAC_TXPAUSEFRAMES EMAC_REG(TXPAUSEFRAMES) +#define EMAC_TXDEFERRED EMAC_REG(TXDEFERRED) +#define EMAC_TXCOLLISION EMAC_REG(TXCOLLISION) +#define EMAC_TXSINGLECOLL EMAC_REG(TXSINGLECOLL) +#define EMAC_TXMULTICOLL EMAC_REG(TXMULTICOLL) +#define EMAC_TXEXCESSIVECOLL EMAC_REG(TXEXCESSIVECOLL) +#define EMAC_TXLATECOLL EMAC_REG(TXLATECOLL) +#define EMAC_TXUNDERRUN EMAC_REG(TXUNDERRUN) +#define EMAC_TXCARRIERSLOSS EMAC_REG(TXCARRIERSLOSS) +#define EMAC_TXOCTETS EMAC_REG(TXOCTETS) +#define EMAC_FRAME64 EMAC_REG(FRAME64) +#define EMAC_FRAME65T127 EMAC_REG(FRAME65T127) +#define EMAC_FRAME128T255 EMAC_REG(FRAME128T255) +#define EMAC_FRAME256T511 EMAC_REG(FRAME256T511) +#define EMAC_FRAME512T1023 EMAC_REG(FRAME512T1023) +#define EMAC_FRAME1024TUP EMAC_REG(FRAME1024TUP) +#define EMAC_NETOCTETS EMAC_REG(NETOCTETS) +#define EMAC_RXSOFOVERRUNS EMAC_REG(RXSOFOVERRUNS) +#define EMAC_RXMOFOVERRUNS EMAC_REG(RXMOFOVERRUNS) +#define EMAC_RXDMAOVERRUNS EMAC_REG(RXDMAOVERRUNS) + +#define _EMAC_RXGOODFRAMES_COUNT_MASK 0xFFFFFFFFu +#define _EMAC_RXBCASTFRAMES_COUNT_MASK 0xFFFFFFFFu +#define _EMAC_RXMCASTFRAMES_COUNT_MASK 0xFFFFFFFFu +#define _EMAC_RXPAUSEFRAMES_COUNT_MASK 0xFFFFFFFFu +#define _EMAC_RXCRCERRORS_COUNT_MASK 0xFFFFFFFFu +#define _EMAC_RXALIGNCODEERRORS_COUNT_MASK 0xFFFFFFFFu +#define _EMAC_RXOVERSIZED_COUNT_MASK 0xFFFFFFFFu +#define _EMAC_RXJABBER_COUNT_MASK 0xFFFFFFFFu +#define _EMAC_RXUNDERSIZED_COUNT_MASK 0xFFFFFFFFu +#define _EMAC_RXFRAGMENTS_COUNT_MASK 0xFFFFFFFFu +#define _EMAC_RXFILTERED_COUNT_MASK 0xFFFFFFFFu +#define _EMAC_RXQOSFILTERED_COUNT_MASK 0xFFFFFFFFu +#define _EMAC_RXOCTETS_COUNT_MASK 0xFFFFFFFFu +#define _EMAC_TXGOODFRAMES_COUNT_MASK 0xFFFFFFFFu +#define _EMAC_TXBCASTFRAMES_COUNT_MASK 0xFFFFFFFFu +#define _EMAC_TXMCASTFRAMES_COUNT_MASK 0xFFFFFFFFu +#define _EMAC_TXPAUSEFRAMES_COUNT_MASK 0xFFFFFFFFu +#define _EMAC_TXDEFERRED_COUNT_MASK 0xFFFFFFFFu +#define _EMAC_TXCOLLISION_COUNT_MASK 0xFFFFFFFFu +#define _EMAC_TXSINGLECOLL_COUNT_MASK 0xFFFFFFFFu +#define _EMAC_TXMULTICOLL_COUNT_MASK 0xFFFFFFFFu +#define _EMAC_TXEXCESSIVECOLL_COUNT_MASK 0xFFFFFFFFu +#define _EMAC_TXLATECOLL_COUNT_MASK 0xFFFFFFFFu +#define _EMAC_TXUNDERRUN_COUNT_MASK 0xFFFFFFFFu +#define _EMAC_TXCARRIERSLOSS_COUNT_MASK 0xFFFFFFFFu +#define _EMAC_TXOCTETS_COUNT_MASK 0xFFFFFFFFu +#define _EMAC_FRAME64_COUNT_MASK 0xFFFFFFFFu +#define _EMAC_FRAME65T127_COUNT_MASK 0xFFFFFFFFu +#define _EMAC_FRAME128T255_COUNT_MASK 0xFFFFFFFFu +#define _EMAC_FRAME256T511_COUNT_MASK 0xFFFFFFFFu +#define _EMAC_FRAME512T1023_COUNT_MASK 0xFFFFFFFFu +#define _EMAC_FRAME1024TUP_COUNT_MASK 0xFFFFFFFFu +#define _EMAC_NETOCTETS_COUNT_MASK 0xFFFFFFFFu +#define _EMAC_RXSOFOVERRUNS_COUNT_MASK 0xFFFFFFFFu +#define _EMAC_RXMOFOVERRUNS_COUNT_MASK 0xFFFFFFFFu +#define _EMAC_RXDMAOVERRUNS_COUNT_MASK 0xFFFFFFFFu + +#define _EMAC_RXGOODFRAMES_COUNT_SHIFT 0u +#define _EMAC_RXBCASTFRAMES_COUNT_SHIFT 0u +#define _EMAC_RXMCASTFRAMES_COUNT_SHIFT 0u +#define _EMAC_RXPAUSEFRAMES_COUNT_SHIFT 0u +#define _EMAC_RXCRCERRORS_COUNT_SHIFT 0u +#define _EMAC_RXALIGNCODEERRORS_COUNT_SHIFT 0u +#define _EMAC_RXOVERSIZED_COUNT_SHIFT 0u +#define _EMAC_RXJABBER_COUNT_SHIFT 0u +#define _EMAC_RXUNDERSIZED_COUNT_SHIFT 0u +#define _EMAC_RXFRAGMENTS_COUNT_SHIFT 0u +#define _EMAC_RXFILTERED_COUNT_SHIFT 0u +#define _EMAC_RXQOSFILTERED_COUNT_SHIFT 0u +#define _EMAC_RXOCTETS_COUNT_SHIFT 0u +#define _EMAC_TXGOODFRAMES_COUNT_SHIFT 0u +#define _EMAC_TXBCASTFRAMES_COUNT_SHIFT 0u +#define _EMAC_TXMCASTFRAMES_COUNT_SHIFT 0u +#define _EMAC_TXPAUSEFRAMES_COUNT_SHIFT 0u +#define _EMAC_TXDEFERRED_COUNT_SHIFT 0u +#define _EMAC_TXCOLLISION_COUNT_SHIFT 0u +#define _EMAC_TXSINGLECOLL_COUNT_SHIFT 0u +#define _EMAC_TXMULTICOLL_COUNT_SHIFT 0u +#define _EMAC_TXEXCESSIVECOLL_COUNT_SHIFT 0u +#define _EMAC_TXLATECOLL_COUNT_SHIFT 0u +#define _EMAC_TXUNDERRUN_COUNT_SHIFT 0u +#define _EMAC_TXCARRIERSLOSS_COUNT_SHIFT 0u +#define _EMAC_TXOCTETS_COUNT_SHIFT 0u +#define _EMAC_FRAME64_COUNT_SHIFT 0u +#define _EMAC_FRAME65T127_COUNT_SHIFT 0u +#define _EMAC_FRAME128T255_COUNT_SHIFT 0u +#define _EMAC_FRAME256T511_COUNT_SHIFT 0u +#define _EMAC_FRAME512T1023_COUNT_SHIFT 0u +#define _EMAC_FRAME1024TUP_COUNT_SHIFT 0u +#define _EMAC_NETOCTETS_COUNT_SHIFT 0u +#define _EMAC_RXSOFOVERRUNS_COUNT_SHIFT 0u +#define _EMAC_RXMOFOVERRUNS_COUNT_SHIFT 0u +#define _EMAC_RXDMAOVERRUNS_COUNT_SHIFT 0u + +#define EMAC_RXGOODFRAMES_COUNT_DEFAULT 0x00000000u +#define EMAC_RXBCASTFRAMES_COUNT_DEFAULT 0x00000000u +#define EMAC_RXMCASTFRAMES_COUNT_DEFAULT 0x00000000u +#define EMAC_RXPAUSEFRAMES_COUNT_DEFAULT 0x00000000u +#define EMAC_RXCRCERRORS_COUNT_DEFAULT 0x00000000u +#define EMAC_RXALIGNCODEERRORS_COUNT_DEFAULT 0x00000000u +#define EMAC_RXOVERSIZED_COUNT_DEFAULT 0x00000000u +#define EMAC_RXJABBER_COUNT_DEFAULT 0x00000000u +#define EMAC_RXUNDERSIZED_COUNT_DEFAULT 0X00000000u +#define EMAC_RXFRAGMENTS_COUNT_DEFAULT 0x00000000u +#define EMAC_RXFILTERED_COUNT_DEFAULT 0x00000000u +#define EMAC_RXQOSFILTERED_COUNT_DEFAULT 0x00000000u +#define EMAC_RXOCTETS_COUNT_DEFAULT 0x00000000u +#define EMAC_TXGOODFRAMES_COUNT_DEFAULT 0x00000000u +#define EMAC_TXBCASTFRAMES_COUNT_DEFAULT 0x00000000u +#define EMAC_TXMCASTFRAMES_COUNT_DEFAULT 0x00000000u +#define EMAC_TXPAUSEFRAMES_COUNT_DEFAULT 0x00000000u +#define EMAC_TXDEFERRED_COUNT_DEFAULT 0x00000000u +#define EMAC_TXCOLLISION_COUNT_DEFAULT 0x00000000u +#define EMAC_TXSINGLECOLL_COUNT_DEFAULT 0x00000000u +#define EMAC_TXMULTICOLL_COUNT_DEFAULT 0x00000000u +#define EMAC_TXEXCESSIVECOLL_COUNT_DEFAULT 0x00000000u +#define EMAC_TXLATECOLL_COUNT_DEFAULT 0x00000000u +#define EMAC_TXUNDERRUN_COUNT_DEFAULT 0x00000000u +#define EMAC_TXCARRIERSLOSS_COUNT_DEFAULT 0x00000000u +#define EMAC_TXOCTETS_COUNT_DEFAULT 0x00000000u +#define EMAC_FRAME64_COUNT_DEFAULT 0x00000000u +#define EMAC_FRAME65T127_COUNT_DEFAULT 0x00000000u +#define EMAC_FRAME128T255_COUNT_DEFAULT 0x00000000u +#define EMAC_FRAME256T511_COUNT_DEFAULT 0x00000000u +#define EMAC_FRAME512T1023_COUNT_DEFAULT 0x00000000u +#define EMAC_FRAME1024TUP_COUNT_DEFAULT 0x00000000u +#define EMAC_NETOCTETS_COUNT_DEFAULT 0x00000000u +#define EMAC_RXSOFOVERRUNS_COUNT_DEFAULT 0x00000000u +#define EMAC_RXMOFOVERRUNS_COUNT_DEFAULT 0x00000000u +#define EMAC_RXDMAOVERRUNS_COUNT_DEFAULT 0x00000000u +/******************************************************************************\ +* _____________________ +* | | +* | EWTRCTRL | +* |___________________| +* +* EWTRCTRL - TR Control +* +* FIELDS (msb -> lsb) +* +* MACROS SUPPORTED +* EMAC_FMK . +* EMAC_FMKS . +* EMAC_FMKCHF . +* EMAC_ADDR y +* EMAC_REG y +* EMAC_RGET y +* EMAC_RSET y +* EMAC_FGET . +* EMAC_FSET . +* EMAC_FSETS . +* EMAC_RGETI . +* EMAC_RSETI . +* EMAC_FGETI . +* EMAC_FSETI . +* EMAC_FSETSI . +* +\******************************************************************************/ +#define _EMAC_EWTRCTRL_ADDR (_EMAC_BASE_ADDR+0x3000u) + +#define EMAC_EWTRCTRL EMAC_REG(EWTRCTRL) + +/******************************************************************************\ +* _____________________ +* | | +* | EWCTL | +* |___________________| +* +* EWCTL - Interrupt control register +* +* FIELDS (msb -> lsb) +* (rw) EMACRST - EMAC Reset +* (rw) MDIORST - MDIO Reset +* (rw) INTEN - EMAC/MDIO Global Interrupt Enable +* +* MACROS SUPPORTED +* EMAC_FMK y +* EMAC_FMKS y +* EMAC_FMKCHF . +* EMAC_ADDR y +* EMAC_REG y +* EMAC_RGET y +* EMAC_RSET y +* EMAC_FGET y +* EMAC_FSET y +* EMAC_FSETS y +* EMAC_RGETI . +* EMAC_RSETI . +* EMAC_FGETI . +* EMAC_FSETI . +* EMAC_FSETSI . +* +\******************************************************************************/ +#define _EMAC_EWCTL_ADDR (_EMAC_BASE_ADDR+0x3004u) + +#define EMAC_EWCTL EMAC_REG(EWCTL) + +#define _EMAC_EWCTL_EMACRST_MASK 0x4u +#define _EMAC_EWCTL_EMACRST_SHIFT 2u +#define EMAC_EWCTL_EMACRST_DEFAULT 0x00000000u +#define EMAC_EWCTL_EMACRST_YES 1u +#define EMAC_EWCTL_EMACRST_NO 0u + +#define _EMAC_EWCTL_MDIORST_MASK 0x2u +#define _EMAC_EWCTL_MDIORST_SHIFT 1u +#define EMAC_EWCTL_MDIORST_DEFAULT 0x00000000u +#define EMAC_EWCTL_MDIORST_YES 1u +#define EMAC_EWCTL_MDIORST_NO 0u + +#define _EMAC_EWCTL_INTEN_MASK 0x1u +#define _EMAC_EWCTL_INTEN_SHIFT 0u +#define EMAC_EWCTL_INTEN_DEFAULT 0x00000000u +#define EMAC_EWCTL_INTEN_ENABLE 1u +#define EMAC_EWCTL_INTEN_DISABLE 0u + +/******************************************************************************\ +* _____________________ +* | | +* | EWINTTCNT | +* |___________________| +* +* EWINTTCNT - Interrupt Timer Count +* +* FIELDS (msb -> lsb) +* +* MACROS SUPPORTED +* EMAC_FMK . +* EMAC_FMKS . +* EMAC_FMKCHF . +* EMAC_ADDR y +* EMAC_REG y +* EMAC_RGET y +* EMAC_RSET y +* EMAC_FGET . +* EMAC_FSET . +* EMAC_FSETS . +* EMAC_RGETI . +* EMAC_RSETI . +* EMAC_FGETI . +* EMAC_FSETI . +* EMAC_FSETSI . +* +\******************************************************************************/ +#define _EMAC_EWINTTCNT_ADDR (_EMAC_BASE_ADDR+0x3008u) + +#define EMAC_EWINTTCNT EMAC_REG(EWINTTCNT) + + + +#endif /* EMAC_SUPPORT */ + +#endif /* _CSL_EMACHAL_H_ */ +/******************************************************************************\ +* End of csl_emachal.h +\******************************************************************************/ + + + + + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_emif.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_emif.h new file mode 100644 index 0000000..db8ec4e --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_emif.h @@ -0,0 +1,235 @@ +/******************************************************************************\ +* Copyright (C) 1999-2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_emif.h +* DATE CREATED.. 06/11/1999 +* LAST MODIFIED. 01/31/2002 -SDCTL reg. setting after SDEXT reg. setting +\******************************************************************************/ +#ifndef _CSL_EMIF_H_ +#define _CSL_EMIF_H_ + +#include +#include +#include + + +#if (EMIF_SUPPORT) +/******************************************************************************\ +* scope and inline control macros +\******************************************************************************/ +#ifdef __cplusplus +#define CSLAPI extern "C" far +#else +#define CSLAPI extern far +#endif + +#undef USEDEFS +#undef IDECL +#undef IDEF + +#ifdef _EMIF_MOD_ + #define IDECL CSLAPI + #define USEDEFS + #define IDEF +#else + #ifdef _INLINE + #define IDECL static inline + #define USEDEFS + #define IDEF static inline + #else + #define IDECL CSLAPI + #endif +#endif + + +/******************************************************************************\ +* global macro declarations +\******************************************************************************/ + + +/******************************************************************************\ +* global typedef declarations +\******************************************************************************/ + +/* device configuration structure */ +typedef struct { + Uint32 gblctl; + Uint32 cectl0; + Uint32 cectl1; + Uint32 cectl2; + Uint32 cectl3; + Uint32 sdctl; + Uint32 sdtim; + #if (C11_SUPPORT) + Uint32 sdext; + #endif +} EMIF_Config; + + +/******************************************************************************\ +* global variable declarations +\******************************************************************************/ + + +/******************************************************************************\ +* global function declarations +\******************************************************************************/ + + +/******************************************************************************\ +* inline function declarations +\******************************************************************************/ +IDECL void EMIF_config(EMIF_Config *config); + +#if (C11_SUPPORT) + IDECL void EMIF_configArgs(Uint32 gblctl, Uint32 cectl0, Uint32 cectl1, + Uint32 cectl2, Uint32 cectl3, Uint32 sdctl, Uint32 sdtim, Uint32 sdext); +#else + IDECL void EMIF_configArgs(Uint32 gblctl, Uint32 cectl0, Uint32 cectl1, + Uint32 cectl2, Uint32 cectl3, Uint32 sdctl, Uint32 sdtim); +#endif + +IDECL void EMIF_getConfig(EMIF_Config *config); + + +/******************************************************************************\ +* inline function definitions +\******************************************************************************/ +#ifdef USEDEFS +/*----------------------------------------------------------------------------*/ +IDEF void EMIF_config(EMIF_Config *config) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)_EMIF_BASE_GLOBAL; + register int x0,x1,x2,x3,x4,x5,x6; + #if (C11_SUPPORT) + register int x7; + #endif + + gie = IRQ_globalDisable(); + + /* the compiler generates more efficient code if the loads */ + /* and stores are grouped together raher than intermixed */ + x0 = config->gblctl; + x1 = config->cectl0; + x2 = config->cectl1; + x3 = config->cectl2; + x4 = config->cectl3; + x5 = config->sdctl; + x6 = config->sdtim; + #if (C11_SUPPORT) + x7 = config->sdext; + #endif + + base[_EMIF_GBLCTL_OFFSET] = x0; + base[_EMIF_CECTL0_OFFSET] = x1; + base[_EMIF_CECTL1_OFFSET] = x2; + base[_EMIF_CECTL2_OFFSET] = x3; + base[_EMIF_CECTL3_OFFSET] = x4; + base[_EMIF_SDTIM_OFFSET] = x6; + #if (C11_SUPPORT) + base[_EMIF_SDEXT_OFFSET] = x7; + #endif + base[_EMIF_SDCTL_OFFSET] = x5; + + IRQ_globalRestore(gie); +} + +/*----------------------------------------------------------------------------*/ +#if (C11_SUPPORT) + +IDEF void EMIF_configArgs(Uint32 gblctl, Uint32 cectl0, Uint32 cectl1, + Uint32 cectl2, Uint32 cectl3, Uint32 sdctl, Uint32 sdtim, Uint32 sdext) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)_EMIF_BASE_GLOBAL; + + gie = IRQ_globalDisable(); + + base[_EMIF_GBLCTL_OFFSET] = gblctl; + base[_EMIF_CECTL0_OFFSET] = cectl0; + base[_EMIF_CECTL1_OFFSET] = cectl1; + base[_EMIF_CECTL2_OFFSET] = cectl2; + base[_EMIF_CECTL3_OFFSET] = cectl3; + base[_EMIF_SDTIM_OFFSET] = sdtim; + base[_EMIF_SDEXT_OFFSET] = sdext; + base[_EMIF_SDCTL_OFFSET] = sdctl; + + IRQ_globalRestore(gie); +} + +#else + +IDEF void EMIF_configArgs(Uint32 gblctl, Uint32 cectl0, Uint32 cectl1, + Uint32 cectl2, Uint32 cectl3, Uint32 sdctl, Uint32 sdtim) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)_EMIF_BASE_GLOBAL; + + gie = IRQ_globalDisable(); + + base[_EMIF_GBLCTL_OFFSET] = gblctl; + base[_EMIF_CECTL0_OFFSET] = cectl0; + base[_EMIF_CECTL1_OFFSET] = cectl1; + base[_EMIF_CECTL2_OFFSET] = cectl2; + base[_EMIF_CECTL3_OFFSET] = cectl3; + base[_EMIF_SDTIM_OFFSET] = sdtim; + base[_EMIF_SDCTL_OFFSET] = sdctl; + + IRQ_globalRestore(gie); +} + +#endif /* (C11_SUPPORT) */ + +/*----------------------------------------------------------------------------*/ +IDEF void EMIF_getConfig(EMIF_Config *config) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)_EMIF_BASE_GLOBAL; + volatile EMIF_Config* cfg = (volatile EMIF_Config*)config; + register int x0,x1,x2,x3,x4,x5,x6; + #if (C11_SUPPORT) + register int x7; + #endif + + gie = IRQ_globalDisable(); + + /* the compiler generates more efficient code if the loads */ + /* and stores are grouped together raher than intermixed */ + + x0 = base[_EMIF_GBLCTL_OFFSET]; + x1 = base[_EMIF_CECTL0_OFFSET]; + x2 = base[_EMIF_CECTL1_OFFSET]; + x3 = base[_EMIF_CECTL2_OFFSET]; + x4 = base[_EMIF_CECTL3_OFFSET]; + x5 = base[_EMIF_SDCTL_OFFSET]; + x6 = base[_EMIF_SDTIM_OFFSET]; + #if (C11_SUPPORT) + x7 = base[_EMIF_SDEXT_OFFSET]; + #endif + + cfg->gblctl = x0; + cfg->cectl0 = x1; + cfg->cectl1 = x2; + cfg->cectl2 = x3; + cfg->cectl3 = x4; + cfg->sdctl = x5; + cfg->sdtim = x6; + #if (C11_SUPPORT) + cfg->sdext = x7; + #endif + + IRQ_globalRestore(gie); +} + +/*----------------------------------------------------------------------------*/ +#endif /* USEDEFS */ + + +#endif /* EMIF_SUPPORT */ +#endif /* _CSL_EMIF_H_ */ +/******************************************************************************\ +* End of csl_emif.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_emifa.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_emifa.h new file mode 100644 index 0000000..0155f52 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_emifa.h @@ -0,0 +1,222 @@ +/******************************************************************************\ +* Copyright (C) 2001 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_emifa.h +* DATE CREATED.. 03/27/2001 +* LAST MODIFIED. 01/31/2002 SDCTL reg. setting after SDEXT reg.setting +\******************************************************************************/ +#ifndef _CSL_EMIFA_H_ +#define _CSL_EMIFA_H_ + +#include +#include +#include + + +#if (EMIFA_SUPPORT) +/******************************************************************************\ +* scope and inline control macros +\******************************************************************************/ +#ifdef __cplusplus +#define CSLAPI extern "C" far +#else +#define CSLAPI extern far +#endif + +#undef USEDEFS +#undef IDECL +#undef IDEF + +#ifdef _EMIFA_MOD_ + #define IDECL CSLAPI + #define USEDEFS + #define IDEF +#else + #ifdef _INLINE + #define IDECL static inline + #define USEDEFS + #define IDEF static inline + #else + #define IDECL CSLAPI + #endif +#endif + + +/******************************************************************************\ +* global macro declarations +\******************************************************************************/ + + +/******************************************************************************\ +* global typedef declarations +\******************************************************************************/ + +/* device configuration structure */ +typedef struct { + Uint32 gblctl; + Uint32 cectl0; + Uint32 cectl1; + Uint32 cectl2; + Uint32 cectl3; + Uint32 sdctl; + Uint32 sdtim; + Uint32 sdext; + Uint32 cesec0; + Uint32 cesec1; + Uint32 cesec2; + Uint32 cesec3; +} EMIFA_Config; + + +/******************************************************************************\ +* global variable declarations +\******************************************************************************/ + + +/******************************************************************************\ +* global function declarations +\******************************************************************************/ + + +/******************************************************************************\ +* inline function declarations +\******************************************************************************/ +#if C64_SUPPORT +IDECL void EMIFA_config(EMIFA_Config *config); +IDECL void EMIFA_configArgs(Uint32 gblctl, Uint32 cectl0, Uint32 cectl1, + Uint32 cectl2, Uint32 cectl3, Uint32 sdctl, Uint32 sdtim, Uint32 sdext, Uint32 cesec0, + Uint32 cesec1, Uint32 cesec2, Uint32 cesec3); +IDECL void EMIFA_getConfig(EMIFA_Config *config); +#endif + +/******************************************************************************\ +* inline function definitions +\******************************************************************************/ +#ifdef USEDEFS +/*----------------------------------------------------------------------------*/ +#if (C64_SUPPORT) +IDEF void EMIFA_config(EMIFA_Config *config) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)_EMIFA_BASE_GLOBAL; + register int x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11; + + gie = IRQ_globalDisable(); + + /* the compiler generates more efficient code if the loads */ + /* and stores are grouped together raher than intermixed */ + x0 = config->gblctl; + x1 = config->cectl0; + x2 = config->cectl1; + x3 = config->cectl2; + x4 = config->cectl3; + x5 = config->sdctl; + x6 = config->sdtim; + x7 = config->sdext; + x8 = config->cesec0; + x9 = config->cesec1; + x10 = config->cesec2; + x11 = config->cesec3; + + base[_EMIFA_GBLCTL_OFFSET] = x0; + base[_EMIFA_CECTL0_OFFSET] = x1; + base[_EMIFA_CECTL1_OFFSET] = x2; + base[_EMIFA_CECTL2_OFFSET] = x3; + base[_EMIFA_CECTL3_OFFSET] = x4; + + base[_EMIFA_SDTIM_OFFSET] = x6; + base[_EMIFA_SDEXT_OFFSET] = x7; + base[_EMIFA_CESEC0_OFFSET] = x8; + base[_EMIFA_CESEC1_OFFSET] = x9; + base[_EMIFA_CESEC2_OFFSET] = x10; + base[_EMIFA_CESEC3_OFFSET] = x11; + + base[_EMIFA_SDCTL_OFFSET] = x5; + + IRQ_globalRestore(gie); +} +#endif /* C64_SUPPORT */ +/*----------------------------------------------------------------------------*/ +#if C64_SUPPORT +IDEF void EMIFA_configArgs(Uint32 gblctl, Uint32 cectl0, Uint32 cectl1, + Uint32 cectl2, Uint32 cectl3, Uint32 sdctl, Uint32 sdtim, Uint32 sdext, + Uint32 cesec0, Uint32 cesec1, Uint32 cesec2, Uint32 cesec3) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)_EMIFA_BASE_GLOBAL; + + gie = IRQ_globalDisable(); + + base[_EMIFA_GBLCTL_OFFSET] = gblctl; + base[_EMIFA_CECTL0_OFFSET] = cectl0; + base[_EMIFA_CECTL1_OFFSET] = cectl1; + base[_EMIFA_CECTL2_OFFSET] = cectl2; + base[_EMIFA_CECTL3_OFFSET] = cectl3; + base[_EMIFA_SDTIM_OFFSET] = sdtim; + base[_EMIFA_SDEXT_OFFSET] = sdext; + base[_EMIFA_CESEC0_OFFSET] = cesec0; + base[_EMIFA_CESEC1_OFFSET] = cesec1; + base[_EMIFA_CESEC2_OFFSET] = cesec2; + base[_EMIFA_CESEC3_OFFSET] = cesec3; + base[_EMIFA_SDCTL_OFFSET] = sdctl; + + IRQ_globalRestore(gie); +} +#endif +/*----------------------------------------------------------------------------*/ +#if (C64_SUPPORT) +IDEF void EMIFA_getConfig(EMIFA_Config *config) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)_EMIFA_BASE_GLOBAL; + volatile EMIFA_Config* cfg = (volatile EMIFA_Config*)config; + register int x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11; + + gie = IRQ_globalDisable(); + + /* the compiler generates more efficient code if the loads */ + /* and stores are grouped together raher than intermixed */ + + x0 = base[_EMIFA_GBLCTL_OFFSET]; + x1 = base[_EMIFA_CECTL0_OFFSET]; + x2 = base[_EMIFA_CECTL1_OFFSET]; + x3 = base[_EMIFA_CECTL2_OFFSET]; + x4 = base[_EMIFA_CECTL3_OFFSET]; + + x6 = base[_EMIFA_SDTIM_OFFSET]; + x7 = base[_EMIFA_SDEXT_OFFSET]; + x8 = base[_EMIFA_CESEC0_OFFSET]; + x9 = base[_EMIFA_CESEC1_OFFSET]; + x10 = base[_EMIFA_CESEC2_OFFSET]; + x11 = base[_EMIFA_CESEC3_OFFSET]; + + x5 = base[_EMIFA_SDCTL_OFFSET]; + + cfg->gblctl = x0; + cfg->cectl0 = x1; + cfg->cectl1 = x2; + cfg->cectl2 = x3; + cfg->cectl3 = x4; + cfg->sdctl = x5; + cfg->sdtim = x6; + cfg->sdext = x7; + cfg->cesec0 = x8; + cfg->cesec1 = x9; + cfg->cesec2 = x10; + cfg->cesec3 = x11; + + IRQ_globalRestore(gie); +} +#endif /* C64_SUPPORT */ +/*----------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------*/ +#endif /* USEDEFS */ + + +#endif /* EMIFA_SUPPORT */ +#endif /* _CSL_EMIF_H_ */ +/******************************************************************************\ +* End of csl_emifa.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_emifahal.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_emifahal.h new file mode 100644 index 0000000..74b7b67 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_emifahal.h @@ -0,0 +1,894 @@ +/******************************************************************************\ +* Copyright (C) 2001 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_emifahal.h +* DATE CREATED.. 03/27/2001 +* LAST MODIFIED. 08/02/2004 - Adding support for C6418 +* 03/27/2001 +* 04/16/2004 Added PDTCTL register support +*------------------------------------------------------------------------------ +* REGISTERS +* +* GBLCTL - global control register +* CECTL0 - CE space control register 0 +* CECTL1 - CE space control register 1 +* CECTL2 - CE space control register 2 +* CECTL3 - CE space control register 3 +* SDCTL - SDRAM control regsiter +* SDTIM - SDRAM timing register +* SDEXT - SDRAM extension register +* CESEC0 - EMIFA CE0 secondary control +* CESEC1 - EMIFA CE1 secondary control +* CESEC2 - EMIFA CE2 secondary control +* CESEC3 - EMIFA CE3 secondary control +* PDTCTL - Peripheral device transfer control +* +\******************************************************************************/ +#ifndef _CSL_EMIFAHAL_H_ +#define _CSL_EMIFAHAL_H_ + + +#include +#include + +#if (EMIFA_SUPPORT) +/******************************************************************************\ +* MISC section +\******************************************************************************/ +#define _EMIFA_BASE_GLOBAL 0x01800000u + +/******************************************************************************\ +* module level register/field access macros +\******************************************************************************/ + + /* ----------------- */ + /* FIELD MAKE MACROS */ + /* ----------------- */ + + #define EMIFA_FMK(REG,FIELD,x)\ + _PER_FMK(EMIFA,##REG,##FIELD,x) + + #define EMIFA_FMKS(REG,FIELD,SYM)\ + _PER_FMKS(EMIFA,##REG,##FIELD,##SYM) + + + /* -------------------------------- */ + /* RAW REGISTER/FIELD ACCESS MACROS */ + /* -------------------------------- */ + + #define EMIFA_ADDR(REG)\ + _EMIFA_##REG##_ADDR + + #define EMIFA_RGET(REG)\ + _PER_RGET(_EMIFA_##REG##_ADDR,EMIFA,##REG) + + #define EMIFA_RSET(REG,x)\ + _PER_RSET(_EMIFA_##REG##_ADDR,EMIFA,##REG,x) + + #define EMIFA_FGET(REG,FIELD)\ + _EMIFA_##REG##_FGET(##FIELD) + + #define EMIFA_FSET(REG,FIELD,x)\ + _EMIFA_##REG##_FSET(##FIELD,##x) + + #define EMIFA_FSETS(REG,FIELD,SYM)\ + _EMIFA_##REG##_FSETS(##FIELD,##SYM) + + + /* ------------------------------------------ */ + /* ADDRESS BASED REGISTER/FIELD ACCESS MACROS */ + /* ------------------------------------------ */ + + #define EMIFA_RGETA(addr,REG)\ + _PER_RGET(addr,EMIFA,##REG) + + #define EMIFA_RSETA(addr,REG,x)\ + _PER_RSET(addr,EMIFA,##REG,x) + + #define EMIFA_FGETA(addr,REG,FIELD)\ + _PER_FGET(addr,EMIFA,##REG,##FIELD) + + #define EMIFA_FSETA(addr,REG,FIELD,x)\ + _PER_FSET(addr,EMIFA,##REG,##FIELD,x) + + #define EMIFA_FSETSA(addr,REG,FIELD,SYM)\ + _PER_FSETS(addr,EMIFA,##REG,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | G B L C T L | +* |___________________| +* +* GBLCTL - global control register +* +* FIELDS (msb -> lsb) +* (rw) EK2RATE +* (rw) EK2HZ +* (rw) EK2EN +* (rw) BRMODE +* (r) BUSREQ +* (r) ARDY +* (r) HOLD +* (r) HOLDA +* (rw) NOHOLD +* (rw) EK1HZ +* (rw) EK1EN +* (rw) CLK4EN +* (rw) CLK6EN +* +\******************************************************************************/ + #define _EMIFA_GBLCTL_OFFSET 0 + + #define _EMIFA_GBLCTL_ADDR 0x01800000u + + #define _EMIFA_GBLCTL_EK2RATE_MASK 0x000C0000u + #define _EMIFA_GBLCTL_EK2RATE_SHIFT 0x00000012u + #define EMIFA_GBLCTL_EK2RATE_DEFAULT 0x00000002u + #define EMIFA_GBLCTL_EK2RATE_OF(x) _VALUEOF(x) + #define EMIFA_GBLCTL_EK2RATE_FULLCLK 0x00000000u + #define EMIFA_GBLCTL_EK2RATE_HALFCLK 0x00000001u + #define EMIFA_GBLCTL_EK2RATE_QUARCLK 0x00000002u + + #define _EMIFA_GBLCTL_EK2HZ_MASK 0x00020000u + #define _EMIFA_GBLCTL_EK2HZ_SHIFT 0x00000011u + #define EMIFA_GBLCTL_EK2HZ_DEFAULT 0x00000000u + #define EMIFA_GBLCTL_EK2HZ_OF(x) _VALUEOF(x) + #define EMIFA_GBLCTL_EK2HZ_CLK 0x00000000u + #define EMIFA_GBLCTL_EK2HZ_HIGHZ 0x00000001u + + #define _EMIFA_GBLCTL_EK2EN_MASK 0x00010000u + #define _EMIFA_GBLCTL_EK2EN_SHIFT 0x00000010u + #define EMIFA_GBLCTL_EK2EN_DEFAULT 0x00000001u + #define EMIFA_GBLCTL_EK2EN_OF(x) _VALUEOF(x) + #define EMIFA_GBLCTL_EK2EN_DISABLE 0x00000000u + #define EMIFA_GBLCTL_EK2EN_ENABLE 0x00000001u + + #define _EMIFA_GBLCTL_BRMODE_MASK 0x00002000u + #define _EMIFA_GBLCTL_BRMODE_SHIFT 0x0000000Du + #define EMIFA_GBLCTL_BRMODE_DEFAULT 0x00000001u + #define EMIFA_GBLCTL_BRMODE_OF(x) _VALUEOF(x) + #define EMIFA_GBLCTL_BRMODE_MSTATUS 0x00000000u + #define EMIFA_GBLCTL_BRMODE_MRSTATUS 0x00000001u + + #define _EMIFA_GBLCTL_BUSREQ_MASK 0x00000800u + #define _EMIFA_GBLCTL_BUSREQ_SHIFT 0x0000000Bu + #define EMIFA_GBLCTL_BUSREQ_DEFAULT 0x00000000u + #define EMIFA_GBLCTL_BUSREQ_OF(x) _VALUEOF(x) + #define EMIFA_GBLCTL_BUSREQ_LOW 0x00000000u + #define EMIFA_GBLCTL_BUSREQ_HIGH 0x00000001u + + #define _EMIFA_GBLCTL_ARDY_MASK 0x00000400u + #define _EMIFA_GBLCTL_ARDY_SHIFT 0x0000000Au + #define EMIFA_GBLCTL_ARDY_DEFAULT 0x00000000u + #define EMIFA_GBLCTL_ARDY_OF(x) _VALUEOF(x) + #define EMIFA_GBLCTL_ARDY_LOW 0x00000000u + #define EMIFA_GBLCTL_ARDY_HIGH 0x00000001u + + #define _EMIFA_GBLCTL_HOLD_MASK 0x00000200u + #define _EMIFA_GBLCTL_HOLD_SHIFT 0x00000009u + #define EMIFA_GBLCTL_HOLD_DEFAULT 0x00000000u + #define EMIFA_GBLCTL_HOLD_OF(x) _VALUEOF(x) + #define EMIFA_GBLCTL_HOLD_LOW 0x00000000u + #define EMIFA_GBLCTL_HOLD_HIGH 0x00000001u + + #define _EMIFA_GBLCTL_HOLDA_MASK 0x00000100u + #define _EMIFA_GBLCTL_HOLDA_SHIFT 0x00000008u + #define EMIFA_GBLCTL_HOLDA_DEFAULT 0x00000000u + #define EMIFA_GBLCTL_HOLDA_OF(x) _VALUEOF(x) + #define EMIFA_GBLCTL_HOLDA_LOW 0x00000000u + #define EMIFA_GBLCTL_HOLDA_HIGH 0x00000001u + + #define _EMIFA_GBLCTL_NOHOLD_MASK 0x00000080u + #define _EMIFA_GBLCTL_NOHOLD_SHIFT 0x00000007u + #define EMIFA_GBLCTL_NOHOLD_DEFAULT 0x00000000u + #define EMIFA_GBLCTL_NOHOLD_OF(x) _VALUEOF(x) + #define EMIFA_GBLCTL_NOHOLD_DISABLE 0x00000000u + #define EMIFA_GBLCTL_NOHOLD_ENABLE 0x00000001u + + #define _EMIFA_GBLCTL_EK1HZ_MASK 0x00000040u + #define _EMIFA_GBLCTL_EK1HZ_SHIFT 0x00000006u + #define EMIFA_GBLCTL_EK1HZ_DEFAULT 0x00000001u + #define EMIFA_GBLCTL_EK1HZ_OF(x) _VALUEOF(x) + #define EMIFA_GBLCTL_EK1HZ_CLK 0x00000000u + #define EMIFA_GBLCTL_EK1HZ_HIGHZ 0x00000001u + + #define _EMIFA_GBLCTL_EK1EN_MASK 0x00000020u + #define _EMIFA_GBLCTL_EK1EN_SHIFT 0x00000005u + #define EMIFA_GBLCTL_EK1EN_DEFAULT 0x00000001u + #define EMIFA_GBLCTL_EK1EN_OF(x) _VALUEOF(x) + #define EMIFA_GBLCTL_EK1EN_DISABLE 0x00000000u + #define EMIFA_GBLCTL_EK1EN_ENABLE 0x00000001u + + #define _EMIFA_GBLCTL_CLK4EN_MASK 0x00000010u + #define _EMIFA_GBLCTL_CLK4EN_SHIFT 0x00000004u + #define EMIFA_GBLCTL_CLK4EN_DEFAULT 0x00000001u + #define EMIFA_GBLCTL_CLK4EN_OF(x) _VALUEOF(x) + #define EMIFA_GBLCTL_CLK4EN_DISABLE 0x00000000u + #define EMIFA_GBLCTL_CLK4EN_ENABLE 0x00000001u + + #define _EMIFA_GBLCTL_CLK6EN_MASK 0x00000008u + #define _EMIFA_GBLCTL_CLK6EN_SHIFT 0x00000003u + #define EMIFA_GBLCTL_CLK6EN_DEFAULT 0x00000001u + #define EMIFA_GBLCTL_CLK6EN_OF(x) _VALUEOF(x) + #define EMIFA_GBLCTL_CLK6EN_DISABLE 0x00000000u + #define EMIFA_GBLCTL_CLK6EN_ENABLE 0x00000001u + + #define EMIFA_GBLCTL_OF(x) _VALUEOF(x) + + #define EMIFA_GBLCTL_DEFAULT (Uint32)( \ + 0x00000004\ + |_PER_FDEFAULT(EMIFA,GBLCTL,EK2RATE)\ + |_PER_FDEFAULT(EMIFA,GBLCTL,EK2HZ)\ + |_PER_FDEFAULT(EMIFA,GBLCTL,EK2EN)\ + |_PER_FDEFAULT(EMIFA,GBLCTL,BRMODE)\ + |_PER_FDEFAULT(EMIFA,GBLCTL,BUSREQ)\ + |_PER_FDEFAULT(EMIFA,GBLCTL,ARDY)\ + |_PER_FDEFAULT(EMIFA,GBLCTL,HOLD)\ + |_PER_FDEFAULT(EMIFA,GBLCTL,HOLDA)\ + |_PER_FDEFAULT(EMIFA,GBLCTL,NOHOLD)\ + |_PER_FDEFAULT(EMIFA,GBLCTL,EK1HZ)\ + |_PER_FDEFAULT(EMIFA,GBLCTL,EK1EN)\ + |_PER_FDEFAULT(EMIFA,GBLCTL,CLK4EN)\ + |_PER_FDEFAULT(EMIFA,GBLCTL,CLK6EN)\ + ) + + #define EMIFA_GBLCTL_RMK(ek2rate,ek2hz,ek2en,brmode,nohold,ek1hz,ek1en,clk4en,clk6en) \ + (Uint32)( \ + _PER_FMK(EMIFA,GBLCTL,EK2RATE,ek2rate)\ + |_PER_FMK(EMIFA,GBLCTL,EK2HZ,ek2hz)\ + |_PER_FMK(EMIFA,GBLCTL,EK2EN,ek2en)\ + |_PER_FMK(EMIFA,GBLCTL,BRMODE,brmode)\ + |_PER_FMK(EMIFA,GBLCTL,NOHOLD,nohold)\ + |_PER_FMK(EMIFA,GBLCTL,EK1HZ,ek1hz)\ + |_PER_FMK(EMIFA,GBLCTL,EK1EN,ek1en)\ + |_PER_FMK(EMIFA,GBLCTL,CLK4EN,clk4en)\ + |_PER_FMK(EMIFA,GBLCTL,CLK6EN,clk6en)\ + ) + + #define _EMIFA_GBLCTL_FGET(FIELD)\ + _PER_FGET(_EMIFA_GBLCTL_ADDR,EMIFA,GBLCTL,##FIELD) + + #define _EMIFA_GBLCTL_FSET(FIELD,field)\ + _PER_FSET(_EMIFA_GBLCTL_ADDR,EMIFA,GBLCTL,##FIELD,field) + + #define _EMIFA_GBLCTL_FSETS(FIELD,SYM)\ + _PER_FSETS(_EMIFA_GBLCTL_ADDR,EMIFA,GBLCTL,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | C E C T L | +* |___________________| +* +* CECTL0 - CE space control register 0 +* CECTL1 - CE space control register 1 +* CECTL2 - CE space control register 2 +* CECTL3 - CE space control register 3 +* +* FIELDS (msb -> lsb) +* (rw) WRSETUP +* (rw) WRSTRB +* (rw) WRHLD +* (rw) RDSETUP +* (rw) TA +* (rw) RDSTRB +* (rw) MTYPE +* (rw) RDHLD +* +\******************************************************************************/ + #define _EMIFA_CECTL0_OFFSET 2 + #define _EMIFA_CECTL1_OFFSET 1 + #define _EMIFA_CECTL2_OFFSET 4 + #define _EMIFA_CECTL3_OFFSET 5 + + #define _EMIFA_CECTL0_ADDR 0x01800008u + #define _EMIFA_CECTL1_ADDR 0x01800004u + #define _EMIFA_CECTL2_ADDR 0x01800010u + #define _EMIFA_CECTL3_ADDR 0x01800014u + + #define _EMIFA_CECTL_WRSETUP_MASK 0xF0000000u + #define _EMIFA_CECTL_WRSETUP_SHIFT 0x0000001Cu + #define EMIFA_CECTL_WRSETUP_DEFAULT 0x0000000Fu + #define EMIFA_CECTL_WRSETUP_OF(x) _VALUEOF(x) + + #define _EMIFA_CECTL_WRSTRB_MASK 0x0FC00000u + #define _EMIFA_CECTL_WRSTRB_SHIFT 0x00000016u + #define EMIFA_CECTL_WRSTRB_DEFAULT 0x0000003Fu + #define EMIFA_CECTL_WRSTRB_OF(x) _VALUEOF(x) + + #define _EMIFA_CECTL_WRHLD_MASK 0x00300000u + #define _EMIFA_CECTL_WRHLD_SHIFT 0x00000014u + #define EMIFA_CECTL_WRHLD_DEFAULT 0x00000003u + #define EMIFA_CECTL_WRHLD_OF(x) _VALUEOF(x) + + #define _EMIFA_CECTL_RDSETUP_MASK 0x000F0000u + #define _EMIFA_CECTL_RDSETUP_SHIFT 0x00000010u + #define EMIFA_CECTL_RDSETUP_DEFAULT 0x0000000Fu + #define EMIFA_CECTL_RDSETUP_OF(x) _VALUEOF(x) + + #define _EMIFA_CECTL_TA_MASK 0x0000C000u + #define _EMIFA_CECTL_TA_SHIFT 0x0000000Eu + #define EMIFA_CECTL_TA_DEFAULT 0x00000003u + #define EMIFA_CECTL_TA_OF(x) _VALUEOF(x) + + #define _EMIFA_CECTL_RDSTRB_MASK 0x00003F00u + #define _EMIFA_CECTL_RDSTRB_SHIFT 0x00000008u + #define EMIFA_CECTL_RDSTRB_DEFAULT 0x0000003Fu + #define EMIFA_CECTL_RDSTRB_OF(x) _VALUEOF(x) + + #define _EMIFA_CECTL_MTYPE_MASK 0x000000F0u + #define _EMIFA_CECTL_MTYPE_SHIFT 0x00000004u + #define EMIFA_CECTL_MTYPE_DEFAULT 0x00000000u + #define EMIFA_CECTL_MTYPE_OF(x) _VALUEOF(x) + #define EMIFA_CECTL_MTYPE_ASYNC8 0x00000000u + #define EMIFA_CECTL_MTYPE_ASYNC16 0x00000001u + #define EMIFA_CECTL_MTYPE_ASYNC32 0x00000002u + #define EMIFA_CECTL_MTYPE_SDRAM32 0x00000003u + #define EMIFA_CECTL_MTYPE_SYNC32 0x00000004u + #define EMIFA_CECTL_MTYPE_SDRAM8 0x00000008u + #define EMIFA_CECTL_MTYPE_SDRAM16 0x00000009u + #define EMIFA_CECTL_MTYPE_SYNC8 0x0000000Au + #define EMIFA_CECTL_MTYPE_SYNC16 0x0000000Bu +#if (!(CHIP_6410 || CHIP_6413 || CHIP_6418 )) + #define EMIFA_CECTL_MTYPE_ASYNC64 0x0000000Cu + #define EMIFA_CECTL_MTYPE_SDRAM64 0x0000000Du + #define EMIFA_CECTL_MTYPE_SYNC64 0x0000000Eu +#endif + #define _EMIFA_CECTL_WRHLDMSB_MASK 0x00000008u + #define _EMIFA_CECTL_WRHLDMSB_SHIFT 0x00000003u + #define EMIFA_CECTL_WRHLDMSB_DEFAULT 0x00000000u + #define EMIFA_CECTL_WRHLDMSB_OF(x) _VALUEOF(x) + + #define _EMIFA_CECTL_RDHLD_MASK 0x00000007u + #define _EMIFA_CECTL_RDHLD_SHIFT 0x00000000u + #define EMIFA_CECTL_RDHLD_DEFAULT 0x00000003u + #define EMIFA_CECTL_RDHLD_OF(x) _VALUEOF(x) + + #define EMIFA_CECTL_OF(x) _VALUEOF(x) + + #define EMIFA_CECTL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(EMIFA,CECTL,WRSETUP)\ + |_PER_FDEFAULT(EMIFA,CECTL,WRSTRB)\ + |_PER_FDEFAULT(EMIFA,CECTL,WRHLD)\ + |_PER_FDEFAULT(EMIFA,CECTL,RDSETUP)\ + |_PER_FDEFAULT(EMIFA,CECTL,TA)\ + |_PER_FDEFAULT(EMIFA,CECTL,RDSTRB)\ + |_PER_FDEFAULT(EMIFA,CECTL,MTYPE)\ + |_PER_FDEFAULT(EMIFA,CECTL,WRHLDMSB)\ + |_PER_FDEFAULT(EMIFA,CECTL,RDHLD)\ + ) +#if (CHIP_6413 || CHIP_6418 || CHIP_6410) + /*Read only field TA has a value of 0x3 */ + #define EMIFA_CECTL_RMK(wrsetup,wrstrb,wrhld,rdsetup,rdstrb,mtype,\ + wrhldmsb,rdhld) (Uint32)( \ + _PER_FMK(EMIFA,CECTL,WRSETUP,wrsetup)\ + |_PER_FMK(EMIFA,CECTL,WRSTRB,wrstrb)\ + |_PER_FMK(EMIFA,CECTL,WRHLD,wrhld)\ + |_PER_FMK(EMIFA,CECTL,TA,0x3)\ + |_PER_FMK(EMIFA,CECTL,RDSETUP,rdsetup)\ + |_PER_FMK(EMIFA,CECTL,RDSTRB,rdstrb)\ + |_PER_FMK(EMIFA,CECTL,MTYPE,mtype)\ + |_PER_FMK(EMIFA,CECTL,WRHLDMSB,wrhldmsb)\ + |_PER_FMK(EMIFA,CECTL,RDHLD,rdhld)\ + ) +#else + #define EMIFA_CECTL_RMK(wrsetup,wrstrb,wrhld,ta,rdsetup,rdstrb,mtype,\ + wrhldmsb,rdhld) (Uint32)( \ + _PER_FMK(EMIFA,CECTL,WRSETUP,wrsetup)\ + |_PER_FMK(EMIFA,CECTL,WRSTRB,wrstrb)\ + |_PER_FMK(EMIFA,CECTL,WRHLD,wrhld)\ + |_PER_FMK(EMIFA,CECTL,TA,ta)\ + |_PER_FMK(EMIFA,CECTL,RDSETUP,rdsetup)\ + |_PER_FMK(EMIFA,CECTL,RDSTRB,rdstrb)\ + |_PER_FMK(EMIFA,CECTL,MTYPE,mtype)\ + |_PER_FMK(EMIFA,CECTL,WRHLDMSB,wrhldmsb)\ + |_PER_FMK(EMIFA,CECTL,RDHLD,rdhld)\ + ) +#endif + #define _EMIFA_CECTL_FGET(N,FIELD)\ + _PER_FGET(_EMIFA_CECTL##N##_ADDR,EMIFA,CECTL,##FIELD) + + #define _EMIFA_CECTL_FSET(N,FIELD,f)\ + _PER_FSET(_EMIFA_CECTL##N##_ADDR,EMIFA,CECTL,##FIELD,f) + + #define _EMIFA_CECTL_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_EMIFA_CECTL##N##_ADDR,EMIFA,CECTL,##FIELD,##SYM) + + #define _EMIFA_CECTL0_FGET(FIELD) _EMIFA_CECTL_FGET(0,##FIELD) + #define _EMIFA_CECTL1_FGET(FIELD) _EMIFA_CECTL_FGET(1,##FIELD) + #define _EMIFA_CECTL2_FGET(FIELD) _EMIFA_CECTL_FGET(2,##FIELD) + #define _EMIFA_CECTL3_FGET(FIELD) _EMIFA_CECTL_FGET(3,##FIELD) + + #define _EMIFA_CECTL0_FSET(FIELD,f) _EMIFA_CECTL_FSET(0,##FIELD,f) + #define _EMIFA_CECTL1_FSET(FIELD,f) _EMIFA_CECTL_FSET(1,##FIELD,f) + #define _EMIFA_CECTL2_FSET(FIELD,f) _EMIFA_CECTL_FSET(2,##FIELD,f) + #define _EMIFA_CECTL3_FSET(FIELD,f) _EMIFA_CECTL_FSET(3,##FIELD,f) + + #define _EMIFA_CECTL0_FSETS(FIELD,SYM) _EMIFA_CECTL_FSETS(0,##FIELD,##SYM) + #define _EMIFA_CECTL1_FSETS(FIELD,SYM) _EMIFA_CECTL_FSETS(1,##FIELD,##SYM) + #define _EMIFA_CECTL2_FSETS(FIELD,SYM) _EMIFA_CECTL_FSETS(2,##FIELD,##SYM) + #define _EMIFA_CECTL3_FSETS(FIELD,SYM) _EMIFA_CECTL_FSETS(3,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | S D C T L | +* |___________________| +* +* SDCTL - SDRAM control regsiter +* +* FIELDS (msb -> lsb) +* (rw) SDBSZ +* (rw) SDRSZ +* (rw) SDCSZ +* (rw) RFEN +* (w) INIT +* (rw) TRCD +* (rw) TRP +* (rw) TRC +* (rw) SLFRFR +* +\******************************************************************************/ + #define _EMIFA_SDCTL_OFFSET 6 + + #define _EMIFA_SDCTL_ADDR 0x01800018u + + #define _EMIFA_SDCTL_SDBSZ_MASK 0x40000000u + #define _EMIFA_SDCTL_SDBSZ_SHIFT 0x0000001Eu + #define EMIFA_SDCTL_SDBSZ_DEFAULT 0x00000000u + #define EMIFA_SDCTL_SDBSZ_OF(x) _VALUEOF(x) + #define EMIFA_SDCTL_SDBSZ_2BANKS 0x00000000u + #define EMIFA_SDCTL_SDBSZ_4BANKS 0x00000001u + + #define _EMIFA_SDCTL_SDRSZ_MASK 0x30000000u + #define _EMIFA_SDCTL_SDRSZ_SHIFT 0x0000001Cu + #define EMIFA_SDCTL_SDRSZ_DEFAULT 0x00000000u + #define EMIFA_SDCTL_SDRSZ_OF(x) _VALUEOF(x) + #define EMIFA_SDCTL_SDRSZ_11ROW 0x00000000u + #define EMIFA_SDCTL_SDRSZ_12ROW 0x00000001u + #define EMIFA_SDCTL_SDRSZ_13ROW 0x00000002u + + #define _EMIFA_SDCTL_SDCSZ_MASK 0x0C000000u + #define _EMIFA_SDCTL_SDCSZ_SHIFT 0x0000001Au + #define EMIFA_SDCTL_SDCSZ_DEFAULT 0x00000000u + #define EMIFA_SDCTL_SDCSZ_OF(x) _VALUEOF(x) + #define EMIFA_SDCTL_SDCSZ_9COL 0x00000000u + #define EMIFA_SDCTL_SDCSZ_8COL 0x00000001u + #define EMIFA_SDCTL_SDCSZ_10COL 0x00000002u + + #define _EMIFA_SDCTL_RFEN_MASK 0x02000000u + #define _EMIFA_SDCTL_RFEN_SHIFT 0x00000019u + #define EMIFA_SDCTL_RFEN_DEFAULT 0x00000001u + #define EMIFA_SDCTL_RFEN_OF(x) _VALUEOF(x) + #define EMIFA_SDCTL_RFEN_DISABLE 0x00000000u + #define EMIFA_SDCTL_RFEN_ENABLE 0x00000001u + + #define _EMIFA_SDCTL_INIT_MASK 0x01000000u + #define _EMIFA_SDCTL_INIT_SHIFT 0x00000018u + #define EMIFA_SDCTL_INIT_DEFAULT 0x00000001u + #define EMIFA_SDCTL_INIT_OF(x) _VALUEOF(x) + #define EMIFA_SDCTL_INIT_NO 0x00000000u + #define EMIFA_SDCTL_INIT_YES 0x00000001u + + #define _EMIFA_SDCTL_TRCD_MASK 0x00F00000u + #define _EMIFA_SDCTL_TRCD_SHIFT 0x00000014u + #define EMIFA_SDCTL_TRCD_DEFAULT 0x00000004u + #define EMIFA_SDCTL_TRCD_OF(x) _VALUEOF(x) + + #define _EMIFA_SDCTL_TRP_MASK 0x000F0000u + #define _EMIFA_SDCTL_TRP_SHIFT 0x00000010u + #define EMIFA_SDCTL_TRP_DEFAULT 0x00000008u + #define EMIFA_SDCTL_TRP_OF(x) _VALUEOF(x) + + #define _EMIFA_SDCTL_TRC_MASK 0x0000F000u + #define _EMIFA_SDCTL_TRC_SHIFT 0x0000000Cu + #define EMIFA_SDCTL_TRC_DEFAULT 0x0000000Fu + #define EMIFA_SDCTL_TRC_OF(x) _VALUEOF(x) + + #define _EMIFA_SDCTL_SLFRFR_MASK 0x00000001u + #define _EMIFA_SDCTL_SLFRFR_SHIFT 0x00000000u + #define EMIFA_SDCTL_SLFRFR_DEFAULT 0x00000000u + #define EMIFA_SDCTL_SLFRFR_OF(x) _VALUEOF(x) + #define EMIFA_SDCTL_SLFRFR_DISABLE 0x00000000u + #define EMIFA_SDCTL_SLFRFR_ENABLE 0x00000001u + + #define EMIFA_SDCTL_OF(x) _VALUEOF(x) + + #define EMIFA_SDCTL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(EMIFA,SDCTL,SDBSZ)\ + |_PER_FDEFAULT(EMIFA,SDCTL,SDRSZ)\ + |_PER_FDEFAULT(EMIFA,SDCTL,SDCSZ)\ + |_PER_FDEFAULT(EMIFA,SDCTL,RFEN)\ + |_PER_FDEFAULT(EMIFA,SDCTL,INIT)\ + |_PER_FDEFAULT(EMIFA,SDCTL,TRCD)\ + |_PER_FDEFAULT(EMIFA,SDCTL,TRP)\ + |_PER_FDEFAULT(EMIFA,SDCTL,TRC)\ + |_PER_FDEFAULT(EMIFA,SDCTL,SLFRFR)\ + ) + + #define EMIFA_SDCTL_RMK(sdbsz,sdrsz,sdcsz,rfen,init,trcd,trp,trc,slfrfr) (Uint32)(\ + _PER_FMK(EMIFA,SDCTL,SDBSZ,sdbsz)\ + |_PER_FMK(EMIFA,SDCTL,SDRSZ,sdrsz)\ + |_PER_FMK(EMIFA,SDCTL,SDCSZ,sdcsz)\ + |_PER_FMK(EMIFA,SDCTL,RFEN,rfen)\ + |_PER_FMK(EMIFA,SDCTL,INIT,init)\ + |_PER_FMK(EMIFA,SDCTL,TRCD,trcd)\ + |_PER_FMK(EMIFA,SDCTL,TRP,trp)\ + |_PER_FMK(EMIFA,SDCTL,TRC,trc)\ + |_PER_FMK(EMIFA,SDCTL,SLFRFR,slfrfr)\ + ) + + #define _EMIFA_SDCTL_FGET(FIELD)\ + _PER_FGET(_EMIFA_SDCTL_ADDR,EMIFA,SDCTL,##FIELD) + + #define _EMIFA_SDCTL_FSET(FIELD,field)\ + _PER_FSET(_EMIFA_SDCTL_ADDR,EMIFA,SDCTL,##FIELD,field) + + #define _EMIFA_SDCTL_FSETS(FIELD,SYM)\ + _PER_FSETS(_EMIFA_SDCTL_ADDR,EMIFA,SDCTL,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | S D T I M | +* |___________________| +* +* SDTIM - SDRAM timing register +* +* FIELDS (msb -> lsb) +* (rw) XRFR +* (r) CNTR +* (rw) PERIOD +* +\******************************************************************************/ + #define _EMIFA_SDTIM_OFFSET 7 + + #define _EMIFA_SDTIM_ADDR 0x0180001Cu + + #define _EMIFA_SDTIM_XRFR_MASK 0x03000000u + #define _EMIFA_SDTIM_XRFR_SHIFT 0x00000018u + #define EMIFA_SDTIM_XRFR_DEFAULT 0x00000000u + #define EMIFA_SDTIM_XRFR_OF(x) _VALUEOF(x) + + #define _EMIFA_SDTIM_CNTR_MASK 0x00FFF000u + #define _EMIFA_SDTIM_CNTR_SHIFT 0x0000000Cu + #define EMIFA_SDTIM_CNTR_DEFAULT 0x000005DCu + #define EMIFA_SDTIM_CNTR_OF(x) _VALUEOF(x) + + #define _EMIFA_SDTIM_PERIOD_MASK 0x00000FFFu + #define _EMIFA_SDTIM_PERIOD_SHIFT 0x00000000u + #define EMIFA_SDTIM_PERIOD_DEFAULT 0x000005DCu + #define EMIFA_SDTIM_PERIOD_OF(x) _VALUEOF(x) + + #define EMIFA_SDTIM_OF(x) _VALUEOF(x) + + #define EMIFA_SDTIM_DEFAULT (Uint32)( \ + _PER_FDEFAULT(EMIFA,SDTIM,XRFR)\ + |_PER_FDEFAULT(EMIFA,SDTIM,CNTR)\ + |_PER_FDEFAULT(EMIFA,SDTIM,PERIOD)\ + ) + + #define EMIFA_SDTIM_RMK(xrfr,period) (Uint32)(\ + _PER_FMK(EMIFA,SDTIM,XRFR,xrfr)\ + |_PER_FMK(EMIFA,SDTIM,PERIOD,period)\ + ) + + #define _EMIFA_SDTIM_FGET(FIELD)\ + _PER_FGET(_EMIFA_SDTIM_ADDR,EMIFA,SDTIM,##FIELD) + + #define _EMIFA_SDTIM_FSET(FIELD,field)\ + _PER_FSET(_EMIFA_SDTIM_ADDR,EMIFA,SDTIM,##FIELD,field) + + #define _EMIFA_SDTIM_FSETS(FIELD,SYM)\ + _PER_FSETS(_EMIFA_SDTIM_ADDR,EMIFA,SDTIM,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | S D E X T | +* |___________________| +* +* SDEXT - SDRAM extension register +* +* FIELDS (msb -> lsb) +* (rw) WR2RD +* (rw) WR2DEAC +* (rw) WR2WR +* (rw) R2WDQM +* (rw) RD2WR +* (rw) RD2DEAC +* (rw) RD2RD +* (rw) THZP +* (rw) TWR +* (rw) TRRD +* (rw) TRAS +* (rw) TCL +* +\******************************************************************************/ + #define _EMIFA_SDEXT_OFFSET 8 + + #define _EMIFA_SDEXT_ADDR 0x01800020u + + #define _EMIFA_SDEXT_WR2RD_MASK 0x00100000u + #define _EMIFA_SDEXT_WR2RD_SHIFT 0x00000014u + #define EMIFA_SDEXT_WR2RD_DEFAULT 0x00000001u + #define EMIFA_SDEXT_WR2RD_OF(x) _VALUEOF(x) + + #define _EMIFA_SDEXT_WR2DEAC_MASK 0x000C0000u + #define _EMIFA_SDEXT_WR2DEAC_SHIFT 0x00000012u + #define EMIFA_SDEXT_WR2DEAC_DEFAULT 0x00000001u + #define EMIFA_SDEXT_WR2DEAC_OF(x) _VALUEOF(x) + + #define _EMIFA_SDEXT_WR2WR_MASK 0x00020000u + #define _EMIFA_SDEXT_WR2WR_SHIFT 0x00000011u + #define EMIFA_SDEXT_WR2WR_DEFAULT 0x00000001u + #define EMIFA_SDEXT_WR2WR_OF(x) _VALUEOF(x) + + #define _EMIFA_SDEXT_R2WDQM_MASK 0x00018000u + #define _EMIFA_SDEXT_R2WDQM_SHIFT 0x0000000Fu + #define EMIFA_SDEXT_R2WDQM_DEFAULT 0x00000002u + #define EMIFA_SDEXT_R2WDQM_OF(x) _VALUEOF(x) + + #define _EMIFA_SDEXT_RD2WR_MASK 0x00007000u + #define _EMIFA_SDEXT_RD2WR_SHIFT 0x0000000Cu + #define EMIFA_SDEXT_RD2WR_DEFAULT 0x00000005u + #define EMIFA_SDEXT_RD2WR_OF(x) _VALUEOF(x) + + #define _EMIFA_SDEXT_RD2DEAC_MASK 0x00000C00u + #define _EMIFA_SDEXT_RD2DEAC_SHIFT 0x0000000Au + #define EMIFA_SDEXT_RD2DEAC_DEFAULT 0x00000003u + #define EMIFA_SDEXT_RD2DEAC_OF(x) _VALUEOF(x) + + #define _EMIFA_SDEXT_RD2RD_MASK 0x00000200u + #define _EMIFA_SDEXT_RD2RD_SHIFT 0x00000009u + #define EMIFA_SDEXT_RD2RD_DEFAULT 0x00000001u + #define EMIFA_SDEXT_RD2RD_OF(x) _VALUEOF(x) + + #define _EMIFA_SDEXT_THZP_MASK 0x00000180u + #define _EMIFA_SDEXT_THZP_SHIFT 0x00000007u + #define EMIFA_SDEXT_THZP_DEFAULT 0x00000002u + #define EMIFA_SDEXT_THZP_OF(x) _VALUEOF(x) + + #define _EMIFA_SDEXT_TWR_MASK 0x00000060u + #define _EMIFA_SDEXT_TWR_SHIFT 0x00000005u + #define EMIFA_SDEXT_TWR_DEFAULT 0x00000001u + #define EMIFA_SDEXT_TWR_OF(x) _VALUEOF(x) + + #define _EMIFA_SDEXT_TRRD_MASK 0x00000010u + #define _EMIFA_SDEXT_TRRD_SHIFT 0x00000004u + #define EMIFA_SDEXT_TRRD_DEFAULT 0x00000001u + #define EMIFA_SDEXT_TRRD_OF(x) _VALUEOF(x) + + #define _EMIFA_SDEXT_TRAS_MASK 0x0000000Eu + #define _EMIFA_SDEXT_TRAS_SHIFT 0x00000001u + #define EMIFA_SDEXT_TRAS_DEFAULT 0x00000007u + #define EMIFA_SDEXT_TRAS_OF(x) _VALUEOF(x) + + #define _EMIFA_SDEXT_TCL_MASK 0x00000001u + #define _EMIFA_SDEXT_TCL_SHIFT 0x00000000u + #define EMIFA_SDEXT_TCL_DEFAULT 0x00000001u + #define EMIFA_SDEXT_TCL_OF(x) _VALUEOF(x) + + #define EMIFA_SDEXT_OF(x) _VALUEOF(x) + + #define EMIFA_SDEXT_DEFAULT (Uint32)( \ + _PER_FDEFAULT(EMIFA,SDEXT,WR2RD)\ + |_PER_FDEFAULT(EMIFA,SDEXT,WR2DEAC)\ + |_PER_FDEFAULT(EMIFA,SDEXT,WR2WR)\ + |_PER_FDEFAULT(EMIFA,SDEXT,R2WDQM)\ + |_PER_FDEFAULT(EMIFA,SDEXT,RD2WR)\ + |_PER_FDEFAULT(EMIFA,SDEXT,RD2DEAC)\ + |_PER_FDEFAULT(EMIFA,SDEXT,RD2RD)\ + |_PER_FDEFAULT(EMIFA,SDEXT,THZP)\ + |_PER_FDEFAULT(EMIFA,SDEXT,TWR)\ + |_PER_FDEFAULT(EMIFA,SDEXT,TRRD)\ + |_PER_FDEFAULT(EMIFA,SDEXT,TRAS)\ + |_PER_FDEFAULT(EMIFA,SDEXT,TCL)\ + ) + + #define EMIFA_SDEXT_RMK(wr2rd,wr2deac,wr2wr,r2wdqm,rd2wr,rd2deac,\ + rd2rd,thzp,twr,trrd,tras,tcl) (Uint32)( \ + _PER_FMK(EMIFA,SDEXT,WR2RD,wr2rd)\ + |_PER_FMK(EMIFA,SDEXT,WR2DEAC,wr2deac)\ + |_PER_FMK(EMIFA,SDEXT,WR2WR,wr2wr)\ + |_PER_FMK(EMIFA,SDEXT,R2WDQM,r2wdqm)\ + |_PER_FMK(EMIFA,SDEXT,RD2WR,rd2wr)\ + |_PER_FMK(EMIFA,SDEXT,RD2DEAC,rd2deac)\ + |_PER_FMK(EMIFA,SDEXT,RD2RD,rd2rd)\ + |_PER_FMK(EMIFA,SDEXT,THZP,thzp)\ + |_PER_FMK(EMIFA,SDEXT,TWR,twr)\ + |_PER_FMK(EMIFA,SDEXT,TRRD,trrd)\ + |_PER_FMK(EMIFA,SDEXT,TRAS,tras)\ + |_PER_FMK(EMIFA,SDEXT,TCL,tcl)\ + ) + + #define _EMIFA_SDEXT_FGET(FIELD)\ + _PER_FGET(_EMIFA_SDEXT_ADDR,EMIFA,SDEXT,##FIELD) + + #define _EMIFA_SDEXT_FSET(FIELD,field)\ + _PER_FSET(_EMIFA_SDEXT_ADDR,EMIFA,SDEXT,##FIELD,field) + + #define _EMIFA_SDEXT_FSETS(FIELD,SYM)\ + _PER_FSETS(_EMIFA_SDEXT_ADDR,EMIFA,SDEXT,##FIELD,##SYM) + +/******************************************************************************\ +* _____________________ +* | | +* | C E x S E C | +* |___________________| +* +* CESEC0 - CE space secondary control register 0 +* CESEC1 - CE space secondary control register 1 +* CESEC2 - CE space secondary control register 2 +* CESEC3 - CE space secondary control register 3 +* +* FIELDS (msb -> lsb) +* (rw) SNCCLK +* (rw) RENEN +* (rw) CEEXT +* (rw) SYNCWL +* (rw) SYNCRL +* +\******************************************************************************/ + #define _EMIFA_CESEC0_OFFSET 18 + #define _EMIFA_CESEC1_OFFSET 17 + #define _EMIFA_CESEC2_OFFSET 20 + #define _EMIFA_CESEC3_OFFSET 21 + + #define _EMIFA_CESEC0_ADDR 0x01800048u + #define _EMIFA_CESEC1_ADDR 0x01800044u + #define _EMIFA_CESEC2_ADDR 0x01800050u + #define _EMIFA_CESEC3_ADDR 0x01800054u + + #define _EMIFA_CESEC_SNCCLK_MASK 0x00000040u + #define _EMIFA_CESEC_SNCCLK_SHIFT 0x00000006u + #define EMIFA_CESEC_SNCCLK_DEFAULT 0x00000000u + #define EMIFA_CESEC_SNCCLK_OF(x) _VALUEOF(x) + #define EMIFA_CESEC_SNCCLK_ECLKOUT1 0x00000000u + #define EMIFA_CESEC_SNCCLK_ECLKOUT2 0x00000001u + + #define _EMIFA_CESEC_RENEN_MASK 0x00000020u + #define _EMIFA_CESEC_RENEN_SHIFT 0x00000005u + #define EMIFA_CESEC_RENEN_DEFAULT 0x00000000u + #define EMIFA_CESEC_RENEN_OF(x) _VALUEOF(x) + #define EMIFA_CESEC_RENEN_ADS 0x00000000u + #define EMIFA_CESEC_RENEN_READ 0x00000001u + + #define _EMIFA_CESEC_CEEXT_MASK 0x00000010u + #define _EMIFA_CESEC_CEEXT_SHIFT 0x00000004u + #define EMIFA_CESEC_CEEXT_DEFAULT 0x00000000u + #define EMIFA_CESEC_CEEXT_OF(x) _VALUEOF(x) + #define EMIFA_CESEC_CEEXT_INACTIVE 0x00000000u + #define EMIFA_CESEC_CEEXT_ACTIVE 0x00000001u + + #define _EMIFA_CESEC_SYNCWL_MASK 0x0000000Cu + #define _EMIFA_CESEC_SYNCWL_SHIFT 0x00000002u + #define EMIFA_CESEC_SYNCWL_DEFAULT 0x00000000u + #define EMIFA_CESEC_SYNCWL_OF(x) _VALUEOF(x) + #define EMIFA_CESEC_SYNCWL_0CYCLE 0x00000000u + #define EMIFA_CESEC_SYNCWL_1CYCLE 0x00000001u + #define EMIFA_CESEC_SYNCWL_2CYCLE 0x00000002u + #define EMIFA_CESEC_SYNCWL_3CYCLE 0x00000003u + + #define _EMIFA_CESEC_SYNCRL_MASK 0x00000003u + #define _EMIFA_CESEC_SYNCRL_SHIFT 0x00000000u + #define EMIFA_CESEC_SYNCRL_DEFAULT 0x00000002u + #define EMIFA_CESEC_SYNCRL_OF(x) _VALUEOF(x) + #define EMIFA_CESEC_SYNCRL_0CYCLE 0x00000000u + #define EMIFA_CESEC_SYNCRL_1CYCLE 0x00000001u + #define EMIFA_CESEC_SYNCRL_2CYCLE 0x00000002u + #define EMIFA_CESEC_SYNCRL_3CYCLE 0x00000003u + + #define EMIFA_CESEC_OF(x) _VALUEOF(x) + + #define EMIFA_CESEC_DEFAULT (Uint32)( \ + _PER_FDEFAULT(EMIFA,CESEC,SNCCLK)\ + |_PER_FDEFAULT(EMIFA,CESEC,RENEN)\ + |_PER_FDEFAULT(EMIFA,CESEC,CEEXT)\ + |_PER_FDEFAULT(EMIFA,CESEC,SYNCWL)\ + |_PER_FDEFAULT(EMIFA,CESEC,SYNCRL)\ + ) + + #define EMIFA_CESEC_RMK(sncclk,renen,ceext,syncwl,syncrl)\ + (Uint32)( \ + _PER_FMK(EMIFA,CESEC,SNCCLK,sncclk)\ + |_PER_FMK(EMIFA,CESEC,RENEN,renen)\ + |_PER_FMK(EMIFA,CESEC,CEEXT,ceext)\ + |_PER_FMK(EMIFA,CESEC,SYNCWL,syncwl)\ + |_PER_FMK(EMIFA,CESEC,SYNCRL,syncrl)\ + ) + + #define _EMIFA_CESEC_FGET(N,FIELD)\ + _PER_FGET(_EMIFA_CESEC##N##_ADDR,EMIFA,CESEC,##FIELD) + + #define _EMIFA_CESEC_FSET(N,FIELD,f)\ + _PER_FSET(_EMIFA_CESEC##N##_ADDR,EMIFA,CESEC,##FIELD,f) + + #define _EMIFA_CESEC_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_EMIFA_CESEC##N##_ADDR,EMIFA,CESEC,##FIELD,##SYM) + + #define _EMIFA_CESEC0_FGET(FIELD) _EMIFA_CESEC_FGET(0,##FIELD) + #define _EMIFA_CESEC1_FGET(FIELD) _EMIFA_CESEC_FGET(1,##FIELD) + #define _EMIFA_CESEC2_FGET(FIELD) _EMIFA_CESEC_FGET(2,##FIELD) + #define _EMIFA_CESEC3_FGET(FIELD) _EMIFA_CESEC_FGET(3,##FIELD) + + #define _EMIFA_CESEC0_FSET(FIELD,f) _EMIFA_CESEC_FSET(0,##FIELD,f) + #define _EMIFA_CESEC1_FSET(FIELD,f) _EMIFA_CESEC_FSET(1,##FIELD,f) + #define _EMIFA_CESEC2_FSET(FIELD,f) _EMIFA_CESEC_FSET(2,##FIELD,f) + #define _EMIFA_CESEC3_FSET(FIELD,f) _EMIFA_CESEC_FSET(3,##FIELD,f) + + #define _EMIFA_CESEC0_FSETS(FIELD,SYM) _EMIFA_CESEC_FSETS(0,##FIELD,##SYM) + #define _EMIFA_CESEC1_FSETS(FIELD,SYM) _EMIFA_CESEC_FSETS(1,##FIELD,##SYM) + #define _EMIFA_CESEC2_FSETS(FIELD,SYM) _EMIFA_CESEC_FSETS(2,##FIELD,##SYM) + #define _EMIFA_CESEC3_FSETS(FIELD,SYM) _EMIFA_CESEC_FSETS(3,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | P D T C T L | +* |___________________| +* +* PDTCTL - Peripheral device transfer (PDT) control +* +* FIELDS (msb -> lsb) +* (rw) PDTWL +* (rw) PDTRL +* +\******************************************************************************/ + #define _EMIFA_PDTCTL_OFFSET 16 + + #define _EMIFA_PDTCTL_ADDR 0x01800040u + + #define _EMIFA_PDTCTL_PDTWL_MASK 0x0000000Cu + #define _EMIFA_PDTCTL_PDTWL_SHIFT 0x00000002u + #define EMIFA_PDTCTL_PDTWL_DEFAULT 0x00000000u + #define EMIFA_PDTCTL_PDTWL_OF(x) _VALUEOF(x) + #define EMIFA_PDTCTL_PDTWL_0CYCLE 0x00000000u + #define EMIFA_PDTCTL_PDTWL_1CYCLE 0x00000001u + #define EMIFA_PDTCTL_PDTWL_2CYCLE 0x00000002u + #define EMIFA_PDTCTL_PDTWL_3CYCLE 0x00000003u + + #define _EMIFA_PDTCTL_PDTRL_MASK 0x000C0003u + #define _EMIFA_PDTCTL_PDTRL_SHIFT 0x00000000u + #define EMIFA_PDTCTL_PDTRL_DEFAULT 0x00000000u + #define EMIFA_PDTCTL_PDTRL_OF(x) _VALUEOF(x) + #define EMIFA_PDTCTL_PDTRL_0CYCLE 0x00000000u + #define EMIFA_PDTCTL_PDTRL_1CYCLE 0x00000001u + #define EMIFA_PDTCTL_PDTRL_2CYCLE 0x00000002u + #define EMIFA_PDTCTL_PDTRL_3CYCLE 0x00000003u + + + #define EMIFA_PDTCTL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(EMIFA,PDTCTL,PDTWL)\ + |_PER_FDEFAULT(EMIFA,PDTCTL,PDTRL)\ + ) + + #define EMIFA_PDTCTL_RMK(pdtwl,pdtrl) (Uint32)( \ + _PER_FMK(EMIFA,PDTCTL,PDTWL,pdtwl)\ + |_PER_FMK(EMIFA,PDTCTL,PDTRL,pdtrl)\ + ) + + #define _EMIFA_PDTCTL_FGET(FIELD)\ + _PER_FGET(_EMIFA_PDTCTL_ADDR,EMIFA,PDTCTL,##FIELD) + + #define _EMIFA_PDTCTL_FSET(FIELD,field)\ + _PER_FSET(_EMIFA_PDTCTL_ADDR,EMIFA,PDTCTL,##FIELD,field) + + #define _EMIFA_PDTCTL_FSETS(FIELD,SYM)\ + _PER_FSETS(_EMIFA_PDTCTL_ADDR,EMIFA,PDTCTL,##FIELD,##SYM) + +#endif /* EMIFA_SUPPORT */ + +#endif /* _CSL_EMIFHAL_H_ */ +/******************************************************************************\ +* End of csl_emifahal.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_emifb.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_emifb.h new file mode 100644 index 0000000..9721773 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_emifb.h @@ -0,0 +1,221 @@ +/******************************************************************************\ +* Copyright (C) 2001 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_emifb.h +* DATE CREATED.. 03/27/2001 +* LAST MODIFIED. 01/31/2002 SDCTL reg. setting after SDEXT reg.setting +\******************************************************************************/ +#ifndef _CSL_EMIFB_H_ +#define _CSL_EMIFB_H_ + +#include +#include +#include + + +#if (EMIFB_SUPPORT) +/******************************************************************************\ +* scope and inline control macros +\******************************************************************************/ +#ifdef __cplusplus +#define CSLAPI extern "C" far +#else +#define CSLAPI extern far +#endif + +#undef USEDEFS +#undef IDECL +#undef IDEF + +#ifdef _EMIFB_MOD_ + #define IDECL CSLAPI + #define USEDEFS + #define IDEF +#else + #ifdef _INLINE + #define IDECL static inline + #define USEDEFS + #define IDEF static inline + #else + #define IDECL CSLAPI + #endif +#endif + + +/******************************************************************************\ +* global macro declarations +\******************************************************************************/ + + +/******************************************************************************\ +* global typedef declarations +\******************************************************************************/ + +/* device configuration structure */ +typedef struct { + Uint32 gblctl; + Uint32 cectl0; + Uint32 cectl1; + Uint32 cectl2; + Uint32 cectl3; + Uint32 sdctl; + Uint32 sdtim; + Uint32 sdext; + Uint32 cesec0; + Uint32 cesec1; + Uint32 cesec2; + Uint32 cesec3; +} EMIFB_Config; + + +/******************************************************************************\ +* global variable declarations +\******************************************************************************/ + + +/******************************************************************************\ +* global function declarations +\******************************************************************************/ + + +/******************************************************************************\ +* inline function declarations +\******************************************************************************/ +#if (CHIP_6414 | CHIP_6415 | CHIP_6416 ) +IDECL void EMIFB_config(EMIFB_Config *config); +IDECL void EMIFB_configArgs(Uint32 gblctl, Uint32 cectl0, Uint32 cectl1, + Uint32 cectl2, Uint32 cectl3, Uint32 sdctl, Uint32 sdtim, Uint32 sdext, Uint32 cesec0, + Uint32 cesec1, Uint32 cesec2, Uint32 cesec3); +IDECL void EMIFB_getConfig(EMIFB_Config *config); +#endif + +/******************************************************************************\ +* inline function definitions +\******************************************************************************/ +#ifdef USEDEFS +/*----------------------------------------------------------------------------*/ +#if (CHIP_6414 | CHIP_6415 | CHIP_6416 ) +IDEF void EMIFB_config(EMIFB_Config *config) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)_EMIFB_BASE_GLOBAL; + register int x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11; + + gie = IRQ_globalDisable(); + + /* the compiler generates more efficient code if the loads */ + /* and stores are grouped together raher than intermixed */ + x0 = config->gblctl; + x1 = config->cectl0; + x2 = config->cectl1; + x3 = config->cectl2; + x4 = config->cectl3; + x5 = config->sdctl; + x6 = config->sdtim; + x7 = config->sdext; + x8 = config->cesec0; + x9 = config->cesec1; + x10 = config->cesec2; + x11 = config->cesec3; + + base[_EMIFB_GBLCTL_OFFSET] = x0; + base[_EMIFB_CECTL0_OFFSET] = x1; + base[_EMIFB_CECTL1_OFFSET] = x2; + base[_EMIFB_CECTL2_OFFSET] = x3; + base[_EMIFB_CECTL3_OFFSET] = x4; + base[_EMIFB_SDTIM_OFFSET] = x6; + base[_EMIFB_SDEXT_OFFSET] = x7; + base[_EMIFB_CESEC0_OFFSET] = x8; + base[_EMIFB_CESEC1_OFFSET] = x9; + base[_EMIFB_CESEC2_OFFSET] = x10; + base[_EMIFB_CESEC3_OFFSET] = x11; + + base[_EMIFB_SDCTL_OFFSET] = x5; + + + IRQ_globalRestore(gie); +} +#endif /* C64_SUPPORT */ +/*----------------------------------------------------------------------------*/ +#if (CHIP_6414 | CHIP_6415 | CHIP_6416 ) +IDEF void EMIFB_configArgs(Uint32 gblctl, Uint32 cectl0, Uint32 cectl1, + Uint32 cectl2, Uint32 cectl3, Uint32 sdctl, Uint32 sdtim, Uint32 sdext, + Uint32 cesec0, Uint32 cesec1, Uint32 cesec2, Uint32 cesec3) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)_EMIFB_BASE_GLOBAL; + + gie = IRQ_globalDisable(); + + base[_EMIFB_GBLCTL_OFFSET] = gblctl; + base[_EMIFB_CECTL0_OFFSET] = cectl0; + base[_EMIFB_CECTL1_OFFSET] = cectl1; + base[_EMIFB_CECTL2_OFFSET] = cectl2; + base[_EMIFB_CECTL3_OFFSET] = cectl3; + base[_EMIFB_SDTIM_OFFSET] = sdtim; + base[_EMIFB_SDEXT_OFFSET] = sdext; + base[_EMIFB_CESEC0_OFFSET] = cesec0; + base[_EMIFB_CESEC1_OFFSET] = cesec1; + base[_EMIFB_CESEC2_OFFSET] = cesec2; + base[_EMIFB_CESEC3_OFFSET] = cesec3; + + base[_EMIFB_SDCTL_OFFSET] = sdctl; + + IRQ_globalRestore(gie); +} + +#endif +/*----------------------------------------------------------------------------*/ +#if (CHIP_6414 | CHIP_6415 | CHIP_6416 ) +IDEF void EMIFB_getConfig(EMIFB_Config *config) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)_EMIFB_BASE_GLOBAL; + volatile EMIFB_Config* cfg = (volatile EMIFB_Config*)config; + register int x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11; + + gie = IRQ_globalDisable(); + + /* the compiler generates more efficient code if the loads */ + /* and stores are grouped together raher than intermixed */ + + x0 = base[_EMIFB_GBLCTL_OFFSET]; + x1 = base[_EMIFB_CECTL0_OFFSET]; + x2 = base[_EMIFB_CECTL1_OFFSET]; + x3 = base[_EMIFB_CECTL2_OFFSET]; + x4 = base[_EMIFB_CECTL3_OFFSET]; + x5 = base[_EMIFB_SDCTL_OFFSET]; + x6 = base[_EMIFB_SDTIM_OFFSET]; + x7 = base[_EMIFB_SDEXT_OFFSET]; + x8 = base[_EMIFB_CESEC0_OFFSET]; + x9 = base[_EMIFB_CESEC1_OFFSET]; + x10 = base[_EMIFB_CESEC2_OFFSET]; + x11 = base[_EMIFB_CESEC3_OFFSET]; + + cfg->gblctl = x0; + cfg->cectl0 = x1; + cfg->cectl1 = x2; + cfg->cectl2 = x3; + cfg->cectl3 = x4; + cfg->sdctl = x5; + cfg->sdtim = x6; + cfg->sdext = x7; + cfg->cesec0 = x8; + cfg->cesec1 = x9; + cfg->cesec2 = x10; + cfg->cesec3 = x11; + + IRQ_globalRestore(gie); +} +#endif /* C64_SUPPORT */ +/*----------------------------------------------------------------------------*/ +#endif /* USEDEFS */ + + +#endif /* EMIFB_SUPPORT */ +#endif /* _CSL_EMIFB_H_ */ +/******************************************************************************\ +* End of csl_emifb.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_emifbhal.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_emifbhal.h new file mode 100644 index 0000000..a7a690d --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_emifbhal.h @@ -0,0 +1,843 @@ +/******************************************************************************\ +* Copyright (C) 2001 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_emifhal.h +* DATE CREATED.. 03/27/2001 +* LAST MODIFIED. 03/27/2001 +* 04/08/2004 Added PDTCTL register support +*------------------------------------------------------------------------------ +* REGISTERS +* +* GBLCTL - global control register +* CECTL0 - CE space control register 0 +* CECTL1 - CE space control register 1 +* CECTL2 - CE space control register 2 +* CECTL3 - CE space control register 3 +* SDCTL - SDRAM control regsiter +* SDTIM - SDRAM timing register +* SDEXT - SDRAM extension register +* CESEC0 - EMIFB CE0 secondary control +* CESEC1 - EMIFB CE1 secondary control +* CESEC2 - EMIFB CE2 secondary control +* CESEC3 - EMIFB CE3 secondary control +* PDTCTL - Peripheral device transfer control +\******************************************************************************/ +#ifndef _CSL_EMIFBHAL_H_ +#define _CSL_EMIFBHAL_H_ + +#include +#include + +#if (EMIFB_SUPPORT) +/******************************************************************************\ +* MISC section +\******************************************************************************/ +#define _EMIFB_BASE_GLOBAL 0x01A80000u + + +/******************************************************************************\ +* module level register/field access macros +\******************************************************************************/ + + /* ----------------- */ + /* FIELD MAKE MACROS */ + /* ----------------- */ + + #define EMIFB_FMK(REG,FIELD,x)\ + _PER_FMK(EMIFB,##REG,##FIELD,x) + + #define EMIFB_FMKS(REG,FIELD,SYM)\ + _PER_FMKS(EMIFB,##REG,##FIELD,##SYM) + + + /* -------------------------------- */ + /* RAW REGISTER/FIELD ACCESS MACROS */ + /* -------------------------------- */ + + #define EMIFB_ADDR(REG)\ + _EMIFB_##REG##_ADDR + + #define EMIFB_RGET(REG)\ + _PER_RGET(_EMIFB_##REG##_ADDR,EMIFB,##REG) + + #define EMIFB_RSET(REG,x)\ + _PER_RSET(_EMIFB_##REG##_ADDR,EMIFB,##REG,x) + + #define EMIFB_FGET(REG,FIELD)\ + _EMIFB_##REG##_FGET(##FIELD) + + #define EMIFB_FSET(REG,FIELD,x)\ + _EMIFB_##REG##_FSET(##FIELD,##x) + + #define EMIFB_FSETS(REG,FIELD,SYM)\ + _EMIFB_##REG##_FSETS(##FIELD,##SYM) + + + /* ------------------------------------------ */ + /* ADDRESS BASED REGISTER/FIELD ACCESS MACROS */ + /* ------------------------------------------ */ + + #define EMIFB_RGETA(addr,REG)\ + _PER_RGET(addr,EMIFB,##REG) + + #define EMIFB_RSETA(addr,REG,x)\ + _PER_RSET(addr,EMIFB,##REG,x) + + #define EMIFB_FGETA(addr,REG,FIELD)\ + _PER_FGET(addr,EMIFB,##REG,##FIELD) + + #define EMIFB_FSETA(addr,REG,FIELD,x)\ + _PER_FSET(addr,EMIFB,##REG,##FIELD,x) + + #define EMIFB_FSETSA(addr,REG,FIELD,SYM)\ + _PER_FSETS(addr,EMIFB,##REG,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | G B L C T L | +* |___________________| +* +* GBLCTL - global control register +* +* FIELDS (msb -> lsb) +* (rw) EK2RATE +* (rw) EK2HZ +* (rw) EK2EN +* (rw) BRMODE +* (r) BUSREQ +* (r) ARDY +* (r) HOLD +* (r) HOLDA +* (rw) NOHOLD +* (rw) EK1HZ +* (rw) EK1EN +* +\******************************************************************************/ + #define _EMIFB_GBLCTL_OFFSET 0 + + #define _EMIFB_GBLCTL_ADDR 0x01A80000u + + #define _EMIFB_GBLCTL_EK2RATE_MASK 0x000C0000u + #define _EMIFB_GBLCTL_EK2RATE_SHIFT 0x00000012u + #define EMIFB_GBLCTL_EK2RATE_DEFAULT 0x00000002u + #define EMIFB_GBLCTL_EK2RATE_OF(x) _VALUEOF(x) + #define EMIFB_GBLCTL_EK2RATE_FULLCLK 0x00000000u + #define EMIFB_GBLCTL_EK2RATE_HALFCLK 0x00000001u + #define EMIFB_GBLCTL_EK2RATE_QUARCLK 0x00000002u + + #define _EMIFB_GBLCTL_EK2HZ_MASK 0x00020000u + #define _EMIFB_GBLCTL_EK2HZ_SHIFT 0x00000011u + #define EMIFB_GBLCTL_EK2HZ_DEFAULT 0x00000000u + #define EMIFB_GBLCTL_EK2HZ_OF(x) _VALUEOF(x) + #define EMIFB_GBLCTL_EK2HZ_CLK 0x00000000u + #define EMIFB_GBLCTL_EK2HZ_HIGHZ 0x00000001u + + #define _EMIFB_GBLCTL_EK2EN_MASK 0x00010000u + #define _EMIFB_GBLCTL_EK2EN_SHIFT 0x00000010u + #define EMIFB_GBLCTL_EK2EN_DEFAULT 0x00000001u + #define EMIFB_GBLCTL_EK2EN_OF(x) _VALUEOF(x) + #define EMIFB_GBLCTL_EK2EN_DISABLE 0x00000000u + #define EMIFB_GBLCTL_EK2EN_ENABLE 0x00000001u + + #define _EMIFB_GBLCTL_BRMODE_MASK 0x00002000u + #define _EMIFB_GBLCTL_BRMODE_SHIFT 0x0000000Du + #define EMIFB_GBLCTL_BRMODE_DEFAULT 0x00000001u + #define EMIFB_GBLCTL_BRMODE_OF(x) _VALUEOF(x) + #define EMIFB_GBLCTL_BRMODE_MSTATUS 0x00000000u + #define EMIFB_GBLCTL_BRMODE_MRSTATUS 0x00000001u + + #define _EMIFB_GBLCTL_BUSREQ_MASK 0x00000800u + #define _EMIFB_GBLCTL_BUSREQ_SHIFT 0x0000000Bu + #define EMIFB_GBLCTL_BUSREQ_DEFAULT 0x00000000u + #define EMIFB_GBLCTL_BUSREQ_OF(x) _VALUEOF(x) + #define EMIFB_GBLCTL_BUSREQ_LOW 0x00000000u + #define EMIFB_GBLCTL_BUSREQ_HIGH 0x00000001u + + #define _EMIFB_GBLCTL_ARDY_MASK 0x00000400u + #define _EMIFB_GBLCTL_ARDY_SHIFT 0x0000000Au + #define EMIFB_GBLCTL_ARDY_DEFAULT 0x00000000u + #define EMIFB_GBLCTL_ARDY_OF(x) _VALUEOF(x) + #define EMIFB_GBLCTL_ARDY_LOW 0x00000000u + #define EMIFB_GBLCTL_ARDY_HIGH 0x00000001u + + #define _EMIFB_GBLCTL_HOLD_MASK 0x00000200u + #define _EMIFB_GBLCTL_HOLD_SHIFT 0x00000009u + #define EMIFB_GBLCTL_HOLD_DEFAULT 0x00000000u + #define EMIFB_GBLCTL_HOLD_OF(x) _VALUEOF(x) + #define EMIFB_GBLCTL_HOLD_LOW 0x00000000u + #define EMIFB_GBLCTL_HOLD_HIGH 0x00000001u + + #define _EMIFB_GBLCTL_HOLDA_MASK 0x00000100u + #define _EMIFB_GBLCTL_HOLDA_SHIFT 0x00000008u + #define EMIFB_GBLCTL_HOLDA_DEFAULT 0x00000000u + #define EMIFB_GBLCTL_HOLDA_OF(x) _VALUEOF(x) + #define EMIFB_GBLCTL_HOLDA_LOW 0x00000000u + #define EMIFB_GBLCTL_HOLDA_HIGH 0x00000001u + + #define _EMIFB_GBLCTL_NOHOLD_MASK 0x00000080u + #define _EMIFB_GBLCTL_NOHOLD_SHIFT 0x00000007u + #define EMIFB_GBLCTL_NOHOLD_DEFAULT 0x00000000u + #define EMIFB_GBLCTL_NOHOLD_OF(x) _VALUEOF(x) + #define EMIFB_GBLCTL_NOHOLD_DISABLE 0x00000000u + #define EMIFB_GBLCTL_NOHOLD_ENABLE 0x00000001u + + #define _EMIFB_GBLCTL_EK1HZ_MASK 0x00000040u + #define _EMIFB_GBLCTL_EK1HZ_SHIFT 0x00000006u + #define EMIFB_GBLCTL_EK1HZ_DEFAULT 0x00000001u + #define EMIFB_GBLCTL_EK1HZ_OF(x) _VALUEOF(x) + #define EMIFB_GBLCTL_EK1HZ_CLK 0x00000000u + #define EMIFB_GBLCTL_EK1HZ_HIGHZ 0x00000001u + + #define _EMIFB_GBLCTL_EK1EN_MASK 0x00000020u + #define _EMIFB_GBLCTL_EK1EN_SHIFT 0x00000005u + #define EMIFB_GBLCTL_EK1EN_DEFAULT 0x00000001u + #define EMIFB_GBLCTL_EK1EN_OF(x) _VALUEOF(x) + #define EMIFB_GBLCTL_EK1EN_DISABLE 0x00000000u + #define EMIFB_GBLCTL_EK1EN_ENABLE 0x00000001u + + #define EMIFB_GBLCTL_OF(x) _VALUEOF(x) + + #define EMIFB_GBLCTL_DEFAULT (Uint32)( \ + 0x00000004\ + |_PER_FDEFAULT(EMIFB,GBLCTL,EK2RATE)\ + |_PER_FDEFAULT(EMIFB,GBLCTL,EK2HZ)\ + |_PER_FDEFAULT(EMIFB,GBLCTL,EK2EN)\ + |_PER_FDEFAULT(EMIFB,GBLCTL,BRMODE)\ + |_PER_FDEFAULT(EMIFB,GBLCTL,BUSREQ)\ + |_PER_FDEFAULT(EMIFB,GBLCTL,ARDY)\ + |_PER_FDEFAULT(EMIFB,GBLCTL,HOLD)\ + |_PER_FDEFAULT(EMIFB,GBLCTL,HOLDA)\ + |_PER_FDEFAULT(EMIFB,GBLCTL,NOHOLD)\ + |_PER_FDEFAULT(EMIFB,GBLCTL,EK1HZ)\ + |_PER_FDEFAULT(EMIFB,GBLCTL,EK1EN)\ + ) + + #define EMIFB_GBLCTL_RMK(ek2rate,ek2hz,ek2en,brmode,nohold,ek1hz,ek1en) \ + (Uint32)( \ + _PER_FMK(EMIFB,GBLCTL,EK2RATE,ek2rate)\ + |_PER_FMK(EMIFB,GBLCTL,EK2HZ,ek2hz)\ + |_PER_FMK(EMIFB,GBLCTL,EK2EN,ek2en)\ + |_PER_FMK(EMIFB,GBLCTL,BRMODE,brmode)\ + |_PER_FMK(EMIFB,GBLCTL,NOHOLD,nohold)\ + |_PER_FMK(EMIFB,GBLCTL,EK1HZ,ek1hz)\ + |_PER_FMK(EMIFB,GBLCTL,EK1EN,ek1en)\ + ) + + #define _EMIFB_GBLCTL_FGET(FIELD)\ + _PER_FGET(_EMIFB_GBLCTL_ADDR,EMIFB,GBLCTL,##FIELD) + + #define _EMIFB_GBLCTL_FSET(FIELD,field)\ + _PER_FSET(_EMIFB_GBLCTL_ADDR,EMIFB,GBLCTL,##FIELD,field) + + #define _EMIFB_GBLCTL_FSETS(FIELD,SYM)\ + _PER_FSETS(_EMIFB_GBLCTL_ADDR,EMIFB,GBLCTL,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | C E C T L | +* |___________________| +* +* CECTL0 - CE space control register 0 +* CECTL1 - CE space control register 1 +* CECTL2 - CE space control register 2 +* CECTL3 - CE space control register 3 +* +* FIELDS (msb -> lsb) +* (rw) WRSETUP +* (rw) WRSTRB +* (rw) WRHLD +* (rw) RDSETUP +* (rw) TA +* (rw) RDSTRB +* (rw) MTYPE +* (rw) RDHLD +* +\******************************************************************************/ + #define _EMIFB_CECTL0_OFFSET 2 + #define _EMIFB_CECTL1_OFFSET 1 + #define _EMIFB_CECTL2_OFFSET 4 + #define _EMIFB_CECTL3_OFFSET 5 + + #define _EMIFB_CECTL0_ADDR 0x01A80008u + #define _EMIFB_CECTL1_ADDR 0x01A80004u + #define _EMIFB_CECTL2_ADDR 0x01A80010u + #define _EMIFB_CECTL3_ADDR 0x01A80014u + + #define _EMIFB_CECTL_WRSETUP_MASK 0xF0000000u + #define _EMIFB_CECTL_WRSETUP_SHIFT 0x0000001Cu + #define EMIFB_CECTL_WRSETUP_DEFAULT 0x0000000Fu + #define EMIFB_CECTL_WRSETUP_OF(x) _VALUEOF(x) + + #define _EMIFB_CECTL_WRSTRB_MASK 0x0FC00000u + #define _EMIFB_CECTL_WRSTRB_SHIFT 0x00000016u + #define EMIFB_CECTL_WRSTRB_DEFAULT 0x0000003Fu + #define EMIFB_CECTL_WRSTRB_OF(x) _VALUEOF(x) + + #define _EMIFB_CECTL_WRHLD_MASK 0x00300000u + #define _EMIFB_CECTL_WRHLD_SHIFT 0x00000014u + #define EMIFB_CECTL_WRHLD_DEFAULT 0x00000003u + #define EMIFB_CECTL_WRHLD_OF(x) _VALUEOF(x) + + #define _EMIFB_CECTL_RDSETUP_MASK 0x000F0000u + #define _EMIFB_CECTL_RDSETUP_SHIFT 0x00000010u + #define EMIFB_CECTL_RDSETUP_DEFAULT 0x0000000Fu + #define EMIFB_CECTL_RDSETUP_OF(x) _VALUEOF(x) + + #define _EMIFB_CECTL_TA_MASK 0x0000C000u + #define _EMIFB_CECTL_TA_SHIFT 0x0000000Eu + #define EMIFB_CECTL_TA_DEFAULT 0x00000003u + #define EMIFB_CECTL_TA_OF(x) _VALUEOF(x) + + #define _EMIFB_CECTL_RDSTRB_MASK 0x00003F00u + #define _EMIFB_CECTL_RDSTRB_SHIFT 0x00000008u + #define EMIFB_CECTL_RDSTRB_DEFAULT 0x0000003Fu + #define EMIFB_CECTL_RDSTRB_OF(x) _VALUEOF(x) + + #define _EMIFB_CECTL_MTYPE_MASK 0x000000F0u + #define _EMIFB_CECTL_MTYPE_SHIFT 0x00000004u + #define EMIFB_CECTL_MTYPE_DEFAULT 0x00000000u + #define EMIFB_CECTL_MTYPE_OF(x) _VALUEOF(x) + #define EMIFB_CECTL_MTYPE_ASYNC8 0x00000000u + #define EMIFB_CECTL_MTYPE_ASYNC16 0x00000001u + #define EMIFB_CECTL_MTYPE_SDRAM8 0x00000008u + #define EMIFB_CECTL_MTYPE_SDRAM16 0x00000009u + #define EMIFB_CECTL_MTYPE_SYNC8 0x0000000Au + #define EMIFB_CECTL_MTYPE_SYNC16 0x0000000Bu + + #define _EMIFB_CECTL_WRHLDMSB_MASK 0x00000008u + #define _EMIFB_CECTL_WRHLDMSB_SHIFT 0x00000003u + #define EMIFB_CECTL_WRHLDMSB_DEFAULT 0x00000000u + #define EMIFB_CECTL_WRHLDMSB_OF(x) _VALUEOF(x) + + #define _EMIFB_CECTL_RDHLD_MASK 0x00000007u + #define _EMIFB_CECTL_RDHLD_SHIFT 0x00000000u + #define EMIFB_CECTL_RDHLD_DEFAULT 0x00000003u + #define EMIFB_CECTL_RDHLD_OF(x) _VALUEOF(x) + + #define EMIFB_CECTL_OF(x) _VALUEOF(x) + + #define EMIFB_CECTL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(EMIFB,CECTL,WRSETUP)\ + |_PER_FDEFAULT(EMIFB,CECTL,WRSTRB)\ + |_PER_FDEFAULT(EMIFB,CECTL,WRHLD)\ + |_PER_FDEFAULT(EMIFB,CECTL,RDSETUP)\ + |_PER_FDEFAULT(EMIFB,CECTL,TA)\ + |_PER_FDEFAULT(EMIFB,CECTL,RDSTRB)\ + |_PER_FDEFAULT(EMIFB,CECTL,MTYPE)\ + |_PER_FDEFAULT(EMIFB,CECTL,WRHLDMSB)\ + |_PER_FDEFAULT(EMIFB,CECTL,RDHLD)\ + ) + + #define EMIFB_CECTL_RMK(wrsetup,wrstrb,wrhld,rdsetup,ta,rdstrb,mtype,\ + wrhldmsb,rdhld) (Uint32)( \ + _PER_FMK(EMIFB,CECTL,WRSETUP,wrsetup)\ + |_PER_FMK(EMIFB,CECTL,WRSTRB,wrstrb)\ + |_PER_FMK(EMIFB,CECTL,WRHLD,wrhld)\ + |_PER_FMK(EMIFB,CECTL,RDSETUP,rdsetup)\ + |_PER_FMK(EMIFB,CECTL,TA,ta)\ + |_PER_FMK(EMIFB,CECTL,RDSTRB,rdstrb)\ + |_PER_FMK(EMIFB,CECTL,MTYPE,mtype)\ + |_PER_FMK(EMIFB,CECTL,WRHLDMSB,wrhldmsb)\ + |_PER_FMK(EMIFB,CECTL,RDHLD,rdhld)\ + ) + + #define _EMIFB_CECTL_FGET(N,FIELD)\ + _PER_FGET(_EMIFB_CECTL##N##_ADDR,EMIFB,CECTL,##FIELD) + + #define _EMIFB_CECTL_FSET(N,FIELD,f)\ + _PER_FSET(_EMIFB_CECTL##N##_ADDR,EMIFB,CECTL,##FIELD,f) + + #define _EMIFB_CECTL_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_EMIFB_CECTL##N##_ADDR,EMIFB,CECTL,##FIELD,##SYM) + + #define _EMIFB_CECTL0_FGET(FIELD) _EMIFB_CECTL_FGET(0,##FIELD) + #define _EMIFB_CECTL1_FGET(FIELD) _EMIFB_CECTL_FGET(1,##FIELD) + #define _EMIFB_CECTL2_FGET(FIELD) _EMIFB_CECTL_FGET(2,##FIELD) + #define _EMIFB_CECTL3_FGET(FIELD) _EMIFB_CECTL_FGET(3,##FIELD) + + #define _EMIFB_CECTL0_FSET(FIELD,f) _EMIFB_CECTL_FSET(0,##FIELD,f) + #define _EMIFB_CECTL1_FSET(FIELD,f) _EMIFB_CECTL_FSET(1,##FIELD,f) + #define _EMIFB_CECTL2_FSET(FIELD,f) _EMIFB_CECTL_FSET(2,##FIELD,f) + #define _EMIFB_CECTL3_FSET(FIELD,f) _EMIFB_CECTL_FSET(3,##FIELD,f) + + #define _EMIFB_CECTL0_FSETS(FIELD,SYM) _EMIFB_CECTL_FSETS(0,##FIELD,##SYM) + #define _EMIFB_CECTL1_FSETS(FIELD,SYM) _EMIFB_CECTL_FSETS(1,##FIELD,##SYM) + #define _EMIFB_CECTL2_FSETS(FIELD,SYM) _EMIFB_CECTL_FSETS(2,##FIELD,##SYM) + #define _EMIFB_CECTL3_FSETS(FIELD,SYM) _EMIFB_CECTL_FSETS(3,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | S D C T L | +* |___________________| +* +* SDCTL - SDRAM control regsiter +* +* FIELDS (msb -> lsb) +* (rw) SDBSZ +* (rw) SDRSZ +* (rw) SDCSZ +* (rw) RFEN +* (w) INIT +* (rw) TRCD +* (rw) TRP +* (rw) TRC +* +\******************************************************************************/ + #define _EMIFB_SDCTL_OFFSET 6 + + #define _EMIFB_SDCTL_ADDR 0x01A80018u + + #define _EMIFB_SDCTL_SDBSZ_MASK 0x40000000u + #define _EMIFB_SDCTL_SDBSZ_SHIFT 0x0000001Eu + #define EMIFB_SDCTL_SDBSZ_DEFAULT 0x00000000u + #define EMIFB_SDCTL_SDBSZ_OF(x) _VALUEOF(x) + #define EMIFB_SDCTL_SDBSZ_2BANKS 0x00000000u + #define EMIFB_SDCTL_SDBSZ_4BANKS 0x00000001u + + #define _EMIFB_SDCTL_SDRSZ_MASK 0x30000000u + #define _EMIFB_SDCTL_SDRSZ_SHIFT 0x0000001Cu + #define EMIFB_SDCTL_SDRSZ_DEFAULT 0x00000000u + #define EMIFB_SDCTL_SDRSZ_OF(x) _VALUEOF(x) + #define EMIFB_SDCTL_SDRSZ_11ROW 0x00000000u + #define EMIFB_SDCTL_SDRSZ_12ROW 0x00000001u + #define EMIFB_SDCTL_SDRSZ_13ROW 0x00000002u + + #define _EMIFB_SDCTL_SDCSZ_MASK 0x0C000000u + #define _EMIFB_SDCTL_SDCSZ_SHIFT 0x0000001Au + #define EMIFB_SDCTL_SDCSZ_DEFAULT 0x00000000u + #define EMIFB_SDCTL_SDCSZ_OF(x) _VALUEOF(x) + #define EMIFB_SDCTL_SDCSZ_9COL 0x00000000u + #define EMIFB_SDCTL_SDCSZ_8COL 0x00000001u + #define EMIFB_SDCTL_SDCSZ_10COL 0x00000002u + + #define _EMIFB_SDCTL_RFEN_MASK 0x02000000u + #define _EMIFB_SDCTL_RFEN_SHIFT 0x00000019u + #define EMIFB_SDCTL_RFEN_DEFAULT 0x00000001u + #define EMIFB_SDCTL_RFEN_OF(x) _VALUEOF(x) + #define EMIFB_SDCTL_RFEN_DISABLE 0x00000000u + #define EMIFB_SDCTL_RFEN_ENABLE 0x00000001u + + #define _EMIFB_SDCTL_INIT_MASK 0x01000000u + #define _EMIFB_SDCTL_INIT_SHIFT 0x00000018u + #define EMIFB_SDCTL_INIT_DEFAULT 0x00000001u + #define EMIFB_SDCTL_INIT_OF(x) _VALUEOF(x) + #define EMIFB_SDCTL_INIT_NO 0x00000000u + #define EMIFB_SDCTL_INIT_YES 0x00000001u + + #define _EMIFB_SDCTL_TRCD_MASK 0x00F00000u + #define _EMIFB_SDCTL_TRCD_SHIFT 0x00000014u + #define EMIFB_SDCTL_TRCD_DEFAULT 0x00000004u + #define EMIFB_SDCTL_TRCD_OF(x) _VALUEOF(x) + + #define _EMIFB_SDCTL_TRP_MASK 0x000F0000u + #define _EMIFB_SDCTL_TRP_SHIFT 0x00000010u + #define EMIFB_SDCTL_TRP_DEFAULT 0x00000008u + #define EMIFB_SDCTL_TRP_OF(x) _VALUEOF(x) + + #define _EMIFB_SDCTL_TRC_MASK 0x0000F000u + #define _EMIFB_SDCTL_TRC_SHIFT 0x0000000Cu + #define EMIFB_SDCTL_TRC_DEFAULT 0x0000000Fu + #define EMIFB_SDCTL_TRC_OF(x) _VALUEOF(x) + + #define EMIFB_SDCTL_OF(x) _VALUEOF(x) + + #define EMIFB_SDCTL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(EMIFB,SDCTL,SDBSZ)\ + |_PER_FDEFAULT(EMIFB,SDCTL,SDRSZ)\ + |_PER_FDEFAULT(EMIFB,SDCTL,SDCSZ)\ + |_PER_FDEFAULT(EMIFB,SDCTL,RFEN)\ + |_PER_FDEFAULT(EMIFB,SDCTL,INIT)\ + |_PER_FDEFAULT(EMIFB,SDCTL,TRCD)\ + |_PER_FDEFAULT(EMIFB,SDCTL,TRP)\ + |_PER_FDEFAULT(EMIFB,SDCTL,TRC)\ + ) + + #define EMIFB_SDCTL_RMK(sdbsz,sdrsz,sdcsz,rfen,init,trcd,trp,trc) (Uint32)(\ + _PER_FMK(EMIFB,SDCTL,SDBSZ,sdbsz)\ + |_PER_FMK(EMIFB,SDCTL,SDRSZ,sdrsz)\ + |_PER_FMK(EMIFB,SDCTL,SDCSZ,sdcsz)\ + |_PER_FMK(EMIFB,SDCTL,RFEN,rfen)\ + |_PER_FMK(EMIFB,SDCTL,INIT,init)\ + |_PER_FMK(EMIFB,SDCTL,TRCD,trcd)\ + |_PER_FMK(EMIFB,SDCTL,TRP,trp)\ + |_PER_FMK(EMIFB,SDCTL,TRC,trc)\ + ) + + #define _EMIFB_SDCTL_FGET(FIELD)\ + _PER_FGET(_EMIFB_SDCTL_ADDR,EMIFB,SDCTL,##FIELD) + + #define _EMIFB_SDCTL_FSET(FIELD,field)\ + _PER_FSET(_EMIFB_SDCTL_ADDR,EMIFB,SDCTL,##FIELD,field) + + #define _EMIFB_SDCTL_FSETS(FIELD,SYM)\ + _PER_FSETS(_EMIFB_SDCTL_ADDR,EMIFB,SDCTL,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | S D T I M | +* |___________________| +* +* SDTIM - SDRAM timing register +* +* FIELDS (msb -> lsb) +* (rw) XRFR +* (r) CNTR +* (rw) PERIOD +* +\******************************************************************************/ + #define _EMIFB_SDTIM_OFFSET 7 + + #define _EMIFB_SDTIM_ADDR 0x01A8001Cu + + #define _EMIFB_SDTIM_XRFR_MASK 0x03000000u + #define _EMIFB_SDTIM_XRFR_SHIFT 0x00000018u + #define EMIFB_SDTIM_XRFR_DEFAULT 0x00000000u + #define EMIFB_SDTIM_XRFR_OF(x) _VALUEOF(x) + + #define _EMIFB_SDTIM_CNTR_MASK 0x00FFF000u + #define _EMIFB_SDTIM_CNTR_SHIFT 0x0000000Cu + #define EMIFB_SDTIM_CNTR_DEFAULT 0x000005DCu + #define EMIFB_SDTIM_CNTR_OF(x) _VALUEOF(x) + + #define _EMIFB_SDTIM_PERIOD_MASK 0x00000FFFu + #define _EMIFB_SDTIM_PERIOD_SHIFT 0x00000000u + #define EMIFB_SDTIM_PERIOD_DEFAULT 0x000005DCu + #define EMIFB_SDTIM_PERIOD_OF(x) _VALUEOF(x) + + #define EMIFB_SDTIM_OF(x) _VALUEOF(x) + + #define EMIFB_SDTIM_DEFAULT (Uint32)( \ + _PER_FDEFAULT(EMIFB,SDTIM,XRFR)\ + |_PER_FDEFAULT(EMIFB,SDTIM,CNTR)\ + |_PER_FDEFAULT(EMIFB,SDTIM,PERIOD)\ + ) + + #define EMIFB_SDTIM_RMK(xrfr,period) (Uint32)(\ + _PER_FMK(EMIFB,SDTIM,XRFR,xrfr)\ + |_PER_FMK(EMIFB,SDTIM,PERIOD,period)\ + ) + + #define _EMIFB_SDTIM_FGET(FIELD)\ + _PER_FGET(_EMIFB_SDTIM_ADDR,EMIFB,SDTIM,##FIELD) + + #define _EMIFB_SDTIM_FSET(FIELD,field)\ + _PER_FSET(_EMIFB_SDTIM_ADDR,EMIFB,SDTIM,##FIELD,field) + + #define _EMIFB_SDTIM_FSETS(FIELD,SYM)\ + _PER_FSETS(_EMIFB_SDTIM_ADDR,EMIFB,SDTIM,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | S D E X T | +* |___________________| +* +* SDEXT - SDRAM extension register +* +* FIELDS (msb -> lsb) +* (rw) WR2RD +* (rw) WR2DEAC +* (rw) WR2WR +* (rw) R2WDQM +* (rw) RD2WR +* (rw) RD2DEAC +* (rw) RD2RD +* (rw) THZP +* (rw) TWR +* (rw) TRRD +* (rw) TRAS +* (rw) TCL +* +\******************************************************************************/ + #define _EMIFB_SDEXT_OFFSET 8 + + #define _EMIFB_SDEXT_ADDR 0x01A80020u + + #define _EMIFB_SDEXT_WR2RD_MASK 0x00100000u + #define _EMIFB_SDEXT_WR2RD_SHIFT 0x00000014u + #define EMIFB_SDEXT_WR2RD_DEFAULT 0x00000001u + #define EMIFB_SDEXT_WR2RD_OF(x) _VALUEOF(x) + + #define _EMIFB_SDEXT_WR2DEAC_MASK 0x000C0000u + #define _EMIFB_SDEXT_WR2DEAC_SHIFT 0x00000012u + #define EMIFB_SDEXT_WR2DEAC_DEFAULT 0x00000001u + #define EMIFB_SDEXT_WR2DEAC_OF(x) _VALUEOF(x) + + #define _EMIFB_SDEXT_WR2WR_MASK 0x00020000u + #define _EMIFB_SDEXT_WR2WR_SHIFT 0x00000011u + #define EMIFB_SDEXT_WR2WR_DEFAULT 0x00000001u + #define EMIFB_SDEXT_WR2WR_OF(x) _VALUEOF(x) + + #define _EMIFB_SDEXT_R2WDQM_MASK 0x00018000u + #define _EMIFB_SDEXT_R2WDQM_SHIFT 0x0000000Fu + #define EMIFB_SDEXT_R2WDQM_DEFAULT 0x00000002u + #define EMIFB_SDEXT_R2WDQM_OF(x) _VALUEOF(x) + + #define _EMIFB_SDEXT_RD2WR_MASK 0x00007000u + #define _EMIFB_SDEXT_RD2WR_SHIFT 0x0000000Cu + #define EMIFB_SDEXT_RD2WR_DEFAULT 0x00000005u + #define EMIFB_SDEXT_RD2WR_OF(x) _VALUEOF(x) + + #define _EMIFB_SDEXT_RD2DEAC_MASK 0x00000C00u + #define _EMIFB_SDEXT_RD2DEAC_SHIFT 0x0000000Au + #define EMIFB_SDEXT_RD2DEAC_DEFAULT 0x00000003u + #define EMIFB_SDEXT_RD2DEAC_OF(x) _VALUEOF(x) + + #define _EMIFB_SDEXT_RD2RD_MASK 0x00000200u + #define _EMIFB_SDEXT_RD2RD_SHIFT 0x00000009u + #define EMIFB_SDEXT_RD2RD_DEFAULT 0x00000001u + #define EMIFB_SDEXT_RD2RD_OF(x) _VALUEOF(x) + + #define _EMIFB_SDEXT_THZP_MASK 0x00000180u + #define _EMIFB_SDEXT_THZP_SHIFT 0x00000007u + #define EMIFB_SDEXT_THZP_DEFAULT 0x00000002u + #define EMIFB_SDEXT_THZP_OF(x) _VALUEOF(x) + + #define _EMIFB_SDEXT_TWR_MASK 0x00000060u + #define _EMIFB_SDEXT_TWR_SHIFT 0x00000005u + #define EMIFB_SDEXT_TWR_DEFAULT 0x00000001u + #define EMIFB_SDEXT_TWR_OF(x) _VALUEOF(x) + + #define _EMIFB_SDEXT_TRRD_MASK 0x00000010u + #define _EMIFB_SDEXT_TRRD_SHIFT 0x00000004u + #define EMIFB_SDEXT_TRRD_DEFAULT 0x00000001u + #define EMIFB_SDEXT_TRRD_OF(x) _VALUEOF(x) + + #define _EMIFB_SDEXT_TRAS_MASK 0x0000000Eu + #define _EMIFB_SDEXT_TRAS_SHIFT 0x00000001u + #define EMIFB_SDEXT_TRAS_DEFAULT 0x00000007u + #define EMIFB_SDEXT_TRAS_OF(x) _VALUEOF(x) + + #define _EMIFB_SDEXT_TCL_MASK 0x00000001u + #define _EMIFB_SDEXT_TCL_SHIFT 0x00000000u + #define EMIFB_SDEXT_TCL_DEFAULT 0x00000001u + #define EMIFB_SDEXT_TCL_OF(x) _VALUEOF(x) + + #define EMIFB_SDEXT_OF(x) _VALUEOF(x) + + #define EMIFB_SDEXT_DEFAULT (Uint32)( \ + _PER_FDEFAULT(EMIFB,SDEXT,WR2RD)\ + |_PER_FDEFAULT(EMIFB,SDEXT,WR2DEAC)\ + |_PER_FDEFAULT(EMIFB,SDEXT,WR2WR)\ + |_PER_FDEFAULT(EMIFB,SDEXT,R2WDQM)\ + |_PER_FDEFAULT(EMIFB,SDEXT,RD2WR)\ + |_PER_FDEFAULT(EMIFB,SDEXT,RD2DEAC)\ + |_PER_FDEFAULT(EMIFB,SDEXT,RD2RD)\ + |_PER_FDEFAULT(EMIFB,SDEXT,THZP)\ + |_PER_FDEFAULT(EMIFB,SDEXT,TWR)\ + |_PER_FDEFAULT(EMIFB,SDEXT,TRRD)\ + |_PER_FDEFAULT(EMIFB,SDEXT,TRAS)\ + |_PER_FDEFAULT(EMIFB,SDEXT,TCL)\ + ) + + #define EMIFB_SDEXT_RMK(wr2rd,wr2deac,wr2wr,r2wdqm,rd2wr,rd2deac,\ + rd2rd,thzp,twr,trrd,tras,tcl) (Uint32)( \ + _PER_FMK(EMIFB,SDEXT,WR2RD,wr2rd)\ + |_PER_FMK(EMIFB,SDEXT,WR2DEAC,wr2deac)\ + |_PER_FMK(EMIFB,SDEXT,WR2WR,wr2wr)\ + |_PER_FMK(EMIFB,SDEXT,R2WDQM,r2wdqm)\ + |_PER_FMK(EMIFB,SDEXT,RD2WR,rd2wr)\ + |_PER_FMK(EMIFB,SDEXT,RD2DEAC,rd2deac)\ + |_PER_FMK(EMIFB,SDEXT,RD2RD,rd2rd)\ + |_PER_FMK(EMIFB,SDEXT,THZP,thzp)\ + |_PER_FMK(EMIFB,SDEXT,TWR,twr)\ + |_PER_FMK(EMIFB,SDEXT,TRRD,trrd)\ + |_PER_FMK(EMIFB,SDEXT,TRAS,tras)\ + |_PER_FMK(EMIFB,SDEXT,TCL,tcl)\ + ) + + #define _EMIFB_SDEXT_FGET(FIELD)\ + _PER_FGET(_EMIFB_SDEXT_ADDR,EMIFB,SDEXT,##FIELD) + + #define _EMIFB_SDEXT_FSET(FIELD,field)\ + _PER_FSET(_EMIFB_SDEXT_ADDR,EMIFB,SDEXT,##FIELD,field) + + #define _EMIFB_SDEXT_FSETS(FIELD,SYM)\ + _PER_FSETS(_EMIFB_SDEXT_ADDR,EMIFB,SDEXT,##FIELD,##SYM) + +/******************************************************************************\ +* _____________________ +* | | +* | C E x S E C | +* |___________________| +* +* CESEC0 - CE space secondary control register 0 +* CESEC1 - CE space secondary control register 1 +* CESEC2 - CE space secondary control register 2 +* CESEC3 - CE space secondary control register 3 +* +* FIELDS (msb -> lsb) +* (rw) SNCCLK +* (rw) RENEN +* (rw) CEEXT +* (rw) SYNCWL +* (rw) SYNCRL +* +\******************************************************************************/ + #define _EMIFB_CESEC0_OFFSET 18 + #define _EMIFB_CESEC1_OFFSET 17 + #define _EMIFB_CESEC2_OFFSET 20 + #define _EMIFB_CESEC3_OFFSET 21 + + #define _EMIFB_CESEC0_ADDR 0x01A80048u + #define _EMIFB_CESEC1_ADDR 0x01A80044u + #define _EMIFB_CESEC2_ADDR 0x01A80050u + #define _EMIFB_CESEC3_ADDR 0x01A80054u + + #define _EMIFB_CESEC_SNCCLK_MASK 0x00000040u + #define _EMIFB_CESEC_SNCCLK_SHIFT 0x00000006u + #define EMIFB_CESEC_SNCCLK_DEFAULT 0x00000000u + #define EMIFB_CESEC_SNCCLK_OF(x) _VALUEOF(x) + #define EMIFB_CESEC_SNCCLK_ECLKOUT1 0x00000000u + #define EMIFB_CESEC_SNCCLK_ECLKOUT2 0x00000001u + + #define _EMIFB_CESEC_RENEN_MASK 0x00000020u + #define _EMIFB_CESEC_RENEN_SHIFT 0x00000005u + #define EMIFB_CESEC_RENEN_DEFAULT 0x00000000u + #define EMIFB_CESEC_RENEN_OF(x) _VALUEOF(x) + #define EMIFB_CESEC_RENEN_ADS 0x00000000u + #define EMIFB_CESEC_RENEN_READ 0x00000001u + + #define _EMIFB_CESEC_CEEXT_MASK 0x00000010u + #define _EMIFB_CESEC_CEEXT_SHIFT 0x00000004u + #define EMIFB_CESEC_CEEXT_DEFAULT 0x00000000u + #define EMIFB_CESEC_CEEXT_OF(x) _VALUEOF(x) + #define EMIFB_CESEC_CEEXT_INACTIVE 0x00000000u + #define EMIFB_CESEC_CEEXT_ACTIVE 0x00000001u + + #define _EMIFB_CESEC_SYNCWL_MASK 0x0000000Cu + #define _EMIFB_CESEC_SYNCWL_SHIFT 0x00000002u + #define EMIFB_CESEC_SYNCWL_DEFAULT 0x00000000u + #define EMIFB_CESEC_SYNCWL_OF(x) _VALUEOF(x) + #define EMIFB_CESEC_SYNCWL_0CYCLE 0x00000000u + #define EMIFB_CESEC_SYNCWL_1CYCLE 0x00000001u + #define EMIFB_CESEC_SYNCWL_2CYCLE 0x00000002u + #define EMIFB_CESEC_SYNCWL_3CYCLE 0x00000003u + + #define _EMIFB_CESEC_SYNCRL_MASK 0x00000003u + #define _EMIFB_CESEC_SYNCRL_SHIFT 0x00000000u + #define EMIFB_CESEC_SYNCRL_DEFAULT 0x00000002u + #define EMIFB_CESEC_SYNCRL_OF(x) _VALUEOF(x) + #define EMIFB_CESEC_SYNCRL_0CYCLE 0x00000000u + #define EMIFB_CESEC_SYNCRL_1CYCLE 0x00000001u + #define EMIFB_CESEC_SYNCRL_2CYCLE 0x00000002u + #define EMIFB_CESEC_SYNCRL_3CYCLE 0x00000003u + + #define EMIFB_CESEC_OF(x) _VALUEOF(x) + + #define EMIFB_CESEC_DEFAULT (Uint32)( \ + _PER_FDEFAULT(EMIFB,CESEC,SNCCLK)\ + |_PER_FDEFAULT(EMIFB,CESEC,RENEN)\ + |_PER_FDEFAULT(EMIFB,CESEC,CEEXT)\ + |_PER_FDEFAULT(EMIFB,CESEC,SYNCWL)\ + |_PER_FDEFAULT(EMIFB,CESEC,SYNCRL)\ + ) + + #define EMIFB_CESEC_RMK(sncclk,renen,ceext,syncwl,syncrl)\ + (Uint32)( \ + _PER_FMK(EMIFB,CESEC,SNCCLK,sncclk)\ + |_PER_FMK(EMIFB,CESEC,RENEN,renen)\ + |_PER_FMK(EMIFB,CESEC,CEEXT,ceext)\ + |_PER_FMK(EMIFB,CESEC,SYNCWL,syncwl)\ + |_PER_FMK(EMIFB,CESEC,SYNCRL,syncrl)\ + ) + + #define _EMIFB_CESEC_FGET(N,FIELD)\ + _PER_FGET(_EMIFB_CESEC##N##_ADDR,EMIFB,CESEC,##FIELD) + + #define _EMIFB_CESEC_FSET(N,FIELD,f)\ + _PER_FSET(_EMIFB_CESEC##N##_ADDR,EMIFB,CESEC,##FIELD,f) + + #define _EMIFB_CESEC_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_EMIFB_CESEC##N##_ADDR,EMIFB,CESEC,##FIELD,##SYM) + + #define _EMIFB_CESEC0_FGET(FIELD) _EMIFB_CESEC_FGET(0,##FIELD) + #define _EMIFB_CESEC1_FGET(FIELD) _EMIFB_CESEC_FGET(1,##FIELD) + #define _EMIFB_CESEC2_FGET(FIELD) _EMIFB_CESEC_FGET(2,##FIELD) + #define _EMIFB_CESEC3_FGET(FIELD) _EMIFB_CESEC_FGET(3,##FIELD) + + #define _EMIFB_CESEC0_FSET(FIELD,f) _EMIFB_CESEC_FSET(0,##FIELD,f) + #define _EMIFB_CESEC1_FSET(FIELD,f) _EMIFB_CESEC_FSET(1,##FIELD,f) + #define _EMIFB_CESEC2_FSET(FIELD,f) _EMIFB_CESEC_FSET(2,##FIELD,f) + #define _EMIFB_CESEC3_FSET(FIELD,f) _EMIFB_CESEC_FSET(3,##FIELD,f) + + #define _EMIFB_CESEC0_FSETS(FIELD,SYM) _EMIFB_CESEC_FSETS(0,##FIELD,##SYM) + #define _EMIFB_CESEC1_FSETS(FIELD,SYM) _EMIFB_CESEC_FSETS(1,##FIELD,##SYM) + #define _EMIFB_CESEC2_FSETS(FIELD,SYM) _EMIFB_CESEC_FSETS(2,##FIELD,##SYM) + #define _EMIFB_CESEC3_FSETS(FIELD,SYM) _EMIFB_CESEC_FSETS(3,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | P D T C T L | +* |___________________| +* +* PDTCTL - Peripheral device transfer (PDT) control +* +* FIELDS (msb -> lsb) +* (rw) PDTWL +* (rw) PDTRL +* +\******************************************************************************/ + #define _EMIFB_PDTCTL_OFFSET 16 + + #define _EMIFB_PDTCTL_ADDR 0x01A80040u + + #define _EMIFB_PDTCTL_PDTWL_MASK 0x0000000Cu + #define _EMIFB_PDTCTL_PDTWL_SHIFT 0x00000002u + #define EMIFB_PDTCTL_PDTWL_DEFAULT 0x00000000u + #define EMIFB_PDTCTL_PDTWL_OF(x) _VALUEOF(x) + #define EMIFB_PDTCTL_PDTWL_0CYCLE 0x00000000u + #define EMIFB_PDTCTL_PDTWL_1CYCLE 0x00000001u + #define EMIFB_PDTCTL_PDTWL_2CYCLE 0x00000002u + #define EMIFB_PDTCTL_PDTWL_3CYCLE 0x00000003u + + #define _EMIFB_PDTCTL_PDTRL_MASK 0x00000003u + #define _EMIFB_PDTCTL_PDTRL_SHIFT 0x00000000u + #define EMIFB_PDTCTL_PDTRL_DEFAULT 0x00000000u + #define EMIFB_PDTCTL_PDTRL_OF(x) _VALUEOF(x) + #define EMIFB_PDTCTL_PDTRL_0CYCLE 0x00000000u + #define EMIFB_PDTCTL_PDTRL_1CYCLE 0x00000001u + #define EMIFB_PDTCTL_PDTRL_2CYCLE 0x00000002u + #define EMIFB_PDTCTL_PDTRL_3CYCLE 0x00000003u + + + #define EMIFB_PDTCTL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(EMIFB,PDTCTL,PDTWL)\ + |_PER_FDEFAULT(EMIFB,PDTCTL,PDTRL)\ + ) + + #define EMIFB_PDTCTL_RMK(pdtwl,pdtrl) (Uint32)( \ + _PER_FMK(EMIFB,PDTCTL,PDTWL,pdtwl)\ + |_PER_FMK(EMIFB,PDTCTL,PDTRL,pdtrl)\ + ) + + #define _EMIFB_PDTCTL_FGET(FIELD)\ + _PER_FGET(_EMIFB_PDTCTL_ADDR,EMIFB,PDTCTL,##FIELD) + + #define _EMIFB_PDTCTL_FSET(FIELD,field)\ + _PER_FSET(_EMIFB_PDTCTL_ADDR,EMIFB,PDTCTL,##FIELD,field) + + #define _EMIFB_PDTCTL_FSETS(FIELD,SYM)\ + _PER_FSETS(_EMIFB_PDTCTL_ADDR,EMIFB,PDTCTL,##FIELD,##SYM) + + + +#endif /* EMIFB_SUPPORT */ + +#endif /* _CSL_EMIFBHAL_H_ */ +/******************************************************************************\ +* End of csl_emifhal.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_emifhal.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_emifhal.h new file mode 100644 index 0000000..7feb20f --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_emifhal.h @@ -0,0 +1,925 @@ +/******************************************************************************\ +* Copyright (C) 1999-2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_emifhal.h +* DATE CREATED.. 06/12/1999 +* LAST MODIFIED. 06/17/2003 Added CHIP_6712C +* 05/28/2003 Added CHIP_6711C +* 10/03/2000 +*------------------------------------------------------------------------------ +* REGISTERS +* +* GBLCTL - global control register +* CECTL0 - CE space control register 0 +* CECTL1 - CE space control register 1 +* CECTL2 - CE space control register 2 +* CECTL3 - CE space control register 3 +* SDCTL - SDRAM control regsiter +* SDTIM - SDRAM timing register +* SDEXT - SDRAM extension register (1) +* +* (1) - only supported on 6211,6711,6712,6713,6711C,6712C +* +\******************************************************************************/ +#ifndef _CSL_EMIFHAL_H_ +#define _CSL_EMIFHAL_H_ + +#include +#include + +#if (EMIF_SUPPORT) +/******************************************************************************\ +* MISC section +\******************************************************************************/ +#define _EMIF_BASE_GLOBAL 0x01800000u + + +/******************************************************************************\ +* module level register/field access macros +\******************************************************************************/ + + /* ----------------- */ + /* FIELD MAKE MACROS */ + /* ----------------- */ + + #define EMIF_FMK(REG,FIELD,x)\ + _PER_FMK(EMIF,##REG,##FIELD,x) + + #define EMIF_FMKS(REG,FIELD,SYM)\ + _PER_FMKS(EMIF,##REG,##FIELD,##SYM) + + + /* -------------------------------- */ + /* RAW REGISTER/FIELD ACCESS MACROS */ + /* -------------------------------- */ + + #define EMIF_ADDR(REG)\ + _EMIF_##REG##_ADDR + + #define EMIF_RGET(REG)\ + _PER_RGET(_EMIF_##REG##_ADDR,EMIF,##REG) + + #define EMIF_RSET(REG,x)\ + _PER_RSET(_EMIF_##REG##_ADDR,EMIF,##REG,x) + + #define EMIF_FGET(REG,FIELD)\ + _EMIF_##REG##_FGET(##FIELD) + + #define EMIF_FSET(REG,FIELD,x)\ + _EMIF_##REG##_FSET(##FIELD,##x) + + #define EMIF_FSETS(REG,FIELD,SYM)\ + _EMIF_##REG##_FSETS(##FIELD,##SYM) + + + /* ------------------------------------------ */ + /* ADDRESS BASED REGISTER/FIELD ACCESS MACROS */ + /* ------------------------------------------ */ + + #define EMIF_RGETA(addr,REG)\ + _PER_RGET(addr,EMIF,##REG) + + #define EMIF_RSETA(addr,REG,x)\ + _PER_RSET(addr,EMIF,##REG,x) + + #define EMIF_FGETA(addr,REG,FIELD)\ + _PER_FGET(addr,EMIF,##REG,##FIELD) + + #define EMIF_FSETA(addr,REG,FIELD,x)\ + _PER_FSET(addr,EMIF,##REG,##FIELD,x) + + #define EMIF_FSETSA(addr,REG,FIELD,SYM)\ + _PER_FSETS(addr,EMIF,##REG,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | G B L C T L | +* |___________________| +* +* GBLCTL - global control register +* +* FIELDS (msb -> lsb) +* (r) BUSREQ (1) +* (r) ARDY +* (r) HOLD +* (r) HOLDA +* (rw) NOHOLD +* (rw) SDCEN (2) +* (rw) SSCEN (2) +* (rw) EKEN (4) +* (rw) CLK1EN +* (rw) CLK2EN (3) +* (rw) SSCRT (2)(3) +* (rw) RBTR8 (2) +* (r) MAP (2) +* +* (1) - Field only exists for C11_SUPPORT +* (2) - Field does not exist for C11_SUPPORT +* (3) - Field does not exist for 6202/6203/6204/6205 +* (4) - Field only exixts for C6713, DA610, 6711C, 6712C +* +\******************************************************************************/ + #define _EMIF_GBLCTL_OFFSET 0 + + #define _EMIF_GBLCTL_ADDR 0x01800000u + +#if (C11_SUPPORT) + #define _EMIF_GBLCTL_BUSREQ_MASK 0x00000800u + #define _EMIF_GBLCTL_BUSREQ_SHIFT 0x0000000Bu + #define EMIF_GBLCTL_BUSREQ_DEFAULT 0x00000000u + #define EMIF_GBLCTL_BUSREQ_OF(x) _VALUEOF(x) + #define EMIF_GBLCTL_BUSREQ_LOW 0x00000000u + #define EMIF_GBLCTL_BUSREQ_HIGH 0x00000001u +#endif + + #define _EMIF_GBLCTL_ARDY_MASK 0x00000400u + #define _EMIF_GBLCTL_ARDY_SHIFT 0x0000000Au + #define EMIF_GBLCTL_ARDY_DEFAULT 0x00000000u + #define EMIF_GBLCTL_ARDY_OF(x) _VALUEOF(x) + #define EMIF_GBLCTL_ARDY_LOW 0x00000000u + #define EMIF_GBLCTL_ARDY_HIGH 0x00000001u + + #define _EMIF_GBLCTL_HOLD_MASK 0x00000200u + #define _EMIF_GBLCTL_HOLD_SHIFT 0x00000009u + #define EMIF_GBLCTL_HOLD_DEFAULT 0x00000000u + #define EMIF_GBLCTL_HOLD_OF(x) _VALUEOF(x) + #define EMIF_GBLCTL_HOLD_LOW 0x00000000u + #define EMIF_GBLCTL_HOLD_HIGH 0x00000001u + + #define _EMIF_GBLCTL_HOLDA_MASK 0x00000100u + #define _EMIF_GBLCTL_HOLDA_SHIFT 0x00000008u + #define EMIF_GBLCTL_HOLDA_DEFAULT 0x00000000u + #define EMIF_GBLCTL_HOLDA_OF(x) _VALUEOF(x) + #define EMIF_GBLCTL_HOLDA_LOW 0x00000000u + #define EMIF_GBLCTL_HOLDA_HIGH 0x00000001u + + #define _EMIF_GBLCTL_NOHOLD_MASK 0x00000080u + #define _EMIF_GBLCTL_NOHOLD_SHIFT 0x00000007u + #define EMIF_GBLCTL_NOHOLD_DEFAULT 0x00000000u + #define EMIF_GBLCTL_NOHOLD_OF(x) _VALUEOF(x) + #define EMIF_GBLCTL_NOHOLD_DISABLE 0x00000000u + #define EMIF_GBLCTL_NOHOLD_ENABLE 0x00000001u + +#if (CHIP_6201 | CHIP_6202 | CHIP_6203 | CHIP_6204 | CHIP_6205 | CHIP_6701) + #define _EMIF_GBLCTL_SDCEN_MASK 0x00000040u + #define _EMIF_GBLCTL_SDCEN_SHIFT 0x00000006u + #define EMIF_GBLCTL_SDCEN_DEFAULT 0x00000001u + #define EMIF_GBLCTL_SDCEN_OF(x) _VALUEOF(x) + #define EMIF_GBLCTL_SDCEN_DISABLE 0x00000000u + #define EMIF_GBLCTL_SDCEN_ENABLE 0x00000001u +#endif + +#if (CHIP_6201 | CHIP_6202 | CHIP_6203 | CHIP_6204 | CHIP_6205 | CHIP_6701) + #define _EMIF_GBLCTL_SSCEN_MASK 0x00000020u + #define _EMIF_GBLCTL_SSCEN_SHIFT 0x00000005u + #define EMIF_GBLCTL_SSCEN_DEFAULT 0x00000001u + #define EMIF_GBLCTL_SSCEN_OF(x) _VALUEOF(x) + #define EMIF_GBLCTL_SSCEN_DISABLE 0x00000000u + #define EMIF_GBLCTL_SSCEN_ENABLE 0x00000001u +#endif + +#if (CHIP_6713 || CHIP_DA610 || CHIP_6711C || CHIP_6712C) + #define _EMIF_GBLCTL_EKEN_MASK 0x00000020u + #define _EMIF_GBLCTL_EKEN_SHIFT 0x00000005u + #define EMIF_GBLCTL_EKEN_DEFAULT 0x00000001u + #define EMIF_GBLCTL_EKEN_OF(x) _VALUEOF(x) + #define EMIF_GBLCTL_EKEN_DISABLE 0x00000000u + #define EMIF_GBLCTL_EKEN_ENABLE 0x00000001u +#endif + + #define _EMIF_GBLCTL_CLK1EN_MASK 0x00000010u + #define _EMIF_GBLCTL_CLK1EN_SHIFT 0x00000004u + +#if (CHIP_6713 || CHIP_DA610) + #define EMIF_GBLCTL_CLK1EN_DEFAULT 0x00000000u +#else + #define EMIF_GBLCTL_CLK1EN_DEFAULT 0x00000001u +#endif + + #define EMIF_GBLCTL_CLK1EN_OF(x) _VALUEOF(x) + #define EMIF_GBLCTL_CLK1EN_DISABLE 0x00000000u + #define EMIF_GBLCTL_CLK1EN_ENABLE 0x00000001u + +#if (!(CHIP_6202|CHIP_6203|CHIP_6204|CHIP_6205)) + #define _EMIF_GBLCTL_CLK2EN_MASK 0x00000008u + #define _EMIF_GBLCTL_CLK2EN_SHIFT 0x00000003u + #define EMIF_GBLCTL_CLK2EN_DEFAULT 0x00000001u + #define EMIF_GBLCTL_CLK2EN_OF(x) _VALUEOF(x) + #define EMIF_GBLCTL_CLK2EN_DISABLE 0x00000000u + #define EMIF_GBLCTL_CLK2EN_ENABLE 0x00000001u +#endif + +#if (CHIP_6201|CHIP_6701) + #define _EMIF_GBLCTL_SSCRT_MASK 0x00000004u + #define _EMIF_GBLCTL_SSCRT_SHIFT 0x00000002u + #define EMIF_GBLCTL_SSCRT_DEFAULT 0x00000000u + #define EMIF_GBLCTL_SSCRT_OF(x) _VALUEOF(x) + #define EMIF_GBLCTL_SSCRT_CPUOVR2 0x00000000u + #define EMIF_GBLCTL_SSCRT_CPU 0x00000001u +#endif + +#if (!C11_SUPPORT) + #define _EMIF_GBLCTL_RBTR8_MASK 0x00000002u + #define _EMIF_GBLCTL_RBTR8_SHIFT 0x00000001u + #define EMIF_GBLCTL_RBTR8_DEFAULT 0x00000000u + #define EMIF_GBLCTL_RBTR8_OF(x) _VALUEOF(x) + #define EMIF_GBLCTL_RBTR8_HPRI 0x00000000u + #define EMIF_GBLCTL_RBTR8_8ACC 0x00000001u +#endif + +#if (!C11_SUPPORT) + #define _EMIF_GBLCTL_MAP_MASK 0x00000001u + #define _EMIF_GBLCTL_MAP_SHIFT 0x00000000u + #define EMIF_GBLCTL_MAP_MAP1 0x00000000u + #define EMIF_GBLCTL_MAP_MAP0 0x00000001u + #define EMIF_GBLCTL_MAP_DEFAULT 0x00000000u + #define EMIF_GBLCTL_MAP_OF(x) _VALUEOF(x) +#endif + + #define EMIF_GBLCTL_OF(x) _VALUEOF(x) + +#if (CHIP_6201|CHIP_6701) + #define EMIF_GBLCTL_DEFAULT (Uint32)( \ + 0x00003000\ + |_PER_FDEFAULT(EMIF,GBLCTL,ARDY)\ + |_PER_FDEFAULT(EMIF,GBLCTL,HOLD)\ + |_PER_FDEFAULT(EMIF,GBLCTL,HOLDA)\ + |_PER_FDEFAULT(EMIF,GBLCTL,NOHOLD)\ + |_PER_FDEFAULT(EMIF,GBLCTL,SDCEN)\ + |_PER_FDEFAULT(EMIF,GBLCTL,SSCEN)\ + |_PER_FDEFAULT(EMIF,GBLCTL,CLK1EN)\ + |_PER_FDEFAULT(EMIF,GBLCTL,CLK2EN)\ + |_PER_FDEFAULT(EMIF,GBLCTL,SSCRT)\ + |_PER_FDEFAULT(EMIF,GBLCTL,RBTR8)\ + |_PER_FDEFAULT(EMIF,GBLCTL,MAP)\ + ) + + #define EMIF_GBLCTL_RMK(nohold,sdcen,sscen,clk1en,clk2en,sscrt,rbtr8) \ + (Uint32)( \ + _PER_FMK(EMIF,GBLCTL,NOHOLD,nohold)\ + |_PER_FMK(EMIF,GBLCTL,SDCEN,sdcen)\ + |_PER_FMK(EMIF,GBLCTL,SSCEN,sscen)\ + |_PER_FMK(EMIF,GBLCTL,CLK1EN,clk1en)\ + |_PER_FMK(EMIF,GBLCTL,CLK2EN,clk2en)\ + |_PER_FMK(EMIF,GBLCTL,SSCRT,sscrt)\ + |_PER_FMK(EMIF,GBLCTL,RBTR8,rbtr8)\ + ) +#endif + +#if (CHIP_6211|CHIP_6711) + #define EMIF_GBLCTL_DEFAULT (Uint32)( \ + 0x00003000\ + |_PER_FDEFAULT(EMIF,GBLCTL,BUSREQ)\ + |_PER_FDEFAULT(EMIF,GBLCTL,ARDY)\ + |_PER_FDEFAULT(EMIF,GBLCTL,HOLD)\ + |_PER_FDEFAULT(EMIF,GBLCTL,HOLDA)\ + |_PER_FDEFAULT(EMIF,GBLCTL,NOHOLD)\ + |_PER_FDEFAULT(EMIF,GBLCTL,CLK1EN)\ + |_PER_FDEFAULT(EMIF,GBLCTL,CLK2EN)\ + ) + + #define EMIF_GBLCTL_RMK(nohold,clk1en,clk2en) (Uint32)( \ + _PER_FMK(EMIF,GBLCTL,NOHOLD,nohold)\ + |_PER_FMK(EMIF,GBLCTL,CLK1EN,clk1en)\ + |_PER_FMK(EMIF,GBLCTL,CLK2EN,clk2en)\ + ) +#endif + +#if (CHIP_6202|CHIP_6203|CHIP_6204|CHIP_6205) + #define EMIF_GBLCTL_DEFAULT (Uint32)( \ + 0x00003008\ + |_PER_FDEFAULT(EMIF,GBLCTL,ARDY)\ + |_PER_FDEFAULT(EMIF,GBLCTL,HOLD)\ + |_PER_FDEFAULT(EMIF,GBLCTL,HOLDA)\ + |_PER_FDEFAULT(EMIF,GBLCTL,NOHOLD)\ + |_PER_FDEFAULT(EMIF,GBLCTL,SDCEN)\ + |_PER_FDEFAULT(EMIF,GBLCTL,SSCEN)\ + |_PER_FDEFAULT(EMIF,GBLCTL,CLK1EN)\ + |_PER_FDEFAULT(EMIF,GBLCTL,RBTR8)\ + |_PER_FDEFAULT(EMIF,GBLCTL,MAP)\ + ) + + #define EMIF_GBLCTL_RMK(nohold,sdcen,sscen,clk1en,rbtr8) (Uint32)( \ + _PER_FMK(EMIF,GBLCTL,NOHOLD,nohold)\ + |_PER_FMK(EMIF,GBLCTL,SDCEN,sdcen)\ + |_PER_FMK(EMIF,GBLCTL,SSCEN,sscen)\ + |_PER_FMK(EMIF,GBLCTL,CLK1EN,clk1en)\ + |_PER_FMK(EMIF,GBLCTL,RBTR8,rbtr8)\ + ) +#endif + +#if (CHIP_6713 || CHIP_DA610 || CHIP_6711C || CHIP_6712C) + #define EMIF_GBLCTL_DEFAULT (Uint32)( \ + 0x00003000\ + |_PER_FDEFAULT(EMIF,GBLCTL,BUSREQ)\ + |_PER_FDEFAULT(EMIF,GBLCTL,ARDY)\ + |_PER_FDEFAULT(EMIF,GBLCTL,HOLD)\ + |_PER_FDEFAULT(EMIF,GBLCTL,HOLDA)\ + |_PER_FDEFAULT(EMIF,GBLCTL,NOHOLD)\ + |_PER_FDEFAULT(EMIF,GBLCTL,EKEN)\ + |_PER_FDEFAULT(EMIF,GBLCTL,CLK1EN)\ + |_PER_FDEFAULT(EMIF,GBLCTL,CLK2EN)\ + ) + + #define EMIF_GBLCTL_RMK(nohold,eken,clk1en,clk2en) (Uint32)( \ + _PER_FMK(EMIF,GBLCTL,NOHOLD,nohold)\ + |_PER_FMK(EMIF,GBLCTL,EKEN,eken)\ + |_PER_FMK(EMIF,GBLCTL,CLK1EN,clk1en)\ + |_PER_FMK(EMIF,GBLCTL,CLK2EN,clk2en)\ + ) +#endif + + #define _EMIF_GBLCTL_FGET(FIELD)\ + _PER_FGET(_EMIF_GBLCTL_ADDR,EMIF,GBLCTL,##FIELD) + + #define _EMIF_GBLCTL_FSET(FIELD,field)\ + _PER_FSET(_EMIF_GBLCTL_ADDR,EMIF,GBLCTL,##FIELD,field) + + #define _EMIF_GBLCTL_FSETS(FIELD,SYM)\ + _PER_FSETS(_EMIF_GBLCTL_ADDR,EMIF,GBLCTL,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | C E C T L | +* |___________________| +* +* CECTL0 - CE space control register 0 +* CECTL1 - CE space control register 1 +* CECTL2 - CE space control register 2 +* CECTL3 - CE space control register 3 +* +* FIELDS (msb -> lsb) +* (rw) WRSETUP +* (rw) WRSTRB +* (rw) WRHLD +* (rw) RDSETUP +* (rw) TA (1) +* (rw) RDSTRB +* (rw) MTYPE +* (rw) WRHLDMSB +* (rw) RDHLD +* +* (1) - Field only exists for C11_SUPPORT +* +* +\******************************************************************************/ + #define _EMIF_CECTL0_OFFSET 2 + #define _EMIF_CECTL1_OFFSET 1 + #define _EMIF_CECTL2_OFFSET 4 + #define _EMIF_CECTL3_OFFSET 5 + + #define _EMIF_CECTL0_ADDR 0x01800008u + #define _EMIF_CECTL1_ADDR 0x01800004u + #define _EMIF_CECTL2_ADDR 0x01800010u + #define _EMIF_CECTL3_ADDR 0x01800014u + + #define _EMIF_CECTL_WRSETUP_MASK 0xF0000000u + #define _EMIF_CECTL_WRSETUP_SHIFT 0x0000001Cu + #define EMIF_CECTL_WRSETUP_DEFAULT 0x0000000Fu + #define EMIF_CECTL_WRSETUP_OF(x) _VALUEOF(x) + + #define _EMIF_CECTL_WRSTRB_MASK 0x0FC00000u + #define _EMIF_CECTL_WRSTRB_SHIFT 0x00000016u + #define EMIF_CECTL_WRSTRB_DEFAULT 0x0000003Fu + #define EMIF_CECTL_WRSTRB_OF(x) _VALUEOF(x) + + #define _EMIF_CECTL_WRHLD_MASK 0x00300000u + #define _EMIF_CECTL_WRHLD_SHIFT 0x00000014u + #define EMIF_CECTL_WRHLD_DEFAULT 0x00000003u + #define EMIF_CECTL_WRHLD_OF(x) _VALUEOF(x) + + #define _EMIF_CECTL_RDSETUP_MASK 0x000F0000u + #define _EMIF_CECTL_RDSETUP_SHIFT 0x00000010u + #define EMIF_CECTL_RDSETUP_DEFAULT 0x0000000Fu + #define EMIF_CECTL_RDSETUP_OF(x) _VALUEOF(x) + +#if (C11_SUPPORT) + #define _EMIF_CECTL_TA_MASK 0x0000C000u + #define _EMIF_CECTL_TA_SHIFT 0x0000000Eu + #define EMIF_CECTL_TA_DEFAULT 0x00000003u + #define EMIF_CECTL_TA_OF(x) _VALUEOF(x) +#endif + + #define _EMIF_CECTL_RDSTRB_MASK 0x00003F00u + #define _EMIF_CECTL_RDSTRB_SHIFT 0x00000008u + #define EMIF_CECTL_RDSTRB_DEFAULT 0x0000003Fu + #define EMIF_CECTL_RDSTRB_OF(x) _VALUEOF(x) + +#if (C11_SUPPORT) + #define _EMIF_CECTL_MTYPE_MASK 0x000000F0u + #define _EMIF_CECTL_MTYPE_SHIFT 0x00000004u + #define EMIF_CECTL_MTYPE_DEFAULT 0x00000002u + #define EMIF_CECTL_MTYPE_OF(x) _VALUEOF(x) + #if (CHIP_6712 || CHIP_6712C) /* 16-bit EMIF */ + #define EMIFB_CECTL_MTYPE_ASYNC8 0x00000000u + #define EMIFB_CECTL_MTYPE_ASYNC16 0x00000001u + #define EMIFB_CECTL_MTYPE_SDRAM8 0x00000008u + #define EMIFB_CECTL_MTYPE_SDRAM16 0x00000009u + #define EMIFB_CECTL_MTYPE_SYNC8 0x0000000Au + #define EMIFB_CECTL_MTYPE_SYNC16 0x0000000Bu + #else /* CHIP_6211/C6711/6711C 32-bit EMIF */ + #define EMIF_CECTL_MTYPE_ASYNC8 0x00000000u + #define EMIF_CECTL_MTYPE_ASYNC16 0x00000001u + #define EMIF_CECTL_MTYPE_ASYNC32 0x00000002u + #define EMIF_CECTL_MTYPE_SDRAM32 0x00000003u + #define EMIF_CECTL_MTYPE_SBSRAM32 0x00000004u + #define EMIF_CECTL_MTYPE_SDRAM8 0x00000008u + #define EMIF_CECTL_MTYPE_SDRAM16 0x00000009u + #define EMIF_CECTL_MTYPE_SBSRAM8 0x0000000Au + #define EMIF_CECTL_MTYPE_SBSRAM16 0x0000000Bu + #endif + +#else + #define _EMIF_CECTL_MTYPE_MASK 0x00000070u + #define _EMIF_CECTL_MTYPE_SHIFT 0x00000004u + #define EMIF_CECTL_MTYPE_DEFAULT 0x00000002u + #define EMIF_CECTL_MTYPE_OF(x) _VALUEOF(x) + #define EMIF_CECTL_MTYPE_ASYNC8 0x00000000u + #define EMIF_CECTL_MTYPE_ASYNC16 0x00000001u + #define EMIF_CECTL_MTYPE_ASYNC32 0x00000002u + #define EMIF_CECTL_MTYPE_SDRAM32 0x00000003u + #define EMIF_CECTL_MTYPE_SBSRAM32 0x00000004u +#endif + + +#if (C11_SUPPORT ) + #define _EMIF_CECTL_RDHLD_MASK 0x00000007u + #define _EMIF_CECTL_RDHLD_SHIFT 0x00000000u + #define EMIF_CECTL_RDHLD_DEFAULT 0x00000003u + #define EMIF_CECTL_RDHLD_OF(x) _VALUEOF(x) +#else + #define _EMIF_CECTL_RDHLD_MASK 0x00000003u + #define _EMIF_CECTL_RDHLD_SHIFT 0x00000000u + #define EMIF_CECTL_RDHLD_DEFAULT 0x00000003u + #define EMIF_CECTL_RDHLD_OF(x) _VALUEOF(x) +#endif + + #define EMIF_CECTL_OF(x) _VALUEOF(x) + +#if (C11_SUPPORT) + #define EMIF_CECTL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(EMIF,CECTL,WRSETUP)\ + |_PER_FDEFAULT(EMIF,CECTL,WRSTRB)\ + |_PER_FDEFAULT(EMIF,CECTL,WRHLD)\ + |_PER_FDEFAULT(EMIF,CECTL,RDSETUP)\ + |_PER_FDEFAULT(EMIF,CECTL,TA)\ + |_PER_FDEFAULT(EMIF,CECTL,RDSTRB)\ + |_PER_FDEFAULT(EMIF,CECTL,MTYPE)\ + |_PER_FDEFAULT(EMIF,CECTL,RDHLD)\ + ) + + #define EMIF_CECTL_RMK(wrsetup,wrstrb,wrhld,rdsetup,ta,rdstrb,mtype,\ + rdhld) (Uint32)( \ + _PER_FMK(EMIF,CECTL,WRSETUP,wrsetup)\ + |_PER_FMK(EMIF,CECTL,WRSTRB,wrstrb)\ + |_PER_FMK(EMIF,CECTL,WRHLD,wrhld)\ + |_PER_FMK(EMIF,CECTL,RDSETUP,rdsetup)\ + |_PER_FMK(EMIF,CECTL,TA,ta)\ + |_PER_FMK(EMIF,CECTL,RDSTRB,rdstrb)\ + |_PER_FMK(EMIF,CECTL,MTYPE,mtype)\ + |_PER_FMK(EMIF,CECTL,RDHLD,rdhld)\ + ) +#endif + + + +#if (!C11_SUPPORT) + #define EMIF_CECTL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(EMIF,CECTL,WRSETUP)\ + |_PER_FDEFAULT(EMIF,CECTL,WRSTRB)\ + |_PER_FDEFAULT(EMIF,CECTL,WRHLD)\ + |_PER_FDEFAULT(EMIF,CECTL,RDSETUP)\ + |_PER_FDEFAULT(EMIF,CECTL,RDSTRB)\ + |_PER_FDEFAULT(EMIF,CECTL,MTYPE)\ + |_PER_FDEFAULT(EMIF,CECTL,RDHLD)\ + ) + + #define EMIF_CECTL_RMK(wrsetup,wrstrb,wrhld,rdsetup,rdstrb,mtype,\ + rdhld) (Uint32)( \ + _PER_FMK(EMIF,CECTL,WRSETUP,wrsetup)\ + |_PER_FMK(EMIF,CECTL,WRSTRB,wrstrb)\ + |_PER_FMK(EMIF,CECTL,WRHLD,wrhld)\ + |_PER_FMK(EMIF,CECTL,RDSETUP,rdsetup)\ + |_PER_FMK(EMIF,CECTL,RDSTRB,rdstrb)\ + |_PER_FMK(EMIF,CECTL,MTYPE,mtype)\ + |_PER_FMK(EMIF,CECTL,RDHLD,rdhld)\ + ) +#endif + + #define _EMIF_CECTL_FGET(N,FIELD)\ + _PER_FGET(_EMIF_CECTL##N##_ADDR,EMIF,CECTL,##FIELD) + + #define _EMIF_CECTL_FSET(N,FIELD,f)\ + _PER_FSET(_EMIF_CECTL##N##_ADDR,EMIF,CECTL,##FIELD,f) + + #define _EMIF_CECTL_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_EMIF_CECTL##N##_ADDR,EMIF,CECTL,##FIELD,##SYM) + + #define _EMIF_CECTL0_FGET(FIELD) _EMIF_CECTL_FGET(0,##FIELD) + #define _EMIF_CECTL1_FGET(FIELD) _EMIF_CECTL_FGET(1,##FIELD) + #define _EMIF_CECTL2_FGET(FIELD) _EMIF_CECTL_FGET(2,##FIELD) + #define _EMIF_CECTL3_FGET(FIELD) _EMIF_CECTL_FGET(3,##FIELD) + + #define _EMIF_CECTL0_FSET(FIELD,f) _EMIF_CECTL_FSET(0,##FIELD,f) + #define _EMIF_CECTL1_FSET(FIELD,f) _EMIF_CECTL_FSET(1,##FIELD,f) + #define _EMIF_CECTL2_FSET(FIELD,f) _EMIF_CECTL_FSET(2,##FIELD,f) + #define _EMIF_CECTL3_FSET(FIELD,f) _EMIF_CECTL_FSET(3,##FIELD,f) + + #define _EMIF_CECTL0_FSETS(FIELD,SYM) _EMIF_CECTL_FSETS(0,##FIELD,##SYM) + #define _EMIF_CECTL1_FSETS(FIELD,SYM) _EMIF_CECTL_FSETS(1,##FIELD,##SYM) + #define _EMIF_CECTL2_FSETS(FIELD,SYM) _EMIF_CECTL_FSETS(2,##FIELD,##SYM) + #define _EMIF_CECTL3_FSETS(FIELD,SYM) _EMIF_CECTL_FSETS(3,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | S D C T L | +* |___________________| +* +* SDCTL - SDRAM control regsiter +* +* FIELDS (msb -> lsb) +* (rw) SDBSZ (2) +* (rw) SDRSZ (2) +* (rw) SDCSZ (2) +* (rw) SDWID (1) +* (rw) RFEN +* (r) INIT +* (rw) TRCD +* (rw) TRP +* (rw) TRC +* +* (1) - Field only exists for C01_SUPPORT +* (2) - Field only exists for C11_SUPPORT +* +\******************************************************************************/ + #define _EMIF_SDCTL_OFFSET 6 + + #define _EMIF_SDCTL_ADDR 0x01800018u + +#if (C11_SUPPORT) + #define _EMIF_SDCTL_SDBSZ_MASK 0x40000000u + #define _EMIF_SDCTL_SDBSZ_SHIFT 0x0000001Eu + #define EMIF_SDCTL_SDBSZ_DEFAULT 0x00000000u + #define EMIF_SDCTL_SDBSZ_OF(x) _VALUEOF(x) + #define EMIF_SDCTL_SDBSZ_2BANKS 0x00000000u + #define EMIF_SDCTL_SDBSZ_4BANKS 0x00000001u +#endif + +#if (C11_SUPPORT) + #define _EMIF_SDCTL_SDRSZ_MASK 0x30000000u + #define _EMIF_SDCTL_SDRSZ_SHIFT 0x0000001Cu + #define EMIF_SDCTL_SDRSZ_DEFAULT 0x00000000u + #define EMIF_SDCTL_SDRSZ_OF(x) _VALUEOF(x) + #define EMIF_SDCTL_SDRSZ_11ROW 0x00000000u + #define EMIF_SDCTL_SDRSZ_12ROW 0x00000001u + #define EMIF_SDCTL_SDRSZ_13ROW 0x00000002u +#endif + +#if (C11_SUPPORT) + #define _EMIF_SDCTL_SDCSZ_MASK 0x0C000000u + #define _EMIF_SDCTL_SDCSZ_SHIFT 0x0000001Au + #define EMIF_SDCTL_SDCSZ_DEFAULT 0x00000000u + #define EMIF_SDCTL_SDCSZ_OF(x) _VALUEOF(x) + #define EMIF_SDCTL_SDCSZ_9COL 0x00000000u + #define EMIF_SDCTL_SDCSZ_8COL 0x00000001u + #define EMIF_SDCTL_SDCSZ_10COL 0x00000002u +#endif + +#if !(C11_SUPPORT) + #define _EMIF_SDCTL_SDWID_MASK 0x04000000u + #define _EMIF_SDCTL_SDWID_SHIFT 0x0000001Au + #define EMIF_SDCTL_SDWID_DEFAULT 0x00000000u + #define EMIF_SDCTL_SDWID_OF(x) _VALUEOF(x) + #define EMIF_SDCTL_SDWID_4X8BIT 0x00000000u + #define EMIF_SDCTL_SDWID_2X16BIT 0x00000001u +#endif + + #define _EMIF_SDCTL_RFEN_MASK 0x02000000u + #define _EMIF_SDCTL_RFEN_SHIFT 0x00000019u + #define EMIF_SDCTL_RFEN_DEFAULT 0x00000001u + #define EMIF_SDCTL_RFEN_OF(x) _VALUEOF(x) + #define EMIF_SDCTL_RFEN_DISABLE 0x00000000u + #define EMIF_SDCTL_RFEN_ENABLE 0x00000001u + + #define _EMIF_SDCTL_INIT_MASK 0x01000000u + #define _EMIF_SDCTL_INIT_SHIFT 0x00000018u + #define EMIF_SDCTL_INIT_DEFAULT 0x00000001u + #define EMIF_SDCTL_INIT_OF(x) _VALUEOF(x) + #define EMIF_SDCTL_INIT_NO 0x00000000u + #define EMIF_SDCTL_INIT_YES 0x00000001u + +#if (C11_SUPPORT) + #define _EMIF_SDCTL_TRCD_MASK 0x00F00000u + #define _EMIF_SDCTL_TRCD_SHIFT 0x00000014u + #define EMIF_SDCTL_TRCD_DEFAULT 0x00000004u + #define EMIF_SDCTL_TRCD_OF(x) _VALUEOF(x) +#else + #define _EMIF_SDCTL_TRCD_MASK 0x00F00000u + #define _EMIF_SDCTL_TRCD_SHIFT 0x00000014u + #define EMIF_SDCTL_TRCD_DEFAULT 0x00000008u + #define EMIF_SDCTL_TRCD_OF(x) _VALUEOF(x) +#endif + + #define _EMIF_SDCTL_TRP_MASK 0x000F0000u + #define _EMIF_SDCTL_TRP_SHIFT 0x00000010u + #define EMIF_SDCTL_TRP_DEFAULT 0x00000008u + #define EMIF_SDCTL_TRP_OF(x) _VALUEOF(x) + + #define _EMIF_SDCTL_TRC_MASK 0x0000F000u + #define _EMIF_SDCTL_TRC_SHIFT 0x0000000Cu + #define EMIF_SDCTL_TRC_DEFAULT 0x0000000Fu + #define EMIF_SDCTL_TRC_OF(x) _VALUEOF(x) + + #define EMIF_SDCTL_OF(x) _VALUEOF(x) + +#if (C11_SUPPORT) + #define EMIF_SDCTL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(EMIF,SDCTL,SDBSZ)\ + |_PER_FDEFAULT(EMIF,SDCTL,SDRSZ)\ + |_PER_FDEFAULT(EMIF,SDCTL,SDCSZ)\ + |_PER_FDEFAULT(EMIF,SDCTL,RFEN)\ + |_PER_FDEFAULT(EMIF,SDCTL,INIT)\ + |_PER_FDEFAULT(EMIF,SDCTL,TRCD)\ + |_PER_FDEFAULT(EMIF,SDCTL,TRP)\ + |_PER_FDEFAULT(EMIF,SDCTL,TRC)\ + ) + + #define EMIF_SDCTL_RMK(sdbsz,sdrsz,sdcsz,rfen,init,trcd,trp,trc) (Uint32)(\ + _PER_FMK(EMIF,SDCTL,SDBSZ,sdbsz)\ + |_PER_FMK(EMIF,SDCTL,SDRSZ,sdrsz)\ + |_PER_FMK(EMIF,SDCTL,SDCSZ,sdcsz)\ + |_PER_FMK(EMIF,SDCTL,RFEN,rfen)\ + |_PER_FMK(EMIF,SDCTL,INIT,init)\ + |_PER_FMK(EMIF,SDCTL,TRCD,trcd)\ + |_PER_FMK(EMIF,SDCTL,TRP,trp)\ + |_PER_FMK(EMIF,SDCTL,TRC,trc)\ + ) +#endif + +#if !(C11_SUPPORT) + #define EMIF_SDCTL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(EMIF,SDCTL,SDWID)\ + |_PER_FDEFAULT(EMIF,SDCTL,RFEN)\ + |_PER_FDEFAULT(EMIF,SDCTL,INIT)\ + |_PER_FDEFAULT(EMIF,SDCTL,TRCD)\ + |_PER_FDEFAULT(EMIF,SDCTL,TRP)\ + |_PER_FDEFAULT(EMIF,SDCTL,TRC)\ + ) + + #define EMIF_SDCTL_RMK(sdwid,rfen,init,trcd,trp,trc) (Uint32)(\ + _PER_FMK(EMIF,SDCTL,SDWID,sdwid)\ + |_PER_FMK(EMIF,SDCTL,RFEN,rfen)\ + |_PER_FMK(EMIF,SDCTL,INIT,init)\ + |_PER_FMK(EMIF,SDCTL,TRCD,trcd)\ + |_PER_FMK(EMIF,SDCTL,TRP,trp)\ + |_PER_FMK(EMIF,SDCTL,TRC,trc)\ + ) +#endif + + #define _EMIF_SDCTL_FGET(FIELD)\ + _PER_FGET(_EMIF_SDCTL_ADDR,EMIF,SDCTL,##FIELD) + + #define _EMIF_SDCTL_FSET(FIELD,field)\ + _PER_FSET(_EMIF_SDCTL_ADDR,EMIF,SDCTL,##FIELD,field) + + #define _EMIF_SDCTL_FSETS(FIELD,SYM)\ + _PER_FSETS(_EMIF_SDCTL_ADDR,EMIF,SDCTL,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | S D T I M | +* |___________________| +* +* SDTIM - SDRAM timing register +* +* FIELDS (msb -> lsb) +* (rw) XRFR (1) +* (r) CNTR +* (rw) PERIOD +* +* (1) - Field only exists for C11_SUPPORT +* +\******************************************************************************/ + #define _EMIF_SDTIM_OFFSET 7 + + #define _EMIF_SDTIM_ADDR 0x0180001Cu + +#if (C11_SUPPORT) + #define _EMIF_SDTIM_XRFR_MASK 0x03000000u + #define _EMIF_SDTIM_XRFR_SHIFT 0x00000018u + #define EMIF_SDTIM_XRFR_DEFAULT 0x00000000u + #define EMIF_SDTIM_XRFR_OF(x) _VALUEOF(x) +#endif + +#if (C11_SUPPORT) + #define _EMIF_SDTIM_CNTR_MASK 0x00FFF000u + #define _EMIF_SDTIM_CNTR_SHIFT 0x0000000Cu + #define EMIF_SDTIM_CNTR_DEFAULT 0x000005DCu + #define EMIF_SDTIM_CNTR_OF(x) _VALUEOF(x) +#else + #define _EMIF_SDTIM_CNTR_MASK 0x00FFF000u + #define _EMIF_SDTIM_CNTR_SHIFT 0x0000000Cu + #define EMIF_SDTIM_CNTR_DEFAULT 0x00000040u + #define EMIF_SDTIM_CNTR_OF(x) _VALUEOF(x) +#endif + +#if (C11_SUPPORT) + #define _EMIF_SDTIM_PERIOD_MASK 0x00000FFFu + #define _EMIF_SDTIM_PERIOD_SHIFT 0x00000000u + #define EMIF_SDTIM_PERIOD_DEFAULT 0x000005DCu + #define EMIF_SDTIM_PERIOD_OF(x) _VALUEOF(x) +#else + #define _EMIF_SDTIM_PERIOD_MASK 0x00000FFFu + #define _EMIF_SDTIM_PERIOD_SHIFT 0x00000000u + #define EMIF_SDTIM_PERIOD_DEFAULT 0x00000040u + #define EMIF_SDTIM_PERIOD_OF(x) _VALUEOF(x) +#endif + + #define EMIF_SDTIM_OF(x) _VALUEOF(x) + +#if (C11_SUPPORT) + #define EMIF_SDTIM_DEFAULT (Uint32)( \ + _PER_FDEFAULT(EMIF,SDTIM,XRFR)\ + |_PER_FDEFAULT(EMIF,SDTIM,CNTR)\ + |_PER_FDEFAULT(EMIF,SDTIM,PERIOD)\ + ) + + #define EMIF_SDTIM_RMK(xrfr,period) (Uint32)(\ + _PER_FMK(EMIF,SDTIM,XRFR,xrfr)\ + |_PER_FMK(EMIF,SDTIM,PERIOD,period)\ + ) +#endif + +#if !(C11_SUPPORT) + #define EMIF_SDTIM_DEFAULT (Uint32)( \ + _PER_FDEFAULT(EMIF,SDTIM,CNTR)\ + |_PER_FDEFAULT(EMIF,SDTIM,PERIOD)\ + ) + + #define EMIF_SDTIM_RMK(period) (Uint32)(\ + _PER_FMK(EMIF,SDTIM,PERIOD,period)\ + ) +#endif + + + #define _EMIF_SDTIM_FGET(FIELD)\ + _PER_FGET(_EMIF_SDTIM_ADDR,EMIF,SDTIM,##FIELD) + + #define _EMIF_SDTIM_FSET(FIELD,field)\ + _PER_FSET(_EMIF_SDTIM_ADDR,EMIF,SDTIM,##FIELD,field) + + #define _EMIF_SDTIM_FSETS(FIELD,SYM)\ + _PER_FSETS(_EMIF_SDTIM_ADDR,EMIF,SDTIM,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | S D E X T | +* |___________________| +* +* SDEXT - SDRAM extension register (1) +* +* (1) - only supported on 6211,6711,6713,DA610,6711C,6712C +* +* FIELDS (msb -> lsb) +* (rw) WR2RD +* (rw) WR2DEAC +* (rw) WR2WR +* (rw) R2WDQM +* (rw) RD2WR +* (rw) RD2DEAC +* (rw) RD2RD +* (rw) THZP +* (rw) TWR +* (rw) TRRD +* (rw) TRAS +* (rw) TCL +* +\******************************************************************************/ +#if (C11_SUPPORT) + #define _EMIF_SDEXT_OFFSET 8 + + #define _EMIF_SDEXT_ADDR 0x01800020u + + #define _EMIF_SDEXT_WR2RD_MASK 0x00100000u + #define _EMIF_SDEXT_WR2RD_SHIFT 0x00000014u + #define EMIF_SDEXT_WR2RD_DEFAULT 0x00000001u + #define EMIF_SDEXT_WR2RD_OF(x) _VALUEOF(x) + + #define _EMIF_SDEXT_WR2DEAC_MASK 0x000C0000u + #define _EMIF_SDEXT_WR2DEAC_SHIFT 0x00000012u + #define EMIF_SDEXT_WR2DEAC_DEFAULT 0x00000001u + #define EMIF_SDEXT_WR2DEAC_OF(x) _VALUEOF(x) + + #define _EMIF_SDEXT_WR2WR_MASK 0x00020000u + #define _EMIF_SDEXT_WR2WR_SHIFT 0x00000011u + #define EMIF_SDEXT_WR2WR_DEFAULT 0x00000001u + #define EMIF_SDEXT_WR2WR_OF(x) _VALUEOF(x) + + #define _EMIF_SDEXT_R2WDQM_MASK 0x00018000u + #define _EMIF_SDEXT_R2WDQM_SHIFT 0x0000000Fu + #define EMIF_SDEXT_R2WDQM_DEFAULT 0x00000003u + #define EMIF_SDEXT_R2WDQM_OF(x) _VALUEOF(x) + + #define _EMIF_SDEXT_RD2WR_MASK 0x00007000u + #define _EMIF_SDEXT_RD2WR_SHIFT 0x0000000Cu + #define EMIF_SDEXT_RD2WR_DEFAULT 0x00000005u + #define EMIF_SDEXT_RD2WR_OF(x) _VALUEOF(x) + + #define _EMIF_SDEXT_RD2DEAC_MASK 0x00000C00u + #define _EMIF_SDEXT_RD2DEAC_SHIFT 0x0000000Au + #define EMIF_SDEXT_RD2DEAC_DEFAULT 0x00000003u + #define EMIF_SDEXT_RD2DEAC_OF(x) _VALUEOF(x) + + #define _EMIF_SDEXT_RD2RD_MASK 0x00000200u + #define _EMIF_SDEXT_RD2RD_SHIFT 0x00000009u + #define EMIF_SDEXT_RD2RD_DEFAULT 0x00000001u + #define EMIF_SDEXT_RD2RD_OF(x) _VALUEOF(x) + + #define _EMIF_SDEXT_THZP_MASK 0x00000180u + #define _EMIF_SDEXT_THZP_SHIFT 0x00000007u + #define EMIF_SDEXT_THZP_DEFAULT 0x00000002u + #define EMIF_SDEXT_THZP_OF(x) _VALUEOF(x) + + #define _EMIF_SDEXT_TWR_MASK 0x00000060u + #define _EMIF_SDEXT_TWR_SHIFT 0x00000005u + #define EMIF_SDEXT_TWR_DEFAULT 0x00000001u + #define EMIF_SDEXT_TWR_OF(x) _VALUEOF(x) + + #define _EMIF_SDEXT_TRRD_MASK 0x00000010u + #define _EMIF_SDEXT_TRRD_SHIFT 0x00000004u + #define EMIF_SDEXT_TRRD_DEFAULT 0x00000001u + #define EMIF_SDEXT_TRRD_OF(x) _VALUEOF(x) + + #define _EMIF_SDEXT_TRAS_MASK 0x0000000Eu + #define _EMIF_SDEXT_TRAS_SHIFT 0x00000001u + #define EMIF_SDEXT_TRAS_DEFAULT 0x00000007u + #define EMIF_SDEXT_TRAS_OF(x) _VALUEOF(x) + + #define _EMIF_SDEXT_TCL_MASK 0x00000001u + #define _EMIF_SDEXT_TCL_SHIFT 0x00000000u + #define EMIF_SDEXT_TCL_DEFAULT 0x00000001u + #define EMIF_SDEXT_TCL_OF(x) _VALUEOF(x) + + #define EMIF_SDEXT_OF(x) _VALUEOF(x) + + #define EMIF_SDEXT_DEFAULT (Uint32)( \ + _PER_FDEFAULT(EMIF,SDEXT,WR2RD)\ + |_PER_FDEFAULT(EMIF,SDEXT,WR2DEAC)\ + |_PER_FDEFAULT(EMIF,SDEXT,WR2WR)\ + |_PER_FDEFAULT(EMIF,SDEXT,R2WDQM)\ + |_PER_FDEFAULT(EMIF,SDEXT,RD2WR)\ + |_PER_FDEFAULT(EMIF,SDEXT,RD2DEAC)\ + |_PER_FDEFAULT(EMIF,SDEXT,RD2RD)\ + |_PER_FDEFAULT(EMIF,SDEXT,THZP)\ + |_PER_FDEFAULT(EMIF,SDEXT,TWR)\ + |_PER_FDEFAULT(EMIF,SDEXT,TRRD)\ + |_PER_FDEFAULT(EMIF,SDEXT,TRAS)\ + |_PER_FDEFAULT(EMIF,SDEXT,TCL)\ + ) + + #define EMIF_SDEXT_RMK(wr2rd,wr2deac,wr2wr,r2wdqm,rd2wr,rd2deac,\ + rd2rd,thzp,twr,trrd,tras,tcl) (Uint32)( \ + _PER_FMK(EMIF,SDEXT,WR2RD,wr2rd)\ + |_PER_FMK(EMIF,SDEXT,WR2DEAC,wr2deac)\ + |_PER_FMK(EMIF,SDEXT,WR2WR,wr2wr)\ + |_PER_FMK(EMIF,SDEXT,R2WDQM,r2wdqm)\ + |_PER_FMK(EMIF,SDEXT,RD2WR,rd2wr)\ + |_PER_FMK(EMIF,SDEXT,RD2DEAC,rd2deac)\ + |_PER_FMK(EMIF,SDEXT,RD2RD,rd2rd)\ + |_PER_FMK(EMIF,SDEXT,THZP,thzp)\ + |_PER_FMK(EMIF,SDEXT,TWR,twr)\ + |_PER_FMK(EMIF,SDEXT,TRRD,trrd)\ + |_PER_FMK(EMIF,SDEXT,TRAS,tras)\ + |_PER_FMK(EMIF,SDEXT,TCL,tcl)\ + ) + + #define _EMIF_SDEXT_FGET(FIELD)\ + _PER_FGET(_EMIF_SDEXT_ADDR,EMIF,SDEXT,##FIELD) + + #define _EMIF_SDEXT_FSET(FIELD,field)\ + _PER_FSET(_EMIF_SDEXT_ADDR,EMIF,SDEXT,##FIELD,field) + + #define _EMIF_SDEXT_FSETS(FIELD,SYM)\ + _PER_FSETS(_EMIF_SDEXT_ADDR,EMIF,SDEXT,##FIELD,##SYM) + +#endif + +/*----------------------------------------------------------------------------*/ + +#endif /* EMIF_SUPPORT */ +#endif /* _CSL_EMIFHAL_H_ */ +/******************************************************************************\ +* End of csl_emifhal.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_emu.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_emu.h new file mode 100644 index 0000000..2189a41 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_emu.h @@ -0,0 +1,132 @@ +/**************************************************************************\ +* Copyright (C) 2002 Texas Instruments Incorporated. +* All Rights Reserved +*-------------------------------------------------------------------------- +* MODULE NAME... EMU +* FILENAME...... csl_emu.h +* DATE CREATED.. 05/12/2003 +* LAST MODIFIED. 05/20/2003 +* PROJECT....... Chip Support Library +* COMPONENT..... Service Layer +* PREREQUISITES. +\**************************************************************************/ +/**************************************************************************\ +* Private Macros - Include files - EMU_SUPPORT +\**************************************************************************/ +#ifndef _CSL_EMU_H_ +#define _CSL_EMU_H_ + +#include +#include + +#if (EMU_SUPPORT) + +/**************************************************************************\ +* EMU scope and inline control macros +\**************************************************************************/ + +#ifdef __cplusplus +# define CSLAPI extern "C" far +#else +# define CSLAPI extern far +#endif + +#undef USEDEFS +#undef IDECL +#undef IDEF + +#ifdef _EMU_MOD_ +# define IDECL CSLAPI +# define USEDEFS +# define IDEF +#else +# ifdef _INLINE +# define IDECL static inline +# define USEDEFS +# define IDEF static inline +# else +# define IDECL CSLAPI +# endif +#endif + +/**************************************************************************\ +* EMU global macro declarations +\**************************************************************************/ + +#define EMU_DEVICE_CNT (1) /* The number of EMU devices */ + +#define EMU_SUCCESS (1) + +#define EMU_FAILURE (0) + +/**************************************************************************\ +* EMU global typedef declarations +\**************************************************************************/ +/**************************************************************************\ +* EMU global function declarations +\**************************************************************************/ + +CSLAPI Uint32 EMU_setDBGM( + void +); + + +CSLAPI Uint32 EMU_clrDBGM( + void +); + + +CSLAPI Uint32 EMU_getDBGM( + void +); + + +CSLAPI void EMU_setABORTI( + void +); + + +CSLAPI void EMU_clrABORTI( + void +); + + +CSLAPI Uint32 EMU_setEALLOW( + void +); + + +CSLAPI Uint32 EMU_clrEALLOW( + void +); + + +CSLAPI Uint32 EMU_getEALLOW( + void +); + + +CSLAPI Uint32 EMU_getDBGSTAT( + void +); + +/**************************************************************************\ +* EMU inline function declarations +\**************************************************************************/ +/**************************************************************************\ +* EMU inline function declarations +\**************************************************************************/ + +#ifdef USEDEFS + +#endif /*USEDEFS */ + + + +#endif /* EMU_SUPPORT */ + +#endif /* _CSL_EMUHAL_H */ + +/**************************************************************************\ +* End of csl_emu.h +\**************************************************************************/ diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_emuhal.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_emuhal.h new file mode 100644 index 0000000..8799257 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_emuhal.h @@ -0,0 +1,202 @@ +/**************************************************************************\ +* Copyright (C) 2002 Texas Instruments Incorporated. +* All Rights Reserved +*-------------------------------------------------------------------------- +* MODULE NAME... EMU +* FILENAME...... csl_emuhal.h +* DATE CREATED.. 05/12/2003 +* LAST MODIFIED. 05/20/2003 +* PROJECT....... Chip Support Library +* COMPONENT..... Hardware Abstraction Layer +* PREREQUISITES. +* +*-------------------------------------------------------------------------- +* DESCRIPTION: +* CSL Hardware Abstraction Layer interface for the EMU module +* +*-------------------------------------------------------------------------- +* REGISTERS: +* +* DBGSTAT - DBGSTAT {Debug Status Register} +* MFREG0 - MFREG0 {Miscellaneous Function Register} +\**************************************************************************/ + +#ifndef _CSL_EMUHAL_H_ +#define _CSL_EMUHAL_H_ + +/**************************************************************************\ +* Private Macros and Include files +\**************************************************************************/ +#include +#include + +#if (EMU_SUPPORT) + + +/**************************************************************************\ +* Module level register/field access macros +\**************************************************************************/ + + /* ----------------- */ + /* FIELD MAKE MACROS */ + /* ----------------- */ + #define EMU_FMK(REG, FIELD, x) \ + _PER_FMK(EMU, ##REG, ##FIELD, x) + #define EMU_FMKS(REG, FIELD, SYM) \ + _PER_FMKS(EMU, ##REG, ##FIELD, ##SYM) + + /* -------------------------------- */ + /* RAW REGISTER/FIELD ACCESS MACROS */ + /* -------------------------------- */ + #define EMU_ADDR(REG) _EMU_##REG##_ADDR + #define EMU_RGET(REG) \ + _PER_RGET(_EMU_##REG##_ADDR, EMU, ##REG) + #define EMU_RSET(REG, x) \ + _PER_RSET(_EMU_##REG##_ADDR, EMU, ##REG, x) + #define EMU_FGET(REG, FLD) _EMU_##REG##_FGET(##FLD) + #define EMU_FSET(REG, FLD, x) _EMU_##REG##_FSET(##FLD, x) + #define EMU_FSETS(REG, FLD, SYM) \ + _EMU_##REG##_FSETS(##FLD, ##SYM) + + /* ------------------------------------------ */ + /* ADDRESS BASED REGISTER/FIELD ACCESS MACROS */ + /* ------------------------------------------ */ + #define EMU_RGETA(addr, REG) _PER_RGET(addr, EMU, ##REG) + #define EMU_RSETA(addr, REG, x) _PER_RSET(addr, EMU, ##REG,x) + #define EMU_FGETA(addr, REG, FLD) \ + _PER_FGET(addr, EMU, ##REG,##FLD) + #define EMU_FSETA(addr, REG, FLD, x) \ + _PER_FSET(addr, EMU, ##REG, ##FLD, x) + #define EMU_FSETSA(addr, REG, FLD, SYM) \ + _PER_FSETS(addr, EMU, ##REG, ##FLD, ##SYM) + + /* ----------------------------------------- */ + /* HANDLE BASED REGISTER/FIELD ACCESS MACROS */ + /* ----------------------------------------- */ + #define EMU_ADDRH(h, REG) \ + ((void *)(&(((EMU_PrivateObj *)h)->baseAddr[_EMU_##REG##_OFFSET]))) + #define EMU_RGETH(h, REG) \ + EMU_RGETA(EMU_ADDRH(h, ##REG), ##REG) + #define EMU_RSETH(h, REG, x) \ + EMU_RSETA(EMU_ADDRH(h, ##REG), ##REG, x) + #define EMU_FGETH(h, REG, FIELD) \ + EMU_FGETA(EMU_ADDRH(h, ##REG), ##REG, ##FIELD) + #define EMU_FSETH(h, REG, FIELD,x) \ + EMU_FSETA(EMU_ADDRH(h, ##REG), ##REG, ##FIELD, x) + #define EMU_FSETSH(h, REG, FIELD, SYM) \ + EMU_FSETSA(EMU_ADDRH(h, ##REG), ##REG, ##FIELD, ##SYM) + + +/**************************************************************************\ +* +* _____________________ +* | | +* | D B G S T A T | +* |___________________| +* +* DBGSTAT - DBGSTAT {Debug Status Register} +* +* FIELDS (msb -> lsb) +* (r) DBGMST Read MFREG0:DBGM state +* (r) EALLOWST Read MFREG0:EALLOW state +\**************************************************************************/ + + #define _EMU_DBGSTAT_ADDR (0x01BC0000) + #define _EMU_DBGSTAT (*(Uint32 *)_EMU_DBGSTAT_ADDR) + + #define _EMU_DBGSTAT_DBGMST_MASK (0x00020000u) + #define _EMU_DBGSTAT_DBGMST_SHIFT (0x00000011u) + + #define EMU_DBGSTAT_DBGMST_OF(x) _VALUEOF(x) + + #define _EMU_DBGSTAT_EALLOWST_MASK \ + (0x00010000u) + #define _EMU_DBGSTAT_EALLOWST_SHIFT \ + (0x00000010u) + #define EMU_DBGSTAT_EALLOWST_OF(x) \ + _VALUEOF(x) + + #define EMU_DBGSTAT_OF(x) _VALUEOF(x) + + + #define _EMU_DBGSTAT_FGET(FLD) \ + _PER_FGET(_EMU_DBGSTAT_ADDR, EMU, DBGSTAT, ##FLD) + #define _EMU_DBGSTAT_FSET(FLD, f) \ + _PER_FSET(_EMU_DBGSTAT_ADDR, EMU, DBGSTAT, ##FLD,f) + #define _EMU_DBGSTAT_FSETS(FLD, SYM) \ + _PER_FSETS(_EMU_DBGSTAT_ADDR, EMU, DBGSTAT, ##FLD, ##SYM) + + +/**************************************************************************\ +* +* _____________________ +* | | +* | M F R E G 0 | +* |___________________| +* +* MFREG0 - MFREG0 {Miscellaneous Function Register} +* +* FIELDS (msb -> lsb) +* (w) DBGMLD Load qualifier for the DBGM bit +* (w) DBGM Set a mask to inhibit debug access +* (w) ABRTILD Load qualifier for the ABORTI bit +* (w) ABRTI set the bit to ABORT a lost ISR +* (w) EALLOWLD Load qualifier for the EALLOW bit +* (w) EALLOW Set the bit to allow Emulation access +\**************************************************************************/ + + #define _EMU_MFREG0_ADDR (0x01BC0014) + #define _EMU_MFREG0 (*(Uint32 *)_EMU_MFREG0_ADDR) + + #define _EMU_MFREG0_DBGMLD_MASK (0x08000000u) + #define _EMU_MFREG0_DBGMLD_SHIFT (0x0000001Bu) + #define EMU_MFREG0_DBGMLD_OF(x) _VALUEOF(x) + + #define _EMU_MFREG0_DBGM_MASK (0x04000000u) + #define _EMU_MFREG0_DBGM_SHIFT (0x0000001Au) + #define EMU_MFREG0_DBGM_OF(x) _VALUEOF(x) + + #define _EMU_MFREG0_ABRTILD_MASK (0x00040000u) + #define _EMU_MFREG0_ABRTILD_SHIFT (0x00000012u) + #define EMU_MFREG0_ABRTILD_OF(x) _VALUEOF(x) + + #define _EMU_MFREG0_ABRTI_MASK (0x00020000u) + #define _EMU_MFREG0_ABRTI_SHIFT (0x00000011u) + #define EMU_MFREG0_ABRTI_OF(x) _VALUEOF(x) + + #define _EMU_MFREG0_EALLOWLD_MASK (0x00004000u) + #define _EMU_MFREG0_EALLOWLD_SHIFT \ + (0x0000000Eu) + #define EMU_MFREG0_EALLOWLD_OF(x) _VALUEOF(x) + + #define _EMU_MFREG0_EALLOW_MASK (0x00002000u) + #define _EMU_MFREG0_EALLOW_SHIFT (0x0000000Du) + #define EMU_MFREG0_EALLOW_OF(x) _VALUEOF(x) + + #define EMU_MFREG0_OF(x) _VALUEOF(x) + + #define EMU_MFREG0_RMK(dbgmld, dbgm, abrtild, abrti, eallowld, eallow) ((Uint32) (\ + _PER_FMK(EMU, MFREG0, DBGMLD, dbgmld) \ + |_PER_FMK(EMU, MFREG0, DBGM, dbgm) \ + |_PER_FMK(EMU, MFREG0, ABRTILD, abrtild) \ + |_PER_FMK(EMU, MFREG0, ABRTI, abrti) \ + |_PER_FMK(EMU, MFREG0, EALLOWLD, eallowld) \ + |_PER_FMK(EMU, MFREG0, EALLOW, eallow) \ + ) \ + ) + + #define _EMU_MFREG0_FGET(FLD) \ + _PER_FGET(_EMU_MFREG0_ADDR, EMU, MFREG0, ##FLD) + #define _EMU_MFREG0_FSET(FLD, f) \ + _PER_FSET(_EMU_MFREG0_ADDR, EMU, MFREG0, ##FLD,f) + #define _EMU_MFREG0_FSETS(FLD, SYM) \ + _PER_FSETS(_EMU_MFREG0_ADDR, EMU, MFREG0, ##FLD, ##SYM) + + + +#endif /* (EMU_SUPPORT) */ +#endif /* _CSL_EMUHAL_H_ */ + +/**************************************************************************\ +* End of csl_emuhal.h +\**************************************************************************/ diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_gpio.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_gpio.h new file mode 100644 index 0000000..ddbaa43 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_gpio.h @@ -0,0 +1,401 @@ +/******************************************************************************\ +* Copyright (C) 2000-2001 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_gpio.h +* DATE CREATED.. 12/04/2000 +* LAST MODIFIED. 05/09/2001 +\******************************************************************************/ + +#ifndef _CSL_GPIO_H_ +#define _CSL_GPIO_H_ + +#include +#include +#include +#include "csl_gpiohal.h" + + +#if (GPIO_SUPPORT) +/******************************************************************************\ +* scope and inline control macros +\******************************************************************************/ +#ifdef __cplusplus +#define CSLAPI extern "C" far +#else +#define CSLAPI extern far +#endif + +#undef USEDEFS +#undef IDECL +#undef IDEF + +#ifdef _GPIO_MOD_ + #define IDECL CSLAPI + #define USEDEFS + #define IDEF +#else + #ifdef _INLINE + #define IDECL static inline + #define USEDEFS + #define IDEF static inline + #else + #define IDECL CSLAPI + #endif +#endif + +/******************************************************************************\ +* global macro declarations +\******************************************************************************/ + +/* Macro define devices */ +#define GPIO_DEV0 0 +#if CHIP_DA610 +#define GPIO_DEV1 1 +#endif + +/* misc global settings */ +#define GPIO_INT_CNT 5 +#define GPIO_PIN_CNT 32 +#define GPIO_OPEN_RESET 1 + + +/* Pin id definitions */ +#define GPIO_PIN0 0x00000001u +#define GPIO_PIN1 0x00000002u +#define GPIO_PIN2 0x00000004u +#define GPIO_PIN3 0x00000008u +#define GPIO_PIN4 0x00000010u +#define GPIO_PIN5 0x00000020u +#define GPIO_PIN6 0x00000040u +#define GPIO_PIN7 0x00000080u +#define GPIO_PIN8 0x00000100u +#define GPIO_PIN9 0x00000200u +#define GPIO_PIN10 0x00000400u +#define GPIO_PIN11 0x00000800u +#define GPIO_PIN12 0x00001000u +#define GPIO_PIN13 0x00002000u +#define GPIO_PIN14 0x00004000u +#define GPIO_PIN15 0x00008000u +#define GPIO_PIN16 0x00010000u +#define GPIO_PIN17 0x00020000u +#define GPIO_PIN18 0x00040000u +#define GPIO_PIN19 0x00080000u +#define GPIO_PIN20 0x00100000u +#define GPIO_PIN21 0x00200000u +#define GPIO_PIN22 0x00400000u +#define GPIO_PIN23 0x00800000u +#define GPIO_PIN24 0x01000000u +#define GPIO_PIN25 0x02000000u +#define GPIO_PIN26 0x04000000u +#define GPIO_PIN27 0x08000000u +#define GPIO_PIN28 0x10000000u +#define GPIO_PIN29 0x20000000u +#define GPIO_PIN30 0x40000000u +#define GPIO_PIN31 0x80000000u + +/* CPU Interrupt Pins for GPIO0 only */ + +#define GPIO_GPINT0 0 +#define GPIO_GPINT4 1 +#define GPIO_GPINT5 2 +#define GPIO_GPINT6 3 +#define GPIO_GPINT7 4 + +/* Interrupt Polarity */ +#define GPIO_RISING 0 +#define GPIO_FALLING 1 + +/* Pin Direction */ +#define GPIO_INPUT 0 +#define GPIO_OUTPUT 1 + +/* GPIO masks */ +#define GPIO_MASK_NA 0x00000000u +#define GPIO_MASK_00 0x00000001u +#define GPIO_MASK_01 0x00000002u +#define GPIO_MASK_02 0x00000004u +#define GPIO_MASK_03 0x00000008u +#define GPIO_MASK_04 0x00000010u +#define GPIO_MASK_05 0x00000020u +#define GPIO_MASK_06 0x00000040u +#define GPIO_MASK_07 0x00000080u +#define GPIO_MASK_08 0x00000100u +#define GPIO_MASK_09 0x00000200u +#define GPIO_MASK_10 0x00000400u +#define GPIO_MASK_11 0x00000800u +#define GPIO_MASK_12 0x00001000u +#define GPIO_MASK_13 0x00002000u +#define GPIO_MASK_14 0x00004000u +#define GPIO_MASK_15 0x00008000u + +/*****************************************************************************\ +* global typedef declarations +\******************************************************************************/ + typedef struct { + Uint32 gpgc; + Uint32 gpen; + Uint32 gpdir; + Uint32 gpval; + Uint32 gphm; + Uint32 gplm; + Uint32 gppol; + } GPIO_Config; + +/* device handle object */ +typedef struct { + Uint32 allocated; + volatile Uint32 *baseAddr; + Uint32 pinAllocMask; +} GPIO_Obj, *GPIO_Handle; + + +/******************************************************************************\ +* global variable declarations +\******************************************************************************/ +//extern far Uint32 _GPIO_pinTable[GPIO_PIN_CNT]; +extern far Uint32 _GPIO_intTable[GPIO_INT_CNT]; +extern far GPIO_Handle _hGpioDev0; + +/******************************************************************************\ +* global function declarations +\******************************************************************************/ + +/* private functions */ +/* API functions (Non-Inline function : Source file) */ +CSLAPI GPIO_Handle GPIO_open(int devnum, Uint32 flags); +CSLAPI void GPIO_close(GPIO_Handle hGpio); +CSLAPI void GPIO_reset(GPIO_Handle hGpio); +CSLAPI void GPIO_clear(GPIO_Handle hGpio); + + +/******************************************************************************\ +* inline function declarations +\******************************************************************************/ +/* configuration */ + +IDECL void GPIO_config(GPIO_Handle hGpio, GPIO_Config *config); +IDECL void GPIO_configArgs(GPIO_Handle hGpio,Uint32 gpgc,Uint32 gpen, Uint32 gpdir,Uint32 gpval, + Uint32 gphm, Uint32 gplm, Uint32 gppol); +IDECL void GPIO_getConfig(GPIO_Handle hGpio, GPIO_Config *config); + + +IDECL void GPIO_pinDisable(GPIO_Handle hGpio, Uint32 pinId); +IDECL void GPIO_pinEnable(GPIO_Handle hGpio,Uint32 pinId); + +IDECL Uint32 GPIO_pinDirection(GPIO_Handle hGpio, Uint32 pinId, Uint32 direction); +IDECL Uint32 GPIO_pinRead(GPIO_Handle hGpio,Uint32 pinId); +IDECL Uint32 GPIO_read(GPIO_Handle hGpio, Uint32 pinMask); + + +/* For output Pins */ +IDECL void GPIO_pinWrite(GPIO_Handle hGpio,Uint32 pinId, Uint32 val); +IDECL void GPIO_write(GPIO_Handle hGpio, Uint32 pinMask, Uint32 val); + + +/* For input Pins */ +IDECL Uint32 GPIO_deltaHighGet(GPIO_Handle hGpio,Uint32 pinId); +IDECL void GPIO_deltaHighClear(GPIO_Handle hGpio,Uint32 pinId); +IDECL Uint32 GPIO_deltaLowGet(GPIO_Handle hGpio,Uint32 pinId); +IDECL void GPIO_deltaLowClear(GPIO_Handle hGpio,Uint32 pinId); + +IDECL void GPIO_maskHighSet(GPIO_Handle hGpio,Uint32 pinId); +IDECL void GPIO_maskHighClear(GPIO_Handle hGpio,Uint32 pinId); +IDECL void GPIO_maskLowSet(GPIO_Handle hGpio,Uint32 pinId); +IDECL void GPIO_maskLowClear(GPIO_Handle hGpio,Uint32 pinId); + + +/* Pass Through Mode */ +IDECL Uint32 GPIO_intPolarity(GPIO_Handle hGpio,Uint32 signal, Uint32 polarity); + + +/******************************************************************************\ +* inline function definitions +\******************************************************************************/ +#ifdef USEDEFS +/*----------------------------------------------------------------------------*/ +IDEF void GPIO_pinEnable(GPIO_Handle hGpio,Uint32 pinId) { + Uint32 gpen = GPIO_RGETH(hGpio,GPEN); + gpen = gpen | (pinId & hGpio->pinAllocMask); + GPIO_FSETH(hGpio,GPEN,GPXEN,gpen); +} +/*----------------------------------------------------------------------------*/ +IDEF void GPIO_pinDisable(GPIO_Handle hGpio,Uint32 pinId) { + Uint32 gpen = GPIO_RGETH(hGpio,GPEN); + gpen = gpen & (~pinId & hGpio->pinAllocMask); + GPIO_FSETH(hGpio,GPEN,GPXEN,gpen); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 GPIO_pinDirection(GPIO_Handle hGpio,Uint32 pinId, Uint32 direction) { + Uint32 gpdir = GPIO_RGETH(hGpio,GPDIR); + if ( direction == 0) { + GPIO_RSETH(hGpio,GPDIR,(gpdir & (~pinId & hGpio->pinAllocMask))); + } else { + GPIO_RSETH(hGpio,GPDIR,(gpdir | (pinId & hGpio->pinAllocMask))); + } + return ( GPIO_RGETH(hGpio,GPDIR)); + +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 GPIO_pinRead(GPIO_Handle hGpio,Uint32 pinId) { +Uint32 x = 0xFFFFFFFF; + + if ( (GPIO_RGETH(hGpio,GPVAL) & (pinId & hGpio->pinAllocMask))!= 0 ) { + x = 1; + } else { + x = 0; + } + + return ( x ); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 GPIO_read(GPIO_Handle hGpio, Uint32 pinMask) +{ + return ((GPIO_RGETH(hGpio,GPVAL) & pinMask) & hGpio->pinAllocMask); +} +/*----------------------------------------------------------------------------*/ +IDEF void GPIO_pinWrite(GPIO_Handle hGpio,Uint32 pinId, Uint32 val) { + Uint32 gpval = GPIO_RGETH(hGpio,GPVAL); + if ( val == 0) { + GPIO_RSETH(hGpio,GPVAL,(gpval & (~pinId & hGpio->pinAllocMask))); + } else { + GPIO_RSETH(hGpio,GPVAL,(gpval | (pinId & hGpio->pinAllocMask))); + } + +} +/*----------------------------------------------------------------------------*/ +IDEF void GPIO_write(GPIO_Handle hGpio, Uint32 pinMask, Uint32 val) +{ + Uint32 gpval = GPIO_RGETH(hGpio,GPVAL); + GPIO_RSETH(hGpio,GPVAL, ((gpval & ~pinMask) | (pinMask & val))); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 GPIO_deltaHighGet(GPIO_Handle hGpio,Uint32 pinId) { + return (GPIO_FGETH(hGpio,GPDH,GPXDH)& (pinId & hGpio->pinAllocMask)); +} +/*----------------------------------------------------------------------------*/ +IDEF void GPIO_deltaHighClear(GPIO_Handle hGpio,Uint32 pinId) { + Uint32 gpdh= GPIO_RGETH(hGpio,GPDH); + GPIO_FSETH(hGpio,GPDH,GPXDH,(gpdh & (pinId & hGpio->pinAllocMask))); + +} +/*----------------------------------------------------------------------------*/ + IDEF Uint32 GPIO_deltaLowGet(GPIO_Handle hGpio,Uint32 pinId) { + return (GPIO_FGETH(hGpio,GPDL,GPXDL)& (pinId & hGpio->pinAllocMask)); +} +/*----------------------------------------------------------------------------*/ + IDEF void GPIO_deltaLowClear(GPIO_Handle hGpio,Uint32 pinId) { + Uint32 gpdl= GPIO_RGETH(hGpio,GPDL); + GPIO_FSETH(hGpio,GPDL,GPXDL,(gpdl & (pinId & hGpio->pinAllocMask))); +} +/*----------------------------------------------------------------------------*/ +IDEF void GPIO_maskHighSet(GPIO_Handle hGpio,Uint32 pinId) { + Uint32 gphm = GPIO_RGETH(hGpio,GPHM); + GPIO_FSETH(hGpio,GPHM,GPXHM,(gphm | (pinId & hGpio->pinAllocMask))); +} +/*----------------------------------------------------------------------------*/ +IDEF void GPIO_maskHighClear(GPIO_Handle hGpio,Uint32 pinId) { + Uint32 gphm = GPIO_RGETH(hGpio,GPHM); + GPIO_FSETH(hGpio,GPHM,GPXHM,(gphm & (~pinId & hGpio->pinAllocMask))); +} +/*----------------------------------------------------------------------------*/ +IDEF void GPIO_maskLowSet(GPIO_Handle hGpio,Uint32 pinId) { + Uint32 gplm = GPIO_RGETH(hGpio,GPLM); + GPIO_FSETH(hGpio,GPLM,GPXLM,(gplm | (pinId & hGpio->pinAllocMask))); +} +/*----------------------------------------------------------------------------*/ +IDEF void GPIO_maskLowClear(GPIO_Handle hGpio,Uint32 pinId) { + Uint32 gplm = GPIO_RGETH(hGpio,GPLM); + GPIO_FSETH(hGpio,GPLM,GPXLM,(gplm & (~pinId & hGpio->pinAllocMask))); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 GPIO_intPolarity(GPIO_Handle hGpio,Uint32 signal, Uint32 polarity){ + Uint32 gppol = GPIO_RGETH(hGpio,GPPOL); + if ( polarity == 0) { + GPIO_FSETH(hGpio,GPPOL,GPINTXPOL,(gppol & ~_GPIO_intTable[signal])); + } else { + GPIO_FSETH(hGpio,GPPOL,GPINTXPOL,(gppol | _GPIO_intTable[signal])); + } + return ( GPIO_RGETH(hGpio,GPPOL)); +} +/*----------------------------------------------------------------------------*/ +IDEF void GPIO_config(GPIO_Handle hGpio,GPIO_Config *config) { + Uint32 gie; + register int x0,x1,x2,x3,x4,x5,x6; + volatile Uint32 *base = (volatile Uint32 *)(hGpio->baseAddr); + + gie = IRQ_globalDisable(); + + x0 = config->gpgc; + x1 = config->gpen; + x2 = config->gpdir; + x3 = config->gpval; + x4 = config->gphm; + x5 = config->gplm; + x6 = config->gppol; + + base[_GPIO_GPGC_OFFSET] = x0; + base[_GPIO_GPEN_OFFSET] = x1; + base[_GPIO_GPDIR_OFFSET]= x2; + base[_GPIO_GPVAL_OFFSET]= x3; + base[_GPIO_GPHM_OFFSET] = x4; + base[_GPIO_GPLM_OFFSET] = x5; + base[_GPIO_GPPOL_OFFSET]= x6; + + IRQ_globalRestore(gie); +} +/*----------------------------------------------------------------------------*/ +IDEF void GPIO_configArgs(GPIO_Handle hGpio, Uint32 gpgc,Uint32 gpen, Uint32 gpdir,Uint32 gpval, + Uint32 gphm, Uint32 gplm, Uint32 gppol) { + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)(hGpio->baseAddr); + + gie = IRQ_globalDisable(); + + base[_GPIO_GPGC_OFFSET] = gpgc; + base[_GPIO_GPEN_OFFSET] = gpen; + base[_GPIO_GPDIR_OFFSET]= gpdir; + base[_GPIO_GPVAL_OFFSET]= gpval; + base[_GPIO_GPHM_OFFSET] = gphm; + base[_GPIO_GPLM_OFFSET] = gplm; + base[_GPIO_GPPOL_OFFSET]= gppol ; + + IRQ_globalRestore(gie); +} +/*----------------------------------------------------------------------------*/ +IDEF void GPIO_getConfig(GPIO_Handle hGpio,GPIO_Config *config) { + Uint32 gie; + register int x0,x1,x2,x3,x4,x5,x6; + volatile Uint32 *base = (volatile Uint32 *)(hGpio->baseAddr); + + gie = IRQ_globalDisable(); + + x0 = base[_GPIO_GPGC_OFFSET]; + x1 = base[_GPIO_GPEN_OFFSET]; + x2 = base[_GPIO_GPDIR_OFFSET]; + x3 = base[_GPIO_GPVAL_OFFSET]; + x4 = base[_GPIO_GPHM_OFFSET]; + x5 = base[_GPIO_GPLM_OFFSET]; + x6 = base[_GPIO_GPPOL_OFFSET]; + + config->gpgc = x0; + config->gpen = x1; + config->gpdir = x2; + config->gpval = x3; + config->gphm = x4; + config->gplm = x5; + config->gppol = x6; + + IRQ_globalRestore(gie); +} +/*---------------------------------------------------------------------------*/ + +#endif /* USEDEFS */ + + +#endif /* GPIO_SUPPORT */ + +#endif /* _CSL_GPIO_H_ */ +/******************************************************************************\ +* End of csl_gpio.h +\******************************************************************************/ diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_gpiohal.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_gpiohal.h new file mode 100644 index 0000000..d177952 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_gpiohal.h @@ -0,0 +1,1211 @@ +/******************************************************************************\ +* Copyright (C) 2000-2001 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_gpiohal.h +* DATE CREATED.. 12/04/2000 +* LAST MODIFIED. 06/17/2003 - Added support for 6712C +* 06/09/2003 - Added support for 6711C +* 10/02/2001 - GPIO1 implementation +* +*------------------------------------------------------------------------------ +* REGISTERS +* +* GPENx - GPIO Enable register +* GPDIRx - GPIO Direction register +* GPVALx - GPIO Value register +* GPDHx - GPIO Delta High register +* GPHMx - GPIO High Mask register +* GPDLx - GPIO Delta Low register +* GPLMx - GPIO Low Mask register +* GPGCx - GPIO Global Control register +* GPPOLx - GPIO Interrupt Polarity register +* +* with x = {0,1} +\******************************************************************************/ +#ifndef _CSL_GPIOHAL_H_ +#define _CSL_GPIOHAL_H_ + +#include +#include + +#if (GPIO_SUPPORT) +/******************************************************************************\ +* MISC section +\******************************************************************************/ + +#define _GPIO_BASE_ADDR 0x01B00000u +#define _GPIO_BASE_ADDR0 0x01B00000u +#if (CHIP_DA610) +#define _GPIO_BASE_ADDR1 0x01B04000u +#endif + +/******************************************************************************\ +* Module level register/field access macros +\******************************************************************************/ + + /* -------------------------- */ + /* FIELD MAKE MACROS */ + /* -------------------------- */ + + #define GPIO_FMK(REG,FIELD,x)\ + _PER_FMK(GPIO,##REG,##FIELD,x) + + #define GPIO_FMKS(REG,FIELD,SYM)\ + _PER_FMKS(GPIO,##REG,##FIELD,##SYM) + + + /* ----------------------------------------- */ + /* RAW REGISTER/FIELD ACCESS MACROS */ + /* ----------------------------------------- */ + + #define GPIO_ADDR(REG)\ + _GPIO_##REG##_ADDR + + #define GPIO_RGET(REG)\ + _PER_RGET(_GPIO_##REG##_ADDR,GPIO,##REG) + + #define GPIO_RSET(REG,x)\ + _PER_RSET(_GPIO_##REG##_ADDR,GPIO,##REG,x) + + #define GPIO_FGET(REG,FIELD)\ + _GPIO_##REG##_FGET(##FIELD) + + #define GPIO_FSET(REG,FIELD,x)\ + _GPIO_##REG##_FSET(##FIELD,##x) + + #define GPIO_FSETS(REG,FIELD,SYM)\ + _GPIO_##REG##_FSETS(##FIELD,##SYM) + + + /* --------------------------------------------------- */ + /* ADDRESS BASED REGISTER/FIELD ACCESS MACROS */ + /* --------------------------------------------------- */ + + #define GPIO_RGETA(addr,REG)\ + _PER_RGET(addr,GPIO,##REG) + + #define GPIO_RSETA(addr,REG,x)\ + _PER_RSET(addr,GPIO,##REG,x) + + #define GPIO_FGETA(addr,REG,FIELD)\ + _PER_FGET(addr,GPIO,##REG,##FIELD) + + #define GPIO_FSETA(addr,REG,FIELD,x)\ + _PER_FSET(addr,GPIO,##REG,##FIELD,x) + + #define GPIO_FSETSA(addr,REG,FIELD,SYM)\ + _PER_FSETS(addr,GPIO,##REG,##FIELD,##SYM) + + /* -------------------------------------------------- */ + /* HANDLE BASED REGISTER/FIELD ACCESS MACROS */ + /* -------------------------------------------------- */ + + + #define GPIO_ADDRH(h,REG)\ + (Uint32)(&((h)->baseAddr[_GPIO_##REG##_OFFSET])) + + #define GPIO_RGETH(h,REG)\ + GPIO_RGETA(GPIO_ADDRH(h,##REG),##REG) + + + #define GPIO_RSETH(h,REG,x)\ + GPIO_RSETA(GPIO_ADDRH(h,##REG),##REG,x) + + + #define GPIO_FGETH(h,REG,FIELD)\ + GPIO_FGETA(GPIO_ADDRH(h,##REG),##REG,##FIELD) + + + #define GPIO_FSETH(h,REG,FIELD,x)\ + GPIO_FSETA(GPIO_ADDRH(h,##REG),##REG,##FIELD,x) + + + #define GPIO_FSETSH(h,REG,FIELD,SYM)\ + GPIO_FSETSA(GPIO_ADDRH(h,##REG),##REG,##FIELD,##SYM) + + + + +/******************************************************************************\ +* _____________________ +* | | +* | G P E N | +* |___________________| +* +* GPEN - GPIO Enable register +* +* FIELDS (msb -> lsb) +* (rw) GPXEN +* +\******************************************************************************/ + #define _GPIO_GPEN_OFFSET 0 + + #define _GPIO_GPEN_ADDR 0x01B00000u + +#if (CHIP_6711C || CHIP_6712C) + #define _GPIO_GPEN_GPXEN_MASK 0x000000F4u +#else + #define _GPIO_GPEN_GPXEN_MASK 0x0000FFFFu +#endif + + #define _GPIO_GPEN_GPXEN_SHIFT 0x00000000u + +#if (CHIP_6713 || CHIP_DA610 || CHIP_6711C || CHIP_6712C) + #define GPIO_GPEN_GPXEN_DEFAULT 0x000000F0u +#else + #define GPIO_GPEN_GPXEN_DEFAULT 0x000000F9u +#endif + + #define GPIO_GPEN_GPXEN_OF(x) _VALUEOF(x) + + #define GPIO_GPEN_OF(x) _VALUEOF(x) + + #define GPIO_GPEN_DEFAULT (Uint32)( \ + _PER_FDEFAULT(GPIO,GPEN,GPXEN)\ + ) + + #define GPIO_GPEN_RMK(gpxen) (Uint32)( \ + _PER_FMK(GPIO,GPEN,GPXEN,gpxen)\ + ) + + #define _GPIO_GPEN_FGET(FIELD)\ + _PER_FGET(_GPIO_GPEN_ADDR,GPIO,GPEN,##FIELD) + + #define _GPIO_GPEN_FSET(FIELD,field)\ + _PER_FSET(_GPIO_GPEN_ADDR,GPIO,GPEN,##FIELD,field) + + #define _GPIO_GPEN_FSETS(FIELD,SYM)\ + _PER_FSETS(_GPIO_GPEN_ADDR,GPIO,GPEN,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | G P D I R | +* |___________________| +* +* GPDIR - GPIO Direction register +* +* FIELDS (msb -> lsb) +* (rw) GPXDIR +* +\******************************************************************************/ + #define _GPIO_GPDIR_OFFSET 1 + + #define _GPIO_GPDIR_ADDR 0x01B00004u + +#if (CHIP_6711C || CHIP_6712C) + #define _GPIO_GPDIR_GPXDIR_MASK 0x000000F4u +#else + #define _GPIO_GPDIR_GPXDIR_MASK 0x0000FFFFu +#endif + + #define _GPIO_GPDIR_GPXDIR_SHIFT 0x00000000u + #define GPIO_GPDIR_GPXDIR_DEFAULT 0x00000000u + #define GPIO_GPDIR_GPXDIR_OF(x) _VALUEOF(x) + + #define GPIO_GPDIR_OF(x) _VALUEOF(x) + + #define GPIO_GPDIR_DEFAULT (Uint32)( \ + _PER_FDEFAULT(GPIO,GPDIR,GPXDIR)\ + ) + + #define GPIO_GPDIR_RMK(gpxdir) (Uint32)( \ + _PER_FMK(GPIO,GPDIR,GPXDIR,gpxdir)\ + ) + + #define _GPIO_GPDIR_FGET(FIELD)\ + _PER_FGET(_GPIO_GPDIR_ADDR,GPIO,GPDIR,##FIELD) + + #define _GPIO_GPDIR_FSET(FIELD,field)\ + _PER_FSET(_GPIO_GPDIR_ADDR,GPIO,GPDIR,##FIELD,field) + + #define _GPIO_GPDIR_FSETS(FIELD,SYM)\ + _PER_FSETS(_GPIO_GPDIR_ADDR,GPIO,GPDIR,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | G P V A L | +* |___________________| +* +* GPVAL - GPIO Value register +* +* FIELDS (msb -> lsb) +* (rw) GPXVAL +* +\******************************************************************************/ + #define _GPIO_GPVAL_OFFSET 2 + + #define _GPIO_GPVAL_ADDR 0x01B00008u + +#if (CHIP_6711C || CHIP_6712C) + #define _GPIO_GPVAL_GPXVAL_MASK 0x000000F4u +#else + #define _GPIO_GPVAL_GPXVAL_MASK 0x0000FFFFu +#endif + + #define _GPIO_GPVAL_GPXVAL_SHIFT 0x00000000u + #define GPIO_GPVAL_GPXVAL_DEFAULT 0x00000000u + #define GPIO_GPVAL_GPXVAL_OF(x) _VALUEOF(x) + + #define GPIO_GPVAL_OF(x) _VALUEOF(x) + + #define GPIO_GPVAL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(GPIO,GPVAL,GPXVAL)\ + ) + + #define GPIO_GPVAL_RMK(gpxval) (Uint32)( \ + _PER_FMK(GPIO,GPVAL,GPXVAL,gpxval)\ + ) + + #define _GPIO_GPVAL_FGET(FIELD)\ + _PER_FGET(_GPIO_GPVAL_ADDR,GPIO,GPVAL,##FIELD) + + #define _GPIO_GPVAL_FSET(FIELD,field)\ + _PER_FSET(_GPIO_GPVAL_ADDR,GPIO,GPVAL,##FIELD,field) + + #define _GPIO_GPVAL_FSETS(FIELD,SYM)\ + _PER_FSETS(_GPIO_GPVAL_ADDR,GPIO,GPVAL,##FIELD,##SYM) + +/******************************************************************************\ +* _____________________ +* | | +* | G P D H | +* |___________________| +* +* GPDH - GPIO Delta High register +* +* FIELDS (msb -> lsb) +* (rw) GPXDH +* +\******************************************************************************/ + #define _GPIO_GPDH_OFFSET 4 + + #define _GPIO_GPDH_ADDR 0x01B00010u + +#if (CHIP_6711C || CHIP_6712C) + #define _GPIO_GPDH_GPXDH_MASK 0x000000F4u +#else + #define _GPIO_GPDH_GPXDH_MASK 0x0000FFFFu +#endif + + #define _GPIO_GPDH_GPXDH_SHIFT 0x00000000u + #define GPIO_GPDH_GPXDH_DEFAULT 0x00000000u + #define GPIO_GPDH_GPXDH_OF(x) _VALUEOF(x) + + #define GPIO_GPDH_OF(x) _VALUEOF(x) + + #define GPIO_GPDH_DEFAULT (Uint32)( \ + _PER_FDEFAULT(GPIO,GPDH,GPXDH)\ + ) + + #define GPIO_GPDH_RMK(gpxdh) (Uint32)( \ + _PER_FMK(GPIO,GPDH,GPXDH,gpxdh)\ + ) + + #define _GPIO_GPDH_FGET(FIELD)\ + _PER_FGET(_GPIO_GPDH_ADDR,GPIO,GPDH,##FIELD) + + #define _GPIO_GPDH_FSET(FIELD,field)\ + _PER_FSET(_GPIO_GPDH_ADDR,GPIO,GPDH,##FIELD,field) + + #define _GPIO_GPDH_FSETS(FIELD,SYM)\ + _PER_FSETS(_GPIO_GPDH_ADDR,GPIO,GPDH,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | G P H M | +* |___________________| +* +* GPHM - GPIO High Mask register +* +* FIELDS (msb -> lsb) +* (rw) GPXHM +* +\******************************************************************************/ + #define _GPIO_GPHM_OFFSET 5 + + #define _GPIO_GPHM_ADDR 0x01B00014u + +#if (CHIP_6711C || CHIP_6712C) + #define _GPIO_GPHM_GPXHM_MASK 0x000000F4u +#else + #define _GPIO_GPHM_GPXHM_MASK 0x0000FFFFu +#endif + + #define _GPIO_GPHM_GPXHM_SHIFT 0x00000000u + #define GPIO_GPHM_GPXHM_DEFAULT 0x00000000u + #define GPIO_GPHM_GPXHM_OF(x) _VALUEOF(x) + + #define GPIO_GPHM_OF(x) _VALUEOF(x) + + #define GPIO_GPHM_DEFAULT (Uint32)( \ + _PER_FDEFAULT(GPIO,GPHM,GPXHM)\ + ) + + #define GPIO_GPHM_RMK(gpxhm) (Uint32)( \ + _PER_FMK(GPIO,GPHM,GPXHM,gpxhm)\ + ) + + #define _GPIO_GPHM_FGET(FIELD)\ + _PER_FGET(_GPIO_GPHM_ADDR,GPIO,GPHM,##FIELD) + + #define _GPIO_GPHM_FSET(FIELD,field)\ + _PER_FSET(_GPIO_GPHM_ADDR,GPIO,GPHM,##FIELD,field) + + #define _GPIO_GPHM_FSETS(FIELD,SYM)\ + _PER_FSETS(_GPIO_GPHM_ADDR,GPIO,GPHM,##FIELD,##SYM) + + + +/******************************************************************************\ +* _____________________ +* | | +* | G P D L | +* |___________________| +* +* GPDL - GPIO Delta Low register +* +* FIELDS (msb -> lsb) +* (rw) GPXDL +* +\******************************************************************************/ + #define _GPIO_GPDL_OFFSET 6 + + #define _GPIO_GPDL_ADDR 0x01B00018u + +#if (CHIP_6711C || CHIP_6712C) + #define _GPIO_GPDL_GPXDL_MASK 0x000000F4u +#else + #define _GPIO_GPDL_GPXDL_MASK 0x0000FFFFu +#endif + + #define _GPIO_GPDL_GPXDL_SHIFT 0x00000000u + #define GPIO_GPDL_GPXDL_DEFAULT 0x00000000u + #define GPIO_GPDL_GPXDL_OF(x) _VALUEOF(x) + + #define GPIO_GPDL_OF(x) _VALUEOF(x) + + #define GPIO_GPDL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(GPIO,GPDL,GPXDL)\ + ) + + #define GPIO_GPDL_RMK(gpxdl) (Uint32)( \ + _PER_FMK(GPIO,GPDL,GPXDL,gpxdl)\ + ) + + #define _GPIO_GPDL_FGET(FIELD)\ + _PER_FGET(_GPIO_GPDL_ADDR,GPIO,GPDL,##FIELD) + + #define _GPIO_GPDL_FSET(FIELD,field)\ + _PER_FSET(_GPIO_GPDL_ADDR,GPIO,GPDL,##FIELD,field) + + #define _GPIO_GPDL_FSETS(FIELD,SYM)\ + _PER_FSETS(_GPIO_GPDL_ADDR,GPIO,GPDL,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | G P L M | +* |___________________| +* +* GPLM - GPIO Low Mask register +* +* FIELDS (msb -> lsb) +* (rw) GPXLM +* +\******************************************************************************/ + #define _GPIO_GPLM_OFFSET 7 + + #define _GPIO_GPLM_ADDR 0x01B0001Cu + +#if (CHIP_6711C || CHIP_6712C) + #define _GPIO_GPLM_GPXLM_MASK 0x000000F4u +#else + #define _GPIO_GPLM_GPXLM_MASK 0x0000FFFFu +#endif + + #define _GPIO_GPLM_GPXLM_SHIFT 0x00000000u + #define GPIO_GPLM_GPXLM_DEFAULT 0x00000000u + #define GPIO_GPLM_GPXLM_OF(x) _VALUEOF(x) + + #define GPIO_GPLM_OF(x) _VALUEOF(x) + + #define GPIO_GPLM_DEFAULT (Uint32)( \ + _PER_FDEFAULT(GPIO,GPLM,GPXLM)\ + ) + + #define GPIO_GPLM_RMK(gpxlm) (Uint32)( \ + _PER_FMK(GPIO,GPLM,GPXLM,gpxlm)\ + ) + + #define _GPIO_GPLM_FGET(FIELD)\ + _PER_FGET(_GPIO_GPLM_ADDR,GPIO,GPLM,##FIELD) + + #define _GPIO_GPLM_FSET(FIELD,field)\ + _PER_FSET(_GPIO_GPLM_ADDR,GPIO,GPLM,##FIELD,field) + + #define _GPIO_GPLM_FSETS(FIELD,SYM)\ + _PER_FSETS(_GPIO_GPLM_ADDR,GPIO,GPLM,##FIELD,##SYM) + + + +/******************************************************************************\ +* _____________________ +* | | +* | G P G C | +* |___________________| +* +* GPGC - GPIO Global Control register +* +* FIELDS (msb -> lsb) +* (rw) GP0M +* (rw) GPINT0M +* (rw) GPINTPOL +* (rw) LOGIC +* (rw) GPINTDV +* +\******************************************************************************/ + #define _GPIO_GPGC_OFFSET 8 + + #define _GPIO_GPGC_ADDR 0x01B00020u + + #define _GPIO_GPGC_GP0M_MASK 0x00000020u + #define _GPIO_GPGC_GP0M_SHIFT 0x00000005u + #define GPIO_GPGC_GP0M_DEFAULT 0x00000000u + #define GPIO_GPGC_GP0M_OF(x) _VALUEOF(x) + #define GPIO_GPGC_GP0M_GPIOMODE 0x00000000u + #define GPIO_GPGC_GP0M_LOGICMODE 0x00000001u + + #define _GPIO_GPGC_GPINT0M_MASK 0x00000010u + #define _GPIO_GPGC_GPINT0M_SHIFT 0x00000004u + #define GPIO_GPGC_GPINT0M_DEFAULT 0x00000000u + #define GPIO_GPGC_GPINT0M_OF(x) _VALUEOF(x) + #define GPIO_GPGC_GPINT0M_PASSMODE 0x00000000u + #define GPIO_GPGC_GPINT0M_LOGICMODE 0x00000001u + + #define _GPIO_GPGC_GPINTPOL_MASK 0x00000004u + #define _GPIO_GPGC_GPINTPOL_SHIFT 0x00000002u + #define GPIO_GPGC_GPINTPOL_DEFAULT 0x00000000u + #define GPIO_GPGC_GPINTPOL_OF(x) _VALUEOF(x) + #define GPIO_GPGC_GPINTPOL_LOGICTRUE 0x00000000u + #define GPIO_GPGC_GPINTPOL_LOGICFALSE 0x00000001u + + #define _GPIO_GPGC_LOGIC_MASK 0x00000002u + #define _GPIO_GPGC_LOGIC_SHIFT 0x00000001u + #define GPIO_GPGC_LOGIC_DEFAULT 0x00000000u + #define GPIO_GPGC_LOGIC_OF(x) _VALUEOF(x) + #define GPIO_GPGC_LOGIC_ORMODE 0x00000000u + #define GPIO_GPGC_LOGIC_ANDMODE 0x00000001u + + #define _GPIO_GPGC_GPINTDV_MASK 0x00000001u + #define _GPIO_GPGC_GPINTDV_SHIFT 0x00000000u + #define GPIO_GPGC_GPINTDV_DEFAULT 0x00000000u + #define GPIO_GPGC_GPINTDV_OF(x) _VALUEOF(x) + #define GPIO_GPGC_GPINTDV_DELTAMODE 0x00000000u + #define GPIO_GPGC_GPINTDV_VALUEMODE 0x00000001u + + #define GPIO_GPGC_OF(x) _VALUEOF(x) + + #define GPIO_GPGC_DEFAULT (Uint32)( \ + _PER_FDEFAULT(GPIO,GPGC,GP0M)\ + |_PER_FDEFAULT(GPIO,GPGC,GPINT0M)\ + |_PER_FDEFAULT(GPIO,GPGC,GPINTPOL)\ + |_PER_FDEFAULT(GPIO,GPGC,LOGIC)\ + |_PER_FDEFAULT(GPIO,GPGC,GPINTDV)\ + ) + + #define GPIO_GPGC_RMK(gp0m,gpint0m,gpintpol,logic,gpintdv) (Uint32)( \ + _PER_FMK(GPIO,GPGC,GP0M,gp0m)\ + |_PER_FMK(GPIO,GPGC,GPINT0M,gpint0m)\ + |_PER_FMK(GPIO,GPGC,GPINTPOL,gpintpol)\ + |_PER_FMK(GPIO,GPGC,LOGIC,logic)\ + |_PER_FMK(GPIO,GPGC,GPINTDV,gpintdv)\ + ) + + #define _GPIO_GPGC_FGET(FIELD)\ + _PER_FGET(_GPIO_GPGC_ADDR,GPIO,GPGC,##FIELD) + + #define _GPIO_GPGC_FSET(FIELD,field)\ + _PER_FSET(_GPIO_GPGC_ADDR,GPIO,GPGC,##FIELD,field) + + #define _GPIO_GPGC_FSETS(FIELD,SYM)\ + _PER_FSETS(_GPIO_GPGC_ADDR,GPIO,GPGC,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | G P P O L | +* |___________________| +* +* GPPOL - GPIO Interrupt Polarity register +* +* FIELDS (msb -> lsb) +* (rw) GPINTXPOL +* +\******************************************************************************/ + #define _GPIO_GPPOL_OFFSET 9 + + #define _GPIO_GPPOL_ADDR 0x01B00024u + + #define _GPIO_GPPOL_GPINTXPOL_MASK 0x000000F9u + #define _GPIO_GPPOL_GPINTXPOL_SHIFT 0x00000000u + #define GPIO_GPPOL_GPINTXPOL_DEFAULT 0x00000000u + #define GPIO_GPPOL_GPINTXPOL_OF(x) _VALUEOF(x) + + #define GPIO_GPPOL_OF(x) _VALUEOF(x) + + #define GPIO_GPPOL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(GPIO,GPPOL,GPINTXPOL)\ + ) + + #define GPIO_GPPOL_RMK(gpintxpol) (Uint32)( \ + _PER_FMK(GPIO,GPPOL,GPINTXPOL,gpintxpol)\ + ) + + #define _GPIO_GPPOL_FGET(FIELD)\ + _PER_FGET(_GPIO_GPPOL_ADDR,GPIO,GPPOL,##FIELD) /* bug fixed pn 10/02/2001 */ + + #define _GPIO_GPPOL_FSET(FIELD,field)\ + _PER_FSET(_GPIO_GPPOL_ADDR,GPIO,GPPOL,##FIELD,field) + + #define _GPIO_GPPOL_FSETS(FIELD,SYM)\ + _PER_FSETS(_GPIO_GPPOL_ADDR,GPIO,GPPOL,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | G P E N | +* |___________________| +* +* GPEN0 - GPIO0 Enable register +* GPEN1 - GPIO1 Enable register +* +* FIELDS (msb -> lsb) +* (rw) GPXEN +* +\******************************************************************************/ + #define _GPIO_GPEN0_OFFSET 0 +#if (CHIP_DA610) + #define _GPIO_GPEN1_OFFSET 0 +#endif + + #define _GPIO_GPEN0_ADDR 0x01B00000u +#if (CHIP_DA610) + #define _GPIO_GPEN1_ADDR 0x01B04000u +#endif + +#if (CHIP_6711C || CHIP_6712C) + #define _GPIO_GPEN_GPXEN_MASK 0x000000F4u +#else + #define _GPIO_GPEN_GPXEN_MASK 0x0000FFFFu +#endif + + #define _GPIO_GPEN_GPXEN_SHIFT 0x00000000u + +#if (CHIP_6713 || CHIP_DA610 || CHIP_6711C || CHIP_6712C) + #define GPIO_GPEN_GPXEN_DEFAULT 0x000000F0u +#else + #define GPIO_GPEN_GPXEN_DEFAULT 0x000000F9u +#endif + + #define GPIO_GPEN_GPXEN_OF(x) _VALUEOF(x) + + #define GPIO_GPEN_OF(x) _VALUEOF(x) + + #define GPIO_GPEN_DEFAULT (Uint32)( \ + _PER_FDEFAULT(GPIO,GPEN,GPXEN)\ + ) + + #define GPIO_GPEN_RMK(gpxen) (Uint32)( \ + _PER_FMK(GPIO,GPEN,GPXEN,gpxen)\ + ) + + #define _GPIO_GPEN0_FGET(FIELD)\ + _PER_FGET(_GPIO_GPEN0_ADDR,GPIO,GPEN,##FIELD) + +#if (CHIP_DA610) + #define _GPIO_GPEN1_FGET(FIELD)\ + _PER_FGET(_GPIO_GPEN1_ADDR,GPIO,GPEN,##FIELD) +#endif + + #define _GPIO_GPEN0_FSET(FIELD,field)\ + _PER_FSET(_GPIO_GPEN0_ADDR,GPIO,GPEN,##FIELD,field) + +#if (CHIP_DA610) + #define _GPIO_GPEN1_FSET(FIELD,field)\ + _PER_FSET(_GPIO_GPEN1_ADDR,GPIO,GPEN,##FIELD,field) +#endif + + #define _GPIO_GPEN0_FSETS(FIELD,SYM)\ + _PER_FSETS(_GPIO_GPEN0_ADDR,GPIO,GPEN,##FIELD,##SYM) + +#if (CHIP_DA610) + #define _GPIO_GPEN1_FSETS(FIELD,SYM)\ + _PER_FSETS(_GPIO_GPEN1_ADDR,GPIO,GPEN,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* _____________________ +* | | +* | G P D I R | +* |___________________| +* +* GPDIR0 - GPIO0 Direction register +* GPDIR1 - GPIO1 Direction register +* FIELDS (msb -> lsb) +* (rw) GPXDIR +* +\******************************************************************************/ + #define _GPIO_GPDIR0_OFFSET 1 +#if (CHIP_DA610) + #define _GPIO_GPDIR1_OFFSET 1 +#endif + + #define _GPIO_GPDIR0_ADDR 0x01B00004u +#if (CHIP_DA610) + #define _GPIO_GPDIR1_ADDR 0x01B04004u +#endif + +#if (CHIP_6711C || CHIP_6712C) + #define _GPIO_GPDIR_GPXDIR_MASK 0x000000F4u +#else + #define _GPIO_GPDIR_GPXDIR_MASK 0x0000FFFFu +#endif + + #define _GPIO_GPDIR_GPXDIR_SHIFT 0x00000000u + #define GPIO_GPDIR_GPXDIR_DEFAULT 0x00000000u + #define GPIO_GPDIR_GPXDIR_OF(x) _VALUEOF(x) + + #define GPIO_GPDIR_OF(x) _VALUEOF(x) + + #define GPIO_GPDIR_DEFAULT (Uint32)( \ + _PER_FDEFAULT(GPIO,GPDIR,GPXDIR)\ + ) + + #define GPIO_GPDIR_RMK(gpxdir) (Uint32)( \ + _PER_FMK(GPIO,GPDIR,GPXDIR,gpxdir)\ + ) + + + #define _GPIO_GPDIR0_FGET(FIELD)\ + _PER_FGET(_GPIO_GPDIR0_ADDR,GPIO,GPDIR,##FIELD) + +#if (CHIP_DA610) + #define _GPIO_GPDIR1_FGET(FIELD)\ + _PER_FGET(_GPIO_GPDIR1_ADDR,GPIO,GPDIR,##FIELD) +#endif + + #define _GPIO_GPDIR0_FSET(FIELD,field)\ + _PER_FSET(_GPIO_GPDIR0_ADDR,GPIO,GPDIR,##FIELD,field) + +#if (CHIP_DA610) + #define _GPIO_GPDIR1_FSET(FIELD,field)\ + _PER_FSET(_GPIO_GPDIR1_ADDR,GPIO,GPDIR,##FIELD,field) +#endif + + + #define _GPIO_GPDIR0_FSETS(FIELD,SYM)\ + _PER_FSETS(_GPIO_GPDIR0_ADDR,GPIO,GPDIR,##FIELD,##SYM) +#if (CHIP_DA610) + #define _GPIO_GPDIR1_FSETS(FIELD,SYM)\ + _PER_FSETS(_GPIO_GPDIR1_ADDR,GPIO,GPDIR,##FIELD,##SYM) +#endif + +/******************************************************************************\ +* _____________________ +* | | +* | G P V A L | +* |___________________| +* +* GPVAL0 - GPIO0 Value register +* GPVAL1 - GPIO1 Value register +* FIELDS (msb -> lsb) +* (rw) GPXVAL +* +\******************************************************************************/ + #define _GPIO_GPVAL0_OFFSET 2 +#if (CHIP_DA610) + #define _GPIO_GPVAL1_OFFSET 2 +#endif + + #define _GPIO_GPVAL0_ADDR 0x01B00008u +#if (CHIP_DA610) + #define _GPIO_GPVAL1_ADDR 0x01B04008u +#endif + +#if (CHIP_6711C || CHIP_6712C) + #define _GPIO_GPVAL_GPXVAL_MASK 0x000000F4u +#else + #define _GPIO_GPVAL_GPXVAL_MASK 0x0000FFFFu +#endif + + #define _GPIO_GPVAL_GPXVAL_SHIFT 0x00000000u + #define GPIO_GPVAL_GPXVAL_DEFAULT 0x00000000u + #define GPIO_GPVAL_GPXVAL_OF(x) _VALUEOF(x) + + #define GPIO_GPVAL_OF(x) _VALUEOF(x) + + #define GPIO_GPVAL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(GPIO,GPVAL,GPXVAL)\ + ) + + #define GPIO_GPVAL_RMK(gpxval) (Uint32)( \ + _PER_FMK(GPIO,GPVAL,GPXVAL,gpxval)\ + ) + + #define _GPIO_GPVAL0_FGET(FIELD)\ + _PER_FGET(_GPIO_GPVAL0_ADDR,GPIO,GPVAL,##FIELD) +#if (CHIP_DA610) + #define _GPIO_GPVAL1_FGET(FIELD)\ + _PER_FGET(_GPIO_GPVAL1_ADDR,GPIO,GPVAL,##FIELD) +#endif + + #define _GPIO_GPVAL0_FSET(FIELD,field)\ + _PER_FSET(_GPIO_GPVAL0_ADDR,GPIO,GPVAL,##FIELD,field) +#if (CHIP_DA610) + #define _GPIO_GPVAL1_FSET(FIELD,field)\ + _PER_FSET(_GPIO_GPVAL1_ADDR,GPIO,GPVAL,##FIELD,field) +#endif + + #define _GPIO_GPVAL0_FSETS(FIELD,SYM)\ + _PER_FSETS(_GPIO_GPVAL0_ADDR,GPIO,GPVAL,##FIELD,##SYM) +#if (CHIP_DA610) + #define _GPIO_GPVAL1_FSETS(FIELD,SYM)\ + _PER_FSETS(_GPIO_GPVAL1_ADDR,GPIO,GPVAL,##FIELD,##SYM) +#endif + +/******************************************************************************\ +* _____________________ +* | | +* | G P D H | +* |___________________| +* +* GPDH0 - GPIO0 Delta High register +* GPDH1 - GPIO1 Delta High register +* FIELDS (msb -> lsb) +* (rw) GPXDH +* +\******************************************************************************/ + #define _GPIO_GPDH0_OFFSET 4 +#if (CHIP_DA610) + #define _GPIO_GPDH1_OFFSET 4 +#endif + + #define _GPIO_GPDH0_ADDR 0x01B04010u +#if (CHIP_DA610) + #define _GPIO_GPDH1_ADDR 0x01B04010u +#endif + +#if (CHIP_6711C || CHIP_6712C) + #define _GPIO_GPDH_GPXDH_MASK 0x000000F4u +#else + #define _GPIO_GPDH_GPXDH_MASK 0x0000FFFFu +#endif + + #define _GPIO_GPDH_GPXDH_SHIFT 0x00000000u + #define GPIO_GPDH_GPXDH_DEFAULT 0x00000000u + #define GPIO_GPDH_GPXDH_OF(x) _VALUEOF(x) + + #define GPIO_GPDH_OF(x) _VALUEOF(x) + + #define GPIO_GPDH_DEFAULT (Uint32)( \ + _PER_FDEFAULT(GPIO,GPDH,GPXDH)\ + ) + + #define GPIO_GPDH_RMK(gpxdh) (Uint32)( \ + _PER_FMK(GPIO,GPDH,GPXDH,gpxdh)\ + ) + + #define _GPIO_GPDH0_FGET(FIELD)\ + _PER_FGET(_GPIO_GPDH0_ADDR,GPIO,GPDH,##FIELD) +#if (CHIP_DA610) + #define _GPIO_GPDH1_FGET(FIELD)\ + _PER_FGET(_GPIO_GPDH1_ADDR,GPIO,GPDH,##FIELD) +#endif + + #define _GPIO_GPDH0_FSET(FIELD,field)\ + _PER_FSET(_GPIO_GPDH0_ADDR,GPIO,GPDH,##FIELD,field) +#if (CHIP_DA610) + #define _GPIO_GPDH1_FSET(FIELD,field)\ + _PER_FSET(_GPIO_GPDH1_ADDR,GPIO,GPDH,##FIELD,field) +#endif + + + #define _GPIO_GPDH0_FSETS(FIELD,SYM)\ + _PER_FSETS(_GPIO_GPDH0_ADDR,GPIO,GPDH,##FIELD,##SYM) +#if (CHIP_DA610) + #define _GPIO_GPDH1_FSETS(FIELD,SYM)\ + _PER_FSETS(_GPIO_GPDH1_ADDR,GPIO,GPDH,##FIELD,##SYM) +#endif + +/******************************************************************************\ +* _____________________ +* | | +* | G P H M | +* |___________________| +* +* GPHM0 - GPIO0 High Mask register +* GPHM1 - GPIO1 High Mask register +* FIELDS (msb -> lsb) +* (rw) GPXHM +* +\******************************************************************************/ + #define _GPIO_GPHM0_OFFSET 5 +#if (CHIP_DA610) + #define _GPIO_GPHM1_OFFSET 5 +#endif + + #define _GPIO_GPHM0_ADDR 0x01B00014u +#if (CHIP_DA610) + #define _GPIO_GPHM1_ADDR 0x01B04014u +#endif + +#if (CHIP_6711C || CHIP_6712C) + #define _GPIO_GPHM_GPXHM_MASK 0x000000F4u +#else + #define _GPIO_GPHM_GPXHM_MASK 0x0000FFFFu +#endif + + #define _GPIO_GPHM_GPXHM_SHIFT 0x00000000u + #define GPIO_GPHM_GPXHM_DEFAULT 0x00000000u + #define GPIO_GPHM_GPXHM_OF(x) _VALUEOF(x) + + #define GPIO_GPHM_OF(x) _VALUEOF(x) + + #define GPIO_GPHM_DEFAULT (Uint32)( \ + _PER_FDEFAULT(GPIO,GPHM,GPXHM)\ + ) + + #define GPIO_GPHM_RMK(gpxhm) (Uint32)( \ + _PER_FMK(GPIO,GPHM,GPXHM,gpxhm)\ + ) + + #define _GPIO_GPHM0_FGET(FIELD)\ + _PER_FGET(_GPIO_GPHM0_ADDR,GPIO,GPHM,##FIELD) +#if (CHIP_DA610) + #define _GPIO_GPHM1_FGET(FIELD)\ + _PER_FGET(_GPIO_GPHM1_ADDR,GPIO,GPHM,##FIELD) +#endif + + #define _GPIO_GPHM0_FSET(FIELD,field)\ + _PER_FSET(_GPIO_GPHM0_ADDR,GPIO,GPHM,##FIELD,field) +#if (CHIP_DA610) + #define _GPIO_GPHM1_FSET(FIELD,field)\ + _PER_FSET(_GPIO_GPHM1_ADDR,GPIO,GPHM,##FIELD,field) +#endif + + #define _GPIO_GPHM0_FSETS(FIELD,SYM)\ + _PER_FSETS(_GPIO_GPHM0_ADDR,GPIO,GPHM,##FIELD,##SYM) +#if (CHIP_DA610) + #define _GPIO_GPHM1_FSETS(FIELD,SYM)\ + _PER_FSETS(_GPIO_GPHM1_ADDR,GPIO,GPHM,##FIELD,##SYM) +#endif + +/******************************************************************************\ +* _____________________ +* | | +* | G P D L | +* |___________________| +* +* GPDL0 - GPIO0 Delta Low register +* GPDL1 - GPIO1 Delta Low register +* FIELDS (msb -> lsb) +* (rw) GPXDL +* +\******************************************************************************/ + #define _GPIO_GPDL0_OFFSET 6 +#if (CHIP_DA610) + #define _GPIO_GPDL1_OFFSET 6 +#endif + + #define _GPIO_GPDL0_ADDR 0x01B00018u +#if (CHIP_DA610) + #define _GPIO_GPDL1_ADDR 0x01B04018u +#endif + +#if (CHIP_6711C || CHIP_6712C) + #define _GPIO_GPDL_GPXDL_MASK 0x000000F4u +#else + #define _GPIO_GPDL_GPXDL_MASK 0x0000FFFFu +#endif + + #define _GPIO_GPDL_GPXDL_SHIFT 0x00000000u + #define GPIO_GPDL_GPXDL_DEFAULT 0x00000000u + #define GPIO_GPDL_GPXDL_OF(x) _VALUEOF(x) + + #define GPIO_GPDL_OF(x) _VALUEOF(x) + + #define GPIO_GPDL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(GPIO,GPDL,GPXDL)\ + ) + + #define GPIO_GPDL_RMK(gpxdl) (Uint32)( \ + _PER_FMK(GPIO,GPDL,GPXDL,gpxdl)\ + ) + + #define _GPIO_GPDL0_FGET(FIELD)\ + _PER_FGET(_GPIO_GPDL0_ADDR,GPIO,GPDL,##FIELD) +#if (CHIP_DA610) + #define _GPIO_GPDL1_FGET(FIELD)\ + _PER_FGET(_GPIO_GPDL1_ADDR,GPIO,GPDL,##FIELD) +#endif + + #define _GPIO_GPDL0_FSET(FIELD,field)\ + _PER_FSET(_GPIO_GPDL0_ADDR,GPIO,GPDL,##FIELD,field) +#if (CHIP_DA610) + #define _GPIO_GPDL1_FSET(FIELD,field)\ + _PER_FSET(_GPIO_GPDL1_ADDR,GPIO,GPDL,##FIELD,field) +#endif + + #define _GPIO_GPDL0_FSETS(FIELD,SYM)\ + _PER_FSETS(_GPIO_GPDL0_ADDR,GPIO,GPDL,##FIELD,##SYM) +#if (CHIP_DA610) + #define _GPIO_GPDL1_FSETS(FIELD,SYM)\ + _PER_FSETS(_GPIO_GPDL1_ADDR,GPIO,GPDL,##FIELD,##SYM) +#endif + +/******************************************************************************\ +* _____________________ +* | | +* | G P L M | +* |___________________| +* +* GPLM0 - GPIO0 Low Mask register +* GPLM1 - GPIO1 Low Mask register +* FIELDS (msb -> lsb) +* (rw) GPXLM +* +\******************************************************************************/ + #define _GPIO_GPLM0_OFFSET 7 +#if (CHIP_DA610) + #define _GPIO_GPLM1_OFFSET 7 +#endif + + #define _GPIO_GPLM0_ADDR 0x01B0001Cu +#if (CHIP_DA610) + #define _GPIO_GPLM1_ADDR 0x01B0401Cu +#endif + +#if (CHIP_6711C || CHIP_6712C) + #define _GPIO_GPLM_GPXLM_MASK 0x000000F4u +#else + #define _GPIO_GPLM_GPXLM_MASK 0x0000FFFFu +#endif + + #define _GPIO_GPLM_GPXLM_SHIFT 0x00000000u + #define GPIO_GPLM_GPXLM_DEFAULT 0x00000000u + #define GPIO_GPLM_GPXLM_OF(x) _VALUEOF(x) + + #define GPIO_GPLM_OF(x) _VALUEOF(x) + + #define GPIO_GPLM_DEFAULT (Uint32)( \ + _PER_FDEFAULT(GPIO,GPLM,GPXLM)\ + ) + + #define GPIO_GPLM_RMK(gpxlm) (Uint32)( \ + _PER_FMK(GPIO,GPLM,GPXLM,gpxlm)\ + ) + + #define _GPIO_GPLM0_FGET(FIELD)\ + _PER_FGET(_GPIO_GPLM0_ADDR,GPIO,GPLM,##FIELD) +#if (CHIP_DA610) + #define _GPIO_GPLM1_FGET(FIELD)\ + _PER_FGET(_GPIO_GPLM1_ADDR,GPIO,GPLM,##FIELD) +#endif + + + #define _GPIO_GPLM0_FSET(FIELD,field)\ + _PER_FSET(_GPIO_GPLM0_ADDR,GPIO,GPLM,##FIELD,field) +#if (CHIP_DA610) + #define _GPIO_GPLM1_FSET(FIELD,field)\ + _PER_FSET(_GPIO_GPLM1_ADDR,GPIO,GPLM,##FIELD,field) +#endif + + #define _GPIO_GPLM0_FSETS(FIELD,SYM)\ + _PER_FSETS(_GPIO_GPLM0_ADDR,GPIO,GPLM,##FIELD,##SYM) +#if (CHIP_DA610) + #define _GPIO_GPLM1_FSETS(FIELD,SYM)\ + _PER_FSETS(_GPIO_GPLM1_ADDR,GPIO,GPLM,##FIELD,##SYM) +#endif + +/******************************************************************************\ +* _____________________ +* | | +* | G P G C | +* |___________________| +* +* GPGC0 - GPIO Global Control register +* GPGC1 - GPIO Global Control register +* FIELDS (msb -> lsb) +* (rw) GP0M +* (rw) GPINT0M +* (rw) GPINTPOL +* (rw) LOGIC +* (rw) GPINTDV +* +\******************************************************************************/ + #define _GPIO_GPGC0_OFFSET 8 +#if (CHIP_DA610) + #define _GPIO_GPGC1_OFFSET 8 +#endif + + #define _GPIO_GPGC0_ADDR 0x01B00020u +#if (CHIP_DA610) + #define _GPIO_GPGC1_ADDR 0x01B04020u +#endif + + #define _GPIO_GPGC_GP0M_MASK 0x00000020u + #define _GPIO_GPGC_GP0M_SHIFT 0x00000005u + #define GPIO_GPGC_GP0M_DEFAULT 0x00000000u + #define GPIO_GPGC_GP0M_OF(x) _VALUEOF(x) + #define GPIO_GPGC_GP0M_GPIOMODE 0x00000000u + #define GPIO_GPGC_GP0M_LOGICMODE 0x00000001u + + #define _GPIO_GPGC_GPINT0M_MASK 0x00000010u + #define _GPIO_GPGC_GPINT0M_SHIFT 0x00000004u + #define GPIO_GPGC_GPINT0M_DEFAULT 0x00000000u + #define GPIO_GPGC_GPINT0M_OF(x) _VALUEOF(x) + #define GPIO_GPGC_GPINT0M_PASSMODE 0x00000000u + #define GPIO_GPGC_GPINT0M_LOGICMODE 0x00000001u + + #define _GPIO_GPGC_GPINTPOL_MASK 0x00000004u + #define _GPIO_GPGC_GPINTPOL_SHIFT 0x00000002u + #define GPIO_GPGC_GPINTPOL_DEFAULT 0x00000000u + #define GPIO_GPGC_GPINTPOL_OF(x) _VALUEOF(x) + #define GPIO_GPGC_GPINTPOL_LOGICTRUE 0x00000000u + #define GPIO_GPGC_GPINTPOL_LOGICFALSE 0x00000001u + + #define _GPIO_GPGC_LOGIC_MASK 0x00000002u + #define _GPIO_GPGC_LOGIC_SHIFT 0x00000001u + #define GPIO_GPGC_LOGIC_DEFAULT 0x00000000u + #define GPIO_GPGC_LOGIC_OF(x) _VALUEOF(x) + #define GPIO_GPGC_LOGIC_ORMODE 0x00000000u + #define GPIO_GPGC_LOGIC_ANDMODE 0x00000001u + + #define _GPIO_GPGC_GPINTDV_MASK 0x00000001u + #define _GPIO_GPGC_GPINTDV_SHIFT 0x00000000u + #define GPIO_GPGC_GPINTDV_DEFAULT 0x00000000u + #define GPIO_GPGC_GPINTDV_OF(x) _VALUEOF(x) + #define GPIO_GPGC_GPINTDV_DELTAMODE 0x00000000u + #define GPIO_GPGC_GPINTDV_VALUEMODE 0x00000001u + + #define GPIO_GPGC_OF(x) _VALUEOF(x) + + #define GPIO_GPGC_DEFAULT (Uint32)( \ + _PER_FDEFAULT(GPIO,GPGC,GP0M)\ + |_PER_FDEFAULT(GPIO,GPGC,GPINT0M)\ + |_PER_FDEFAULT(GPIO,GPGC,GPINTPOL)\ + |_PER_FDEFAULT(GPIO,GPGC,LOGIC)\ + |_PER_FDEFAULT(GPIO,GPGC,GPINTDV)\ + ) + + #define GPIO_GPGC_RMK(gp0m,gpint0m,gpintpol,logic,gpintdv) (Uint32)( \ + _PER_FMK(GPIO,GPGC,GP0M,gp0m)\ + |_PER_FMK(GPIO,GPGC,GPINT0M,gpint0m)\ + |_PER_FMK(GPIO,GPGC,GPINTPOL,gpintpol)\ + |_PER_FMK(GPIO,GPGC,LOGIC,logic)\ + |_PER_FMK(GPIO,GPGC,GPINTDV,gpintdv)\ + ) + + #define _GPIO_GPGC0_FGET(FIELD)\ + _PER_FGET(_GPIO_GPGC0_ADDR,GPIO,GPGC,##FIELD) +#if (CHIP_DA610) + #define _GPIO_GPGC1_FGET(FIELD)\ + _PER_FGET(_GPIO_GPGC1_ADDR,GPIO,GPGC,##FIELD) +#endif + + #define _GPIO_GPGC0_FSET(FIELD,field)\ + _PER_FSET(_GPIO_GPGC0_ADDR,GPIO,GPGC,##FIELD,field) +#if (CHIP_DA610) + #define _GPIO_GPGC1_FSET(FIELD,field)\ + _PER_FSET(_GPIO_GPGC1_ADDR,GPIO,GPGC,##FIELD,field) +#endif + + #define _GPIO_GPGC0_FSETS(FIELD,SYM)\ + _PER_FSETS(_GPIO_GPGC0_ADDR,GPIO,GPGC,##FIELD,##SYM) +#if (CHIP_DA610) + #define _GPIO_GPGC1_FSETS(FIELD,SYM)\ + _PER_FSETS(_GPIO_GPGC1_ADDR,GPIO,GPGC,##FIELD,##SYM) +#endif +/******************************************************************************\ +* _____________________ +* | | +* | G P P O L | +* |___________________| +* +* GPPOL0 - GPIO0 Interrupt Polarity register +* GPPOL1 - GPIO1 Interrupt Polarity register +* FIELDS (msb -> lsb) +* (rw) GPINTXPOL +* +\******************************************************************************/ + #define _GPIO_GPPOL0_OFFSET 9 +#if (CHIP_DA610) + #define _GPIO_GPPOL1_OFFSET 9 +#endif + + #define _GPIO_GPPOL0_ADDR 0x01B00024u +#if (CHIP_DA610) + #define _GPIO_GPPOL1_ADDR 0x01B04024u +#endif + + #define _GPIO_GPPOL_GPINTXPOL_MASK 0x000000F9u + #define _GPIO_GPPOL_GPINTXPOL_SHIFT 0x00000000u + #define GPIO_GPPOL_GPINTXPOL_DEFAULT 0x00000000u + #define GPIO_GPPOL_GPINTXPOL_OF(x) _VALUEOF(x) + + #define GPIO_GPPOL_OF(x) _VALUEOF(x) + + #define GPIO_GPPOL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(GPIO,GPPOL,GPINTXPOL)\ + ) + + #define GPIO_GPPOL_RMK(gpintxpol) (Uint32)( \ + _PER_FMK(GPIO,GPPOL,GPINTXPOL,gpintxpol)\ + ) + #define _GPIO_GPPOL0_FGET(FIELD)\ + _PER_FGET(_GPIO_GPPOL0_ADDR,GPIO,GPPOL,##FIELD) +#if (CHIP_DA610) + #define _GPIO_GPPOL1_FGET(FIELD)\ + _PER_FGET(_GPIO_GPPOL1_ADDR,GPIO,GPPOL,##FIELD) +#endif + + #define _GPIO_GPPOL0_FSET(FIELD,field)\ + _PER_FSET(_GPIO_GPPOL0_ADDR,GPIO,GPPOL,##FIELD,field) +#if (CHIP_DA610) + #define _GPIO_GPPOL1_FSET(FIELD,field)\ + _PER_FSET(_GPIO_GPPOL1_ADDR,GPIO,GPPOL,##FIELD,field) +#endif + + #define _GPIO_GPPOL0_FSETS(FIELD,SYM)\ + _PER_FSETS(_GPIO_GPPOL0_ADDR,GPIO,GPPOL,##FIELD,##SYM) +#if (CHIP_DA610) + #define _GPIO_GPPOL1_FSETS(FIELD,SYM)\ + _PER_FSETS(_GPIO_GPPOL1_ADDR,GPIO,GPPOL,##FIELD,##SYM) +#endif + +/*----------------------------------------------------------------------------*/ + + +#endif /* GPIO_SUPPORT */ +#endif /* _CSL_GPIOHAL_H_ */ +/******************************************************************************\ +* End of csl_gpiohal.h +\******************************************************************************/ + + + + + + + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_gpioleg.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_gpioleg.h new file mode 100644 index 0000000..fa5e9d5 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_gpioleg.h @@ -0,0 +1,36 @@ +#include + +#if C64_SUPPORT +#define GPIO_config(config) GPIO_config(_hGpioDev0,config); +#define GPIO_configArgs( gpgc, gpen, gpdir, gpval, gphm, gplm, gppol)\ + GPIO_configArgs(_hGpioDev0, gpgc, gpen, gpdir, gpval, gphm, gplm, gppol) +#define GPIO_getConfig(config) GPIO_getConfig(_hGpioDev0,config) + + +#define GPIO_pinEnable(pinId) GPIO_pinEnable(_hGpioDev0,pinId) + +#define GPIO_pinDisable(pinId) GPIO_pinDisable(_hGpioDev0, pinId) +#define GPIO_pinDirection(pinId,direction) GPIO_pinDirection(_hGpioDev0,pinId,direction) + + +#define GPIO_pinRead( pinId) GPIO_pinRead(_hGpioDev0, pinId) + +/* For output Pins */ +#define GPIO_pinWrite( pinId, val) GPIO_pinWrite(_hGpioDev0, pinId, val) + + +/* For input Pins */ +#define GPIO_deltaHighGet( pinId) GPIO_deltaHighGet(_hGpioDev0, pinId) +#define GPIO_deltaHighClear( pinId) GPIO_deltaHighClear(_hGpioDev0, pinId) +#define GPIO_deltaLowGet( pinId) GPIO_deltaLowGet(_hGpioDev0, pinId) +#define GPIO_deltaLowClear( pinId) GPIO_deltaLowClear(_hGpioDev0, pinId) + +#define GPIO_maskHighSet( pinId) GPIO_maskHighSet(_hGpioDev0, pinId) +#define GPIO_maskHighClear( pinId) GPIO_maskHighClear(_hGpioDev0, pinId) +#define GPIO_maskLowSet( pinId) GPIO_maskLowSet(_hGpioDev0, pinId) +#define GPIO_maskLowClear( pinId) GPIO_maskLowClear(_hGpioDev0, pinId) + +/* Pass Through Mode */ +#define GPIO_intPolarity(signal,polarity) GPIO_intPolarity(_hGpioDev0, signal, polarity) +#endif + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_hpi.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_hpi.h new file mode 100644 index 0000000..ac122b7 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_hpi.h @@ -0,0 +1,150 @@ +/******************************************************************************\ +* Copyright (C) 1999-2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_hpi.h +* DATE CREATED.. 09/01/1999 +* LAST MODIFIED. 04/20/2001 (C64x compatibility) +\******************************************************************************/ +#ifndef _CSL_HPI_H_ +#define _CSL_HPI_H_ + +#include +#include +#include + + +#if (HPI_SUPPORT) +/******************************************************************************\ +* scope and inline control macros +\******************************************************************************/ +#ifdef __cplusplus +#define CSLAPI extern "C" far +#else +#define CSLAPI extern far +#endif + +#undef USEDEFS +#undef IDECL +#undef IDEF + +#ifdef _HPI_MOD_ + #define IDECL CSLAPI + #define USEDEFS + #define IDEF +#else + #ifdef _INLINE + #define IDECL static inline + #define USEDEFS + #define IDEF static inline + #else + #define IDECL CSLAPI + #endif +#endif + + +/******************************************************************************\ +* global macro declarations +\******************************************************************************/ + + +/******************************************************************************\ +* global typedef declarations +\******************************************************************************/ + + +/******************************************************************************\ +* global variable declarations +\******************************************************************************/ + + +/******************************************************************************\ +* global function declarations +\******************************************************************************/ + + +/******************************************************************************\ +* inline function declarations +\******************************************************************************/ +IDECL Uint32 HPI_getEventId(); +IDECL Uint32 HPI_getHwob(); +IDECL Uint32 HPI_getDspint(); +IDECL Uint32 HPI_getHint(); +IDECL Uint32 HPI_getHrdy(); +IDECL Uint32 HPI_getFetch(); +IDECL void HPI_setDspint(Uint32 val); +IDECL void HPI_setHint(Uint32 val); + +#if (C64_SUPPORT) +IDECL void HPI_setWriteAddr(Uint32 address); +IDECL Uint32 HPI_getWriteAddr(); +IDECL void HPI_setReadAddr(Uint32 address); +IDECL Uint32 HPI_getReadAddr(); +#endif /* C64_SUPPORT */ + +/******************************************************************************\ +* inline function definitions +\******************************************************************************/ +#ifdef USEDEFS +/*----------------------------------------------------------------------------*/ +IDEF Uint32 HPI_getEventId() { + return (Uint32)IRQ_EVT_DSPINT; +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 HPI_getHwob() { + return HPI_FGET(HPIC,HWOB); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 HPI_getDspint() { + return HPI_FGET(HPIC,DSPINT); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 HPI_getHint() { + return HPI_FGET(HPIC,HINT); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 HPI_getHrdy() { + return HPI_FGET(HPIC,HRDY); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 HPI_getFetch() { + return HPI_FGET(HPIC,FETCH); +} +/*----------------------------------------------------------------------------*/ +IDEF void HPI_setDspint(Uint32 val) { + HPI_FSET(HPIC,DSPINT,val); +} +/*----------------------------------------------------------------------------*/ +IDEF void HPI_setHint(Uint32 val) { + HPI_FSET(HPIC,HINT,val); +} +/*----------------------------------------------------------------------------*/ +#if (C64_SUPPORT) + +IDEF void HPI_setWriteAddr(Uint32 address) { + HPI_FSET(HPIAW,HPIAW,address); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 HPI_getWriteAddr(){ + return ( HPI_FGET(HPIAW,HPIAW)); +} +/*----------------------------------------------------------------------------*/ +IDEF void HPI_setReadAddr(Uint32 address) { + HPI_FSET(HPIAR,HPIAR,address); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 HPI_getReadAddr(){ + return ( HPI_FGET(HPIAR,HPIAR)); +} +/*----------------------------------------------------------------------------*/ +#endif /* C64_SUPPORT */ + +#endif /* USEDEFS */ + + +#endif /* HPI_SUPPORT */ +#endif /* _CSL_HPI_H_ */ +/******************************************************************************\ +* End of csl_hpi.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_hpihal.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_hpihal.h new file mode 100644 index 0000000..7ccdde3 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_hpihal.h @@ -0,0 +1,314 @@ +/******************************************************************************\ +* Copyright (C) 1999-2001 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_hpihal.h +* DATE CREATED.. 06/20/1999 +* LAST MODIFIED. 04/20/2001 (C64x compatibility) +* 06/09/2003 TRCTL bug +* 04/16/2004 Fixed TRCTL bad adress +* 12/09/2005 Changed the HPIAW/HPIAR shift macro from 0x00000002 +* to 0x00000000 to make it byte addressable. +*------------------------------------------------------------------------------ +* REGISTERS +* +* HPIC - HPI control register +* HPIAW - HPI Address Write register (1) +* HPIAR - HPI Address Read registrer (1) +* TRCTL - TR Control register (1) +* +* (1) supported by C64x devices only +\******************************************************************************/ +#ifndef _CSL_HPIHAL_H_ +#define _CSL_HPIHAL_H_ + +#include + +#if (HPI_SUPPORT) +/******************************************************************************\ +* MISC section +\******************************************************************************/ +#define _HPI_BASE_ADDR 0x01880000u + + +/******************************************************************************\ +* module level register/field access macros +\******************************************************************************/ + + /* ----------------- */ + /* FIELD MAKE MACROS */ + /* ----------------- */ + + #define HPI_FMK(REG,FIELD,x)\ + _PER_FMK(HPI,##REG,##FIELD,x) + + #define HPI_FMKS(REG,FIELD,SYM)\ + _PER_FMKS(HPI,##REG,##FIELD,##SYM) + + + /* -------------------------------- */ + /* RAW REGISTER/FIELD ACCESS MACROS */ + /* -------------------------------- */ + + #define HPI_ADDR(REG)\ + _HPI_##REG##_ADDR + + #define HPI_RGET(REG)\ + _PER_RGET(_HPI_##REG##_ADDR,HPI,##REG) + + #define HPI_RSET(REG,x)\ + _PER_RSET(_HPI_##REG##_ADDR,HPI,##REG,x) + + #define HPI_FGET(REG,FIELD)\ + _HPI_##REG##_FGET(##FIELD) + + #define HPI_FSET(REG,FIELD,x)\ + _HPI_##REG##_FSET(##FIELD,##x) + + #define HPI_FSETS(REG,FIELD,SYM)\ + _HPI_##REG##_FSETS(##FIELD,##SYM) + + + /* ------------------------------------------ */ + /* ADDRESS BASED REGISTER/FIELD ACCESS MACROS */ + /* ------------------------------------------ */ + + #define HPI_RGETA(addr,REG)\ + _PER_RGET(addr,HPI,##REG) + + #define HPI_RSETA(addr,REG,x)\ + _PER_RSET(addr,HPI,##REG,x) + + #define HPI_FGETA(addr,REG,FIELD)\ + _PER_FGET(addr,HPI,##REG,##FIELD) + + #define HPI_FSETA(addr,REG,FIELD,x)\ + _PER_FSET(addr,HPI,##REG,##FIELD,x) + + #define HPI_FSETSA(addr,REG,FIELD,SYM)\ + _PER_FSETS(addr,HPI,##REG,##FIELD,##SYM) + + + +/******************************************************************************\ +* _____________________ +* | | +* | H P I C | +* |___________________| +* +* HPI - HPI control register +* +* FIELDS (msb -> lsb) +* (r) FETCH +* (r) HRDY +* (rw) HINT +* (rw) DSPINT +* (r) HWOB +* +\******************************************************************************/ + #define _HPI_HPIC_OFFSET 0 + #define _HPI_HPIC_ADDR 0x01880000u + + #define _HPI_HPIC_FETCH_MASK 0x00000010u + #define _HPI_HPIC_FETCH_SHIFT 0x00000004u + #define HPI_HPIC_FETCH_DEFAULT 0x00000000u + #define HPI_HPIC_FETCH_OF(x) _VALUEOF(x) + #define HPI_HPIC_FETCH_0 0x00000000u + #define HPI_HPIC_FETCH_1 0x00000001u + + #define _HPI_HPIC_HRDY_MASK 0x00000008u + #define _HPI_HPIC_HRDY_SHIFT 0x00000003u + #define HPI_HPIC_HRDY_DEFAULT 0x00000001u + #define HPI_HPIC_HRDY_OF(x) _VALUEOF(x) + #define HPI_HPIC_HRDY_0 0x00000000u + #define HPI_HPIC_HRDY_1 0x00000001u + + #define _HPI_HPIC_HINT_MASK 0x00000004u + #define _HPI_HPIC_HINT_SHIFT 0x00000002u + #define HPI_HPIC_HINT_DEFAULT 0x00000000u + #define HPI_HPIC_HINT_OF(x) _VALUEOF(x) + #define HPI_HPIC_HINT_0 0x00000000u + #define HPI_HPIC_HINT_1 0x00000001u + + #define _HPI_HPIC_DSPINT_MASK 0x00000002u + #define _HPI_HPIC_DSPINT_SHIFT 0x00000001u + #define HPI_HPIC_DSPINT_DEFAULT 0x00000000u + #define HPI_HPIC_DSPINT_OF(x) _VALUEOF(x) + #define HPI_HPIC_DSPINT_0 0x00000000u + #define HPI_HPIC_DSPINT_1 0x00000001u + + #define _HPI_HPIC_HWOB_MASK 0x00000001u + #define _HPI_HPIC_HWOB_SHIFT 0x00000000u + #define HPI_HPIC_HWOB_DEFAULT 0x00000000u + #define HPI_HPIC_HWOB_OF(x) _VALUEOF(x) + #define HPI_HPIC_HWOB_0 0x00000000u + #define HPI_HPIC_HWOB_1 0x00000001u + + #define HPI_HPIC_OF(x) _VALUEOF(x) + + #define HPI_HPIC_DEFAULT (Uint32)( \ + _PER_FDEFAULT(HPI,HPIC,FETCH) \ + |_PER_FDEFAULT(HPI,HPIC,HRDY) \ + |_PER_FDEFAULT(HPI,HPIC,HINT) \ + |_PER_FDEFAULT(HPI,HPIC,DSPINT) \ + |_PER_FDEFAULT(HPI,HPIC,HWOB) \ + ) + + #define HPI_HPIC_RMK(hint,dspint) (Uint32)( \ + _PER_FMK(HPI,HPIC,HINT,hint) \ + |_PER_FMK(HPI,HPIC,DSPINT,dspint) \ + ) + + #define _HPI_HPIC_FGET(FIELD)\ + _PER_FGET(_HPI_HPIC_ADDR,HPI,HPIC,##FIELD) + + #define _HPI_HPIC_FSET(FIELD,field)\ + _PER_FSET(_HPI_HPIC_ADDR,HPI,HPIC,##FIELD,field) + + #define _HPI_HPIC_FSETS(FIELD,SYM)\ + _PER_FSETS(_HPI_HPIC_ADDR,HPI,HPIC,##FIELD,##SYM) +/******************************************************************************\ +* _____________________ +* | | +* | H P I A W | +* |___________________| +* +* HPIAW - HPI Address Write register +* +* FIELDS (msb -> lsb) +* (rw) HPIAW +* +\******************************************************************************/ + #if (C64_SUPPORT) + #define _HPI_HPIAW_OFFSET 1 + #define _HPI_HPIAW_ADDR 0x01880004u + + #define _HPI_HPIAW_HPIAW_MASK 0xFFFFFFFCu + #define _HPI_HPIAW_HPIAW_SHIFT 0x00000000u + #define HPI_HPIAW_HPIAW_DEFAULT 0x00000000u + #define HPI_HPIAW_HPIAW_OF(x) _VALUEOF(x) + + #define HPI_HPIAW_DEFAULT (Uint32)( \ + _PER_FDEFAULT(HPI,HPIAW,HPIAW) \ + ) + + #define HPI_HPIAW_RMK(hpiaw) (Uint32)( \ + _PER_FMK(HPI,HPIAW,HPIAW,hpiaw) \ + ) + + #define _HPI_HPIAW_FGET(FIELD)\ + _PER_FGET(_HPI_HPIAW_ADDR,HPI,HPIAW,##FIELD) + + #define _HPI_HPIAW_FSET(FIELD,field)\ + _PER_FSET(_HPI_HPIAW_ADDR,HPI,HPIAW,##FIELD,field) + + #define _HPI_HPIAW_FSETS(FIELD,SYM)\ + _PER_FSETS(_HPI_HPIAW_ADDR,HPI,HPIAW,##FIELD,##SYM) + +#endif /* C64_SUPPORT */ +/******************************************************************************\ +* _____________________ +* | | +* | H P I A R | +* |___________________| +* +* HPIAR - HPI Address Read register +* +* FIELDS (msb -> lsb) +* (rw) HPIAR +* +\******************************************************************************/ + #if (C64_SUPPORT) + #define _HPI_HPIAR_OFFSET 2 + #define _HPI_HPIAR_ADDR 0x01880008u + + #define _HPI_HPIAR_HPIAR_MASK 0xFFFFFFFCu + #define _HPI_HPIAR_HPIAR_SHIFT 0x00000000u + #define HPI_HPIAR_HPIAR_DEFAULT 0x00000000u + #define HPI_HPIAR_HPIAR_OF(x) _VALUEOF(x) + + #define HPI_HPIAR_DEFAULT (Uint32)( \ + _PER_FDEFAULT(HPI,HPIAR,HPIAR) \ + ) + + #define HPI_HPIAR_RMK(hpiar) (Uint32)( \ + _PER_FMK(HPI,HPIAR,HPIAR,hpiar) \ + ) + + #define _HPI_HPIAR_FGET(FIELD)\ + _PER_FGET(_HPI_HPIAR_ADDR,HPI,HPIAR,##FIELD) + + #define _HPI_HPIAR_FSET(FIELD,field)\ + _PER_FSET(_HPI_HPIAR_ADDR,HPI,HPIAR,##FIELD,field) + + #define _HPI_HPIAR_FSETS(FIELD,SYM)\ + _PER_FSETS(_HPI_HPIAR_ADDR,HPI,HPIAR,##FIELD,##SYM) + +#endif /* C64_SUPPORT */ + +/******************************************************************************\ +* _____________________ +* | | +* | T R C T L | +* |___________________| +* +* TRCTL - TR Control register +* +* FIELDS (msb -> lsb) +* (rw) TRSTALL +* (rw) PRI +* (rw) PALLOC +* +\******************************************************************************/ + #if (C64_SUPPORT) + #define _HPI_TRCTL_OFFSET 16384 + #define _HPI_TRCTL_ADDR 0x018A0000u + + #define _HPI_TRCTL_TRSTALL_MASK 0x00000100u + #define _HPI_TRCTL_TRSTALL_SHIFT 0x00000008u + #define HPI_TRCTL_TRSTALL_DEFAULT 0x00000000u + #define HPI_TRCTL_TRSTALL_OF(x) _VALUEOF(x) + + #define _HPI_TRCTL_PRI_MASK 0x00000030u + #define _HPI_TRCTL_PRI_SHIFT 0x00000004u + #define HPI_TRCTL_PRI_DEFAULT 0x00000002u + #define HPI_TRCTL_PRI_OF(x) _VALUEOF(x) + + #define _HPI_TRCTL_PALLOC_MASK 0x0000000Fu + #define _HPI_TRCTL_PALLOC_SHIFT 0x00000000u + #define HPI_TRCTL_PALLOC_DEFAULT 0x00000004u + #define HPI_TRCTL_PALLOC_OF(x) _VALUEOF(x) + + #define HPI_TRCTL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(HPI,TRCTL,TRSTALL) \ + |_PER_FDEFAULT(HPI,TRCTL,PRI) \ + |_PER_FDEFAULT(HPI,TRCTL,PALLOC) \ + ) + + #define HPI_TRCTL_RMK(trstall,pri,palloc) (Uint32)( \ + _PER_FMK(HPI,TRCTL,TRSTALL,trstall) \ + |_PER_FMK(HPI,TRCTL,PRI,pri) \ + |_PER_FMK(HPI,TRCTL,PALLOC,palloc) \ + ) + + #define _HPI_TRCTL_FGET(FIELD)\ + _PER_FGET(_HPI_TRCTL_ADDR,HPI,TRCTL,##FIELD) + + #define _HPI_TRCTL_FSET(FIELD,field)\ + _PER_FSET(_HPI_TRCTL_ADDR,HPI,TRCTL,##FIELD,field) + + #define _HPI_TRCTL_FSETS(FIELD,SYM)\ + _PER_FSETS(_HPI_TRCTL_ADDR,HPI,TRCTL,##FIELD,##SYM) + +#endif /* C64_SUPPORT */ + + + +/*----------------------------------------------------------------------------*/ + +#endif /* HPI_SUPPORT */ +#endif /* _CSL_HPIHAL_H_ */ +/******************************************************************************\ +* End of csl_hpihal.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_i2c.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_i2c.h new file mode 100644 index 0000000..2744b60 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_i2c.h @@ -0,0 +1,487 @@ +/******************************************************************************\ +* Copyright (C) 1999-2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_i2c.h +* DATE CREATED.. 06/11/1999 +* LAST MODIFIED. 08/02/2004 - Adding support for C6418 +* 13/03/2002 - added I2C_outOfReset() +* 01/08/2003 - Removing unused variable 'I2C_isrDispatchTable[6]' +\******************************************************************************/ +#ifndef _CSL_I2C_H_ +#define _CSL_I2C_H_ + +#include +#include +#include + + +/* defining i2cimr as i2cier for backward compatibility */ + +#define i2cimr i2cier + +#if (I2C_SUPPORT) +/******************************************************************************\ +* scope and inline control macros +\******************************************************************************/ +#ifdef __cplusplus +#define CSLAPI extern "C" far +#else +#define CSLAPI extern far +#endif + +#undef USEDEFS +#undef IDECL +#undef IDEF + +#ifdef _I2C_MOD_ + #define IDECL CSLAPI + #define USEDEFS + #define IDEF +#else + #ifdef _INLINE + #define IDECL static inline + #define USEDEFS + #define IDEF static inline + #else + #define IDECL CSLAPI + #endif +#endif + + +/******************************************************************************\ +* global macro declarations +\******************************************************************************/ + +/* I2C_open() flags */ +#define I2C_OPEN_RESET (0x00000001) + +/* device identifiers for I2C_open() */ + +#if (CHIP_6713 | CHIP_DA610 | CHIP_6413 | CHIP_6418 | CHIP_6410) + #define I2C_DEV0 (0) + #define I2C_DEV1 (1) +#endif + +#if (CHIP_DM642 | CHIP_DM641 | CHIP_DM640 | CHIP_6412) + #define I2C_DEV0 (0) +#endif + +/* device identifiers for I2C_open() */ + +#if (CHIP_6713 | CHIP_DA610 | CHIP_6413 | CHIP_6418 | CHIP_6410) + #define I2C_PORT0 I2C_DEV0 + #define I2C_PORT1 I2C_DEV1 +#endif + +#if (CHIP_DM642 | CHIP_DM641 | CHIP_DM640 | CHIP_6412) + #define I2C_PORT0 I2C_DEV0 +#endif + +/* error codes */ +#define I2C_ERR_ALLOC (0x00000000) +#define I2C_ERR_INVALID_HANDLE (0x00000001) + +#define I2C_EVT_AL 0x01 // Arbitration win/lose +#define I2C_EVT_NACK 0x02 // No acknowledgement +#define I2C_EVT_ARDY 0x03 // register access ready +#define I2C_EVT_ICRRDY 0x04 // receive data ready +#define I2C_EVT_ICXRDY 0x05 // transmit data ready + +#if (CHIP_6413 | CHIP_6418 | CHIP_6410) + #define I2C_EVT_SCD 0x06 // stop condition detect + #define I2C_EVT_AAS 0x07 // address as slave +#endif + +/******************************************************************************\ +* global typedef declarations +\******************************************************************************/ + +/* device handle object */ +typedef struct { + Uint32 allocated; + Uint32 eventId; + volatile Uint32 *baseAddr; + Uint32 i2cdrrAddr; + Uint32 i2cdxrAddr; +} I2C_Obj, *I2C_Handle; + +/* device configuration structure */ +typedef struct { + Uint32 i2coar; + Uint32 i2cier; + Uint32 i2cclkl; + Uint32 i2cclkh; + Uint32 i2ccnt; + Uint32 i2csar; + Uint32 i2cmdr; + Uint32 i2cpsc; +#if (CHIP_6413 | CHIP_6418 | CHIP_6410) + Uint32 i2cemdr; + Uint32 i2cpfunc; + Uint32 i2cpdir; +#endif +} I2C_Config; + +typedef struct { + Uint32 addrmode; /* 7 or 10 bit address mode */ + Uint32 ownaddr; /* don't care if master */ + Uint32 sysinclock; /* clkout value (Mhz) */ + Uint32 rate; /* a number between 10 and 400 in kbps*/ + Uint32 bitbyte; /* number of bits/byte to be received or transmitted */ + Uint32 dlb; /* digital loopback mode */ + Uint32 free; /* free mode */ +} I2C_Init; + + +/******************************************************************************\ +* global variable declarations +\******************************************************************************/ + +/******************************************************************************\ +* global function declarations +\******************************************************************************/ +CSLAPI void I2C_reset(I2C_Handle hI2c); +CSLAPI void I2C_resetAll(); +CSLAPI I2C_Handle I2C_open(int devNum, Uint32 flags); +CSLAPI void I2C_close(I2C_Handle hI2c); +//CSLAPI void I2C_init(I2C_Init *init); + +/******************************************************************************\ +* inline function declarations +\******************************************************************************/ +IDECL Uint32 I2C_getXmtAddr(I2C_Handle hI2c); +IDECL Uint32 I2C_getRcvAddr(I2C_Handle hI2c); +IDECL Uint32 I2C_getEventId(I2C_Handle hI2c); +IDECL Uint32 I2C_rfull(I2C_Handle hI2c); +IDECL Uint32 I2C_rrdy(I2C_Handle hI2c); +IDECL Uint32 I2C_xempty(I2C_Handle hI2c); +IDECL Uint32 I2C_xrdy(I2C_Handle hI2c); +IDECL Uint32 I2C_bb(I2C_Handle hI2c); + +IDECL void I2C_writeByte(I2C_Handle hI2c, Uint8 val); +IDECL Uint8 I2C_readByte(I2C_Handle hI2c); + +IDECL void I2C_sendStop(I2C_Handle hI2c); +IDECL void I2C_start(I2C_Handle hI2c); +IDECL void I2C_outOfReset(I2C_Handle hI2c); + +IDECL Uint32 I2C_intClear(I2C_Handle hI2c); +IDECL void I2C_intClearAll(I2C_Handle hI2c); +IDECL void I2C_intEvtEnable(I2C_Handle hI2c,Uint32 maskFlag); +IDECL void I2C_intEvtDisable(I2C_Handle hI2c,Uint32 unmaskFlag); + +IDECL void I2C_config(I2C_Handle hI2c,I2C_Config *config); + +#if (CHIP_6413 | CHIP_6418 | CHIP_6410) + IDECL void I2C_configArgs(I2C_Handle hI2c,Uint32 i2coar,Uint32 i2cier,Uint32 i2cclkl, + Uint32 i2cclkh,Uint32 i2ccnt,Uint32 i2csar,Uint32 i2cmdr, + Uint32 i2cpsc,Uint32 i2cemdr,Uint32 i2cpfunc,Uint32 i2cpdir); +#else + IDECL void I2C_configArgs(I2C_Handle hI2c,Uint32 i2coar,Uint32 i2cier,Uint32 i2cclkl, + Uint32 i2cclkh,Uint32 i2ccnt,Uint32 i2csar,Uint32 i2cmdr, + Uint32 i2cpsc); + +#endif +IDECL void I2C_getConfig(I2C_Handle hI2c,I2C_Config *config); + + +/******************************************************************************\ +* inline function definitions +\******************************************************************************/ +#ifdef USEDEFS +#if (CHIP_6413 | CHIP_6418 | CHIP_6410) +/*----------------------------------------------------------------------------*/ +IDEF Uint32 I2C_getPins(I2C_Handle hI2c) { + return I2C_RGETH(hI2c,I2CPDIN); +} +/*----------------------------------------------------------------------------*/ +IDEF void I2C_setPins(I2C_Handle hI2c,Uint32 pins) { + I2C_RSETH(hI2c,I2CPDSET, + ( + I2C_FMK(I2CPDSET, SCLOUT, pins>>_I2C_I2CPDSET_SCLOUT_SHIFT) + |I2C_FMK(I2CPDSET, SDAOUT, pins>>_I2C_I2CPDSET_SDAOUT_SHIFT) + ) + ); +} +IDEF void I2C_clearPins(I2C_Handle hI2c,Uint32 pins) { + I2C_RSETH(hI2c,I2CPDCLR, + ( + I2C_FMK(I2CPDCLR, SCLOUT, pins>>_I2C_I2CPDCLR_SCLOUT_SHIFT) + |I2C_FMK(I2CPDCLR, SDAOUT, pins>>_I2C_I2CPDCLR_SDAOUT_SHIFT) + ) + ); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 I2C_getExtMode(I2C_Handle hI2C) { + return I2C_FGETH(hI2C,I2CEMDR,XRDYM); +} +/*----------------------------------------------------------------------------*/ +IDEF void I2C_setMstAck(I2C_Handle hI2C) { + I2C_FSETSH(hI2C,I2CEMDR,XRDYM,MSTACK); +} +/*----------------------------------------------------------------------------*/ +IDEF void I2C_setDxrCpy(I2C_Handle hI2C) { + I2C_FSETSH(hI2C,I2CEMDR,XRDYM,DXRCPY); +} +#endif +/*----------------------------------------------------------------------------*/ +IDEF Uint32 I2C_getXmtAddr(I2C_Handle hI2c) { + return (Uint32)(hI2c->i2cdxrAddr); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 I2C_getRcvAddr(I2C_Handle hI2c) { + return (Uint32)(hI2c->i2cdrrAddr); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 I2C_getEventId(I2C_Handle hI2c) { + return (Uint32)(hI2c->eventId); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 I2C_rfull(I2C_Handle hI2c){ + return I2C_FGETH(hI2c,I2CSTR,RSFULL); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 I2C_rrdy(I2C_Handle hI2c){ + return I2C_FGETH(hI2c,I2CSTR,ICRRDY); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 I2C_xempty(I2C_Handle hI2c){ + return I2C_FGETH(hI2c,I2CSTR,XSMT); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 I2C_xrdy(I2C_Handle hI2c){ + return I2C_FGETH(hI2c,I2CSTR,ICXRDY); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 I2C_bb(I2C_Handle hI2c){ + return I2C_FGETH(hI2c,I2CSTR,BB); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint8 I2C_readByte(I2C_Handle hI2c) { + return (*(volatile Uint8 *)(hI2c->i2cdrrAddr)); +} +/*----------------------------------------------------------------------------*/ +IDEF void I2C_writeByte(I2C_Handle hI2c, Uint8 val) { + (*(volatile Uint8 *)(hI2c->i2cdxrAddr)) = val; +} +/*----------------------------------------------------------------------------*/ +IDEF void I2C_sendStop(I2C_Handle hI2c){ + I2C_FSETSH(hI2c,I2CMDR,STP,STOP); +} +/*----------------------------------------------------------------------------*/ +IDEF void I2C_start(I2C_Handle hI2c){ + I2C_FSETSH(hI2c,I2CMDR,STT,START); +} +/*----------------------------------------------------------------------------*/ +IDEF void I2C_outOfReset(I2C_Handle hI2c){ + I2C_FSETSH(hI2c,I2CMDR,IRS,NRST); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 I2C_intClear(I2C_Handle hI2c){ + return I2C_RGETH(hI2c,I2CISRC); +} +/*----------------------------------------------------------------------------*/ +IDEF void I2C_intClearAll(I2C_Handle hI2c){ + Uint32 x=I2C_RGETH(hI2c,I2CISRC); + while(x != 0) { x=I2C_RGETH(hI2c,I2CISRC); } +} +/*----------------------------------------------------------------------------*/ +IDEF void I2C_intEvtEnable(I2C_Handle hI2c,Uint32 maskFlag){ + + Uint32 newMask; + + newMask = I2C_RGETH(hI2c,I2CIER) | maskFlag; + I2C_RSETH(hI2c,I2CIER,newMask); + IRQ_enable(hI2c->eventId); + +} +/*----------------------------------------------------------------------------*/ +IDEF void I2C_intEvtDisable(I2C_Handle hI2c,Uint32 unmaskFlag){ + + Uint32 newMask; + + newMask = I2C_RGETH(hI2c,I2CIER) & unmaskFlag; + I2C_RSETH(hI2c,I2CIER,newMask); + + #if (CHIP_6410 | CHIP_6413| CHIP_6418 ) + if(!(I2C_RGETH(hI2c,I2CIER) & 0x0000007F)) + #else + if(!(I2C_RGETH(hI2c,I2CIER) & 0x0000001F)) + #endif + IRQ_disable(hI2c->eventId); +} +/*----------------------------------------------------------------------------*/ + +IDEF void I2C_config(I2C_Handle hI2c, I2C_Config *config) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)(hI2c->baseAddr); + register int x0,x1,x2,x3,x4,x5,x6,x7; +#if (CHIP_6413 | CHIP_6418 | CHIP_6410) + register int x8,x9,x10; +#endif + + gie = IRQ_globalDisable(); + + /* the compiler generates more efficient code if the loads */ + /* and stores are grouped together rather than intermixed */ + x0 = config->i2coar; + x1 = config->i2cier; + x2 = config->i2cclkl; + x3 = config->i2cclkh; + x4 = config->i2ccnt; + x5 = config->i2csar; + x6 = config->i2cpsc; + x7 = config->i2cmdr; +#if (CHIP_6413 | CHIP_6418 | CHIP_6410) + x8 = config->i2cemdr; + x9 = config->i2cpfunc; + x10 = config->i2cpdir; +#endif + + base[_I2C_I2COAR_OFFSET] = x0; + base[_I2C_I2CIER_OFFSET] = x1; + base[_I2C_I2CCLKL_OFFSET] = x2; + base[_I2C_I2CCLKH_OFFSET] = x3; + base[_I2C_I2CCNT_OFFSET] = x4; + base[_I2C_I2CSAR_OFFSET] = x5; + base[_I2C_I2CPSC_OFFSET] = x6; + base[_I2C_I2CMDR_OFFSET] = x7; +#if (CHIP_6413 | CHIP_6418 | CHIP_6410) + base[_I2C_I2CEMDR_OFFSET] = x8; + base[_I2C_I2CPFUNC_OFFSET] = x9; + base[_I2C_I2CPDIR_OFFSET] = x10; +#endif + + IRQ_globalRestore(gie); +} +/*----------------------------------------------------------------------------*/ +#if (CHIP_6413 | CHIP_6418 | CHIP_6410) +IDEF void I2C_configArgs(I2C_Handle hI2c,Uint32 i2coar,Uint32 i2cier,Uint32 i2cclkl, + Uint32 i2cclkh,Uint32 i2ccnt,Uint32 i2csar,Uint32 i2cmdr, + Uint32 i2cpsc,Uint32 i2cemdr,Uint32 i2cpfunc,Uint32 i2cpdir){ + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)(hI2c->baseAddr); + + gie = IRQ_globalDisable(); + + base[_I2C_I2COAR_OFFSET] = i2coar; + base[_I2C_I2CIER_OFFSET] = i2cier; + base[_I2C_I2CCLKL_OFFSET] = i2cclkl; + base[_I2C_I2CCLKH_OFFSET] = i2cclkh; + base[_I2C_I2CCNT_OFFSET] = i2ccnt; + base[_I2C_I2CSAR_OFFSET] = i2csar; + base[_I2C_I2CPSC_OFFSET] = i2cpsc; + base[_I2C_I2CMDR_OFFSET] = i2cmdr; + base[_I2C_I2CEMDR_OFFSET] = i2cemdr; + base[_I2C_I2CPFUNC_OFFSET] = i2cpfunc; + base[_I2C_I2CPDIR_OFFSET] = i2cpdir; + + IRQ_globalRestore(gie); +} +#else +IDEF void I2C_configArgs(I2C_Handle hI2c,Uint32 i2coar,Uint32 i2cier, +Uint32 i2cclkl,Uint32 i2cclkh,Uint32 i2ccnt,Uint32 i2csar, +Uint32 i2cmdr,Uint32 i2cpsc){ + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)(hI2c->baseAddr); + + gie = IRQ_globalDisable(); + + base[_I2C_I2COAR_OFFSET] = i2coar; + base[_I2C_I2CIER_OFFSET] = i2cier; + base[_I2C_I2CCLKL_OFFSET] = i2cclkl; + base[_I2C_I2CCLKH_OFFSET] = i2cclkh; + base[_I2C_I2CCNT_OFFSET] = i2ccnt; + base[_I2C_I2CSAR_OFFSET] = i2csar; + base[_I2C_I2CPSC_OFFSET] = i2cpsc; + base[_I2C_I2CMDR_OFFSET] = i2cmdr; + + IRQ_globalRestore(gie); +} +#endif +/*----------------------------------------------------------------------------*/ +#if (CHIP_6413 | CHIP_6418 | CHIP_6410) +IDEF void I2C_getConfig(I2C_Handle hI2c, I2C_Config *config) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)(hI2c->baseAddr); + register int x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10; + + gie = IRQ_globalDisable(); + + /* the compiler generates more efficient code if the loads */ + /* and stores are grouped together rather than intermixed */ + + x0 = base[_I2C_I2COAR_OFFSET]; + x1 = base[_I2C_I2CIER_OFFSET]; + x2 = base[_I2C_I2CCLKL_OFFSET]; + x3 = base[_I2C_I2CCLKH_OFFSET]; + x4 = base[_I2C_I2CCNT_OFFSET]; + x5 = base[_I2C_I2CSAR_OFFSET]; + x6 = base[_I2C_I2CMDR_OFFSET]; + x7 = base[_I2C_I2CPSC_OFFSET]; + x8 = base[_I2C_I2CEMDR_OFFSET]; + x9 = base[_I2C_I2CPFUNC_OFFSET]; + x10 = base[_I2C_I2CPDIR_OFFSET]; + + config->i2coar = x0; + config->i2cier = x1; + config->i2cclkl = x2; + config->i2cclkh = x3; + config->i2ccnt = x4; + config->i2csar = x5; + config->i2cmdr = x6; + config->i2cpsc = x7; + config->i2cemdr = x8; + config->i2cpfunc = x9; + config->i2cpdir = x10; + + IRQ_globalRestore(gie); +} +#else +IDEF void I2C_getConfig(I2C_Handle hI2c, I2C_Config *config) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)(hI2c->baseAddr); + register int x0,x1,x2,x3,x4,x5,x6,x7; + + gie = IRQ_globalDisable(); + + /* the compiler generates more efficient code if the loads */ + /* and stores are grouped together rather than intermixed */ + + x0 = base[_I2C_I2COAR_OFFSET]; + x1 = base[_I2C_I2CIER_OFFSET]; + x2 = base[_I2C_I2CCLKL_OFFSET]; + x3 = base[_I2C_I2CCLKH_OFFSET]; + x4 = base[_I2C_I2CCNT_OFFSET]; + x5 = base[_I2C_I2CSAR_OFFSET]; + x6 = base[_I2C_I2CMDR_OFFSET]; + x7 = base[_I2C_I2CPSC_OFFSET]; + + config->i2coar = x0; + config->i2cier = x1; + config->i2cclkl = x2; + config->i2cclkh = x3; + config->i2ccnt = x4; + config->i2csar = x5; + config->i2cmdr = x6; + config->i2cpsc = x7; + + IRQ_globalRestore(gie); +} +#endif +/*----------------------------------------------------------------------------*/ +#endif /* USEDEFS */ + + +#endif /* I2C_SUPPORT */ +#endif /* _CSL_I2C_H_ */ +/******************************************************************************\ +* End of csl_i2c.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_i2chal.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_i2chal.h new file mode 100644 index 0000000..0094e4c --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_i2chal.h @@ -0,0 +1,1842 @@ +/******************************************************************************\ +* Copyright (C) 1999-2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_i2chal.h +* DATE CREATED.. 10/02/2001 +* LAST MODIFIED. 08/02/2004 - Adding support for C6418 +* 11/19/2001 register renaming +* 11/09/2001 update bit field names +* 07/02/2003 update to latest spec. +*------------------------------------------------------------------------------ +* REGISTERS +* +* I2COAR0 - I2C0 Own Address register +* I2COAR1 - I2C1 Own Address register +* I2CIER0 - I2C0 Interrupt Mask/Status register +* I2CIER1 - I2C1 Interrupt Mask/Status register +* I2CSTR0 - I2C0 Interrupt Status register +* I2CSTR1 - I2C1 Interrupt Status register +* I2CCLKL0 - I2C0 Clock Divider Low register +* I2CCLKL1 - I2C1 Clock Divider Low register +* I2CCLKH0 - I2C0 Clock Divider High register +* I2CCLKH1 - I2C1 Clock Divider High register +* I2CCNT0 - I2C0 Data Count register +* I2CCNT1 - I2C1 Data Count register +* I2CDRR0 - I2C0 Data Receive register +* I2CDRR1 - I2C1 Data Receive register +* I2CSAR0 - I2C0 Slave Address register +* I2CSAR1 - I2C1 Slave Address register +* I2CDXR0 - I2C0 Data Transmit register +* I2CDXR1 - I2C1 Data Transmit register +* I2CMDR0 - I2C0 Mode register +* I2CMDR1 - I2C1 Mode register +* I2CISRC0 - I2C0 Interrupt Vector register +* I2CISRC1 - I2C1 Interrupt Vector register +* I2CEMDR0 - I2C0 Extended Mode register(1) +* I2CEMDR1 - I2C1 Extended Mode register(1) +* I2CPSC0 - I2C0 Prescaler register +* I2CPSC1 - I2C1 Prescaler register +* I2CPID10 - I2C0 Peripheral ID register 1(1) +* I2CPID11 - I2C1 Peripheral ID register 1(1) +* I2CPID20 - I2C0 Peripheral ID register 2(1) +* I2CPID21 - I2C1 Peripheral ID register 2(1) +* I2CPFUNC0 - I2C0 Peripheral Functional register(1) +* I2CPFUNC1 - I2C1 Peripheral Functional register(1) +* I2CPDIR0 - I2C0 Pin Direction register(1) +* I2CPDIR1 - I2C1 Pin Direction register(1) +* I2CPDIN0 - I2C0 Pin Data In register(1) +* I2CPDIN1 - I2C1 Pin Data In register(1) +* I2CPDOUT0 - I2C0 Pin Data Out register(1) +* I2CPDOUT1 - I2C1 Pin Data Out register(1) +* I2CPDSET0 - I2C0 Pin Data Set register(1) +* I2CPDSET1 - I2C1 Pin Data Set register(1) +* I2CPDCLR0 - I2C0 Pin Data Clear register(1) +* I2CPDCLR1 - I2C1 Pin Data Clear register(1) +* +* (1) For C6418/C6413/C6410 only +\******************************************************************************/ +#ifndef _CSL_I2CHAL_H_ +#define _CSL_I2CHAL_H_ + +#include +#include +#if (I2C_SUPPORT) +/******************************************************************************\ +* MISC section +\******************************************************************************/ +#if (CHIP_6713 | CHIP_DA610 | CHIP_6413 | CHIP_6418 | CHIP_6410) + #define _I2C_PORT_CNT 2 + #define _I2C_BASE_PORT0 0x01B40000u + #define _I2C_BASE_PORT1 0x01B44000u +#endif + +#if (CHIP_DM642 | CHIP_DM641 | CHIP_DM640 | CHIP_6412) + #define _I2C_PORT_CNT 1 + #define _I2C_BASE_PORT0 0x01B40000u +#endif + + +/******************************************************************************\ +* module level register/field access macros +\******************************************************************************/ + + /* ----------------- */ + /* FIELD MAKE MACROS */ + /* ----------------- */ + + #define I2C_FMK(REG,FIELD,x)\ + _PER_FMK(I2C,##REG,##FIELD,x) + + #define I2C_FMKS(REG,FIELD,SYM)\ + _PER_FMKS(I2C,##REG,##FIELD,##SYM) + + + /* -------------------------------- */ + /* RAW REGISTER/FIELD ACCESS MACROS */ + /* -------------------------------- */ + + #define I2C_ADDR(REG)\ + _I2C_##REG##_ADDR + + #define I2C_RGET(REG)\ + _PER_RGET(_I2C_##REG##_ADDR,I2C,##REG) + + #define I2C_RSET(REG,x)\ + _PER_RSET(_I2C_##REG##_ADDR,I2C,##REG,x) + + #define I2C_FGET(REG,FIELD)\ + _I2C_##REG##_FGET(##FIELD) + + #define I2C_FSET(REG,FIELD,x)\ + _I2C_##REG##_FSET(##FIELD,##x) + + #define I2C_FSETS(REG,FIELD,SYM)\ + _I2C_##REG##_FSETS(##FIELD,##SYM) + + + /* ------------------------------------------ */ + /* ADDRESS BASED REGISTER/FIELD ACCESS MACROS */ + /* ------------------------------------------ */ + + #define I2C_RGETA(addr,REG)\ + _PER_RGET(addr,I2C,##REG) + + #define I2C_RSETA(addr,REG,x)\ + _PER_RSET(addr,I2C,##REG,x) + + #define I2C_FGETA(addr,REG,FIELD)\ + _PER_FGET(addr,I2C,##REG,##FIELD) + + #define I2C_FSETA(addr,REG,FIELD,x)\ + _PER_FSET(addr,I2C,##REG,##FIELD,x) + + #define I2C_FSETSA(addr,REG,FIELD,SYM)\ + _PER_FSETS(addr,I2C,##REG,##FIELD,##SYM) + + + /* ----------------------------------------- */ + /* HANDLE BASED REGISTER/FIELD ACCESS MACROS */ + /* ----------------------------------------- */ + + #define I2C_ADDRH(h,REG)\ + (Uint32)(&((h)->baseAddr[_I2C_##REG##_OFFSET])) + + #define I2C_RGETH(h,REG)\ + I2C_RGETA(I2C_ADDRH(h,##REG),##REG) + + + #define I2C_RSETH(h,REG,x)\ + I2C_RSETA(I2C_ADDRH(h,##REG),##REG,x) + + + #define I2C_FGETH(h,REG,FIELD)\ + I2C_FGETA(I2C_ADDRH(h,##REG),##REG,##FIELD) + + + #define I2C_FSETH(h,REG,FIELD,x)\ + I2C_FSETA(I2C_ADDRH(h,##REG),##REG,##FIELD,x) + + + #define I2C_FSETSH(h,REG,FIELD,SYM)\ + I2C_FSETSA(I2C_ADDRH(h,##REG),##REG,##FIELD,##SYM) + + + +/******************************************************************************\ +* ___________________ +* | | +* | I 2 C O A R | +* |___________________| +* +* I2COAR0 - I2C0 Own Address register +* I2COAR1 - I2C1 Own Address register +* +* FIELDS (msb -> lsb) +* (rw) A +* +\******************************************************************************/ + #define _I2C_I2COAR_OFFSET 0 + + #define _I2C_I2COAR0_ADDR 0x01B40000 + #define _I2C_I2COAR1_ADDR 0x01B44000 + + #define _I2C_I2COAR_A_MASK 0x000003FFu + #define _I2C_I2COAR_A_SHIFT 0x00000000u + #define I2C_I2COAR_A_DEFAULT 0x00000000u + #define I2C_I2COAR_A_OF(x) _VALUEOF(x) + + #define I2C_I2COAR_OF(x) _VALUEOF(x) + + #define I2C_I2COAR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(I2C,I2COAR,A)\ + ) + + #define I2C_I2COAR_RMK(a) (Uint32)(\ + _PER_FMK(I2C,I2COAR,A,a)\ + ) + + #define _I2C_I2COAR_FGET(N,FIELD)\ + _PER_FGET(_I2C_I2COAR##N##_ADDR,I2C,I2COAR,##FIELD) + + #define _I2C_I2COAR_FSET(N,FIELD,field)\ + _PER_FSET(_I2C_I2COAR##N##_ADDR,I2C,I2COAR,##FIELD,field) + + #define _I2C_I2COAR_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_I2C_I2COAR##N##_ADDR,I2C,I2COAR,##FIELD,##SYM) + + #define _I2C_I2COAR0_FGET(FIELD) _I2C_I2COAR_FGET(0,##FIELD) + #define _I2C_I2COAR1_FGET(FIELD) _I2C_I2COAR_FGET(1,##FIELD) + + #define _I2C_I2COAR0_FSET(FIELD,f) _I2C_I2COAR_FSET(0,##FIELD,f) + #define _I2C_I2COAR1_FSET(FIELD,f) _I2C_I2COAR_FSET(1,##FIELD,f) + + #define _I2C_I2COAR0_FSETS(FIELD,SYM) _I2C_I2COAR_FSETS(0,##FIELD,##SYM) + #define _I2C_I2COAR1_FSETS(FIELD,SYM) _I2C_I2COAR_FSETS(1,##FIELD,##SYM) + +/******************************************************************************\ +* (Keeping the old definitions for backward compatibility) +* ___________________ +* | | +* | I 2 C I M R | +* |___________________| +* +* I2CIMR0 - I2C0 Interrupt Mask/Status register +* I2CIMR1 - I2C1 Interrupt Mask/Status register +* +* FIELDS (msb -> lsb) +* (rw) ICXRDY +* (rw) ICRRDY +* (rw) ARDY +* (rw) NACK +* (rw) AL +\******************************************************************************/ +#if (!(CHIP_6410 | CHIP_6413| CHIP_6418 )) + + #define _I2C_I2CIMR_OFFSET 1 + + #define _I2C_I2CIMR0_ADDR 0x01B40004 + #define _I2C_I2CIMR1_ADDR 0x01B44004 + + #define _I2C_I2CIMR_ICXRDY_MASK 0x00000010u + #define _I2C_I2CIMR_ICXRDY_SHIFT 0x00000004u + #define I2C_I2CIMR_ICXRDY_DEFAULT 0x00000000u + #define I2C_I2CIMR_ICXRDY_OF(x) _VALUEOF(x) + #define I2C_I2CIMR_ICXRDY_MSK 0x00000000u + #define I2C_I2CIMR_ICXRDY_UNMSK 0x00000001u + + #define _I2C_I2CIMR_ICRRDY_MASK 0x00000008u + #define _I2C_I2CIMR_ICRRDY_SHIFT 0x00000003u + #define I2C_I2CIMR_ICRRDY_DEFAULT 0x00000000u + #define I2C_I2CIMR_ICRRDY_OF(x) _VALUEOF(x) + #define I2C_I2CIMR_ICRRDY_MSK 0x00000000u + #define I2C_I2CIMR_ICRRDY_UNMSK 0x00000001u + + #define _I2C_I2CIMR_ARDY_MASK 0x00000004u + #define _I2C_I2CIMR_ARDY_SHIFT 0x00000002u + #define I2C_I2CIMR_ARDY_DEFAULT 0x00000000u + #define I2C_I2CIMR_ARDY_OF(x) _VALUEOF(x) + #define I2C_I2CIMR_ARDY_MSK 0x00000000u + #define I2C_I2CIMR_ARDY_UNMSK 0x00000001u + + #define _I2C_I2CIMR_NACK_MASK 0x00000002u + #define _I2C_I2CIMR_NACK_SHIFT 0x00000001u + #define I2C_I2CIMR_NACK_DEFAULT 0x00000000u + #define I2C_I2CIMR_NACK_OF(x) _VALUEOF(x) + #define I2C_I2CIMR_NACK_MSK 0x00000000u + #define I2C_I2CIMR_NACK_UNMSK 0x00000001u + + #define _I2C_I2CIMR_AL_MASK 0x00000001u + #define _I2C_I2CIMR_AL_SHIFT 0x00000000u + #define I2C_I2CIMR_AL_DEFAULT 0x00000000u + #define I2C_I2CIMR_AL_OF(x) _VALUEOF(x) + #define I2C_I2CIMR_AL_MSK 0x00000000u + #define I2C_I2CIMR_AL_UNMSK 0x00000001u + + + #define I2C_I2CIMR_OF(x) _VALUEOF(x) + + #define I2C_I2CIMR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(I2C,I2CIMR,ICXRDY)\ + |_PER_FDEFAULT(I2C,I2CIMR,ICRRDY)\ + |_PER_FDEFAULT(I2C,I2CIMR,ARDY)\ + |_PER_FDEFAULT(I2C,I2CIMR,NACK)\ + |_PER_FDEFAULT(I2C,I2CIMR,AL)\ + ) + + #define I2C_I2CIMR_RMK(icxrdy,icrrdy,ardy,nack,al) (Uint32)(\ + _PER_FMK(I2C,I2CIMR,ICXRDY,icxrdy)\ + |_PER_FMK(I2C,I2CIMR,ICRRDY,icrrdy)\ + |_PER_FMK(I2C,I2CIMR,ARDY,ardy)\ + |_PER_FMK(I2C,I2CIMR,NACK,nack)\ + |_PER_FMK(I2C,I2CIMR,AL,al)\ + ) + + + #define _I2C_I2CIMR_FGET(N,FIELD)\ + _PER_FGET(_I2C_I2CIMR##N##_ADDR,I2C,I2CIMR,##FIELD) + + #define _I2C_I2CIMR_FSET(N,FIELD,field)\ + _PER_FSET(_I2C_I2CIMR##N##_ADDR,I2C,I2CIMR,##FIELD,field) + + #define _I2C_I2CIMR_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_I2C_I2CIMR##N##_ADDR,I2C,I2CIMR,##FIELD,##SYM) + + #define _I2C_I2CIMR0_FGET(FIELD) _I2C_I2CIMR_FGET(0,##FIELD) + #define _I2C_I2CIMR1_FGET(FIELD) _I2C_I2CIMR_FGET(1,##FIELD) + + #define _I2C_I2CIMR0_FSET(FIELD,f) _I2C_I2CIMR_FSET(0,##FIELD,f) + #define _I2C_I2CIMR1_FSET(FIELD,f) _I2C_I2CIMR_FSET(1,##FIELD,f) + + #define _I2C_I2CIMR0_FSETS(FIELD,SYM) _I2C_I2CIMR_FSETS(0,##FIELD,##SYM) + #define _I2C_I2CIMR1_FSETS(FIELD,SYM) _I2C_I2CIMR_FSETS(1,##FIELD,##SYM) +#endif + +/******************************************************************************\ +* ___________________ +* | | +* | I 2 C I E R | +* |___________________| +* +* I2CIER0 - I2C0 Interrupt Mask/Status register +* I2CIER1 - I2C1 Interrupt Mask/Status register +* +* FIELDS (msb -> lsb) +* (rw) AAS(1) +* (rw) SCD(1) +* (rw) ICXRDY +* (rw) ICRRDY +* (rw) ARDY +* (rw) NACK +* (rw) AL +* +* (1) For C6418/C6413/C6410 only +\******************************************************************************/ + #define _I2C_I2CIER_OFFSET 1 + + #define _I2C_I2CIER0_ADDR 0x01B40004 + #define _I2C_I2CIER1_ADDR 0x01B44004 + +#if (CHIP_6413 | CHIP_6418 | CHIP_6410) + #define _I2C_I2CIER_AAS_MASK 0x00000040u + #define _I2C_I2CIER_AAS_SHIFT 0x00000006u + #define I2C_I2CIER_AAS_DEFAULT 0x00000000u + #define I2C_I2CIER_AAS_OF(x) _VALUEOF(x) + #define I2C_I2CIER_AAS_MSK 0x00000000u + #define I2C_I2CIER_AAS_UNMSK 0x00000001u + + #define _I2C_I2CIER_SCD_MASK 0x00000020u + #define _I2C_I2CIER_SCD_SHIFT 0x00000005u + #define I2C_I2CIER_SCD_DEFAULT 0x00000000u + #define I2C_I2CIER_SCD_OF(x) _VALUEOF(x) + #define I2C_I2CIER_SCD_MSK 0x00000000u + #define I2C_I2CIER_SCD_UNMSK 0x00000001u +#endif + + #define _I2C_I2CIER_ICXRDY_MASK 0x00000010u + #define _I2C_I2CIER_ICXRDY_SHIFT 0x00000004u + #define I2C_I2CIER_ICXRDY_DEFAULT 0x00000000u + #define I2C_I2CIER_ICXRDY_OF(x) _VALUEOF(x) + #define I2C_I2CIER_ICXRDY_MSK 0x00000000u + #define I2C_I2CIER_ICXRDY_UNMSK 0x00000001u + + #define _I2C_I2CIER_ICRRDY_MASK 0x00000008u + #define _I2C_I2CIER_ICRRDY_SHIFT 0x00000003u + #define I2C_I2CIER_ICRRDY_DEFAULT 0x00000000u + #define I2C_I2CIER_ICRRDY_OF(x) _VALUEOF(x) + #define I2C_I2CIER_ICRRDY_MSK 0x00000000u + #define I2C_I2CIER_ICRRDY_UNMSK 0x00000001u + + #define _I2C_I2CIER_ARDY_MASK 0x00000004u + #define _I2C_I2CIER_ARDY_SHIFT 0x00000002u + #define I2C_I2CIER_ARDY_DEFAULT 0x00000000u + #define I2C_I2CIER_ARDY_OF(x) _VALUEOF(x) + #define I2C_I2CIER_ARDY_MSK 0x00000000u + #define I2C_I2CIER_ARDY_UNMSK 0x00000001u + + #define _I2C_I2CIER_NACK_MASK 0x00000002u + #define _I2C_I2CIER_NACK_SHIFT 0x00000001u + #define I2C_I2CIER_NACK_DEFAULT 0x00000000u + #define I2C_I2CIER_NACK_OF(x) _VALUEOF(x) + #define I2C_I2CIER_NACK_MSK 0x00000000u + #define I2C_I2CIER_NACK_UNMSK 0x00000001u + + #define _I2C_I2CIER_AL_MASK 0x00000001u + #define _I2C_I2CIER_AL_SHIFT 0x00000000u + #define I2C_I2CIER_AL_DEFAULT 0x00000000u + #define I2C_I2CIER_AL_OF(x) _VALUEOF(x) + #define I2C_I2CIER_AL_MSK 0x00000000u + #define I2C_I2CIER_AL_UNMSK 0x00000001u + + + #define I2C_I2CIER_OF(x) _VALUEOF(x) + +#if (!(CHIP_6413 | CHIP_6418 | CHIP_6410)) + #define I2C_I2CIER_DEFAULT (Uint32)(\ + _PER_FDEFAULT(I2C,I2CIER,ICXRDY)\ + |_PER_FDEFAULT(I2C,I2CIER,ICRRDY)\ + |_PER_FDEFAULT(I2C,I2CIER,ARDY)\ + |_PER_FDEFAULT(I2C,I2CIER,NACK)\ + |_PER_FDEFAULT(I2C,I2CIER,AL)\ + ) + + #define I2C_I2CIER_RMK(icxrdy,icrrdy,ardy,nack,al) (Uint32)(\ + _PER_FMK(I2C,I2CIER,ICXRDY,icxrdy)\ + |_PER_FMK(I2C,I2CIER,ICRRDY,icrrdy)\ + |_PER_FMK(I2C,I2CIER,ARDY,ardy)\ + |_PER_FMK(I2C,I2CIER,NACK,nack)\ + |_PER_FMK(I2C,I2CIER,AL,al)\ + ) +#else + #define I2C_I2CIER_DEFAULT (Uint32)(\ + _PER_FDEFAULT(I2C,I2CIER,AAS)\ + |_PER_FDEFAULT(I2C,I2CIER,SCD)\ + |_PER_FDEFAULT(I2C,I2CIER,ICXRDY)\ + |_PER_FDEFAULT(I2C,I2CIER,ICRRDY)\ + |_PER_FDEFAULT(I2C,I2CIER,ARDY)\ + |_PER_FDEFAULT(I2C,I2CIER,NACK)\ + |_PER_FDEFAULT(I2C,I2CIER,AL)\ + ) + + #define I2C_I2CIER_RMK(aas,scd,icxrdy,icrrdy,ardy,nack,al) (Uint32)(\ + _PER_FMK(I2C,I2CIER,AAS,aas)\ + |_PER_FMK(I2C,I2CIER,SCD,scd)\ + |_PER_FMK(I2C,I2CIER,ICXRDY,icxrdy)\ + |_PER_FMK(I2C,I2CIER,ICRRDY,icrrdy)\ + |_PER_FMK(I2C,I2CIER,ARDY,ardy)\ + |_PER_FMK(I2C,I2CIER,NACK,nack)\ + |_PER_FMK(I2C,I2CIER,AL,al)\ + ) +#endif + + #define _I2C_I2CIER_FGET(N,FIELD)\ + _PER_FGET(_I2C_I2CIER##N##_ADDR,I2C,I2CIER,##FIELD) + + #define _I2C_I2CIER_FSET(N,FIELD,field)\ + _PER_FSET(_I2C_I2CIER##N##_ADDR,I2C,I2CIER,##FIELD,field) + + #define _I2C_I2CIER_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_I2C_I2CIER##N##_ADDR,I2C,I2CIER,##FIELD,##SYM) + + #define _I2C_I2CIER0_FGET(FIELD) _I2C_I2CIER_FGET(0,##FIELD) + #define _I2C_I2CIER1_FGET(FIELD) _I2C_I2CIER_FGET(1,##FIELD) + + #define _I2C_I2CIER0_FSET(FIELD,f) _I2C_I2CIER_FSET(0,##FIELD,f) + #define _I2C_I2CIER1_FSET(FIELD,f) _I2C_I2CIER_FSET(1,##FIELD,f) + + #define _I2C_I2CIER0_FSETS(FIELD,SYM) _I2C_I2CIER_FSETS(0,##FIELD,##SYM) + #define _I2C_I2CIER1_FSETS(FIELD,SYM) _I2C_I2CIER_FSETS(1,##FIELD,##SYM) + +/******************************************************************************\ +* ___________________ +* | | +* | I 2 C S T R | +* |___________________| +* +* I2CSTR0 - I2C0 Interrupt Status register +* I2CSTR1 - I2C1 Interrupt Status register +* +* FIELDS (msb -> lsb) +* (rc) SDIR(1) +* (rc) NACKSNT +* (rc) BB +* (r) RSFULL +* (r) XSMT +* (r) AAS +* (r) AD0 +* (rc) SCD(1) +* (rc) ICXRDY +* (rc) ICRRDY +* (rc) ARDY +* (rc) NACK +* (rc) AL +* +* (1) For C6418/C6413/C6410 only +\******************************************************************************/ + #define _I2C_I2CSTR_OFFSET 2 + + #define _I2C_I2CSTR0_ADDR 0x01B40008 + #define _I2C_I2CSTR1_ADDR 0x01B44008 + +#if (CHIP_6413 | CHIP_6418 | CHIP_6410) + #define _I2C_I2CSTR_SDIR_MASK 0x00004000u + #define _I2C_I2CSTR_SDIR_SHIFT 0x0000000Eu + #define I2C_I2CSTR_SDIR_DEFAULT 0x00000000u + #define I2C_I2CSTR_SDIR_OF(x) _VALUEOF(x) + #define I2C_I2CSTR_SDIR_NONE 0x00000000u + #define I2C_I2CSTR_SDIR_INT 0x00000001u + #define I2C_I2CSTR_SDIR_CLR 0x00000001u +#endif + + #define _I2C_I2CSTR_NACKSNT_MASK 0x00002000u + #define _I2C_I2CSTR_NACKSNT_SHIFT 0x0000000Du + #define I2C_I2CSTR_NACKSNT_DEFAULT 0x00000000u + #define I2C_I2CSTR_NACKSNT_OF(x) _VALUEOF(x) + #define I2C_I2CSTR_NACKSNT_NONE 0x00000000u + #define I2C_I2CSTR_NACKSNT_INT 0x00000001u + #define I2C_I2CSTR_NACKSNT_CLR 0x00000001u + + #define _I2C_I2CSTR_BB_MASK 0x00001000u + #define _I2C_I2CSTR_BB_SHIFT 0x0000000Cu + #define I2C_I2CSTR_BB_DEFAULT 0x00000000u + #define I2C_I2CSTR_BB_OF(x) _VALUEOF(x) + #define I2C_I2CSTR_BB_NONE 0x00000000u + #define I2C_I2CSTR_BB_INT 0x00000001u + #define I2C_I2CSTR_BB_CLR 0x00000001u + + #define _I2C_I2CSTR_RSFULL_MASK 0x00000800u + #define _I2C_I2CSTR_RSFULL_SHIFT 0x0000000Bu + #define I2C_I2CSTR_RSFULL_DEFAULT 0x00000000u + #define I2C_I2CSTR_RSFULL_OF(x) _VALUEOF(x) + #define I2C_I2CSTR_RSFULL_NONE 0x00000000u + #define I2C_I2CSTR_RSFULL_INT 0x00000001u + + #define _I2C_I2CSTR_XSMT_MASK 0x00000400u + #define _I2C_I2CSTR_XSMT_SHIFT 0x0000000Au + #define I2C_I2CSTR_XSMT_DEFAULT 0x00000001u + #define I2C_I2CSTR_XSMT_OF(x) _VALUEOF(x) + #define I2C_I2CSTR_XSMT_NONE 0x00000000u + #define I2C_I2CSTR_XSMT_INT 0x00000001u + + #define _I2C_I2CSTR_AAS_MASK 0x00000200u + #define _I2C_I2CSTR_AAS_SHIFT 0x00000009u + #define I2C_I2CSTR_AAS_DEFAULT 0x00000000u + #define I2C_I2CSTR_AAS_OF(x) _VALUEOF(x) + #define I2C_I2CSTR_AAS_NONE 0x00000000u + #define I2C_I2CSTR_AAS_INT 0x00000001u + + #define _I2C_I2CSTR_AD0_MASK 0x00000100u + #define _I2C_I2CSTR_AD0_SHIFT 0x00000008u + #define I2C_I2CSTR_AD0_DEFAULT 0x00000000u + #define I2C_I2CSTR_AD0_OF(x) _VALUEOF(x) + #define I2C_I2CSTR_AD0_NONE 0x00000000u + #define I2C_I2CSTR_AD0_INT 0x00000001u + +#if (CHIP_6413 | CHIP_6418 | CHIP_6410) + #define _I2C_I2CSTR_SCD_MASK 0x00000020u + #define _I2C_I2CSTR_SCD_SHIFT 0x00000005u + #define I2C_I2CSTR_SCD_DEFAULT 0x00000000u + #define I2C_I2CSTR_SCD_OF(x) _VALUEOF(x) + #define I2C_I2CSTR_SCD_NONE 0x00000000u + #define I2C_I2CSTR_SCD_INT 0x00000001u + #define I2C_I2CSTR_SCD_CLR 0x00000001u +#endif + + #define _I2C_I2CSTR_ICXRDY_MASK 0x00000010u + #define _I2C_I2CSTR_ICXRDY_SHIFT 0x00000004u + #define I2C_I2CSTR_ICXRDY_DEFAULT 0x00000001u + #define I2C_I2CSTR_ICXRDY_OF(x) _VALUEOF(x) + #define I2C_I2CSTR_ICXRDY_NONE 0x00000000u + #define I2C_I2CSTR_ICXRDY_INT 0x00000001u + #define I2C_I2CSTR_ICXRDY_CLR 0x00000001u + + #define _I2C_I2CSTR_ICRRDY_MASK 0x00000008u + #define _I2C_I2CSTR_ICRRDY_SHIFT 0x00000003u + #define I2C_I2CSTR_ICRRDY_DEFAULT 0x00000000u + #define I2C_I2CSTR_ICRRDY_OF(x) _VALUEOF(x) + #define I2C_I2CSTR_ICRRDY_NONE 0x00000000u + #define I2C_I2CSTR_ICRRDY_INT 0x00000001u + #define I2C_I2CSTR_ICRRDY_CLR 0x00000001u + + #define _I2C_I2CSTR_ARDY_MASK 0x00000004u + #define _I2C_I2CSTR_ARDY_SHIFT 0x00000002u + #define I2C_I2CSTR_ARDY_DEFAULT 0x00000000u + #define I2C_I2CSTR_ARDY_OF(x) _VALUEOF(x) + #define I2C_I2CSTR_ARDY_NONE 0x00000000u + #define I2C_I2CSTR_ARDY_INT 0x00000001u + #define I2C_I2CSTR_ARDY_CLR 0x00000001u + + #define _I2C_I2CSTR_NACK_MASK 0x00000002u + #define _I2C_I2CSTR_NACK_SHIFT 0x00000001u + #define I2C_I2CSTR_NACK_DEFAULT 0x00000000u + #define I2C_I2CSTR_NACK_OF(x) _VALUEOF(x) + #define I2C_I2CSTR_NACK_NONE 0x00000000u + #define I2C_I2CSTR_NACK_INT 0x00000001u + #define I2C_I2CSTR_NACK_CLR 0x00000001u + + #define _I2C_I2CSTR_AL_MASK 0x00000001u + #define _I2C_I2CSTR_AL_SHIFT 0x00000000u + #define I2C_I2CSTR_AL_DEFAULT 0x00000000u + #define I2C_I2CSTR_AL_OF(x) _VALUEOF(x) + #define I2C_I2CSTR_AL_NONE 0x00000000u + #define I2C_I2CSTR_AL_INT 0x00000001u + #define I2C_I2CSTR_AL_CLR 0x00000001u + + + #define I2C_I2CSTR_OF(x) _VALUEOF(x) + +#if !(CHIP_6413 | CHIP_6418 | CHIP_6410) + #define I2C_I2CSTR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(I2C,I2CSTR,NACKSNT)\ + |_PER_FDEFAULT(I2C,I2CSTR,BB)\ + |_PER_FDEFAULT(I2C,I2CSTR,RSFULL)\ + |_PER_FDEFAULT(I2C,I2CSTR,XSMT)\ + |_PER_FDEFAULT(I2C,I2CSTR,AAS)\ + |_PER_FDEFAULT(I2C,I2CSTR,AD0)\ + |_PER_FDEFAULT(I2C,I2CSTR,ICXRDY)\ + |_PER_FDEFAULT(I2C,I2CSTR,ICRRDY)\ + |_PER_FDEFAULT(I2C,I2CSTR,ARDY)\ + |_PER_FDEFAULT(I2C,I2CSTR,NACK)\ + |_PER_FDEFAULT(I2C,I2CSTR,AL)\ + ) +#else + #define I2C_I2CSTR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(I2C,I2CSTR,SDIR)\ + |_PER_FDEFAULT(I2C,I2CSTR,NACKSNT)\ + |_PER_FDEFAULT(I2C,I2CSTR,BB)\ + |_PER_FDEFAULT(I2C,I2CSTR,RSFULL)\ + |_PER_FDEFAULT(I2C,I2CSTR,XSMT)\ + |_PER_FDEFAULT(I2C,I2CSTR,AAS)\ + |_PER_FDEFAULT(I2C,I2CSTR,AD0)\ + |_PER_FDEFAULT(I2C,I2CSTR,SCD)\ + |_PER_FDEFAULT(I2C,I2CSTR,ICXRDY)\ + |_PER_FDEFAULT(I2C,I2CSTR,ICRRDY)\ + |_PER_FDEFAULT(I2C,I2CSTR,ARDY)\ + |_PER_FDEFAULT(I2C,I2CSTR,NACK)\ + |_PER_FDEFAULT(I2C,I2CSTR,AL)\ + ) +#endif +#if !(CHIP_6413 | CHIP_6418 | CHIP_6410) + #define I2C_I2CSTR_RMK(nacksnt,bb,icxrdy,icrrdy,ardy,nack,al) (Uint32)(\ + _PER_FMK(I2C,I2CSTR,NACKSNT,nacksnt)\ + |_PER_FMK(I2C,I2CSTR,BB,bb)\ + |_PER_FMK(I2C,I2CSTR,ICXRDY,icxrdy)\ + |_PER_FMK(I2C,I2CSTR,ICRRDY,icrrdy)\ + |_PER_FMK(I2C,I2CSTR,ARDY,ardy)\ + |_PER_FMK(I2C,I2CSTR,NACK,nack)\ + |_PER_FMK(I2C,I2CSTR,AL,al)\ + ) +#else + #define I2C_I2CSTR_RMK(sdir,nacksnt,bb,scd,icxrdy,icrrdy,ardy,nack,al) (Uint32)(\ + _PER_FMK(I2C,I2CSTR,SDIR,sdir)\ + _PER_FMK(I2C,I2CSTR,NACKSNT,nacksnt)\ + |_PER_FMK(I2C,I2CSTR,BB,bb)\ + |_PER_FMK(I2C,I2CSTR,SCD,scd)\ + |_PER_FMK(I2C,I2CSTR,ICXRDY,icxrdy)\ + |_PER_FMK(I2C,I2CSTR,ICRRDY,icrrdy)\ + |_PER_FMK(I2C,I2CSTR,ARDY,ardy)\ + |_PER_FMK(I2C,I2CSTR,NACK,nack)\ + |_PER_FMK(I2C,I2CSTR,AL,al)\ + ) +#endif + #define _I2C_I2CSTR_FGET(N,FIELD)\ + _PER_FGET(_I2C_I2CSTR##N##_ADDR,I2C,I2CSTR,##FIELD) + + #define _I2C_I2CSTR_FSET(N,FIELD,field)\ + _PER_FSET(_I2C_I2CSTR##N##_ADDR,I2C,I2CSTR,##FIELD,field) + + #define _I2C_I2CSTR_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_I2C_I2CSTR##N##_ADDR,I2C,I2CSTR,##FIELD,##SYM) + + #define _I2C_I2CSTR0_FGET(FIELD) _I2C_I2CSTR_FGET(0,##FIELD) + #define _I2C_I2CSTR1_FGET(FIELD) _I2C_I2CSTR_FGET(1,##FIELD) + + #define _I2C_I2CSTR0_FSET(FIELD,f) _I2C_I2CSTR_FSET(0,##FIELD,f) + #define _I2C_I2CSTR1_FSET(FIELD,f) _I2C_I2CSTR_FSET(1,##FIELD,f) + + #define _I2C_I2CSTR0_FSETS(FIELD,SYM) _I2C_I2CSTR_FSETS(0,##FIELD,##SYM) + #define _I2C_I2CSTR1_FSETS(FIELD,SYM) _I2C_I2CSTR_FSETS(1,##FIELD,##SYM) + + +/******************************************************************************\ +* ___________________ +* | | +* | I 2 C C L K L | +* |___________________| +* +* I2CCLKL0 - I2C0 Clock Divider Low register +* I2CCLKL1 - I2C1 Clock Divider Low register +* +* FIELDS (msb -> lsb) +* (rw) ICCL +* +\******************************************************************************/ + #define _I2C_I2CCLKL_OFFSET 3 + + #define _I2C_I2CCLKL0_ADDR 0x01B4000C + #define _I2C_I2CCLKL1_ADDR 0x01B4400C + + #define _I2C_I2CCLKL_ICCL_MASK 0x0000FFFFu + #define _I2C_I2CCLKL_ICCL_SHIFT 0x00000000u + #define I2C_I2CCLKL_ICCL_DEFAULT 0x00000000u + #define I2C_I2CCLKL_ICCL_OF(x) _VALUEOF(x) + + #define I2C_I2CCLKL_OF(x) _VALUEOF(x) + + #define I2C_I2CCLKL_DEFAULT (Uint32)(\ + _PER_FDEFAULT(I2C,I2CCLKL,ICCL)\ + ) + + #define I2C_I2CCLKL_RMK(iccl) (Uint32)(\ + _PER_FMK(I2C,I2CCLKL,ICCL,iccl)\ + ) + + #define _I2C_I2CCLKL_FGET(N,FIELD)\ + _PER_FGET(_I2C_I2CCLKL##N##_ADDR,I2C,I2CCLKL,##FIELD) + + #define _I2C_I2CCLKL_FSET(N,FIELD,field)\ + _PER_FSET(_I2C_I2CCLKL##N##_ADDR,I2C,I2CCLKL,##FIELD,field) + + #define _I2C_I2CCLKL_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_I2C_I2CCLKL##N##_ADDR,I2C,I2CCLKL,##FIELD,##SYM) + + #define _I2C_I2CCLKL0_FGET(FIELD) _I2C_I2CCLKL_FGET(0,##FIELD) + #define _I2C_I2CCLKL1_FGET(FIELD) _I2C_I2CCLKL_FGET(1,##FIELD) + + #define _I2C_I2CCLKL0_FSET(FIELD,f) _I2C_I2CCLKL_FSET(0,##FIELD,f) + #define _I2C_I2CCLKL1_FSET(FIELD,f) _I2C_I2CCLKL_FSET(1,##FIELD,f) + + #define _I2C_I2CCLKL0_FSETS(FIELD,SYM) _I2C_I2CCLKL_FSETS(0,##FIELD,##SYM) + #define _I2C_I2CCLKL1_FSETS(FIELD,SYM) _I2C_I2CCLKL_FSETS(1,##FIELD,##SYM) + + +/******************************************************************************\ +* ___________________ +* | | +* | I 2 C C L K H | +* |___________________| +* +* I2CCLKH0 - I2C0 Clock Divider High register +* I2CCLKH1 - I2C1 Clock Divider High register +* +* FIELDS (msb -> lsb) +* (rw) ICCH +* +\******************************************************************************/ + #define _I2C_I2CCLKH_OFFSET 4 + + #define _I2C_I2CCLKH0_ADDR 0x01B40010 + #define _I2C_I2CCLKH1_ADDR 0x01B44010 + + #define _I2C_I2CCLKH_ICCH_MASK 0x0000FFFFu + #define _I2C_I2CCLKH_ICCH_SHIFT 0x00000000u + #define I2C_I2CCLKH_ICCH_DEFAULT 0x00000000u + #define I2C_I2CCLKH_ICCH_OF(x) _VALUEOF(x) + + #define I2C_I2CCLKH_OF(x) _VALUEOF(x) + + #define I2C_I2CCLKH_DEFAULT (Uint32)(\ + _PER_FDEFAULT(I2C,I2CCLKH,ICCH)\ + ) + + #define I2C_I2CCLKH_RMK(icch) (Uint32)(\ + _PER_FMK(I2C,I2CCLKH,ICCH,icch)\ + ) + + #define _I2C_I2CCLKH_FGET(N,FIELD)\ + _PER_FGET(_I2C_I2CCLKH##N##_ADDR,I2C,I2CCLKH,##FIELD) + + #define _I2C_I2CCLKH_FSET(N,FIELD,field)\ + _PER_FSET(_I2C_I2CCLKH##N##_ADDR,I2C,I2CCLKH,##FIELD,field) + + #define _I2C_I2CCLKH_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_I2C_I2CCLKH##N##_ADDR,I2C,I2CCLKH,##FIELD,##SYM) + + #define _I2C_I2CCLKH0_FGET(FIELD) _I2C_I2CCLKH_FGET(0,##FIELD) + #define _I2C_I2CCLKH1_FGET(FIELD) _I2C_I2CCLKH_FGET(1,##FIELD) + + #define _I2C_I2CCLKH0_FSET(FIELD,f) _I2C_I2CCLKH_FSET(0,##FIELD,f) + #define _I2C_I2CCLKH1_FSET(FIELD,f) _I2C_I2CCLKH_FSET(1,##FIELD,f) + + #define _I2C_I2CCLKH0_FSETS(FIELD,SYM) _I2C_I2CCLKH_FSETS(0,##FIELD,##SYM) + #define _I2C_I2CCLKH1_FSETS(FIELD,SYM) _I2C_I2CCLKH_FSETS(1,##FIELD,##SYM) + + +/******************************************************************************\ +* ___________________ +* | | +* | I 2 C C N T | +* |___________________| +* +* I2CCNT0 - I2C0 Data Count register +* I2CCNT1 - I2C1 Data Count register +* +* FIELDS (msb -> lsb) +* (rw) ICDC +\******************************************************************************/ + #define _I2C_I2CCNT_OFFSET 5 + + #define _I2C_I2CCNT0_ADDR 0x01B40014 + #define _I2C_I2CCNT1_ADDR 0x01B44014 + + #define _I2C_I2CCNT_ICDC_MASK 0x0000FFFFu + #define _I2C_I2CCNT_ICDC_SHIFT 0x00000000u + #define I2C_I2CCNT_ICDC_DEFAULT 0x00000000u + #define I2C_I2CCNT_ICDC_OF(x) _VALUEOF(x) + + #define I2C_I2CCNT_OF(x) _VALUEOF(x) + + #define I2C_I2CCNT_DEFAULT (Uint32)(\ + _PER_FDEFAULT(I2C,I2CCNT,ICDC)\ + ) + + #define I2C_I2CCNT_RMK(icdc) (Uint32)(\ + _PER_FMK(I2C,I2CCNT,ICDC,icdc)\ + ) + + #define _I2C_I2CCNT_FGET(N,FIELD)\ + _PER_FGET(_I2C_I2CCNT##N##_ADDR,I2C,I2CCNT,##FIELD) + + #define _I2C_I2CCNT_FSET(N,FIELD,field)\ + _PER_FSET(_I2C_I2CCNT##N##_ADDR,I2C,I2CCNT,##FIELD,field) + + #define _I2C_I2CCNT_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_I2C_I2CCNT##N##_ADDR,I2C,I2CCNT,##FIELD,##SYM) + + #define _I2C_I2CCNT0_FGET(FIELD) _I2C_I2CCNT_FGET(0,##FIELD) + #define _I2C_I2CCNT1_FGET(FIELD) _I2C_I2CCNT_FGET(1,##FIELD) + + #define _I2C_I2CCNT0_FSET(FIELD,f) _I2C_I2CCNT_FSET(0,##FIELD,f) + #define _I2C_I2CCNT1_FSET(FIELD,f) _I2C_I2CCNT_FSET(1,##FIELD,f) + + #define _I2C_I2CCNT0_FSETS(FIELD,SYM) _I2C_I2CCNT_FSETS(0,##FIELD,##SYM) + #define _I2C_I2CCNT1_FSETS(FIELD,SYM) _I2C_I2CCNT_FSETS(1,##FIELD,##SYM) + + +/******************************************************************************\ +* ___________________ +* | | +* | I 2 C D R R | +* |___________________| +* +* I2CDRR0 - I2C0 Data Receive register +* I2CDRR1 - I2C1 Data Receive register +* +* FIELDS (msb -> lsb) +* (r) D +\******************************************************************************/ + #define _I2C_I2CDRR_OFFSET 6 + + #define _I2C_I2CDRR0_ADDR 0x01B40018 + #define _I2C_I2CDRR1_ADDR 0x01B44018 + + #define _I2C_I2CDRR_D_MASK 0x000000FFu + #define _I2C_I2CDRR_D_SHIFT 0x00000000u + #define I2C_I2CDRR_D_DEFAULT 0x00000000u + #define I2C_I2CDRR_D_OF(x) _VALUEOF(x) + + #define I2C_I2CDRR_OF(x) _VALUEOF(x) + + #define I2C_I2CDRR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(I2C,I2CDRR,D)\ + ) + + #define I2C_I2CDRR_RMK(d) (Uint32)(\ + _PER_FMK(I2C,I2CDRR,D,d)\ + ) + + #define _I2C_I2CDRR_FGET(N,FIELD)\ + _PER_FGET(_I2C_I2CDRR##N##_ADDR,I2C,I2CDRR,##FIELD) + + #define _I2C_I2CDRR_FSET(N,FIELD,field)\ + _PER_FSET(_I2C_I2CDRR##N##_ADDR,I2C,I2CDRR,##FIELD,field) + + #define _I2C_I2CDRR_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_I2C_I2CDRR##N##_ADDR,I2C,I2CDRR,##FIELD,##SYM) + + #define _I2C_I2CDRR0_FGET(FIELD) _I2C_I2CDRR_FGET(0,##FIELD) + #define _I2C_I2CDRR1_FGET(FIELD) _I2C_I2CDRR_FGET(1,##FIELD) + + #define _I2C_I2CDRR0_FSET(FIELD,f) _I2C_I2CDRR_FSET(0,##FIELD,f) + #define _I2C_I2CDRR1_FSET(FIELD,f) _I2C_I2CDRR_FSET(1,##FIELD,f) + + #define _I2C_I2CDRR0_FSETS(FIELD,SYM) _I2C_I2CDRR_FSETS(0,##FIELD,##SYM) + #define _I2C_I2CDRR1_FSETS(FIELD,SYM) _I2C_I2CDRR_FSETS(1,##FIELD,##SYM) + + +/******************************************************************************\ +* ___________________ +* | | +* | I 2 C S A R | +* |___________________| +* +* I2CSAR0 - I2C0 Slave Address register +* I2CSAR1 - I2C1 Slave Address register +* +* FIELDS (msb -> lsb) +* (rw) A +\******************************************************************************/ + #define _I2C_I2CSAR_OFFSET 7 + + #define _I2C_I2CSAR0_ADDR 0x01B4001C + #define _I2C_I2CSAR1_ADDR 0x01B4401C + + #define _I2C_I2CSAR_A_MASK 0x000003FFu + #define _I2C_I2CSAR_A_SHIFT 0x00000000u + #define I2C_I2CSAR_A_DEFAULT 0x000003FFu /*???*/ + #define I2C_I2CSAR_A_OF(x) _VALUEOF(x) + + #define I2C_I2CSAR_OF(x) _VALUEOF(x) + + #define I2C_I2CSAR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(I2C,I2CSAR,A)\ + ) + + #define I2C_I2CSAR_RMK(a) (Uint32)(\ + _PER_FMK(I2C,I2CSAR,A,a)\ + ) + + #define _I2C_I2CSAR_FGET(N,FIELD)\ + _PER_FGET(_I2C_I2CSAR##N##_ADDR,I2C,I2CSAR,##FIELD) + + #define _I2C_I2CSAR_FSET(N,FIELD,field)\ + _PER_FSET(_I2C_I2CSAR##N##_ADDR,I2C,I2CSAR,##FIELD,field) + + #define _I2C_I2CSAR_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_I2C_I2CSAR##N##_ADDR,I2C,I2CSAR,##FIELD,##SYM) + + #define _I2C_I2CSAR0_FGET(FIELD) _I2C_I2CSAR_FGET(0,##FIELD) + #define _I2C_I2CSAR1_FGET(FIELD) _I2C_I2CSAR_FGET(1,##FIELD) + + #define _I2C_I2CSAR0_FSET(FIELD,f) _I2C_I2CSAR_FSET(0,##FIELD,f) + #define _I2C_I2CSAR1_FSET(FIELD,f) _I2C_I2CSAR_FSET(1,##FIELD,f) + + #define _I2C_I2CSAR0_FSETS(FIELD,SYM) _I2C_I2CSAR_FSETS(0,##FIELD,##SYM) + #define _I2C_I2CSAR1_FSETS(FIELD,SYM) _I2C_I2CSAR_FSETS(1,##FIELD,##SYM) + + +/******************************************************************************\ +* ___________________ +* | | +* | I 2 C D X R | +* |___________________| +* +* I2CDXR0 - I2C0 Data Transmit register +* I2CDXR1 - I2C1 Data Transmit register +* +* FIELDS (msb -> lsb) +* (rw) D +\******************************************************************************/ + #define _I2C_I2CDXR_OFFSET 8 + + #define _I2C_I2CDXR0_ADDR 0x01B40020 + #define _I2C_I2CDXR1_ADDR 0x01B44020 + + #define _I2C_I2CDXR_D_MASK 0x000000FFu + #define _I2C_I2CDXR_D_SHIFT 0x00000000u + #define I2C_I2CDXR_D_DEFAULT 0x00000000u + #define I2C_I2CDXR_D_OF(x) _VALUEOF(x) + + #define I2C_I2CDXR_OF(x) _VALUEOF(x) + + #define I2C_I2CDXR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(I2C,I2CDXR,D)\ + ) + + #define I2C_I2CDXR_RMK(d) (Uint32)(\ + _PER_FMK(I2C,I2CDXR,D,d)\ + ) + + #define _I2C_I2CDXR_FGET(N,FIELD)\ + _PER_FGET(_I2C_I2CDXR##N##_ADDR,I2C,I2CDXR,##FIELD) + + #define _I2C_I2CDXR_FSET(N,FIELD,field)\ + _PER_FSET(_I2C_I2CDXR##N##_ADDR,I2C,I2CDXR,##FIELD,field) + + #define _I2C_I2CDXR_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_I2C_I2CDXR##N##_ADDR,I2C,I2CDXR,##FIELD,##SYM) + + #define _I2C_I2CDXR0_FGET(FIELD) _I2C_I2CDXR_FGET(0,##FIELD) + #define _I2C_I2CDXR1_FGET(FIELD) _I2C_I2CDXR_FGET(1,##FIELD) + + #define _I2C_I2CDXR0_FSET(FIELD,f) _I2C_I2CDXR_FSET(0,##FIELD,f) + #define _I2C_I2CDXR1_FSET(FIELD,f) _I2C_I2CDXR_FSET(1,##FIELD,f) + + #define _I2C_I2CDXR0_FSETS(FIELD,SYM) _I2C_I2CDXR_FSETS(0,##FIELD,##SYM) + #define _I2C_I2CDXR1_FSETS(FIELD,SYM) _I2C_I2CDXR_FSETS(1,##FIELD,##SYM) + +/******************************************************************************\ +* ___________________ +* | | +* | I 2 C M D R | +* |___________________| +* +* I2CMDR0 - I2C0 Mode register +* I2CMDR1 - I2C1 Mode register +* +* FIELDS (msb -> lsb) +* (rw) NACKMOD +* (rw) FREE +* (rw) STT +* (rw) STP +* (rw) MST +* (rw) TRX +* (rw) XA +* (rw) RM +* (rw) DLB +* (rw) IRS +* (rw) STB +* (rw) FDF +* (rw) BC +\******************************************************************************/ + #define _I2C_I2CMDR_OFFSET 9 + + #define _I2C_I2CMDR0_ADDR 0x01B40024 + #define _I2C_I2CMDR1_ADDR 0x01B44024 + + #define _I2C_I2CMDR_NACKMOD_MASK 0x00008000u + #define _I2C_I2CMDR_NACKMOD_SHIFT 0x0000000Fu + #define I2C_I2CMDR_NACKMOD_DEFAULT 0x00000000u + #define I2C_I2CMDR_NACKMOD_OF(x) _VALUEOF(x) + #define I2C_I2CMDR_NACKMOD_ACK 0x00000000u + #define I2C_I2CMDR_NACKMOD_NACK 0x00000001u + + #define _I2C_I2CMDR_FREE_MASK 0x00004000u + #define _I2C_I2CMDR_FREE_SHIFT 0x0000000Eu + #define I2C_I2CMDR_FREE_DEFAULT 0x00000000u + #define I2C_I2CMDR_FREE_OF(x) _VALUEOF(x) + #define I2C_I2CMDR_FREE_BSTOP 0x00000000u + #define I2C_I2CMDR_FREE_RFREE 0x00000001u + + #define _I2C_I2CMDR_STT_MASK 0x00002000u + #define _I2C_I2CMDR_STT_SHIFT 0x0000000Du + #define I2C_I2CMDR_STT_DEFAULT 0x00000000u + #define I2C_I2CMDR_STT_OF(x) _VALUEOF(x) + #define I2C_I2CMDR_STT_NONE 0x00000000u + #define I2C_I2CMDR_STT_START 0x00000001u + + #define _I2C_I2CMDR_STP_MASK 0x00000800u + #define _I2C_I2CMDR_STP_SHIFT 0x0000000Bu + #define I2C_I2CMDR_STP_DEFAULT 0x00000000u + #define I2C_I2CMDR_STP_OF(x) _VALUEOF(x) + #define I2C_I2CMDR_STP_NONE 0x00000000u + #define I2C_I2CMDR_STP_STOP 0x00000001u + + #define _I2C_I2CMDR_MST_MASK 0x00000400u + #define _I2C_I2CMDR_MST_SHIFT 0x0000000Au + #define I2C_I2CMDR_MST_DEFAULT 0x00000000u + #define I2C_I2CMDR_MST_OF(x) _VALUEOF(x) + #define I2C_I2CMDR_MST_SLAVE 0x00000000u + #define I2C_I2CMDR_MST_MASTER 0x00000001u + + #define _I2C_I2CMDR_TRX_MASK 0x00000200u + #define _I2C_I2CMDR_TRX_SHIFT 0x00000009u + #define I2C_I2CMDR_TRX_DEFAULT 0x00000000u + #define I2C_I2CMDR_TRX_OF(x) _VALUEOF(x) + #define I2C_I2CMDR_TRX_RCV 0x00000000u + #define I2C_I2CMDR_TRX_XMT 0x00000001u + + #define _I2C_I2CMDR_XA_MASK 0x00000100u + #define _I2C_I2CMDR_XA_SHIFT 0x00000008u + #define I2C_I2CMDR_XA_DEFAULT 0x00000000u + #define I2C_I2CMDR_XA_OF(x) _VALUEOF(x) + #define I2C_I2CMDR_XA_7BIT 0x00000000u + #define I2C_I2CMDR_XA_10BIT 0x00000001u + + #define _I2C_I2CMDR_RM_MASK 0x00000080u + #define _I2C_I2CMDR_RM_SHIFT 0x00000007u + #define I2C_I2CMDR_RM_DEFAULT 0x00000000u + #define I2C_I2CMDR_RM_OF(x) _VALUEOF(x) + #define I2C_I2CMDR_RM_NONE 0x00000000u + #define I2C_I2CMDR_RM_REPEAD 0x00000001u + + #define _I2C_I2CMDR_DLB_MASK 0x00000040u + #define _I2C_I2CMDR_DLB_SHIFT 0x00000006u + #define I2C_I2CMDR_DLB_DEFAULT 0x00000000u + #define I2C_I2CMDR_DLB_OF(x) _VALUEOF(x) + #define I2C_I2CMDR_DLB_NONE 0x00000000u + #define I2C_I2CMDR_DLB_LOOPBACK 0x00000001u + + #define _I2C_I2CMDR_IRS_MASK 0x00000020u + #define _I2C_I2CMDR_IRS_SHIFT 0x00000005u + #define I2C_I2CMDR_IRS_DEFAULT 0x00000000u + #define I2C_I2CMDR_IRS_OF(x) _VALUEOF(x) + #define I2C_I2CMDR_IRS_RST 0x00000000u + #define I2C_I2CMDR_IRS_NRST 0x00000001u + + #define _I2C_I2CMDR_STB_MASK 0x00000010u + #define _I2C_I2CMDR_STB_SHIFT 0x00000004u + #define I2C_I2CMDR_STB_DEFAULT 0x00000000u + #define I2C_I2CMDR_STB_OF(x) _VALUEOF(x) + #define I2C_I2CMDR_STB_NONE 0x00000000u + #define I2C_I2CMDR_STB_SET 0x00000001u + + #define _I2C_I2CMDR_FDF_MASK 0x00000008u + #define _I2C_I2CMDR_FDF_SHIFT 0x00000003u + #define I2C_I2CMDR_FDF_DEFAULT 0x00000000u + #define I2C_I2CMDR_FDF_OF(x) _VFDFUEOF(x) + #define I2C_I2CMDR_FDF_NONE 0x00000000u + #define I2C_I2CMDR_FDF_SET 0x00000001u + + #define _I2C_I2CMDR_BC_MASK 0x00000007u + #define _I2C_I2CMDR_BC_SHIFT 0x00000000u + #define I2C_I2CMDR_BC_DEFAULT 0x00000000u + #define I2C_I2CMDR_BC_OF(x) _VALUEOF(x) + #define I2C_I2CMDR_BC_BIT8FDF 0x00000000u + #define I2C_I2CMDR_BC_BIT7FDF 0x00000007u + #define I2C_I2CMDR_BC_BIT6FDF 0x00000006u + #define I2C_I2CMDR_BC_BIT5FDF 0x00000005u + #define I2C_I2CMDR_BC_BIT4FDF 0x00000004u + #define I2C_I2CMDR_BC_BIT3FDF 0x00000003u + #define I2C_I2CMDR_BC_BIT2FDF 0x00000002u + #define I2C_I2CMDR_BC_BIT1FDF 0x00000001u + + #define I2C_I2CMDR_OF(x) _VALUEOF(x) + + #define I2C_I2CMDR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(I2C,I2CMDR,NACKMOD)\ + |_PER_FDEFAULT(I2C,I2CMDR,FREE)\ + |_PER_FDEFAULT(I2C,I2CMDR,STT)\ + |_PER_FDEFAULT(I2C,I2CMDR,STP)\ + |_PER_FDEFAULT(I2C,I2CMDR,MST)\ + |_PER_FDEFAULT(I2C,I2CMDR,TRX)\ + |_PER_FDEFAULT(I2C,I2CMDR,XA)\ + |_PER_FDEFAULT(I2C,I2CMDR,RM)\ + |_PER_FDEFAULT(I2C,I2CMDR,DLB)\ + |_PER_FDEFAULT(I2C,I2CMDR,IRS)\ + |_PER_FDEFAULT(I2C,I2CMDR,STB)\ + |_PER_FDEFAULT(I2C,I2CMDR,FDF)\ + |_PER_FDEFAULT(I2C,I2CMDR,BC)\ + ) + + #define I2C_I2CMDR_RMK(nackmod,free,stt,stp,mst,trx,xa,rm,dlb,irs,stb,fdf,bc) (Uint32)(\ + _PER_FMK(I2C,I2CMDR,NACKMOD,nackmod)\ + |_PER_FMK(I2C,I2CMDR,FREE,free)\ + |_PER_FMK(I2C,I2CMDR,STT,stt)\ + |_PER_FMK(I2C,I2CMDR,STP,stp)\ + |_PER_FMK(I2C,I2CMDR,MST,mst)\ + |_PER_FMK(I2C,I2CMDR,TRX,trx)\ + |_PER_FMK(I2C,I2CMDR,XA,xa)\ + |_PER_FMK(I2C,I2CMDR,RM,rm)\ + |_PER_FMK(I2C,I2CMDR,DLB,dlb)\ + |_PER_FMK(I2C,I2CMDR,IRS,irs)\ + |_PER_FMK(I2C,I2CMDR,STB,stb)\ + |_PER_FMK(I2C,I2CMDR,FDF,fdf)\ + |_PER_FMK(I2C,I2CMDR,BC,bc)\ + ) + + #define _I2C_I2CMDR_FGET(N,FIELD)\ + _PER_FGET(_I2C_I2CMDR##N##_ADDR,I2C,I2CMDR,##FIELD) + + #define _I2C_I2CMDR_FSET(N,FIELD,field)\ + _PER_FSET(_I2C_I2CMDR##N##_ADDR,I2C,I2CMDR,##FIELD,field) + + #define _I2C_I2CMDR_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_I2C_I2CMDR##N##_ADDR,I2C,I2CMDR,##FIELD,##SYM) + + #define _I2C_I2CMDR0_FGET(FIELD) _I2C_I2CMDR_FGET(0,##FIELD) + #define _I2C_I2CMDR1_FGET(FIELD) _I2C_I2CMDR_FGET(1,##FIELD) + + #define _I2C_I2CMDR0_FSET(FIELD,f) _I2C_I2CMDR_FSET(0,##FIELD,f) + #define _I2C_I2CMDR1_FSET(FIELD,f) _I2C_I2CMDR_FSET(1,##FIELD,f) + + #define _I2C_I2CMDR0_FSETS(FIELD,SYM) _I2C_I2CMDR_FSETS(0,##FIELD,##SYM) + #define _I2C_I2CMDR1_FSETS(FIELD,SYM) _I2C_I2CMDR_FSETS(1,##FIELD,##SYM) + +/******************************************************************************\ +* (Keeping the old definitions for backward compatibility) +* ___________________ +* | | +* | I 2 C I V R | +* |___________________| +* +* I2CIVR0 - I2C0 Interrupt Vector register +* I2CIVR1 - I2C1 Interrupt Vector register +* +* FIELDS (msb -> lsb) +* (r) INTCODE +\******************************************************************************/ + +#if (!(CHIP_6410 | CHIP_6413 | CHIP_6418)) + #define _I2C_I2CIVR_OFFSET 10 + + #define _I2C_I2CIVR0_ADDR 0x01B40028 + #define _I2C_I2CIVR1_ADDR 0x01B44028 + + /*** old names ***/ + #define _I2C_I2CISR0_ADDR _I2C_I2CIVR0_ADDR + #define _I2C_I2CISR1_ADDR _I2C_I2CIVR1_ADDR + + #define _I2C_I2CIVR_INTCODE_MASK 0x00000007u + #define _I2C_I2CIVR_INTCODE_SHIFT 0x00000000u + #define I2C_I2CIVR_INTCODE_DEFAULT 0x00000000u + #define I2C_I2CIVR_INTCODE_OF(x) _VALUEOF(x) + #define I2C_I2CIVR_INTCODE_NONE 0x00000000u + #define I2C_I2CIVR_INTCODE_AL 0x00000001u + #define I2C_I2CIVR_INTCODE_NACK 0x00000002u + #define I2C_I2CIVR_INTCODE_RAR 0x00000003u + #define I2C_I2CIVR_INTCODE_RDR 0x00000004u + #define I2C_I2CIVR_INTCODE_XDR 0x00000005u + + #define I2C_I2CIVR_OF(x) _VALUEOF(x) + + #define I2C_I2CIVR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(I2C,I2CIVR,INTCODE)\ + ) + + #define I2C_I2CIVR_RMK(intcode) (Uint32)(\ + _PER_FMK(I2C,I2CIVR,INTCODE,intcode)\ + ) + + #define _I2C_I2CIVR_FGET(N,FIELD)\ + _PER_FGET(_I2C_I2CIVR##N##_ADDR,I2C,I2CIVR,##FIELD) + + #define _I2C_I2CIVR_FSET(N,FIELD,field)\ + _PER_FSET(_I2C_I2CIVR##N##_ADDR,I2C,I2CIVR,##FIELD,field) + + #define _I2C_I2CIVR_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_I2C_I2CIVR##N##_ADDR,I2C,I2CIVR,##FIELD,##SYM) + + #define _I2C_I2CIVR0_FGET(FIELD) _I2C_I2CIVR_FGET(0,##FIELD) + #define _I2C_I2CIVR1_FGET(FIELD) _I2C_I2CIVR_FGET(1,##FIELD) + + #define _I2C_I2CIVR0_FSET(FIELD,f) _I2C_I2CIVR_FSET(0,##FIELD,f) + #define _I2C_I2CIVR1_FSET(FIELD,f) _I2C_I2CIVR_FSET(1,##FIELD,f) + + #define _I2C_I2CIVR0_FSETS(FIELD,SYM) _I2C_I2CIVR_FSETS(0,##FIELD,##SYM) + #define _I2C_I2CIVR1_FSETS(FIELD,SYM) _I2C_I2CIVR_FSETS(1,##FIELD,##SYM) +#endif + +/******************************************************************************\ +* ___________________ +* | | +* | I 2 C I S R C | +* |___________________| +* +* I2CISRC0 - I2C0 Interrupt Vector register +* I2CISRC1 - I2C1 Interrupt Vector register +* +* FIELDS (msb -> lsb) +* (r) INTCODE +\******************************************************************************/ + + #define _I2C_I2CISRC_OFFSET 10 + + #define _I2C_I2CISRC0_ADDR 0x01B40028 + #define _I2C_I2CISRC1_ADDR 0x01B44028 + + #define _I2C_I2CISRC_INTCODE_MASK 0x00000007u + #define _I2C_I2CISRC_INTCODE_SHIFT 0x00000000u + #define I2C_I2CISRC_INTCODE_DEFAULT 0x00000000u + #define I2C_I2CISRC_INTCODE_OF(x) _VALUEOF(x) + #define I2C_I2CISRC_INTCODE_NONE 0x00000000u + #define I2C_I2CISRC_INTCODE_AL 0x00000001u + #define I2C_I2CISRC_INTCODE_NACK 0x00000002u + #define I2C_I2CISRC_INTCODE_RAR 0x00000003u + #define I2C_I2CISRC_INTCODE_RDR 0x00000004u + #define I2C_I2CISRC_INTCODE_XDR 0x00000005u +#if (CHIP_6413 | CHIP_6418 | CHIP_6410) + #define I2C_I2CISRC_INTCODE_SCD 0x00000006u + #define I2C_I2CISRC_INTCODE_AAS 0x00000007u +#endif + + #define I2C_I2CISRC_OF(x) _VALUEOF(x) + + #define I2C_I2CISRC_DEFAULT (Uint32)(\ + _PER_FDEFAULT(I2C,I2CISRC,INTCODE)\ + ) + + #define I2C_I2CISRC_RMK(intcode) (Uint32)(\ + _PER_FMK(I2C,I2CISRC,INTCODE,intcode)\ + ) + + #define _I2C_I2CISRC_FGET(N,FIELD)\ + _PER_FGET(_I2C_I2CISRC##N##_ADDR,I2C,I2CISRC,##FIELD) + + #define _I2C_I2CISRC_FSET(N,FIELD,field)\ + _PER_FSET(_I2C_I2CISRC##N##_ADDR,I2C,I2CISRC,##FIELD,field) + + #define _I2C_I2CISRC_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_I2C_I2CISRC##N##_ADDR,I2C,I2CISRC,##FIELD,##SYM) + + #define _I2C_I2CISRC0_FGET(FIELD) _I2C_I2CISRC_FGET(0,##FIELD) + #define _I2C_I2CISRC1_FGET(FIELD) _I2C_I2CISRC_FGET(1,##FIELD) + + #define _I2C_I2CISRC0_FSET(FIELD,f) _I2C_I2CISRC_FSET(0,##FIELD,f) + #define _I2C_I2CISRC1_FSET(FIELD,f) _I2C_I2CISRC_FSET(1,##FIELD,f) + + #define _I2C_I2CISRC0_FSETS(FIELD,SYM) _I2C_I2CISRC_FSETS(0,##FIELD,##SYM) + #define _I2C_I2CISRC1_FSETS(FIELD,SYM) _I2C_I2CISRC_FSETS(1,##FIELD,##SYM) + +/******************************************************************************\ +* ___________________ +* | | +* | I 2 C E M D R | +* |___________________| +* +* I2CEMDR0 - I2C0 Extended Mode register(1) +* I2CEMDR1 - I2C1 Extended Mode register(1) +* +* FIELDS (msb -> lsb) +* (rw) XRDYM +* +* (1) For C6418/C6413/C6410 only +\******************************************************************************/ +#if (CHIP_6413 | CHIP_6418 | CHIP_6410) + #define _I2C_I2CEMDR_OFFSET 11 + + #define _I2C_I2CEMDR0_ADDR 0x01B4002C + #define _I2C_I2CEMDR1_ADDR 0x01B4402C + + #define _I2C_I2CEMDR_XRDYM_MASK 0x00000001u + #define _I2C_I2CEMDR_XRDYM_SHIFT 0x00000000u + #define I2C_I2CEMDR_XRDYM_DEFAULT 0x00000001u + #define I2C_I2CEMDR_XRDYM_OF(x) _VALUEOF(x) + #define I2C_I2CEMDR_XRDYM_MSTACK 0x00000000u + #define I2C_I2CEMDR_XRDYM_DXRCPY 0x00000001u + + #define I2C_I2CEMDR_OF(x) _VALUEOF(x) + + #define I2C_I2CEMDR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(I2C,I2CEMDR,XRDYM)\ + ) + + #define I2C_I2CEMDR_RMK(xrdym) (Uint32)(\ + _PER_FMK(I2C,I2CEMDR,XRDYM,xrdym)\ + ) + + #define _I2C_I2CEMDR_FGET(N,FIELD)\ + _PER_FGET(_I2C_I2CEMDR##N##_ADDR,I2C,I2CEMDR,##FIELD) + + #define _I2C_I2CEMDR_FSET(N,FIELD,field)\ + _PER_FSET(_I2C_I2CEMDR##N##_ADDR,I2C,I2CEMDR,##FIELD,field) + + #define _I2C_I2CEMDR_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_I2C_I2CEMDR##N##_ADDR,I2C,I2CEMDR,##FIELD,##SYM) + + #define _I2C_I2CEMDR0_FGET(FIELD) _I2C_I2CEMDR_FGET(0,##FIELD) + #define _I2C_I2CEMDR1_FGET(FIELD) _I2C_I2CEMDR_FGET(1,##FIELD) + + #define _I2C_I2CEMDR0_FSET(FIELD,f) _I2C_I2CEMDR_FSET(0,##FIELD,f) + #define _I2C_I2CEMDR1_FSET(FIELD,f) _I2C_I2CEMDR_FSET(1,##FIELD,f) + + #define _I2C_I2CEMDR0_FSETS(FIELD,SYM) _I2C_I2CEMDR_FSETS(0,##FIELD,##SYM) + #define _I2C_I2CEMDR1_FSETS(FIELD,SYM) _I2C_I2CEMDR_FSETS(1,##FIELD,##SYM) +#endif + +/******************************************************************************\ +* ___________________ +* | | +* | I 2 C P S C | +* |___________________| +* +* I2CPSC0 - I2C0 Prescaler register +* I2CPSC1 - I2C1 Prescaler register +* +* FIELDS (msb -> lsb) +* (rw) IPSC +\******************************************************************************/ + #define _I2C_I2CPSC_OFFSET 12 + + #define _I2C_I2CPSC0_ADDR 0x01B40030 + #define _I2C_I2CPSC1_ADDR 0x01B44030 + + #define _I2C_I2CPSC_IPSC_MASK 0x000000FFu + #define _I2C_I2CPSC_IPSC_SHIFT 0x00000000u + #define I2C_I2CPSC_IPSC_DEFAULT 0x00000000u + #define I2C_I2CPSC_IPSC_OF(x) _VALUEOF(x) + + #define I2C_I2CPSC_OF(x) _VALUEOF(x) + + #define I2C_I2CPSC_DEFAULT (Uint32)(\ + _PER_FDEFAULT(I2C,I2CPSC,IPSC)\ + ) + + #define I2C_I2CPSC_RMK(ipsc) (Uint32)(\ + _PER_FMK(I2C,I2CPSC,IPSC,ipsc)\ + ) + + #define _I2C_I2CPSC_FGET(N,FIELD)\ + _PER_FGET(_I2C_I2CPSC##N##_ADDR,I2C,I2CPSC,##FIELD) + + #define _I2C_I2CPSC_FSET(N,FIELD,field)\ + _PER_FSET(_I2C_I2CPSC##N##_ADDR,I2C,I2CPSC,##FIELD,field) + + #define _I2C_I2CPSC_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_I2C_I2CPSC##N##_ADDR,I2C,I2CPSC,##FIELD,##SYM) + + #define _I2C_I2CPSC0_FGET(FIELD) _I2C_I2CPSC_FGET(0,##FIELD) + #define _I2C_I2CPSC1_FGET(FIELD) _I2C_I2CPSC_FGET(1,##FIELD) + + #define _I2C_I2CPSC0_FSET(FIELD,f) _I2C_I2CPSC_FSET(0,##FIELD,f) + #define _I2C_I2CPSC1_FSET(FIELD,f) _I2C_I2CPSC_FSET(1,##FIELD,f) + + #define _I2C_I2CPSC0_FSETS(FIELD,SYM) _I2C_I2CPSC_FSETS(0,##FIELD,##SYM) + #define _I2C_I2CPSC1_FSETS(FIELD,SYM) _I2C_I2CPSC_FSETS(1,##FIELD,##SYM) + +/******************************************************************************\ +* ___________________ +* | | +* | I 2 C P I D 1 | +* |___________________| +* +* I2CPID10 - I2C0 Peripheral ID Register 1(1) +* I2CPID11 - I2C1 Peripheral ID Register 1(1) +* +* FIELDS (msb -> lsb) +* (r) CLASS +* (r) REVISION +* +* (1) For C6418/C6413/C6410 only +\******************************************************************************/ +#if (CHIP_6413 | CHIP_6418 | CHIP_6410) + #define _I2C_I2CPID1_OFFSET 13 + + #define _I2C_I2CPID10_ADDR 0x01B40034 + #define _I2C_I2CPID11_ADDR 0x01B44034 + + #define _I2C_I2CPID1_CLASS_MASK 0x0000FF00u + #define _I2C_I2CPID1_CLASS_SHIFT 0x00000008u + #define I2C_I2CPID1_CLASS_DEFAULT 0x00000001u + #define I2C_I2CPID1_CLASS_OF(x) _VALUEOF(x) + + #define _I2C_I2CPID1_REVISION_MASK 0x000000FFu + #define _I2C_I2CPID1_REVISION_SHIFT 0x00000000u + #define I2C_I2CPID1_REVISION_DEFAULT 0x00000025u + #define I2C_I2CPID1_REVISION_OF(x) _VALUEOF(x) + + #define I2C_I2CPID1_OF(x) _VALUEOF(x) + + #define I2C_I2CPID1_DEFAULT (Uint32)(\ + _PER_FDEFAULT(I2C,I2CPID1,CLASS)\ + |_PER_FDEFAULT(I2C,I2CPID1,REVISION)\ + ) + + #define _I2C_I2CPID1_FGET(N,FIELD)\ + _PER_FGET(_I2C_I2CPID1##N##_ADDR,I2C,I2CPID1,##FIELD) + + #define _I2C_I2CPID10_FGET(FIELD) _I2C_I2CPID1_FGET(0,##FIELD) + #define _I2C_I2CPID11_FGET(FIELD) _I2C_I2CPID1_FGET(1,##FIELD) +#endif /* CHIP_6413 | CHIP_6418 | CHIP_6410 */ + +/******************************************************************************\ +* ___________________ +* | | +* | I 2 C P I D 2 | +* |___________________| +* +* I2CPID20 - I2C0 Peripheral ID Register 2(1) +* I2CPID21 - I2C1 Peripheral ID Register 2(1) +* +* FIELDS (msb -> lsb) +* (r) TYPE +* +* (1) For C6418/C6413/C6410 only +\******************************************************************************/ +#if (CHIP_6413 | CHIP_6418 | CHIP_6410) + #define _I2C_I2CPID2_OFFSET 14 + + #define _I2C_I2CPID20_ADDR 0x01B40038 + #define _I2C_I2CPID21_ADDR 0x01B44038 + + #define _I2C_I2CPID2_TYPE_MASK 0x000000FFu + #define _I2C_I2CPID2_TYPE_SHIFT 0x00000000u + #define I2C_I2CPID2_TYPE_DEFAULT 0x00000005u + #define I2C_I2CPID2_TYPE_OF(x) _VALUEOF(x) + + #define I2C_I2CPID2_OF(x) _VALUEOF(x) + + #define I2C_I2CPID2_DEFAULT (Uint32)(\ + _PER_FDEFAULT(I2C,I2CPID2,TYPE)\ + ) + + #define _I2C_I2CPID2_FGET(N,FIELD)\ + _PER_FGET(_I2C_I2CPID2##N##_ADDR,I2C,I2CPID2,##FIELD) + + #define _I2C_I2CPID20_FGET(FIELD) _I2C_I2CPID2_FGET(0,##FIELD) + #define _I2C_I2CPID21_FGET(FIELD) _I2C_I2CPID2_FGET(1,##FIELD) + +#endif /* CHIP_6413 | CHIP_6418 | CHIP_6410) */ + +/******************************************************************************\ +* _____________________ +* | | +* | I 2 C P F U N C | +* |___________________| +* +* I2CPFUNC0 - I2C 0 Pin Function Register(1) +* I2CPFUNC1 - I2C 1 Pin Function Register(1) +* +* FIELDS (msb -> lsb) +* (rw) GPMODE +* +* (1) For C6418/C6413/C6410 only +\******************************************************************************/ +#if (CHIP_6413 | CHIP_6418 | CHIP_6410) + #define _I2C_I2CPFUNC_OFFSET 18 + + #define _I2C_I2CPFUNC0_ADDR 0x01B40048 + #define _I2C_I2CPFUNC1_ADDR 0x01B44048 + + #define _I2C_I2CPFUNC_GPMODE_MASK 0x00000001u + #define _I2C_I2CPFUNC_GPMODE_SHIFT 0x00000000u + #define I2C_I2CPFUNC_GPMODE_DEFAULT 0x00000000u + #define I2C_I2CPFUNC_GPMODE_OF(x) _VALUEOF(x) + #define I2C_I2CPFUNC_GPMODE_ENABLE 0x00000001u + #define I2C_I2CPFUNC_GPMODE_DISABLE 0x00000000u + + #define I2C_I2CPFUNC_OF(x) _VALUEOF(x) + + #define I2C_I2CPFUNC_DEFAULT (Uint32)(\ + _PER_FDEFAULT(I2C,I2CPFUNC,GPMODE)\ + ) + + #define I2C_I2CPFUNC_RMK(gpmode) (Uint32)(\ + _PER_FMK(I2C,I2CPFUNC,GPMODE,gpmode)\ + ) + + #define _I2C_I2CPFUNC_FGET(N,FIELD)\ + _PER_FGET(_I2C_I2CPFUNC##N##_ADDR,I2C,I2CPFUNC,##FIELD) + + #define _I2C_I2CPFUNC_FSET(N,FIELD,field)\ + _PER_FSET(_I2C_I2CPFUNC##N##_ADDR,I2C,I2CPFUNC,##FIELD,field) + + #define _I2C_I2CPFUNC_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_I2C_I2CPFUNC##N##_ADDR,I2C,I2CPFUNC,##FIELD,##SYM) + + #define _I2C_I2CPFUNC0_FGET(FIELD) _I2C_I2CPFUNC_FGET(0,##FIELD) + #define _I2C_I2CPFUNC1_FGET(FIELD) _I2C_I2CPFUNC_FGET(1,##FIELD) + + #define _I2C_I2CPFUNC0_FSET(FIELD,f) _I2C_I2CPFUNC_FSET(0,##FIELD,f) + #define _I2C_I2CPFUNC1_FSET(FIELD,f) _I2C_I2CPFUNC_FSET(1,##FIELD,f) + + #define _I2C_I2CPFUNC0_FSETS(FIELD,SYM) _I2C_I2CPFUNC_FSETS(0,##FIELD,##SYM) + #define _I2C_I2CPFUNC1_FSETS(FIELD,SYM) _I2C_I2CPFUNC_FSETS(1,##FIELD,##SYM) +#endif /* CHIP_6413 | CHIP_6418 | CHIP_6410) */ + +/******************************************************************************\ +* ___________________ +* | | +* | I 2 C P D I R | +* |_________________| +* +* I2CPDIR0 - I2C 0 Pin Direction Register(1) +* I2CPDIR1 - I2C 1 Pin Direction Register(1) +* +* FIELDS (msb -> lsb) +* (rw) SDADIR +* (rw) SCLDIR +* +* (1) For C6418/C6413/C6410 only +\******************************************************************************/ +#if (CHIP_6413 | CHIP_6418 | CHIP_6410) + #define _I2C_I2CPDIR_OFFSET 19 + + #define _I2C_I2CPDIR0_ADDR 0x01B4004C + #define _I2C_I2CPDIR1_ADDR 0x01B4404C + + #define _I2C_I2CPDIR_SDADIR_MASK 0x00000002u + #define _I2C_I2CPDIR_SDADIR_SHIFT 0x00000001u + #define I2C_I2CPDIR_SDADIR_DEFAULT 0x00000000u + #define I2C_I2CPDIR_SDADIR_OF(x) _VALUEOF(x) + #define I2C_I2CPDIR_SDADIR_INPUT 0x00000000u + #define I2C_I2CPDIR_SDADIR_OUTPUT 0x00000001u + + #define _I2C_I2CPDIR_SCLDIR_MASK 0x00000001u + #define _I2C_I2CPDIR_SCLDIR_SHIFT 0x00000000u + #define I2C_I2CPDIR_SCLDIR_DEFAULT 0x00000000u + #define I2C_I2CPDIR_SCLDIR_OF(x) _VALUEOF(x) + #define I2C_I2CPDIR_SCLDIR_INPUT 0x00000000u + #define I2C_I2CPDIR_SCLDIR_OUTPUT 0x00000001u + + #define I2C_I2CPDIR_OF(x) _VALUEOF(x) + + #define I2C_I2CPDIR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(I2C,I2CPDIR,SDADIR)\ + |_PER_FDEFAULT(I2C,I2CPDIR,SCLDIR)\ + ) + + #define I2C_I2CPDIR_RMK(sdadir,scldir) (Uint32)(\ + _PER_FMK(I2C,I2CPDIR,SDADIR,sdadir)\ + |_PER_FMK(I2C,I2CPDIR,SCLDIR,scldir)\ + ) + + #define _I2C_I2CPDIR_FGET(N,FIELD)\ + _PER_FGET(_I2C_I2CPDIR##N##_ADDR,I2C,I2CPDIR,##FIELD) + + #define _I2C_I2CPDIR_FSET(N,FIELD,field)\ + _PER_FSET(_I2C_I2CPDIR##N##_ADDR,I2C,I2CPDIR,##FIELD,field) + + #define _I2C_I2CPDIR_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_I2C_I2CPDIR##N##_ADDR,I2C,I2CPDIR,##FIELD,##SYM) + + #define _I2C_I2CPDIR0_FGET(FIELD) _I2C_I2CPDIR_FGET(0,##FIELD) + #define _I2C_I2CPDIR1_FGET(FIELD) _I2C_I2CPDIR_FGET(1,##FIELD) + + #define _I2C_I2CPDIR0_FSET(FIELD,f) _I2C_I2CPDIR_FSET(0,##FIELD,f) + #define _I2C_I2CPDIR1_FSET(FIELD,f) _I2C_I2CPDIR_FSET(1,##FIELD,f) + + #define _I2C_I2CPDIR0_FSETS(FIELD,SYM) _I2C_I2CPDIR_FSETS(0,##FIELD,##SYM) + #define _I2C_I2CPDIR1_FSETS(FIELD,SYM) _I2C_I2CPDIR_FSETS(1,##FIELD,##SYM) +#endif /* CHIP_6413 | CHIP_6418 | CHIP_6410) */ + +/******************************************************************************\ +* ___________________ +* | | +* | I 2 C P D I N | +* |_________________| +* +* I2CPDIN0 - I2C 0 Pin Data In Register(1) +* I2CPDIN1 - I2C 1 Pin Data In Register(1) +* +* FIELDS (msb -> lsb) +* (r) SDAIN +* (r) SCLIN +* +* (1) For C6418/C6413/C6410 only +\******************************************************************************/ +#if (CHIP_6413 | CHIP_6418 | CHIP_6410) + #define _I2C_I2CPDIN_OFFSET 20 + + #define _I2C_I2CPDIN0_ADDR 0x01B40050 + #define _I2C_I2CPDIN1_ADDR 0x01B44050 + + #define _I2C_I2CPDIN_SDAIN_MASK 0x00000002u + #define _I2C_I2CPDIN_SDAIN_SHIFT 0x00000001u + #define I2C_I2CPDIN_SDAIN_OF(x) _VALUEOF(x) + #define I2C_I2CPDIN_SDAIN_LOW 0x00000000u + #define I2C_I2CPDIN_SDAIN_HIGH 0x00000001u + + #define _I2C_I2CPDIN_SCLIN_MASK 0x00000001u + #define _I2C_I2CPDIN_SCLIN_SHIFT 0x00000000u + #define I2C_I2CPDIN_SCLIN_OF(x) _VALUEOF(x) + #define I2C_I2CPDIN_SCLIN_LOW 0x00000000u + #define I2C_I2CPDIN_SCLIN_HIGH 0x00000001u + + #define I2C_I2CPDIN_OF(x) _VALUEOF(x) + + #define I2C_I2CPDIN_DEFAULT (Uint32)(\ + _PER_FDEFAULT(I2C,I2CPDIN,SDAIN)\ + |_PER_FDEFAULT(I2C,I2CPDIN,SCLIN)\ + ) + + #define I2C_I2CPDIN_RMK(sdain,sclin) (Uint32)(\ + _PER_FMK(I2C,I2CPDIN,SDAIN,sdain)\ + |_PER_FMK(I2C,I2CPDIN,SCLIN,sclin)\ + ) + + #define _I2C_I2CPDIN_FGET(N,FIELD)\ + _PER_FGET(_I2C_I2CPDIN##N##_ADDR,I2C,I2CPDIN,##FIELD) + + #define _I2C_I2CPDIN0_FGET(FIELD) _I2C_I2CPDIN_FGET(0,##FIELD) + #define _I2C_I2CPDIN1_FGET(FIELD) _I2C_I2CPDIN_FGET(1,##FIELD) + +#endif /* CHIP_6413 | CHIP_6418 | CHIP_6410) */ + +/******************************************************************************\ +* _____________________ +* | | +* | I 2 C P D O U T | +* |___________________| +* +* I2CPDOUT0 - I2C 0 Pin Data Out Register(1) +* I2CPDOUT1 - I2C 1 Pin Data Out Register(1) +* +* FIELDS (msb -> lsb) +* (rw) SDAOUT +* (rw) SCLOUT +* +* (1) For C6418/C6413/C6410 only +\******************************************************************************/ +#if (CHIP_6413 | CHIP_6418 | CHIP_6410) + #define _I2C_I2CPDOUT_OFFSET 21 + + #define _I2C_I2CPDOUT0_ADDR 0x01B40054 + #define _I2C_I2CPDOUT1_ADDR 0x01B44054 + + #define _I2C_I2CPDOUT_SDAOUT_MASK 0x00000002u + #define _I2C_I2CPDOUT_SDAOUT_SHIFT 0x00000001u + #define I2C_I2CPDOUT_SDAOUT_DEFAULT 0x00000000u + #define I2C_I2CPDOUT_SDAOUT_OF(x) _VALUEOF(x) + #define I2C_I2CPDOUT_SDAOUT_LOW 0x00000000u + #define I2C_I2CPDOUT_SDAOUT_HIGH 0x00000001u + + #define _I2C_I2CPDOUT_SCLOUT_MASK 0x00000001u + #define _I2C_I2CPDOUT_SCLOUT_SHIFT 0x00000000u + #define I2C_I2CPDOUT_SCLOUT_DEFAULT 0x00000000u + #define I2C_I2CPDOUT_SCLOUT_OF(x) _VALUEOF(x) + #define I2C_I2CPDOUT_SCLOUT_LOW 0x00000000u + #define I2C_I2CPDOUT_SCLOUT_HIGH 0x00000001u + + #define I2C_I2CPDOUT_OF(x) _VALUEOF(x) + + #define I2C_I2CPDOUT_DEFAULT (Uint32)(\ + _PER_FDEFAULT(I2C,I2CPDOUT,SDAOUT)\ + |_PER_FDEFAULT(I2C,I2CPDOUT,SCLOUT)\ + ) + + #define I2C_I2CPDOUT_RMK(sdaout,sclout) (Uint32)(\ + _PER_FMK(I2C,I2CPDOUT,SDAOUT,sdaout)\ + |_PER_FMK(I2C,I2CPDOUT,SCLOUT,sclout)\ + ) + + #define _I2C_I2CPDOUT_FGET(N,FIELD)\ + _PER_FGET(_I2C_I2CPDOUT##N##_ADDR,I2C,I2CPDOUT,##FIELD) + + #define _I2C_I2CPDOUT_FSET(N,FIELD,field)\ + _PER_FSET(_I2C_I2CPDOUT##N##_ADDR,I2C,I2CPDOUT,##FIELD,field) + + #define _I2C_I2CPDOUT_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_I2C_I2CPDOUT##N##_ADDR,I2C,I2CPDOUT,##FIELD,##SYM) + + #define _I2C_I2CPDOUT0_FGET(FIELD) _I2C_I2CPDOUT_FGET(0,##FIELD) + #define _I2C_I2CPDOUT1_FGET(FIELD) _I2C_I2CPDOUT_FGET(1,##FIELD) + + #define _I2C_I2CPDOUT0_FSET(FIELD,f) _I2C_I2CPDOUT_FSET(0,##FIELD,f) + #define _I2C_I2CPDOUT1_FSET(FIELD,f) _I2C_I2CPDOUT_FSET(1,##FIELD,f) + + #define _I2C_I2CPDOUT0_FSETS(FIELD,SYM) _I2C_I2CPDOUT_FSETS(0,##FIELD,##SYM) + #define _I2C_I2CPDOUT1_FSETS(FIELD,SYM) _I2C_I2CPDOUT_FSETS(1,##FIELD,##SYM) +#endif /* CHIP_6413 | CHIP_6418 | CHIP_6410) */ + +/******************************************************************************\ +* _____________________ +* | | +* | I 2 C P D S E T | +* |___________________| +* +* I2CPDSET0 - I2C 0 Pin Data Set Register(1) +* I2CPDSET1 - I2C 1 Pin Data Set Register(1) +* +* FIELDS (msb -> lsb) +* (rw) PDSET1 +* (rw) PDSET0 +* +* (1) For C6418/C6413/C6410 only +* +* Note: Read of these two bits is indeterminate +\******************************************************************************/ +#if (CHIP_6413 | CHIP_6418 | CHIP_6410) + #define _I2C_I2CPDSET_OFFSET 22 + + #define _I2C_I2CPDSET0_ADDR 0x01B40058 + #define _I2C_I2CPDSET1_ADDR 0x01B44058 + + #define _I2C_I2CPDSET_SDAOUT_MASK 0x00000002u + #define _I2C_I2CPDSET_SDAOUT_SHIFT 0x00000001u + #define I2C_I2CPDSET_SDAOUT_DEFAULT 0x00000000u + #define I2C_I2CPDSET_SDAOUT_OF(x) _VALUEOF(x) + #define I2C_I2CPDSET_SDAOUT_UNCHGN 0x00000000u + #define I2C_I2CPDSET_SDAOUT_SET 0x00000001u + + #define _I2C_I2CPDSET_SCLOUT_MASK 0x00000001u + #define _I2C_I2CPDSET_SCLOUT_SHIFT 0x00000000u + #define I2C_I2CPDSET_SCLOUT_DEFAULT 0x00000000u + #define I2C_I2CPDSET_SCLOUT_OF(x) _VALUEOF(x) + #define I2C_I2CPDSET_SCLOUT_UNCHGN 0x00000000u + #define I2C_I2CPDSET_SCLOUT_SET 0x00000001u + + #define I2C_I2CPDSET_OF(x) _VALUEOF(x) + + #define I2C_I2CPDSET_DEFAULT (Uint32)(\ + _PER_FDEFAULT(I2C,I2CPDSET,SDAOUT)\ + |_PER_FDEFAULT(I2C,I2CPDSET,SCLOUT)\ + ) + + #define I2C_I2CPDSET_RMK(sdaout,sclout) (Uint32)(\ + _PER_FMK(I2C,I2CPDSET,SDAOUT,sdaout)\ + |_PER_FMK(I2C,I2CPDSET,SCLOUT,sclout)\ + ) + + #define _I2C_I2CPDSET_FGET(N,FIELD)\ + _PER_FGET(_I2C_I2CPDSET##N##_ADDR,I2C,I2CPDSET,##FIELD) + + #define _I2C_I2CPDSET_FSET(N,FIELD,field)\ + _PER_FSET(_I2C_I2CPDSET##N##_ADDR,I2C,I2CPDSET,##FIELD,field) + + #define _I2C_I2CPDSET_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_I2C_I2CPDSET##N##_ADDR,I2C,I2CPDSET,##FIELD,##SYM) + + #define _I2C_I2CPDSET0_FGET(FIELD) _I2C_I2CPDSET_FGET(0,##FIELD) + #define _I2C_I2CPDSET1_FGET(FIELD) _I2C_I2CPDSET_FGET(1,##FIELD) + + #define _I2C_I2CPDSET0_FSET(FIELD,f) _I2C_I2CPDSET_FSET(0,##FIELD,f) + #define _I2C_I2CPDSET1_FSET(FIELD,f) _I2C_I2CPDSET_FSET(1,##FIELD,f) + + #define _I2C_I2CPDSET0_FSETS(FIELD,SYM) _I2C_I2CPDSET_FSETS(0,##FIELD,##SYM) + #define _I2C_I2CPDSET1_FSETS(FIELD,SYM) _I2C_I2CPDSET_FSETS(1,##FIELD,##SYM) +#endif /* CHIP_6413 | CHIP_6418 | CHIP_6410) */ + +/******************************************************************************\ +* _____________________ +* | | +* | I 2 C P D C L R | +* |___________________| +* +* I2CPDCLR0 - I2C 0 Pin Data Clear Register(1) +* I2CPDCLR1 - I2C 1 Pin Data Clear Register(1) +* +* FIELDS (msb -> lsb) +* (rw) PDCLR1 +* (rw) PDCLR0 +* +* (1) For C6418/C6413/C6410 only +* +* Note: Read of these two bits is indeterminate +\******************************************************************************/ +#if (CHIP_6413 | CHIP_6418 | CHIP_6410) + #define _I2C_I2CPDCLR_OFFSET 23 + + #define _I2C_I2CPDCLR0_ADDR 0x01B4005C + #define _I2C_I2CPDCLR1_ADDR 0x01B4405C + + #define _I2C_I2CPDCLR_SDAOUT_MASK 0x00000002u + #define _I2C_I2CPDCLR_SDAOUT_SHIFT 0x00000001u + #define I2C_I2CPDCLR_SDAOUT_DEFAULT 0x00000000u + #define I2C_I2CPDCLR_SDAOUT_OF(x) _VALUEOF(x) + #define I2C_I2CPDCLR_SDAOUT_UNCHGN 0x00000000u + #define I2C_I2CPDCLR_SDAOUT_CLR 0x00000001u + + #define _I2C_I2CPDCLR_SCLOUT_MASK 0x00000001u + #define _I2C_I2CPDCLR_SCLOUT_SHIFT 0x00000000u + #define I2C_I2CPDCLR_SCLOUT_DEFAULT 0x00000000u + #define I2C_I2CPDCLR_SCLOUT_OF(x) _VALUEOF(x) + #define I2C_I2CPDCLR_SCLOUT_UNCHGN 0x00000000u + #define I2C_I2CPDCLR_SCLOUT_CLR 0x00000001u + + #define I2C_I2CPDCLR_OF(x) _VALUEOF(x) + + #define I2C_I2CPDCLR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(I2C,I2CPDCLR,SDAOUT)\ + |_PER_FDEFAULT(I2C,I2CPDCLR,SCLOUT)\ + ) + + #define I2C_I2CPDCLR_RMK(sdaout,sclout) (Uint32)(\ + _PER_FMK(I2C,I2CPDCLR,SDAOUT,sdaout)\ + |_PER_FMK(I2C,I2CPDCLR,SCLOUT,sclout)\ + ) + + #define _I2C_I2CPDCLR_FGET(N,FIELD)\ + _PER_FGET(_I2C_I2CPDCLR##N##_ADDR,I2C,I2CPDCLR,##FIELD) + + #define _I2C_I2CPDCLR_FSET(N,FIELD,field)\ + _PER_FSET(_I2C_I2CPDCLR##N##_ADDR,I2C,I2CPDCLR,##FIELD,field) + + #define _I2C_I2CPDCLR_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_I2C_I2CPDCLR##N##_ADDR,I2C,I2CPDCLR,##FIELD,##SYM) + + #define _I2C_I2CPDCLR0_FGET(FIELD) _I2C_I2CPDCLR_FGET(0,##FIELD) + #define _I2C_I2CPDCLR1_FGET(FIELD) _I2C_I2CPDCLR_FGET(1,##FIELD) + + #define _I2C_I2CPDCLR0_FSET(FIELD,f) _I2C_I2CPDCLR_FSET(0,##FIELD,f) + #define _I2C_I2CPDCLR1_FSET(FIELD,f) _I2C_I2CPDCLR_FSET(1,##FIELD,f) + + #define _I2C_I2CPDCLR0_FSETS(FIELD,SYM) _I2C_I2CPDCLR_FSETS(0,##FIELD,##SYM) + #define _I2C_I2CPDCLR1_FSETS(FIELD,SYM) _I2C_I2CPDCLR_FSETS(1,##FIELD,##SYM) +#endif /* CHIP_6413 | CHIP_6418 | CHIP_6410 */ + +#endif /* I2C_SUPPORT */ +#endif /* _CSL_I2CHAL_H_ */ +/******************************************************************************\ +* End of csl_i2chal.h +\******************************************************************************/ diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_irq.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_irq.h new file mode 100644 index 0000000..d0b832d --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_irq.h @@ -0,0 +1,390 @@ +/******************************************************************************\ +* Copyright (C) 1999-2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_irq.h +* DATE CREATED.. 06/09/1999 +* LAST MODIFIED. 08/02/2004 - Adding support for C6418 +* 07/24/2004 - Re-introducing BIOS components from CSL due to compatibility issues. +* 02/05/2004 Removed bios related components +* 10/03/2001 +* - CHIP_RSET()/CHIP_RGET() replaced by CHIP_CRSET()/CHIP_CRGET() +\******************************************************************************/ +#ifndef _CSL_IRQ_H_ +#define _CSL_IRQ_H_ + +#include +#include +#include + + +#if (IRQ_SUPPORT) +/******************************************************************************\ +* scope and inline control macros +\******************************************************************************/ +#ifdef __cplusplus +#define CSLAPI extern "C" far +#else +#define CSLAPI extern far +#endif + +#undef USEDEFS +#undef IDECL +#undef IDEF + +#ifdef _IRQ_MOD_ + #define IDECL CSLAPI + #define USEDEFS + #define IDEF +#else + #ifdef _INLINE + #define IDECL static inline + #define USEDEFS + #define IDEF static inline + #else + #define IDECL CSLAPI + #endif +#endif + + +/******************************************************************************\ +* global macro declarations +\******************************************************************************/ + +/* misc global settings */ +#define IRQ_INT_CNT 16 +#define IRQ_EVENT_CNT 32 + +#define IRQ_EVT_NA IRQ_EVENT_CNT + +/* event id definitions */ +#if (CHIP_6410 | CHIP_6413 | CHIP_6418) + + #define IRQ_EVT_DSPINT 0 + #define IRQ_EVT_TINT0 1 + #define IRQ_EVT_TINT1 2 + #define IRQ_EVT_SDINTA 3 + #define IRQ_EVT_EXTINT4 4 + #define IRQ_EVT_GPINT4 4 + #define IRQ_EVT_EXTINT5 5 + #define IRQ_EVT_GPINT5 5 + #define IRQ_EVT_EXTINT6 6 + #define IRQ_EVT_GPINT6 6 + #define IRQ_EVT_EXTINT7 7 + #define IRQ_EVT_GPINT7 7 + #define IRQ_EVT_EDMAINT 8 + #define IRQ_EVT_EMUDTDMA 9 + #define IRQ_EVT_EMURTDXRX 10 + #define IRQ_EVT_EMURTDXTX 11 + #define IRQ_EVT_XINT0 12 + #define IRQ_EVT_RINT0 13 + #define IRQ_EVT_XINT1 14 + #define IRQ_EVT_RINT1 15 + #define IRQ_EVT_GPINT0 16 + #define IRQ_EVT_TINT2 19 + #define IRQ_EVT_I2CINT0 22 + #define IRQ_EVT_I2CINT1 23 + #define IRQ_EVT_AXINT1 24 + #define IRQ_EVT_ARINT1 25 + #define IRQ_EVT_AXINT0 28 + #define IRQ_EVT_ARINT0 29 + + #if (CHIP_6418) + #define IRQ_EVT_VCPINT 30 + #endif + +#else + + #if (CHIP_DM642 | CHIP_DM641 | CHIP_DM640 | CHIP_6412) + + #define IRQ_EVT_DSPINT 0 + #define IRQ_EVT_TINT0 1 + #define IRQ_EVT_TINT1 2 + #define IRQ_EVT_SDINTA 3 + #define IRQ_EVT_EXTINT4 4 + #define IRQ_EVT_GPINT4 4 + #define IRQ_EVT_EXTINT5 5 + #define IRQ_EVT_GPINT5 5 + #define IRQ_EVT_EXTINT6 6 + #define IRQ_EVT_GPINT6 6 + #define IRQ_EVT_EXTINT7 7 + #define IRQ_EVT_GPINT7 7 + #define IRQ_EVT_EDMAINT 8 + #define IRQ_EVT_EMUDTDMA 9 + #define IRQ_EVT_EMURTDXRX 10 + #define IRQ_EVT_EMURTDXTX 11 + #define IRQ_EVT_XINT0 12 + #define IRQ_EVT_RINT0 13 + #define IRQ_EVT_XINT1 14 + #define IRQ_EVT_RINT1 15 + #define IRQ_EVT_GPINT0 16 + #define IRQ_EVT_TINT2 19 + #define IRQ_EVT_I2CINT0 22 + #define IRQ_EVT_MACINT 24 + + #if !(CHIP_6412) + #define IRQ_EVT_VINT0 25 + #define IRQ_EVT_VINT1 26 + #endif + + #if (CHIP_DM642) + #define IRQ_EVT_VINT2 27 + #endif + + #if !(CHIP_6412) + #define IRQ_EVT_AXINT0 28 + #define IRQ_EVT_ARINT0 29 + #endif + + #else + + #define IRQ_EVT_DSPINT 0 + #define IRQ_EVT_TINT0 1 + #define IRQ_EVT_TINT1 2 + #define IRQ_EVT_SDINT 3 + #define IRQ_EVT_SDINTA 3 + #define IRQ_EVT_EXTINT4 4 + #define IRQ_EVT_GPINT4 4 + #define IRQ_EVT_EXTINT5 5 + #define IRQ_EVT_GPINT5 5 + #define IRQ_EVT_EXTINT6 6 + #define IRQ_EVT_GPINT6 6 + #define IRQ_EVT_EXTINT7 7 + #define IRQ_EVT_GPINT7 7 + #define IRQ_EVT_EDMAINT 8 + #define IRQ_EVT_DMAINT0 8 + #define IRQ_EVT_EMUDTDMA 9 + #define IRQ_EVT_DMAINT1 9 + #define IRQ_EVT_EMURTDXRX 10 + #define IRQ_EVT_DMAINT2 10 + #define IRQ_EVT_EMURTDXTX 11 + #define IRQ_EVT_DMAINT3 11 + #define IRQ_EVT_XINT0 12 + #define IRQ_EVT_RINT0 13 + #define IRQ_EVT_XINT1 14 + #define IRQ_EVT_RINT1 15 + #define IRQ_EVT_GPINT0 16 + #define IRQ_EVT_XINT2 17 + #define IRQ_EVT_RINT2 18 + #define IRQ_EVT_TINT2 19 + #define IRQ_EVT_SDINTB 20 + #define IRQ_EVT_PCIWAKE 21 + #define IRQ_EVT_MDIO 21 + #define IRQ_EVT_QDMAERR 22 + #define IRQ_EVT_I2CINT0 22 /* 6713 */ + #define IRQ_EVT_UINT 23 + #define IRQ_EVT_I2CINT1 23 /* 6713 */ + #define IRQ_EVT_I2CINT2 23 + #define IRQ_EVT_I2CINT3 22 + #define IRQ_EVT_I2CINT4 23 + + #define IRQ_EVT_MACINT 24 /* DM642 */ + #define IRQ_EVT_VINT0 25 /* DM642 */ + #define IRQ_EVT_VINT1 26 /* DM642 */ + #define IRQ_EVT_VINT2 27 /* DM642 */ + #define IRQ_EVT_AXINT0 28 /* 6713 / DM642 */ + #define IRQ_EVT_ARINT0 29 /* 6713 / DM642 */ + #define IRQ_EVT_AXINT3 IRQ_EVT_EXTINT4 /* 6713 */ + #define IRQ_EVT_ARINT3 IRQ_EVT_EXTINT5 /* 6713 */ + #define IRQ_EVT_VCPINT 30 + #define IRQ_EVT_AXINT1 30 /* 6713 */ + + #define IRQ_EVT_AXINT2 30 /* 6713 */ + #define IRQ_EVT_AXINT4 IRQ_EVT_EXTINT6 + #define IRQ_EVT_TCPINT 31 + #define IRQ_EVT_ARINT1 31 /* 6713 */ + + #define IRQ_EVT_ARINT2 31 /* 6713 */ + #define IRQ_EVT_ARINT4 IRQ_EVT_EXTINT7 + + #endif + +#endif +/* interrupt masks */ +#define IRQ_MASK_NA 0x00000000 +#define IRQ_MASK_00 0x00000001 +#define IRQ_MASK_01 0x00000002 +#define IRQ_MASK_02 0x00000004 +#define IRQ_MASK_03 0x00000008 +#define IRQ_MASK_04 0x00000010 +#define IRQ_MASK_05 0x00000020 +#define IRQ_MASK_06 0x00000040 +#define IRQ_MASK_07 0x00000080 +#define IRQ_MASK_08 0x00000100 +#define IRQ_MASK_09 0x00000200 +#define IRQ_MASK_10 0x00000400 +#define IRQ_MASK_11 0x00000800 +#define IRQ_MASK_12 0x00001000 +#define IRQ_MASK_13 0x00002000 +#define IRQ_MASK_14 0x00004000 +#define IRQ_MASK_15 0x00008000 + +/* defines used with the dispatcher functions */ +#define IRQ_CCMASK_NONE 0x00000001u +#define IRQ_CCMASK_PCC_MAPPED 0x00000000u +#define IRQ_CCMASK_PCC_ENABLE 0x00000040u +#define IRQ_CCMASK_PCC_FREEZE 0x00000060u +#define IRQ_CCMASK_PCC_BYPASS 0x00000080u +#define IRQ_CCMASK_DCC_MAPPED 0x00000000u +#define IRQ_CCMASK_DCC_ENABLE 0x00000008u +#define IRQ_CCMASK_DCC_FREEZE 0x0000000Cu +#define IRQ_CCMASK_DCC_BYPASS 0x00000010u +#define IRQ_CCMASK_DEFAULT IRQ_CCMASK_NONE +#define IRQ_IEMASK_SELF 0x80000000u +#define IRQ_IEMASK_ALL 0x0000FFFFu +#define IRQ_IEMASK_DEFAULT IRQ_IEMASK_SELF + + +/* private stuff */ +#define _IRQ_DISPATCHTABLE_CNT (IRQ_INT_CNT) +#define _IRQ_EVENT2INTTABLE_CNT (IRQ_EVENT_CNT+1) +#define _IRQ_INT2EVENTTABLE_CNT (IRQ_INT_CNT) + + +/******************************************************************************\ +* global typedef declarations +\******************************************************************************/ +typedef struct { + void *funcAddr; + Uint32 ieMask; + Uint32 ccMask; + Uint32 funcArg; +} _IRQ_Dispatch; + +typedef struct { + void *funcAddr; + Uint32 funcArg; + Uint32 ccMask; + Uint32 ieMask; +} IRQ_Config; + + +/******************************************************************************\ +* global variable declarations +\******************************************************************************/ + +/* private vars */ +extern far Uint32 _IRQ_eventTable[IRQ_EVENT_CNT+1]; +extern far Uint32 _IRQ_intTable[IRQ_INT_CNT]; +extern far _IRQ_Dispatch _IRQ_internalDispatchTable[_IRQ_DISPATCHTABLE_CNT]; +extern far _IRQ_Dispatch *_IRQ_dispatchTable; + +/******************************************************************************\ +* global function declarations +\******************************************************************************/ + +/* private functions */ +CSLAPI void _IRQ_init(Uint32 biosPresent, _IRQ_Dispatch *dispatchTable); + +/* API functions */ +CSLAPI void IRQ_map(Uint32 eventId, Uint32 intNumber); +CSLAPI void *IRQ_setVecs(void *vecs); +CSLAPI Uint32 IRQ_biosPresent(); +CSLAPI void IRQ_hook(int intNum, void *func); + +/* These functions only work with the DSP/BIOS HWI dispatcher */ +CSLAPI void IRQ_config(Uint32 eventId, IRQ_Config *config); +CSLAPI void IRQ_configArgs(Uint32 eventId, void *funcAddr, Uint32 funcArg, + Uint32 ccMask, Uint32 ieMask); +CSLAPI void IRQ_getConfig(Uint32 eventId, IRQ_Config *config); +CSLAPI Uint32 IRQ_getArg(Uint32 eventId); +CSLAPI void IRQ_setArg(Uint32 eventId, Uint32 arg); + + +/******************************************************************************\ +* inline function declarations +\******************************************************************************/ +IDECL void IRQ_enable(Uint32 eventId); +IDECL Uint32 IRQ_disable(Uint32 eventId); +IDECL void IRQ_restore(Uint32 eventId, Uint32 ie); +IDECL void IRQ_set(Uint32 eventId); +IDECL void IRQ_clear(Uint32 eventId); +IDECL Uint32 IRQ_test(Uint32 eventId); +IDECL void IRQ_reset(Uint32 eventId); +IDECL void IRQ_resetAll(); + +IDECL void IRQ_globalEnable(); +IDECL Uint32 IRQ_globalDisable(); +IDECL void IRQ_globalRestore(Uint32 gie); + +IDECL void IRQ_nmiEnable(); +IDECL void IRQ_nmiDisable(); + + +/******************************************************************************\ +* inline function definitions +\******************************************************************************/ +#ifdef USEDEFS +/*----------------------------------------------------------------------------*/ +IDEF void IRQ_enable(Uint32 eventId) { + IER |= _IRQ_eventTable[eventId]; +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 IRQ_disable(Uint32 eventId) { + Uint32 ie = IER & _IRQ_eventTable[eventId]; + IER &= ~_IRQ_eventTable[eventId]; + return ie; +} +/*----------------------------------------------------------------------------*/ +IDEF void IRQ_restore(Uint32 eventId, Uint32 ie) { + if (ie) { + IER |= _IRQ_eventTable[eventId]; + } else { + IER &= ~_IRQ_eventTable[eventId]; + } +} +/*----------------------------------------------------------------------------*/ +IDEF void IRQ_set(Uint32 eventId) { + ISR = _IRQ_eventTable[eventId]; +} +/*----------------------------------------------------------------------------*/ +IDEF void IRQ_clear(Uint32 eventId) { + ICR = _IRQ_eventTable[eventId]; +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 IRQ_test(Uint32 eventId) { + return (Uint32)((IFR & _IRQ_eventTable[eventId]) ? 1 : 0); +} +/*----------------------------------------------------------------------------*/ +IDEF void IRQ_globalEnable() { + CHIP_FSET(CSR,GIE,1); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 IRQ_globalDisable() { + Uint32 gie = CHIP_FGET(CSR,GIE); + CHIP_FSET(CSR,GIE,0); + return gie; +} +/*----------------------------------------------------------------------------*/ +IDEF void IRQ_globalRestore(Uint32 gie) { + CHIP_FSET(CSR,GIE,gie); +} +/*----------------------------------------------------------------------------*/ +IDEF void IRQ_reset(Uint32 eventId) { + IER &= ~_IRQ_eventTable[eventId]; + ICR = _IRQ_eventTable[eventId]; +} +/*----------------------------------------------------------------------------*/ +IDEF void IRQ_resetAll() { + CHIP_FSET(CSR,GIE,0); + CHIP_CRSET(IER,0x00000000); + CHIP_CRSET(ICR,0xFFFFFFFF); +} +/*----------------------------------------------------------------------------*/ +IDEF void IRQ_nmiEnable() { + IER |= 0x00000002; +} +/*----------------------------------------------------------------------------*/ +IDEF void IRQ_nmiDisable() { + IER &= ~0x00000002; +} +/*----------------------------------------------------------------------------*/ +#endif /* USEDEFS */ + + +#endif /* IRQ_SUPPORT */ +#endif /* _CSL_IRQ_H_ */ +/******************************************************************************\ +* End of csl_irq.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_irqhal.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_irqhal.h new file mode 100644 index 0000000..0a21ce1 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_irqhal.h @@ -0,0 +1,292 @@ +/******************************************************************************\ +* Copyright (C) 1999-2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_irqhal.h +* DATE CREATED.. 06/20/1999 +* LAST MODIFIED. 10/03/2000 +*------------------------------------------------------------------------------ +* REGISTERS +* +* MUXH - interrupt multiplexer high register +* MUXL - interrupt multiplexer low register +* EXTPOL - external interrupt polarity register +* +\******************************************************************************/ +#ifndef _CSL_IRQHAL_H_ +#define _CSL_IRQHAL_H_ + +#include +#include + +#if (IRQ_SUPPORT) +/******************************************************************************\ +* MISC section +\******************************************************************************/ + + +/******************************************************************************\ +* module level register/field access macros +\******************************************************************************/ + + /* ----------------- */ + /* FIELD MAKE MACROS */ + /* ----------------- */ + + #define IRQ_FMK(REG,FIELD,x)\ + _PER_FMK(IRQ,##REG,##FIELD,x) + + #define IRQ_FMKS(REG,FIELD,SYM)\ + _PER_FMKS(IRQ,##REG,##FIELD,##SYM) + + + /* -------------------------------- */ + /* RAW REGISTER/FIELD ACCESS MACROS */ + /* -------------------------------- */ + + #define IRQ_ADDR(REG)\ + _IRQ_##REG##_ADDR + + #define IRQ_RGET(REG)\ + _PER_RGET(_IRQ_##REG##_ADDR,IRQ,##REG) + + #define IRQ_RSET(REG,x)\ + _PER_RSET(_IRQ_##REG##_ADDR,IRQ,##REG,x) + + #define IRQ_FGET(REG,FIELD)\ + _IRQ_##REG##_FGET(##FIELD) + + #define IRQ_FSET(REG,FIELD,x)\ + _IRQ_##REG##_FSET(##FIELD,##x) + + #define IRQ_FSETS(REG,FIELD,SYM)\ + _IRQ_##REG##_FSETS(##FIELD,##SYM) + + + /* ------------------------------------------ */ + /* ADDRESS BASED REGISTER/FIELD ACCESS MACROS */ + /* ------------------------------------------ */ + + #define IRQ_RGETA(addr,REG)\ + _PER_RGET(addr,IRQ,##REG) + + #define IRQ_RSETA(addr,REG,x)\ + _PER_RSET(addr,IRQ,##REG,x) + + #define IRQ_FGETA(addr,REG,FIELD)\ + _PER_FGET(addr,IRQ,##REG,##FIELD) + + #define IRQ_FSETA(addr,REG,FIELD,x)\ + _PER_FSET(addr,IRQ,##REG,##FIELD,x) + + #define IRQ_FSETSA(addr,REG,FIELD,SYM)\ + _PER_FSETS(addr,IRQ,##REG,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | M U X H | +* |___________________| +* +* MUXH - interrupt multiplexer high register +* +* FIELDS (msb -> lsb) +* (rw) INTSEL15 +* (rw) INTSEL14 +* (rw) INTSEL13 +* (rw) INTSEL12 +* (rw) INTSEL11 +* (rw) INTSEL10 +* +\******************************************************************************/ + #define _IRQ_MUXH_ADDR 0x019C0000u + + #define _IRQ_MUXH_INTSEL15_MASK 0x7C000000u + #define _IRQ_MUXH_INTSEL15_SHIFT 0x0000001Au + #define IRQ_MUXH_INTSEL15_DEFAULT 0x00000002u + #define IRQ_MUXH_INTSEL15_OF(x) _VALUEOF(x) + + #define _IRQ_MUXH_INTSEL14_MASK 0x03E00000u + #define _IRQ_MUXH_INTSEL14_SHIFT 0x00000015u + #define IRQ_MUXH_INTSEL14_DEFAULT 0x00000001u + #define IRQ_MUXH_INTSEL14_OF(x) _VALUEOF(x) + + #define _IRQ_MUXH_INTSEL13_MASK 0x001F0000u + #define _IRQ_MUXH_INTSEL13_SHIFT 0x00000010u + #define IRQ_MUXH_INTSEL13_DEFAULT 0x00000000u + #define IRQ_MUXH_INTSEL13_OF(x) _VALUEOF(x) + + #define _IRQ_MUXH_INTSEL12_MASK 0x00007C00u + #define _IRQ_MUXH_INTSEL12_SHIFT 0x0000000Au + #define IRQ_MUXH_INTSEL12_DEFAULT 0x0000000Bu + #define IRQ_MUXH_INTSEL12_OF(x) _VALUEOF(x) + + #define _IRQ_MUXH_INTSEL11_MASK 0x000003E0u + #define _IRQ_MUXH_INTSEL11_SHIFT 0x00000005u + #define IRQ_MUXH_INTSEL11_DEFAULT 0x0000000Au + #define IRQ_MUXH_INTSEL11_OF(x) _VALUEOF(x) + + #define _IRQ_MUXH_INTSEL10_MASK 0x0000001Fu + #define _IRQ_MUXH_INTSEL10_SHIFT 0x00000000u + #define IRQ_MUXH_INTSEL10_DEFAULT 0x00000003u + #define IRQ_MUXH_INTSEL10_OF(x) _VALUEOF(x) + + #define IRQ_MUXH_OF(x) _VALUEOF(x) + + #define IRQ_MUXH_DEFAULT (Uint32)( \ + _PER_FDEFAULT(IRQ,MUXH,INTSEL15) \ + |_PER_FDEFAULT(IRQ,MUXH,INTSEL14) \ + |_PER_FDEFAULT(IRQ,MUXH,INTSEL13) \ + |_PER_FDEFAULT(IRQ,MUXH,INTSEL12) \ + |_PER_FDEFAULT(IRQ,MUXH,INTSEL11) \ + |_PER_FDEFAULT(IRQ,MUXH,INTSEL10) \ + ) + + #define IRQ_MUXH_RMK(intsel15,intsel14,intsel13,intsel12,intsel11,intsel10) \ + (Uint32)( \ + _PER_FMK(IRQ,MUXH,INTSEL15,intsel15) \ + |_PER_FMK(IRQ,MUXH,INTSEL14,intsel14) \ + |_PER_FMK(IRQ,MUXH,INTSEL13,intsel13) \ + |_PER_FMK(IRQ,MUXH,INTSEL12,intsel12) \ + |_PER_FMK(IRQ,MUXH,INTSEL11,intsel11) \ + |_PER_FMK(IRQ,MUXH,INTSEL10,intsel10) \ + ) + + #define _IRQ_MUXH_FGET(FIELD)\ + _PER_FGET(_IRQ_MUXH_ADDR,IRQ,MUXH,##FIELD) + + #define _IRQ_MUXH_FSET(FIELD,field)\ + _PER_FSET(_IRQ_MUXH_ADDR,IRQ,MUXH,##FIELD,field) + + #define _IRQ_MUXH_FSETS(FIELD,SYM)\ + _PER_FSETS(_IRQ_MUXH_ADDR,IRQ,MUXH,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | M U X L | +* |___________________| +* +* MUXL - interrupt multiplexer low register +* +* FIELDS (msb -> lsb) +* (rw) INTSEL9 +* (rw) INTSEL8 +* (rw) INTSEL7 +* (rw) INTSEL6 +* (rw) INTSEL5 +* (rw) INTSEL4 +* +\******************************************************************************/ + #define _IRQ_MUXL_ADDR 0x019C0004u + + #define _IRQ_MUXL_INTSEL9_MASK 0x7C000000u + #define _IRQ_MUXL_INTSEL9_SHIFT 0x0000001Au + #define IRQ_MUXL_INTSEL9_DEFAULT 0x00000009u + #define IRQ_MUXL_INTSEL9_OF(x) _VALUEOF(x) + + #define _IRQ_MUXL_INTSEL8_MASK 0x03E00000u + #define _IRQ_MUXL_INTSEL8_SHIFT 0x00000015u + #define IRQ_MUXL_INTSEL8_DEFAULT 0x00000008u + #define IRQ_MUXL_INTSEL8_OF(x) _VALUEOF(x) + + #define _IRQ_MUXL_INTSEL7_MASK 0x001F0000u + #define _IRQ_MUXL_INTSEL7_SHIFT 0x00000010u + #define IRQ_MUXL_INTSEL7_DEFAULT 0x00000007u + #define IRQ_MUXL_INTSEL7_OF(x) _VALUEOF(x) + + #define _IRQ_MUXL_INTSEL6_MASK 0x00007C00u + #define _IRQ_MUXL_INTSEL6_SHIFT 0x0000000Au + #define IRQ_MUXL_INTSEL6_DEFAULT 0x00000006u + #define IRQ_MUXL_INTSEL6_OF(x) _VALUEOF(x) + + #define _IRQ_MUXL_INTSEL5_MASK 0x000003E0u + #define _IRQ_MUXL_INTSEL5_SHIFT 0x00000005u + #define IRQ_MUXL_INTSEL5_DEFAULT 0x00000005u + #define IRQ_MUXL_INTSEL5_OF(x) _VALUEOF(x) + + #define _IRQ_MUXL_INTSEL4_MASK 0x0000001Fu + #define _IRQ_MUXL_INTSEL4_SHIFT 0x00000000u + #define IRQ_MUXL_INTSEL4_DEFAULT 0x00000004u + #define IRQ_MUXL_INTSEL4_OF(x) _VALUEOF(x) + + #define IRQ_MUXL_OF(x) _VALUEOF(x) + + #define IRQ_MUXL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(IRQ,MUXL,INTSEL9) \ + |_PER_FDEFAULT(IRQ,MUXL,INTSEL8) \ + |_PER_FDEFAULT(IRQ,MUXL,INTSEL7) \ + |_PER_FDEFAULT(IRQ,MUXL,INTSEL6) \ + |_PER_FDEFAULT(IRQ,MUXL,INTSEL5) \ + |_PER_FDEFAULT(IRQ,MUXL,INTSEL4) \ + ) + + #define IRQ_MUXL_RMK(intsel9,intsel8,intsel7,intsel6,intsel5,intsel4) \ + (Uint32)( \ + _PER_FMK(IRQ,MUXL,INTSEL9,intsel9) \ + |_PER_FMK(IRQ,MUXL,INTSEL8,intsel8) \ + |_PER_FMK(IRQ,MUXL,INTSEL7,intsel7) \ + |_PER_FMK(IRQ,MUXL,INTSEL6,intsel6) \ + |_PER_FMK(IRQ,MUXL,INTSEL5,intsel5) \ + |_PER_FMK(IRQ,MUXL,INTSEL4,intsel4) \ + ) + + #define _IRQ_MUXL_FGET(FIELD)\ + _PER_FGET(_IRQ_MUXL_ADDR,IRQ,MUXL,##FIELD) + + #define _IRQ_MUXL_FSET(FIELD,field)\ + _PER_FSET(_IRQ_MUXL_ADDR,IRQ,MUXL,##FIELD,field) + + #define _IRQ_MUXL_FSETS(FIELD,SYM)\ + _PER_FSETS(_IRQ_MUXL_ADDR,IRQ,MUXL,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | E X T P O L | +* |___________________| +* +* EXTPOL - external interrupt polarity register +* +* FIELDS (msb -> lsb) +* (rw) XIP +* +\******************************************************************************/ + #define _IRQ_EXTPOL_ADDR 0x019C0008u + + #define _IRQ_EXTPOL_XIP_MASK 0x0000000Fu + #define _IRQ_EXTPOL_XIP_SHIFT 0x00000000u + #define IRQ_EXTPOL_XIP_DEFAULT 0x00000000u + #define IRQ_EXTPOL_XIP_OF(x) _VALUEOF(x) + + #define IRQ_EXTPOL_OF(x) _VALUEOF(x) + + #define IRQ_EXTPOL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(IRQ,EXTPOL,XIP) \ + ) + + #define IRQ_EXTPOL_RMK(xip) (Uint32)( \ + _PER_FMK(IRQ,EXTPOL,XIP,xip) \ + ) + + #define _IRQ_EXTPOL_FGET(FIELD)\ + _PER_FGET(_IRQ_EXTPOL_ADDR,IRQ,EXTPOL,##FIELD) + + #define _IRQ_EXTPOL_FSET(FIELD,field)\ + _PER_FSET(_IRQ_EXTPOL_ADDR,IRQ,EXTPOL,##FIELD,field) + + #define _IRQ_EXTPOL_FSETS(FIELD,SYM)\ + _PER_FSETS(_IRQ_EXTPOL_ADDR,IRQ,EXTPOL,##FIELD,##SYM) + + +/*----------------------------------------------------------------------------*/ + +#endif /* IRQ_SUPPORT */ +#endif /* _CSL_IRQHAL_H_ */ +/******************************************************************************\ +* End of csl_irqhal.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_legacy.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_legacy.h new file mode 100644 index 0000000..530ba6e --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_legacy.h @@ -0,0 +1,838 @@ +/* + * Copyright 2001 by Texas Instruments Incorporated. + * All rights reserved. Property of Texas Instruments Incorporated. + * Restricted rights to use, duplicate or disclose this code are + * granted through contract. + * U.S. Patent Nos. 5,283,900 5,392,448 + */ +/* "@(#) DSP/BIOS 4.50.2 03-27-01 (barracuda-i02)" */ +/******************************************************************************\ +* Copyright (C) 2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_legacy.h +* DATE CREATED.. 04/24/2000 +* LAST MODIFIED. 10/30/2001 - + EMIF_GBLCTL_NOHOLD_0 => EMIF_GBLCTL_NOHOLD_DISABLE + EMIF_GBLCTL_NOHOLD_1 => EMIF_GBLCTL_NOHOLD_ENABLE + MCBSP : Baseaddr => baseaddr +\******************************************************************************/ +#ifndef _CSL_LEGACY_H_ +#define _CSL_LEGACY_H_ + +#include + +/******************************************************************************\ +* scope and inline control macros +\******************************************************************************/ +#ifdef __cplusplus +#define CSLAPI extern "C" far +#else +#define CSLAPI extern far +#endif + +#undef USEDEFS +#undef IDECL +#undef IDEF + +#ifdef _LEGACY_MOD_ + #define IDECL CSLAPI + #define USEDEFS + #define IDEF +#else + #ifdef _INLINE + #define IDECL static inline + #define USEDEFS + #define IDEF static inline + #else + #define IDECL CSLAPI + #endif +#endif + + +/******************************************************************************\ +* global macro declarations +\******************************************************************************/ + +#if (CACHE_SUPPORT) + #define CACHE_64KSRAM CACHE_64KSRAM + #define CACHE_0KCACHE CACHE_0KCACHE + #define CACHE_48KSRAM CACHE_48KSRAM + #define CACHE_16KCACHE CACHE_16KCACHE + #define CACHE_32KSRAM CACHE_32KSRAM + #define CACHE_32KCACHE CACHE_32KCACHE + #define CACHE_16KSRAM CACHE_16KSRAM + #define CACHE_48KCACHE CACHE_48KCACHE + #define CACHE_0KSRAM CACHE_0KSRAM + #define CACHE_64KCACHE CACHE_64KCACHE + #define CACHE_L2MODE CACHE_L2Mode + #define CACHE_L2ALL CACHE_L2ALL + #define CACHE_L1PALL CACHE_L1PALL + #define CACHE_L1DALL CACHE_L1DALL + #define CACHE_REGION CACHE_Region + #define CACHE_PCCMAPPED CACHE_PCC_MAPPED + #define CACHE_PCCENABLE CACHE_PCC_ENABLE + #define CACHE_PCCFREEZE CACHE_PCC_FREEZE + #define CACHE_PCCBYPASS CACHE_PCC_BYPASS + #define CACHE_PCC CACHE_Pcc + #define CACHE_Reset CACHE_reset + #define CACHE_SetL2Mode CACHE_setL2Mode + #define CACHE_GetL2Mode CACHE_getL2Mode + #define CACHE_SetPccMode CACHE_setPccMode + #define CACHE_GetL2SramSize CACHE_getL2SramSize + //#define CACHE_Init CACHE_init + #define CACHE_Init() + #define CACHE_EnableCaching CACHE_enableCaching + + #define CACHE_Flush(r,a,w) CACHE_flush(r,(void*)(a),w) + #define CACHE_Clean(r,a,w) CACHE_clean(r,(void*)(a),w) + #define CACHE_Invalidate(r,a,w) CACHE_invalidate(r,(void*)(a),w) + +#endif /* CACHE_SUPPORT */ + +#if (1) + //#define CHIP_Init CHIP_init + #define CHIP_Init() + #define CHIP_GetCpuId CHIP_getCpuId + #define CHIP_GetRevId CHIP_getRevId + #define CHIP_GetEndian CHIP_getEndian + #define CHIP_GetMapMode CHIP_getMapMode +#endif + +#if (1) + #define CSL_Init CSL_init + #define CSLINIT_Init CSLINIT_init + #define CSLLIB_Init CSLLIB_init +#endif + +#if (DAT_SUPPORT) + #define DAT_Open DAT_open + #define DAT_Close DAT_close + #define DAT_Copy DAT_copy + #define DAT_Fill DAT_fill + #define DAT_Wait DAT_wait + #define DAT_Copy2D DAT_copy2d + //#define DAT_Init DAT_init + #define DAT_Init() + #define _DAT_Open _DAT_open + #define _DAT_Close _DAT_close + #define _DAT_Copy _DAT_copy + #define _DAT_Fill _DAT_fill + #define _DAT_Wait _DAT_wait + #define _DAT_Copy2D _DAT_copy2d + #define _DAT_Init _DAT_init +#endif /* DAT_SUPPORT */ + +#if (DMA_SUPPORT) + #define DMA_PRIVATE_OBJ DMA_PrivateObj + #define DMA_HANDLE DMA_Handle + #define DMA_CONFIG DMA_Config + #define DMA_GBL DMA_Gbl + #define DMA_HCHA0 _DMA_hCha0 + #define DMA_HCHA1 _DMA_hCha1 + #define DMA_HCHA2 _DMA_hCha2 + #define DMA_HCHA3 _DMA_hCha3 + #define DMA_GBL_PRIVATE DMA_gblPrivate + #define DMA_Reset DMA_reset + #define DMA_Open DMA_open + #define DMA_Close DMA_close + #define DMA_ConfigA DMA_config + #define DMA_ConfigB DMA_configArgs + #define DMA_AllocGlobalReg DMA_allocGlobalReg + #define DMA_FreeGlobalReg DMA_freeGlobalReg + //#define DMA_Init DMA_init + #define DMA_Init() + #define DMA_GetEventId DMA_getEventId + #define DMA_GetStatus DMA_getStatus + #define DMA_Start DMA_start + #define DMA_Stop DMA_stop + #define DMA_Pause DMA_pause + #define DMA_AutoStart DMA_autoStart + #define DMA_Wait DMA_wait + #define DMA_SetAuxCtl DMA_setAuxCtl + #define DMA_GetGlobalReg DMA_getGlobalReg + #define DMA_SetGlobalReg DMA_setGlobalReg + +#if (0) + #define DMA_GBL_ADDRRLDB 0x00000001u + #define DMA_GBL_ADDRRLDC 0x00000002u + #define DMA_GBL_ADDRRLDD 0x00000003u + #define DMA_GBL_INDEXA 0x00000004u + #define DMA_GBL_INDEXB 0x00000005u + #define DMA_GBL_CNTRLDA 0x00000008u + #define DMA_GBL_CNTRLDB 0x00000009u + #define DMA_GBL_SPLITA 0x0000000Du + #define DMA_GBL_SPLITB 0x0000000Eu + #define DMA_GBL_SPLITC 0x0000000Fu + + #define _DMA_GBLREG_CNT 16 + #define _DMA_GBLREG_MASK (_DMA_GBLREG_CNT-1) +#endif + + #define DMA_MK_AUXCTL(chpri,auxpri) ((Uint32)(\ + HFIELD_SHIFT(HDMA_AUXCTL_CHPRI,chpri)|\ + HFIELD_SHIFT(HDMA_AUXCTL_AUXPRI,auxpri)\ + )\ + ) + + #define DMA_MK_PRICTL(start,srcdir,dstdir,esize,split,cntrld,\ + index,rsync,wsync,pri,tcint,fs,emod,srcrld,dstrld) ((UINT32)(\ + HFIELD_SHIFT(HDMA_PRICTL_START,start)|\ + HFIELD_SHIFT(HDMA_PRICTL_SRCDIR,srcdir)|\ + HFIELD_SHIFT(HDMA_PRICTL_DSTDIR,dstdir)|\ + HFIELD_SHIFT(HDMA_PRICTL_ESIZE,esize)|\ + HFIELD_SHIFT(HDMA_PRICTL_SPLIT,split)|\ + HFIELD_SHIFT(HDMA_PRICTL_CNTRLD,cntrld)|\ + HFIELD_SHIFT(HDMA_PRICTL_INDEX,index)|\ + HFIELD_SHIFT(HDMA_PRICTL_RSYNC,rsync)|\ + HFIELD_SHIFT(HDMA_PRICTL_WSYNC,wsync)|\ + HFIELD_SHIFT(HDMA_PRICTL_PRI,pri)|\ + HFIELD_SHIFT(HDMA_PRICTL_TCINT,tcint)|\ + HFIELD_SHIFT(HDMA_PRICTL_FS,fs)|\ + HFIELD_SHIFT(HDMA_PRICTL_EMOD,emod)|\ + HFIELD_SHIFT(HDMA_PRICTL_SRCRLD,srcrld)|\ + HFIELD_SHIFT(HDMA_PRICTL_DSTRLD,dstrld)\ + )\ + ) + + #define DMA_MK_SECCTL(sxie,frameie,lastie,blockie,rdropie,wdropie,\ + dmacen,fsig,rspol,wspol) ((UINT32)(\ + HFIELD_SHIFT(HDMA_SECCTL_SXIE,sxie)|\ + HFIELD_SHIFT(HDMA_SECCTL_FRAMEIE,frameie)|\ + HFIELD_SHIFT(HDMA_SECCTL_LASTIE,lastie)|\ + HFIELD_SHIFT(HDMA_SECCTL_BLOCKIE,blockie)|\ + HFIELD_SHIFT(HDMA_SECCTL_RDROPIE,rdropie)|\ + HFIELD_SHIFT(HDMA_SECCTL_WDROPIE,wdropie)|\ + HFIELD_SHIFT(HDMA_SECCTL_DMACEN,dmacen)|\ + HFIELD_SHIFT(HDMA_SECCTL_FSIG,fsig)|\ + HFIELD_SHIFT(HDMA_SECCTL_RSPOL,rspol)|\ + HFIELD_SHIFT(HDMA_SECCTL_WSPOL,wspol)\ + )\ + ) + + #define DMA_MK_SRC(src) ((Uint32)(\ + HFIELD_SHIFT(HDMA_SRC_SRC,src)\ + )\ + ) + + #define DMA_MK_DST(dst) ((Uint32)(\ + HFIELD_SHIFT(HDMA_DST_DST,dst)\ + )\ + ) + + #define DMA_MK_XFRCNT(elecnt,frmcnt) ((Uint32)(\ + HFIELD_SHIFT(HDMA_XFRCNT_ELECNT,elecnt)|\ + HFIELD_SHIFT(HDMA_XFRCNT_FRMCNT,frmcnt)\ + )\ + ) + + #define DMA_MK_GBLCNT(elecnt,frmcnt) ((Uint32)(\ + HFIELD_SHIFT(HDMA_GBLCNT_ELECNT,elecnt)|\ + HFIELD_SHIFT(HDMA_GBLCNT_FRMCNT,frmcnt)\ + )\ + ) + + #define DMA_MK_GBLIDX(eleidx,frmidx) ((Uint32)(\ + HFIELD_SHIFT(HDMA_GBLIDX_ELEIDX,eleidx)|\ + HFIELD_SHIFT(HDMA_GBLIDX_FRMIDX,frmidx)\ + )\ + ) + + #define DMA_MK_GBLADDR(gbladdr) ((Uint32)(\ + HFIELD_SHIFT(HDMA_GBLADDR_GBLADDR,gbladdr)\ + )\ + ) +#endif /* DMA_SUPPORT */ + +#if (EDMA_SUPPORT) + #define EDMA_HANDLE EDMA_Handle + #define EDMA_CONFIG EDMA_Config + #define EDMA_Reset EDMA_reset + #define EDMA_Open EDMA_open + #define EDMA_Close EDMA_close + #define EDMA_AllocTable EDMA_allocTable + #define EDMA_FreeTable EDMA_freeTable + #define EDMA_ConfigA EDMA_config + #define EDMA_ConfigB EDMA_configArgs + //#define EDMA_Init EDMA_init + #define EDMA_Init() + #define EDMA_GetScratchAddr EDMA_getScratchAddr + #define EDMA_GetScratchSize EDMA_getScratchSize + #define EDMA_GetPriQStatus EDMA_getPriQStatus + #define EDMA_EnableChannel EDMA_enableChannel + #define EDMA_DisableChannel EDMA_disableChannel + #define EDMA_SetChannel EDMA_setChannel + #define EDMA_GetChannel EDMA_getChannel + #define EDMA_ClearChannel EDMA_clearChannel + #define EDMA_GetTableAddress EDMA_getTableAddress + + #if (0) + #define EDMA_CCER HEDMA_CCER + #define EDMA_CIPR HEDMA_CIPR + #define EDMA_CIER HEDMA_CIER + #endif + + #define EDMA_MK_OPT(fs,link,tcc,tcint,dum,d2d,sum,s2d,esize,pri)\ + ((Uint32)( \ + HFIELD_SHIFT(HEDMA_OPT_FS,fs)| \ + HFIELD_SHIFT(HEDMA_OPT_LINK,link)| \ + HFIELD_SHIFT(HEDMA_OPT_TCC,tcc)| \ + HFIELD_SHIFT(HEDMA_OPT_TCINT,tcint)| \ + HFIELD_SHIFT(HEDMA_OPT_DUM,dum)| \ + HFIELD_SHIFT(HEDMA_OPT_2DD,d2d)| \ + HFIELD_SHIFT(HEDMA_OPT_SUM,sum)| \ + HFIELD_SHIFT(HEDMA_OPT_2DS,s2d)| \ + HFIELD_SHIFT(HEDMA_OPT_ESIZE,esize)| \ + HFIELD_SHIFT(HEDMA_OPT_PRI,pri) \ + ) \ + ) + + #define EDMA_MK_SRC(src) \ + ((Uint32)(\ + HFIELD_SHIFT(HEDMA_SRC_SRC,src)\ + )\ + ) + + #define EDMA_MK_CNT(elecnt,frmcnt)\ + ((Uint32)(\ + HFIELD_SHIFT(HEDMA_CNT_ELECNT,elecnt)|\ + HFIELD_SHIFT(HEDMA_CNT_FRMCNT,frmcnt)\ + )\ + ) + + #define EDMA_MK_DST(dst) \ + ((Uint32)(\ + HFIELD_SHIFT(HEDMA_DST_DST,dst)\ + )\ + ) + + #define EDMA_MK_IDX(eleidx,frmidx)\ + ((Uint32)(\ + HFIELD_SHIFT(HEDMA_IDX_ELEIDX,eleidx)|\ + HFIELD_SHIFT(HEDMA_IDX_FRMIDX,frmidx)\ + )\ + ) + + #define EDMA_MK_RLD(link,elerld)\ + ((Uint32)(\ + HFIELD_SHIFT(HEDMA_RLD_LINK,link)|\ + HFIELD_SHIFT(HEDMA_RLD_ELERLD,elerld)\ + )\ + ) +#endif /* EDMA_SUPPORT */ + + +#if (EMIF_SUPPORT) + /* 3 following functions are declared later on */ + // EMIF_CONFIG + // EMIF_ConfigA + // EMIF_ConfigB + + //#define EMIF_Init EMIF_init + #define EMIF_Init() + + #define EMIF_GBLCTL_RBTR8_NA (0x00000000) + #define EMIF_GBLCTL_SSCRT_NA (0x00000000) + #define EMIF_GBLCTL_CLK2EN_NA (0x00000000) + #define EMIF_GBLCTL_SSCEN_NA (0x00000000) + #define EMIF_GBLCTL_SDCEN_NA (0x00000000) + #define EMIF_CECTL_TA_NA (0x00000000) + #define EMIF_SDCTL_SDWID_NA (0x00000000) + #define EMIF_SDCTL_SDCSZ_NA (0x00000000) + #define EMIF_SDCTL_SDRSZ_NA (0x00000000) + #define EMIF_SDCTL_SDBSZ_NA (0x00000000) + #define EMIF_SDTIM_XRFR_NA (0x00000000) + #define EMIF_SDEXT_NA (0x00000000) + +/* added for reported bug SDSsq22603*/ + #define EMIF_GBLCTL_NOHOLD_0 EMIF_GBLCTL_NOHOLD_DISABLE + #define EMIF_GBLCTL_NOHOLD_1 EMIF_GBLCTL_NOHOLD_ENABLE + + + #define EMIF_CECTL_TA_OF(x) _VALUEOF(x) + #define EMIF_SDEXT_OF(x) _VALUEOF(x) + + #define EMIF_MK_GBLCTL(rbtr8,sscrt,clk2en,clk1en,sscen,sdcen,nohold)\ + ((Uint32)( \ + HFIELD_SHIFT(HEMIF_GBLCTL_RBTR8,rbtr8)|\ + HFIELD_SHIFT(HEMIF_GBLCTL_SSCRT,sscrt)|\ + HFIELD_SHIFT(HEMIF_GBLCTL_CLK2EN,clk2en)|\ + HFIELD_SHIFT(HEMIF_GBLCTL_CLK1EN,clk1en)|\ + HFIELD_SHIFT(HEMIF_GBLCTL_SSCEN,sscen)|\ + HFIELD_SHIFT(HEMIF_GBLCTL_SDCEN,sdcen)|\ + HFIELD_SHIFT(HEMIF_GBLCTL_NOHOLD,nohold)|\ + 0x00003000 \ + )\ + ) + + #define EMIF_MK_CECTL(rdhld,mtype,rdstrb,ta,rdsetup,wrhld,wrstrb,wrsetup)\ + ((Uint32)( \ + HFIELD_SHIFT(HEMIF_CECTL_RDHLD,rdhld)|\ + HFIELD_SHIFT(HEMIF_CECTL_WRHLDMSB,(wrhld>>2))|\ + HFIELD_SHIFT(HEMIF_CECTL_MTYPE,mtype)|\ + HFIELD_SHIFT(HEMIF_CECTL_RDSTRB,rdstrb)|\ + HFIELD_SHIFT(HEMIF_CECTL_TA,ta)|\ + HFIELD_SHIFT(HEMIF_CECTL_RDSETUP,rdsetup)|\ + HFIELD_SHIFT(HEMIF_CECTL_WRHLD,wrhld)|\ + HFIELD_SHIFT(HEMIF_CECTL_WRSTRB,wrstrb)|\ + HFIELD_SHIFT(HEMIF_CECTL_WRSETUP,wrsetup)\ + )\ + ) + + #define EMIF_MK_SDCTL(trc,trp,trcd,init,rfen,sdwid,sdcsz,sdrsz,sdbsz)\ + ((Uint32)( \ + HFIELD_SHIFT(HEMIF_SDCTL_TRC,trc)|\ + HFIELD_SHIFT(HEMIF_SDCTL_TRP,trp)|\ + HFIELD_SHIFT(HEMIF_SDCTL_TRCD,trcd)|\ + HFIELD_SHIFT(HEMIF_SDCTL_INIT,init)|\ + HFIELD_SHIFT(HEMIF_SDCTL_RFEN,rfen)|\ + HFIELD_SHIFT(HEMIF_SDCTL_SDWID,sdwid)|\ + HFIELD_SHIFT(HEMIF_SDCTL_SDCSZ,sdcsz)|\ + HFIELD_SHIFT(HEMIF_SDCTL_SDRSZ,sdrsz)|\ + HFIELD_SHIFT(HEMIF_SDCTL_SDBSZ,sdbsz)\ + )\ + ) + + #define EMIF_MK_SDTIM(period,xrfr)\ + ((Uint32)( \ + HFIELD_SHIFT(HEMIF_SDTIM_PERIOD,period)|\ + HFIELD_SHIFT(HEMIF_SDTIM_XRFR,xrfr)\ + )\ + ) + + #define EMIF_MK_SDEXT(tcl,tras,trrd,twr,thzp,rd2rd,rd2deac,rd2wr,\ + r2wdqm,wr2wr,wr2deac,wr2rd) ((Uint32)( \ + HFIELD_SHIFT(HEMIF_SDEXT_TCL,tcl)|\ + HFIELD_SHIFT(HEMIF_SDEXT_TRAS,tras)|\ + HFIELD_SHIFT(HEMIF_SDEXT_TRRD,trrd)|\ + HFIELD_SHIFT(HEMIF_SDEXT_TWR,twr)|\ + HFIELD_SHIFT(HEMIF_SDEXT_THZP,thzp)|\ + HFIELD_SHIFT(HEMIF_SDEXT_RD2RD,rd2rd)|\ + HFIELD_SHIFT(HEMIF_SDEXT_RD2DEAC,rd2deac)|\ + HFIELD_SHIFT(HEMIF_SDEXT_RD2WR,rd2wr)|\ + HFIELD_SHIFT(HEMIF_SDEXT_R2WDQM,r2wdqm)|\ + HFIELD_SHIFT(HEMIF_SDEXT_WR2WR,wr2wr)|\ + HFIELD_SHIFT(HEMIF_SDEXT_WR2DEAC,wr2deac)|\ + HFIELD_SHIFT(HEMIF_SDEXT_WR2RD,wr2rd)\ + )\ + ) +#endif /* EMIF_SUPPORT */ + + +#if (GPIO_SUPPORT && C64_SUPPORT) + +#define GPIO_config(config) GPIO_config(_hGpioDev0,config); +#define GPIO_configArgs( gpgc, gpen, gpdir, gpval, gphm, gplm, gppol)\ + GPIO_configArgs(_hGpioDev0, gpgc, gpen, gpdir, gpval, gphm, gplm, gppol) +#define GPIO_getConfig(config) GPIO_getConfig(_hGpioDev0,config) + + +#define GPIO_pinEnable(pinId) GPIO_pinEnable(_hGpioDev0,pinId) + +#define GPIO_pinDisable(pinId) GPIO_pinDisable(_hGpioDev0, pinId) +#define GPIO_pinDirection(pinId,direction) GPIO_pinDirection(_hGpioDev0,pinId,direction) + + +#define GPIO_pinRead( pinId) GPIO_pinRead(_hGpioDev0, pinId) +#define GPIO_read( pinMask) GPIO_read(_hGpioDev0, pinMask) + +/* For output Pins */ +#define GPIO_pinWrite( pinId, val) GPIO_pinWrite(_hGpioDev0, pinId, val) +#define GPIO_write( pinMask, val) GPIO_write(_hGpioDev0, pinMask, val) + + +/* For input Pins */ +#define GPIO_deltaHighGet( pinId) GPIO_deltaHighGet(_hGpioDev0, pinId) +#define GPIO_deltaHighClear( pinId) GPIO_deltaHighClear(_hGpioDev0, pinId) +#define GPIO_deltaLowGet( pinId) GPIO_deltaLowGet(_hGpioDev0, pinId) +#define GPIO_deltaLowClear( pinId) GPIO_deltaLowClear(_hGpioDev0, pinId) + +#define GPIO_maskHighSet( pinId) GPIO_maskHighSet(_hGpioDev0, pinId) +#define GPIO_maskHighClear( pinId) GPIO_maskHighClear(_hGpioDev0, pinId) +#define GPIO_maskLowSet( pinId) GPIO_maskLowSet(_hGpioDev0, pinId) +#define GPIO_maskLowClear( pinId) GPIO_maskLowClear(_hGpioDev0, pinId) + +/* Pass Through Mode */ +#define GPIO_intPolarity(signal,polarity) GPIO_intPolarity(_hGpioDev0, signal, polarity) + +#endif + + + +#if (HPI_SUPPORT) + //#define HPI_Init HPI_init + #define HPI_Init() + #define HPI_GetEventId HPI_getEventId + #define HPI_GetHwob HPI_getHwob + #define HPI_GetDspint HPI_getDspint + #define HPI_GetHint HPI_getHint + #define HPI_GetHrdy HPI_getHrdy + #define HPI_GetFetch HPI_getFetch + #define HPI_SetDspint HPI_setDspint + #define HPI_SetHint HPI_setHint +#endif /* HPI_SUPPORT */ + +#if (IRQ_SUPPORT) + #define IntMask intMask + #define IRQ_EVENT IRQ_Event + #define IRQ_EventTable IRQ_eventTable + #define IRQ_IntTable IRQ_intTable + //#define IRQ_Init IRQ_init + #define IRQ_Init() + #define IRQ_Map IRQ_map + #define IRQ_Enable IRQ_enable + #define IRQ_Disable IRQ_disable + #define IRQ_Set IRQ_set + #define IRQ_Clear IRQ_clear + #define IRQ_Test IRQ_test + #define IRQ_DisableGie IRQ_globalDisable + #define IRQ_RestoreGie IRQ_globalRestore +#endif /* IRQ_SUPPORT */ + +#if (MCBSP_SUPPORT) + + #define BaseAddr baseAddr + #define MCBSP_PRIVATE_OBJ MCBSP_PrivateObj + #define MCBSP_HANDLE MCBSP_Handle + #define MCBSP_CONFIG MCBSP_Config + #define MCBSP_HDEV0 _MCBSP_hDev0 + #define MCBSP_HDEV1 _MCBSP_hDev1 + #define MCBSP_HDEV2 _MCBSP_hDev2 + #define MCBSP_Reset MCBSP_reset + #define MCBSP_Open MCBSP_open + #define MCBSP_Close MCBSP_close + #define MCBSP_ConfigA MCBSP_config + #define MCBSP_ConfigB MCBSP_configArgs + #define MCBSP_GetPins MCBSP_getPins + #define MCBSP_SetPins MCBSP_setPins + //#define MCBSP_Init MCBSP_init + #define MCBSP_Init() + #define MCBSP_GetXmtAddr MCBSP_getXmtAddr + #define MCBSP_GetRcvAddr MCBSP_getRcvAddr + #define MCBSP_GetXmtEventId MCBSP_getXmtEventId + #define MCBSP_GetRcvEventId MCBSP_getRcvEventId + #define MCBSP_Read MCBSP_read + #define MCBSP_Write MCBSP_write + #define MCBSP_EnableXmt MCBSP_enableXmt + #define MCBSP_EnableRcv MCBSP_enableRcv + #define MCBSP_EnableFsync MCBSP_enableFsync + #define MCBSP_EnableSrgr MCBSP_enableSrgr + #define MCBSP_Xrdy MCBSP_xrdy + #define MCBSP_Rrdy MCBSP_rrdy + #define MCBSP_Xempty MCBSP_xempty + #define MCBSP_Rfull MCBSP_rfull + #define MCBSP_XsyncErr MCBSP_xsyncerr + #define MCBSP_RsyncErr MCBSP_rsyncerr + + #define MCBSP_SPCR_DXENA_NA (0x00000000) + #define MCBSP_RCR_RWDREVRS_NA (0x00000000) + #define MCBSP_RCR_RPHASE2_NA (0x00000000) + #define MCBSP_RCR_RPHASE2_NORMAL (0x00000000) + #define MCBSP_RCR_RPHASE2_OPPOSITE (0x00000000) + #define MCBSP_XCR_XWDREVRS_NA (0x00000000) + #define MCBSP_XCR_XPHASE2_NA (0x00000000) + #define MCBSP_XCR_XPHASE2_NORMAL (0x00000000) + #define MCBSP_XCR_XPHASE2_OPPOSITE (0x00000000) + + #define MCBSP_DRR_OFFSET 0 + #define MCBSP_DXR_OFFSET 1 + #define MCBSP_SPCR_OFFSET 2 + #define MCBSP_RCR_OFFSET 3 + #define MCBSP_XCR_OFFSET 4 + #define MCBSP_SRGR_OFFSET 5 + #define MCBSP_MCR_OFFSET 6 + #define MCBSP_RCER_OFFSET 7 + #define MCBSP_XCER_OFFSET 8 + #define MCBSP_PCR_OFFSET 9 + + #define MCBSP_ALLOCATED(hMcbsp) ((hMcbsp)->Allocated) + #define MCBSP_XMTEVENTID(hMcbsp) ((hMcbsp)->XmtEventId) + #define MCBSP_RCVEVENTID(hMcbsp) ((hMcbsp)->RcvEventId) + #define MCBSP_DRR(hMcbsp) (((hMcbsp)->BaseAddr)[MCBSP_DRR_OFFSET]) + #define MCBSP_DXR(hMcbsp) (((hMcbsp)->BaseAddr)[MCBSP_DXR_OFFSET]) + #define MCBSP_SPCR(hMcbsp) (((hMcbsp)->BaseAddr)[MCBSP_SPCR_OFFSET]) + #define MCBSP_RCR(hMcbsp) (((hMcbsp)->BaseAddr)[MCBSP_RCR_OFFSET]) + #define MCBSP_XCR(hMcbsp) (((hMcbsp)->BaseAddr)[MCBSP_XCR_OFFSET]) + #define MCBSP_SRGR(hMcbsp) (((hMcbsp)->BaseAddr)[MCBSP_SRGR_OFFSET]) + #define MCBSP_MCR(hMcbsp) (((hMcbsp)->BaseAddr)[MCBSP_MCR_OFFSET]) + #define MCBSP_RCER(hMcbsp) (((hMcbsp)->BaseAddr)[MCBSP_RCER_OFFSET]) + #define MCBSP_XCER(hMcbsp) (((hMcbsp)->BaseAddr)[MCBSP_XCER_OFFSET]) + #define MCBSP_PCR(hMcbsp) (((hMcbsp)->BaseAddr)[MCBSP_PCR_OFFSET]) + + + #define MCBSP_MK_SPCR(rrst,rintm,dxena,clkstp,rjust,dlb,xrst,xintm,grst,\ + frst) ((Uint32)( \ + HFIELD_SHIFT(HMCBSP_SPCR_RRST,rrst)| \ + HFIELD_SHIFT(HMCBSP_SPCR_RINTM,rintm)| \ + HFIELD_SHIFT(HMCBSP_SPCR_DXENA,dxena)| \ + HFIELD_SHIFT(HMCBSP_SPCR_CLKSTP,clkstp)| \ + HFIELD_SHIFT(HMCBSP_SPCR_RJUST,rjust)| \ + HFIELD_SHIFT(HMCBSP_SPCR_DLB,dlb)| \ + HFIELD_SHIFT(HMCBSP_SPCR_XRST,xrst)| \ + HFIELD_SHIFT(HMCBSP_SPCR_XINTM,xintm)| \ + HFIELD_SHIFT(HMCBSP_SPCR_GRST,grst)| \ + HFIELD_SHIFT(HMCBSP_SPCR_FRST,frst) \ + ) \ + ) + + +/******** redefined for CSL 1.2 / 1.23 ************/ + #define _MCBSP_RCR_RPHASE2_MASK 0x00008000u + #define _MCBSP_RCR_RPHASE2_SHIFT 0x0000000Fu + #define MCBSP_RCR_RPHASE2_DEFAULT 0x00000000u + #define MCBSP_RCR_RPHASE2_OF(x) _VALUEOF(x) + + #define _MCBSP_XCR_XPHASE2_MASK 0x00008000u + #define _MCBSP_XCR_XPHASE2_SHIFT 0x0000000Fu + #define MCBSP_XCR_XPHASE2_DEFAULT 0x00000000u + #define MCBSP_XCR_XPHASE2_OF(x) _VALUEOF(x) + + + + #define MCBSP_MK_RCR(rwdrevrs,rwdlen1,rfrlen1,rphase2,rdatdly,rfig,\ + rcompand,rwdlen2,rfrlen2,rphase) ((Uint32)(\ + HFIELD_SHIFT(HMCBSP_RCR_RWDREVRS,rwdrevrs)|\ + HFIELD_SHIFT(HMCBSP_RCR_RWDLEN1,rwdlen1)|\ + HFIELD_SHIFT(HMCBSP_RCR_RFRLEN1,rfrlen1)|\ + HFIELD_SHIFT(HMCBSP_RCR_RPHASE2,rphase2)|\ + HFIELD_SHIFT(HMCBSP_RCR_RDATDLY,rdatdly)|\ + HFIELD_SHIFT(HMCBSP_RCR_RFIG,rfig)|\ + HFIELD_SHIFT(HMCBSP_RCR_RCOMPAND,rcompand)|\ + HFIELD_SHIFT(HMCBSP_RCR_RWDLEN2,rwdlen2)|\ + HFIELD_SHIFT(HMCBSP_RCR_RFRLEN2,rfrlen2)|\ + HFIELD_SHIFT(HMCBSP_RCR_RPHASE,rphase)\ + ) \ + ) + + #define MCBSP_MK_XCR(xwdrevrs,xwdlen1,xfrlen1,xphase2,xdatdly,xfig,\ + xcompand,xwdlen2,xfrlen2,xphase) ((Uint32)(\ + HFIELD_SHIFT(HMCBSP_XCR_XWDREVRS,xwdrevrs)|\ + HFIELD_SHIFT(HMCBSP_XCR_XWDLEN1,xwdlen1)|\ + HFIELD_SHIFT(HMCBSP_XCR_XFRLEN1,xfrlen1)|\ + HFIELD_SHIFT(HMCBSP_XCR_XPHASE2,xphase2)|\ + HFIELD_SHIFT(HMCBSP_XCR_XDATDLY,xdatdly)|\ + HFIELD_SHIFT(HMCBSP_XCR_XFIG,xfig)|\ + HFIELD_SHIFT(HMCBSP_XCR_XCOMPAND,xcompand)|\ + HFIELD_SHIFT(HMCBSP_XCR_XWDLEN2,xwdlen2)|\ + HFIELD_SHIFT(HMCBSP_XCR_XFRLEN2,xfrlen2)|\ + HFIELD_SHIFT(HMCBSP_XCR_XPHASE,xphase)\ + ) \ + ) + + /* make SRGR register value based on symbolic constants */ + #define MCBSP_MK_SRGR(clkgdv,fwid,fper,fsgm,clksm,clksp,gsync) (\ + (Uint32)(\ + HFIELD_SHIFT(HMCBSP_SRGR_CLKGDV,clkgdv)|\ + HFIELD_SHIFT(HMCBSP_SRGR_FWID,fwid)|\ + HFIELD_SHIFT(HMCBSP_SRGR_FPER,fper)|\ + HFIELD_SHIFT(HMCBSP_SRGR_FSGM,fsgm)|\ + HFIELD_SHIFT(HMCBSP_SRGR_CLKSM,clksm)|\ + HFIELD_SHIFT(HMCBSP_SRGR_CLKSP,clksp)|\ + HFIELD_SHIFT(HMCBSP_SRGR_GSYNC,gsync)\ + )\ + ) + + #define MCBSP_MK_MCR(rmcm,rpablk,rpbblk,xmcm,xpablk,xpbblk)\ + ((Uint32)(\ + HFIELD_SHIFT(HMCBSP_MCR_RMCM,rmcm)|\ + HFIELD_SHIFT(HMCBSP_MCR_RPABLK,rpablk)|\ + HFIELD_SHIFT(HMCBSP_MCR_RPBBLK,rpbblk)|\ + HFIELD_SHIFT(HMCBSP_MCR_XMCM,xmcm)|\ + HFIELD_SHIFT(HMCBSP_MCR_XPABLK,xpablk)|\ + HFIELD_SHIFT(HMCBSP_MCR_XPBBLK,xpbblk)\ + )\ + ) + + #define MCBSP_MK_RCER(rcea,rceb) (\ + (Uint32)(\ + (((Uint32)(rcea))&0x0000FFFF)|\ + ((((Uint32)(rceb))<<16)&0xFFFF0000)\ + )\ + ) + + #define MCBSP_MK_XCER(xcea,xceb) (\ + (Uint32)(\ + (((Uint32)(xcea))&0x0000FFFF)|\ + ((((Uint32)(xceb))<<16)&0xFFFF0000)\ + )\ + ) + + #define MCBSP_MK_PCR(clkrp,clkxp,fsrp,fsxp,dxstat,clksstat,clkrm,clkxm,\ + fsrm,fsxm,rioen,xioen) ((Uint32)(\ + HFIELD_SHIFT(HMCBSP_PCR_CLKRP,clkrp)|\ + HFIELD_SHIFT(HMCBSP_PCR_CLKXP,clkxp)|\ + HFIELD_SHIFT(HMCBSP_PCR_FSRP,fsrp)|\ + HFIELD_SHIFT(HMCBSP_PCR_FSXP,fsxp)|\ + HFIELD_SHIFT(HMCBSP_PCR_DXSTAT,dxstat)|\ + HFIELD_SHIFT(HMCBSP_PCR_CLKSSTAT,clksstat)|\ + HFIELD_SHIFT(HMCBSP_PCR_CLKRM,clkrm)|\ + HFIELD_SHIFT(HMCBSP_PCR_CLKXM,clkxm)|\ + HFIELD_SHIFT(HMCBSP_PCR_FSRM,fsrm)|\ + HFIELD_SHIFT(HMCBSP_PCR_FSXM,fsxm)|\ + HFIELD_SHIFT(HMCBSP_PCR_RIOEN,rioen)|\ + HFIELD_SHIFT(HMCBSP_PCR_XIOEN,xioen)\ + )\ + ) +#endif /* MCBSP_SUPPORT */ + +#if (PWR_SUPPORT) + #define PWR_MODE PWR_Mode + //#define PWR_Init PWR_init + #define PWR_Init() + #define PWR_PowerDown PWR_powerDown + #define PWR_ConfigB PWR_configArgs + + #define PWR_MK_PDCTL(dma,emif,mcbsp0,mcbsp1,mcbsp2) ((Uint32)( \ + HFIELD_SHIFT(HPWR_PDCTL_DMA,dma)|\ + HFIELD_SHIFT(HPWR_PDCTL_EMIF,emif)|\ + HFIELD_SHIFT(HPWR_PDCTL_MCBSP0,mcbsp0)|\ + HFIELD_SHIFT(HPWR_PDCTL_MCBSP1,mcbsp1)|\ + HFIELD_SHIFT(HPWR_PDCTL_MCBSP2,mcbsp2)\ + )\ + ) +#endif /* PWR_SUPPORT */ + + +#if (1) + #define UINT8 Uint8 + #define UINT16 Uint16 + #define UINT32 Uint32 + #define UINT40 Uint40 + #define INT8 Int8 + #define INT16 Int16 + #define INT32 Int32 + #define INT40 Int40 + #define BOOL int + #define HANDLE Handle +#endif + +#if (TIMER_SUPPORT) + #define TIMER_PRIVATE_OBJ TIMER_PrivateObj + #define TIMER_HANDLE TIMER_Handle + #define TIMER_CONFIG TIMER_Config + #define TIMER_HDEV0 _TIMER_hDev0 + #define TIMER_HDEV1 _TIMER_hDev1 + #define TIMER_Reset TIMER_reset + #define TIMER_Open TIMER_open + #define TIMER_Close TIMER_close + #define TIMER_ConfigA TIMER_config + #define TIMER_ConfigB TIMER_configArgs + //#define TIMER_Init TIMER_init + #define TIMER_Init() + #define TIMER_GetEventId TIMER_getEventId + #define TIMER_Start TIMER_start + #define TIMER_Pause TIMER_pause + #define TIMER_Resume TIMER_resume + #define TIMER_GetPeriod TIMER_getPeriod + #define TIMER_SetPeriod TIMER_setPeriod + #define TIMER_GetCount TIMER_getCount + #define TIMER_SetCount TIMER_setCount + #define TIMER_GetDatin TIMER_getDatIn + #define TIMER_SetDatout TIMER_setDatOut + #define TIMER_GetTstat TIMER_getTStat + + /* make CTL register value based on symbolic constants */ + #define TIMER_MK_CTL(func,invout,datout,pwid,go,hld,cp,clksrc,invinp)\ + ((Uint32)( \ + HFIELD_SHIFT(HTIMER_CTL_FUNC,func)|\ + HFIELD_SHIFT(HTIMER_CTL_INVOUT,invout)|\ + HFIELD_SHIFT(HTIMER_CTL_DATOUT,datout)|\ + HFIELD_SHIFT(HTIMER_CTL_PWID,pwid)|\ + HFIELD_SHIFT(HTIMER_CTL_GO,go)|\ + HFIELD_SHIFT(HTIMER_CTL_HLD,hld)|\ + HFIELD_SHIFT(HTIMER_CTL_CP,cp)|\ + HFIELD_SHIFT(HTIMER_CTL_CLKSRC,clksrc)|\ + HFIELD_SHIFT(HTIMER_CTL_INVINP,invinp)\ + ) \ + ) +#endif /* TIMER_SUPPORT */ + + +/******************************************************************************\ +* global typedef declarations +\******************************************************************************/ + +#if (DMA_SUPPORT&&0) + typedef enum { + DMA_GBL_ADDRRLD = 0x00, + DMA_GBL_INDEX = 0x04, + DMA_GBL_CNTRLD = 0x08, + DMA_GBL_SPLIT = 0x0C + } DMA_Gbl; +#endif /* DMA_SUPPORT */ + +#if (EMIF_SUPPORT) +/* device configuration structure */ +typedef struct { + UINT32 gblctl; + UINT32 ce0ctl; + UINT32 ce1ctl; + UINT32 ce2ctl; + UINT32 ce3ctl; + UINT32 sdctl; + UINT32 sdtim; + UINT32 sdext; +} EMIF_CONFIG; +#endif /* EMIF_SUPPORT */ + + +/******************************************************************************\ +* global variable declarations +\******************************************************************************/ +#if (DMA_SUPPORT&&0) + extern far Uint32 _DMA_gblRegTbl[_DMA_GBLREG_CNT]; +#endif /* DMA_SUPPORT */ + + +/******************************************************************************\ +* global function declarations +\******************************************************************************/ +#if (DMA_SUPPORT&&0) + CSLAPI Uint32 DMA_allocGlobalReg(DMA_Gbl regType, Uint32 initVal); + CSLAPI void DMA_freeGlobalReg(Uint32 regId); +#endif /* DMA_SUPPORT */ + +#if (EMIF_SUPPORT) + CSLAPI void EMIF_ConfigA(EMIF_CONFIG *Config); + CSLAPI void EMIF_ConfigB(UINT32 gblctl, UINT32 ce0ctl, UINT32 ce1ctl, + UINT32 ce2ctl, UINT32 ce3ctl, UINT32 sdctl, UINT32 sdtim, UINT32 sdext); +#endif + +/******************************************************************************\ +* inline function declarations +\******************************************************************************/ +#if (DMA_SUPPORT&&0) + IDECL Uint32 DMA_getGlobalRegAddr(Uint32 regId); + IDECL Uint32 DMA_getGlobalReg(Uint32 regId); + IDECL void DMA_setGlobalReg(Uint32 regId, Uint32 val); +#endif /* DMA_SUPPORT */ + + +/******************************************************************************\ +* inline function definitions +\******************************************************************************/ +#ifdef USEDEFS +#if (DMA_SUPPORT&&0) +/*----------------------------------------------------------------------------*/ +IDEF Uint32 DMA_getGlobalRegAddr(Uint32 regId) { + return _DMA_gblRegTbl[regId&_DMA_GBLREG_MASK]; +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 DMA_getGlobalReg(Uint32 regId) { + return REG32(_DMA_gblRegTbl[regId&_DMA_GBLREG_MASK]); +} +/*----------------------------------------------------------------------------*/ +IDEF void DMA_setGlobalReg(Uint32 regId, Uint32 val) { + REG32(_DMA_gblRegTbl[regId&_DMA_GBLREG_MASK])=val; +} +/*----------------------------------------------------------------------------*/ +#endif /* DMA_SUPPORT */ +/*----------------------------------------------------------------------------*/ +#endif /* USEDEFS */ + + +#endif /* _CSL_LEGACY_H_ */ +/******************************************************************************\ +* End of csl_legacy.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_legacyhal.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_legacyhal.h new file mode 100644 index 0000000..3a67b1a --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_legacyhal.h @@ -0,0 +1,9689 @@ +/* + * Copyright 2001 by Texas Instruments Incorporated. + * All rights reserved. Property of Texas Instruments Incorporated. + * Restricted rights to use, duplicate or disclose this code are + * granted through contract. + * + */ +/* "@(#) DSP/BIOS 4.60.22 12-07-01 (barracuda-j15)" */ +/******************************************************************************\ +* Copyright (C) 2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_legacyhal.h +* DATE CREATED.. 09/01/2000 +* LAST MODIFIED. 03/08/2002 +\******************************************************************************/ +#ifndef _CSL_LEGACYHAL_H_ +#define _CSL_LEGACYHAL_H_ + +#include "csl_stdinc.h" +#include "csl_chiphal.h" + +/*----------------------------------------------------------------------------*/ +/* Legacy HAL support macro definitions */ +/*----------------------------------------------------------------------------*/ + #define _VALUEOF(x) ((Uint32)(x)) + +#ifndef UNREFERENCED_PARAMETER + #define UNREFERENCED_PARAMETER(P) ((P)=(P)) +#endif + +#ifndef REG32 + #define REG32(addr) (*(volatile unsigned int*)(addr)) + #define REG16(addr) (*(volatile unsigned short*)(addr)) + #define REG8(addr) (*(volatile unsigned char*)(addr)) +#endif + +/* memory mapped register macros */ +#define HFIELD_GET(RegAddr,FIELD) (Uint32)( \ + (REG32(RegAddr)&##FIELD##_MASK)>>##FIELD##_SHIFT \ +) + +#define HFIELD_SET(RegAddr,FIELD,Val) REG32(RegAddr)=(Uint32)( \ + (REG32(RegAddr)&~##FIELD##_MASK)| \ + (((Uint32)(Val)<<##FIELD##_SHIFT)&##FIELD##_MASK) \ +) + +#define HFIELD_SHIFT(FIELD,Val) \ + (((Uint32)(Val)<<##FIELD##_SHIFT)&##FIELD##_MASK) + +#define HREG32_GET(RegAddr) \ + (Uint32)REG32(RegAddr) + +#define HREG32_SET(RegAddr,Val) \ + REG32(RegAddr)=(Uint32)(Val) + +/* control register macros */ +#define HCRFIELD_GET(CRREG,FIELD) (Uint32)( \ + (((CRREG)&##FIELD##_MASK)>>##FIELD##_SHIFT) \ +) + + + +#define HCRFIELD_SET(CRREG,FIELD,Val) CRREG = (Uint32)( \ + ((CRREG)&~##FIELD##_MASK)| \ + (((Uint32)(Val)<<##FIELD##_SHIFT)&##FIELD##_MASK) \ +) + +#define HCRFIELD_SHIFT(FIELD,Val) \ + (((Uint32)(Val)<<##FIELD##_SHIFT)&##FIELD##_MASK) + +#define HCRREG32_GET(CRREG) \ + (Uint32)(CRREG) + +#define HCRREG32_SET(CRREG,Val) \ + (CRREG)=(Uint32)(Val) + + +/******************************************************************************\ +* Copyright (C) 1999-2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... chiphal.h +* DATE CREATED.. 08/19/1999 +* LAST MODIFIED. 03/08/2000 +* +*------------------------------------------------------------------------------ +* DESCRIPTION: (HAL interface file for the CHIP module) +* +* CHIP Control Registers Covered +* HCHIP_CSR - control status register +* HCHIP_IFR - interrupt flag register +* HCHIP_ISR - interrupt set register +* HCHIP_ICR - interrupt clear register +* HCHIP_IER - interrupt enable register +* HCHIP_ISTP - interrupt service table pointer +* HCHIP_IRP - interrrupt return pointer +* HCHIP_NRP - nonmaskable interrupt return pointer +* HCHIP_AMR - addressing mode register +* HCHIP_FADCR - floating-point adder config register (1) +* HCHIP_FAUCR - floating-point auxiliary config register (1) +* HCHIP_FMCR - floating-point multiplier config register (1) +* +* (1) only on devices with an FPU +* +\******************************************************************************/ +#ifndef _CHIPHAL_H_ +#define _CHIPHAL_H_ + +/*----------------------------------------------------------------*/ + +#define HCHIP_PERBASE_ADDR (0x01800000) + +/******************************************************************************\ +* HCHIP_NULL - dummy register +* +\******************************************************************************/ + #define HCHIP_NULL_ADDR ((UINT32)(0x01840074)) + #define HCHIP_NULL REG32(HCHIP_NULL_ADDR) + +/******************************************************************************\ +* HCHIP_CSR - control status register +* +* Fields: +* (RW) HCHIP_CSR_GIE +* (RW) HCHIP_CSR_PGIE +* (RW) HCHIP_CSR_DCC +* (RW) HCHIP_CSR_PCC +* (R) HCHIP_CSR_EN +* (RC) HCHIP_CSR_SAT +* (RW) HCHIP_CSR_PWRD +* (R) HCHIP_CSR_REVID +* (R) HCHIP_CSR_CPUID +* +\******************************************************************************/ + extern far cregister volatile unsigned int CSR; + #define HCHIP_CSR CSR + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_CSR_GIE +\*----------------------------------------------------------------------------*/ + #define HCHIP_CSR_GIE_MASK (0x00000001) + #define HCHIP_CSR_GIE_SHIFT (0x00000000) + + #define HCHIP_CSR_GIE_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_CSR_GIE) + + #define HCHIP_CSR_GIE_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_CSR_GIE,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_CSR_PGIE +\*----------------------------------------------------------------------------*/ + #define HCHIP_CSR_PGIE_MASK (0x00000002) + #define HCHIP_CSR_PGIE_SHIFT (0x00000001) + + #define HCHIP_CSR_PGIE_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_CSR_PGIE) + + #define HCHIP_CSR_PGIE_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_CSR_PGIE,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_CSR_DCC +\*----------------------------------------------------------------------------*/ + #define HCHIP_CSR_DCC_MASK (0x0000001C) + #define HCHIP_CSR_DCC_SHIFT (0x00000002) + + #define HCHIP_CSR_DCC_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_CSR_DCC) + + #define HCHIP_CSR_DCC_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_CSR_DCC,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_CSR_PCC +\*----------------------------------------------------------------------------*/ + #define HCHIP_CSR_PCC_MASK (0x000000E0) + #define HCHIP_CSR_PCC_SHIFT (0x00000005) + + #define HCHIP_CSR_PCC_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_CSR_PCC) + + #define HCHIP_CSR_PCC_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_CSR_PCC,Val) + +/*----------------------------------------------------------------------------*\ +* (R) HCHIP_CSR_EN +\*----------------------------------------------------------------------------*/ + #define HCHIP_CSR_EN_MASK (0x00000100) + #define HCHIP_CSR_EN_SHIFT (0x00000008) + + #define HCHIP_CSR_EN_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_CSR_EN) + +/*----------------------------------------------------------------------------*\ +* (RC) HCHIP_CSR_SAT +\*----------------------------------------------------------------------------*/ + #define HCHIP_CSR_SAT_MASK (0x00000200) + #define HCHIP_CSR_SAT_SHIFT (0x00000009) + + #define HCHIP_CSR_SAT_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_CSR_SAT) + + #define HCHIP_CSR_SAT_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_CSR_SAT,Val) + +/*----------------------------------------------------------------------------*\ +* (W) HCHIP_CSR_PWRD +\*----------------------------------------------------------------------------*/ + #define HCHIP_CSR_PWRD_MASK (0x0000FC00) + #define HCHIP_CSR_PWRD_SHIFT (0x0000000A) + + #define HCHIP_CSR_PWRD_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_CSR_PWRD,Val) + +/*----------------------------------------------------------------------------*\ +* (R) HCHIP_CSR_REVID +\*----------------------------------------------------------------------------*/ + #define HCHIP_CSR_REVID_MASK (0x00FF0000) + #define HCHIP_CSR_REVID_SHIFT (0x00000010) + + #define HCHIP_CSR_REVID_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_CSR_REVID) + +/*----------------------------------------------------------------------------*\ +* (R) HCHIP_CSR_CPUID +\*----------------------------------------------------------------------------*/ + #define HCHIP_CSR_CPUID_MASK (0xFF000000) + #define HCHIP_CSR_CPUID_SHIFT (0x00000018) + + #define HCHIP_CSR_CPUID_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_CSR_CPUID) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_CSR +\*----------------------------------------------------------------------------*/ + #define HCHIP_CSR_GET(CrReg) HCRREG32_GET(CrReg) + + #define HCHIP_CSR_SET(CrReg,Val) HCRREG32_SET(CrReg,Val) + + #define HCHIP_CSR_CFG(CrReg,gie,pgie,dcc,pcc,pwrd) CrReg=(UINT32)( \ + HCRFIELD_SHIFT(HCHIP_CSR_GIE, gie) |\ + HCRFIELD_SHIFT(HCHIP_CSR_PGIE,pgie)|\ + HCRFIELD_SHIFT(HCHIP_CSR_DCC, dcc) |\ + HCRFIELD_SHIFT(HCHIP_CSR_PCC, pcc) |\ + HCRFIELD_SHIFT(HCHIP_CSR_PWRD,pwrd) \ + ) + +/******************************************************************************\ +* HCHIP_IFR - interrupt flag register +* +* Fields: +* (R) HCHIP_IFR_NMIF +* (R) HCHIP_IFR_IF4 +* (R) HCHIP_IFR_IF5 +* (R) HCHIP_IFR_IF6 +* (R) HCHIP_IFR_IF7 +* (R) HCHIP_IFR_IF8 +* (R) HCHIP_IFR_IF9 +* (R) HCHIP_IFR_IF10 +* (R) HCHIP_IFR_IF11 +* (R) HCHIP_IFR_IF12 +* (R) HCHIP_IFR_IF13 +* (R) HCHIP_IFR_IF14 +* (R) HCHIP_IFR_IF15 +* +\******************************************************************************/ + extern far cregister volatile unsigned int IFR; + #define HCHIP_IFR IFR + +/*----------------------------------------------------------------------------*\ +* (R) HCHIP_IFR_NMIF +\*----------------------------------------------------------------------------*/ + #define HCHIP_IFR_NMIF_MASK (0x00000002) + #define HCHIP_IFR_NMIF_SHIFT (0x00000001) + + #define HCHIP_IFR_NMIF_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_IFR_NMIF) + +/*----------------------------------------------------------------------------*\ +* (R) HCHIP_IFR_IF4 +\*----------------------------------------------------------------------------*/ + #define HCHIP_IFR_IF4_MASK (0x00000010) + #define HCHIP_IFR_IF4_SHIFT (0x00000004) + + #define HCHIP_IFR_IF4_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_IFR_IF4) + +/*----------------------------------------------------------------------------*\ +* (R) HCHIP_IFR_IF5 +\*----------------------------------------------------------------------------*/ + #define HCHIP_IFR_IF5_MASK (0x00000020) + #define HCHIP_IFR_IF5_SHIFT (0x00000005) + + #define HCHIP_IFR_IF5_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_IFR_IF5) + +/*----------------------------------------------------------------------------*\ +* (R) HCHIP_IFR_IF6 +\*----------------------------------------------------------------------------*/ + #define HCHIP_IFR_IF6_MASK (0x00000040) + #define HCHIP_IFR_IF6_SHIFT (0x00000006) + + #define HCHIP_IFR_IF6_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_IFR_IF6) + +/*----------------------------------------------------------------------------*\ +* (R) HCHIP_IFR_IF7 +\*----------------------------------------------------------------------------*/ + #define HCHIP_IFR_IF7_MASK (0x00000080) + #define HCHIP_IFR_IF7_SHIFT (0x00000007) + + #define HCHIP_IFR_IF7_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_IFR_IF7) + +/*----------------------------------------------------------------------------*\ +* (R) HCHIP_IFR_IF8 +\*----------------------------------------------------------------------------*/ + #define HCHIP_IFR_IF8_MASK (0x00000100) + #define HCHIP_IFR_IF8_SHIFT (0x00000008) + + #define HCHIP_IFR_IF8_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_IFR_IF8) + +/*----------------------------------------------------------------------------*\ +* (R) HCHIP_IFR_IF9 +\*----------------------------------------------------------------------------*/ + #define HCHIP_IFR_IF9_MASK (0x00000200) + #define HCHIP_IFR_IF9_SHIFT (0x00000009) + + #define HCHIP_IFR_IF9_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_IFR_IF9) + +/*----------------------------------------------------------------------------*\ +* (R) HCHIP_IFR_IF10 +\*----------------------------------------------------------------------------*/ + #define HCHIP_IFR_IF10_MASK (0x00000400) + #define HCHIP_IFR_IF10_SHIFT (0x0000000A) + + #define HCHIP_IFR_IF10_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_IFR_IF10) + +/*----------------------------------------------------------------------------*\ +* (R) HCHIP_IFR_IF11 +\*----------------------------------------------------------------------------*/ + #define HCHIP_IFR_IF11_MASK (0x00000800) + #define HCHIP_IFR_IF11_SHIFT (0x0000000B) + + #define HCHIP_IFR_IF11_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_IFR_IF11) + +/*----------------------------------------------------------------------------*\ +* (R) HCHIP_IFR_IF12 +\*----------------------------------------------------------------------------*/ + #define HCHIP_IFR_IF12_MASK (0x00001000) + #define HCHIP_IFR_IF12_SHIFT (0x0000000C) + + #define HCHIP_IFR_IF12_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_IFR_IF12) + +/*----------------------------------------------------------------------------*\ +* (R) HCHIP_IFR_IF13 +\*----------------------------------------------------------------------------*/ + #define HCHIP_IFR_IF13_MASK (0x00002000) + #define HCHIP_IFR_IF13_SHIFT (0x0000000D) + + #define HCHIP_IFR_IF13_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_IFR_IF13) + +/*----------------------------------------------------------------------------*\ +* (R) HCHIP_IFR_IF14 +\*----------------------------------------------------------------------------*/ + #define HCHIP_IFR_IF14_MASK (0x00004000) + #define HCHIP_IFR_IF14_SHIFT (0x0000000E) + + #define HCHIP_IFR_IF14_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_IFR_IF14) + +/*----------------------------------------------------------------------------*\ +* (R) HCHIP_IFR_IF15 +\*----------------------------------------------------------------------------*/ + #define HCHIP_IFR_IF15_MASK (0x00008000) + #define HCHIP_IFR_IF15_SHIFT (0x0000000F) + + #define HCHIP_IFR_IF15_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_IFR_IF15) + +/*----------------------------------------------------------------------------*\ +* (R) HCHIP_IFR +\*----------------------------------------------------------------------------*/ + #define HCHIP_IFR_GET(CrReg) HCRREG32_GET(CrReg) + +/******************************************************************************\ +* HCHIP_ISR - interrupt set register +* +* Fields: +* (W) HCHIP_ISR_IS4 +* (W) HCHIP_ISR_IS5 +* (W) HCHIP_ISR_IS6 +* (W) HCHIP_ISR_IS7 +* (W) HCHIP_ISR_IS8 +* (W) HCHIP_ISR_IS9 +* (W) HCHIP_ISR_IS10 +* (W) HCHIP_ISR_IS11 +* (W) HCHIP_ISR_IS12 +* (W) HCHIP_ISR_IS13 +* (W) HCHIP_ISR_IS14 +* (W) HCHIP_ISR_IS15 +* +\******************************************************************************/ + extern far cregister volatile unsigned int ISR; + #define HCHIP_ISR ISR + +/*----------------------------------------------------------------------------*\ +* (W) HCHIP_ISR_IS4 +\*----------------------------------------------------------------------------*/ + #define HCHIP_ISR_IS4_MASK (0x00000010) + #define HCHIP_ISR_IS4_SHIFT (0x00000004) + + #define HCHIP_ISR_IS4_SET(CrReg,Val) \ + HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ISR_IS4,Val)) + +/*----------------------------------------------------------------------------*\ +* (W) HCHIP_ISR_IS5 +\*----------------------------------------------------------------------------*/ + #define HCHIP_ISR_IS5_MASK (0x00000020) + #define HCHIP_ISR_IS5_SHIFT (0x00000005) + + #define HCHIP_ISR_IS5_SET(CrReg,Val) \ + HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ISR_IS5,Val)) + +/*----------------------------------------------------------------------------*\ +* (W) HCHIP_ISR_IS6 +\*----------------------------------------------------------------------------*/ + #define HCHIP_ISR_IS6_MASK (0x00000040) + #define HCHIP_ISR_IS6_SHIFT (0x00000006) + + #define HCHIP_ISR_IS6_SET(CrReg,Val) \ + HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ISR_IS6,Val)) + +/*----------------------------------------------------------------------------*\ +* (W) HCHIP_ISR_IS7 +\*----------------------------------------------------------------------------*/ + #define HCHIP_ISR_IS7_MASK (0x00000080) + #define HCHIP_ISR_IS7_SHIFT (0x00000007) + + #define HCHIP_ISR_IS7_SET(CrReg,Val) \ + HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ISR_IS7,Val)) + +/*----------------------------------------------------------------------------*\ +* (W) HCHIP_ISR_IS8 +\*----------------------------------------------------------------------------*/ + #define HCHIP_ISR_IS8_MASK (0x00000100) + #define HCHIP_ISR_IS8_SHIFT (0x00000008) + + #define HCHIP_ISR_IS8_SET(CrReg,Val) \ + HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ISR_IS8,Val)) + +/*----------------------------------------------------------------------------*\ +* (W) HCHIP_ISR_IS9 +\*----------------------------------------------------------------------------*/ + #define HCHIP_ISR_IS9_MASK (0x00000200) + #define HCHIP_ISR_IS9_SHIFT (0x00000009) + + #define HCHIP_ISR_IS9_SET(CrReg,Val) \ + HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ISR_IS9,Val)) + +/*----------------------------------------------------------------------------*\ +* (W) HCHIP_ISR_IS10 +\*----------------------------------------------------------------------------*/ + #define HCHIP_ISR_IS10_MASK (0x00000400) + #define HCHIP_ISR_IS10_SHIFT (0x0000000A) + + #define HCHIP_ISR_IS10_SET(CrReg,Val) \ + HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ISR_IS10,Val)) + +/*----------------------------------------------------------------------------*\ +* (W) HCHIP_ISR_IS11 +\*----------------------------------------------------------------------------*/ + #define HCHIP_ISR_IS11_MASK (0x00000800) + #define HCHIP_ISR_IS11_SHIFT (0x0000000B) + + #define HCHIP_ISR_IS11_SET(CrReg,Val) \ + HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ISR_IS11,Val)) +/*----------------------------------------------------------------------------*\ +* (W) HCHIP_ISR_IS12 +\*----------------------------------------------------------------------------*/ + #define HCHIP_ISR_IS12_MASK (0x00001000) + #define HCHIP_ISR_IS12_SHIFT (0x0000000C) + + #define HCHIP_ISR_IS12_SET(CrReg,Val) \ + HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ISR_IS12,Val)) + +/*----------------------------------------------------------------------------*\ +* (W) HCHIP_ISR_IS13 +\*----------------------------------------------------------------------------*/ + #define HCHIP_ISR_IS13_MASK (0x00002000) + #define HCHIP_ISR_IS13_SHIFT (0x0000000D) + + #define HCHIP_ISR_IS13_SET(CrReg,Val) \ + HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ISR_IS13,Val)) + +/*----------------------------------------------------------------------------*\ +* (W) HCHIP_ISR_IS14 +\*----------------------------------------------------------------------------*/ + #define HCHIP_ISR_IS14_MASK (0x00004000) + #define HCHIP_ISR_IS14_SHIFT (0x0000000E) + + #define HCHIP_ISR_IS14_SET(CrReg,Val) \ + HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ISR_IS14,Val)) + +/*----------------------------------------------------------------------------*\ +* (W) HCHIP_ISR_IS15 +\*----------------------------------------------------------------------------*/ + #define HCHIP_ISR_IS15_MASK (0x00008000) + #define HCHIP_ISR_IS15_SHIFT (0x0000000F) + + #define HCHIP_ISR_IS15_SET(CrReg,Val) \ + HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ISR_IS15,Val)) + +/*----------------------------------------------------------------------------*\ +* (W) HCHIP_ISR +\*----------------------------------------------------------------------------*/ + #define HCHIP_ISR_SET(CrReg,Val) HCRREG32_SET(CrReg,Val) + + #define HCHIP_ISR_CFG(CrReg,is4,is5,is6,is7,is8,is9,is10,is11,is12,is13,is14,\ + is15) CrReg=(UINT32)( \ + HCRFIELD_SHIFT(HCHIP_ISR_IS4, is4) |\ + HCRFIELD_SHIFT(HCHIP_ISR_IS5, is5) |\ + HCRFIELD_SHIFT(HCHIP_ISR_IS6, is6) |\ + HCRFIELD_SHIFT(HCHIP_ISR_IS7, is7) |\ + HCRFIELD_SHIFT(HCHIP_ISR_IS8, is8) |\ + HCRFIELD_SHIFT(HCHIP_ISR_IS9, is9) |\ + HCRFIELD_SHIFT(HCHIP_ISR_IS10,is10)|\ + HCRFIELD_SHIFT(HCHIP_ISR_IS11,is11)|\ + HCRFIELD_SHIFT(HCHIP_ISR_IS12,is12)|\ + HCRFIELD_SHIFT(HCHIP_ISR_IS13,is13)|\ + HCRFIELD_SHIFT(HCHIP_ISR_IS14,is14)|\ + HCRFIELD_SHIFT(HCHIP_ISR_IS15,is15) \ + ) + +/******************************************************************************\ +* HCHIP_ICR - interrupt clear register +* +* Fields: +* (W) HCHIP_ICR_IC4 +* (W) HCHIP_ICR_IC5 +* (W) HCHIP_ICR_IC6 +* (W) HCHIP_ICR_IC7 +* (W) HCHIP_ICR_IC8 +* (W) HCHIP_ICR_IC9 +* (W) HCHIP_ICR_IC10 +* (W) HCHIP_ICR_IC11 +* (W) HCHIP_ICR_IC12 +* (W) HCHIP_ICR_IC13 +* (W) HCHIP_ICR_IC14 +* (W) HCHIP_ICR_IC15 +* +\******************************************************************************/ + extern far cregister volatile unsigned int ICR; + #define HCHIP_ICR ICR + +/*----------------------------------------------------------------------------*\ +* (W) HCHIP_ICR_IC4 +\*----------------------------------------------------------------------------*/ + #define HCHIP_ICR_IC4_MASK (0x00000010) + #define HCHIP_ICR_IC4_SHIFT (0x00000004) + + #define HCHIP_ICR_IC4_SET(CrReg,Val) \ + HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ICR_IC4,Val)) + +/*----------------------------------------------------------------------------*\ +* (W) HCHIP_ICR_IC5 +\*----------------------------------------------------------------------------*/ + #define HCHIP_ICR_IC5_MASK (0x00000020) + #define HCHIP_ICR_IC5_SHIFT (0x00000005) + + #define HCHIP_ICR_IC5_SET(CrReg,Val) \ + HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ICR_IC5,Val)) + + +/*----------------------------------------------------------------------------*\ +* (W) HCHIP_ICR_IC6 +\*----------------------------------------------------------------------------*/ + #define HCHIP_ICR_IC6_MASK (0x00000040) + #define HCHIP_ICR_IC6_SHIFT (0x00000006) + + #define HCHIP_ICR_IC6_SET(CrReg,Val) \ + HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ICR_IC6,Val)) + +/*----------------------------------------------------------------------------*\ +* (W) HCHIP_ICR_IC7 +\*----------------------------------------------------------------------------*/ + #define HCHIP_ICR_IC7_MASK (0x00000080) + #define HCHIP_ICR_IC7_SHIFT (0x00000007) + + #define HCHIP_ICR_IC7_SET(CrReg,Val) \ + HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ICR_IC7,Val)) + +/*----------------------------------------------------------------------------*\ +* (W) HCHIP_ICR_IC8 +\*----------------------------------------------------------------------------*/ + #define HCHIP_ICR_IC8_MASK (0x00000100) + #define HCHIP_ICR_IC8_SHIFT (0x00000008) + + #define HCHIP_ICR_IC8_SET(CrReg,Val) \ + HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ICR_IC8,Val)) + +/*----------------------------------------------------------------------------*\ +* (W) HCHIP_ICR_IC9 +\*----------------------------------------------------------------------------*/ + #define HCHIP_ICR_IC9_MASK (0x00000200) + #define HCHIP_ICR_IC9_SHIFT (0x00000009) + + #define HCHIP_ICR_IC9_SET(CrReg,Val) \ + HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ICR_IC9,Val)) + +/*----------------------------------------------------------------------------*\ +* (W) HCHIP_ICR_IC10 +\*----------------------------------------------------------------------------*/ + #define HCHIP_ICR_IC10_MASK (0x00000400) + #define HCHIP_ICR_IC10_SHIFT (0x0000000A) + + #define HCHIP_ICR_IC10_SET(CrReg,Val) \ + HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ICR_IC10,Val)) + +/*----------------------------------------------------------------------------*\ +* (W) HCHIP_ICR_IC11 +\*----------------------------------------------------------------------------*/ + #define HCHIP_ICR_IC11_MASK (0x00000800) + #define HCHIP_ICR_IC11_SHIFT (0x0000000B) + + #define HCHIP_ICR_IC11_SET(CrReg,Val) \ + HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ICR_IC11,Val)) +/*----------------------------------------------------------------------------*\ +* (W) HCHIP_ICR_IC12 +\*----------------------------------------------------------------------------*/ + #define HCHIP_ICR_IC12_MASK (0x00001000) + #define HCHIP_ICR_IC12_SHIFT (0x0000000C) + + #define HCHIP_ICR_IC12_SET(CrReg,Val) \ + HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ICR_IC12,Val)) + +/*----------------------------------------------------------------------------*\ +* (W) HCHIP_ICR_IC13 +\*----------------------------------------------------------------------------*/ + #define HCHIP_ICR_IC13_MASK (0x00002000) + #define HCHIP_ICR_IC13_SHIFT (0x0000000D) + + #define HCHIP_ICR_IC13_SET(CrReg,Val) \ + HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ICR_IC13,Val)) + +/*----------------------------------------------------------------------------*\ +* (W) HCHIP_ICR_IC14 +\*----------------------------------------------------------------------------*/ + #define HCHIP_ICR_IC14_MASK (0x00004000) + #define HCHIP_ICR_IC14_SHIFT (0x0000000E) + + #define HCHIP_ICR_IC14_SET(CrReg,Val) \ + HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ICR_IC14,Val)) + +/*----------------------------------------------------------------------------*\ +* (W) HCHIP_ICR_IC15 +\*----------------------------------------------------------------------------*/ + #define HCHIP_ICR_IC15_MASK (0x00008000) + #define HCHIP_ICR_IC15_SHIFT (0x0000000F) + + #define HCHIP_ICR_IC15_SET(CrReg,Val) \ + HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ICR_IC15,Val)) + +/*----------------------------------------------------------------------------*\ +* (W) HCHIP_ICR +\*----------------------------------------------------------------------------*/ + #define HCHIP_ICR_SET(CrReg,Val) HCRREG32_SET(CrReg,Val) + + #define HCHIP_ICR_CFG(CrReg,ic4,ic5,ic6,ic7,ic8,ic9,ic10,ic11,ic12,ic13,ic14,\ + ic15) CrReg=(UINT32)( \ + HCRFIELD_SHIFT(HCHIP_ICR_IC4, ic4) |\ + HCRFIELD_SHIFT(HCHIP_ICR_IC5, ic5) |\ + HCRFIELD_SHIFT(HCHIP_ICR_IC6, ic6) |\ + HCRFIELD_SHIFT(HCHIP_ICR_IC7, ic7) |\ + HCRFIELD_SHIFT(HCHIP_ICR_IC8, ic8) |\ + HCRFIELD_SHIFT(HCHIP_ICR_IC9, ic9) |\ + HCRFIELD_SHIFT(HCHIP_ICR_IC10,ic10)|\ + HCRFIELD_SHIFT(HCHIP_ICR_IC11,ic11)|\ + HCRFIELD_SHIFT(HCHIP_ICR_IC12,ic12)|\ + HCRFIELD_SHIFT(HCHIP_ICR_IC13,ic13)|\ + HCRFIELD_SHIFT(HCHIP_ICR_IC14,ic14)|\ + HCRFIELD_SHIFT(HCHIP_ICR_IC15,ic15) \ + ) + +/******************************************************************************\ +* HCHIP_IER - interrupt enable register +* +* Fields: +* (RW) HCHIP_IER_NMIE +* (RW) HCHIP_IER_IE4 +* (RW) HCHIP_IER_IE5 +* (RW) HCHIP_IER_IE6 +* (RW) HCHIP_IER_IE7 +* (RW) HCHIP_IER_IE8 +* (RW) HCHIP_IER_IE9 +* (RW) HCHIP_IER_IE10 +* (RW) HCHIP_IER_IE11 +* (RW) HCHIP_IER_IE12 +* (RW) HCHIP_IER_IE13 +* (RW) HCHIP_IER_IE14 +* (RW) HCHIP_IER_IE15 +* +\******************************************************************************/ + extern far cregister volatile unsigned int IER; + #define HCHIP_IER IER + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_IER_NMIE +\*----------------------------------------------------------------------------*/ + #define HCHIP_IER_NMIE_MASK (0x00000002) + #define HCHIP_IER_NMIE_SHIFT (0x00000001) + + #define HCHIP_IER_NMIE_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_IER_NMIE) + + #define HCHIP_IER_NMIE_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_IER_NMIE,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_IER_IE4 +\*----------------------------------------------------------------------------*/ + #define HCHIP_IER_IE4_MASK (0x00000010) + #define HCHIP_IER_IE4_SHIFT (0x00000004) + + #define HCHIP_IER_IE4_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_IER_IE4) + + #define HCHIP_IER_IE4_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_IER_IE4,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_IER_IE5 +\*----------------------------------------------------------------------------*/ + #define HCHIP_IER_IE5_MASK (0x00000020) + #define HCHIP_IER_IE5_SHIFT (0x00000005) + + #define HCHIP_IER_IE5_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_IER_IE5) + + #define HCHIP_IER_IE5_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_IER_IE5,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_IER_IE6 +\*----------------------------------------------------------------------------*/ + #define HCHIP_IER_IE6_MASK (0x00000040) + #define HCHIP_IER_IE6_SHIFT (0x00000006) + + #define HCHIP_IER_IE6_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_IER_IE6) + + #define HCHIP_IER_IE6_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_IER_IE6,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_IER_IE7 +\*----------------------------------------------------------------------------*/ + #define HCHIP_IER_IE7_MASK (0x00000080) + #define HCHIP_IER_IE7_SHIFT (0x00000007) + + #define HCHIP_IER_IE7_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_IER_IE7) + + #define HCHIP_IER_IE7_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_IER_IE7,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_IER_IE8 +\*----------------------------------------------------------------------------*/ + #define HCHIP_IER_IE8_MASK (0x00000100) + #define HCHIP_IER_IE8_SHIFT (0x00000008) + + #define HCHIP_IER_IE8_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_IER_IE8) + + #define HCHIP_IER_IE8_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_IER_IE8,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_IER_IE9 +\*----------------------------------------------------------------------------*/ + #define HCHIP_IER_IE9_MASK (0x00000200) + #define HCHIP_IER_IE9_SHIFT (0x00000009) + + #define HCHIP_IER_IE9_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_IER_IE9) + + #define HCHIP_IER_IE9_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_IER_IE9,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_IER_IE10 +\*----------------------------------------------------------------------------*/ + #define HCHIP_IER_IE10_MASK (0x00000400) + #define HCHIP_IER_IE10_SHIFT (0x0000000A) + + #define HCHIP_IER_IE10_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_IER_IE10) + + #define HCHIP_IER_IE10_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_IER_IE10,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_IER_IE11 +\*----------------------------------------------------------------------------*/ + #define HCHIP_IER_IE11_MASK (0x00000800) + #define HCHIP_IER_IE11_SHIFT (0x0000000B) + + #define HCHIP_IER_IE11_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_IER_IE11) + + #define HCHIP_IER_IE11_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_IER_IE11,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_IER_IE12 +\*----------------------------------------------------------------------------*/ + #define HCHIP_IER_IE12_MASK (0x00001000) + #define HCHIP_IER_IE12_SHIFT (0x0000000C) + + #define HCHIP_IER_IE12_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_IER_IE12) + + #define HCHIP_IER_IE12_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_IER_IE12,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_IER_IE13 +\*----------------------------------------------------------------------------*/ + #define HCHIP_IER_IE13_MASK (0x00002000) + #define HCHIP_IER_IE13_SHIFT (0x0000000D) + + #define HCHIP_IER_IE13_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_IER_IE13) + + #define HCHIP_IER_IE13_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_IER_IE13,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_IER_IE14 +\*----------------------------------------------------------------------------*/ + #define HCHIP_IER_IE14_MASK (0x00004000) + #define HCHIP_IER_IE14_SHIFT (0x0000000E) + + #define HCHIP_IER_IE14_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_IER_IE14) + + #define HCHIP_IER_IE14_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_IER_IE14,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_IER_IE15 +\*----------------------------------------------------------------------------*/ + #define HCHIP_IER_IE15_MASK (0x00008000) + #define HCHIP_IER_IE15_SHIFT (0x0000000F) + + #define HCHIP_IER_IE15_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_IER_IE15) + + #define HCHIP_IER_IE15_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_IER_IE15,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_IER +\*----------------------------------------------------------------------------*/ + #define HCHIP_IER_GET(CrReg) HCRREG32_GET(CrReg) + + #define HCHIP_IER_SET(CrReg,Val) HCRREG32_SET(CrReg,Val) + + #define HCHIP_IER_CFG(CrReg,nmie,ie4,ie5,ie6,ie7,ie8,ie9,ie10,ie11,ie12,ie13,\ + ie14,ie15) CrReg=(UINT32)( \ + HCRFIELD_SHIFT(HCHIP_IER_NMIE,nmie)|\ + HCRFIELD_SHIFT(HCHIP_IER_IE4, ie4) |\ + HCRFIELD_SHIFT(HCHIP_IER_IE5, ie5) |\ + HCRFIELD_SHIFT(HCHIP_IER_IE6, ie6) |\ + HCRFIELD_SHIFT(HCHIP_IER_IE7, ie7) |\ + HCRFIELD_SHIFT(HCHIP_IER_IE8, ie8) |\ + HCRFIELD_SHIFT(HCHIP_IER_IE9, ie9) |\ + HCRFIELD_SHIFT(HCHIP_IER_IE10,ie10)|\ + HCRFIELD_SHIFT(HCHIP_IER_IE11,ie11)|\ + HCRFIELD_SHIFT(HCHIP_IER_IE12,ie12)|\ + HCRFIELD_SHIFT(HCHIP_IER_IE13,ie13)|\ + HCRFIELD_SHIFT(HCHIP_IER_IE14,ie14)|\ + HCRFIELD_SHIFT(HCHIP_IER_IE15,ie15) \ + ) + +/******************************************************************************\ +* HCHIP_ISTP - interrupt service table pointer +* +* Fields: +* (R) HCHIP_ISTP_HPEINT +* (RW) HCHIP_ISTP_ISTB +* +\******************************************************************************/ + extern far cregister volatile unsigned int ISTP; + #define HCHIP_ISTP ISTP + +/*----------------------------------------------------------------------------*\ +* (R) HCHIP_ISTP_HPEINT +\*----------------------------------------------------------------------------*/ + #define HCHIP_ISTP_HPEINT_MASK (0x000003E0) + #define HCHIP_ISTP_HPEINT_SHIFT (0x00000005) + + #define HCHIP_ISTP_HPEINT_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_ISTP_HPEINT) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_ISTP_ISTB +\*----------------------------------------------------------------------------*/ + #define HCHIP_ISTP_ISTB_MASK (0xFFFFFC00) + #define HCHIP_ISTP_ISTB_SHIFT (0x0000000A) + + #define HCHIP_ISTP_ISTB_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_ISTP_ISTB) + + #define HCHIP_ISTP_ISTB_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_ISTP_ISTB,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_ISTP +\*----------------------------------------------------------------------------*/ + #define HCHIP_ISTP_GET(CrReg) HCRREG32_GET(CrReg) + + #define HCHIP_ISTP_SET(CrReg,Val) HCRREG32_SET(CrReg,Val) + + #define HCHIP_ISTP_CFG(CrReg,istb) CrReg=(UINT32)(\ + HCRFIELD_SHIFT(HCHIP_ISTP_ISTB,istb) \ + ) + +/******************************************************************************\ +* HCHIP_IRP - interrrupt return pointer +* +* Fields: +* (RW) HCHIP_IRP_IRP +* +\******************************************************************************/ + extern far cregister volatile unsigned int IRP; + #define HCHIP_IRP IRP + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_IRP_IRP +\*----------------------------------------------------------------------------*/ + #define HCHIP_IRP_IRP_MASK (0xFFFFFFFF) + #define HCHIP_IRP_IRP_SHIFT (0x00000000) + + #define HCHIP_IRP_IRP_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_IRP_IRP) + + #define HCHIP_IRP_IRP_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_IRP_IRP,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_IRP +\*----------------------------------------------------------------------------*/ + #define HCHIP_IRP_GET(CrReg) HCRREG32_GET(CrReg) + + #define HCHIP_IRP_SET(CrReg,Val) HCRREG32_SET(CrReg,Val) + + #define HCHIP_IRP_CFG(CrReg,irp) CrReg=(UINT32)( \ + HCRFIELD_SHIFT(HCHIP_IRP_IRP,irp) \ + ) + +/******************************************************************************\ +* HCHIP_NRP - nonmaskable interrupt return pointer +* +* Fields: +* (RW) HCHIP_NRP_NRP +* +\******************************************************************************/ + extern far cregister volatile unsigned int NRP; + #define HCHIP_NRP NRP + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_NRP_NRP +\*----------------------------------------------------------------------------*/ + #define HCHIP_NRP_NRP_MASK (0xFFFFFFFF) + #define HCHIP_NRP_NRP_SHIFT (0x00000000) + + #define HCHIP_NRP_NRP_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_NRP_NRP) + + #define HCHIP_NRP_NRP_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_NRP_NRP,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_NRP +\*----------------------------------------------------------------------------*/ + #define HCHIP_NRP_GET(CrReg) HCRREG32_GET(CrReg) + + #define HCHIP_NRP_SET(CrReg,Val) HCRREG32_SET(CrReg,Val) + + #define HCHIP_NRP_CFG(CrReg,nrp) CrReg=(UINT32)( \ + HCRFIELD_SHIFT(HCHIP_NRP_NRP,nrp) \ + ) + +/******************************************************************************\ +* HCHIP_AMR - addressing mode register +* +* Fields: +* (RW) HCHIP_AMR_A4MODE +* (RW) HCHIP_AMR_A5MODE +* (RW) HCHIP_AMR_A6MODE +* (RW) HCHIP_AMR_A7MODE +* (RW) HCHIP_AMR_B4MODE +* (RW) HCHIP_AMR_B5MODE +* (RW) HCHIP_AMR_B6MODE +* (RW) HCHIP_AMR_B7MODE +* (RW) HCHIP_AMR_BK0 +* (RW) HCHIP_AMR_BK1 +* +\******************************************************************************/ + extern far cregister volatile unsigned int AMR; + #define HCHIP_AMR AMR + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_AMR_A4MODE +\*----------------------------------------------------------------------------*/ + #define HCHIP_AMR_A4MODE_MASK (0x00000003) + #define HCHIP_AMR_A4MODE_SHIFT (0x00000000) + + #define HCHIP_AMR_A4MODE_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_AMR_A4MODE) + + #define HCHIP_AMR_A4MODE_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_AMR_A4MODE,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_AMR_A5MODE +\*----------------------------------------------------------------------------*/ + #define HCHIP_AMR_A5MODE_MASK (0x0000000C) + #define HCHIP_AMR_A5MODE_SHIFT (0x00000002) + + #define HCHIP_AMR_A5MODE_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_AMR_A5MODE) + + #define HCHIP_AMR_A5MODE_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_AMR_A5MODE,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_AMR_A6MODE +\*----------------------------------------------------------------------------*/ + #define HCHIP_AMR_A6MODE_MASK (0x00000030) + #define HCHIP_AMR_A6MODE_SHIFT (0x00000004) + + #define HCHIP_AMR_A6MODE_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_AMR_A6MODE) + + #define HCHIP_AMR_A6MODE_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_AMR_A6MODE,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_AMR_A7MODE +\*----------------------------------------------------------------------------*/ + #define HCHIP_AMR_A7MODE_MASK (0x000000C0) + #define HCHIP_AMR_A7MODE_SHIFT (0x00000006) + + #define HCHIP_AMR_A7MODE_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_AMR_A7MODE) + + #define HCHIP_AMR_A7MODE_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_AMR_A7MODE,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_AMR_B4MODE +\*----------------------------------------------------------------------------*/ + #define HCHIP_AMR_B4MODE_MASK (0x00000300) + #define HCHIP_AMR_B4MODE_SHIFT (0x00000008) + + #define HCHIP_AMR_B4MODE_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_AMR_B4MODE) + + #define HCHIP_AMR_B4MODE_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_AMR_B4MODE,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_AMR_B5MODE +\*----------------------------------------------------------------------------*/ + #define HCHIP_AMR_B5MODE_MASK (0x00000C00) + #define HCHIP_AMR_B5MODE_SHIFT (0x0000000A) + + #define HCHIP_AMR_B5MODE_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_AMR_B5MODE) + + #define HCHIP_AMR_B5MODE_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_AMR_B5MODE,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_AMR_B6MODE +\*----------------------------------------------------------------------------*/ + #define HCHIP_AMR_B6MODE_MASK (0x00003000) + #define HCHIP_AMR_B6MODE_SHIFT (0x0000000C) + + #define HCHIP_AMR_B6MODE_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_AMR_B6MODE) + + #define HCHIP_AMR_B6MODE_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_AMR_B6MODE,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_AMR_B7MODE +\*----------------------------------------------------------------------------*/ + #define HCHIP_AMR_B7MODE_MASK (0x0000C000) + #define HCHIP_AMR_B7MODE_SHIFT (0x0000000E) + + #define HCHIP_AMR_B7MODE_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_AMR_B7MODE) + + #define HCHIP_AMR_B7MODE_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_AMR_B7MODE,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_AMR_BK0 +\*----------------------------------------------------------------------------*/ + #define HCHIP_AMR_BK0_MASK (0x001F0000) + #define HCHIP_AMR_BK0_SHIFT (0x00000010) + + #define HCHIP_AMR_BK0_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_AMR_BK0) + + #define HCHIP_AMR_BK0_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_AMR_BK0,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_AMR_BK1 +\*----------------------------------------------------------------------------*/ + #define HCHIP_AMR_BK1_MASK (0x001F0000) + #define HCHIP_AMR_BK1_SHIFT (0x00000010) + + #define HCHIP_AMR_BK1_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_AMR_BK1) + + #define HCHIP_AMR_BK1_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_AMR_BK1,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_AMR +\*----------------------------------------------------------------------------*/ + #define HCHIP_AMR_GET(CrReg) HCRREG32_GET(CrReg) + + #define HCHIP_AMR_SET(CrReg,Val) HCRREG32_SET(CrReg,Val) + + #define HCHIP_AMR_CFG(CrReg,a4mode,a5mode,a6mode,a7mode,b4mode,b5mode,b6mode,\ + b7mode,bk0,bk1) CrReg=(UINT32)( \ + HCRFIELD_SHIFT(HCHIP_AMR_A4MODE,a4mode)| \ + HCRFIELD_SHIFT(HCHIP_AMR_A5MODE,a5mode)| \ + HCRFIELD_SHIFT(HCHIP_AMR_A6MODE,a6mode)| \ + HCRFIELD_SHIFT(HCHIP_AMR_A7MODE,a7mode)| \ + HCRFIELD_SHIFT(HCHIP_AMR_B4MODE,b4mode)| \ + HCRFIELD_SHIFT(HCHIP_AMR_B5MODE,b5mode)| \ + HCRFIELD_SHIFT(HCHIP_AMR_B6MODE,b6mode)| \ + HCRFIELD_SHIFT(HCHIP_AMR_B7MODE,b7mode)| \ + HCRFIELD_SHIFT(HCHIP_AMR_BK0,bk0)| \ + HCRFIELD_SHIFT(HCHIP_AMR_BK1,bk1) \ + ) + +#if (FPU_SUPPORT) +/******************************************************************************\ +* HCHIP_FADCR - floating-point adder config register (1) +* +* (1) only supported on devices with floating point unit +* +* Fields: +* (RW) HCHIP_FADCR_L1NAN1 +* (RW) HCHIP_FADCR_L1NAN2 +* (RW) HCHIP_FADCR_L1DEN1 +* (RW) HCHIP_FADCR_L1DEN2 +* (RW) HCHIP_FADCR_L1INVAL +* (RW) HCHIP_FADCR_L1INFO +* (RW) HCHIP_FADCR_L1OVER +* (RW) HCHIP_FADCR_L1INEX +* (RW) HCHIP_FADCR_L1UNDER +* (RW) HCHIP_FADCR_L1RMODE +* (RW) HCHIP_FADCR_L2NAN1 +* (RW) HCHIP_FADCR_L2NAN2 +* (RW) HCHIP_FADCR_L2DEN1 +* (RW) HCHIP_FADCR_L2DEN2 +* (RW) HCHIP_FADCR_L2INVAL +* (RW) HCHIP_FADCR_L2INFO +* (RW) HCHIP_FADCR_L2OVER +* (RW) HCHIP_FADCR_L2INEX +* (RW) HCHIP_FADCR_L2UNDER +* (RW) HCHIP_FADCR_L2RMODE +* +\******************************************************************************/ + extern far cregister volatile unsigned int FADCR; + #define HCHIP_FADCR FADCR + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FADCR_L1NAN1 +\*----------------------------------------------------------------------------*/ + #define HCHIP_FADCR_L1NAN1_MASK (0x00000001) + #define HCHIP_FADCR_L1NAN1_SHIFT (0x00000000) + + #define HCHIP_FADCR_L1NAN1_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FADCR_L1NAN1) + + #define HCHIP_FADCR_L1NAN1_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FADCR_L1NAN1,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FADCR_L1NAN2 +\*----------------------------------------------------------------------------*/ + #define HCHIP_FADCR_L1NAN2_MASK (0x00000002) + #define HCHIP_FADCR_L1NAN2_SHIFT (0x00000001) + + #define HCHIP_FADCR_L1NAN2_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FADCR_L1NAN2) + + #define HCHIP_FADCR_L1NAN2_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FADCR_L1NAN2,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FADCR_L1DEN1 +\*----------------------------------------------------------------------------*/ + #define HCHIP_FADCR_L1DEN1_MASK (0x00000004) + #define HCHIP_FADCR_L1DEN1_SHIFT (0x00000002) + + #define HCHIP_FADCR_L1DEN1_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FADCR_L1DEN1) + + #define HCHIP_FADCR_L1DEN1_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FADCR_L1DEN1,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FADCR_L1DEN2 +\*----------------------------------------------------------------------------*/ + #define HCHIP_FADCR_L1DEN2_MASK (0x00000008) + #define HCHIP_FADCR_L1DEN2_SHIFT (0x00000003) + + #define HCHIP_FADCR_L1DEN2_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FADCR_L1DEN2) + + #define HCHIP_FADCR_L1DEN2_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FADCR_L1DEN2,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FADCR_L1INVAL +\*----------------------------------------------------------------------------*/ + #define HCHIP_FADCR_L1INVAL_MASK (0x00000010) + #define HCHIP_FADCR_L1INVAL_SHIFT (0x00000004) + + #define HCHIP_FADCR_L1INVAL_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FADCR_L1INVAL) + + #define HCHIP_FADCR_L1INVAL_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FADCR_L1INVAL,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FADCR_L1INFO +\*----------------------------------------------------------------------------*/ + #define HCHIP_FADCR_L1INFO_MASK (0x00000020) + #define HCHIP_FADCR_L1INFO_SHIFT (0x00000005) + + #define HCHIP_FADCR_L1INFO_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FADCR_L1INFO) + + #define HCHIP_FADCR_L1INFO_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FADCR_L1INFO,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FADCR_L1OVER +\*----------------------------------------------------------------------------*/ + #define HCHIP_FADCR_L1OVER_MASK (0x00000040) + #define HCHIP_FADCR_L1OVER_SHIFT (0x00000006) + + #define HCHIP_FADCR_L1OVER_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FADCR_L1OVER) + + #define HCHIP_FADCR_L1OVER_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FADCR_L1OVER,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FADCR_L1INEX +\*----------------------------------------------------------------------------*/ + #define HCHIP_FADCR_L1INEX_MASK (0x00000080) + #define HCHIP_FADCR_L1INEX_SHIFT (0x00000007) + + #define HCHIP_FADCR_L1INEX_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FADCR_L1INEX) + + #define HCHIP_FADCR_L1INEX_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FADCR_L1INEX,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FADCR_L1UNDER +\*----------------------------------------------------------------------------*/ + #define HCHIP_FADCR_L1UNDER_MASK (0x00000100) + #define HCHIP_FADCR_L1UNDER_SHIFT (0x00000008) + + #define HCHIP_FADCR_L1UNDER_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FADCR_L1UNDER) + + #define HCHIP_FADCR_L1UNDER_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FADCR_L1UNDER,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FADCR_L1RMODE +\*----------------------------------------------------------------------------*/ + #define HCHIP_FADCR_L1RMODE_MASK (0x00000600) + #define HCHIP_FADCR_L1RMODE_SHIFT (0x00000009) + + #define HCHIP_FADCR_L1RMODE_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FADCR_L1RMODE) + + #define HCHIP_FADCR_L1RMODE_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FADCR_L1RMODE,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FADCR_L2NAN1 +\*----------------------------------------------------------------------------*/ + #define HCHIP_FADCR_L2NAN1_MASK (0x00010000) + #define HCHIP_FADCR_L2NAN1_SHIFT (0x00000010) + + #define HCHIP_FADCR_L2NAN1_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FADCR_L2NAN1) + + #define HCHIP_FADCR_L2NAN1_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FADCR_L2NAN1,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FADCR_L2NAN2 +\*----------------------------------------------------------------------------*/ + #define HCHIP_FADCR_L2NAN2_MASK (0x00020000) + #define HCHIP_FADCR_L2NAN2_SHIFT (0x00000011) + + #define HCHIP_FADCR_L2NAN2_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FADCR_L2NAN2) + + #define HCHIP_FADCR_L2NAN2_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FADCR_L2NAN2,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FADCR_L2DEN1 +\*----------------------------------------------------------------------------*/ + #define HCHIP_FADCR_L2DEN1_MASK (0x00040000) + #define HCHIP_FADCR_L2DEN1_SHIFT (0x00000012) + + #define HCHIP_FADCR_L2DEN1_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FADCR_L2DEN1) + + #define HCHIP_FADCR_L2DEN1_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FADCR_L2DEN1,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FADCR_L2DEN2 +\*----------------------------------------------------------------------------*/ + #define HCHIP_FADCR_L2DEN2_MASK (0x00080000) + #define HCHIP_FADCR_L2DEN2_SHIFT (0x00000013) + + #define HCHIP_FADCR_L2DEN2_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FADCR_L2DEN2) + + #define HCHIP_FADCR_L2DEN2_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FADCR_L2DEN2,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FADCR_L2INVAL +\*----------------------------------------------------------------------------*/ + #define HCHIP_FADCR_L2INVAL_MASK (0x00100000) + #define HCHIP_FADCR_L2INVAL_SHIFT (0x00000014) + + #define HCHIP_FADCR_L2INVAL_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FADCR_L2INVAL) + + #define HCHIP_FADCR_L2INVAL_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FADCR_L2INVAL,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FADCR_L2INFO +\*----------------------------------------------------------------------------*/ + #define HCHIP_FADCR_L2INFO_MASK (0x00200000) + #define HCHIP_FADCR_L2INFO_SHIFT (0x00000015) + + #define HCHIP_FADCR_L2INFO_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FADCR_L2INFO) + + #define HCHIP_FADCR_L2INFO_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FADCR_L2INFO,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FADCR_L2OVER +\*----------------------------------------------------------------------------*/ + #define HCHIP_FADCR_L2OVER_MASK (0x00400000) + #define HCHIP_FADCR_L2OVER_SHIFT (0x00000016) + + #define HCHIP_FADCR_L2OVER_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FADCR_L2OVER) + + #define HCHIP_FADCR_L2OVER_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FADCR_L2OVER,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FADCR_L2INEX +\*----------------------------------------------------------------------------*/ + #define HCHIP_FADCR_L2INEX_MASK (0x00800000) + #define HCHIP_FADCR_L2INEX_SHIFT (0x00000017) + + #define HCHIP_FADCR_L2INEX_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FADCR_L2INEX) + + #define HCHIP_FADCR_L2INEX_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FADCR_L2INEX,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FADCR_L2UNDER +\*----------------------------------------------------------------------------*/ + #define HCHIP_FADCR_L2UNDER_MASK (0x01000000) + #define HCHIP_FADCR_L2UNDER_SHIFT (0x00000018) + + #define HCHIP_FADCR_L2UNDER_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FADCR_L2UNDER) + + #define HCHIP_FADCR_L2UNDER_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FADCR_L2UNDER,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FADCR_L2RMODE +\*----------------------------------------------------------------------------*/ + #define HCHIP_FADCR_L2RMODE_MASK (0x06000000) + #define HCHIP_FADCR_L2RMODE_SHIFT (0x00000019) + + #define HCHIP_FADCR_L2RMODE_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FADCR_L2RMODE) + + #define HCHIP_FADCR_L2RMODE_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FADCR_L2RMODE,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FADCR +\*----------------------------------------------------------------------------*/ + #define HCHIP_FADCR_GET(CrReg) HCRREG32_GET(CrReg) + + #define HCHIP_FADCR_SET(CrReg,Val) HCRREG32_SET(CrReg,Val) + + #define HCHIP_FADCR_CFG(CrReg,l1nan1,l1nan2,l1den1,l1den2,l1inval,l1info,\ + l1over,l1inex,l1under,l1rmode,l2nan1,l2nan2,l2den1,l2den2,l2inval,l2info,\ + l2over,l2inex,l2under,l2rmode) CrReg=(UINT32)( \ + HCRFIELD_SHIFT(HCHIP_FADCR_L1NAN1, l1nan1) |\ + HCRFIELD_SHIFT(HCHIP_FADCR_L1NAN2, l1nan2) |\ + HCRFIELD_SHIFT(HCHIP_FADCR_L1DEN1, l1den1) |\ + HCRFIELD_SHIFT(HCHIP_FADCR_L1DEN2, l1den2) |\ + HCRFIELD_SHIFT(HCHIP_FADCR_L1INVAL,l1inval)|\ + HCRFIELD_SHIFT(HCHIP_FADCR_L1INFO, l1info) |\ + HCRFIELD_SHIFT(HCHIP_FADCR_L1OVER, l1over) |\ + HCRFIELD_SHIFT(HCHIP_FADCR_L1INEX, l1inex) |\ + HCRFIELD_SHIFT(HCHIP_FADCR_L1UNDER,l1under)|\ + HCRFIELD_SHIFT(HCHIP_FADCR_L1RMODE,l1rmode)|\ + HCRFIELD_SHIFT(HCHIP_FADCR_L2NAN1, l2nan1) |\ + HCRFIELD_SHIFT(HCHIP_FADCR_L2NAN2, l2nan2) |\ + HCRFIELD_SHIFT(HCHIP_FADCR_L2DEN1, l2den1) |\ + HCRFIELD_SHIFT(HCHIP_FADCR_L2DEN2, l2den2) |\ + HCRFIELD_SHIFT(HCHIP_FADCR_L2INVAL,l2inval)|\ + HCRFIELD_SHIFT(HCHIP_FADCR_L2INFO, l2info) |\ + HCRFIELD_SHIFT(HCHIP_FADCR_L2OVER, l2over) |\ + HCRFIELD_SHIFT(HCHIP_FADCR_L2INEX, l2inex) |\ + HCRFIELD_SHIFT(HCHIP_FADCR_L2UNDER,l2under)|\ + HCRFIELD_SHIFT(HCHIP_FADCR_L2RMODE,l2rmode) \ + ) +#endif /* FPU_SUPPORT */ + +#if (FPU_SUPPORT) +/******************************************************************************\ +* HCHIP_FAUCR - floating-point auxiliary config register (1) +* +* (1) only supported on devices with floating point unit +* +* Fields: +* (RW) HCHIP_FAUCR_S1NAN1 +* (RW) HCHIP_FAUCR_S1NAN2 +* (RW) HCHIP_FAUCR_S1DEN1 +* (RW) HCHIP_FAUCR_S1DEN2 +* (RW) HCHIP_FAUCR_S1INVAL +* (RW) HCHIP_FAUCR_S1INFO +* (RW) HCHIP_FAUCR_S1OVER +* (RW) HCHIP_FAUCR_S1INEX +* (RW) HCHIP_FAUCR_S1UNDER +* (RW) HCHIP_FAUCR_S1UNORD +* (RW) HCHIP_FAUCR_S1DIV0 +* (RW) HCHIP_FAUCR_S2NAN1 +* (RW) HCHIP_FAUCR_S2NAN2 +* (RW) HCHIP_FAUCR_S2DEN1 +* (RW) HCHIP_FAUCR_S2DEN2 +* (RW) HCHIP_FAUCR_S2INVAL +* (RW) HCHIP_FAUCR_S2INFO +* (RW) HCHIP_FAUCR_S2OVER +* (RW) HCHIP_FAUCR_S2INEX +* (RW) HCHIP_FAUCR_S2UNDER +* (RW) HCHIP_FAUCR_S2UNORD +* (RW) HCHIP_FAUCR_S2DIV0 +* +\******************************************************************************/ + extern far cregister volatile unsigned int FAUCR; + #define HCHIP_FAUCR FAUCR + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FAUCR_S1NAN1 +\*----------------------------------------------------------------------------*/ + #define HCHIP_FAUCR_S1NAN1_MASK (0x00000001) + #define HCHIP_FAUCR_S1NAN1_SHIFT (0x00000000) + + #define HCHIP_FAUCR_S1NAN1_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FAUCR_S1NAN1) + + #define HCHIP_FAUCR_S1NAN1_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FAUCR_S1NAN1,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FAUCR_S1NAN2 +\*----------------------------------------------------------------------------*/ + #define HCHIP_FAUCR_S1NAN2_MASK (0x00000002) + #define HCHIP_FAUCR_S1NAN2_SHIFT (0x00000001) + + #define HCHIP_FAUCR_S1NAN2_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FAUCR_S1NAN2) + + #define HCHIP_FAUCR_S1NAN2_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FAUCR_S1NAN2,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FAUCR_S1DEN1 +\*----------------------------------------------------------------------------*/ + #define HCHIP_FAUCR_S1DEN1_MASK (0x00000004) + #define HCHIP_FAUCR_S1DEN1_SHIFT (0x00000002) + + #define HCHIP_FAUCR_S1DEN1_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FAUCR_S1DEN1) + + #define HCHIP_FAUCR_S1DEN1_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FAUCR_S1DEN1,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FAUCR_S1DEN2 +\*----------------------------------------------------------------------------*/ + #define HCHIP_FAUCR_S1DEN2_MASK (0x00000008) + #define HCHIP_FAUCR_S1DEN2_SHIFT (0x00000003) + + #define HCHIP_FAUCR_S1DEN2_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FAUCR_S1DEN2) + + #define HCHIP_FAUCR_S1DEN2_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FAUCR_S1DEN2,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FAUCR_S1INVAL +\*----------------------------------------------------------------------------*/ + #define HCHIP_FAUCR_S1INVAL_MASK (0x00000010) + #define HCHIP_FAUCR_S1INVAL_SHIFT (0x00000004) + + #define HCHIP_FAUCR_S1INVAL_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FAUCR_S1INVAL) + + #define HCHIP_FAUCR_S1INVAL_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FAUCR_S1INVAL,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FAUCR_S1INFO +\*----------------------------------------------------------------------------*/ + #define HCHIP_FAUCR_S1INFO_MASK (0x00000020) + #define HCHIP_FAUCR_S1INFO_SHIFT (0x00000005) + + #define HCHIP_FAUCR_S1INFO_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FAUCR_S1INFO) + + #define HCHIP_FAUCR_S1INFO_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FAUCR_S1INFO,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FAUCR_S1OVER +\*----------------------------------------------------------------------------*/ + #define HCHIP_FAUCR_S1OVER_MASK (0x00000040) + #define HCHIP_FAUCR_S1OVER_SHIFT (0x00000006) + + #define HCHIP_FAUCR_S1OVER_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FAUCR_S1OVER) + + #define HCHIP_FAUCR_S1OVER_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FAUCR_S1OVER,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FAUCR_S1INEX +\*----------------------------------------------------------------------------*/ + #define HCHIP_FAUCR_S1INEX_MASK (0x00000080) + #define HCHIP_FAUCR_S1INEX_SHIFT (0x00000007) + + #define HCHIP_FAUCR_S1INEX_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FAUCR_S1INEX) + + #define HCHIP_FAUCR_S1INEX_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FAUCR_S1INEX,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FAUCR_S1UNDER +\*----------------------------------------------------------------------------*/ + #define HCHIP_FAUCR_S1UNDER_MASK (0x00000100) + #define HCHIP_FAUCR_S1UNDER_SHIFT (0x00000008) + + #define HCHIP_FAUCR_S1UNDER_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FAUCR_S1UNDER) + + #define HCHIP_FAUCR_S1UNDER_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FAUCR_S1UNDER,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FAUCR_S1UNORD +\*----------------------------------------------------------------------------*/ + #define HCHIP_FAUCR_S1UNORD_MASK (0x00000200) + #define HCHIP_FAUCR_S1UNORD_SHIFT (0x00000009) + + #define HCHIP_FAUCR_S1UNORD_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FAUCR_S1UNORD) + + #define HCHIP_FAUCR_S1UNORD_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FAUCR_S1UNORD,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FAUCR_S1DIV0 +\*----------------------------------------------------------------------------*/ + #define HCHIP_FAUCR_S1DIV0_MASK (0x00000400) + #define HCHIP_FAUCR_S1DIV0_SHIFT (0x0000000A) + + #define HCHIP_FAUCR_S1DIV0_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FAUCR_S1DIV0) + + #define HCHIP_FAUCR_S1DIV0_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FAUCR_S1DIV0,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FAUCR_S2NAN1 +\*----------------------------------------------------------------------------*/ + #define HCHIP_FAUCR_S2NAN1_MASK (0x00010000) + #define HCHIP_FAUCR_S2NAN1_SHIFT (0x00000010) + + #define HCHIP_FAUCR_S2NAN1_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FAUCR_S2NAN1) + + #define HCHIP_FAUCR_S2NAN1_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FAUCR_S2NAN1,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FAUCR_S2NAN2 +\*----------------------------------------------------------------------------*/ + #define HCHIP_FAUCR_S2NAN2_MASK (0x00020000) + #define HCHIP_FAUCR_S2NAN2_SHIFT (0x00000011) + + #define HCHIP_FAUCR_S2NAN2_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FAUCR_S2NAN2) + + #define HCHIP_FAUCR_S2NAN2_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FAUCR_S2NAN2,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FAUCR_S2DEN1 +\*----------------------------------------------------------------------------*/ + #define HCHIP_FAUCR_S2DEN1_MASK (0x00040000) + #define HCHIP_FAUCR_S2DEN1_SHIFT (0x00000012) + + #define HCHIP_FAUCR_S2DEN1_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FAUCR_S2DEN1) + + #define HCHIP_FAUCR_S2DEN1_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FAUCR_S2DEN1,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FAUCR_S2DEN2 +\*----------------------------------------------------------------------------*/ + #define HCHIP_FAUCR_S2DEN2_MASK (0x00080000) + #define HCHIP_FAUCR_S2DEN2_SHIFT (0x00000013) + + #define HCHIP_FAUCR_S2DEN2_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FAUCR_S2DEN2) + + #define HCHIP_FAUCR_S2DEN2_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FAUCR_S2DEN2,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FAUCR_S2INVAL +\*----------------------------------------------------------------------------*/ + #define HCHIP_FAUCR_S2INVAL_MASK (0x00100000) + #define HCHIP_FAUCR_S2INVAL_SHIFT (0x00000014) + + #define HCHIP_FAUCR_S2INVAL_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FAUCR_S2INVAL) + + #define HCHIP_FAUCR_S2INVAL_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FAUCR_S2INVAL,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FAUCR_S2INFO +\*----------------------------------------------------------------------------*/ + #define HCHIP_FAUCR_S2INFO_MASK (0x00200000) + #define HCHIP_FAUCR_S2INFO_SHIFT (0x00000015) + + #define HCHIP_FAUCR_S2INFO_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FAUCR_S2INFO) + + #define HCHIP_FAUCR_S2INFO_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FAUCR_S2INFO,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FAUCR_S2OVER +\*----------------------------------------------------------------------------*/ + #define HCHIP_FAUCR_S2OVER_MASK (0x00400000) + #define HCHIP_FAUCR_S2OVER_SHIFT (0x00000016) + + #define HCHIP_FAUCR_S2OVER_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FAUCR_S2OVER) + + #define HCHIP_FAUCR_S2OVER_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FAUCR_S2OVER,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FAUCR_S2INEX +\*----------------------------------------------------------------------------*/ + #define HCHIP_FAUCR_S2INEX_MASK (0x00800000) + #define HCHIP_FAUCR_S2INEX_SHIFT (0x00000017) + + #define HCHIP_FAUCR_S2INEX_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FAUCR_S2INEX) + + #define HCHIP_FAUCR_S2INEX_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FAUCR_S2INEX,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FAUCR_S2UNDER +\*----------------------------------------------------------------------------*/ + #define HCHIP_FAUCR_S2UNDER_MASK (0x01000000) + #define HCHIP_FAUCR_S2UNDER_SHIFT (0x00000018) + + #define HCHIP_FAUCR_S2UNDER_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FAUCR_S2UNDER) + + #define HCHIP_FAUCR_S2UNDER_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FAUCR_S2UNDER,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FAUCR_S2UNORD +\*----------------------------------------------------------------------------*/ + #define HCHIP_FAUCR_S2UNORD_MASK (0x02000000) + #define HCHIP_FAUCR_S2UNORD_SHIFT (0x00000019) + + #define HCHIP_FAUCR_S2UNORD_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FAUCR_S2UNORD) + + #define HCHIP_FAUCR_S2UNORD_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FAUCR_S2UNORD,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FAUCR_S2DIV0 +\*----------------------------------------------------------------------------*/ + #define HCHIP_FAUCR_S2DIV0_MASK (0x04000000) + #define HCHIP_FAUCR_S2DIV0_SHIFT (0x0000001A) + + #define HCHIP_FAUCR_S2DIV0_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FAUCR_S2DIV0) + + #define HCHIP_FAUCR_S2DIV0_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FAUCR_S2DIV0,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FADCR +\*----------------------------------------------------------------------------*/ + #define HCHIP_FAUCR_GET(CrReg) HCRREG32_GET(CrReg) + + #define HCHIP_FAUCR_SET(CrReg,Val) HCRREG32_SET(CrReg,Val) + + #define HCHIP_FAUCR_CFG(CrReg,s1nan1,s1nan2,s1den1,s1den2,s1inval,s1info,\ + s1over,s1inex,s1under,s1unord,s1div0,s2nan1,s2nan2,s2den1,s2den2,s2inval,\ + s2info,s2over,s2inex,s2under,s2unord,s2div0) CrReg=(UINT32)( \ + HCRFIELD_SHIFT(HCHIP_FAUCR_S1NAN1, s1nan1) |\ + HCRFIELD_SHIFT(HCHIP_FAUCR_S1NAN2, s1nan2) |\ + HCRFIELD_SHIFT(HCHIP_FAUCR_S1DEN1, s1den1) |\ + HCRFIELD_SHIFT(HCHIP_FAUCR_S1DEN2, s1den2) |\ + HCRFIELD_SHIFT(HCHIP_FAUCR_S1INVAL,s1inval)|\ + HCRFIELD_SHIFT(HCHIP_FAUCR_S1INFO, s1info) |\ + HCRFIELD_SHIFT(HCHIP_FAUCR_S1OVER, s1over) |\ + HCRFIELD_SHIFT(HCHIP_FAUCR_S1INEX, s1inex) |\ + HCRFIELD_SHIFT(HCHIP_FAUCR_S1UNDER,s1under)|\ + HCRFIELD_SHIFT(HCHIP_FAUCR_S1UNORD,s1unord)|\ + HCRFIELD_SHIFT(HCHIP_FAUCR_S1DIV0, s1div0) |\ + HCRFIELD_SHIFT(HCHIP_FAUCR_S2NAN1, s2nan1) |\ + HCRFIELD_SHIFT(HCHIP_FAUCR_S2NAN2, s2nan2) |\ + HCRFIELD_SHIFT(HCHIP_FAUCR_S2DEN1, s2den1) |\ + HCRFIELD_SHIFT(HCHIP_FAUCR_S2DEN2, s2den2) |\ + HCRFIELD_SHIFT(HCHIP_FAUCR_S2INVAL,s2inval)|\ + HCRFIELD_SHIFT(HCHIP_FAUCR_S2INFO, s2info) |\ + HCRFIELD_SHIFT(HCHIP_FAUCR_S2OVER, s2over) |\ + HCRFIELD_SHIFT(HCHIP_FAUCR_S2INEX, s2inex) |\ + HCRFIELD_SHIFT(HCHIP_FAUCR_S2UNDER,s2under)|\ + HCRFIELD_SHIFT(HCHIP_FAUCR_S2UNORD,s2unord)|\ + HCRFIELD_SHIFT(HCHIP_FAUCR_S2DIV0, s2div0) \ + ) +#endif /* FPU_SUPPORT */ + +#if (FPU_SUPPORT) +/******************************************************************************\ +* HCHIP_FMCR - floating-point multiplier config register (1) +* +* (1) only supported on devices with floating point unit +* +* Fields: +* (RW) HCHIP_FMCR_M1NAN1 +* (RW) HCHIP_FMCR_M1NAN2 +* (RW) HCHIP_FMCR_M1DEN1 +* (RW) HCHIP_FMCR_M1DEN2 +* (RW) HCHIP_FMCR_M1INVAL +* (RW) HCHIP_FMCR_M1INFO +* (RW) HCHIP_FMCR_M1OVER +* (RW) HCHIP_FMCR_M1INEX +* (RW) HCHIP_FMCR_M1UNDER +* (RW) HCHIP_FMCR_M1RMODE +* (RW) HCHIP_FMCR_M2NAN1 +* (RW) HCHIP_FMCR_M2NAN2 +* (RW) HCHIP_FMCR_M2DEN1 +* (RW) HCHIP_FMCR_M2DEN2 +* (RW) HCHIP_FMCR_M2INVAL +* (RW) HCHIP_FMCR_M2INFO +* (RW) HCHIP_FMCR_M2OVER +* (RW) HCHIP_FMCR_M2INEX +* (RW) HCHIP_FMCR_M2UNDER +* (RW) HCHIP_FMCR_M2RMODE +* +\******************************************************************************/ + extern far cregister volatile unsigned int FMCR; + #define HCHIP_FMCR FMCR + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FMCR_M1NAN1 +\*----------------------------------------------------------------------------*/ + #define HCHIP_FMCR_M1NAN1_MASK (0x00000001) + #define HCHIP_FMCR_M1NAN1_SHIFT (0x00000000) + + #define HCHIP_FMCR_M1NAN1_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FMCR_M1NAN1) + + #define HCHIP_FMCR_M1NAN1_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FMCR_M1NAN1,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FMCR_M1NAN2 +\*----------------------------------------------------------------------------*/ + #define HCHIP_FMCR_M1NAN2_MASK (0x00000002) + #define HCHIP_FMCR_M1NAN2_SHIFT (0x00000001) + + #define HCHIP_FMCR_M1NAN2_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FMCR_M1NAN2) + + #define HCHIP_FMCR_M1NAN2_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FMCR_M1NAN2,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FMCR_M1DEN1 +\*----------------------------------------------------------------------------*/ + #define HCHIP_FMCR_M1DEN1_MASK (0x00000004) + #define HCHIP_FMCR_M1DEN1_SHIFT (0x00000002) + + #define HCHIP_FMCR_M1DEN1_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FMCR_M1DEN1) + + #define HCHIP_FMCR_M1DEN1_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FMCR_M1DEN1,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FMCR_M1DEN2 +\*----------------------------------------------------------------------------*/ + #define HCHIP_FMCR_M1DEN2_MASK (0x00000008) + #define HCHIP_FMCR_M1DEN2_SHIFT (0x00000003) + + #define HCHIP_FMCR_M1DEN2_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FMCR_M1DEN2) + + #define HCHIP_FMCR_M1DEN2_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FMCR_M1DEN2,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FMCR_M1INVAL +\*----------------------------------------------------------------------------*/ + #define HCHIP_FMCR_M1INVAL_MASK (0x00000010) + #define HCHIP_FMCR_M1INVAL_SHIFT (0x00000004) + + #define HCHIP_FMCR_M1INVAL_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FMCR_M1INVAL) + + #define HCHIP_FMCR_M1INVAL_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FMCR_M1INVAL,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FMCR_M1INFO +\*----------------------------------------------------------------------------*/ + #define HCHIP_FMCR_M1INFO_MASK (0x00000020) + #define HCHIP_FMCR_M1INFO_SHIFT (0x00000005) + + #define HCHIP_FMCR_M1INFO_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FMCR_M1INFO) + + #define HCHIP_FMCR_M1INFO_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FMCR_M1INFO,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FMCR_M1OVER +\*----------------------------------------------------------------------------*/ + #define HCHIP_FMCR_M1OVER_MASK (0x00000040) + #define HCHIP_FMCR_M1OVER_SHIFT (0x00000006) + + #define HCHIP_FMCR_M1OVER_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FMCR_M1OVER) + + #define HCHIP_FMCR_M1OVER_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FMCR_M1OVER,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FMCR_M1INEX +\*----------------------------------------------------------------------------*/ + #define HCHIP_FMCR_M1INEX_MASK (0x00000080) + #define HCHIP_FMCR_M1INEX_SHIFT (0x00000007) + + #define HCHIP_FMCR_M1INEX_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FMCR_M1INEX) + + #define HCHIP_FMCR_M1INEX_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FMCR_M1INEX,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FMCR_M1UNDER +\*----------------------------------------------------------------------------*/ + #define HCHIP_FMCR_M1UNDER_MASK (0x00000100) + #define HCHIP_FMCR_M1UNDER_SHIFT (0x00000008) + + #define HCHIP_FMCR_M1UNDER_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FMCR_M1UNDER) + + #define HCHIP_FMCR_M1UNDER_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FMCR_M1UNDER,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FMCR_M1RMODE +\*----------------------------------------------------------------------------*/ + #define HCHIP_FMCR_M1RMODE_MASK (0x00000600) + #define HCHIP_FMCR_M1RMODE_SHIFT (0x00000009) + + #define HCHIP_FMCR_M1RMODE_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FMCR_M1RMODE) + + #define HCHIP_FMCR_M1RMODE_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FMCR_M1RMODE,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FMCR_M2NAN1 +\*----------------------------------------------------------------------------*/ + #define HCHIP_FMCR_M2NAN1_MASK (0x00010000) + #define HCHIP_FMCR_M2NAN1_SHIFT (0x00000010) + + #define HCHIP_FMCR_M2NAN1_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FMCR_M2NAN1) + + #define HCHIP_FMCR_M2NAN1_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FMCR_M2NAN1,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FMCR_M2NAN2 +\*----------------------------------------------------------------------------*/ + #define HCHIP_FMCR_M2NAN2_MASK (0x00020000) + #define HCHIP_FMCR_M2NAN2_SHIFT (0x00000011) + + #define HCHIP_FMCR_M2NAN2_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FMCR_M2NAN2) + + #define HCHIP_FMCR_M2NAN2_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FMCR_M2NAN2,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FMCR_M2DEN1 +\*----------------------------------------------------------------------------*/ + #define HCHIP_FMCR_M2DEN1_MASK (0x00040000) + #define HCHIP_FMCR_M2DEN1_SHIFT (0x00000012) + + #define HCHIP_FMCR_M2DEN1_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FMCR_M2DEN1) + + #define HCHIP_FMCR_M2DEN1_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FMCR_M2DEN1,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FMCR_M2DEN2 +\*----------------------------------------------------------------------------*/ + #define HCHIP_FMCR_M2DEN2_MASK (0x00080000) + #define HCHIP_FMCR_M2DEN2_SHIFT (0x00000013) + + #define HCHIP_FMCR_M2DEN2_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FMCR_M2DEN2) + + #define HCHIP_FMCR_M2DEN2_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FMCR_M2DEN2,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FMCR_M2INVAL +\*----------------------------------------------------------------------------*/ + #define HCHIP_FMCR_M2INVAL_MASK (0x00100000) + #define HCHIP_FMCR_M2INVAL_SHIFT (0x00000014) + + #define HCHIP_FMCR_M2INVAL_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FMCR_M2INVAL) + + #define HCHIP_FMCR_M2INVAL_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FMCR_M2INVAL,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FMCR_M2INFO +\*----------------------------------------------------------------------------*/ + #define HCHIP_FMCR_M2INFO_MASK (0x00200000) + #define HCHIP_FMCR_M2INFO_SHIFT (0x00000015) + + #define HCHIP_FMCR_M2INFO_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FMCR_M2INFO) + + #define HCHIP_FMCR_M2INFO_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FMCR_M2INFO,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FMCR_M2OVER +\*----------------------------------------------------------------------------*/ + #define HCHIP_FMCR_M2OVER_MASK (0x00400000) + #define HCHIP_FMCR_M2OVER_SHIFT (0x00000016) + + #define HCHIP_FMCR_M2OVER_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FMCR_M2OVER) + + #define HCHIP_FMCR_M2OVER_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FMCR_M2OVER,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FMCR_M2INEX +\*----------------------------------------------------------------------------*/ + #define HCHIP_FMCR_M2INEX_MASK (0x00800000) + #define HCHIP_FMCR_M2INEX_SHIFT (0x00000017) + + #define HCHIP_FMCR_M2INEX_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FMCR_M2INEX) + + #define HCHIP_FMCR_M2INEX_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FMCR_M2INEX,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FMCR_M2UNDER +\*----------------------------------------------------------------------------*/ + #define HCHIP_FMCR_M2UNDER_MASK (0x01000000) + #define HCHIP_FMCR_M2UNDER_SHIFT (0x00000018) + + #define HCHIP_FMCR_M2UNDER_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FMCR_M2UNDER) + + #define HCHIP_FMCR_M2UNDER_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FMCR_M2UNDER,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FMCR_M2RMODE +\*----------------------------------------------------------------------------*/ + #define HCHIP_FMCR_M2RMODE_MASK (0x06000000) + #define HCHIP_FMCR_M2RMODE_SHIFT (0x00000019) + + #define HCHIP_FMCR_M2RMODE_GET(CrReg) \ + HCRFIELD_GET(CrReg,HCHIP_FMCR_M2RMODE) + + #define HCHIP_FMCR_M2RMODE_SET(CrReg,Val) \ + HCRFIELD_SET(CrReg,HCHIP_FMCR_M2RMODE,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCHIP_FMCR +\*----------------------------------------------------------------------------*/ + #define HCHIP_FMCR_GET(CrReg) HCRREG32_GET(CrReg) + + #define HCHIP_FMCR_SET(CrReg,Val) HCRREG32_SET(CrReg,Val) + + #define HCHIP_FMCR_CFG(CrReg,m1nan1,m1nan2,m1den1,m1den2,m1inval,m1info,\ + m1over,m1inex,m1under,m1rmode,m2nan1,m2nan2,m2den1,m2den2,m2inval,m2info,\ + m2over,m2inex,m2under,m2rmode) CrReg=(UINT32)( \ + HSHIFT_FDIELD(HCHIP_FMCR_M1NAN1, m1nan1) |\ + HSHIFT_FDIELD(HCHIP_FMCR_M1NAN2, m1nan2) |\ + HSHIFT_FDIELD(HCHIP_FMCR_M1DEN1, m1den1) |\ + HSHIFT_FDIELD(HCHIP_FMCR_M1DEN2, m1den2) |\ + HSHIFT_FDIELD(HCHIP_FMCR_M1INVAL,m1inval)|\ + HSHIFT_FDIELD(HCHIP_FMCR_M1INFO, m1info) |\ + HSHIFT_FDIELD(HCHIP_FMCR_M1OVER, m1over) |\ + HSHIFT_FDIELD(HCHIP_FMCR_M1INEX, m1inex) |\ + HSHIFT_FDIELD(HCHIP_FMCR_M1UNDER,m1under)|\ + HSHIFT_FDIELD(HCHIP_FMCR_M1RMODE,m1rmode)|\ + HSHIFT_FDIELD(HCHIP_FMCR_M2NAN1, m2nan1) |\ + HSHIFT_FDIELD(HCHIP_FMCR_M2NAN2, m2nan2) |\ + HSHIFT_FDIELD(HCHIP_FMCR_M2DEN1, m2den1) |\ + HSHIFT_FDIELD(HCHIP_FMCR_M2DEN2, m2den2) |\ + HSHIFT_FDIELD(HCHIP_FMCR_M2INVAL,m2inval)|\ + HSHIFT_FDIELD(HCHIP_FMCR_M2INFO, m2info) |\ + HSHIFT_FDIELD(HCHIP_FMCR_M2OVER, m2over) |\ + HSHIFT_FDIELD(HCHIP_FMCR_M2INEX, m2inex) |\ + HSHIFT_FDIELD(HCHIP_FMCR_M2UNDER,m2under)|\ + HSHIFT_FDIELD(HCHIP_FMCR_M2RMODE,m2rmode) \ + ) +#endif /* FPU_SUPPORT */ + +/******************************************************************************/ + +#endif /* _CHIPHAL_H_ */ +/******************************************************************************\ +* End of chiphal.h +\******************************************************************************/ + + + +/******************************************************************************\ +* Copyright (C) 1999-2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... cachehal.h +* DATE CREATED.. 06/12/1999 +* LAST MODIFIED. 03/08/2000 +* +*------------------------------------------------------------------------------ +* DESCRIPTION: (HAL interface file for the CACHE module) +* +* Registers Covered: +* HCACHE_CCFG - cache configuration register +* HCACHE_L2FBAR - L2 flush base address register +* HCACHE_L2FWC - L2 flush word count register +* HCACHE_L2CBAR - L2 clean base register +* HCACHE_L2CWC - L2 clean word count register +* HCACHE_L1PFBAR - L1P flush base address register +* HCACHE_L1PFWC - L1P flush word count register +* HCACHE_L1DFBAR - L1D flush base address register +* HCACHE_L1DFWC - L1D flush word count register +* HCACHE_L2FLUSH - L2 flush register +* HCACHE_L2CLEAN - L2 clean register +* HCACHE_MAR0 - memory attribute register, region 0 +* HCACHE_MAR1 - memory attribute register, region 1 +* HCACHE_MAR2 - memory attribute register, region 2 +* HCACHE_MAR3 - memory attribute register, region 3 +* HCACHE_MAR4 - memory attribute register, region 4 +* HCACHE_MAR5 - memory attribute register, region 5 +* HCACHE_MAR6 - memory attribute register, region 6 +* HCACHE_MAR7 - memory attribute register, region 7 +* HCACHE_MAR8 - memory attribute register, region 8 +* HCACHE_MAR9 - memory attribute register, region 9 +* HCACHE_MAR10 - memory attribute register, region 10 +* HCACHE_MAR11 - memory attribute register, region 11 +* HCACHE_MAR12 - memory attribute register, region 12 +* HCACHE_MAR13 - memory attribute register, region 13 +* HCACHE_MAR14 - memory attribute register, region 14 +* HCACHE_MAR15 - memory attribute register, region 15 +* +\******************************************************************************/ +#ifndef _CACHEHAL_H_ +#define _CACHEHAL_H_ + +#if (CACHE_SUPPORT) +/*============================================================================*\ +* misc declarations +\*============================================================================*/ + #define HCACHE_BASE_ADDR (HCHIP_PERBASE_ADDR+0x00040000) + +/******************************************************************************\ +* HCACHE_CCFG - cache configuration register +* +* Fields: +* (RW) HCACHE_CCFG_L2MODE +* (RW) HCACHE_CCFG_ID +* (RW) HCACHE_CCFG_IP +* (RW) HCACHE_CCFG_P +* +\******************************************************************************/ + #define HCACHE_CCFG_ADDR (HCACHE_BASE_ADDR+0x0000) + #define HCACHE_CCFG REG32(HCACHE_CCFG_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HCACHE_CCFG_L2MODE +\*----------------------------------------------------------------------------*/ + #define HCACHE_CCFG_L2MODE_MASK (0x00000007) + #define HCACHE_CCFG_L2MODE_SHIFT (0x00000000) + + #define HCACHE_CCFG_L2MODE_GET(RegAddr) \ + HFIELD_GET(RegAddr,HCACHE_CCFG_L2MODE) + + #define HCACHE_CCFG_L2MODE_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HCACHE_CCFG_L2MODE,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCACHE_CCFG_ID +\*----------------------------------------------------------------------------*/ + #define HCACHE_CCFG_ID_MASK (0x00000100) + #define HCACHE_CCFG_ID_SHIFT (0x00000008) + + #define HCACHE_CCFG_ID_GET(RegAddr) \ + HFIELD_GET(RegAddr,HCACHE_CCFG_ID) + + #define HCACHE_CCFG_ID_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HCACHE_CCFG_ID,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCACHE_CCFG_IP +\*----------------------------------------------------------------------------*/ + #define HCACHE_CCFG_IP_MASK (0x00000200) + #define HCACHE_CCFG_IP_SHIFT (0x00000009) + + #define HCACHE_CCFG_IP_GET(RegAddr) \ + HFIELD_GET(RegAddr,HCACHE_CCFG_IP) + + #define HCACHE_CCFG_IP_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HCACHE_CCFG_IP,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCACHE_CCFG_P +\*----------------------------------------------------------------------------*/ + #define HCACHE_CCFG_P_MASK (0x80000000) + #define HCACHE_CCFG_P_SHIFT (0x0000001F) + + #define HCACHE_CCFG_P_GET(RegAddr) \ + HFIELD_GET(RegAddr,HCACHE_CCFG_P) + + #define HCACHE_CCFG_P_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HCACHE_CCFG_P,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCACHE_CCFG +\*----------------------------------------------------------------------------*/ + #define HCACHE_CCFG_GET(RegAddr) HREG32_GET(RegAddr) + #define HCACHE_CCFG_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HCACHE_CCFG_CFG(RegAddr,l2mode,id,ip,p) REG32(RegAddr) = (UINT32)( \ + HFIELD_SHIFT(HCACHE_CCFG_L2MODE,l2mode)| \ + HFIELD_SHIFT(HCACHE_CCFG_ID,id)| \ + HFIELD_SHIFT(HCACHE_CCFG_IP,ip)| \ + HFIELD_SHIFT(HCACHE_CCFG_P,p) \ + ) + +/******************************************************************************\ +* HCACHE_L2FBAR - L2 flush base address register +* +* Fields: +* (RW) HCACHE_L2FBAR_L2FBAR +* +\******************************************************************************/ + #define HCACHE_L2FBAR_ADDR (HCACHE_BASE_ADDR+0x4000) + #define HCACHE_L2FBAR REG32(HCACHE_L2FBAR_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HCACHE_L2FBAR_L2FBAR +\*----------------------------------------------------------------------------*/ + #define HCACHE_L2FBAR_L2FBAR_MASK (0xFFFFFFFF) + #define HCACHE_L2FBAR_L2FBAR_SHIFT (0x00000000) + + #define HCACHE_L2FBAR_L2FBAR_GET(RegAddr) \ + HFIELD_GET(RegAddr,HCACHE_L2FBAR_L2FBAR) + + #define HCACHE_L2FBAR_L2FBAR_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HCACHE_L2FBAR_L2FBAR,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCACHE_L2FBAR +\*----------------------------------------------------------------------------*/ + #define HCACHE_L2FBAR_GET(RegAddr) HREG32_GET(RegAddr) + #define HCACHE_L2FBAR_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HCACHE_L2FBAR_CFG(RegAddr,l2fbar) REG32(RegAddr) = (UINT32)( \ + HFIELD_SHIFT(HCACHE_L2FBAR_L2FBAR,l2fbar) \ + ) + +/******************************************************************************\ +* HCACHE_L2FWC - L2 flush word count register +* +* Fields: +* (RW) HCACHE_L2FWC_L2FWC +* +\******************************************************************************/ + #define HCACHE_L2FWC_ADDR (HCACHE_BASE_ADDR+0x4004) + #define HCACHE_L2FWC REG32(HCACHE_L2FWC_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HCACHE_L2FWC_L2FWC +\*----------------------------------------------------------------------------*/ + #define HCACHE_L2FWC_L2FWC_MASK (0x0000FFFF) + #define HCACHE_L2FWC_L2FWC_SHIFT (0x00000000) + + #define HCACHE_L2FWC_L2FWC_GET(RegAddr) \ + HFIELD_GET(RegAddr,HCACHE_L2FWC_L2FWC) + + #define HCACHE_L2FWC_L2FWC_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HCACHE_L2FWC_L2FWC,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCACHE_L2FWC +\*----------------------------------------------------------------------------*/ + #define HCACHE_L2FWC_GET(RegAddr) HREG32_GET(RegAddr) + #define HCACHE_L2FWC_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HCACHE_L2FWC_CFG(RegAddr,l2fwc) REG32(RegAddr) = (UINT32)( \ + HFIELD_SHIFT(HCACHE_L2FWC_L2FWC,l2fwc) \ + ) + +/******************************************************************************\ +* HCACHE_L2CBAR - L2 clean base register +* +* Fields: +* (RW) HCACHE_L2CBAR_L2CBAR +* +\******************************************************************************/ + #define HCACHE_L2CBAR_ADDR (HCACHE_BASE_ADDR+0x4010) + #define HCACHE_L2CBAR REG32(HCACHE_L2CBAR_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HCACHE_L2CBAR_L2CBAR +\*----------------------------------------------------------------------------*/ + #define HCACHE_L2CBAR_L2CBAR_MASK (0xFFFFFFFF) + #define HCACHE_L2CBAR_L2CBAR_SHIFT (0x00000000) + + #define HCACHE_L2CBAR_L2CBAR_GET(RegAddr) \ + HFIELD_GET(RegAddr,HCACHE_L2CBAR_L2CBAR) + + #define HCACHE_L2CBAR_L2CBAR_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HCACHE_L2CBAR_L2CBAR,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCACHE_L2CBAR +\*----------------------------------------------------------------------------*/ + #define HCACHE_L2CBAR_GET(RegAddr) HREG32_GET(RegAddr) + #define HCACHE_L2CBAR_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HCACHE_L2CBAR_CFG(RegAddr,l2cbar) REG32(RegAddr) = (UINT32)( \ + HFIELD_SHIFT(HCACHE_L2CBAR_L2CBAR,l2cbar) \ + ) + +/******************************************************************************\ +* HCACHE_L2CWC - L2 clean word count register +* +* Fields: +* (RW) HCACHE_L2CWC_L2CWC +* +\******************************************************************************/ + #define HCACHE_L2CWC_ADDR (HCACHE_BASE_ADDR+0x4014) + #define HCACHE_L2CWC REG32(HCACHE_L2CWC_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HCACHE_L2CWC_L2CWC +\*----------------------------------------------------------------------------*/ + #define HCACHE_L2CWC_L2CWC_MASK (0x0000FFFF) + #define HCACHE_L2CWC_L2CWC_SHIFT (0x00000000) + + #define HCACHE_L2CWC_L2CWC_GET(RegAddr) \ + HFIELD_GET(RegAddr,HCACHE_L2CWC_L2CWC) + + #define HCACHE_L2CWC_L2CWC_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HCACHE_L2CWC_L2CWC,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCACHE_L2CWC +\*----------------------------------------------------------------------------*/ + #define HCACHE_L2CWC_GET(RegAddr) HREG32_GET(RegAddr) + #define HCACHE_L2CWC_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HCACHE_L2CWC_CFG(RegAddr,l2cwc) REG32(RegAddr) = (UINT32)( \ + HFIELD_SHIFT(HCACHE_L2CWC_L2CWC,l2cwc) \ + ) + +/******************************************************************************\ +* HCACHE_L1PFBAR - L1P flush base address register +* +* Fields: +* (RW) HCACHE_L1PFBAR_L1PFBAR +* +\******************************************************************************/ + #define HCACHE_L1PFBAR_ADDR (HCACHE_BASE_ADDR+0x4020) + #define HCACHE_L1PFBAR REG32(HCACHE_L1PFBAR_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HCACHE_L1PFBAR_L1PFBAR +\*----------------------------------------------------------------------------*/ + #define HCACHE_L1PFBAR_L1PFBAR_MASK (0xFFFFFFFF) + #define HCACHE_L1PFBAR_L1PFBAR_SHIFT (0x00000000) + + #define HCACHE_L1PFBAR_L1PFBAR_GET(RegAddr) \ + HFIELD_GET(RegAddr,HCACHE_L1PFBAR_L1PFBAR) + + #define HCACHE_L1PFBAR_L1PFBAR_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HCACHE_L1PFBAR_L1PFBAR,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCACHE_L1PFBAR +\*----------------------------------------------------------------------------*/ + #define HCACHE_L1PFBAR_GET(RegAddr) HREG32_GET(RegAddr) + #define HCACHE_L1PFBAR_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HCACHE_L1PFBAR_CFG(RegAddr,l1pfbar) REG32(RegAddr) = (UINT32)( \ + HFIELD_SHIFT(HCACHE_L1PFBAR_L1PFBAR,l1pfbar) \ + ) + +/******************************************************************************\ +* HCACHE_L1PFWC - L1P flush word count register +* +* Fields: +* (RW) HCACHE_L1PFWC_L1PFWC +* +\******************************************************************************/ + #define HCACHE_L1PFWC_ADDR (HCACHE_BASE_ADDR+0x4024) + #define HCACHE_L1PFWC REG32(HCACHE_L1PFWC_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HCACHE_L1PFWC_L1PFWC +\*----------------------------------------------------------------------------*/ + #define HCACHE_L1PFWC_L1PFWC_MASK (0x0000FFFF) + #define HCACHE_L1PFWC_L1PFWC_SHIFT (0x00000000) + + #define HCACHE_L1PFWC_L1PFWC_GET(RegAddr) \ + HFIELD_GET(RegAddr,HCACHE_L1PFWC_L1PFWC) + + #define HCACHE_L1PFWC_L1PFWC_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HCACHE_L1PFWC_L1PFWC,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCACHE_L1PFWC +\*----------------------------------------------------------------------------*/ + #define HCACHE_L1PFWC_GET(RegAddr) HREG32_GET(RegAddr) + #define HCACHE_L1PFWC_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HCACHE_L1PFWC_CFG(RegAddr,l1pfwc) REG32(RegAddr) = (UINT32)( \ + HFIELD_SHIFT(HCACHE_L1PFWC_L1PFWC,l1pfwc) \ + ) + +/******************************************************************************\ +* HCACHE_L1DFBAR - L1D flush base address register +* +* Fields: +* (RW) HCACHE_L1DFBAR_L1DFBAR +* +\******************************************************************************/ + #define HCACHE_L1DFBAR_ADDR (HCACHE_BASE_ADDR+0x4030) + #define HCACHE_L1DFBAR REG32(HCACHE_L1DFBAR_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HCACHE_L1DFBAR_L1DFBAR +\*----------------------------------------------------------------------------*/ + #define HCACHE_L1DFBAR_L1DFBAR_MASK (0xFFFFFFFF) + #define HCACHE_L1DFBAR_L1DFBAR_SHIFT (0x00000000) + + #define HCACHE_L1DFBAR_L1DFBAR_GET(RegAddr) \ + HFIELD_GET(RegAddr,HCACHE_L1DFBAR_L1DFBAR) + + #define HCACHE_L1DFBAR_L1DFBAR_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HCACHE_L1DFBAR_L1DFBAR,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCACHE_L1DFBAR +\*----------------------------------------------------------------------------*/ + #define HCACHE_L1DFBAR_GET(RegAddr) HREG32_GET(RegAddr) + #define HCACHE_L1DFBAR_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HCACHE_L1DFBAR_CFG(RegAddr,l1dfbar) REG32(RegAddr) = (UINT32)( \ + HFIELD_SHIFT(HCACHE_L1DFBAR_L1DFBAR,l1dfbar) \ + ) + +/******************************************************************************\ +* HCACHE_L1DFWC - L1D flush word count register +* +* Fields: +* (RW) HCACHE_L1DFWC_L1DFWC +* +\******************************************************************************/ + #define HCACHE_L1DFWC_ADDR (HCACHE_BASE_ADDR+0x4034) + #define HCACHE_L1DFWC REG32(HCACHE_L1DFWC_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HCACHE_L1DFWC_L1DFWC +\*----------------------------------------------------------------------------*/ + #define HCACHE_L1DFWC_L1DFWC_MASK (0x0000FFFF) + #define HCACHE_L1DFWC_L1DFWC_SHIFT (0x00000000) + + #define HCACHE_L1DFWC_L1DFWC_GET(RegAddr) \ + HFIELD_GET(RegAddr,HCACHE_L1DFWC_L1DFWC) + + #define HCACHE_L1DFWC_L1DFWC_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HCACHE_L1DFWC_L1DFWC,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCACHE_L1DFWC +\*----------------------------------------------------------------------------*/ + #define HCACHE_L1DFWC_GET(RegAddr) HREG32_GET(RegAddr) + #define HCACHE_L1DFWC_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HCACHE_L1DFWC_CFG(RegAddr,l1dfwc) REG32(RegAddr) = (UINT32)( \ + HFIELD_SHIFT(HCACHE_L1DFWC_L1DFWC,l1dfwc) \ + ) + +/******************************************************************************\ +* HCACHE_L2FLUSH - L2 flush register +* +* Fields: +* (RW) HCACHE_L2FLUSH_F +* +\******************************************************************************/ + #define HCACHE_L2FLUSH_ADDR (HCACHE_BASE_ADDR+0x5000) + #define HCACHE_L2FLUSH REG32(HCACHE_L2FLUSH_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HCACHE_L2FLUSH_F +\*----------------------------------------------------------------------------*/ + #define HCACHE_L2FLUSH_F_MASK (0x00000001) + #define HCACHE_L2FLUSH_F_SHIFT (0x00000000) + + #define HCACHE_L2FLUSH_F_GET(RegAddr) \ + HFIELD_GET(RegAddr,HCACHE_L2FLUSH_F) + + #define HCACHE_L2FLUSH_F_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HCACHE_L2FLUSH_F,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCACHE_L2FLUSH +\*----------------------------------------------------------------------------*/ + #define HCACHE_L2FLUSH_GET(RegAddr) HREG32_GET(RegAddr) + #define HCACHE_L2FLUSH_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HCACHE_L2FLUSH_CFG(RegAddr,f) REG32(RegAddr) = (UINT32)( \ + HFIELD_SHIFT(HCACHE_L2FLUSH_F,f) \ + ) + +/******************************************************************************\ +* HCACHE_L2CLEAN - L2 clean register +* +* Fields: +* (RW) HCACHE_L2CLEAN_C +* +\******************************************************************************/ + #define HCACHE_L2CLEAN_ADDR (HCACHE_BASE_ADDR+0x5004) + #define HCACHE_L2CLEAN REG32(HCACHE_L2CLEAN_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HCACHE_L2CLEAN_C +\*----------------------------------------------------------------------------*/ + #define HCACHE_L2CLEAN_C_MASK (0x00000001) + #define HCACHE_L2CLEAN_C_SHIFT (0x00000000) + + #define HCACHE_L2CLEAN_C_GET(RegAddr) \ + HFIELD_GET(RegAddr,HCACHE_L2CLEAN_C) + + #define HCACHE_L2CLEAN_C_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HCACHE_L2CLEAN_C,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCACHE_L2CLEAN +\*----------------------------------------------------------------------------*/ + #define HCACHE_L2CLEAN_GET(RegAddr) HREG32_GET(RegAddr) + #define HCACHE_L2CLEAN_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HCACHE_L2CLEAN_CFG(RegAddr,c) REG32(RegAddr) = (UINT32)( \ + HFIELD_SHIFT(HCACHE_L2CLEAN_C,c) \ + ) + +/******************************************************************************\ +* HCACHE_MAR0 - memory attribute register 0 (16M) 0x80000000->0x80FFFFFF +* HCACHE_MAR1 - memory attribute register 1 (16M) 0x81000000->0x81FFFFFF +* HCACHE_MAR2 - memory attribute register 2 (16M) 0x82000000->0x82FFFFFF +* HCACHE_MAR3 - memory attribute register 3 (16M) 0x83000000->0x83FFFFFF +* HCACHE_MAR4 - memory attribute register 4 (16M) 0x90000000->0x90FFFFFF +* HCACHE_MAR5 - memory attribute register 5 (16M) 0x91000000->0x91FFFFFF +* HCACHE_MAR6 - memory attribute register 6 (16M) 0x92000000->0x92FFFFFF +* HCACHE_MAR7 - memory attribute register 7 (16M) 0x93000000->0x93FFFFFF +* HCACHE_MAR8 - memory attribute register 8 (16M) 0xA0000000->0xA0FFFFFF +* HCACHE_MAR9 - memory attribute register 9 (16M) 0xA1000000->0xA1FFFFFF +* HCACHE_MAR10 - memory attribute register 10 (16M) 0xA2000000->0xA2FFFFFF +* HCACHE_MAR11 - memory attribute register 11 (16M) 0xA3000000->0xA3FFFFFF +* HCACHE_MAR12 - memory attribute register 12 (16M) 0xB0000000->0xB0FFFFFF +* HCACHE_MAR13 - memory attribute register 13 (16M) 0xB1000000->0xB1FFFFFF +* HCACHE_MAR14 - memory attribute register 14 (16M) 0xB2000000->0xB2FFFFFF +* HCACHE_MAR15 - memory attribute register 15 (16M) 0xB3000000->0xB3FFFFFF +* +* Fields: +* (RW) HCACHE_MAR_CE +* +\******************************************************************************/ + #define HCACHE_MAR0_ADDR (HCACHE_BASE_ADDR+0x8200) + #define HCACHE_MAR1_ADDR (HCACHE_BASE_ADDR+0x8204) + #define HCACHE_MAR2_ADDR (HCACHE_BASE_ADDR+0x8208) + #define HCACHE_MAR3_ADDR (HCACHE_BASE_ADDR+0x820C) + #define HCACHE_MAR4_ADDR (HCACHE_BASE_ADDR+0x8240) + #define HCACHE_MAR5_ADDR (HCACHE_BASE_ADDR+0x8244) + #define HCACHE_MAR6_ADDR (HCACHE_BASE_ADDR+0x8248) + #define HCACHE_MAR7_ADDR (HCACHE_BASE_ADDR+0x824C) + #define HCACHE_MAR8_ADDR (HCACHE_BASE_ADDR+0x8280) + #define HCACHE_MAR9_ADDR (HCACHE_BASE_ADDR+0x8284) + #define HCACHE_MAR10_ADDR (HCACHE_BASE_ADDR+0x8288) + #define HCACHE_MAR11_ADDR (HCACHE_BASE_ADDR+0x828C) + #define HCACHE_MAR12_ADDR (HCACHE_BASE_ADDR+0x82C0) + #define HCACHE_MAR13_ADDR (HCACHE_BASE_ADDR+0x82C4) + #define HCACHE_MAR14_ADDR (HCACHE_BASE_ADDR+0x82C8) + #define HCACHE_MAR15_ADDR (HCACHE_BASE_ADDR+0x82CC) + + #define HCACHE_MAR0 REG32(HCACHE_MAR0_ADDR) + #define HCACHE_MAR1 REG32(HCACHE_MAR1_ADDR) + #define HCACHE_MAR2 REG32(HCACHE_MAR2_ADDR) + #define HCACHE_MAR3 REG32(HCACHE_MAR3_ADDR) + #define HCACHE_MAR4 REG32(HCACHE_MAR4_ADDR) + #define HCACHE_MAR5 REG32(HCACHE_MAR5_ADDR) + #define HCACHE_MAR6 REG32(HCACHE_MAR6_ADDR) + #define HCACHE_MAR7 REG32(HCACHE_MAR7_ADDR) + #define HCACHE_MAR8 REG32(HCACHE_MAR8_ADDR) + #define HCACHE_MAR9 REG32(HCACHE_MAR9_ADDR) + #define HCACHE_MAR10 REG32(HCACHE_MAR10_ADDR) + #define HCACHE_MAR11 REG32(HCACHE_MAR11_ADDR) + #define HCACHE_MAR12 REG32(HCACHE_MAR12_ADDR) + #define HCACHE_MAR13 REG32(HCACHE_MAR13_ADDR) + #define HCACHE_MAR14 REG32(HCACHE_MAR14_ADDR) + #define HCACHE_MAR15 REG32(HCACHE_MAR15_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HCACHE_MAR_CE +\*----------------------------------------------------------------------------*/ + #define HCACHE_MAR_CE_MASK (0x00000001) + #define HCACHE_MAR_CE_SHIFT (0x00000000) + + #define HCACHE_MAR_CE_GET(RegAddr) \ + HFIELD_GET(RegAddr,HCACHE_MAR_CE) + + #define HCACHE_MAR_CE_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HCACHE_MAR_CE,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HCACHE_MAR +\*----------------------------------------------------------------------------*/ + #define HCACHE_MAR_GET(RegAddr) HREG32_GET(RegAddr) + #define HCACHE_MAR_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HCACHE_MAR_CFG(RegAddr,ce) REG32(RegAddr) = (UINT32)( \ + HFIELD_SHIFT(HCACHE_MAR_CE,ce) \ + ) + +/******************************************************************************/ + +#endif /* CACHE_SUPPORT */ +#endif /* _CACHEHAL_H_ */ +/******************************************************************************\ +* End of cachehal.h +\******************************************************************************/ + +/******************************************************************************\ +* Copyright (C) 1999-2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... dmahal.h +* DATE CREATED.. 03/12/1999 +* LAST MODIFIED. 03/08/2000 +* +*------------------------------------------------------------------------------ +* DESCRIPTION: (HAL interface file for the DMA module) +* +* Registers Covered: +* HDMA_AUXCTL_ADDR - auxiliary control register +* HDMA_PRICTL0_ADDR - primary control register +* HDMA_PRICTL1_ADDR - primary control register +* HDMA_PRICTL2_ADDR - primary control register +* HDMA_PRICTL3_ADDR - primary control register +* HDMA_SECCTL0_ADDR - seconday control register +* HDMA_SECCTL1_ADDR - seconday control register +* HDMA_SECCTL2_ADDR - seconday control register +* HDMA_SECCTL3_ADDR - seconday control register +* HDMA_SRC0_ADDR - source address register +* HDMA_SRC1_ADDR - source address register +* HDMA_SRC2_ADDR - source address register +* HDMA_SRC3_ADDR - source address register +* HDMA_DST0_ADDR - destination address register +* HDMA_DST1_ADDR - destination address register +* HDMA_DST2_ADDR - destination address register +* HDMA_DST3_ADDR - destination address register +* HDMA_XFRCNT0_ADDR - transfer count register +* HDMA_XFRCNT1_ADDR - transfer count register +* HDMA_XFRCNT2_ADDR - transfer count register +* HDMA_XFRCNT3_ADDR - transfer count register +* HDMA_GBLCNTA_ADDR - global count reload register +* HDMA_GBLCNTB_ADDR - global count reload register +* HDMA_GBLIDXA_ADDR - global index register +* HDMA_GBLIDXB_ADDR - global index register +* HDMA_GBLADDRA_ADDR - global address register +* HDMA_GBLADDRB_ADDR - global address register +* HDMA_GBLADDRC_ADDR - global address register +* HDMA_GBLADDRD_ADDR - global address register +* +* +\******************************************************************************/ +#ifndef _DMAHAL_H_ +#define _DMAHAL_H_ + +#if (DMA_SUPPORT) +/*============================================================================*\ +* misc declarations +\*============================================================================*/ + #define HDMA_BASE_ADDR (HCHIP_PERBASE_ADDR+0x00040000) + + #define HDMA_CHA_CNT (4) + #define HDMA_GBLADDR_CNT (4) + #define HDMA_GBLIDX_CNT (2) + #define HDMA_GBLCNT_CNT (2) + +/******************************************************************************\ +* HDMA_AUXCTL_ADDR - auxiliary control register +* +* Fields: +* (RW) HDMA_AUXCTL_CHPRI +* (RW) HDMA_AUXCTL_AUXPRI +* +\******************************************************************************/ + #define HDMA_AUXCTL_ADDR (HDMA_BASE_ADDR+0x0070) + #define HDMA_AUXCTL REG32(HDMA_AUXCTL_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_AUXCTL_CHPRI +\*----------------------------------------------------------------------------*/ + #define HDMA_AUXCTL_CHPRI_MASK (0x0000000F) + #define HDMA_AUXCTL_CHPRI_SHIFT (0x00000000) + + #define HDMA_AUXCTL_CHPRI_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_AUXCTL_CHPRI) + + #define HDMA_AUXCTL_CHPRI_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_AUXCTL_CHPRI,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_AUXCTL_AUXPRI +\*----------------------------------------------------------------------------*/ + #define HDMA_AUXCTL_AUXPRI_MASK (0x00000010) + #define HDMA_AUXCTL_AUXPRI_SHIFT (0x00000004) + + #define HDMA_AUXCTL_AUXPRI_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_AUXCTL_AUXPRI) + + #define HDMA_AUXCTL_AUXPRI_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_AUXCTL_AUXPRI,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_AUXCTL +\*----------------------------------------------------------------------------*/ + #define HDMA_AUXCTL_GET(RegAddr) HREG32_GET(RegAddr) + #define HDMA_AUXCTL_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HDMA_AUXCTL_CFG(RegAddr,chpri,auxpri) REG32(RegAddr)=(UINT32)(\ + HFIELD_SHIFT(HDMA_AUXCTL_CHPRI,chpri)|\ + HFIELD_SHIFT(HDMA_AUXCTL_AUXPRI,auxpri)\ + ) + +/******************************************************************************\ +* HDMA_PRICTL0_ADDR - primary control register +* HDMA_PRICTL1_ADDR - primary control register +* HDMA_PRICTL2_ADDR - primary control register +* HDMA_PRICTL3_ADDR - primary control register +* +* Fields: +* (RW) HDMA_PRICTL_START +* (R) HDMA_PRICTL_STATUS +* (RW) HDMA_PRICTL_SRCDIR +* (RW) HDMA_PRICTL_DSTDIR +* (RW) HDMA_PRICTL_ESIZE +* (RW) HDMA_PRICTL_SPLIT +* (RW) HDMA_PRICTL_CNTRLD +* (RW) HDMA_PRICTL_INDEX +* (RW) HDMA_PRICTL_RSYNC +* (RW) HDMA_PRICTL_WSYNC +* (RW) HDMA_PRICTL_PRI +* (RW) HDMA_PRICTL_TCINT +* (RW) HDMA_PRICTL_FS +* (RW) HDMA_PRICTL_EMOD +* (RW) HDMA_PRICTL_SRCRLD +* (RW) HDMA_PRICTL_DSTRLD +* +\******************************************************************************/ + #define HDMA_PRICTL0_ADDR (HDMA_BASE_ADDR+0x0000) + #define HDMA_PRICTL1_ADDR (HDMA_BASE_ADDR+0x0040) + #define HDMA_PRICTL2_ADDR (HDMA_BASE_ADDR+0x0004) + #define HDMA_PRICTL3_ADDR (HDMA_BASE_ADDR+0x0044) + + #define HDMA_PRICTL0 REG32(HDMA_PRICTL0_ADDR) + #define HDMA_PRICTL1 REG32(HDMA_PRICTL1_ADDR) + #define HDMA_PRICTL2 REG32(HDMA_PRICTL2_ADDR) + #define HDMA_PRICTL3 REG32(HDMA_PRICTL3_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_PRICTL_START +\*----------------------------------------------------------------------------*/ + #define HDMA_PRICTL_START_MASK (0x00000003) + #define HDMA_PRICTL_START_SHIFT (0x00000000) + + #define HDMA_PRICTL_START_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_PRICTL_START) + + #define HDMA_PRICTL_START_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_PRICTL_START,Val) + +/*----------------------------------------------------------------------------*\ +* (R) HDMA_PRICTL_STATUS +\*----------------------------------------------------------------------------*/ + #define HDMA_PRICTL_STATUS_MASK (0x0000000C) + #define HDMA_PRICTL_STATUS_SHIFT (0x00000002) + + #define HDMA_PRICTL_STATUS_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_PRICTL_STATUS) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_PRICTL_SRCDIR +\*----------------------------------------------------------------------------*/ + #define HDMA_PRICTL_SRCDIR_MASK (0x00000030) + #define HDMA_PRICTL_SRCDIR_SHIFT (0x00000004) + + #define HDMA_PRICTL_SRCDIR_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_PRICTL_SRCDIR) + + #define HDMA_PRICTL_SRCDIR_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_PRICTL_SRCDIR,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_PRICTL_DSTDIR +\*----------------------------------------------------------------------------*/ + #define HDMA_PRICTL_DSTDIR_MASK (0x000000C0) + #define HDMA_PRICTL_DSTDIR_SHIFT (0x00000006) + + #define HDMA_PRICTL_DSTDIR_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_PRICTL_DSTDIR) + + #define HDMA_PRICTL_DSTDIR_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_PRICTL_DSTDIR,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_PRICTL_ESIZE +\*----------------------------------------------------------------------------*/ + #define HDMA_PRICTL_ESIZE_MASK (0x00000300) + #define HDMA_PRICTL_ESIZE_SHIFT (0x00000008) + + #define HDMA_PRICTL_ESIZE_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_PRICTL_ESIZE) + + #define HDMA_PRICTL_ESIZE_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_PRICTL_ESIZE,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_PRICTL_SPLIT +\*----------------------------------------------------------------------------*/ + #define HDMA_PRICTL_SPLIT_MASK (0x00000C00) + #define HDMA_PRICTL_SPLIT_SHIFT (0x0000000A) + + #define HDMA_PRICTL_SPLIT_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_PRICTL_SPLIT) + + #define HDMA_PRICTL_SPLIT_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_PRICTL_SPLIT,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_PRICTL_CNTRLD +\*----------------------------------------------------------------------------*/ + #define HDMA_PRICTL_CNTRLD_MASK (0x00001000) + #define HDMA_PRICTL_CNTRLD_SHIFT (0x0000000C) + + #define HDMA_PRICTL_CNTRLD_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_PRICTL_CNTRLD) + + #define HDMA_PRICTL_CNTRLD_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_PRICTL_CNTRLD,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_PRICTL_INDEX +\*----------------------------------------------------------------------------*/ + #define HDMA_PRICTL_INDEX_MASK (0x00002000) + #define HDMA_PRICTL_INDEX_SHIFT (0x0000000D) + + #define HDMA_PRICTL_INDEX_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_PRICTL_INDEX) + + #define HDMA_PRICTL_INDEX_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_PRICTL_INDEX,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_PRICTL_RSYNC +\*----------------------------------------------------------------------------*/ + #define HDMA_PRICTL_RSYNC_MASK (0x0007C000) + #define HDMA_PRICTL_RSYNC_SHIFT (0x0000000E) + + #define HDMA_PRICTL_RSYNC_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_PRICTL_RSYNC) + + #define HDMA_PRICTL_RSYNC_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_PRICTL_RSYNC,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_PRICTL_WSYNC +\*----------------------------------------------------------------------------*/ + #define HDMA_PRICTL_WSYNC_MASK (0x00F10000) + #define HDMA_PRICTL_WSYNC_SHIFT (0x00000013) + + #define HDMA_PRICTL_WSYNC_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_PRICTL_WSYNC) + + #define HDMA_PRICTL_WSYNC_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_PRICTL_WSYNC,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_PRICTL_PRI +\*----------------------------------------------------------------------------*/ + #define HDMA_PRICTL_PRI_MASK (0x01000000) + #define HDMA_PRICTL_PRI_SHIFT (0x00000018) + + #define HDMA_PRICTL_PRI_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_PRICTL_PRI) + + #define HDMA_PRICTL_PRI_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_PRICTL_PRI,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_PRICTL_TCINT +\*----------------------------------------------------------------------------*/ + #define HDMA_PRICTL_TCINT_MASK (0x02000000) + #define HDMA_PRICTL_TCINT_SHIFT (0x00000019) + + #define HDMA_PRICTL_TCINT_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_PRICTL_TCINT) + + #define HDMA_PRICTL_TCINT_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_PRICTL_TCINT,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_PRICTL_FS +\*----------------------------------------------------------------------------*/ + #define HDMA_PRICTL_FS_MASK (0x04000000) + #define HDMA_PRICTL_FS_SHIFT (0x0000001A) + + #define HDMA_PRICTL_FS_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_PRICTL_FS) + + #define HDMA_PRICTL_FS_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_PRICTL_FS,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_PRICTL_EMOD +\*----------------------------------------------------------------------------*/ + #define HDMA_PRICTL_EMOD_MASK (0x08000000) + #define HDMA_PRICTL_EMOD_SHIFT (0x0000001B) + + #define HDMA_PRICTL_EMOD_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_PRICTL_EMOD) + + #define HDMA_PRICTL_EMOD_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_PRICTL_EMOD,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_PRICTL_SRCRLD +\*----------------------------------------------------------------------------*/ + #define HDMA_PRICTL_SRCRLD_MASK (0x30000000) + #define HDMA_PRICTL_SRCRLD_SHIFT (0x0000001C) + + #define HDMA_PRICTL_SRCRLD_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_PRICTL_SRCRLD) + + #define HDMA_PRICTL_SRCRLD_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_PRICTL_SRCRLD,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_PRICTL_DSTRLD +\*----------------------------------------------------------------------------*/ + #define HDMA_PRICTL_DSTRLD_MASK (0xC0000000) + #define HDMA_PRICTL_DSTRLD_SHIFT (0x0000001E) + + #define HDMA_PRICTL_DSTRLD_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_PRICTL_DSTRLD) + + #define HDMA_PRICTL_DSTRLD_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_PRICTL_DSTRLD,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_PRICTL +\*----------------------------------------------------------------------------*/ + #define HDMA_PRICTL_GET(RegAddr) HREG32_GET(RegAddr) + #define HDMA_PRICTL_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HDMA_PRICTL_CFG(RegAddr,start,srcdir,dstdir,esize,split,cntrld,\ + index,rsync,wsync,pri,tcint,fs,emod,srcrld,dstrld) \ + REG32(RegAddr)=(UINT32)(\ + HFIELD_SHIFT(HDMA_PRICTL_START,start)|\ + HFIELD_SHIFT(HDMA_PRICTL_SRCDIR,srcdir)|\ + HFIELD_SHIFT(HDMA_PRICTL_DSTDIR,dstdir)|\ + HFIELD_SHIFT(HDMA_PRICTL_ESIZE,esize)|\ + HFIELD_SHIFT(HDMA_PRICTL_SPLIT,split)|\ + HFIELD_SHIFT(HDMA_PRICTL_CNTRLD,cntrld)|\ + HFIELD_SHIFT(HDMA_PRICTL_INDEX,index)|\ + HFIELD_SHIFT(HDMA_PRICTL_RSYNC,rsync)|\ + HFIELD_SHIFT(HDMA_PRICTL_WSYNC,wsync)|\ + HFIELD_SHIFT(HDMA_PRICTL_PRI,pri)|\ + HFIELD_SHIFT(HDMA_PRICTL_TCINT,tcint)|\ + HFIELD_SHIFT(HDMA_PRICTL_FS,fs)|\ + HFIELD_SHIFT(HDMA_PRICTL_EMOD,emod)|\ + HFIELD_SHIFT(HDMA_PRICTL_SRCRLD,srcrld)|\ + HFIELD_SHIFT(HDMA_PRICTL_DSTRLD,dstrld)\ + ) + +/******************************************************************************\ +* HDMA_SECCTL0_ADDR - seconday control register +* HDMA_SECCTL1_ADDR - seconday control register +* HDMA_SECCTL2_ADDR - seconday control register +* HDMA_SECCTL3_ADDR - seconday control register +* +* Fields: +* (RW) HDMA_SECCTL_SXCOND +* (RW) HDMA_SECCTL_SXIE +* (RW) HDMA_SECCTL_FRAMECOND +* (RW) HDMA_SECCTL_FRAMEIE +* (RW) HDMA_SECCTL_LASTCOND +* (RW) HDMA_SECCTL_LASTIE +* (RW) HDMA_SECCTL_BLOCKCOND +* (RW) HDMA_SECCTL_BLOCKIE +* (RW) HDMA_SECCTL_RDROPCOND +* (RW) HDMA_SECCTL_RDROPIE +* (RW) HDMA_SECCTL_WDROPCOND +* (RW) HDMA_SECCTL_WDROPIE +* (RW) HDMA_SECCTL_RSYNCSTAT +* (RW) HDMA_SECCTL_RSYNCCLR +* (RW) HDMA_SECCTL_WSYNCSTAT +* (RW) HDMA_SECCTL_WSYNCCLR +* (RW) HDMA_SECCTL_DMACEN +* (RW) HDMA_SECCTL_FSIG (1) +* (RW) HDMA_SECCTL_RSPOL (1) +* (RW) HDMA_SECCTL_WSPOL (1) +* +* (1) only on 6202 or 6203 devices +* +\******************************************************************************/ + #define HDMA_SECCTL0_ADDR (HDMA_BASE_ADDR+0x0008) + #define HDMA_SECCTL1_ADDR (HDMA_BASE_ADDR+0x0048) + #define HDMA_SECCTL2_ADDR (HDMA_BASE_ADDR+0x000C) + #define HDMA_SECCTL3_ADDR (HDMA_BASE_ADDR+0x004C) + + #define HDMA_SECCTL0 REG32(HDMA_SECCTL0_ADDR) + #define HDMA_SECCTL1 REG32(HDMA_SECCTL1_ADDR) + #define HDMA_SECCTL2 REG32(HDMA_SECCTL2_ADDR) + #define HDMA_SECCTL3 REG32(HDMA_SECCTL3_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_SECCTL_SXCOND +\*----------------------------------------------------------------------------*/ + #define HDMA_SECCTL_SXCOND_MASK (0x00000001) + #define HDMA_SECCTL_SXCOND_SHIFT (0x00000000) + + #define HDMA_SECCTL_SXCOND_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_SECCTL_SXCOND) + + #define HDMA_SECCTL_SXCOND_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_SECCTL_SXCOND,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_SECCTL_SXIE +\*----------------------------------------------------------------------------*/ + #define HDMA_SECCTL_SXIE_MASK (0x00000002) + #define HDMA_SECCTL_SXIE_SHIFT (0x00000001) + + #define HDMA_SECCTL_SXIE_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_SECCTL_SXIE) + + #define HDMA_SECCTL_SXIE_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_SECCTL_SXIE,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_SECCTL_FRAMECOND +\*----------------------------------------------------------------------------*/ + #define HDMA_SECCTL_FRAMECOND_MASK (0x00000004) + #define HDMA_SECCTL_FRAMECOND_SHIFT (0x00000002) + + #define HDMA_SECCTL_FRAMECOND_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_SECCTL_FRAMECOND) + + #define HDMA_SECCTL_FRAMECOND_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_SECCTL_FRAMECOND,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_SECCTL_FRAMEIE +\*----------------------------------------------------------------------------*/ + #define HDMA_SECCTL_FRAMEIE_MASK (0x00000008) + #define HDMA_SECCTL_FRAMEIE_SHIFT (0x00000003) + + #define HDMA_SECCTL_FRAMEIE_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_SECCTL_FRAMEIE) + + #define HDMA_SECCTL_FRAMEIE_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_SECCTL_FRAMEIE,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_SECCTL_LASTCOND +\*----------------------------------------------------------------------------*/ + #define HDMA_SECCTL_LASTCOND_MASK (0x00000010) + #define HDMA_SECCTL_LASTCOND_SHIFT (0x00000004) + + #define HDMA_SECCTL_LASTCOND_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_SECCTL_LASTCOND) + + #define HDMA_SECCTL_LASTCOND_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_SECCTL_LASTCOND,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_SECCTL_LASTIE +\*----------------------------------------------------------------------------*/ + #define HDMA_SECCTL_LASTIE_MASK (0x00000020) + #define HDMA_SECCTL_LASTIE_SHIFT (0x00000005) + + #define HDMA_SECCTL_LASTIE_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_SECCTL_LASTIE) + + #define HDMA_SECCTL_LASTIE_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_SECCTL_LASTIE,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_SECCTL_BLOCKCOND +\*----------------------------------------------------------------------------*/ + #define HDMA_SECCTL_BLOCKCOND_MASK (0x00000040) + #define HDMA_SECCTL_BLOCKCOND_SHIFT (0x00000006) + + #define HDMA_SECCTL_BLOCKCOND_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_SECCTL_BLOCKCOND) + + #define HDMA_SECCTL_BLOCKCOND_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_SECCTL_BLOCKCOND,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_SECCTL_BLOCKIE +\*----------------------------------------------------------------------------*/ + #define HDMA_SECCTL_BLOCKIE_MASK (0x00000080) + #define HDMA_SECCTL_BLOCKIE_SHIFT (0x00000007) + + #define HDMA_SECCTL_BLOCKIE_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_SECCTL_BLOCKIE) + + #define HDMA_SECCTL_BLOCKIE_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_SECCTL_BLOCKIE,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_SECCTL_RDROPCOND +\*----------------------------------------------------------------------------*/ + #define HDMA_SECCTL_RDROPCOND_MASK (0x00000100) + #define HDMA_SECCTL_RDROPCOND_SHIFT (0x00000008) + + #define HDMA_SECCTL_RDROPCOND_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_SECCTL_RDROPCOND) + + #define HDMA_SECCTL_RDROPCOND_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_SECCTL_RDROPCOND,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_SECCTL_RDROPIE +\*----------------------------------------------------------------------------*/ + #define HDMA_SECCTL_RDROPIE_MASK (0x00000200) + #define HDMA_SECCTL_RDROPIE_SHIFT (0x00000009) + + #define HDMA_SECCTL_RDROPIE_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_SECCTL_RDROPIE) + + #define HDMA_SECCTL_RDROPIE_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_SECCTL_RDROPIE,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_SECCTL_WDROPCOND +\*----------------------------------------------------------------------------*/ + #define HDMA_SECCTL_WDROPCOND_MASK (0x00000400) + #define HDMA_SECCTL_WDROPCOND_SHIFT (0x0000000A) + + #define HDMA_SECCTL_WDROPCOND_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_SECCTL_WDROPCOND) + + #define HDMA_SECCTL_WDROPCOND_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_SECCTL_WDROPCOND,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_SECCTL_WDROPIE +\*----------------------------------------------------------------------------*/ + #define HDMA_SECCTL_WDROPIE_MASK (0x00000800) + #define HDMA_SECCTL_WDROPIE_SHIFT (0x0000000B) + + #define HDMA_SECCTL_WDROPIE_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_SECCTL_WDROPIE) + + #define HDMA_SECCTL_WDROPIE_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_SECCTL_WDROPIE,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_SECCTL_RSYNCSTAT +\*----------------------------------------------------------------------------*/ + #define HDMA_SECCTL_RSYNCSTAT_MASK (0x00001000) + #define HDMA_SECCTL_RSYNCSTAT_SHIFT (0x0000000C) + + #define HDMA_SECCTL_RSYNCSTAT_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_SECCTL_RSYNCSTAT) + + #define HDMA_SECCTL_RSYNCSTAT_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_SECCTL_RSYNCSTAT,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_SECCTL_RSYNCCLR +\*----------------------------------------------------------------------------*/ + #define HDMA_SECCTL_RSYNCCLR_MASK (0x00002000) + #define HDMA_SECCTL_RSYNCCLR_SHIFT (0x0000000D) + + #define HDMA_SECCTL_RSYNCCLR_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_SECCTL_RSYNCCLR) + + #define HDMA_SECCTL_RSYNCCLR_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_SECCTL_RSYNCCLR,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_SECCTL_WSYNCSTAT +\*----------------------------------------------------------------------------*/ + #define HDMA_SECCTL_WSYNCSTAT_MASK (0x00004000) + #define HDMA_SECCTL_WSYNCSTAT_SHIFT (0x0000000E) + + #define HDMA_SECCTL_WSYNCSTAT_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_SECCTL_WSYNCSTAT) + + #define HDMA_SECCTL_WSYNCSTAT_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_SECCTL_WSYNCSTAT,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_SECCTL_WSYNCCLR +\*----------------------------------------------------------------------------*/ + #define HDMA_SECCTL_WSYNCCLR_MASK (0x00008000) + #define HDMA_SECCTL_WSYNCCLR_SHIFT (0x0000000F) + + #define HDMA_SECCTL_WSYNCCLR_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_SECCTL_WSYNCCLR) + + #define HDMA_SECCTL_WSYNCCLR_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_SECCTL_WSYNCCLR,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_SECCTL_DMACEN +\*----------------------------------------------------------------------------*/ + #define HDMA_SECCTL_DMACEN_MASK (0x00070000) + #define HDMA_SECCTL_DMACEN_SHIFT (0x00000010) + + #define HDMA_SECCTL_DMACEN_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_SECCTL_DMACEN) + + #define HDMA_SECCTL_DMACEN_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_SECCTL_DMACEN,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_SECCTL_FSIG +\*----------------------------------------------------------------------------*/ +#if (CHIP_6201|CHIP_6203) + #define HDMA_SECCTL_FSIG_MASK (0x00080000) + #define HDMA_SECCTL_FSIG_SHIFT (0x00000013) +#else + #define HDMA_SECCTL_FSIG_MASK (0x00000000) + #define HDMA_SECCTL_FSIG_SHIFT (0x00000000) +#endif + + #define HDMA_SECCTL_FSIG_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_SECCTL_FSIG) + + #define HDMA_SECCTL_FSIG_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_SECCTL_FSIG,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_SECCTL_RSPOL +\*----------------------------------------------------------------------------*/ +#if (CHIP_6201|CHIP_6203) + #define HDMA_SECCTL_RSPOL_MASK (0x00100000) + #define HDMA_SECCTL_RSPOL_SHIFT (0x00000014) +#else + #define HDMA_SECCTL_RSPOL_MASK (0x00000000) + #define HDMA_SECCTL_RSPOL_SHIFT (0x00000000) +#endif + + #define HDMA_SECCTL_RSPOL_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_SECCTL_RSPOL) + + #define HDMA_SECCTL_RSPOL_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_SECCTL_RSPOL,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_SECCTL_WSPOL +\*----------------------------------------------------------------------------*/ +#if (CHIP_6201|CHIP_6203) + #define HDMA_SECCTL_WSPOL_MASK (0x00200000) + #define HDMA_SECCTL_WSPOL_SHIFT (0x00000015) +#else + #define HDMA_SECCTL_WSPOL_MASK (0x00000000) + #define HDMA_SECCTL_WSPOL_SHIFT (0x00000000) +#endif + + #define HDMA_SECCTL_WSPOL_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_SECCTL_WSPOL) + + #define HDMA_SECCTL_WSPOL_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_SECCTL_WSPOL,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_SECCTL +\*----------------------------------------------------------------------------*/ + #define HDMA_SECCTL_GET(RegAddr) HREG32_GET(RegAddr) + #define HDMA_SECCTL_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HDMA_SECCTL_CFG(RegAddr,sxcond,sxie,framecond,frameie,lastcond,\ + lastie,blockcond,blockie,rdropcond,rdropie,wdropcond,wdropie,rsyncstat,\ + rsyncclr,wsyncstat,wsyncclr,dmacen,fsig,rspol,wspol) \ + REG32(RegAddr)=(UINT32)(\ + HFIELD_SHIFT(HDMA_SECCTL_SXCOND,sxcond)|\ + HFIELD_SHIFT(HDMA_SECCTL_SXIE,sxie)|\ + HFIELD_SHIFT(HDMA_SECCTL_FRAMECOND,framecond)|\ + HFIELD_SHIFT(HDMA_SECCTL_FRAMEIE,frameie)|\ + HFIELD_SHIFT(HDMA_SECCTL_LASTCOND,lastcond)|\ + HFIELD_SHIFT(HDMA_SECCTL_LASTIE,lastie)|\ + HFIELD_SHIFT(HDMA_SECCTL_BLOCKCOND,blockcond)|\ + HFIELD_SHIFT(HDMA_SECCTL_BLOCKIE,blockie)|\ + HFIELD_SHIFT(HDMA_SECCTL_RDROPCOND,rdropcond)|\ + HFIELD_SHIFT(HDMA_SECCTL_RDROPIE,rdropie)|\ + HFIELD_SHIFT(HDMA_SECCTL_WDROPCOND,wdropcond)|\ + HFIELD_SHIFT(HDMA_SECCTL_WDROPIE,wdropie)|\ + HFIELD_SHIFT(HDMA_SECCTL_RSYNCSTAT,rsyncstat)|\ + HFIELD_SHIFT(HDMA_SECCTL_RSYNCCLR,rsyncclr)|\ + HFIELD_SHIFT(HDMA_SECCTL_WSYNCSTAT,wsyncstat)|\ + HFIELD_SHIFT(HDMA_SECCTL_WSYNCCLR,wsyncclr)|\ + HFIELD_SHIFT(HDMA_SECCTL_DMACEN,dmacen)|\ + HFIELD_SHIFT(HDMA_SECCTL_FSIG,fsig)|\ + HFIELD_SHIFT(HDMA_SECCTL_RSPOL,rspol)|\ + HFIELD_SHIFT(HDMA_SECCTL_WSPOL,wspol)\ + ) + +/******************************************************************************\ +* HDMA_SRC0_ADDR - source address register +* HDMA_SRC1_ADDR - source address register +* HDMA_SRC2_ADDR - source address register +* HDMA_SRC3_ADDR - source address register +* +* Fields: +* (RW) HDMA_SRC_SRC +* +\******************************************************************************/ + #define HDMA_SRC0_ADDR (HDMA_BASE_ADDR+0x0010) + #define HDMA_SRC1_ADDR (HDMA_BASE_ADDR+0x0050) + #define HDMA_SRC2_ADDR (HDMA_BASE_ADDR+0x0014) + #define HDMA_SRC3_ADDR (HDMA_BASE_ADDR+0x0054) + + #define HDMA_SRC0 REG32(HDMA_SRC0_ADDR) + #define HDMA_SRC1 REG32(HDMA_SRC1_ADDR) + #define HDMA_SRC2 REG32(HDMA_SRC2_ADDR) + #define HDMA_SRC3 REG32(HDMA_SRC3_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_SRC_SRC +\*----------------------------------------------------------------------------*/ + #define HDMA_SRC_SRC_MASK (0xFFFFFFFF) + #define HDMA_SRC_SRC_SHIFT (0x00000000) + + #define HDMA_SRC_SRC_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_SRC_SRC) + + #define HDMA_SRC_SRC_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_SRC_SRC,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_SRC +\*----------------------------------------------------------------------------*/ + #define HDMA_SRC_GET(RegAddr) HREG32_GET(RegAddr) + #define HDMA_SRC_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HDMA_SRC_CFG(RegAddr,src) \ + REG32(RegAddr)=(UINT32)(\ + HFIELD_SHIFT(HDMA_SRC_SRC,src)\ + ) + +/******************************************************************************\ +* HDMA_DST0_ADDR - destination address register +* HDMA_DST1_ADDR - destination address register +* HDMA_DST2_ADDR - destination address register +* HDMA_DST3_ADDR - destination address register +* +* Fields: +* (RW) HDMA_DST_DST +* +\******************************************************************************/ + #define HDMA_DST0_ADDR (HDMA_BASE_ADDR+0x0018) + #define HDMA_DST1_ADDR (HDMA_BASE_ADDR+0x0058) + #define HDMA_DST2_ADDR (HDMA_BASE_ADDR+0x001C) + #define HDMA_DST3_ADDR (HDMA_BASE_ADDR+0x005C) + + #define HDMA_DST0 REG32(HDMA_DST0_ADDR) + #define HDMA_DST1 REG32(HDMA_DST1_ADDR) + #define HDMA_DST2 REG32(HDMA_DST2_ADDR) + #define HDMA_DST3 REG32(HDMA_DST3_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_DST_DST +\*----------------------------------------------------------------------------*/ + #define HDMA_DST_DST_MASK (0xFFFFFFFF) + #define HDMA_DST_DST_SHIFT (0x00000000) + + #define HDMA_DST_DST_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_DST_DST) + + #define HDMA_DST_DST_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_DST_DST,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_DST +\*----------------------------------------------------------------------------*/ + #define HDMA_DST_GET(RegAddr) HREG32_GET(RegAddr) + #define HDMA_DST_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HDMA_DST_CFG(RegAddr,dst) \ + REG32(RegAddr)=(UINT32)(\ + HFIELD_SHIFT(HDMA_DST_DST,dst)\ + ) + +/******************************************************************************\ +* HDMA_XFRCNT0_ADDR - transfer count register +* HDMA_XFRCNT1_ADDR - transfer count register +* HDMA_XFRCNT2_ADDR - transfer count register +* HDMA_XFRCNT3_ADDR - transfer count register +* +* Fields: +* (RW) HDMA_XFRCNT_ELECNT +* (RW) HDMA_XFRCNT_FRMCNT +* +\******************************************************************************/ + #define HDMA_XFRCNT0_ADDR (HDMA_BASE_ADDR+0x0020) + #define HDMA_XFRCNT1_ADDR (HDMA_BASE_ADDR+0x0060) + #define HDMA_XFRCNT2_ADDR (HDMA_BASE_ADDR+0x0024) + #define HDMA_XFRCNT3_ADDR (HDMA_BASE_ADDR+0x0064) + + #define HDMA_XFRCNT0 REG32(HDMA_XFRCNT0_ADDR) + #define HDMA_XFRCNT1 REG32(HDMA_XFRCNT1_ADDR) + #define HDMA_XFRCNT2 REG32(HDMA_XFRCNT2_ADDR) + #define HDMA_XFRCNT3 REG32(HDMA_XFRCNT3_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_XFRCNT_ELECNT +\*----------------------------------------------------------------------------*/ + #define HDMA_XFRCNT_ELECNT_MASK (0x0000FFFF) + #define HDMA_XFRCNT_ELECNT_SHIFT (0x00000000) + + #define HDMA_XFRCNT_ELECNT_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_XFRCNT_ELECNT) + + #define HDMA_XFRCNT_ELECNT_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_XFRCNT_ELECNT,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_XFRCNT_FRMCNT +\*----------------------------------------------------------------------------*/ + #define HDMA_XFRCNT_FRMCNT_MASK (0xFFFF0000) + #define HDMA_XFRCNT_FRMCNT_SHIFT (0x00000010) + + #define HDMA_XFRCNT_FRMCNT_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_XFRCNT_FRMCNT) + + #define HDMA_XFRCNT_FRMCNT_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_XFRCNT_FRMCNT,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_XFRCNT +\*----------------------------------------------------------------------------*/ + #define HDMA_XFRCNT_GET(RegAddr) HREG32_GET(RegAddr) + #define HDMA_XFRCNT_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HDMA_XFRCNT_CFG(RegAddr,elecnt,frmcnt) \ + REG32(RegAddr)=(UINT32)(\ + HFIELD_SHIFT(HDMA_XFRCNT_ELECNT,elecnt)|\ + HFIELD_SHIFT(HDMA_XFRCNT_FRMCNT,frmcnt)\ + ) + +/******************************************************************************\ +* HDMA_GBLCNTA_ADDR - global count reload register +* HDMA_GBLCNTB_ADDR - global count reload register +* +* Fields: +* (RW) HDMA_GBLCNT_ELECNT +* (RW) HDMA_GBLCNT_FRMCNT +* +\******************************************************************************/ + #define HDMA_GBLCNTA_ADDR (HDMA_BASE_ADDR+0x0028) + #define HDMA_GBLCNTB_ADDR (HDMA_BASE_ADDR+0x002C) + + #define HDMA_GBLCNTA REG32(HDMA_GBLCNTA_ADDR) + #define HDMA_GBLCNTB REG32(HDMA_GBLCNTB_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_GBLCNT_ELECNT +\*----------------------------------------------------------------------------*/ + #define HDMA_GBLCNT_ELECNT_MASK (0x0000FFFF) + #define HDMA_GBLCNT_ELECNT_SHIFT (0x00000000) + + #define HDMA_GBLCNT_ELECNT_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_GBLCNT_ELECNT) + + #define HDMA_GBLCNT_ELECNT_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_GBLCNT_ELECNT,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_GBLCNT_FRMCNT +\*----------------------------------------------------------------------------*/ + #define HDMA_GBLCNT_FRMCNT_MASK (0xFFFF0000) + #define HDMA_GBLCNT_FRMCNT_SHIFT (0x00000010) + + #define HDMA_GBLCNT_FRMCNT_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_GBLCNT_FRMCNT) + + #define HDMA_GBLCNT_FRMCNT_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_GBLCNT_FRMCNT,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_GBLCNT +\*----------------------------------------------------------------------------*/ + #define HDMA_GBLCNT_GET(RegAddr) HREG32_GET(RegAddr) + #define HDMA_GBLCNT_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HDMA_GBLCNT_CFG(RegAddr,elecnt,frmcnt) \ + REG32(RegAddr)=(UINT32)(\ + HFIELD_SHIFT(HDMA_GBLCNT_ELECNT,elecnt)|\ + HFIELD_SHIFT(HDMA_GBLCNT_FRMCNT,frmcnt)\ + ) + +/******************************************************************************\ +* HDMA_GBLIDXA_ADDR - global index register +* HDMA_GBLIDXB_ADDR - global index register +* +* Fields: +* (RW) HDMA_GBLIDX_ELEIDX +* (RW) HDMA_GBLIDX_FRMIDX +* +\******************************************************************************/ + #define HDMA_GBLIDXA_ADDR (HDMA_BASE_ADDR+0x0030) + #define HDMA_GBLIDXB_ADDR (HDMA_BASE_ADDR+0x0034) + + #define HDMA_GBLIDXA REG32(HDMA_GBLIDXA_ADDR) + #define HDMA_GBLIDXB REG32(HDMA_GBLIDXB_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_GBLIDX_ELEIDX +\*----------------------------------------------------------------------------*/ + #define HDMA_GBLIDX_ELEIDX_MASK (0x0000FFFF) + #define HDMA_GBLIDX_ELEIDX_SHIFT (0x00000000) + + #define HDMA_GBLIDX_ELEIDX_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_GBLIDX_ELEIDX) + + #define HDMA_GBLIDX_ELEIDX_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_GBLIDX_ELEIDX,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_GBLIDX_FRMIDX +\*----------------------------------------------------------------------------*/ + #define HDMA_GBLIDX_FRMIDX_MASK (0xFFFF0000) + #define HDMA_GBLIDX_FRMIDX_SHIFT (0x00000010) + + #define HDMA_GBLIDX_FRMIDX_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_GBLIDX_FRMIDX) + + #define HDMA_GBLIDX_FRMIDX_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_GBLIDX_FRMIDX,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_GBLIDX +\*----------------------------------------------------------------------------*/ + #define HDMA_GBLIDX_GET(RegAddr) HREG32_GET(RegAddr) + #define HDMA_GBLIDX_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HDMA_GBLIDX_CFG(RegAddr,eleidx, frmidx) \ + REG32(RegAddr)=(UINT32)(\ + HFIELD_SHIFT(HDMA_GBLIDX_ELEIDX,eleidx)|\ + HFIELD_SHIFT(HDMA_GBLIDX_FRMIDX,frmidx)\ + ) + +/******************************************************************************\ +* HDMA_GBLADDRA_ADDR - global address register +* HDMA_GBLADDRB_ADDR - global address register +* HDMA_GBLADDRC_ADDR - global address register +* HDMA_GBLADDRD_ADDR - global address register +* +* Fields: +* (RW) HDMA_GBLADDR_GBLADDR +* +\******************************************************************************/ + #define HDMA_GBLADDRA_ADDR (HDMA_BASE_ADDR+0x0038) + #define HDMA_GBLADDRB_ADDR (HDMA_BASE_ADDR+0x003C) + #define HDMA_GBLADDRC_ADDR (HDMA_BASE_ADDR+0x0068) + #define HDMA_GBLADDRD_ADDR (HDMA_BASE_ADDR+0x006C) + + #define HDMA_GBLADDRA REG32(HDMA_GBLADDRA_ADDR) + #define HDMA_GBLADDRB REG32(HDMA_GBLADDRB_ADDR) + #define HDMA_GBLADDRC REG32(HDMA_GBLADDRC_ADDR) + #define HDMA_GBLADDRD REG32(HDMA_GBLADDRD_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_GBLADDR_GBLADDR +\*----------------------------------------------------------------------------*/ + #define HDMA_GBLADDR_ADDR_MASK (0xFFFFFFFF) + #define HDMA_GBLADDR_ADDR_SHIFT (0x00000000) + + #define HDMA_GBLADDR_GBLADDR_GET(RegAddr) \ + HFIELD_GET(RegAddr,HDMA_GBLADDR_GBLADDR) + + #define HDMA_GBLADDR_GBLADDR_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HDMA_GBLADDR_GBLADDR,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HDMA_GBLADDR +\*----------------------------------------------------------------------------*/ + #define HDMA_GBLADDR_GET(RegAddr) HREG32_GET(RegAddr) + #define HDMA_GBLADDR_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HDMA_GBLADDR_CFG(RegAddr,gbladdr) \ + REG32(RegAddr)=(UINT32)(\ + HFIELD_SHIFT(HDMA_GBLADDR_GBLADDR,gbladdr)\ + ) + +/******************************************************************************/ + +#endif /* DMA_SUPPORT */ +#endif /* _DMAHAL_H_ */ +/******************************************************************************\ +* End of dmahal.h +\******************************************************************************/ +/******************************************************************************\ +* Copyright (C) 1999-2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... edmahal.h +* DATE CREATED.. 06/12/1999 +* LAST MODIFIED. 03/08/2000 +* +*------------------------------------------------------------------------------ +* DESCRIPTION: (HAL interface file for the EDMA module) +* +* Registers Covered: +* HEDMA_OPT - options (for both QDMA and PRAM entries) +* HEDMA_SRC - source address (for both QDMA and PRAM entries) +* HEDMA_CNT - transfer count (for both QDMA and PRAM entries) +* HEDMA_DST - destination address (for both QDMA and PRAM entries) +* HEDMA_IDX - index (for both QDMA and PRAM entries) +* HEDMA_RLD - reload/link (for PRAM entries) +* HEDMA_PQSR - priority queue status register +* HEDMA_CIPR - channel interrupt pending register +* HEDMA_CIER - channel interrupt enable register +* HEDMA_CCER - channel chain enable register +* HEDMA_ER - event register +* HEDMA_EER - event enable register +* HEDMA_ECR - event clear register +* HEDMA_ESR - event set register +* +\******************************************************************************/ +#ifndef _EDMAHAL_H_ +#define _EDMAHAL_H_ + +#if (EDMA_SUPPORT) +/*============================================================================*\ +* misc declarations +\*============================================================================*/ + #define HEDMA_BASE0_ADDR (HCHIP_PERBASE_ADDR+0x00200000) + #define HEDMA_BASE1_ADDR (HCHIP_PERBASE_ADDR+0x00800000) + + #define HEDMA_CHA_CNT (16) + + #define HEDMA_PRAM_START (HEDMA_BASE0_ADDR) + #define HEDMA_PRAM_SIZE (0x00000800) + #define HEDMA_PRAM_END (HEDMA_PRAM_START+HEDMA_PRAM_SIZE-1) + #define HEDMA_ENTRY_SIZE (24) + #define HEDMA_ENTRY_CNT (HEDMA_PRAM_SIZE / HEDMA_ENTRY_SIZE) + + #define HEDMA_MK_ENTRY_ADDR(cha) (HEDMA_PRAM_START+(cha)*HEDMA_ENTRY_SIZE) + + #define HEDMA_ENTRY0_ADDR HEDMA_MK_ENTRY_ADDR(0) + #define HEDMA_ENTRY1_ADDR HEDMA_MK_ENTRY_ADDR(1) + #define HEDMA_ENTRY2_ADDR HEDMA_MK_ENTRY_ADDR(2) + #define HEDMA_ENTRY3_ADDR HEDMA_MK_ENTRY_ADDR(3) + #define HEDMA_ENTRY4_ADDR HEDMA_MK_ENTRY_ADDR(4) + #define HEDMA_ENTRY5_ADDR HEDMA_MK_ENTRY_ADDR(5) + #define HEDMA_ENTRY6_ADDR HEDMA_MK_ENTRY_ADDR(6) + #define HEDMA_ENTRY7_ADDR HEDMA_MK_ENTRY_ADDR(7) + #define HEDMA_ENTRY8_ADDR HEDMA_MK_ENTRY_ADDR(8) + #define HEDMA_ENTRY9_ADDR HEDMA_MK_ENTRY_ADDR(9) + #define HEDMA_ENTRY10_ADDR HEDMA_MK_ENTRY_ADDR(10) + #define HEDMA_ENTRY11_ADDR HEDMA_MK_ENTRY_ADDR(11) + #define HEDMA_ENTRY12_ADDR HEDMA_MK_ENTRY_ADDR(12) + #define HEDMA_ENTRY13_ADDR HEDMA_MK_ENTRY_ADDR(13) + #define HEDMA_ENTRY14_ADDR HEDMA_MK_ENTRY_ADDR(14) + #define HEDMA_ENTRY15_ADDR HEDMA_MK_ENTRY_ADDR(15) + + #define HEDMA_LINK_START HEDMA_MK_ENTRY_ADDR(16) + + #define HEDMA_LINK_CNT ((HEDMA_PRAM_END-HEDMA_LINK_START+1)\ + /HEDMA_ENTRY_SIZE) + + #define HEDMA_MK_LINK_ADDR(l) (HEDMA_LINK_START+(l)*HEDMA_ENTRY_SIZE) + + #define HEDMA_SCRATCH_START (HEDMA_LINK_START+\ + (HEDMA_ENTRY_SIZE*HEDMA_LINK_CNT)) + + #define HEDMA_SCRATCH_SIZE (HEDMA_PRAM_END-HEDMA_SCRATCH_START+1) + + + #define HEDMA_OPT_OFFSET (0x00000000) + #define HEDMA_SRC_OFFSET (0x00000004) + #define HEDMA_CNT_OFFSET (0x00000008) + #define HEDMA_DST_OFFSET (0x0000000C) + #define HEDMA_IDX_OFFSET (0x00000010) + #define HEDMA_RLD_OFFSET (0x00000014) + +/******************************************************************************\ +* HEDMA_OPT - transfer options +* +* Fields: +* (RW) HEDMA_OPT_FS +* (RW) HEDMA_OPT_LINK +* (RW) HEDMA_OPT_TCC +* (RW) HEDMA_OPT_TCINT +* (RW) HEDMA_OPT_DUM +* (RW) HEDMA_OPT_2DD +* (RW) HEDMA_OPT_SUM +* (RW) HEDMA_OPT_2DS +* (RW) HEDMA_OPT_ESIZE +* (RW) HEDMA_OPT_PRI +* +\******************************************************************************/ + #define HEDMA_QOPT_ADDR (HEDMA_BASE1_ADDR+0x0000) + #define HEDMA_QSOPT_ADDR (HEDMA_BASE1_ADDR+0x0020) + #define HEDMA_QOPT REG32(HEDMA_QOPT_ADDR) + #define HEDMA_QSOPT REG32(HEDMA_QSOPT_ADDR) + + #define HEDMA_OPT0_ADDR (HEDMA_ENTRY0_ADDR+HEDMA_OPT_OFFSET) + #define HEDMA_OPT1_ADDR (HEDMA_ENTRY1_ADDR+HEDMA_OPT_OFFSET) + #define HEDMA_OPT2_ADDR (HEDMA_ENTRY2_ADDR+HEDMA_OPT_OFFSET) + #define HEDMA_OPT3_ADDR (HEDMA_ENTRY3_ADDR+HEDMA_OPT_OFFSET) + #define HEDMA_OPT4_ADDR (HEDMA_ENTRY4_ADDR+HEDMA_OPT_OFFSET) + #define HEDMA_OPT5_ADDR (HEDMA_ENTRY5_ADDR+HEDMA_OPT_OFFSET) + #define HEDMA_OPT6_ADDR (HEDMA_ENTRY6_ADDR+HEDMA_OPT_OFFSET) + #define HEDMA_OPT7_ADDR (HEDMA_ENTRY7_ADDR+HEDMA_OPT_OFFSET) + #define HEDMA_OPT8_ADDR (HEDMA_ENTRY8_ADDR+HEDMA_OPT_OFFSET) + #define HEDMA_OPT9_ADDR (HEDMA_ENTRY9_ADDR+HEDMA_OPT_OFFSET) + #define HEDMA_OPT10_ADDR (HEDMA_ENTRY10_ADDR+HEDMA_OPT_OFFSET) + #define HEDMA_OPT11_ADDR (HEDMA_ENTRY11_ADDR+HEDMA_OPT_OFFSET) + #define HEDMA_OPT12_ADDR (HEDMA_ENTRY12_ADDR+HEDMA_OPT_OFFSET) + #define HEDMA_OPT13_ADDR (HEDMA_ENTRY13_ADDR+HEDMA_OPT_OFFSET) + #define HEDMA_OPT14_ADDR (HEDMA_ENTRY14_ADDR+HEDMA_OPT_OFFSET) + #define HEDMA_OPT15_ADDR (HEDMA_ENTRY15_ADDR+HEDMA_OPT_OFFSET) + + #define HEDMA_OPT0 REG32(HEDMA_OPT0_ADDR) + #define HEDMA_OPT1 REG32(HEDMA_OPT1_ADDR) + #define HEDMA_OPT2 REG32(HEDMA_OPT2_ADDR) + #define HEDMA_OPT3 REG32(HEDMA_OPT3_ADDR) + #define HEDMA_OPT4 REG32(HEDMA_OPT4_ADDR) + #define HEDMA_OPT5 REG32(HEDMA_OPT5_ADDR) + #define HEDMA_OPT6 REG32(HEDMA_OPT6_ADDR) + #define HEDMA_OPT7 REG32(HEDMA_OPT7_ADDR) + #define HEDMA_OPT8 REG32(HEDMA_OPT8_ADDR) + #define HEDMA_OPT9 REG32(HEDMA_OPT9_ADDR) + #define HEDMA_OPT10 REG32(HEDMA_OPT10_ADDR) + #define HEDMA_OPT11 REG32(HEDMA_OPT11_ADDR) + #define HEDMA_OPT12 REG32(HEDMA_OPT12_ADDR) + #define HEDMA_OPT13 REG32(HEDMA_OPT13_ADDR) + #define HEDMA_OPT14 REG32(HEDMA_OPT14_ADDR) + #define HEDMA_OPT15 REG32(HEDMA_OPT15_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_OPT_FS +\*----------------------------------------------------------------------------*/ + #define HEDMA_OPT_FS_MASK (0x00000001) + #define HEDMA_OPT_FS_SHIFT (0x00000000) + + #define HEDMA_OPT_FS_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_OPT_FS) + + #define HEDMA_OPT_FS_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_OPT_FS,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_OPT_LINK +\*----------------------------------------------------------------------------*/ + #define HEDMA_OPT_LINK_MASK (0x00000002) + #define HEDMA_OPT_LINK_SHIFT (0x00000001) + + #define HEDMA_OPT_LINK_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_OPT_LINK) + + #define HEDMA_OPT_LINK_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_OPT_LINK,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_OPT_TCC +\*----------------------------------------------------------------------------*/ + #define HEDMA_OPT_TCC_MASK (0x000F0000) + #define HEDMA_OPT_TCC_SHIFT (0x00000010) + + #define HEDMA_OPT_TCC_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_OPT_TCC) + + #define HEDMA_OPT_TCC_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_OPT_TCC,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_OPT_TCINT +\*----------------------------------------------------------------------------*/ + #define HEDMA_OPT_TCINT_MASK (0x00100000) + #define HEDMA_OPT_TCINT_SHIFT (0x00000014) + + #define HEDMA_OPT_TCINT_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_OPT_TCINT) + + #define HEDMA_OPT_TCINT_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_OPT_TCINT,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_OPT_DUM +\*----------------------------------------------------------------------------*/ + #define HEDMA_OPT_DUM_MASK (0x00600000) + #define HEDMA_OPT_DUM_SHIFT (0x00000015) + + #define HEDMA_OPT_DUM_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_OPT_DUM) + + #define HEDMA_OPT_DUM_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_OPT_DUM,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_OPT_2DD +\*----------------------------------------------------------------------------*/ + #define HEDMA_OPT_2DD_MASK (0x00800000) + #define HEDMA_OPT_2DD_SHIFT (0x00000017) + + #define HEDMA_OPT_2DD_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_OPT_2DD) + + #define HEDMA_OPT_2DD_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_OPT_2DD,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_OPT_SUM +\*----------------------------------------------------------------------------*/ + #define HEDMA_OPT_SUM_MASK (0x03000000) + #define HEDMA_OPT_SUM_SHIFT (0x00000018) + + #define HEDMA_OPT_SUM_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_OPT_SUM) + + #define HEDMA_OPT_SUM_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_OPT_SUM,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_OPT_2DS +\*----------------------------------------------------------------------------*/ + #define HEDMA_OPT_2DS_MASK (0x04000000) + #define HEDMA_OPT_2DS_SHIFT (0x0000001A) + + #define HEDMA_OPT_2DS_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_OPT_2DS) + + #define HEDMA_OPT_2DS_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_OPT_2DS,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_OPT_ESIZE +\*----------------------------------------------------------------------------*/ + #define HEDMA_OPT_ESIZE_MASK (0x18000000) + #define HEDMA_OPT_ESIZE_SHIFT (0x0000001B) + + #define HEDMA_OPT_ESIZE_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_OPT_ESIZE) + + #define HEDMA_OPT_ESIZE_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_OPT_ESIZE,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_OPT_PRI +\*----------------------------------------------------------------------------*/ + #define HEDMA_OPT_PRI_MASK (0xE0000000) + #define HEDMA_OPT_PRI_SHIFT (0x0000001D) + + #define HEDMA_OPT_PRI_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_OPT_PRI) + + #define HEDMA_OPT_PRI_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_OPT_PRI,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_OPT +\*----------------------------------------------------------------------------*/ + #define HEDMA_OPT_GET(RegAddr) HREG32_GET(RegAddr) + #define HEDMA_OPT_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HEDMA_OPT_CFG(RegAddr,fs,link,tcc,tcint,dum,d2d,sum,s2d,esize,pri)\ + REG32(RegAddr)=(UINT32)(\ + HFIELD_SHIFT(HEDMA_OPT_FS,fs)|\ + HFIELD_SHIFT(HEDMA_OPT_LINK,link)|\ + HFIELD_SHIFT(HEDMA_OPT_TCC,tcc)|\ + HFIELD_SHIFT(HEDMA_OPT_TCINT,tcint)|\ + HFIELD_SHIFT(HEDMA_OPT_DUM,dum)|\ + HFIELD_SHIFT(HEDMA_OPT_2DD,d2d)|\ + HFIELD_SHIFT(HEDMA_OPT_SUM,sum)|\ + HFIELD_SHIFT(HEDMA_OPT_2DS,s2d)|\ + HFIELD_SHIFT(HEDMA_OPT_ESIZE,esize)|\ + HFIELD_SHIFT(HEDMA_OPT_PRI,pri)\ + ) + +/******************************************************************************\ +* HEDMA_SRC - source address +* +* Fields: +* (RW) HEDMA_SRC_SRC +* +\******************************************************************************/ + #define HEDMA_QSRC_ADDR (HEDMA_BASE1_ADDR+0x0004) + #define HEDMA_QSSRC_ADDR (HEDMA_BASE1_ADDR+0x0024) + #define HEDMA_QSRC REG32(HEDMA_QSRC_ADDR) + #define HEDMA_QSSRC REG32(HEDMA_QSSRC_ADDR) + + #define HEDMA_SRC0_ADDR (HEDMA_ENTRY0_ADDR+HEDMA_SRC_OFFSET) + #define HEDMA_SRC1_ADDR (HEDMA_ENTRY1_ADDR+HEDMA_SRC_OFFSET) + #define HEDMA_SRC2_ADDR (HEDMA_ENTRY2_ADDR+HEDMA_SRC_OFFSET) + #define HEDMA_SRC3_ADDR (HEDMA_ENTRY3_ADDR+HEDMA_SRC_OFFSET) + #define HEDMA_SRC4_ADDR (HEDMA_ENTRY4_ADDR+HEDMA_SRC_OFFSET) + #define HEDMA_SRC5_ADDR (HEDMA_ENTRY5_ADDR+HEDMA_SRC_OFFSET) + #define HEDMA_SRC6_ADDR (HEDMA_ENTRY6_ADDR+HEDMA_SRC_OFFSET) + #define HEDMA_SRC7_ADDR (HEDMA_ENTRY7_ADDR+HEDMA_SRC_OFFSET) + #define HEDMA_SRC8_ADDR (HEDMA_ENTRY8_ADDR+HEDMA_SRC_OFFSET) + #define HEDMA_SRC9_ADDR (HEDMA_ENTRY9_ADDR+HEDMA_SRC_OFFSET) + #define HEDMA_SRC10_ADDR (HEDMA_ENTRY10_ADDR+HEDMA_SRC_OFFSET) + #define HEDMA_SRC11_ADDR (HEDMA_ENTRY11_ADDR+HEDMA_SRC_OFFSET) + #define HEDMA_SRC12_ADDR (HEDMA_ENTRY12_ADDR+HEDMA_SRC_OFFSET) + #define HEDMA_SRC13_ADDR (HEDMA_ENTRY13_ADDR+HEDMA_SRC_OFFSET) + #define HEDMA_SRC14_ADDR (HEDMA_ENTRY14_ADDR+HEDMA_SRC_OFFSET) + #define HEDMA_SRC15_ADDR (HEDMA_ENTRY15_ADDR+HEDMA_SRC_OFFSET) + + #define HEDMA_SRC0 REG32(HEDMA_SRC0_ADDR) + #define HEDMA_SRC1 REG32(HEDMA_SRC1_ADDR) + #define HEDMA_SRC2 REG32(HEDMA_SRC2_ADDR) + #define HEDMA_SRC3 REG32(HEDMA_SRC3_ADDR) + #define HEDMA_SRC4 REG32(HEDMA_SRC4_ADDR) + #define HEDMA_SRC5 REG32(HEDMA_SRC5_ADDR) + #define HEDMA_SRC6 REG32(HEDMA_SRC6_ADDR) + #define HEDMA_SRC7 REG32(HEDMA_SRC7_ADDR) + #define HEDMA_SRC8 REG32(HEDMA_SRC8_ADDR) + #define HEDMA_SRC9 REG32(HEDMA_SRC9_ADDR) + #define HEDMA_SRC10 REG32(HEDMA_SRC10_ADDR) + #define HEDMA_SRC11 REG32(HEDMA_SRC11_ADDR) + #define HEDMA_SRC12 REG32(HEDMA_SRC12_ADDR) + #define HEDMA_SRC13 REG32(HEDMA_SRC13_ADDR) + #define HEDMA_SRC14 REG32(HEDMA_SRC14_ADDR) + #define HEDMA_SRC15 REG32(HEDMA_SRC15_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_SRC_SRC +\*----------------------------------------------------------------------------*/ + #define HEDMA_SRC_SRC_MASK (0xFFFFFFFF) + #define HEDMA_SRC_SRC_SHIFT (0x00000000) + + #define HEDMA_SRC_SRC_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_SRC_SRC) + + #define HEDMA_SRC_SRC_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_SRC_SRC,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_SRC +\*----------------------------------------------------------------------------*/ + #define HEDMA_SRC_GET(RegAddr) HREG32_GET(RegAddr) + #define HEDMA_SRC_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HEDMA_SRC_CFG(RegAddr,src)\ + REG32(RegAddr)=(UINT32)(\ + HFIELD_SHIFT(HEDMA_SRC_SRC,src)\ + ) + +/******************************************************************************\ +* HEDMA_CNT - transfer count +* +* Fields: +* (RW) HEDMA_CNT_ELECNT +* (RW) HEDMA_CNT_FRMCNT +* +\******************************************************************************/ + #define HEDMA_QCNT_ADDR (HEDMA_BASE1_ADDR+0x0008) + #define HEDMA_QSCNT_ADDR (HEDMA_BASE1_ADDR+0x0028) + #define HEDMA_QCNT REG32(HEDMA_QCNT_ADDR) + #define HEDMA_QSCNT REG32(HEDMA_QSCNT_ADDR) + + #define HEDMA_CNT0_ADDR (HEDMA_ENTRY0_ADDR+HEDMA_CNT_OFFSET) + #define HEDMA_CNT1_ADDR (HEDMA_ENTRY1_ADDR+HEDMA_CNT_OFFSET) + #define HEDMA_CNT2_ADDR (HEDMA_ENTRY2_ADDR+HEDMA_CNT_OFFSET) + #define HEDMA_CNT3_ADDR (HEDMA_ENTRY3_ADDR+HEDMA_CNT_OFFSET) + #define HEDMA_CNT4_ADDR (HEDMA_ENTRY4_ADDR+HEDMA_CNT_OFFSET) + #define HEDMA_CNT5_ADDR (HEDMA_ENTRY5_ADDR+HEDMA_CNT_OFFSET) + #define HEDMA_CNT6_ADDR (HEDMA_ENTRY6_ADDR+HEDMA_CNT_OFFSET) + #define HEDMA_CNT7_ADDR (HEDMA_ENTRY7_ADDR+HEDMA_CNT_OFFSET) + #define HEDMA_CNT8_ADDR (HEDMA_ENTRY8_ADDR+HEDMA_CNT_OFFSET) + #define HEDMA_CNT9_ADDR (HEDMA_ENTRY9_ADDR+HEDMA_CNT_OFFSET) + #define HEDMA_CNT10_ADDR (HEDMA_ENTRY10_ADDR+HEDMA_CNT_OFFSET) + #define HEDMA_CNT11_ADDR (HEDMA_ENTRY11_ADDR+HEDMA_CNT_OFFSET) + #define HEDMA_CNT12_ADDR (HEDMA_ENTRY12_ADDR+HEDMA_CNT_OFFSET) + #define HEDMA_CNT13_ADDR (HEDMA_ENTRY13_ADDR+HEDMA_CNT_OFFSET) + #define HEDMA_CNT14_ADDR (HEDMA_ENTRY14_ADDR+HEDMA_CNT_OFFSET) + #define HEDMA_CNT15_ADDR (HEDMA_ENTRY15_ADDR+HEDMA_CNT_OFFSET) + + #define HEDMA_CNT0 REG32(HEDMA_CNT0_ADDR) + #define HEDMA_CNT1 REG32(HEDMA_CNT1_ADDR) + #define HEDMA_CNT2 REG32(HEDMA_CNT2_ADDR) + #define HEDMA_CNT3 REG32(HEDMA_CNT3_ADDR) + #define HEDMA_CNT4 REG32(HEDMA_CNT4_ADDR) + #define HEDMA_CNT5 REG32(HEDMA_CNT5_ADDR) + #define HEDMA_CNT6 REG32(HEDMA_CNT6_ADDR) + #define HEDMA_CNT7 REG32(HEDMA_CNT7_ADDR) + #define HEDMA_CNT8 REG32(HEDMA_CNT8_ADDR) + #define HEDMA_CNT9 REG32(HEDMA_CNT9_ADDR) + #define HEDMA_CNT10 REG32(HEDMA_CNT10_ADDR) + #define HEDMA_CNT11 REG32(HEDMA_CNT11_ADDR) + #define HEDMA_CNT12 REG32(HEDMA_CNT12_ADDR) + #define HEDMA_CNT13 REG32(HEDMA_CNT13_ADDR) + #define HEDMA_CNT14 REG32(HEDMA_CNT14_ADDR) + #define HEDMA_CNT15 REG32(HEDMA_CNT15_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CNT_ELECNT +\*----------------------------------------------------------------------------*/ + #define HEDMA_CNT_ELECNT_MASK (0x0000FFFF) + #define HEDMA_CNT_ELECNT_SHIFT (0x00000000) + + #define HEDMA_CNT_ELECNT_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CNT_ELECNT) + + #define HEDMA_CNT_ELECNT_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CNT_ELECNT,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CNT_FRMCNT +\*----------------------------------------------------------------------------*/ + #define HEDMA_CNT_FRMCNT_MASK (0xFFFF0000) + #define HEDMA_CNT_FRMCNT_SHIFT (0x00000010) + + #define HEDMA_CNT_FRMCNT_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CNT_FRMCNT) + + #define HEDMA_CNT_FRMCNT_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CNT_FRMCNT,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CNT +\*----------------------------------------------------------------------------*/ + #define HEDMA_CNT_GET(RegAddr) HREG32_GET(RegAddr) + #define HEDMA_CNT_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HEDMA_CNT_CFG(RegAddr,elecnt,frmcnt)\ + REG32(RegAddr)=(UINT32)(\ + HFIELD_SHIFT(HEDMA_CNT_ELECNT,elecnt)|\ + HFIELD_SHIFT(HEDMA_CNT_FRMCNT,frmcnt)\ + ) + +/******************************************************************************\ +* HEDMA_DST - destination address +* +* Fields: +* (RW) HEDMA_DST_DST +* +\******************************************************************************/ + #define HEDMA_QDST_ADDR (HEDMA_BASE1_ADDR+0x000C) + #define HEDMA_QSDST_ADDR (HEDMA_BASE1_ADDR+0x002C) + #define HEDMA_QDST REG32(HEDMA_QDST_ADDR) + #define HEDMA_QSDST REG32(HEDMA_QSDST_ADDR) + + #define HEDMA_DST0_ADDR (HEDMA_ENTRY0_ADDR+HEDMA_DST_OFFSET) + #define HEDMA_DST1_ADDR (HEDMA_ENTRY1_ADDR+HEDMA_DST_OFFSET) + #define HEDMA_DST2_ADDR (HEDMA_ENTRY2_ADDR+HEDMA_DST_OFFSET) + #define HEDMA_DST3_ADDR (HEDMA_ENTRY3_ADDR+HEDMA_DST_OFFSET) + #define HEDMA_DST4_ADDR (HEDMA_ENTRY4_ADDR+HEDMA_DST_OFFSET) + #define HEDMA_DST5_ADDR (HEDMA_ENTRY5_ADDR+HEDMA_DST_OFFSET) + #define HEDMA_DST6_ADDR (HEDMA_ENTRY6_ADDR+HEDMA_DST_OFFSET) + #define HEDMA_DST7_ADDR (HEDMA_ENTRY7_ADDR+HEDMA_DST_OFFSET) + #define HEDMA_DST8_ADDR (HEDMA_ENTRY8_ADDR+HEDMA_DST_OFFSET) + #define HEDMA_DST9_ADDR (HEDMA_ENTRY9_ADDR+HEDMA_DST_OFFSET) + #define HEDMA_DST10_ADDR (HEDMA_ENTRY10_ADDR+HEDMA_DST_OFFSET) + #define HEDMA_DST11_ADDR (HEDMA_ENTRY11_ADDR+HEDMA_DST_OFFSET) + #define HEDMA_DST12_ADDR (HEDMA_ENTRY12_ADDR+HEDMA_DST_OFFSET) + #define HEDMA_DST13_ADDR (HEDMA_ENTRY13_ADDR+HEDMA_DST_OFFSET) + #define HEDMA_DST14_ADDR (HEDMA_ENTRY14_ADDR+HEDMA_DST_OFFSET) + #define HEDMA_DST15_ADDR (HEDMA_ENTRY15_ADDR+HEDMA_DST_OFFSET) + + #define HEDMA_DST0 REG32(HEDMA_DST0_ADDR) + #define HEDMA_DST1 REG32(HEDMA_DST1_ADDR) + #define HEDMA_DST2 REG32(HEDMA_DST2_ADDR) + #define HEDMA_DST3 REG32(HEDMA_DST3_ADDR) + #define HEDMA_DST4 REG32(HEDMA_DST4_ADDR) + #define HEDMA_DST5 REG32(HEDMA_DST5_ADDR) + #define HEDMA_DST6 REG32(HEDMA_DST6_ADDR) + #define HEDMA_DST7 REG32(HEDMA_DST7_ADDR) + #define HEDMA_DST8 REG32(HEDMA_DST8_ADDR) + #define HEDMA_DST9 REG32(HEDMA_DST9_ADDR) + #define HEDMA_DST10 REG32(HEDMA_DST10_ADDR) + #define HEDMA_DST11 REG32(HEDMA_DST11_ADDR) + #define HEDMA_DST12 REG32(HEDMA_DST12_ADDR) + #define HEDMA_DST13 REG32(HEDMA_DST13_ADDR) + #define HEDMA_DST14 REG32(HEDMA_DST14_ADDR) + #define HEDMA_DST15 REG32(HEDMA_DST15_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_DST_DST +\*----------------------------------------------------------------------------*/ + #define HEDMA_DST_DST_MASK (0xFFFFFFFF) + #define HEDMA_DST_DST_SHIFT (0x00000000) + + #define HEDMA_DST_DST_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_DST_DST) + + #define HEDMA_DST_DST_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_DST_DST,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_DST +\*----------------------------------------------------------------------------*/ + #define HEDMA_DST_GET(RegAddr) HREG32_GET(RegAddr) + #define HEDMA_DST_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HEDMA_DST_CFG(RegAddr,src)\ + REG32(RegAddr)=(UINT32)(\ + HFIELD_SHIFT(HEDMA_DST_DST,src)\ + ) + +/******************************************************************************\ +* HEDMA_IDX - transfer count +* +* Fields: +* (RW) HEDMA_IDX_ELEIDX +* (RW) HEDMA_IDX_FRMIDX +* +\******************************************************************************/ + #define HEDMA_QIDX_ADDR (HEDMA_BASE1_ADDR+0x0010) + #define HEDMA_QSIDX_ADDR (HEDMA_BASE1_ADDR+0x0030) + #define HEDMA_QIDX REG32(HEDMA_QIDX_ADDR) + #define HEDMA_QSIDX REG32(HEDMA_QSIDX_ADDR) + + #define HEDMA_IDX0_ADDR (HEDMA_ENTRY0_ADDR+HEDMA_IDX_OFFSET) + #define HEDMA_IDX1_ADDR (HEDMA_ENTRY1_ADDR+HEDMA_IDX_OFFSET) + #define HEDMA_IDX2_ADDR (HEDMA_ENTRY2_ADDR+HEDMA_IDX_OFFSET) + #define HEDMA_IDX3_ADDR (HEDMA_ENTRY3_ADDR+HEDMA_IDX_OFFSET) + #define HEDMA_IDX4_ADDR (HEDMA_ENTRY4_ADDR+HEDMA_IDX_OFFSET) + #define HEDMA_IDX5_ADDR (HEDMA_ENTRY5_ADDR+HEDMA_IDX_OFFSET) + #define HEDMA_IDX6_ADDR (HEDMA_ENTRY6_ADDR+HEDMA_IDX_OFFSET) + #define HEDMA_IDX7_ADDR (HEDMA_ENTRY7_ADDR+HEDMA_IDX_OFFSET) + #define HEDMA_IDX8_ADDR (HEDMA_ENTRY8_ADDR+HEDMA_IDX_OFFSET) + #define HEDMA_IDX9_ADDR (HEDMA_ENTRY9_ADDR+HEDMA_IDX_OFFSET) + #define HEDMA_IDX10_ADDR (HEDMA_ENTRY10_ADDR+HEDMA_IDX_OFFSET) + #define HEDMA_IDX11_ADDR (HEDMA_ENTRY11_ADDR+HEDMA_IDX_OFFSET) + #define HEDMA_IDX12_ADDR (HEDMA_ENTRY12_ADDR+HEDMA_IDX_OFFSET) + #define HEDMA_IDX13_ADDR (HEDMA_ENTRY13_ADDR+HEDMA_IDX_OFFSET) + #define HEDMA_IDX14_ADDR (HEDMA_ENTRY14_ADDR+HEDMA_IDX_OFFSET) + #define HEDMA_IDX15_ADDR (HEDMA_ENTRY15_ADDR+HEDMA_IDX_OFFSET) + + #define HEDMA_IDX0 REG32(HEDMA_IDX0_ADDR) + #define HEDMA_IDX1 REG32(HEDMA_IDX1_ADDR) + #define HEDMA_IDX2 REG32(HEDMA_IDX2_ADDR) + #define HEDMA_IDX3 REG32(HEDMA_IDX3_ADDR) + #define HEDMA_IDX4 REG32(HEDMA_IDX4_ADDR) + #define HEDMA_IDX5 REG32(HEDMA_IDX5_ADDR) + #define HEDMA_IDX6 REG32(HEDMA_IDX6_ADDR) + #define HEDMA_IDX7 REG32(HEDMA_IDX7_ADDR) + #define HEDMA_IDX8 REG32(HEDMA_IDX8_ADDR) + #define HEDMA_IDX9 REG32(HEDMA_IDX9_ADDR) + #define HEDMA_IDX10 REG32(HEDMA_IDX10_ADDR) + #define HEDMA_IDX11 REG32(HEDMA_IDX11_ADDR) + #define HEDMA_IDX12 REG32(HEDMA_IDX12_ADDR) + #define HEDMA_IDX13 REG32(HEDMA_IDX13_ADDR) + #define HEDMA_IDX14 REG32(HEDMA_IDX14_ADDR) + #define HEDMA_IDX15 REG32(HEDMA_IDX15_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_IDX_ELEIDX +\*----------------------------------------------------------------------------*/ + #define HEDMA_IDX_ELEIDX_MASK (0x0000FFFF) + #define HEDMA_IDX_ELEIDX_SHIFT (0x00000000) + + #define HEDMA_IDX_ELEIDX_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_IDX_ELEIDX) + + #define HEDMA_IDX_ELEIDX_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_IDX_ELEIDX,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_IDX_FRMIDX +\*----------------------------------------------------------------------------*/ + #define HEDMA_IDX_FRMIDX_MASK (0xFFFF0000) + #define HEDMA_IDX_FRMIDX_SHIFT (0x00000010) + + #define HEDMA_IDX_FRMIDX_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_IDX_FRMIDX) + + #define HEDMA_IDX_FRMIDX_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_IDX_FRMIDX,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_IDX +\*----------------------------------------------------------------------------*/ + #define HEDMA_IDX_GET(RegAddr) HREG32_GET(RegAddr) + #define HEDMA_IDX_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HEDMA_IDX_CFG(RegAddr,eleidx,frmidx)\ + REG32(RegAddr)=(UINT32)(\ + HFIELD_SHIFT(HEDMA_IDX_ELEIDX,eleidx)|\ + HFIELD_SHIFT(HEDMA_IDX_FRMIDX,frmidx)\ + ) + +/******************************************************************************\ +* HEDMA_RLD - element reload/link address +* +* Fields: +* (RW) HEDMA_RLD_LINK +* (RW) HEDMA_RLD_ELERLD +* +\******************************************************************************/ + #define HEDMA_RLD0_ADDR (HEDMA_ENTRY0_ADDR+HEDMA_RLD_OFFSET) + #define HEDMA_RLD1_ADDR (HEDMA_ENTRY1_ADDR+HEDMA_RLD_OFFSET) + #define HEDMA_RLD2_ADDR (HEDMA_ENTRY2_ADDR+HEDMA_RLD_OFFSET) + #define HEDMA_RLD3_ADDR (HEDMA_ENTRY3_ADDR+HEDMA_RLD_OFFSET) + #define HEDMA_RLD4_ADDR (HEDMA_ENTRY4_ADDR+HEDMA_RLD_OFFSET) + #define HEDMA_RLD5_ADDR (HEDMA_ENTRY5_ADDR+HEDMA_RLD_OFFSET) + #define HEDMA_RLD6_ADDR (HEDMA_ENTRY6_ADDR+HEDMA_RLD_OFFSET) + #define HEDMA_RLD7_ADDR (HEDMA_ENTRY7_ADDR+HEDMA_RLD_OFFSET) + #define HEDMA_RLD8_ADDR (HEDMA_ENTRY8_ADDR+HEDMA_RLD_OFFSET) + #define HEDMA_RLD9_ADDR (HEDMA_ENTRY9_ADDR+HEDMA_RLD_OFFSET) + #define HEDMA_RLD10_ADDR (HEDMA_ENTRY10_ADDR+HEDMA_RLD_OFFSET) + #define HEDMA_RLD11_ADDR (HEDMA_ENTRY11_ADDR+HEDMA_RLD_OFFSET) + #define HEDMA_RLD12_ADDR (HEDMA_ENTRY12_ADDR+HEDMA_RLD_OFFSET) + #define HEDMA_RLD13_ADDR (HEDMA_ENTRY13_ADDR+HEDMA_RLD_OFFSET) + #define HEDMA_RLD14_ADDR (HEDMA_ENTRY14_ADDR+HEDMA_RLD_OFFSET) + #define HEDMA_RLD15_ADDR (HEDMA_ENTRY15_ADDR+HEDMA_RLD_OFFSET) + + #define HEDMA_RLD0 REG32(HEDMA_RLD0_ADDR) + #define HEDMA_RLD1 REG32(HEDMA_RLD1_ADDR) + #define HEDMA_RLD2 REG32(HEDMA_RLD2_ADDR) + #define HEDMA_RLD3 REG32(HEDMA_RLD3_ADDR) + #define HEDMA_RLD4 REG32(HEDMA_RLD4_ADDR) + #define HEDMA_RLD5 REG32(HEDMA_RLD5_ADDR) + #define HEDMA_RLD6 REG32(HEDMA_RLD6_ADDR) + #define HEDMA_RLD7 REG32(HEDMA_RLD7_ADDR) + #define HEDMA_RLD8 REG32(HEDMA_RLD8_ADDR) + #define HEDMA_RLD9 REG32(HEDMA_RLD9_ADDR) + #define HEDMA_RLD10 REG32(HEDMA_RLD10_ADDR) + #define HEDMA_RLD11 REG32(HEDMA_RLD11_ADDR) + #define HEDMA_RLD12 REG32(HEDMA_RLD12_ADDR) + #define HEDMA_RLD13 REG32(HEDMA_RLD13_ADDR) + #define HEDMA_RLD14 REG32(HEDMA_RLD14_ADDR) + #define HEDMA_RLD15 REG32(HEDMA_RLD15_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_RLD_LINK +\*----------------------------------------------------------------------------*/ + #define HEDMA_RLD_LINK_MASK (0x0000FFFF) + #define HEDMA_RLD_LINK_SHIFT (0x00000000) + + #define HEDMA_RLD_LINK_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_RLD_LINK) + + #define HEDMA_RLD_LINK_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_RLD_LINK,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_RLD_ELERLD +\*----------------------------------------------------------------------------*/ + #define HEDMA_RLD_ELERLD_MASK (0xFFFF0000) + #define HEDMA_RLD_ELERLD_SHIFT (0x00000010) + + #define HEDMA_RLD_ELERLD_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_RLD_ELERLD) + + #define HEDMA_RLD_ELERLD_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_RLD_ELERLD,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_RLD +\*----------------------------------------------------------------------------*/ + #define HEDMA_RLD_GET(RegAddr) HREG32_GET(RegAddr) + #define HEDMA_RLD_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HEDMA_RLD_CFG(RegAddr,link,elerld)\ + REG32(RegAddr)=(UINT32)(\ + HFIELD_SHIFT(HEDMA_RLD_LINK,link)|\ + HFIELD_SHIFT(HEDMA_RLD_ELERLD,elerld)\ + ) + +/******************************************************************************\ +* HEDMA_PQSR - priority queue status register +* +* Fields: +* (R) HEDMA_PQSR_PQ0 +* (R) HEDMA_PQSR_PQ1 +* (R) HEDMA_PQSR_PQ2 +* +\******************************************************************************/ + #define HEDMA_PQSR_ADDR (HEDMA_BASE0_ADDR+0xFFE0) + #define HEDMA_PQSR REG32(HEDMA_PQSR_ADDR) + +/*----------------------------------------------------------------------------*\ +* (R) HEDMA_PQSR_PQ0 +\*----------------------------------------------------------------------------*/ + #define HEDMA_PQSR_PQ0_MASK (0x00000001) + #define HEDMA_PQSR_PQ0_SHIFT (0x00000000) + + #define HEDMA_PQSR_PQ0_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_PQSR_PQ0) + +/*----------------------------------------------------------------------------*\ +* (R) HEDMA_PQSR_PQ1 +\*----------------------------------------------------------------------------*/ + #define HEDMA_PQSR_PQ1_MASK (0x00000002) + #define HEDMA_PQSR_PQ1_SHIFT (0x00000001) + + #define HEDMA_PQSR_PQ1_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_PQSR_PQ1) + +/*----------------------------------------------------------------------------*\ +* (R) HEDMA_PQSR_PQ2 +\*----------------------------------------------------------------------------*/ + #define HEDMA_PQSR_PQ2_MASK (0x00000004) + #define HEDMA_PQSR_PQ2_SHIFT (0x00000002) + + #define HEDMA_PQSR_PQ2_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_PQSR_PQ2) + +/*----------------------------------------------------------------------------*\ +* (R) HEDMA_PQSR +\*----------------------------------------------------------------------------*/ + #define HEDMA_PQSR_GET(RegAddr) HREG32_GET(RegAddr) + +/******************************************************************************\ +* HEDMA_CIPR - channel interrupt pending register +* +* Fields: +* (RW) HEDMA_CIPR_CIP0 +* (RW) HEDMA_CIPR_CIP1 +* (RW) HEDMA_CIPR_CIP2 +* (RW) HEDMA_CIPR_CIP3 +* (RW) HEDMA_CIPR_CIP4 +* (RW) HEDMA_CIPR_CIP5 +* (RW) HEDMA_CIPR_CIP6 +* (RW) HEDMA_CIPR_CIP7 +* (RW) HEDMA_CIPR_CIP8 +* (RW) HEDMA_CIPR_CIP9 +* (RW) HEDMA_CIPR_CIP10 +* (RW) HEDMA_CIPR_CIP11 +* (RW) HEDMA_CIPR_CIP12 +* (RW) HEDMA_CIPR_CIP13 +* (RW) HEDMA_CIPR_CIP14 +* (RW) HEDMA_CIPR_CIP15 +* +\******************************************************************************/ + #define HEDMA_CIPR_ADDR (HEDMA_BASE0_ADDR+0xFFE4) + #define HEDMA_CIPR REG32(HEDMA_CIPR_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CIPR_CIP0 +\*----------------------------------------------------------------------------*/ + #define HEDMA_CIPR_CIP0_MASK (0x00000001) + #define HEDMA_CIPR_CIP0_SHIFT (0x00000000) + + #define HEDMA_CIPR_CIP0_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CIPR_CIP0) + + #define HEDMA_CIPR_CIP0_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CIPR_CIP0,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CIPR_CIP1 +\*----------------------------------------------------------------------------*/ + #define HEDMA_CIPR_CIP1_MASK (0x00000002) + #define HEDMA_CIPR_CIP1_SHIFT (0x00000001) + + #define HEDMA_CIPR_CIP1_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CIPR_CIP1) + + #define HEDMA_CIPR_CIP1_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CIPR_CIP1,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CIPR_CIP2 +\*----------------------------------------------------------------------------*/ + #define HEDMA_CIPR_CIP2_MASK (0x00000004) + #define HEDMA_CIPR_CIP2_SHIFT (0x00000002) + + #define HEDMA_CIPR_CIP2_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CIPR_CIP2) + + #define HEDMA_CIPR_CIP2_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CIPR_CIP2,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CIPR_CIP3 +\*----------------------------------------------------------------------------*/ + #define HEDMA_CIPR_CIP3_MASK (0x00000008) + #define HEDMA_CIPR_CIP3_SHIFT (0x00000003) + + #define HEDMA_CIPR_CIP3_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CIPR_CIP3) + + #define HEDMA_CIPR_CIP3_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CIPR_CIP3,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CIPR_CIP4 +\*----------------------------------------------------------------------------*/ + #define HEDMA_CIPR_CIP4_MASK (0x00000010) + #define HEDMA_CIPR_CIP4_SHIFT (0x00000004) + + #define HEDMA_CIPR_CIP4_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CIPR_CIP4) + + #define HEDMA_CIPR_CIP4_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CIPR_CIP4,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CIPR_CIP5 +\*----------------------------------------------------------------------------*/ + #define HEDMA_CIPR_CIP5_MASK (0x00000020) + #define HEDMA_CIPR_CIP5_SHIFT (0x00000005) + + #define HEDMA_CIPR_CIP5_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CIPR_CIP5) + + #define HEDMA_CIPR_CIP5_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CIPR_CIP5,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CIPR_CIP6 +\*----------------------------------------------------------------------------*/ + #define HEDMA_CIPR_CIP6_MASK (0x00000040) + #define HEDMA_CIPR_CIP6_SHIFT (0x00000006) + + #define HEDMA_CIPR_CIP6_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CIPR_CIP6) + + #define HEDMA_CIPR_CIP6_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CIPR_CIP6,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CIPR_CIP7 +\*----------------------------------------------------------------------------*/ + #define HEDMA_CIPR_CIP7_MASK (0x00000080) + #define HEDMA_CIPR_CIP7_SHIFT (0x00000007) + + #define HEDMA_CIPR_CIP7_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CIPR_CIP7) + + #define HEDMA_CIPR_CIP7_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CIPR_CIP7,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CIPR_CIP8 +\*----------------------------------------------------------------------------*/ + #define HEDMA_CIPR_CIP8_MASK (0x00000100) + #define HEDMA_CIPR_CIP8_SHIFT (0x00000008) + + #define HEDMA_CIPR_CIP8_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CIPR_CIP8) + + #define HEDMA_CIPR_CIP8_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CIPR_CIP8,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CIPR_CIP9 +\*----------------------------------------------------------------------------*/ + #define HEDMA_CIPR_CIP9_MASK (0x00000200) + #define HEDMA_CIPR_CIP9_SHIFT (0x00000009) + + #define HEDMA_CIPR_CIP9_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CIPR_CIP9) + + #define HEDMA_CIPR_CIP9_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CIPR_CIP9,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CIPR_CIP10 +\*----------------------------------------------------------------------------*/ + #define HEDMA_CIPR_CIP10_MASK (0x00000400) + #define HEDMA_CIPR_CIP10_SHIFT (0x0000000A) + + #define HEDMA_CIPR_CIP10_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CIPR_CIP10) + + #define HEDMA_CIPR_CIP10_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CIPR_CIP10,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CIPR_CIP11 +\*----------------------------------------------------------------------------*/ + #define HEDMA_CIPR_CIP11_MASK (0x00000800) + #define HEDMA_CIPR_CIP11_SHIFT (0x0000000B) + + #define HEDMA_CIPR_CIP11_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CIPR_CIP11) + + #define HEDMA_CIPR_CIP11_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CIPR_CIP11,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CIPR_CIP12 +\*----------------------------------------------------------------------------*/ + #define HEDMA_CIPR_CIP12_MASK (0x00001000) + #define HEDMA_CIPR_CIP12_SHIFT (0x0000000C) + + #define HEDMA_CIPR_CIP12_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CIPR_CIP12) + + #define HEDMA_CIPR_CIP12_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CIPR_CIP12,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CIPR_CIP13 +\*----------------------------------------------------------------------------*/ + #define HEDMA_CIPR_CIP13_MASK (0x00002000) + #define HEDMA_CIPR_CIP13_SHIFT (0x0000000D) + + #define HEDMA_CIPR_CIP13_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CIPR_CIP13) + + #define HEDMA_CIPR_CIP13_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CIPR_CIP13,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CIPR_CIP14 +\*----------------------------------------------------------------------------*/ + #define HEDMA_CIPR_CIP14_MASK (0x00004000) + #define HEDMA_CIPR_CIP14_SHIFT (0x0000000E) + + #define HEDMA_CIPR_CIP14_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CIPR_CIP14) + + #define HEDMA_CIPR_CIP14_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CIPR_CIP14,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CIPR_CIP15 +\*----------------------------------------------------------------------------*/ + #define HEDMA_CIPR_CIP15_MASK (0x00008000) + #define HEDMA_CIPR_CIP15_SHIFT (0x0000000F) + + #define HEDMA_CIPR_CIP15_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CIPR_CIP15) + + #define HEDMA_CIPR_CIP15_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CIPR_CIP15,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CIPR +\*----------------------------------------------------------------------------*/ + #define HEDMA_CIPR_GET(RegAddr) HREG32_GET(RegAddr) + #define HEDMA_CIPR_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HEDMA_CIPR_CFG(RegAddr,cip0,cip1,cip2,cip3,cip4,cip5,cip6,cip7,\ + cip8,cip9,cip10,cip11,cip12,cip13,cip14,cip15) REG32(RegAddr)=(UINT32)(\ + HFIELD_SHIFT(HEDMA_CIPR_CIP0,cip0)|\ + HFIELD_SHIFT(HEDMA_CIPR_CIP1,cip1)|\ + HFIELD_SHIFT(HEDMA_CIPR_CIP2,cip2)|\ + HFIELD_SHIFT(HEDMA_CIPR_CIP3,cip3)|\ + HFIELD_SHIFT(HEDMA_CIPR_CIP4,cip4)|\ + HFIELD_SHIFT(HEDMA_CIPR_CIP5,cip5)|\ + HFIELD_SHIFT(HEDMA_CIPR_CIP6,cip6)|\ + HFIELD_SHIFT(HEDMA_CIPR_CIP7,cip7)|\ + HFIELD_SHIFT(HEDMA_CIPR_CIP8,cip8)|\ + HFIELD_SHIFT(HEDMA_CIPR_CIP9,cip9)|\ + HFIELD_SHIFT(HEDMA_CIPR_CIP10,cip10)|\ + HFIELD_SHIFT(HEDMA_CIPR_CIP11,cip11)|\ + HFIELD_SHIFT(HEDMA_CIPR_CIP12,cip12)|\ + HFIELD_SHIFT(HEDMA_CIPR_CIP13,cip13)|\ + HFIELD_SHIFT(HEDMA_CIPR_CIP14,cip14)|\ + HFIELD_SHIFT(HEDMA_CIPR_CIP15,cip15)\ + ) + +/******************************************************************************\ +* HEDMA_CIER - channel interrupt enable register +* +* Fields: +* (RW) HEDMA_CIER_CIE0 +* (RW) HEDMA_CIER_CIE1 +* (RW) HEDMA_CIER_CIE2 +* (RW) HEDMA_CIER_CIE3 +* (RW) HEDMA_CIER_CIE4 +* (RW) HEDMA_CIER_CIE5 +* (RW) HEDMA_CIER_CIE6 +* (RW) HEDMA_CIER_CIE7 +* (RW) HEDMA_CIER_CIE8 +* (RW) HEDMA_CIER_CIE9 +* (RW) HEDMA_CIER_CIE10 +* (RW) HEDMA_CIER_CIE11 +* (RW) HEDMA_CIER_CIE12 +* (RW) HEDMA_CIER_CIE13 +* (RW) HEDMA_CIER_CIE14 +* (RW) HEDMA_CIER_CIE15 +* +\******************************************************************************/ + #define HEDMA_CIER_ADDR (HEDMA_BASE0_ADDR+0xFFE8) + #define HEDMA_CIER REG32(HEDMA_CIER_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CIER_CIE0 +\*----------------------------------------------------------------------------*/ + #define HEDMA_CIER_CIE0_MASK (0x00000001) + #define HEDMA_CIER_CIE0_SHIFT (0x00000000) + + #define HEDMA_CIER_CIE0_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CIER_CIE0) + + #define HEDMA_CIER_CIE0_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CIER_CIE0,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CIER_CIE1 +\*----------------------------------------------------------------------------*/ + #define HEDMA_CIER_CIE1_MASK (0x00000002) + #define HEDMA_CIER_CIE1_SHIFT (0x00000001) + + #define HEDMA_CIER_CIE1_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CIER_CIE1) + + #define HEDMA_CIER_CIE1_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CIER_CIE1,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CIER_CIE2 +\*----------------------------------------------------------------------------*/ + #define HEDMA_CIER_CIE2_MASK (0x00000004) + #define HEDMA_CIER_CIE2_SHIFT (0x00000002) + + #define HEDMA_CIER_CIE2_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CIER_CIE2) + + #define HEDMA_CIER_CIE2_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CIER_CIE2,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CIER_CIE3 +\*----------------------------------------------------------------------------*/ + #define HEDMA_CIER_CIE3_MASK (0x00000008) + #define HEDMA_CIER_CIE3_SHIFT (0x00000003) + + #define HEDMA_CIER_CIE3_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CIER_CIE3) + + #define HEDMA_CIER_CIE3_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CIER_CIE3,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CIER_CIE4 +\*----------------------------------------------------------------------------*/ + #define HEDMA_CIER_CIE4_MASK (0x00000010) + #define HEDMA_CIER_CIE4_SHIFT (0x00000004) + + #define HEDMA_CIER_CIE4_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CIER_CIE4) + + #define HEDMA_CIER_CIE4_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CIER_CIE4,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CIER_CIE5 +\*----------------------------------------------------------------------------*/ + #define HEDMA_CIER_CIE5_MASK (0x00000020) + #define HEDMA_CIER_CIE5_SHIFT (0x00000005) + + #define HEDMA_CIER_CIE5_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CIER_CIE5) + + #define HEDMA_CIER_CIE5_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CIER_CIE5,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CIER_CIE6 +\*----------------------------------------------------------------------------*/ + #define HEDMA_CIER_CIE6_MASK (0x00000040) + #define HEDMA_CIER_CIE6_SHIFT (0x00000006) + + #define HEDMA_CIER_CIE6_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CIER_CIE6) + + #define HEDMA_CIER_CIE6_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CIER_CIE6,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CIER_CIE7 +\*----------------------------------------------------------------------------*/ + #define HEDMA_CIER_CIE7_MASK (0x00000080) + #define HEDMA_CIER_CIE7_SHIFT (0x00000007) + + #define HEDMA_CIER_CIE7_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CIER_CIE7) + + #define HEDMA_CIER_CIE7_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CIER_CIE7,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CIER_CIE8 +\*----------------------------------------------------------------------------*/ + #define HEDMA_CIER_CIE8_MASK (0x00000100) + #define HEDMA_CIER_CIE8_SHIFT (0x00000008) + + #define HEDMA_CIER_CIE8_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CIER_CIE8) + + #define HEDMA_CIER_CIE8_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CIER_CIE8,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CIER_CIE9 +\*----------------------------------------------------------------------------*/ + #define HEDMA_CIER_CIE9_MASK (0x00000200) + #define HEDMA_CIER_CIE9_SHIFT (0x00000009) + + #define HEDMA_CIER_CIE9_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CIER_CIE9) + + #define HEDMA_CIER_CIE9_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CIER_CIE9,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CIER_CIE10 +\*----------------------------------------------------------------------------*/ + #define HEDMA_CIER_CIE10_MASK (0x00000400) + #define HEDMA_CIER_CIE10_SHIFT (0x0000000A) + + #define HEDMA_CIER_CIE10_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CIER_CIE10) + + #define HEDMA_CIER_CIE10_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CIER_CIE10,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CIER_CIE11 +\*----------------------------------------------------------------------------*/ + #define HEDMA_CIER_CIE11_MASK (0x00000800) + #define HEDMA_CIER_CIE11_SHIFT (0x0000000B) + + #define HEDMA_CIER_CIE11_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CIER_CIE11) + + #define HEDMA_CIER_CIE11_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CIER_CIE11,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CIER_CIE12 +\*----------------------------------------------------------------------------*/ + #define HEDMA_CIER_CIE12_MASK (0x00001000) + #define HEDMA_CIER_CIE12_SHIFT (0x0000000C) + + #define HEDMA_CIER_CIE12_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CIER_CIE12) + + #define HEDMA_CIER_CIE12_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CIER_CIE12,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CIER_CIE13 +\*----------------------------------------------------------------------------*/ + #define HEDMA_CIER_CIE13_MASK (0x00002000) + #define HEDMA_CIER_CIE13_SHIFT (0x0000000D) + + #define HEDMA_CIER_CIE13_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CIER_CIE13) + + #define HEDMA_CIER_CIE13_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CIER_CIE13,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CIER_CIE14 +\*----------------------------------------------------------------------------*/ + #define HEDMA_CIER_CIE14_MASK (0x00004000) + #define HEDMA_CIER_CIE14_SHIFT (0x0000000E) + + #define HEDMA_CIER_CIE14_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CIER_CIE14) + + #define HEDMA_CIER_CIE14_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CIER_CIE14,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CIER_CIE15 +\*----------------------------------------------------------------------------*/ + #define HEDMA_CIER_CIE15_MASK (0x00008000) + #define HEDMA_CIER_CIE15_SHIFT (0x0000000F) + + #define HEDMA_CIER_CIE15_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CIER_CIE15) + + #define HEDMA_CIER_CIE15_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CIER_CIE15,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CIER +\*----------------------------------------------------------------------------*/ + #define HEDMA_CIER_GET(RegAddr) HREG32_GET(RegAddr) + #define HEDMA_CIER_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HEDMA_CIER_CFG(RegAddr,cie0,cie1,cie2,cie3,cie4,cie5,cie6,cie7,\ + cie8,cie9,cie10,cie11,cie12,cie13,cie14,cie15) REG32(RegAddr)=(UINT32)(\ + HFIELD_SHIFT(HEDMA_CIER_CIE0,cie0)|\ + HFIELD_SHIFT(HEDMA_CIER_CIE1,cie1)|\ + HFIELD_SHIFT(HEDMA_CIER_CIE2,cie2)|\ + HFIELD_SHIFT(HEDMA_CIER_CIE3,cie3)|\ + HFIELD_SHIFT(HEDMA_CIER_CIE4,cie4)|\ + HFIELD_SHIFT(HEDMA_CIER_CIE5,cie5)|\ + HFIELD_SHIFT(HEDMA_CIER_CIE6,cie6)|\ + HFIELD_SHIFT(HEDMA_CIER_CIE7,cie7)|\ + HFIELD_SHIFT(HEDMA_CIER_CIE8,cie8)|\ + HFIELD_SHIFT(HEDMA_CIER_CIE9,cie9)|\ + HFIELD_SHIFT(HEDMA_CIER_CIE10,cie10)|\ + HFIELD_SHIFT(HEDMA_CIER_CIE11,cie11)|\ + HFIELD_SHIFT(HEDMA_CIER_CIE12,cie12)|\ + HFIELD_SHIFT(HEDMA_CIER_CIE13,cie13)|\ + HFIELD_SHIFT(HEDMA_CIER_CIE14,cie14)|\ + HFIELD_SHIFT(HEDMA_CIER_CIE15,cie15)\ + ) + +/******************************************************************************\ +* HEDMA_CCER - channel chain enable register +* +* Fields: +* (RW) HEDMA_CCER_CCE8 +* (RW) HEDMA_CCER_CCE9 +* (RW) HEDMA_CCER_CCE10 +* (RW) HEDMA_CCER_CCE11 +* +\******************************************************************************/ + #define HEDMA_CCER_ADDR (HEDMA_BASE0_ADDR+0xFFEC) + #define HEDMA_CCER REG32(HEDMA_CCER_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CCER_CCE8 +\*----------------------------------------------------------------------------*/ + #define HEDMA_CCER_CCE8_MASK (0x00000100) + #define HEDMA_CCER_CCE8_SHIFT (0x00000008) + + #define HEDMA_CCER_CCE8_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CCER_CCE8) + + #define HEDMA_CCER_CCE8_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CCER_CCE8,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CCER_CCE9 +\*----------------------------------------------------------------------------*/ + #define HEDMA_CCER_CCE9_MASK (0x00000200) + #define HEDMA_CCER_CCE9_SHIFT (0x00000009) + + #define HEDMA_CCER_CCE9_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CCER_CCE9) + + #define HEDMA_CCER_CCE9_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CCER_CCE9,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CCER_CCE10 +\*----------------------------------------------------------------------------*/ + #define HEDMA_CCER_CCE10_MASK (0x00000400) + #define HEDMA_CCER_CCE10_SHIFT (0x0000000A) + + #define HEDMA_CCER_CCE10_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CCER_CCE10) + + #define HEDMA_CCER_CCE10_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CCER_CCE10,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CCER_CCE11 +\*----------------------------------------------------------------------------*/ + #define HEDMA_CCER_CCE11_MASK (0x00000800) + #define HEDMA_CCER_CCE11_SHIFT (0x0000000B) + + #define HEDMA_CCER_CCE11_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_CCER_CCE11) + + #define HEDMA_CCER_CCE11_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_CCER_CCE11,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_CCER +\*----------------------------------------------------------------------------*/ + #define HEDMA_CCER_GET(RegAddr) HREG32_GET(RegAddr) + #define HEDMA_CCER_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HEDMA_CCER_CFG(RegAddr,cce8,cce9,cce10,cce11)\ + REG32(RegAddr)=(UINT32)(\ + HFIELD_SHIFT(HEDMA_CCER_CCE8,cce8)|\ + HFIELD_SHIFT(HEDMA_CCER_CCE9,cce9)|\ + HFIELD_SHIFT(HEDMA_CCER_CCE10,cce10)|\ + HFIELD_SHIFT(HEDMA_CCER_CCE11,cce11)\ + ) + +/******************************************************************************\ +* HEDMA_ER - event register +* +* Fields: +* (R) HEDMA_ER_EVT0 +* (R) HEDMA_ER_EVT1 +* (R) HEDMA_ER_EVT2 +* (R) HEDMA_ER_EVT3 +* (R) HEDMA_ER_EVT4 +* (R) HEDMA_ER_EVT5 +* (R) HEDMA_ER_EVT6 +* (R) HEDMA_ER_EVT7 +* (R) HEDMA_ER_EVT8 +* (R) HEDMA_ER_EVT9 +* (R) HEDMA_ER_EVT10 +* (R) HEDMA_ER_EVT11 +* (R) HEDMA_ER_EVT12 +* (R) HEDMA_ER_EVT13 +* (R) HEDMA_ER_EVT14 +* (R) HEDMA_ER_EVT15 +* +\******************************************************************************/ + #define HEDMA_ER_ADDR (HEDMA_BASE0_ADDR+0xFFF0) + #define HEDMA_ER REG32(HEDMA_ER_ADDR) + +/*----------------------------------------------------------------------------*\ +* (R) HEDMA_ER_EVT0 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ER_EVT0_MASK (0x00000001) + #define HEDMA_ER_EVT0_SHIFT (0x00000000) + + #define HEDMA_ER_EVT0_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ER_EVT0) + +/*----------------------------------------------------------------------------*\ +* (R) HEDMA_ER_EVT1 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ER_EVT1_MASK (0x00000002) + #define HEDMA_ER_EVT1_SHIFT (0x00000001) + + #define HEDMA_ER_EVT1_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ER_EVT1) + +/*----------------------------------------------------------------------------*\ +* (R) HEDMA_ER_EVT2 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ER_EVT2_MASK (0x00000004) + #define HEDMA_ER_EVT2_SHIFT (0x00000002) + + #define HEDMA_ER_EVT2_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ER_EVT2) + +/*----------------------------------------------------------------------------*\ +* (R) HEDMA_ER_EVT3 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ER_EVT3_MASK (0x00000008) + #define HEDMA_ER_EVT3_SHIFT (0x00000003) + + #define HEDMA_ER_EVT3_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ER_EVT3) + +/*----------------------------------------------------------------------------*\ +* (R) HEDMA_ER_EVT4 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ER_EVT4_MASK (0x00000010) + #define HEDMA_ER_EVT4_SHIFT (0x00000004) + + #define HEDMA_ER_EVT4_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ER_EVT4) + +/*----------------------------------------------------------------------------*\ +* (R) HEDMA_ER_EVT5 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ER_EVT5_MASK (0x00000020) + #define HEDMA_ER_EVT5_SHIFT (0x00000005) + + #define HEDMA_ER_EVT5_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ER_EVT5) + +/*----------------------------------------------------------------------------*\ +* (R) HEDMA_ER_EVT6 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ER_EVT6_MASK (0x00000040) + #define HEDMA_ER_EVT6_SHIFT (0x00000006) + + #define HEDMA_ER_EVT6_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ER_EVT6) + +/*----------------------------------------------------------------------------*\ +* (R) HEDMA_ER_EVT7 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ER_EVT7_MASK (0x00000080) + #define HEDMA_ER_EVT7_SHIFT (0x00000007) + + #define HEDMA_ER_EVT7_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ER_EVT7) + +/*----------------------------------------------------------------------------*\ +* (R) HEDMA_ER_EVT8 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ER_EVT8_MASK (0x00000100) + #define HEDMA_ER_EVT8_SHIFT (0x00000008) + + #define HEDMA_ER_EVT8_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ER_EVT8) + +/*----------------------------------------------------------------------------*\ +* (R) HEDMA_ER_EVT9 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ER_EVT9_MASK (0x00000200) + #define HEDMA_ER_EVT9_SHIFT (0x00000009) + + #define HEDMA_ER_EVT9_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ER_EVT9) + +/*----------------------------------------------------------------------------*\ +* (R) HEDMA_ER_EVT10 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ER_EVT10_MASK (0x00000400) + #define HEDMA_ER_EVT10_SHIFT (0x0000000A) + + #define HEDMA_ER_EVT10_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ER_EVT10) + +/*----------------------------------------------------------------------------*\ +* (R) HEDMA_ER_EVT11 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ER_EVT11_MASK (0x00000800) + #define HEDMA_ER_EVT11_SHIFT (0x0000000B) + + #define HEDMA_ER_EVT11_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ER_EVT11) + +/*----------------------------------------------------------------------------*\ +* (R) HEDMA_ER_EVT12 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ER_EVT12_MASK (0x00001000) + #define HEDMA_ER_EVT12_SHIFT (0x0000000C) + + #define HEDMA_ER_EVT12_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ER_EVT12) + +/*----------------------------------------------------------------------------*\ +* (R) HEDMA_ER_EVT13 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ER_EVT13_MASK (0x00002000) + #define HEDMA_ER_EVT13_SHIFT (0x0000000D) + + #define HEDMA_ER_EVT13_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ER_EVT13) + +/*----------------------------------------------------------------------------*\ +* (R) HEDMA_ER_EVT14 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ER_EVT14_MASK (0x00004000) + #define HEDMA_ER_EVT14_SHIFT (0x0000000E) + + #define HEDMA_ER_EVT14_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ER_EVT14) + +/*----------------------------------------------------------------------------*\ +* (R) HEDMA_ER_EVT15 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ER_EVT15_MASK (0x00008000) + #define HEDMA_ER_EVT15_SHIFT (0x0000000F) + + #define HEDMA_ER_EVT15_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ER_EVT15) + +/*----------------------------------------------------------------------------*\ +* (R) HEDMA_ER +\*----------------------------------------------------------------------------*/ + #define HEDMA_ER_GET(RegAddr) HREG32_GET(RegAddr) + +/******************************************************************************\ +* HEDMA_EER - event enable register +* +* Fields: +* (RW) HEDMA_EER_EE0 +* (RW) HEDMA_EER_EE1 +* (RW) HEDMA_EER_EE2 +* (RW) HEDMA_EER_EE3 +* (RW) HEDMA_EER_EE4 +* (RW) HEDMA_EER_EE5 +* (RW) HEDMA_EER_EE6 +* (RW) HEDMA_EER_EE7 +* (RW) HEDMA_EER_EE8 +* (RW) HEDMA_EER_EE9 +* (RW) HEDMA_EER_EE10 +* (RW) HEDMA_EER_EE11 +* (RW) HEDMA_EER_EE12 +* (RW) HEDMA_EER_EE13 +* (RW) HEDMA_EER_EE14 +* (RW) HEDMA_EER_EE15 +* +\******************************************************************************/ + #define HEDMA_EER_ADDR (HEDMA_BASE0_ADDR+0xFFF4) + #define HEDMA_EER REG32(HEDMA_EER_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_EER_EE0 +\*----------------------------------------------------------------------------*/ + #define HEDMA_EER_EE0_MASK (0x00000001) + #define HEDMA_EER_EE0_SHIFT (0x00000000) + + #define HEDMA_EER_EE0_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_EER_EE0) + + #define HEDMA_EER_EE0_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_EER_EE0,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_EER_EE1 +\*----------------------------------------------------------------------------*/ + #define HEDMA_EER_EE1_MASK (0x00000002) + #define HEDMA_EER_EE1_SHIFT (0x00000001) + + #define HEDMA_EER_EE1_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_EER_EE1) + + #define HEDMA_EER_EE1_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_EER_EE1,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_EER_EE2 +\*----------------------------------------------------------------------------*/ + #define HEDMA_EER_EE2_MASK (0x00000004) + #define HEDMA_EER_EE2_SHIFT (0x00000002) + + #define HEDMA_EER_EE2_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_EER_EE2) + + #define HEDMA_EER_EE2_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_EER_EE2,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_EER_EE3 +\*----------------------------------------------------------------------------*/ + #define HEDMA_EER_EE3_MASK (0x00000008) + #define HEDMA_EER_EE3_SHIFT (0x00000003) + + #define HEDMA_EER_EE3_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_EER_EE3) + + #define HEDMA_EER_EE3_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_EER_EE3,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_EER_EE4 +\*----------------------------------------------------------------------------*/ + #define HEDMA_EER_EE4_MASK (0x00000010) + #define HEDMA_EER_EE4_SHIFT (0x00000004) + + #define HEDMA_EER_EE4_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_EER_EE4) + + #define HEDMA_EER_EE4_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_EER_EE4,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_EER_EE5 +\*----------------------------------------------------------------------------*/ + #define HEDMA_EER_EE5_MASK (0x00000020) + #define HEDMA_EER_EE5_SHIFT (0x00000005) + + #define HEDMA_EER_EE5_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_EER_EE5) + + #define HEDMA_EER_EE5_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_EER_EE5,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_EER_EE6 +\*----------------------------------------------------------------------------*/ + #define HEDMA_EER_EE6_MASK (0x00000040) + #define HEDMA_EER_EE6_SHIFT (0x00000006) + + #define HEDMA_EER_EE6_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_EER_EE6) + + #define HEDMA_EER_EE6_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_EER_EE6,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_EER_EE7 +\*----------------------------------------------------------------------------*/ + #define HEDMA_EER_EE7_MASK (0x00000080) + #define HEDMA_EER_EE7_SHIFT (0x00000007) + + #define HEDMA_EER_EE7_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_EER_EE7) + + #define HEDMA_EER_EE7_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_EER_EE7,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_EER_EE8 +\*----------------------------------------------------------------------------*/ + #define HEDMA_EER_EE8_MASK (0x00000100) + #define HEDMA_EER_EE8_SHIFT (0x00000008) + + #define HEDMA_EER_EE8_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_EER_EE8) + + #define HEDMA_EER_EE8_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_EER_EE8,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_EER_EE9 +\*----------------------------------------------------------------------------*/ + #define HEDMA_EER_EE9_MASK (0x00000200) + #define HEDMA_EER_EE9_SHIFT (0x00000009) + + #define HEDMA_EER_EE9_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_EER_EE9) + + #define HEDMA_EER_EE9_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_EER_EE9,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_EER_EE10 +\*----------------------------------------------------------------------------*/ + #define HEDMA_EER_EE10_MASK (0x00000400) + #define HEDMA_EER_EE10_SHIFT (0x0000000A) + + #define HEDMA_EER_EE10_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_EER_EE10) + + #define HEDMA_EER_EE10_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_EER_EE10,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_EER_EE11 +\*----------------------------------------------------------------------------*/ + #define HEDMA_EER_EE11_MASK (0x00000800) + #define HEDMA_EER_EE11_SHIFT (0x0000000B) + + #define HEDMA_EER_EE11_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_EER_EE11) + + #define HEDMA_EER_EE11_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_EER_EE11,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_EER_EE12 +\*----------------------------------------------------------------------------*/ + #define HEDMA_EER_EE12_MASK (0x00001000) + #define HEDMA_EER_EE12_SHIFT (0x0000000C) + + #define HEDMA_EER_EE12_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_EER_EE12) + + #define HEDMA_EER_EE12_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_EER_EE12,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_EER_EE13 +\*----------------------------------------------------------------------------*/ + #define HEDMA_EER_EE13_MASK (0x00002000) + #define HEDMA_EER_EE13_SHIFT (0x0000000D) + + #define HEDMA_EER_EE13_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_EER_EE13) + + #define HEDMA_EER_EE13_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_EER_EE13,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_EER_EE14 +\*----------------------------------------------------------------------------*/ + #define HEDMA_EER_EE14_MASK (0x00004000) + #define HEDMA_EER_EE14_SHIFT (0x0000000E) + + #define HEDMA_EER_EE14_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_EER_EE14) + + #define HEDMA_EER_EE14_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_EER_EE14,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_EER_EE15 +\*----------------------------------------------------------------------------*/ + #define HEDMA_EER_EE15_MASK (0x00008000) + #define HEDMA_EER_EE15_SHIFT (0x0000000F) + + #define HEDMA_EER_EE15_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_EER_EE15) + + #define HEDMA_EER_EE15_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_EER_EE15,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_EER +\*----------------------------------------------------------------------------*/ + #define HEDMA_EER_GET(RegAddr) HREG32_GET(RegAddr) + #define HEDMA_EER_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HEDMA_EER_CFG(RegAddr,ee0,ee1,ee2,ee3,ee4,ee5,ee6,ee7,\ + ee8,ee9,ee10,ee11,ee12,ee13,ee14,ee15) REG32(RegAddr)=(UINT32)(\ + HFIELD_SHIFT(HEDMA_EER_EE0,ee0)|\ + HFIELD_SHIFT(HEDMA_EER_EE1,ee1)|\ + HFIELD_SHIFT(HEDMA_EER_EE2,ee2)|\ + HFIELD_SHIFT(HEDMA_EER_EE3,ee3)|\ + HFIELD_SHIFT(HEDMA_EER_EE4,ee4)|\ + HFIELD_SHIFT(HEDMA_EER_EE5,ee5)|\ + HFIELD_SHIFT(HEDMA_EER_EE6,ee6)|\ + HFIELD_SHIFT(HEDMA_EER_EE7,ee7)|\ + HFIELD_SHIFT(HEDMA_EER_EE8,ee8)|\ + HFIELD_SHIFT(HEDMA_EER_EE9,ee9)|\ + HFIELD_SHIFT(HEDMA_EER_EE10,ee10)|\ + HFIELD_SHIFT(HEDMA_EER_EE11,ee11)|\ + HFIELD_SHIFT(HEDMA_EER_EE12,ee12)|\ + HFIELD_SHIFT(HEDMA_EER_EE13,ee13)|\ + HFIELD_SHIFT(HEDMA_EER_EE14,ee14)|\ + HFIELD_SHIFT(HEDMA_EER_EE15,ee15)\ + ) + +/******************************************************************************\ +* HEDMA_ECR - event clear register +* +* Fields: +* (RW) HEDMA_ECR_EC0 +* (RW) HEDMA_ECR_EC1 +* (RW) HEDMA_ECR_EC2 +* (RW) HEDMA_ECR_EC3 +* (RW) HEDMA_ECR_EC4 +* (RW) HEDMA_ECR_EC5 +* (RW) HEDMA_ECR_EC6 +* (RW) HEDMA_ECR_EC7 +* (RW) HEDMA_ECR_EC8 +* (RW) HEDMA_ECR_EC9 +* (RW) HEDMA_ECR_EC10 +* (RW) HEDMA_ECR_EC11 +* (RW) HEDMA_ECR_EC12 +* (RW) HEDMA_ECR_EC13 +* (RW) HEDMA_ECR_EC14 +* (RW) HEDMA_ECR_EC15 +* +\******************************************************************************/ + #define HEDMA_ECR_ADDR (HEDMA_BASE0_ADDR+0xFFF8) + #define HEDMA_ECR REG32(HEDMA_ECR_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_ECR_EC0 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ECR_EC0_MASK (0x00000001) + #define HEDMA_ECR_EC0_SHIFT (0x00000000) + + #define HEDMA_ECR_EC0_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ECR_EC0) + + #define HEDMA_ECR_EC0_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_ECR_EC0,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_ECR_EC1 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ECR_EC1_MASK (0x00000002) + #define HEDMA_ECR_EC1_SHIFT (0x00000001) + + #define HEDMA_ECR_EC1_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ECR_EC1) + + #define HEDMA_ECR_EC1_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_ECR_EC1,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_ECR_EC2 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ECR_EC2_MASK (0x00000004) + #define HEDMA_ECR_EC2_SHIFT (0x00000002) + + #define HEDMA_ECR_EC2_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ECR_EC2) + + #define HEDMA_ECR_EC2_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_ECR_EC2,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_ECR_EC3 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ECR_EC3_MASK (0x00000008) + #define HEDMA_ECR_EC3_SHIFT (0x00000003) + + #define HEDMA_ECR_EC3_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ECR_EC3) + + #define HEDMA_ECR_EC3_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_ECR_EC3,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_ECR_EC4 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ECR_EC4_MASK (0x00000010) + #define HEDMA_ECR_EC4_SHIFT (0x00000004) + + #define HEDMA_ECR_EC4_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ECR_EC4) + + #define HEDMA_ECR_EC4_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_ECR_EC4,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_ECR_EC5 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ECR_EC5_MASK (0x00000020) + #define HEDMA_ECR_EC5_SHIFT (0x00000005) + + #define HEDMA_ECR_EC5_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ECR_EC5) + + #define HEDMA_ECR_EC5_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_ECR_EC5,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_ECR_EC6 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ECR_EC6_MASK (0x00000040) + #define HEDMA_ECR_EC6_SHIFT (0x00000006) + + #define HEDMA_ECR_EC6_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ECR_EC6) + + #define HEDMA_ECR_EC6_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_ECR_EC6,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_ECR_EC7 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ECR_EC7_MASK (0x00000080) + #define HEDMA_ECR_EC7_SHIFT (0x00000007) + + #define HEDMA_ECR_EC7_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ECR_EC7) + + #define HEDMA_ECR_EC7_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_ECR_EC7,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_ECR_EC8 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ECR_EC8_MASK (0x00000100) + #define HEDMA_ECR_EC8_SHIFT (0x00000008) + + #define HEDMA_ECR_EC8_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ECR_EC8) + + #define HEDMA_ECR_EC8_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_ECR_EC8,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_ECR_EC9 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ECR_EC9_MASK (0x00000200) + #define HEDMA_ECR_EC9_SHIFT (0x00000009) + + #define HEDMA_ECR_EC9_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ECR_EC9) + + #define HEDMA_ECR_EC9_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_ECR_EC9,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_ECR_EC10 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ECR_EC10_MASK (0x00000400) + #define HEDMA_ECR_EC10_SHIFT (0x0000000A) + + #define HEDMA_ECR_EC10_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ECR_EC10) + + #define HEDMA_ECR_EC10_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_ECR_EC10,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_ECR_EC11 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ECR_EC11_MASK (0x00000800) + #define HEDMA_ECR_EC11_SHIFT (0x0000000B) + + #define HEDMA_ECR_EC11_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ECR_EC11) + + #define HEDMA_ECR_EC11_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_ECR_EC11,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_ECR_EC12 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ECR_EC12_MASK (0x00001000) + #define HEDMA_ECR_EC12_SHIFT (0x0000000C) + + #define HEDMA_ECR_EC12_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ECR_EC12) + + #define HEDMA_ECR_EC12_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_ECR_EC12,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_ECR_EC13 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ECR_EC13_MASK (0x00002000) + #define HEDMA_ECR_EC13_SHIFT (0x0000000D) + + #define HEDMA_ECR_EC13_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ECR_EC13) + + #define HEDMA_ECR_EC13_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_ECR_EC13,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_ECR_EC14 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ECR_EC14_MASK (0x00004000) + #define HEDMA_ECR_EC14_SHIFT (0x0000000E) + + #define HEDMA_ECR_EC14_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ECR_EC14) + + #define HEDMA_ECR_EC14_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_ECR_EC14,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_ECR_EC15 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ECR_EC15_MASK (0x00008000) + #define HEDMA_ECR_EC15_SHIFT (0x0000000F) + + #define HEDMA_ECR_EC15_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ECR_EC15) + + #define HEDMA_ECR_EC15_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_ECR_EC15,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_ECR +\*----------------------------------------------------------------------------*/ + #define HEDMA_ECR_GET(RegAddr) HREG32_GET(RegAddr) + #define HEDMA_ECR_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HEDMA_ECR_CFG(RegAddr,ec0,ec1,ec2,ec3,ec4,ec5,ec6,ec7,\ + ec8,ec9,ec10,ec11,ec12,ec13,ec14,ec15) REG32(RegAddr)=(UINT32)(\ + HFIELD_SHIFT(HEDMA_ECR_EC0,ec0)|\ + HFIELD_SHIFT(HEDMA_ECR_EC1,ec1)|\ + HFIELD_SHIFT(HEDMA_ECR_EC2,ec2)|\ + HFIELD_SHIFT(HEDMA_ECR_EC3,ec3)|\ + HFIELD_SHIFT(HEDMA_ECR_EC4,ec4)|\ + HFIELD_SHIFT(HEDMA_ECR_EC5,ec5)|\ + HFIELD_SHIFT(HEDMA_ECR_EC6,ec6)|\ + HFIELD_SHIFT(HEDMA_ECR_EC7,ec7)|\ + HFIELD_SHIFT(HEDMA_ECR_EC8,ec8)|\ + HFIELD_SHIFT(HEDMA_ECR_EC9,ec9)|\ + HFIELD_SHIFT(HEDMA_ECR_EC10,ec10)|\ + HFIELD_SHIFT(HEDMA_ECR_EC11,ec11)|\ + HFIELD_SHIFT(HEDMA_ECR_EC12,ec12)|\ + HFIELD_SHIFT(HEDMA_ECR_EC13,ec13)|\ + HFIELD_SHIFT(HEDMA_ECR_EC14,ec14)|\ + HFIELD_SHIFT(HEDMA_ECR_EC15,ec15)\ + ) + +/******************************************************************************\ +* HEDMA_ESR - event set register +* +* Fields: +* (RW) HEDMA_ESR_ES0 +* (RW) HEDMA_ESR_ES1 +* (RW) HEDMA_ESR_ES2 +* (RW) HEDMA_ESR_ES3 +* (RW) HEDMA_ESR_ES4 +* (RW) HEDMA_ESR_ES5 +* (RW) HEDMA_ESR_ES6 +* (RW) HEDMA_ESR_ES7 +* (RW) HEDMA_ESR_ES8 +* (RW) HEDMA_ESR_ES9 +* (RW) HEDMA_ESR_ES10 +* (RW) HEDMA_ESR_ES11 +* (RW) HEDMA_ESR_ES12 +* (RW) HEDMA_ESR_ES13 +* (RW) HEDMA_ESR_ES14 +* (RW) HEDMA_ESR_ES15 +* +\******************************************************************************/ + #define HEDMA_ESR_ADDR (HEDMA_BASE0_ADDR+0xFFFC) + #define HEDMA_ESR REG32(HEDMA_ESR_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_ESR_ES0 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ESR_ES0_MASK (0x00000001) + #define HEDMA_ESR_ES0_SHIFT (0x00000000) + + #define HEDMA_ESR_ES0_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ESR_ES0) + + #define HEDMA_ESR_ES0_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_ESR_ES0,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_ESR_ES1 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ESR_ES1_MASK (0x00000002) + #define HEDMA_ESR_ES1_SHIFT (0x00000001) + + #define HEDMA_ESR_ES1_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ESR_ES1) + + #define HEDMA_ESR_ES1_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_ESR_ES1,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_ESR_ES2 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ESR_ES2_MASK (0x00000004) + #define HEDMA_ESR_ES2_SHIFT (0x00000002) + + #define HEDMA_ESR_ES2_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ESR_ES2) + + #define HEDMA_ESR_ES2_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_ESR_ES2,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_ESR_ES3 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ESR_ES3_MASK (0x00000008) + #define HEDMA_ESR_ES3_SHIFT (0x00000003) + + #define HEDMA_ESR_ES3_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ESR_ES3) + + #define HEDMA_ESR_ES3_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_ESR_ES3,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_ESR_ES4 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ESR_ES4_MASK (0x00000010) + #define HEDMA_ESR_ES4_SHIFT (0x00000004) + + #define HEDMA_ESR_ES4_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ESR_ES4) + + #define HEDMA_ESR_ES4_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_ESR_ES4,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_ESR_ES5 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ESR_ES5_MASK (0x00000020) + #define HEDMA_ESR_ES5_SHIFT (0x00000005) + + #define HEDMA_ESR_ES5_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ESR_ES5) + + #define HEDMA_ESR_ES5_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_ESR_ES5,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_ESR_ES6 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ESR_ES6_MASK (0x00000040) + #define HEDMA_ESR_ES6_SHIFT (0x00000006) + + #define HEDMA_ESR_ES6_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ESR_ES6) + + #define HEDMA_ESR_ES6_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_ESR_ES6,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_ESR_ES7 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ESR_ES7_MASK (0x00000080) + #define HEDMA_ESR_ES7_SHIFT (0x00000007) + + #define HEDMA_ESR_ES7_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ESR_ES7) + + #define HEDMA_ESR_ES7_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_ESR_ES7,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_ESR_ES8 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ESR_ES8_MASK (0x00000100) + #define HEDMA_ESR_ES8_SHIFT (0x00000008) + + #define HEDMA_ESR_ES8_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ESR_ES8) + + #define HEDMA_ESR_ES8_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_ESR_ES8,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_ESR_ES9 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ESR_ES9_MASK (0x00000200) + #define HEDMA_ESR_ES9_SHIFT (0x00000009) + + #define HEDMA_ESR_ES9_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ESR_ES9) + + #define HEDMA_ESR_ES9_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_ESR_ES9,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_ESR_ES10 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ESR_ES10_MASK (0x00000400) + #define HEDMA_ESR_ES10_SHIFT (0x0000000A) + + #define HEDMA_ESR_ES10_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ESR_ES10) + + #define HEDMA_ESR_ES10_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_ESR_ES10,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_ESR_ES11 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ESR_ES11_MASK (0x00000800) + #define HEDMA_ESR_ES11_SHIFT (0x0000000B) + + #define HEDMA_ESR_ES11_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ESR_ES11) + + #define HEDMA_ESR_ES11_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_ESR_ES11,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_ESR_ES12 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ESR_ES12_MASK (0x00001000) + #define HEDMA_ESR_ES12_SHIFT (0x0000000C) + + #define HEDMA_ESR_ES12_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ESR_ES12) + + #define HEDMA_ESR_ES12_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_ESR_ES12,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_ESR_ES13 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ESR_ES13_MASK (0x00002000) + #define HEDMA_ESR_ES13_SHIFT (0x0000000D) + + #define HEDMA_ESR_ES13_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ESR_ES13) + + #define HEDMA_ESR_ES13_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_ESR_ES13,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_ESR_ES14 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ESR_ES14_MASK (0x00004000) + #define HEDMA_ESR_ES14_SHIFT (0x0000000E) + + #define HEDMA_ESR_ES14_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ESR_ES14) + + #define HEDMA_ESR_ES14_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_ESR_ES14,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_ESR_ES15 +\*----------------------------------------------------------------------------*/ + #define HEDMA_ESR_ES15_MASK (0x00008000) + #define HEDMA_ESR_ES15_SHIFT (0x0000000F) + + #define HEDMA_ESR_ES15_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEDMA_ESR_ES15) + + #define HEDMA_ESR_ES15_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEDMA_ESR_ES15,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEDMA_ESR +\*----------------------------------------------------------------------------*/ + #define HEDMA_ESR_GET(RegAddr) HREG32_GET(RegAddr) + #define HEDMA_ESR_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HEDMA_ESR_CFG(RegAddr,es0,es1,es2,es3,es4,es5,es6,es7,\ + es8,es9,es10,es11,es12,es13,es14,es15) REG32(RegAddr)=(UINT32)(\ + HFIELD_SHIFT(HEDMA_ESR_ES0,es0)|\ + HFIELD_SHIFT(HEDMA_ESR_ES1,es1)|\ + HFIELD_SHIFT(HEDMA_ESR_ES2,es2)|\ + HFIELD_SHIFT(HEDMA_ESR_ES3,es3)|\ + HFIELD_SHIFT(HEDMA_ESR_ES4,es4)|\ + HFIELD_SHIFT(HEDMA_ESR_ES5,es5)|\ + HFIELD_SHIFT(HEDMA_ESR_ES6,es6)|\ + HFIELD_SHIFT(HEDMA_ESR_ES7,es7)|\ + HFIELD_SHIFT(HEDMA_ESR_ES8,es8)|\ + HFIELD_SHIFT(HEDMA_ESR_ES9,es9)|\ + HFIELD_SHIFT(HEDMA_ESR_ES10,es10)|\ + HFIELD_SHIFT(HEDMA_ESR_ES11,es11)|\ + HFIELD_SHIFT(HEDMA_ESR_ES12,es12)|\ + HFIELD_SHIFT(HEDMA_ESR_ES13,es13)|\ + HFIELD_SHIFT(HEDMA_ESR_ES14,es14)|\ + HFIELD_SHIFT(HEDMA_ESR_ES15,es15)\ + ) + +/*----------------------------------------------------------------------------*/ + +#endif /* EDMA_SUPPORT */ +#endif /* _EDMAHAL_H_ */ +/******************************************************************************\ +* End of edmahal.h +\******************************************************************************/ +/******************************************************************************\ +* Copyright (C) 1999-2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... emifhal.h +* DATE CREATED.. 06/12/1999 +* LAST MODIFIED. 03/08/2000 +* +*------------------------------------------------------------------------------ +* DESCRIPTION: (HAL interface file for the EMIF module) +* +* Registers Covered: +* (RW) HEMIF_GBLCTL - global control register +* (RW) HEMIF_CE0CTL - chip-enable space 0 control register +* (RW) HEMIF_CE1CTL - chip-enable space 1 control register +* (RW) HEMIF_CE2CTL - chip-enable space 2 control register +* (RW) HEMIF_CE3CTL - chip-enable space 3 control register +* (RW) HEMIF_SDCTL - SDRAM control register +* (RW) HEMIF_SDTIM - SDRAM timing register +* (RW) HEMIF_SDEXT - SDRAM extension register (1) +* +* (1) Only available for C11_SUPPORT +* +\******************************************************************************/ +#ifndef _EMIFHAL_H_ +#define _EMIFHAL_H_ + +#if (EMIF_SUPPORT) +#define HEMIF_BASE_ADDR (HCHIP_PERBASE_ADDR+0x00000000) + +/******************************************************************************\ +* HEMIF_GBLCTL - global control register +* +* Fields: +* (R) HEMIF_GBLCTL_MAP (2) +* (RW) HEMIF_GBLCTL_RBTR8 (2) +* (RW) HEMIF_GBLCTL_SSCRT (2)(3) +* (RW) HEMIF_GBLCTL_CLK2EN (3) +* (RW) HEMIF_GBLCTL_CLK1EN +* (RW) HEMIF_GBLCTL_SSCEN (2) +* (RW) HEMIF_GBLCTL_SDCEN (2) +* (RW) HEMIF_GBLCTL_NOHOLD +* (R) HEMIF_GBLCTL_HOLDA +* (R) HEMIF_GBLCTL_HOLD +* (R) HEMIF_GBLCTL_ARDY +* (R) HEMIF_GBLCTL_BUSREQ (1) +* +* (1) Field only exists for C11_SUPPORT +* (2) Field does not exist for C11_SUPPORT +* (3) Field does not exist for CHIP_6202, CHIP_6203 +* +\******************************************************************************/ + #define HEMIF_GBLCTL_ADDR (HEMIF_BASE_ADDR+0x0000) + #define HEMIF_GBLCTL REG32(HEMIF_GBLCTL_ADDR) + +/*----------------------------------------------------------------------------*\ +* (R) HEMIF_GBLCTL_MAP +\*----------------------------------------------------------------------------*/ +#if !(C11_SUPPORT) + #define HEMIF_GBLCTL_MAP_MASK (0x00000001) + #define HEMIF_GBLCTL_MAP_SHIFT (0x00000000) +#else + #define HEMIF_GBLCTL_MAP_MASK (0x00000000) + #define HEMIF_GBLCTL_MAP_SHIFT (0x00000000) +#endif + + #define HEMIF_GBLCTL_MAP_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_GBLCTL_MAP) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_GBLCTL_RBTR8 +\*----------------------------------------------------------------------------*/ +#if !(C11_SUPPORT) + #define HEMIF_GBLCTL_RBTR8_MASK (0x00000002) + #define HEMIF_GBLCTL_RBTR8_SHIFT (0x00000001) +#else + #define HEMIF_GBLCTL_RBTR8_MASK (0x00000000) + #define HEMIF_GBLCTL_RBTR8_SHIFT (0x00000000) +#endif + + #define HEMIF_GBLCTL_RBTR8_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_GBLCTL_RBTR8) + + #define HEMIF_GBLCTL_RBTR8_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_GBLCTL_RBTR8,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_GBLCTL_SSCRT +\*----------------------------------------------------------------------------*/ +#if !(CHIP_6202|CHIP_6203|C11_SUPPORT) + #define HEMIF_GBLCTL_SSCRT_MASK (0x00000004) + #define HEMIF_GBLCTL_SSCRT_SHIFT (0x00000002) +#else + #define HEMIF_GBLCTL_SSCRT_MASK (0x00000000) + #define HEMIF_GBLCTL_SSCRT_SHIFT (0x00000000) +#endif + + #define HEMIF_GBLCTL_SSCRT_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_GBLCTL_SSCRT) + + #define HEMIF_GBLCTL_SSCRT_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_GBLCTL_SSCRT,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_GBLCTL_CLK2EN +\*----------------------------------------------------------------------------*/ +#if !(CHIP_6202|CHIP_6203) + #define HEMIF_GBLCTL_CLK2EN_MASK (0x00000008) + #define HEMIF_GBLCTL_CLK2EN_SHIFT (0x00000003) +#else + #define HEMIF_GBLCTL_CLK2EN_MASK (0x00000000) + #define HEMIF_GBLCTL_CLK2EN_SHIFT (0x00000000) +#endif + + #define HEMIF_GBLCTL_CLK2EN_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_GBLCTL_CLK2EN) + + #define HEMIF_GBLCTL_CLK2EN_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_GBLCTL_CLK2EN,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_GBLCTL_CLK1EN +\*----------------------------------------------------------------------------*/ + #define HEMIF_GBLCTL_CLK1EN_MASK (0x00000010) + #define HEMIF_GBLCTL_CLK1EN_SHIFT (0x00000004) + + #define HEMIF_GBLCTL_CLK1EN_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_GBLCTL_CLK1EN) + + #define HEMIF_GBLCTL_CLK1EN_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_GBLCTL_CLK1EN,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_GBLCTL_SSCEN +\*----------------------------------------------------------------------------*/ +#if !(C11_SUPPORT) + #define HEMIF_GBLCTL_SSCEN_MASK (0x00000020) + #define HEMIF_GBLCTL_SSCEN_SHIFT (0x00000005) +#else + #define HEMIF_GBLCTL_SSCEN_MASK (0x00000000) + #define HEMIF_GBLCTL_SSCEN_SHIFT (0x00000000) +#endif + + #define HEMIF_GBLCTL_SSCEN_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_GBLCTL_SSCEN) + + #define HEMIF_GBLCTL_SSCEN_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_GBLCTL_SSCEN,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_GBLCTL_SDCEN +\*----------------------------------------------------------------------------*/ +#if !(C11_SUPPORT) + #define HEMIF_GBLCTL_SDCEN_MASK (0x00000040) + #define HEMIF_GBLCTL_SDCEN_SHIFT (0x00000006) +#else + #define HEMIF_GBLCTL_SDCEN_MASK (0x00000000) + #define HEMIF_GBLCTL_SDCEN_SHIFT (0x00000000) +#endif + + #define HEMIF_GBLCTL_SDCEN_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_GBLCTL_SDCEN) + + #define HEMIF_GBLCTL_SDCEN_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_GBLCTL_SDCEN,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_GBLCTL_NOHOLD +\*----------------------------------------------------------------------------*/ + #define HEMIF_GBLCTL_NOHOLD_MASK (0x00000080) + #define HEMIF_GBLCTL_NOHOLD_SHIFT (0x00000007) + + #define HEMIF_GBLCTL_NOHOLD_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_GBLCTL_NOHOLD) + + #define HEMIF_GBLCTL_NOHOLD_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_GBLCTL_NOHOLD,Val) + +/*----------------------------------------------------------------------------*\ +* (R) HEMIF_GBLCTL_HOLDA +\*----------------------------------------------------------------------------*/ + #define HEMIF_GBLCTL_HOLDA_MASK (0x00000100) + #define HEMIF_GBLCTL_HOLDA_SHIFT (0x00000008) + + #define HEMIF_GBLCTL_HOLDA_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_GBLCTL_HOLDA) + +/*----------------------------------------------------------------------------*\ +* (R) HEMIF_GBLCTL_HOLD +\*----------------------------------------------------------------------------*/ + #define HEMIF_GBLCTL_HOLD_MASK (0x00000200) + #define HEMIF_GBLCTL_HOLD_SHIFT (0x00000009) + + #define HEMIF_GBLCTL_HOLD_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_GBLCTL_HOLD) + +/*----------------------------------------------------------------------------*\ +* (R) HEMIF_GBLCTL_ARDY +\*----------------------------------------------------------------------------*/ + #define HEMIF_GBLCTL_ARDY_MASK (0x00000400) + #define HEMIF_GBLCTL_ARDY_SHIFT (0x0000000A) + + #define HEMIF_GBLCTL_ARDY_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_GBLCTL_ARDY) + +/*----------------------------------------------------------------------------*\ +* (R) HEMIF_GBLCTL_BUSREQ +\*----------------------------------------------------------------------------*/ +#if (C11_SUPPORT) + #define HEMIF_GBLCTL_BUSREQ_MASK (0x00000800) + #define HEMIF_GBLCTL_BUSREQ_SHIFT (0x0000000B) +#else + #define HEMIF_GBLCTL_BUSREQ_MASK (0x00000000) + #define HEMIF_GBLCTL_BUSREQ_SHIFT (0x00000000) +#endif + + #define HEMIF_GBLCTL_BUSREQ_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_GBLCTL_BUSREQ) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_GBLCTL +\*----------------------------------------------------------------------------*/ + #define HEMIF_GBLCTL_GET(RegAddr) HREG32_GET(RegAddr) + #define HEMIF_GBLCTL_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HEMIF_GBLCTL_CFG(RegAddr,rbtr8,sscrt,clk2en,clk1en,sscen,sdcen,\ + nohold) REG32(RegAddr) = (UINT32)( \ + HFIELD_SHIFT(HEMIF_GBLCTL_RBTR8,rbtr8)|\ + HFIELD_SHIFT(HEMIF_GBLCTL_SSCRT,sscrt)|\ + HFIELD_SHIFT(HEMIF_GBLCTL_CLK2EN,clk2en)|\ + HFIELD_SHIFT(HEMIF_GBLCTL_CLK1EN,clk1en)|\ + HFIELD_SHIFT(HEMIF_GBLCTL_SSCEN,sscen)|\ + HFIELD_SHIFT(HEMIF_GBLCTL_SDCEN,sdcen)|\ + HFIELD_SHIFT(HEMIF_GBLCTL_NOHOLD,nohold)|\ + 0x00003000 \ + ) + +/*----------------------------------------------------------------------------*/ + +/******************************************************************************\ +* HEMIF_CE0CTL - chip-enable space 0 control register +* HEMIF_CE1CTL - chip-enable space 1 control register +* HEMIF_CE2CTL - chip-enable space 2 control register +* HEMIF_CE3CTL - chip-enable space 3 control register +* +* Fields: +* (RW) HEMIF_CECTL_RDHLD +* (RW) HEMIF_CECTL_WRHLDMSB (1) +* (RW) HEMIF_CECTL_MTYPE +* (RW) HEMIF_CECTL_RDSTRB +* (RW) HEMIF_CECTL_TA (1) +* (RW) HEMIF_CECTL_RDSETUP +* (RW) HEMIF_CECTL_WRHLD +* (RW) HEMIF_CECTL_WRSTRB +* (RW) HEMIF_CECTL_WRSETUP +* +* (1) Field only exists for C11_SUPPORT +* +\******************************************************************************/ + #define HEMIF_CE0CTL_ADDR (HEMIF_BASE_ADDR+0x0008) + #define HEMIF_CE1CTL_ADDR (HEMIF_BASE_ADDR+0x0004) + #define HEMIF_CE2CTL_ADDR (HEMIF_BASE_ADDR+0x0010) + #define HEMIF_CE3CTL_ADDR (HEMIF_BASE_ADDR+0x0014) + + #define HEMIF_CE0CTL REG32(HEMIF_CE0CTL_ADDR) + #define HEMIF_CE1CTL REG32(HEMIF_CE1CTL_ADDR) + #define HEMIF_CE2CTL REG32(HEMIF_CE2CTL_ADDR) + #define HEMIF_CE3CTL REG32(HEMIF_CE3CTL_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_CECTL_RDHLD +\*----------------------------------------------------------------------------*/ +#if (C11_SUPPORT) + #define HEMIF_CECTL_RDHLD_MASK (0x00000007) + #define HEMIF_CECTL_RDHLD_SHIFT (0x00000000) +#elif (C01_SUPPORT) + #define HEMIF_CECTL_RDHLD_MASK (0x00000003) + #define HEMIF_CECTL_RDHLD_SHIFT (0x00000000) +#endif + + #define HEMIF_CECTL_RDHLD_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_CECTL_RDHLD) + + #define HEMIF_CECTL_RDHLD_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_CECTL_RDHLD,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_CECTL_WRHLDMSB +\*----------------------------------------------------------------------------*/ +#if (C11_SUPPORT) + #define HEMIF_CECTL_WRHLDMSB_MASK (0x00000008) + #define HEMIF_CECTL_WRHLDMSB_SHIFT (0x00000003) +#else + #define HEMIF_CECTL_WRHLDMSB_MASK (0x00000000) + #define HEMIF_CECTL_WRHLDMSB_SHIFT (0x00000000) +#endif + + #define HEMIF_CECTL_WRHLDMSB_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_CECTL_WRHLDMSB) + + #define HEMIF_CECTL_WRHLDMSB_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_CECTL_WRHLDMSB,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_CECTL_MTYPE +\*----------------------------------------------------------------------------*/ +#if (C11_SUPPORT) + #define HEMIF_CECTL_MTYPE_MASK (0x000000F0) + #define HEMIF_CECTL_MTYPE_SHIFT (0x00000004) +#elif (C01_SUPPORT) + #define HEMIF_CECTL_MTYPE_MASK (0x00000070) + #define HEMIF_CECTL_MTYPE_SHIFT (0x00000004) +#else + #define HEMIF_CECTL_MTYPE_MASK (0x00000000) + #define HEMIF_CECTL_MTYPE_SHIFT (0x00000000) +#endif + + #define HEMIF_CECTL_MTYPE_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_CECTL_MTYPE) + + #define HEMIF_CECTL_MTYPE_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_CECTL_MTYPE,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_CECTL_RDSTRB +\*----------------------------------------------------------------------------*/ + #define HEMIF_CECTL_RDSTRB_MASK (0x00003F00) + #define HEMIF_CECTL_RDSTRB_SHIFT (0x00000008) + + #define HEMIF_CECTL_RDSTRB_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_CECTL_RDSTRB) + + #define HEMIF_CECTL_RDSTRB_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_CECTL_RDSTRB,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_CECTL_TA +\*----------------------------------------------------------------------------*/ +#if (C11_SUPPORT) + #define HEMIF_CECTL_TA_MASK (0x0000C000) + #define HEMIF_CECTL_TA_SHIFT (0x0000000E) +#else + #define HEMIF_CECTL_TA_MASK (0x00000000) + #define HEMIF_CECTL_TA_SHIFT (0x00000000) +#endif + + #define HEMIF_CECTL_TA_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_CECTL_TA) + + #define HEMIF_CECTL_TA_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_CECTL_TA,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_CECTL_RDSETUP +\*----------------------------------------------------------------------------*/ + #define HEMIF_CECTL_RDSETUP_MASK (0x000F0000) + #define HEMIF_CECTL_RDSETUP_SHIFT (0x00000010) + + #define HEMIF_CECTL_RDSETUP_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_CECTL_RDSETUP) + + #define HEMIF_CECTL_RDSETUP_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_CECTL_RDSETUP,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_CECTL_WRHLD +\*----------------------------------------------------------------------------*/ + #define HEMIF_CECTL_WRHLD_MASK (0x00300000) + #define HEMIF_CECTL_WRHLD_SHIFT (0x00000014) + + #define HEMIF_CECTL_WRHLD_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_CECTL_WRHLD) + + #define HEMIF_CECTL_WRHLD_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_CECTL_WRHLD,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_CECTL_WRSTRB +\*----------------------------------------------------------------------------*/ + #define HEMIF_CECTL_WRSTRB_MASK (0x0FC00000) + #define HEMIF_CECTL_WRSTRB_SHIFT (0x00000016) + + #define HEMIF_CECTL_WRSTRB_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_CECTL_WRSTRB) + + #define HEMIF_CECTL_WRSTRB_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_CECTL_WRSTRB,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_CECTL_WRSETUP +\*----------------------------------------------------------------------------*/ + #define HEMIF_CECTL_WRSETUP_MASK (0xF0000000) + #define HEMIF_CECTL_WRSETUP_SHIFT (0x0000001C) + + #define HEMIF_CECTL_WRSETUP_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_CECTL_WRSETUP) + + #define HEMIF_CECTL_WRSETUP_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_CECTL_WRSETUP,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_CECTL +\*----------------------------------------------------------------------------*/ + #define HEMIF_CECTL_GET(RegAddr) HREG32_GET(RegAddr) + #define HEMIF_CECTL_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HEMIF_CECTL_CFG(RegAddr,rdhld,wrhldmsb,mtype,rdstrb,ta,\ + rdsetup,wrhld,wrstrb,wrsetup) REG32(RegAddr) = (UINT32)( \ + HFIELD_SHIFT(HEMIF_CECTL_RDHLD,rdhld)|\ + HFIELD_SHIFT(HEMIF_CECTL_WRHLDMSB,wrhldmsb)|\ + HFIELD_SHIFT(HEMIF_CECTL_MTYPE,mtype)|\ + HFIELD_SHIFT(HEMIF_CECTL_RDSTRB,rdstrb)|\ + HFIELD_SHIFT(HEMIF_CECTL_TA,ta)|\ + HFIELD_SHIFT(HEMIF_CECTL_RDSETUP,rdsetup)|\ + HFIELD_SHIFT(HEMIF_CECTL_WRHLD,wrhld)|\ + HFIELD_SHIFT(HEMIF_CECTL_WRSTRB,wrstrb)|\ + HFIELD_SHIFT(HEMIF_CECTL_WRSETUP,wrsetup)\ + ) + +/******************************************************************************\ +* HEMIF_SDCTL - SDRAM control register +* +* Fields: +* (RW) HEMIF_SDCTL_TRC +* (RW) HEMIF_SDCTL_TRP +* (RW) HEMIF_SDCTL_TRCD +* (W) HEMIF_SDCTL_INIT +* (RW) HEMIF_SDCTL_RFEN +* (RW) HEMIF_SDCTL_SDWID (1) +* (RW) HEMIF_SDCTL_SDCSZ (2) +* (RW) HEMIF_SDCTL_SDRSZ (2) +* (RW) HEMIF_SDCTL_SDBSZ (2) +* +* (1) Field only exists for C01_SUPPORT +* (2) Field only exists for C11_SUPPORT +* +\******************************************************************************/ + #define HEMIF_SDCTL_ADDR (HEMIF_BASE_ADDR+0x0018) + #define HEMIF_SDCTL REG32(HEMIF_SDCTL_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_SDCTL_TRC +\*----------------------------------------------------------------------------*/ + #define HEMIF_SDCTL_TRC_MASK (0x0000F000) + #define HEMIF_SDCTL_TRC_SHIFT (0x0000000C) + + #define HEMIF_SDCTL_TRC_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_SDCTL_TRC) + + #define HEMIF_SDCTL_TRC_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_SDCTL_TRC,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_SDCTL_TRP +\*----------------------------------------------------------------------------*/ + #define HEMIF_SDCTL_TRP_MASK (0x000F0000) + #define HEMIF_SDCTL_TRP_SHIFT (0x00000010) + + #define HEMIF_SDCTL_TRP_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_SDCTL_TRP) + + #define HEMIF_SDCTL_TRP_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_SDCTL_TRP,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_SDCTL_TRCD +\*----------------------------------------------------------------------------*/ + #define HEMIF_SDCTL_TRCD_MASK (0x00F00000) + #define HEMIF_SDCTL_TRCD_SHIFT (0x00000014) + + #define HEMIF_SDCTL_TRCD_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_SDCTL_TRCD) + + #define HEMIF_SDCTL_TRCD_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_SDCTL_TRCD,Val) + +/*----------------------------------------------------------------------------*\ +* (W) HEMIF_SDCTL_INIT +\*----------------------------------------------------------------------------*/ + #define HEMIF_SDCTL_INIT_MASK (0x01000000) + #define HEMIF_SDCTL_INIT_SHIFT (0x00000018) + + #define HEMIF_SDCTL_INIT_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_SDCTL_INIT,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_SDCTL_RFEN +\*----------------------------------------------------------------------------*/ + #define HEMIF_SDCTL_RFEN_MASK (0x02000000) + #define HEMIF_SDCTL_RFEN_SHIFT (0x00000019) + + #define HEMIF_SDCTL_RFEN_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_SDCTL_RFEN) + + #define HEMIF_SDCTL_RFEN_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_SDCTL_RFEN,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_SDCTL_SDWID +\*----------------------------------------------------------------------------*/ +#if (C01_SUPPORT) + #define HEMIF_SDCTL_SDWID_MASK (0x04000000) + #define HEMIF_SDCTL_SDWID_SHIFT (0x0000001A) +#else + #define HEMIF_SDCTL_SDWID_MASK (0x00000000) + #define HEMIF_SDCTL_SDWID_SHIFT (0x00000000) +#endif + + #define HEMIF_SDCTL_SDWID_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_SDCTL_SDWID) + + #define HEMIF_SDCTL_SDWID_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_SDCTL_SDWID,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_SDCTL_SDCSZ +\*----------------------------------------------------------------------------*/ +#if (C11_SUPPORT) + #define HEMIF_SDCTL_SDCSZ_MASK (0x0C000000) + #define HEMIF_SDCTL_SDCSZ_SHIFT (0x0000001A) +#else + #define HEMIF_SDCTL_SDCSZ_MASK (0x00000000) + #define HEMIF_SDCTL_SDCSZ_SHIFT (0x00000000) +#endif + + #define HEMIF_SDCTL_SDCSZ_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_SDCTL_SDCSZ) + + #define HEMIF_SDCTL_SDCSZ_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_SDCTL_SDCSZ,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_SDCTL_SDRSZ +\*----------------------------------------------------------------------------*/ +#if (C11_SUPPORT) + #define HEMIF_SDCTL_SDRSZ_MASK (0x30000000) + #define HEMIF_SDCTL_SDRSZ_SHIFT (0x0000001C) +#else + #define HEMIF_SDCTL_SDRSZ_MASK (0x00000000) + #define HEMIF_SDCTL_SDRSZ_SHIFT (0x00000000) +#endif + + #define HEMIF_SDCTL_SDRSZ_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_SDCTL_SDRSZ) + + #define HEMIF_SDCTL_SDRSZ_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_SDCTL_SDRSZ,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_SDCTL_SDBSZ +\*----------------------------------------------------------------------------*/ +#if (C11_SUPPORT) + #define HEMIF_SDCTL_SDBSZ_MASK (0x40000000) + #define HEMIF_SDCTL_SDBSZ_SHIFT (0x0000001E) +#else + #define HEMIF_SDCTL_SDBSZ_MASK (0x00000000) + #define HEMIF_SDCTL_SDBSZ_SHIFT (0x00000000) +#endif + + #define HEMIF_SDCTL_SDBSZ_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_SDCTL_SDBSZ) + + #define HEMIF_SDCTL_SDBSZ_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_SDCTL_SDBSZ,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_SDCTL +\*----------------------------------------------------------------------------*/ + #define HEMIF_SDCTL_GET(RegAddr) HREG32_GET(RegAddr) + #define HEMIF_SDCTL_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HEMIF_SDCTL_CFG(RegAddr,trc,trp,trcd,init,rfen,sdwid,\ + sdcsz,sdrsz,sdbsz) REG32(RegAddr) = (UINT32)( \ + HFIELD_SHIFT(HEMIF_SDCTL_TRC,trc)|\ + HFIELD_SHIFT(HEMIF_SDCTL_TRP,trp)|\ + HFIELD_SHIFT(HEMIF_SDCTL_TRCD,trcd)|\ + HFIELD_SHIFT(HEMIF_SDCTL_INIT,init)|\ + HFIELD_SHIFT(HEMIF_SDCTL_RFEN,rfen)|\ + HFIELD_SHIFT(HEMIF_SDCTL_SDWID,sdwid)|\ + HFIELD_SHIFT(HEMIF_SDCTL_SDCSZ,sdcsz)|\ + HFIELD_SHIFT(HEMIF_SDCTL_SDRSZ,sdrsz)|\ + HFIELD_SHIFT(HEMIF_SDCTL_SDBSZ,sdbsz)\ + ) + +/******************************************************************************\ +* HEMIF_SDTIM - SDRAM timing register +* +* Fields: +* (RW) HEMIF_SDTIM_PERIOD +* (R) HEMIF_SDTIM_CNTR +* (RW) HEMIF_SDTIM_XRFR (1) +* +* (1) Field only exists for C11_SUPPORT +* +\******************************************************************************/ + #define HEMIF_SDTIM_ADDR (HEMIF_BASE_ADDR+0x001C) + #define HEMIF_SDTIM REG32(HEMIF_SDTIM_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_SDTIM_PERIOD +\*----------------------------------------------------------------------------*/ + #define HEMIF_SDTIM_PERIOD_MASK (0x00000FFF) + #define HEMIF_SDTIM_PERIOD_SHIFT (0x00000000) + + #define HEMIF_SDTIM_PERIOD_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_SDTIM_PERIOD) + + #define HEMIF_SDTIM_PERIOD_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_SDTIM_PERIOD,Val) + +/*----------------------------------------------------------------------------*\ +* (R) HEMIF_SDTIM_CNTR +\*----------------------------------------------------------------------------*/ + #define HEMIF_SDTIM_CNTR_MASK (0x00FFF000) + #define HEMIF_SDTIM_CNTR_SHIFT (0x0000000C) + + #define HEMIF_SDTIM_CNTR_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_SDTIM_CNTR) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_SDTIM_XRFR +\*----------------------------------------------------------------------------*/ +#if (C11_SUPPORT) + #define HEMIF_SDTIM_XRFR_MASK (0x03000000) + #define HEMIF_SDTIM_XRFR_SHIFT (0x00000018) +#else + #define HEMIF_SDTIM_XRFR_MASK (0x00000000) + #define HEMIF_SDTIM_XRFR_SHIFT (0x00000000) +#endif + + #define HEMIF_SDTIM_XRFR_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_SDTIM_XRFR) + + #define HEMIF_SDTIM_XRFR_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_SDTIM_XRFR,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_SDTIM +\*----------------------------------------------------------------------------*/ + #define HEMIF_SDTIM_GET(RegAddr) HREG32_GET(RegAddr) + #define HEMIF_SDTIM_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HEMIF_SDTIM_CFG(RegAddr,period,xrfr) REG32(RegAddr)=(UINT32)(\ + HFIELD_SHIFT(HEMIF_SDTIM_PERIOD,period)|\ + HFIELD_SHIFT(HEMIF_SDTIM_XRFR,xrfr)\ + ) + +/******************************************************************************\ +* HEMIF_SDEXT - SDRAM extension register (1) +* (1) Only available for C11_SUPPORT +* +* Fields: +* (RW) HEMIF_SDEXT_TCL +* (RW) HEMIF_SDEXT_TRAS +* (RW) HEMIF_SDEXT_TRRD +* (RW) HEMIF_SDEXT_TWR +* (RW) HEMIF_SDEXT_THZP +* (RW) HEMIF_SDEXT_RD2RD +* (RW) HEMIF_SDEXT_RD2DEAC +* (RW) HEMIF_SDEXT_RD2WR +* (RW) HEMIF_SDEXT_R2WDQM +* (RW) HEMIF_SDEXT_WR2WR +* (RW) HEMIF_SDEXT_WR2DEAC +* (RW) HEMIF_SDEXT_WR2RD +* +\******************************************************************************/ +#if (C11_SUPPORT) + #define HEMIF_SDEXT_ADDR (HEMIF_BASE_ADDR+0x0020) + #define HEMIF_SDEXT REG32(HEMIF_SDEXT_ADDR) +#else + #define HEMIF_SDEXT_ADDR HCHIP_NULL_ADDR + #define HEMIF_SDEXT REG32(HEMIF_SDEXT_ADDR) +#endif + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_SDEXT_TCL +\*----------------------------------------------------------------------------*/ +#if (C11_SUPPORT) + #define HEMIF_SDEXT_TCL_MASK (0x00000001) + #define HEMIF_SDEXT_TCL_SHIFT (0x00000000) +#else + #define HEMIF_SDEXT_TCL_MASK (0x00000000) + #define HEMIF_SDEXT_TCL_SHIFT (0x00000000) +#endif + + #define HEMIF_SDEXT_TCL_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_SDEXT_TCL) + + #define HEMIF_SDEXT_TCL_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_SDEXT_TCL,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_SDEXT_TRAS +\*----------------------------------------------------------------------------*/ +#if (C11_SUPPORT) + #define HEMIF_SDEXT_TRAS_MASK (0x0000000D) + #define HEMIF_SDEXT_TRAS_SHIFT (0x00000001) +#else + #define HEMIF_SDEXT_TRAS_MASK (0x00000000) + #define HEMIF_SDEXT_TRAS_SHIFT (0x00000000) +#endif + + #define HEMIF_SDEXT_TRAS_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_SDEXT_TRAS) + + #define HEMIF_SDEXT_TRAS_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_SDEXT_TRAS,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_SDEXT_TRRD +\*----------------------------------------------------------------------------*/ +#if (C11_SUPPORT) + #define HEMIF_SDEXT_TRRD_MASK (0x00000010) + #define HEMIF_SDEXT_TRRD_SHIFT (0x00000004) +#else + #define HEMIF_SDEXT_TRRD_MASK (0x00000000) + #define HEMIF_SDEXT_TRRD_SHIFT (0x00000000) +#endif + + #define HEMIF_SDEXT_TRRD_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_SDEXT_TRRD) + + #define HEMIF_SDEXT_TRRD_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_SDEXT_TRRD,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_SDEXT_TWR +\*----------------------------------------------------------------------------*/ +#if (C11_SUPPORT) + #define HEMIF_SDEXT_TWR_MASK (0x00000060) + #define HEMIF_SDEXT_TWR_SHIFT (0x00000005) +#else + #define HEMIF_SDEXT_TWR_MASK (0x00000000) + #define HEMIF_SDEXT_TWR_SHIFT (0x00000000) +#endif + + #define HEMIF_SDEXT_TWR_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_SDEXT_TWR) + + #define HEMIF_SDEXT_TWR_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_SDEXT_TWR,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_SDEXT_THZP +\*----------------------------------------------------------------------------*/ +#if (C11_SUPPORT) + #define HEMIF_SDEXT_THZP_MASK (0x00000180) + #define HEMIF_SDEXT_THZP_SHIFT (0x00000007) +#else + #define HEMIF_SDEXT_THZP_MASK (0x00000000) + #define HEMIF_SDEXT_THZP_SHIFT (0x00000000) +#endif + + #define HEMIF_SDEXT_THZP_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_SDEXT_THZP) + + #define HEMIF_SDEXT_THZP_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_SDEXT_THZP,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_SDEXT_RD2RD +\*----------------------------------------------------------------------------*/ +#if (C11_SUPPORT) + #define HEMIF_SDEXT_RD2RD_MASK (0x00000200) + #define HEMIF_SDEXT_RD2RD_SHIFT (0x00000009) +#else + #define HEMIF_SDEXT_RD2RD_MASK (0x00000000) + #define HEMIF_SDEXT_RD2RD_SHIFT (0x00000000) +#endif + + #define HEMIF_SDEXT_RD2RD_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_SDEXT_RD2RD) + + #define HEMIF_SDEXT_RD2RD_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_SDEXT_RD2RD,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_SDEXT_RD2DEAC +\*----------------------------------------------------------------------------*/ +#if (C11_SUPPORT) + #define HEMIF_SDEXT_RD2DEAC_MASK (0x00000C00) + #define HEMIF_SDEXT_RD2DEAC_SHIFT (0x0000000A) +#else + #define HEMIF_SDEXT_RD2DEAC_MASK (0x00000000) + #define HEMIF_SDEXT_RD2DEAC_SHIFT (0x00000000) +#endif + + #define HEMIF_SDEXT_RD2DEAC_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_SDEXT_RD2DEAC) + + #define HEMIF_SDEXT_RD2DEAC_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_SDEXT_RD2DEAC,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_SDEXT_RD2WR +\*----------------------------------------------------------------------------*/ +#if (C11_SUPPORT) + #define HEMIF_SDEXT_RD2WR_MASK (0x00007000) + #define HEMIF_SDEXT_RD2WR_SHIFT (0x0000000C) +#else + #define HEMIF_SDEXT_RD2WR_MASK (0x00000000) + #define HEMIF_SDEXT_RD2WR_SHIFT (0x00000000) +#endif + + #define HEMIF_SDEXT_RD2WR_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_SDEXT_RD2WR) + + #define HEMIF_SDEXT_RD2WR_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_SDEXT_RD2WR,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_SDEXT_R2WDQM +\*----------------------------------------------------------------------------*/ +#if (C11_SUPPORT) + #define HEMIF_SDEXT_R2WDQM_MASK (0x00018000) + #define HEMIF_SDEXT_R2WDQM_SHIFT (0x0000000F) +#else + #define HEMIF_SDEXT_R2WDQM_MASK (0x00000000) + #define HEMIF_SDEXT_R2WDQM_SHIFT (0x00000000) +#endif + + #define HEMIF_SDEXT_R2WDQM_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_SDEXT_R2WDQM) + + #define HEMIF_SDEXT_R2WDQM_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_SDEXT_R2WDQM,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_SDEXT_WR2WR +\*----------------------------------------------------------------------------*/ +#if (C11_SUPPORT) + #define HEMIF_SDEXT_WR2WR_MASK (0x00020000) + #define HEMIF_SDEXT_WR2WR_SHIFT (0x00000011) +#else + #define HEMIF_SDEXT_WR2WR_MASK (0x00000000) + #define HEMIF_SDEXT_WR2WR_SHIFT (0x00000000) +#endif + + #define HEMIF_SDEXT_WR2WR_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_SDEXT_WR2WR) + + #define HEMIF_SDEXT_WR2WR_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_SDEXT_WR2WR,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_SDEXT_WR2DEAC +\*----------------------------------------------------------------------------*/ +#if (C11_SUPPORT) + #define HEMIF_SDEXT_WR2DEAC_MASK (0x000C0000) + #define HEMIF_SDEXT_WR2DEAC_SHIFT (0x00000012) +#else + #define HEMIF_SDEXT_WR2DEAC_MASK (0x00000000) + #define HEMIF_SDEXT_WR2DEAC_SHIFT (0x00000000) +#endif + + #define HEMIF_SDEXT_WR2DEAC_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_SDEXT_WR2DEAC) + + #define HEMIF_SDEXT_WR2DEAC_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_SDEXT_WR2DEAC,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_SDEXT_WR2RD +\*----------------------------------------------------------------------------*/ +#if (C11_SUPPORT) + #define HEMIF_SDEXT_WR2RD_MASK (0x00100000) + #define HEMIF_SDEXT_WR2RD_SHIFT (0x00000014) +#else + #define HEMIF_SDEXT_WR2RD_MASK (0x00000000) + #define HEMIF_SDEXT_WR2RD_SHIFT (0x00000000) +#endif + + #define HEMIF_SDEXT_WR2RD_GET(RegAddr) \ + HFIELD_GET(RegAddr,HEMIF_SDEXT_WR2RD) + + #define HEMIF_SDEXT_WR2RD_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HEMIF_SDEXT_WR2RD,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HEMIF_SDEXT +\*----------------------------------------------------------------------------*/ + #define HEMIF_SDEXT_GET(RegAddr) HREG32_GET(RegAddr) + #define HEMIF_SDEXT_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HEMIF_SDEXT_CFG(RegAddr,tcl,tras,trrd,twr,thzp,rd2rd,rd2deac,\ + rd2wr,r2wdqm,wr2wr,wr2deac,wr2rd) REG32(RagAddr)=(UINT32)(\ + HFIELD_SHIFT(HEMIF_SDEXT_TCL,tcl)|\ + HFIELD_SHIFT(HEMIF_SDEXT_TRAS,tras)|\ + HFIELD_SHIFT(HEMIF_SDEXT_TRRD,trrd)|\ + HFIELD_SHIFT(HEMIF_SDEXT_TWR,twr)|\ + HFIELD_SHIFT(HEMIF_SDEXT_THZP,thzp)|\ + HFIELD_SHIFT(HEMIF_SDEXT_RD2RD,rd2rd)|\ + HFIELD_SHIFT(HEMIF_SDEXT_RD2DEAC,rd2deac)|\ + HFIELD_SHIFT(HEMIF_SDEXT_RD2WR,rd2wr)|\ + HFIELD_SHIFT(HEMIF_SDEXT_R2WDQM,r2wdqm)|\ + HFIELD_SHIFT(HEMIF_SDEXT_WR2WR,wr2wr)|\ + HFIELD_SHIFT(HEMIF_SDEXT_WR2DEAC,wr2deac)|\ + HFIELD_SHIFT(HEMIF_SDEXT_WR2RD,wr2rd)\ + ) + +/******************************************************************************/ + +#endif /* EMIF_SUPPORT */ +#endif /* _EMIFHAL_H_ */ +/******************************************************************************\ +* End of emifhal.h +\******************************************************************************/ + +/******************************************************************************\ +* Copyright (C) 1999-2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... hpihal.h +* DATE CREATED.. 06/20/1999 +* LAST MODIFIED. 03/08/2000 +* +*------------------------------------------------------------------------------ +* DESCRIPTION: (HAL interface file for the HPI module) +* +* Registers Covered: +* (RW) HHPI_HPIC - HPI control register +* +\******************************************************************************/ +#ifndef _HPIHAL_H_ +#define _HPIHAL_H_ + +#if (HPI_SUPPORT) +#define HHPI_BASE_ADDR (HCHIP_PERBASE_ADDR+0x00080000) + +/******************************************************************************\ +* HHPI_HPIC - HPI control register +* +* Fields: +* (R) HHPI_HPIC_HWOB +* (RW) HHPI_HPIC_DSPINT +* (RW) HHPI_HPIC_HINT +* (R) HHPI_HPIC_HRDY +* (R) HHPI_HPIC_FETCH +* +\******************************************************************************/ + #define HHPI_HPIC_ADDR (HHPI_BASE_ADDR+0x0000) + #define HHPI_HPIC REG32(HHPI_HPIC_ADDR) + +/*----------------------------------------------------------------------------*\ +* (R) HHPI_HPIC_HWOB +\*----------------------------------------------------------------------------*/ + #define HHPI_HPIC_HWOB_MASK (0x00000001) + #define HHPI_HPIC_HWOB_SHIFT (0x00000000) + + #define HHPI_HPIC_HWOB_GET(RegAddr) \ + HFIELD_GET(RegAddr,HHPI_HPIC_HWOB) + +/*----------------------------------------------------------------------------*\ +* (RW) HHPI_HPIC_DSPINT +\*----------------------------------------------------------------------------*/ + #define HHPI_HPIC_DSPINT_MASK (0x00000002) + #define HHPI_HPIC_DSPINT_SHIFT (0x00000001) + + #define HHPI_HPIC_DSPINT_GET(RegAddr) \ + HFIELD_GET(RegAddr,HHPI_HPIC_DSPINT) + + #define HHPI_HPIC_DSPINT_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HHPI_HPIC_DSPINT,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HHPI_HPIC_HINT +\*----------------------------------------------------------------------------*/ + #define HHPI_HPIC_HINT_MASK (0x00000004) + #define HHPI_HPIC_HINT_SHIFT (0x00000002) + + #define HHPI_HPIC_HINT_GET(RegAddr) \ + HFIELD_GET(RegAddr,HHPI_HPIC_HINT) + + #define HHPI_HPIC_HINT_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HHPI_HPIC_HINT,Val) + +/*----------------------------------------------------------------------------*\ +* (R) HHPI_HPIC_HRDY +\*----------------------------------------------------------------------------*/ + #define HHPI_HPIC_HRDY_MASK (0x00000008) + #define HHPI_HPIC_HRDY_SHIFT (0x00000003) + + #define HHPI_HPIC_HRDY_GET(RegAddr) \ + HFIELD_GET(RegAddr,HHPI_HPIC_HRDY) + +/*----------------------------------------------------------------------------*\ +* (R) HHPI_HPIC_FETCH +\*----------------------------------------------------------------------------*/ + #define HHPI_HPIC_FETCH_MASK (0x00000010) + #define HHPI_HPIC_FETCH_SHIFT (0x00000004) + + #define HHPI_HPIC_FETCH_GET(RegAddr) \ + HFIELD_GET(RegAddr,HHPI_HPIC_FETCH) + +/*----------------------------------------------------------------------------*\ +* (RW) HHPI_HPIC +\*----------------------------------------------------------------------------*/ + #define HHPI_HPIC_GET(RegAddr) HREG32_GET(RegAddr) + #define HHPI_HPIC_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HHPI_HPIC_CFG(RegAddr,dspint,hint)\ + REG32(RegAddr) = (\ + HFIELD_SHIFT(HHPI_HPIC_DSPINT, dspint)|\ + HFIELD_SHIFT(HHPI_HPIC_HINT, hint)\ + ) + +/*----------------------------------------------------------------------------*/ + +#endif /* HPI_SUPPORT */ +#endif /* _HPIHAL_H_ */ +/******************************************************************************\ +* End of hpihal.h +\******************************************************************************/ + +/******************************************************************************\ +* Copyright (C) 1999-2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... irqhal.h +* DATE CREATED.. 06/20/1999 +* LAST MODIFIED. 03/08/2000 +* +*------------------------------------------------------------------------------ +* DESCRIPTION: (HAL interface file for the IRQ module) +* +* Registers Covered: +* (RW) HIRQ_MUXL - interrupt multiplexer low register +* (RW) HIRQ_MUXH - interrupt multiplexer high register +* (RW) HIRQ_EXTPOL - external interrupt polarity register +* +\******************************************************************************/ +#ifndef _IRQHAL_H_ +#define _IRQHAL_H_ + +#if (IRQ_SUPPORT) +/*============================================================================*\ +* misc declarations +\*============================================================================*/ +#define HIRQ_BASE_ADDR (HCHIP_PERBASE_ADDR+0x001C0000) + +#define HIRQ_INT_CNT (16) /* number of interrupts */ +#define HIRQ_EVENT_CNT (19) /* number of mappable events */ + +/******************************************************************************\ +* HIRQ_MUXL - interrupt multiplexer low register +* +* Fields: +* (RW) HIRQ_MUXL_INTSEL4 +* (RW) HIRQ_MUXL_INTSEL5 +* (RW) HIRQ_MUXL_INTSEL6 +* (RW) HIRQ_MUXL_INTSEL7 +* (RW) HIRQ_MUXL_INTSEL8 +* (RW) HIRQ_MUXL_INTSEL9 +* +\******************************************************************************/ + #define HIRQ_MUXL_ADDR (HIRQ_BASE_ADDR+0x0004) + #define HIRQ_MUXL REG32(HIRQ_MUXL_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HIRQ_MUXL_INTSEL4 +\*----------------------------------------------------------------------------*/ + #define HIRQ_MUXL_INTSEL4_MASK (0x0000001F) + #define HIRQ_MUXL_INTSEL4_SHIFT (0x00000000) + + #define HIRQ_MUXL_INTSEL4_GET(RegAddr) \ + HFIELD_GET(RegAddr,HIRQ_MUXL_INTSEL4) + + #define HIRQ_MUXL_INTSEL4_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HIRQ_MUXL_INTSEL4,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HIRQ_MUXL_INTSEL5 +\*----------------------------------------------------------------------------*/ + #define HIRQ_MUXL_INTSEL5_MASK (0x000003E0) + #define HIRQ_MUXL_INTSEL5_SHIFT (0x00000005) + + #define HIRQ_MUXL_INTSEL5_GET(RegAddr) \ + HFIELD_GET(RegAddr,HIRQ_MUXL_INTSEL5) + + #define HIRQ_MUXL_INTSEL5_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HIRQ_MUXL_INTSEL5,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HIRQ_MUXL_INTSEL6 +\*----------------------------------------------------------------------------*/ + #define HIRQ_MUXL_INTSEL6_MASK (0x00007C00) + #define HIRQ_MUXL_INTSEL6_SHIFT (0x0000000A) + + #define HIRQ_MUXL_INTSEL6_GET(RegAddr) \ + HFIELD_GET(RegAddr,HIRQ_MUXL_INTSEL6) + + #define HIRQ_MUXL_INTSEL6_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HIRQ_MUXL_INTSEL6,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HIRQ_MUXL_INTSEL7 +\*----------------------------------------------------------------------------*/ + #define HIRQ_MUXL_INTSEL7_MASK (0x001F0000) + #define HIRQ_MUXL_INTSEL7_SHIFT (0x00000010) + + #define HIRQ_MUXL_INTSEL7_GET(RegAddr) \ + HFIELD_GET(RegAddr,HIRQ_MUXL_INTSEL7) + + #define HIRQ_MUXL_INTSEL7_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HIRQ_MUXL_INTSEL7,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HIRQ_MUXL_INTSEL8 +\*----------------------------------------------------------------------------*/ + #define HIRQ_MUXL_INTSEL8_MASK (0x03E00000) + #define HIRQ_MUXL_INTSEL8_SHIFT (0x00000015) + + #define HIRQ_MUXL_INTSEL8_GET(RegAddr) \ + HFIELD_GET(RegAddr,HIRQ_MUXL_INTSEL8) + + #define HIRQ_MUXL_INTSEL8_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HIRQ_MUXL_INTSEL8,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HIRQ_MUXL_INTSEL9 +\*----------------------------------------------------------------------------*/ + #define HIRQ_MUXL_INTSEL9_MASK (0x7C000000) + #define HIRQ_MUXL_INTSEL9_SHIFT (0x0000001A) + + #define HIRQ_MUXL_INTSEL9_GET(RegAddr) \ + HFIELD_GET(RegAddr,HIRQ_MUXL_INTSEL9) + + #define HIRQ_MUXL_INTSEL9_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HIRQ_MUXL_INTSEL9,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HIRQ_MUXL +\*----------------------------------------------------------------------------*/ + #define HIRQ_MUXL_GET(RegAddr) HREG32_GET(RegAddr) + #define HIRQ_MUXL_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HIRQ_MUXL_CFG(RegAddr,intsel4,intsel5,intsel6,intsel7,intsel8,\ + intsel9) REG32(RegAddr) = (\ + HFIELD_SHIFT(HIRQ_MUXL_INTSEL4, intsel4)|\ + HFIELD_SHIFT(HIRQ_MUXL_INTSEL5, intsel5)|\ + HFIELD_SHIFT(HIRQ_MUXL_INTSEL6, intsel6)|\ + HFIELD_SHIFT(HIRQ_MUXL_INTSEL7, intsel7)|\ + HFIELD_SHIFT(HIRQ_MUXL_INTSEL8, intsel8)|\ + HFIELD_SHIFT(HIRQ_MUXL_INTSEL9, intsel9)\ + ) + +/******************************************************************************\ +* HIRQ_MUXH - interrupt multiplexer high register +* +* Fields: +* (RW) HIRQ_MUXH_INTSEL10 +* (RW) HIRQ_MUXH_INTSEL11 +* (RW) HIRQ_MUXH_INTSEL12 +* (RW) HIRQ_MUXH_INTSEL13 +* (RW) HIRQ_MUXH_INTSEL14 +* (RW) HIRQ_MUXH_INTSEL15 +* +\******************************************************************************/ + #define HIRQ_MUXH_ADDR (HIRQ_BASE_ADDR+0x0000) + #define HIRQ_MUXH REG32(HIRQ_MUXH_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HIRQ_MUXH_INTSEL10 +\*----------------------------------------------------------------------------*/ + #define HIRQ_MUXH_INTSEL10_MASK (0x0000001F) + #define HIRQ_MUXH_INTSEL10_SHIFT (0x00000000) + + #define HIRQ_MUXH_INTSEL10_GET(RegAddr) \ + HFIELD_GET(RegAddr,HIRQ_MUXH_INTSEL10) + + #define HIRQ_MUXH_INTSEL10_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HIRQ_MUXH_INTSEL10,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HIRQ_MUXH_INTSEL11 +\*----------------------------------------------------------------------------*/ + #define HIRQ_MUXH_INTSEL11_MASK (0x000003E0) + #define HIRQ_MUXH_INTSEL11_SHIFT (0x00000005) + + #define HIRQ_MUXH_INTSEL11_GET(RegAddr) \ + HFIELD_GET(RegAddr,HIRQ_MUXH_INTSEL11) + + #define HIRQ_MUXH_INTSEL11_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HIRQ_MUXH_INTSEL11,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HIRQ_MUXH_INTSEL12 +\*----------------------------------------------------------------------------*/ + #define HIRQ_MUXH_INTSEL12_MASK (0x00007C00) + #define HIRQ_MUXH_INTSEL12_SHIFT (0x0000000A) + + #define HIRQ_MUXH_INTSEL12_GET(RegAddr) \ + HFIELD_GET(RegAddr,HIRQ_MUXH_INTSEL12) + + #define HIRQ_MUXH_INTSEL12_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HIRQ_MUXH_INTSEL12,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HIRQ_MUXH_INTSEL13 +\*----------------------------------------------------------------------------*/ + #define HIRQ_MUXH_INTSEL13_MASK (0x001F0000) + #define HIRQ_MUXH_INTSEL13_SHIFT (0x00000010) + + #define HIRQ_MUXH_INTSEL13_GET(RegAddr) \ + HFIELD_GET(RegAddr,HIRQ_MUXH_INTSEL13) + + #define HIRQ_MUXH_INTSEL13_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HIRQ_MUXH_INTSEL13,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HIRQ_MUXH_INTSEL14 +\*----------------------------------------------------------------------------*/ + #define HIRQ_MUXH_INTSEL14_MASK (0x03E00000) + #define HIRQ_MUXH_INTSEL14_SHIFT (0x00000015) + + #define HIRQ_MUXH_INTSEL14_GET(RegAddr) \ + HFIELD_GET(RegAddr,HIRQ_MUXH_INTSEL14) + + #define HIRQ_MUXH_INTSEL14_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HIRQ_MUXH_INTSEL14,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HIRQ_MUXH_INTSEL15 +\*----------------------------------------------------------------------------*/ + #define HIRQ_MUXH_INTSEL15_MASK (0x7C000000) + #define HIRQ_MUXH_INTSEL15_SHIFT (0x0000001A) + + #define HIRQ_MUXH_INTSEL15_GET(RegAddr) \ + HFIELD_GET(RegAddr,HIRQ_MUXH_INTSEL15) + + #define HIRQ_MUXH_INTSEL15_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HIRQ_MUXH_INTSEL15,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HIRQ_MUXH +\*----------------------------------------------------------------------------*/ + #define HIRQ_MUXH_GET(RegAddr) HREG32_GET(RegAddr) + #define HIRQ_MUXH_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HIRQ_MUXH_CFG(RegAddr,intsel10,intsel11,intsel12,intsel13,intsel14,\ + intsel15) REG32(RegAddr) = (\ + HFIELD_SHIFT(HIRQ_MUXH_INTSEL10, intsel10)|\ + HFIELD_SHIFT(HIRQ_MUXH_INTSEL11, intsel11)|\ + HFIELD_SHIFT(HIRQ_MUXH_INTSEL12, intsel12)|\ + HFIELD_SHIFT(HIRQ_MUXH_INTSEL13, intsel13)|\ + HFIELD_SHIFT(HIRQ_MUXH_INTSEL14, intsel14)|\ + HFIELD_SHIFT(HIRQ_MUXH_INTSEL15, intsel15)\ + ) + +/******************************************************************************\ +* HIRQ_EXTPOL - external interrupt polarity register +* +* Fields: +* (RW) HIRQ_EXTPOL_XIP4 +* (RW) HIRQ_EXTPOL_XIP5 +* (RW) HIRQ_EXTPOL_XIP6 +* (RW) HIRQ_EXTPOL_XIP7 +* +\******************************************************************************/ + #define HIRQ_EXTPOL_ADDR (HIRQ_BASE_ADDR+0x0008) + #define HIRQ_EXTPOL REG32(HIRQ_EXTPOL_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) HIRQ_EXTPOL_XIP4 +\*----------------------------------------------------------------------------*/ + #define HIRQ_EXTPOL_XIP4_MASK (0x00000001) + #define HIRQ_EXTPOL_XIP4_SHIFT (0x00000000) + + #define HIRQ_EXTPOL_XIP4_GET(RegAddr) \ + HFIELD_GET(RegAddr,HIRQ_EXTPOL_XIP4) + + #define HIRQ_EXTPOL_XIP4_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HIRQ_EXTPOL_XIP4,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HIRQ_EXTPOL_XIP5 +\*----------------------------------------------------------------------------*/ + #define HIRQ_EXTPOL_XIP5_MASK (0x00000002) + #define HIRQ_EXTPOL_XIP5_SHIFT (0x00000001) + + #define HIRQ_EXTPOL_XIP5_GET(RegAddr) \ + HFIELD_GET(RegAddr,HIRQ_EXTPOL_XIP5) + + #define HIRQ_EXTPOL_XIP5_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HIRQ_EXTPOL_XIP5,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HIRQ_EXTPOL_XIP6 +\*----------------------------------------------------------------------------*/ + #define HIRQ_EXTPOL_XIP6_MASK (0x00000004) + #define HIRQ_EXTPOL_XIP6_SHIFT (0x00000002) + + #define HIRQ_EXTPOL_XIP6_GET(RegAddr) \ + HFIELD_GET(RegAddr,HIRQ_EXTPOL_XIP6) + + #define HIRQ_EXTPOL_XIP6_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HIRQ_EXTPOL_XIP6,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HIRQ_EXTPOL_XIP7 +\*----------------------------------------------------------------------------*/ + #define HIRQ_EXTPOL_XIP7_MASK (0x00000008) + #define HIRQ_EXTPOL_XIP7_SHIFT (0x00000003) + + #define HIRQ_EXTPOL_XIP7_GET(RegAddr) \ + HFIELD_GET(RegAddr,HIRQ_EXTPOL_XIP7) + + #define HIRQ_EXTPOL_XIP7_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HIRQ_EXTPOL_XIP7,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HIRQ_EXTPOL +\*----------------------------------------------------------------------------*/ + #define HIRQ_EXTPOL_GET(RegAddr) HREG32_GET(RegAddr) + #define HIRQ_EXTPOL_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HIRQ_EXTPOL_CFG(RegAddr,xip4,xip5,xip6,xip7)\ + REG32(RegAddr) = (\ + HFIELD_SHIFT(HIRQ_EXTPOL_XIP4, xip4)|\ + HFIELD_SHIFT(HIRQ_EXTPOL_XIP5, xip5)|\ + HFIELD_SHIFT(HIRQ_EXTPOL_XIP6, xip6)|\ + HFIELD_SHIFT(HIRQ_EXTPOL_XIP7, xip7)\ + ) + +/*----------------------------------------------------------------------------*/ + +#endif /* IRQ_SUPPORT */ +#endif /* _IRQHAL_H_ */ +/******************************************************************************\ +* End of irqhal.h +\******************************************************************************/ + +/******************************************************************************\ +* Copyright (C) 1999-2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... mcbsphal.h +* DATE CREATED.. 06/12/1999 +* LAST MODIFIED. 03/08/2000 +* +*------------------------------------------------------------------------------ +* DESCRIPTION: (HAL interface file for the MCBSP module) +* +* Registers Covered: +* HMCBSP_DRR0 - serial port 0 data receive register +* HMCBSP_DXR0 - serial port 0 data transmit register +* HMCBSP_SPCR0 - serial port 0 control register +* HMCBSP_RCR0 - serial port 0 receive control register +* HMCBSP_XCR0 - serial port 0 transmit control register +* HMCBSP_SRGR0 - serial port 0 sample rate generator register +* HMCBSP_MCR0 - serial port 0 multichannel control register +* HMCBSP_RCER0 - serial port 0 receive channel enable register +* HMCBSP_XCER0 - serial port 0 transmit channel enable register +* HMCBSP_PCR0 - serial port 0 pin control register +* +* HMCBSP_DRR1 - serial port 1 data receive register +* HMCBSP_DXR1 - serial port 1 data transmit register +* HMCBSP_SPCR1 - serial port 1 control register +* HMCBSP_RCR1 - serial port 1 receive control register +* HMCBSP_XCR1 - serial port 1 transmit control register +* HMCBSP_SRGR1 - serial port 1 sample rate generator register +* HMCBSP_MCR1 - serial port 1 multichannel control register +* HMCBSP_RCER1 - serial port 1 receive channel enable register +* HMCBSP_XCER1 - serial port 1 transmit channel enable register +* HMCBSP_PCR1 - serial port 1 pin control register +* +* HMCBSP_DRR2 - serial port 2 data receive register (1) +* HMCBSP_DXR2 - serial port 2 data transmit register (1) +* HMCBSP_SPCR2 - serial port 2 control register (1) +* HMCBSP_RCR2 - serial port 2 receive control register (1) +* HMCBSP_XCR2 - serial port 2 transmit control register (1) +* HMCBSP_SRGR2 - serial port 2 sample rate generator register (1) +* HMCBSP_MCR2 - serial port 2 multichannel control register (1) +* HMCBSP_RCER2 - serial port 2 receive channel enable register (1) +* HMCBSP_XCER2 - serial port 2 transmit channel enable register (1) +* HMCBSP_PCR2 - serial port 2 pin control register (1) +* +* (1) only on devices with three serial ports +* +\******************************************************************************/ +#ifndef _MCBSPHAL_H_ +#define _MCBSPHAL_H_ + +#if (MCBSP_SUPPORT) +/*============================================================================*\ +* misc declarations +\*============================================================================*/ +#define HMCBSP_BASE0_ADDR (HCHIP_PERBASE_ADDR+0x000C0000) +#define HMCBSP_BASE1_ADDR (HCHIP_PERBASE_ADDR+0x00100000) +#define HMCBSP_BASE2_ADDR (HCHIP_PERBASE_ADDR+0x00240000) + +#if (CHIP_6202 | CHIP_6203) + #define HMCBSP_PORT_CNT (3) +#else + #define HMCBSP_PORT_CNT (2) +#endif + +/******************************************************************************\ +* HMCBSP_DRR0 - serial port 0 data receive register +* HMCBSP_DRR1 - serial port 1 data receive register +* HMCBSP_DRR2 - serial port 2 data receive register (1) +* +* (1) only on devices with three serial ports +* +* Fields: +* (R) HMCBSP_DRR_DRR +* +\******************************************************************************/ +#if (C11_SUPPORT & 0) + #define HMCBSP_DRR0_ADDR (0x30000000) + #define HMCBSP_DRR1_ADDR (0x34000000) +#else + #define HMCBSP_DRR0_ADDR (HMCBSP_BASE0_ADDR+0x0000) + #define HMCBSP_DRR1_ADDR (HMCBSP_BASE1_ADDR+0x0000) +#endif + #define HMCBSP_DRR0 REG32(HMCBSP_DRR0_ADDR) + #define HMCBSP_DRR1 REG32(HMCBSP_DRR1_ADDR) + +#if (HMCBSP_PORT_CNT==3) + #define HMCBSP_DRR2_ADDR (HMCBSP_BASE2_ADDR+0x0000) + #define HMCBSP_DRR2 REG32(HMCBSP_DRR2_ADDR) +#endif + +/*----------------------------------------------------------------------------*\ +* (R) HMCBSP_DRR_DRR +\*----------------------------------------------------------------------------*/ + #define HMCBSP_DRR_DRR_MASK (0xFFFFFFFF) + #define HMCBSP_DRR_DRR_SHIFT (0x00000000) + + #define HMCBSP_DRR_DRR_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_DRR_DRR) + +/*----------------------------------------------------------------------------*\ +* (R) HMCBSP_DRR +\*----------------------------------------------------------------------------*/ + #define HMCBSP_DRR_GET(RegAddr) HREG32_GET(RegAddr) + +/******************************************************************************\ +* HMCBSP_DXR0 - serial port 0 data transmit register +* HMCBSP_DXR1 - serial port 1 data transmit register +* HMCBSP_DXR2 - serial port 2 data transmit register (1) +* +* (1) only on devices with three serial ports +* +* Fields: +* (W) HMCBSP_DXR_DXR +* +\******************************************************************************/ +#if (C11_SUPPORT & 0) + #define HMCBSP_DXR0_ADDR (0x30000000) + #define HMCBSP_DXR1_ADDR (0x34000000) +#else + #define HMCBSP_DXR0_ADDR (HMCBSP_BASE0_ADDR+0x0004) + #define HMCBSP_DXR1_ADDR (HMCBSP_BASE1_ADDR+0x0004) +#endif + #define HMCBSP_DXR0 REG32(HMCBSP_DXR0_ADDR) + #define HMCBSP_DXR1 REG32(HMCBSP_DXR1_ADDR) + +#if (HMCBSP_PORT_CNT==3) + #define HMCBSP_DXR2_ADDR (HMCBSP_BASE2_ADDR+0x0004) + #define HMCBSP_DXR2 REG32(HMCBSP_DXR2_ADDR) +#endif + +/*----------------------------------------------------------------------------*\ +* (W) HMCBSP_DXR_DXR +\*----------------------------------------------------------------------------*/ + #define HMCBSP_DXR_DXR_MASK (0xFFFFFFFF) + #define HMCBSP_DXR_DXR_SHIFT (0x00000000) + + #define HMCBSP_DXR_DXR_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_DXR_DXR,Val) + +/*----------------------------------------------------------------------------*\ +* (W) HMCBSP_DXR +\*----------------------------------------------------------------------------*/ + #define HMCBSP_DXR_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HMCBSP_DXR_CFG(RegAddr,dxr) REG32(RegAddr)=(UINT32)( \ + HFIELD_SHIFT(HMCBSP_DXR_DXR,dxr) \ + ) + +/******************************************************************************\ +* HMCBSP_SPCR0 - serial port 0 control register +* HMCBSP_SPCR1 - serial port 1 control register +* HMCBSP_SPCR2 - serial port 2 control register (1) +* +* (1) only on devices with three serial ports +* +* Fields: +* (RW) HMCBSP_SPCR_RRST +* (R) HMCBSP_SPCR_RRDY +* (R) HMCBSP_SPCR_FULL +* (RW) HMCBSP_SPCR_RSYNCERR +* (RW) HMCBSP_SPCR_RINTM +* (RW) HMCBSP_SPCR_DXENA +* (RW) HMCBSP_SPCR_CLKSTP +* (RW) HMCBSP_SPCR_RJUST +* (RW) HMCBSP_SPCR_DLB +* (RW) HMCBSP_SPCR_XRST +* (R) HMCBSP_SPCR_XRDY +* (R) HMCBSP_SPCR_XEMPTY +* (RW) HMCBSP_SPCR_XSYNCERR +* (RW) HMCBSP_SPCR_XINTM +* (RW) HMCBSP_SPCR_GRST +* (RW) HMCBSP_SPCR_FRST +* +\******************************************************************************/ + #define HMCBSP_SPCR0_ADDR (HMCBSP_BASE0_ADDR+0x0008) + #define HMCBSP_SPCR1_ADDR (HMCBSP_BASE1_ADDR+0x0008) + #define HMCBSP_SPCR0 REG32(HMCBSP_SPCR0_ADDR) + #define HMCBSP_SPCR1 REG32(HMCBSP_SPCR1_ADDR) + +#if (HMCBSP_PORT_CNT==3) + #define HMCBSP_SPCR2_ADDR (HMCBSP_BASE2_ADDR+0x0008) + #define HMCBSP_SPCR2 REG32(HMCBSP_SPCR2_ADDR) +#endif + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_SPCR_RRST +\*----------------------------------------------------------------------------*/ + #define HMCBSP_SPCR_RRST_MASK (0x00000001) + #define HMCBSP_SPCR_RRST_SHIFT (0x00000000) + + #define HMCBSP_SPCR_RRST_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_SPCR_RRST) + + #define HMCBSP_SPCR_RRST_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_SPCR_RRST,Val) + +/*----------------------------------------------------------------------------*\ +* (R) HMCBSP_SPCR_RRDY +\*----------------------------------------------------------------------------*/ + #define HMCBSP_SPCR_RRDY_MASK (0x00000002) + #define HMCBSP_SPCR_RRDY_SHIFT (0x00000001) + + #define HMCBSP_SPCR_RRDY_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_SPCR_RRDY) + +/*----------------------------------------------------------------------------*\ +* (R) HMCBSP_SPCR_RFULL +\*----------------------------------------------------------------------------*/ + #define HMCBSP_SPCR_RFULL_MASK (0x00000004) + #define HMCBSP_SPCR_RFULL_SHIFT (0x00000002) + + #define HMCBSP_SPCR_RFULL_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_SPCR_RFULL) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_SPCR_RSYNCERR +\*----------------------------------------------------------------------------*/ + #define HMCBSP_SPCR_RSYNCERR_MASK (0x00000008) + #define HMCBSP_SPCR_RSYNCERR_SHIFT (0x00000003) + + #define HMCBSP_SPCR_RSYNCERR_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_SPCR_RSYNCERR) + + #define HMCBSP_SPCR_RSYNCERR_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_SPCR_RSYNCERR,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_SPCR_RINTM +\*----------------------------------------------------------------------------*/ + #define HMCBSP_SPCR_RINTM_MASK (0x00000030) + #define HMCBSP_SPCR_RINTM_SHIFT (0x00000004) + + #define HMCBSP_SPCR_RINTM_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_SPCR_RINTM) + + #define HMCBSP_SPCR_RINTM_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_SPCR_RINTM,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_SPCR_DXENA +\*----------------------------------------------------------------------------*/ +#if (C11_SUPPORT) + #define HMCBSP_SPCR_DXENA_MASK (0x00000080) + #define HMCBSP_SPCR_DXENA_SHIFT (0x00000007) +#else + #define HMCBSP_SPCR_DXENA_MASK (0x00000000) + #define HMCBSP_SPCR_DXENA_SHIFT (0x00000000) +#endif + + #define HMCBSP_SPCR_DXENA_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_SPCR_DXENA) + + #define HMCBSP_SPCR_DXENA_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_SPCR_DXENA,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_SPCR_CLKSTP +\*----------------------------------------------------------------------------*/ + #define HMCBSP_SPCR_CLKSTP_MASK (0x00001800) + #define HMCBSP_SPCR_CLKSTP_SHIFT (0x0000000B) + + #define HMCBSP_SPCR_CLKSTP_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_SPCR_CLKSTP) + + #define HMCBSP_SPCR_CLKSTP_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_SPCR_CLKSTP,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_SPCR_RJUST +\*----------------------------------------------------------------------------*/ + #define HMCBSP_SPCR_RJUST_MASK (0x00006000) + #define HMCBSP_SPCR_RJUST_SHIFT (0x0000000D) + + #define HMCBSP_SPCR_RJUST_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_SPCR_RJUST) + + #define HMCBSP_SPCR_RJUST_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_SPCR_RJUST,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_SPCR_DLB +\*----------------------------------------------------------------------------*/ + #define HMCBSP_SPCR_DLB_MASK (0x00008000) + #define HMCBSP_SPCR_DLB_SHIFT (0x0000000F) + + #define HMCBSP_SPCR_DLB_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_SPCR_DLB) + + #define HMCBSP_SPCR_DLB_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_SPCR_DLB,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_SPCR_XRST +\*----------------------------------------------------------------------------*/ + #define HMCBSP_SPCR_XRST_MASK (0x00010000) + #define HMCBSP_SPCR_XRST_SHIFT (0x00000010) + + #define HMCBSP_SPCR_XRST_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_SPCR_XRST) + + #define HMCBSP_SPCR_XRST_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_SPCR_XRST,Val) + +/*----------------------------------------------------------------------------*\ +* (R) HMCBSP_SPCR_XRDY +\*----------------------------------------------------------------------------*/ + #define HMCBSP_SPCR_XRDY_MASK (0x00020000) + #define HMCBSP_SPCR_XRDY_SHIFT (0x00000011) + + #define HMCBSP_SPCR_XRDY_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_SPCR_XRDY) + + #define HMCBSP_SPCR_XRDY_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_SPCR_XRDY,Val) + +/*----------------------------------------------------------------------------*\ +* (R) HMCBSP_SPCR_XEMPTY +\*----------------------------------------------------------------------------*/ + #define HMCBSP_SPCR_XEMPTY_MASK (0x00040000) + #define HMCBSP_SPCR_XEMPTY_SHIFT (0x00000012) + + #define HMCBSP_SPCR_XEMPTY_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_SPCR_XEMPTY) + + #define HMCBSP_SPCR_XEMPTY_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_SPCR_XEMPTY,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_SPCR_XSYNCERR +\*----------------------------------------------------------------------------*/ + #define HMCBSP_SPCR_XSYNCERR_MASK (0x00080000) + #define HMCBSP_SPCR_XSYNCERR_SHIFT (0x00000013) + + #define HMCBSP_SPCR_XSYNCERR_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_SPCR_XSYNCERR) + + #define HMCBSP_SPCR_XSYNCERR_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_SPCR_XSYNCERR,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_SPCR_XINTM +\*----------------------------------------------------------------------------*/ + #define HMCBSP_SPCR_XINTM_MASK (0x00300000) + #define HMCBSP_SPCR_XINTM_SHIFT (0x00000014) + + #define HMCBSP_SPCR_XINTM_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_SPCR_XINTM) + + #define HMCBSP_SPCR_XINTM_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_SPCR_XINTM,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_SPCR_GRST +\*----------------------------------------------------------------------------*/ + #define HMCBSP_SPCR_GRST_MASK (0x00400000) + #define HMCBSP_SPCR_GRST_SHIFT (0x00000016) + + #define HMCBSP_SPCR_GRST_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_SPCR_GRST) + + #define HMCBSP_SPCR_GRST_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_SPCR_GRST,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_SPCR_FRST +\*----------------------------------------------------------------------------*/ + #define HMCBSP_SPCR_FRST_MASK (0x00800000) + #define HMCBSP_SPCR_FRST_SHIFT (0x00000017) + + #define HMCBSP_SPCR_FRST_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_SPCR_FRST) + + #define HMCBSP_SPCR_FRST_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_SPCR_FRST,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_SPCR +\*----------------------------------------------------------------------------*/ + #define HMCBSP_SPCR_GET(RegAddr) HREG32_GET(RegAddr) + #define HMCBSP_SPCR_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HMCBSP_SPCR_CFG(RegAddr,rrst,rsyncerr,rintm,dxena,clkstp,rjust,dlb,\ + xrst,xsyncerr,xintm,grst,frst) REG32(RegAddr)=(UINT32)(\ + HFIELD_SHIFT(HMCBSP_SPCR_RRST, rrst) |\ + HFIELD_SHIFT(HMCBSP_SPCR_RSYNCERR,rsyncerr)|\ + HFIELD_SHIFT(HMCBSP_SPCR_RINTM, rintm) |\ + HFIELD_SHIFT(HMCBSP_SPCR_DXENA, dxena) |\ + HFIELD_SHIFT(HMCBSP_SPCR_CLKSTP, clkstp) |\ + HFIELD_SHIFT(HMCBSP_SPCR_RJUST, rjust) |\ + HFIELD_SHIFT(HMCBSP_SPCR_DLB, dlb) |\ + HFIELD_SHIFT(HMCBSP_SPCR_XRST, xrst) |\ + HFIELD_SHIFT(HMCBSP_SPCR_XSYNCERR,xsyncerr)|\ + HFIELD_SHIFT(HMCBSP_SPCR_XINTM, xintm) |\ + HFIELD_SHIFT(HMCBSP_SPCR_GRST, grst) |\ + HFIELD_SHIFT(HMCBSP_SPCR_FRST, frst) \ + ) + +/******************************************************************************\ +* HMCBSP_RCR0 - serial port 0 receive control register +* HMCBSP_RCR1 - serial port 1 receive control register +* HMCBSP_RCR2 - serial port 2 receive control register (1) +* +* (1) only on devices with three serial ports +* +* Fields: +* (RW) HMCBSP_RCR_RWDREVRS (2) +* (RW) HMCBSP_RCR_RWDLEN1 +* (RW) HMCBSP_RCR_RFRLEN1 +* (RW) HMCBSP_RCR_RPHASE2 (2) +* (RW) HMCBSP_RCR_RDATDLY +* (RW) HMCBSP_RCR_RFIG +* (RW) HMCBSP_RCR_RCOMPAND +* (RW) HMCBSP_RCR_RWDLEN2 +* (RW) HMCBSP_RCR_RFRLEN2 +* (RW) HMCBSP_RCR_RPHASE +* +* (2) - C11_SUPPORT only +* +\******************************************************************************/ + #define HMCBSP_RCR0_ADDR (HMCBSP_BASE0_ADDR+0x000C) + #define HMCBSP_RCR1_ADDR (HMCBSP_BASE1_ADDR+0x000C) + #define HMCBSP_RCR0 REG32(HMCBSP_RCR0_ADDR) + #define HMCBSP_RCR1 REG32(HMCBSP_RCR1_ADDR) + +#if (HMCBSP_PORT_CNT==3) + #define HMCBSP_RCR2_ADDR (HMCBSP_BASE2_ADDR+0x000C) + #define HMCBSP_RCR2 REG32(HMCBSP_RCR2_ADDR) +#endif + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCR_RWDREVRS +\*----------------------------------------------------------------------------*/ +#if (C11_SUPPORT) + #define HMCBSP_RCR_RWDREVRS_MASK (0x00000010) + #define HMCBSP_RCR_RWDREVRS_SHIFT (0x00000004) +#else + #define HMCBSP_RCR_RWDREVRS_MASK (0x00000000) + #define HMCBSP_RCR_RWDREVRS_SHIFT (0x00000000) +#endif + + #define HMCBSP_RCR_RWDREVRS_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCR_RWDREVRS) + + #define HMCBSP_RCR_RWDREVRS_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCR_RWDREVRS,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCR_RWDLEN1 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCR_RWDLEN1_MASK (0x000000E0) + #define HMCBSP_RCR_RWDLEN1_SHIFT (0x00000005) + + #define HMCBSP_RCR_RWDLEN1_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCR_RWDLEN1) + + #define HMCBSP_RCR_RWDLEN1_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCR_RWDLEN1,Val) +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCR_RFRLEN1 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCR_RFRLEN1_MASK (0x00007F00) + #define HMCBSP_RCR_RFRLEN1_SHIFT (0x00000008) + + #define HMCBSP_RCR_RFRLEN1_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCR_RFRLEN1) + + #define HMCBSP_RCR_RFRLEN1_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCR_RFRLEN1,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCR_RPHASE2 +\*----------------------------------------------------------------------------*/ +#if (C11_SUPPORT) + #define HMCBSP_RCR_RPHASE2_MASK (0x00008000) + #define HMCBSP_RCR_RPHASE2_SHIFT (0x0000000F) +#else + #define HMCBSP_RCR_RPHASE2_MASK (0x00000000) + #define HMCBSP_RCR_RPHASE2_SHIFT (0x00000000) +#endif + + #define HMCBSP_RCR_RPHASE2_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCR_RPHASE2) + + #define HMCBSP_RCR_RPHASE2_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCR_RPHASE2,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCR_RDATDLY +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCR_RDATDLY_MASK (0x00030000) + #define HMCBSP_RCR_RDATDLY_SHIFT (0x00000010) + + #define HMCBSP_RCR_RDATDLY_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCR_RDATDLY) + + #define HMCBSP_RCR_RDATDLY_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCR_RDATDLY,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCR_RFIG +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCR_RFIG_MASK (0x00040000) + #define HMCBSP_RCR_RFIG_SHIFT (0x00000012) + + #define HMCBSP_RCR_RFIG_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCR_RFIG) + + #define HMCBSP_RCR_RFIG_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCR_RFIG,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCR_RCOMPAND +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCR_RCOMPAND_MASK (0x00180000) + #define HMCBSP_RCR_RCOMPAND_SHIFT (0x00000013) + + #define HMCBSP_RCR_RCOMPAND_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCR_RCOMPAND) + + #define HMCBSP_RCR_RCOMPAND_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCR_RCOMPAND,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCR_RWDLEN2 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCR_RWDLEN2_MASK (0x00E00000) + #define HMCBSP_RCR_RWDLEN2_SHIFT (0x00000015) + + #define HMCBSP_RCR_RWDLEN2_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCR_RWDLEN2) + + #define HMCBSP_RCR_RWDLEN2_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCR_RWDLEN2,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCR_RFRLEN2 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCR_RFRLEN2_MASK (0x7F000000) + #define HMCBSP_RCR_RFRLEN2_SHIFT (0x00000018) + + #define HMCBSP_RCR_FRFLEN2_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCR_FRFLEN2) + + #define HMCBSP_RCR_FRFLEN2_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCR_FRFLEN2,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCR_RPHASE +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCR_RPHASE_MASK (0x80000000) + #define HMCBSP_RCR_RPHASE_SHIFT (0x0000001F) + + #define HMCBSP_RCR_RPHASE_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCR_RPHASE) + + #define HMCBSP_RCR_RPHASE_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCR_RPHASE,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCR +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCR_GET(RegAddr) HREG32_GET(RegAddr) + #define HMCBSP_RCR_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HMCBSP_RCR_CFG(RegAddr,rwdrevrs,rwdlen1,rfrlen1,rphase2,rdatdly,\ + rfig,rcompand,rwdlen2,rfrlen2,rphase) REG32(RegAddr)=(UINT32)(\ + HFIELD_SHIFT(HMCBSP_RCR_RWDREVRS,rwdrevrs)|\ + HFIELD_SHIFT(HMCBSP_RCR_RWDLEN1, rwdlen1) |\ + HFIELD_SHIFT(HMCBSP_RCR_RFRLEN1, rfrlen1) |\ + HFIELD_SHIFT(HMCBSP_RCR_RPHASE2, rphase2) |\ + HFIELD_SHIFT(HMCBSP_RCR_RDATDLY, rdatdly) |\ + HFIELD_SHIFT(HMCBSP_RCR_RFIG, rfig) |\ + HFIELD_SHIFT(HMCBSP_RCR_RCOMPAND,rcompand)|\ + HFIELD_SHIFT(HMCBSP_RCR_RWDLEN2, rwdlen2) |\ + HFIELD_SHIFT(HMCBSP_RCR_RFRLEN2, rfrlen2) |\ + HFIELD_SHIFT(HMCBSP_RCR_RPHASE, rphase) \ + ) + +/******************************************************************************\ +* HMCBSP_XCR0 - serial port 0 transmit control register +* HMCBSP_XCR1 - serial port 1 transmit control register +* HMCBSP_XCR2 - serial port 2 transmit control register (1) +* +* (1) only on devices with three serial ports +* +* Fields: +* (RW) HMCBSP_XCR_XWDREVRS (2) +* (RW) HMCBSP_XCR_XWDLEN1 +* (RW) HMCBSP_XCR_XFRLEN1 +* (RW) HMCBSP_XCR_XPHASE2 (2) +* (RW) HMCBSP_XCR_XDATDLY +* (RW) HMCBSP_XCR_XFIG +* (RW) HMCBSP_XCR_XCOMPAND +* (RW) HMCBSP_XCR_XWDLEN2 +* (RW) HMCBSP_XCR_XFRLEN2 +* (RW) HMCBSP_XCR_XPHASE +* +* (2) - C11_SUPPORT only +* +\******************************************************************************/ + #define HMCBSP_XCR0_ADDR (HMCBSP_BASE0_ADDR+0x0010) + #define HMCBSP_XCR1_ADDR (HMCBSP_BASE1_ADDR+0x0010) + #define HMCBSP_XCR0 REG32(HMCBSP_XCR0_ADDR) + #define HMCBSP_XCR1 REG32(HMCBSP_XCR1_ADDR) + +#if (HMCBSP_PORT_CNT==3) + #define HMCBSP_XCR2_ADDR (HMCBSP_BASE2_ADDR+0x0010) + #define HMCBSP_XCR2 REG32(HMCBSP_XCR2_ADDR) +#endif + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCR_RWDREVRS +\*----------------------------------------------------------------------------*/ +#if (C11_SUPPORT) + #define HMCBSP_XCR_XWDREVRS_MASK (0x00000010) + #define HMCBSP_XCR_XWDREVRS_SHIFT (0x00000004) +#else + #define HMCBSP_XCR_XWDREVRS_MASK (0x00000000) + #define HMCBSP_XCR_XWDREVRS_SHIFT (0x00000000) +#endif + + #define HMCBSP_XCR_XWDREVRS_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCR_XWDREVRS) + + #define HMCBSP_XCR_XWDREVRS_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCR_XWDREVRS,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCR_XWDLEN1 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCR_XWDLEN1_MASK (0x000000E0) + #define HMCBSP_XCR_XWDLEN1_SHIFT (0x00000005) + + #define HMCBSP_XCR_XWDLEN1_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCR_XWDLEN1) + + #define HMCBSP_XCR_XWDLEN1_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCR_XWDLEN1,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCR_XFRLEN1 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCR_XFRLEN1_MASK (0x00007F00) + #define HMCBSP_XCR_XFRLEN1_SHIFT (0x00000008) + + #define HMCBSP_XCR_XFRLEN1_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCR_XFRLEN1) + + #define HMCBSP_XCR_XFRLEN1_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCR_XFRLEN1,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCR_XPHASE2 +\*----------------------------------------------------------------------------*/ +#if (C11_SUPPORT) + #define HMCBSP_XCR_XPHASE2_MASK (0x00008000) + #define HMCBSP_XCR_XPHASE2_SHIFT (0x0000000F) +#else + #define HMCBSP_XCR_XPHASE2_MASK (0x00000000) + #define HMCBSP_XCR_XPHASE2_SHIFT (0x00000000) +#endif + + #define HMCBSP_XCR_XPHASE2_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCR_XPHASE2) + + #define HMCBSP_XCR_XPHASE2_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCR_XPHASE2,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCR_XDATDLY +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCR_XDATDLY_MASK (0x00030000) + #define HMCBSP_XCR_XDATDLY_SHIFT (0x00000010) + + #define HMCBSP_XCR_XDATDLY_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCR_XDATDLY) + + #define HMCBSP_XCR_XDATDLY_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCR_XDATDLY,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCR_XFIG +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCR_XFIG_MASK (0x00040000) + #define HMCBSP_XCR_XFIG_SHIFT (0x00000012) + + #define HMCBSP_XCR_XFIG_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCR_XFIG) + + #define HMCBSP_XCR_XFIG_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCR_XFIG,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCR_XCOMPAND +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCR_XCOMPAND_MASK (0x00180000) + #define HMCBSP_XCR_XCOMPAND_SHIFT (0x00000013) + + #define HMCBSP_XCR_XCOMPAND_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCR_XCOMPAND) + + #define HMCBSP_XCR_XCOMPAND_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCR_XCOMPAND,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCR_XWDLEN2 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCR_XWDLEN2_MASK (0x00E00000) + #define HMCBSP_XCR_XWDLEN2_SHIFT (0x00000015) + + #define HMCBSP_XCR_XWDLEN2_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCR_XWDLEN2) + + #define HMCBSP_XCR_XWDLEN2_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCR_XWDLEN2,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCR_XFRLEN2 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCR_XFRLEN2_MASK (0x7F000000) + #define HMCBSP_XCR_XFRLEN2_SHIFT (0x00000018) + + #define HMCBSP_XCR_XFRLEN2_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCR_XFRLEN2) + + #define HMCBSP_XCR_XFRLEN2_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCR_XFRLEN2,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCR_XPHASE +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCR_XPHASE_MASK (0x80000000) + #define HMCBSP_XCR_XPHASE_SHIFT (0x0000001F) + + #define HMCBSP_XCR_XPHASE_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCR_XPHASE) + + #define HMCBSP_XCR_XPHASE_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCR_XPHASE,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCR +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCR_GET(RegAddr) HREG32_GET(RegAddr) + #define HMCBSP_XCR_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HMCBSP_XCR_CFG(RegAddr,xwdrevrs,xwdlen1,xfrlen1,xphase2,xdatdly,\ + xfig,xcompand,xwdlen2,xfrlen2,xphase) (REG32(RegAddr)=(UINT32)(\ + HFIELD_SHIFT(HMCBSP_XCR_XWDREVRS,xwdrevrs)|\ + HFIELD_SHIFT(HMCBSP_XCR_XWDLEN1, xwdlen1) |\ + HFIELD_SHIFT(HMCBSP_XCR_XFRLEN1, xfrlen1) |\ + HFIELD_SHIFT(HMCBSP_XCR_XPHASE2, xphase2) |\ + HFIELD_SHIFT(HMCBSP_XCR_XDATDLY, xdatdly) |\ + HFIELD_SHIFT(HMCBSP_XCR_XFIG, xfig) |\ + HFIELD_SHIFT(HMCBSP_XCR_XCOMPAND,xcompand)|\ + HFIELD_SHIFT(HMCBSP_XCR_XWDLEN2, xwdlen2) |\ + HFIELD_SHIFT(HMCBSP_XCR_XFRLEN2, xfrlen2) |\ + HFIELD_SHIFT(HMCBSP_XCR_XPHASE, xphase) \ + ) + +/******************************************************************************\ +* HMCBSP_SRGR0 - serial port 0 sample rate generator register +* HMCBSP_SRGR1 - serial port 1 sample rate generator register +* HMCBSP_SRGR2 - serial port 2 sample rate generator register (1) +* +* (1) only on devices with three serial ports +* +* Fields: +* (RW) HMCBSP_SRGR_CLKGDV +* (RW) HMCBSP_SRGR_FWID +* (RW) HMCBSP_SRGR_FPER +* (RW) HMCBSP_SRGR_FSGM +* (RW) HMCBSP_SRGR_CLKSM +* (RW) HMCBSP_SRGR_CLKSP +* (RW) HMCBSP_SRGR_GSYNC +* +\******************************************************************************/ + #define HMCBSP_SRGR0_ADDR (HMCBSP_BASE0_ADDR+0x0014) + #define HMCBSP_SRGR1_ADDR (HMCBSP_BASE1_ADDR+0x0014) + #define HMCBSP_SRGR0 REG32(HMCBSP_SRGR0_ADDR) + #define HMCBSP_SRGR1 REG32(HMCBSP_SRGR1_ADDR) + +#if (HMCBSP_PORT_CNT==3) + #define HMCBSP_SRGR2_ADDR (HMCBSP_BASE2_ADDR+0x0014) + #define HMCBSP_SRGR2 REG32(HMCBSP_SRGR2_ADDR) +#endif + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_SRGR_CLKGDV +\*----------------------------------------------------------------------------*/ + #define HMCBSP_SRGR_CLKGDV_MASK (0x000000FF) + #define HMCBSP_SRGR_CLKGDV_SHIFT (0x00000000) + + #define HMCBSP_SRGR_CLKGDV_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_SRGR_CLKGDV) + + #define HMCBSP_SRGR_CLKGDV_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_SRGR_CLKGDV,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_SRGR_FWID +\*----------------------------------------------------------------------------*/ + #define HMCBSP_SRGR_FWID_MASK (0x0000FF00) + #define HMCBSP_SRGR_FWID_SHIFT (0x00000008) + + #define HMCBSP_SRGR_FWID_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_SRGR_FWID) + + #define HMCBSP_SRGR_FWID_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_SRGR_FWID,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_SRGR_FPER +\*----------------------------------------------------------------------------*/ + #define HMCBSP_SRGR_FPER_MASK (0x0FFF0000) + #define HMCBSP_SRGR_FPER_SHIFT (0x00000010) + + #define HMCBSP_SRGR_FPER_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_SRGR_FPER) + + #define HMCBSP_SRGR_FPER_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_SRGR_FPER,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_SRGR_FSGM +\*----------------------------------------------------------------------------*/ + #define HMCBSP_SRGR_FSGM_MASK (0x10000000) + #define HMCBSP_SRGR_FSGM_SHIFT (0x0000001C) + + #define HMCBSP_SRGR_FSGM_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_SRGR_FSGM) + + #define HMCBSP_SRGR_FSGM_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_SRGR_FSGM,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_SRGR_CLKSM +\*----------------------------------------------------------------------------*/ + #define HMCBSP_SRGR_CLKSM_MASK (0x20000000) + #define HMCBSP_SRGR_CLKSM_SHIFT (0x0000001D) + + #define HMCBSP_SRGR_CLKSM_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_SRGR_CLKSM) + + #define HMCBSP_SRGR_CLKSM_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_SRGR_CLKSM,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_SRGR_CLKSP +\*----------------------------------------------------------------------------*/ + #define HMCBSP_SRGR_CLKSP_MASK (0x40000000) + #define HMCBSP_SRGR_CLKSP_SHIFT (0x0000001E) + + #define HMCBSP_SRGR_CLKSP_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_SRGR_CLKSP) + + #define HMCBSP_SRGR_CLKSP_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_SRGR_CLKSP,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_SRGR_GSYNC +\*----------------------------------------------------------------------------*/ + #define HMCBSP_SRGR_GSYNC_MASK (0x80000000) + #define HMCBSP_SRGR_GSYNC_SHIFT (0x0000001F) + + #define HMCBSP_SRGR_GSYNC_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_SRGR_GSYNC) + + #define HMCBSP_SRGR_GSYNC_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_SRGR_GSYNC,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_SRGR +\*----------------------------------------------------------------------------*/ + #define HMCBSP_SRGR_GET(RegAddr) HREG32_GET(RegAddr) + #define HMCBSP_SRGR_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HMCBSP_SRGR_CFG(RegAddr,clkgdv,fwid,fper,fsgm,clksm,clksp,gsync) \ + REG32(RegAddr)=(UINT32)( \ + HFIELD_SHIFT(HMCBSP_SRGR_CLKGDV , clkgdv )|\ + HFIELD_SHIFT(HMCBSP_SRGR_FWID , fwid )|\ + HFIELD_SHIFT(HMCBSP_SRGR_FPER , fper )|\ + HFIELD_SHIFT(HMCBSP_SRGR_FSGM , fsgm )|\ + HFIELD_SHIFT(HMCBSP_SRGR_CLKSM , clksm )|\ + HFIELD_SHIFT(HMCBSP_SRGR_CLKSP , clksp )|\ + HFIELD_SHIFT(HMCBSP_SRGR_GSYNC , gsync ) \ + ) + +/******************************************************************************\ +* HMCBSP_MCR0 - serial port 0 multichannel control register +* HMCBSP_MCR1 - serial port 1 multichannel control register +* HMCBSP_MCR2 - serial port 2 multichannel control register (1) +* +* (1) only on devices with three serial ports +* +* Fields: +* (RW) HMCBSP_MCR_RMCM +* (R) HMCBSP_MCR_RCBLK +* (RW) HMCBSP_MCR_RPABLK +* (RW) HMCBSP_MCR_RPBBLK +* (RW) HMCBSP_MCR_XMCM +* (R) HMCBSP_MCR_XCBLK +* (RW) HMCBSP_MCR_XPABLK +* (RW) HMCBSP_MCR_XPBBLK +* +\******************************************************************************/ + #define HMCBSP_MCR0_ADDR (HMCBSP_BASE0_ADDR+0x0018) + #define HMCBSP_MCR1_ADDR (HMCBSP_BASE1_ADDR+0x0018) + #define HMCBSP_MCR0 REG32(HMCBSP_MCR0_ADDR) + #define HMCBSP_MCR1 REG32(HMCBSP_MCR1_ADDR) + +#if (HMCBSP_PORT_CNT==3) + #define HMCBSP_MCR2_ADDR (HMCBSP_BASE2_ADDR+0x0018) + #define HMCBSP_MCR2 REG32(HMCBSP_MCR2_ADDR) +#endif + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_MCR_RMCM +\*----------------------------------------------------------------------------*/ + #define HMCBSP_MCR_RMCM_MASK (0x00000001) + #define HMCBSP_MCR_RMCM_SHIFT (0x00000000) + + #define HMCBSP_MCR_RMCM_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_MCR_RMCM) + + #define HMCBSP_MCR_RMCM_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_MCR_RMCM,Val) + +/*----------------------------------------------------------------------------*\ +* (R) HMCBSP_MCR_RCBLK +\*----------------------------------------------------------------------------*/ + #define HMCBSP_MCR_RCBLK_MASK (0x0000001C) + #define HMCBSP_MCR_RCBLK_SHIFT (0x00000002) + + #define HMCBSP_MCR_RCBLK_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_MCR_RCBLK) + + #define HMCBSP_MCR_RCBLK_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_MCR_RCBLK,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_MCR_RPABLK +\*----------------------------------------------------------------------------*/ + #define HMCBSP_MCR_RPABLK_MASK (0x00000060) + #define HMCBSP_MCR_RPABLK_SHIFT (0x00000005) + + #define HMCBSP_MCR_RPABLK_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_MCR_RPABLK) + + #define HMCBSP_MCR_RPABLK_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_MCR_RPABLK,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_MCR_RPBBLK +\*----------------------------------------------------------------------------*/ + #define HMCBSP_MCR_RPBBLK_MASK (0x00000180) + #define HMCBSP_MCR_RPBBLK_SHIFT (0x00000007) + + #define HMCBSP_MCR_RPBBLK_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_MCR_RPBBLK) + + #define HMCBSP_MCR_RPBBLK_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_MCR_RPBBLK,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_MCR_XMCM +\*----------------------------------------------------------------------------*/ + #define HMCBSP_MCR_XMCM_MASK (0x00030000) + #define HMCBSP_MCR_XMCM_SHIFT (0x00000010) + + #define HMCBSP_MCR_XMCM_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_MCR_XMCM) + + #define HMCBSP_MCR_XMCM_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_MCR_XMCM,Val) + +/*----------------------------------------------------------------------------*\ +* (R) HMCBSP_MCR_XCBLK +\*----------------------------------------------------------------------------*/ + #define HMCBSP_MCR_XCBLK_MASK (0x001C0000) + #define HMCBSP_MCR_XCBLK_SHIFT (0x00000012) + + #define HMCBSP_MCR_XCBLK_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_MCR_XCBLK) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_MCR_XPABLK +\*----------------------------------------------------------------------------*/ + #define HMCBSP_MCR_XPABLK_MASK (0x00600000) + #define HMCBSP_MCR_XPABLK_SHIFT (0x00000015) + + #define HMCBSP_MCR_XPABLK_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_MCR_XPABLK) + + #define HMCBSP_MCR_XPABLK_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_MCR_XPABLK,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_MCR_XPBBLK +\*----------------------------------------------------------------------------*/ + #define HMCBSP_MCR_XPBBLK_MASK (0x01800000) + #define HMCBSP_MCR_XPBBLK_SHIFT (0x00000017) + + #define HMCBSP_MCR_XPBBLK_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_MCR_XPBBLK) + + #define HMCBSP_MCR_XPBBLK_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_MCR_XPBBLK,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_MCR +\*----------------------------------------------------------------------------*/ + #define HMCBSP_MCR_GET(RegAddr) HREG32_GET(RegAddr) + #define HMCBSP_MCR_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HMCBSP_MCR_CFG(RegAddr,rmcm,rpablk,rpbblk,xmcm,xpablk,xpbblk) \ + REG32(RegAddr)=(UINT32)( \ + HFIELD_SHIFT(HMCBSP_MCR_RMCM ,rmcm )|\ + HFIELD_SHIFT(HMCBSP_MCR_RPABLK,rpablk)|\ + HFIELD_SHIFT(HMCBSP_MCR_RPBBLK,rpbblk)|\ + HFIELD_SHIFT(HMCBSP_MCR_XMCM ,xmcm )|\ + HFIELD_SHIFT(HMCBSP_MCR_XPABLK,xpablk)|\ + HFIELD_SHIFT(HMCBSP_MCR_XPBBLK,xpbblk) \ + ) + +/******************************************************************************\ +* HMCBSP_RCER0 - serial port 0 receive channel enable register +* HMCBSP_RCER1 - serial port 1 receive channel enable register +* HMCBSP_RCER2 - serial port 2 receive channel enable register (1) +* +* (1) only on devices with three serial ports +* +* Fields: +* +\******************************************************************************/ + #define HMCBSP_RCER0_ADDR (HMCBSP_BASE0_ADDR+0x001C) + #define HMCBSP_RCER1_ADDR (HMCBSP_BASE1_ADDR+0x001C) + #define HMCBSP_RCER0 REG32(HMCBSP_RCER0_ADDR) + #define HMCBSP_RCER1 REG32(HMCBSP_RCER1_ADDR) + +#if (HMCBSP_PORT_CNT==3) + #define HMCBSP_RCER2_ADDR (HMCBSP_BASE2_ADDR+0x001C) + #define HMCBSP_RCER2 REG32(HMCBSP_RCER2_ADDR) +#endif + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCER_RCEA0 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCER_RCEA0_MASK (0x00000001) + #define HMCBSP_RCER_RCEA0_SHIFT (0x00000000) + + #define HMCBSP_RCER_RCEA0_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCER_RCEA0) + + #define HMCBSP_RCER_RCEA0_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCER_RCEA0,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCER_RCEA1 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCER_RCEA1_MASK (0x00000002) + #define HMCBSP_RCER_RCEA1_SHIFT (0x00000001) + + #define HMCBSP_RCER_RCEA1_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCER_RCEA1) + + #define HMCBSP_RCER_RCEA1_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCER_RCEA1,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCER_RCEA2 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCER_RCEA2_MASK (0x00000004) + #define HMCBSP_RCER_RCEA2_SHIFT (0x00000002) + + #define HMCBSP_RCER_RCEA2_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCER_RCEA2) + + #define HMCBSP_RCER_RCEA2_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCER_RCEA2,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCER_RCEA3 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCER_RCEA3_MASK (0x00000008) + #define HMCBSP_RCER_RCEA3_SHIFT (0x00000003) + + #define HMCBSP_RCER_RCEA3_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCER_RCEA3) + + #define HMCBSP_RCER_RCEA3_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCER_RCEA3,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCER_RCEA4 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCER_RCEA4_MASK (0x00000010) + #define HMCBSP_RCER_RCEA4_SHIFT (0x00000004) + + #define HMCBSP_RCER_RCEA4_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCER_RCEA4) + + #define HMCBSP_RCER_RCEA4_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCER_RCEA4,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCER_RCEA5 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCER_RCEA5_MASK (0x00000020) + #define HMCBSP_RCER_RCEA5_SHIFT (0x00000005) + + #define HMCBSP_RCER_RCEA5_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCER_RCEA5) + + #define HMCBSP_RCER_RCEA5_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCER_RCEA5,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCER_RCEA6 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCER_RCEA6_MASK (0x00000040) + #define HMCBSP_RCER_RCEA6_SHIFT (0x00000006) + + #define HMCBSP_RCER_RCEA6_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCER_RCEA6) + + #define HMCBSP_RCER_RCEA6_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCER_RCEA6,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCER_RCEA7 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCER_RCEA7_MASK (0x00000080) + #define HMCBSP_RCER_RCEA7_SHIFT (0x00000007) + + #define HMCBSP_RCER_RCEA7_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCER_RCEA7) + + #define HMCBSP_RCER_RCEA7_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCER_RCEA7,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCER_RCEA8 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCER_RCEA8_MASK (0x00000100) + #define HMCBSP_RCER_RCEA8_SHIFT (0x00000008) + + #define HMCBSP_RCER_RCEA8_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCER_RCEA8) + + #define HMCBSP_RCER_RCEA8_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCER_RCEA8,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCER_RCEA9 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCER_RCEA9_MASK (0x00000200) + #define HMCBSP_RCER_RCEA9_SHIFT (0x00000009) + + #define HMCBSP_RCER_RCEA9_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCER_RCEA9) + + #define HMCBSP_RCER_RCEA9_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCER_RCEA9,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCER_RCEA10 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCER_RCEA10_MASK (0x00000400) + #define HMCBSP_RCER_RCEA10_SHIFT (0x0000000A) + + #define HMCBSP_RCER_RCEA10_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCER_RCEA10) + + #define HMCBSP_RCER_RCEA10_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCER_RCEA10,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCER_RCEA11 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCER_RCEA11_MASK (0x00000800) + #define HMCBSP_RCER_RCEA11_SHIFT (0x0000000B) + + #define HMCBSP_RCER_RCEA11_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCER_RCEA11) + + #define HMCBSP_RCER_RCEA11_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCER_RCEA11,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCER_RCEA12 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCER_RCEA12_MASK (0x00001000) + #define HMCBSP_RCER_RCEA12_SHIFT (0x0000000C) + + #define HMCBSP_RCER_RCEA12_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCER_RCEA12) + + #define HMCBSP_RCER_RCEA12_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCER_RCEA12,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCER_RCEA13 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCER_RCEA13_MASK (0x00002000) + #define HMCBSP_RCER_RCEA13_SHIFT (0x0000000D) + + #define HMCBSP_RCER_RCEA13_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCER_RCEA13) + + #define HMCBSP_RCER_RCEA13_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCER_RCEA13,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCER_RCEA14 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCER_RCEA14_MASK (0x00004000) + #define HMCBSP_RCER_RCEA14_SHIFT (0x0000000E) + + #define HMCBSP_RCER_RCEA14_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCER_RCEA14) + + #define HMCBSP_RCER_RCEA14_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCER_RCEA14,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCER_RCEA15 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCER_RCEA15_MASK (0x00008000) + #define HMCBSP_RCER_RCEA15_SHIFT (0x0000000F) + + #define HMCBSP_RCER_RCEA15_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCER_RCEA15) + + #define HMCBSP_RCER_RCEA15_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCER_RCEA15,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCER_RCEB0 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCER_RCEB0_MASK (0x00010000) + #define HMCBSP_RCER_RCEB0_SHIFT (0x00000010) + + #define HMCBSP_RCER_RCEB0_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCER_RCEB0) + + #define HMCBSP_RCER_RCEB0_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCER_RCEB0,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCER_RCEB1 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCER_RCEB1_MASK (0x00020000) + #define HMCBSP_RCER_RCEB1_SHIFT (0x00000011) + + #define HMCBSP_RCER_RCEB1_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCER_RCEB1) + + #define HMCBSP_RCER_RCEB1_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCER_RCEB1,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCER_RCEB2 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCER_RCEB2_MASK (0x00040000) + #define HMCBSP_RCER_RCEB2_SHIFT (0x00000012) + + #define HMCBSP_RCER_RCEB2_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCER_RCEB2) + + #define HMCBSP_RCER_RCEB2_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCER_RCEB2,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCER_RCEB3 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCER_RCEB3_MASK (0x00080000) + #define HMCBSP_RCER_RCEB3_SHIFT (0x00000013) + + #define HMCBSP_RCER_RCEB3_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCER_RCEB3) + + #define HMCBSP_RCER_RCEB3_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCER_RCEB3,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCER_RCEB4 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCER_RCEB4_MASK (0x00100000) + #define HMCBSP_RCER_RCEB4_SHIFT (0x00000014) + + #define HMCBSP_RCER_RCEB4_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCER_RCEB4) + + #define HMCBSP_RCER_RCEB4_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCER_RCEB4,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCER_RCEB5 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCER_RCEB5_MASK (0x00200000) + #define HMCBSP_RCER_RCEB5_SHIFT (0x00000015) + + #define HMCBSP_RCER_RCEB5_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCER_RCEB5) + + #define HMCBSP_RCER_RCEB5_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCER_RCEB5,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCER_RCEB6 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCER_RCEB6_MASK (0x00400000) + #define HMCBSP_RCER_RCEB6_SHIFT (0x00000016) + + #define HMCBSP_RCER_RCEB6_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCER_RCEB6) + + #define HMCBSP_RCER_RCEB6_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCER_RCEB6,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCER_RCEB7 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCER_RCEB7_MASK (0x00800000) + #define HMCBSP_RCER_RCEB7_SHIFT (0x00000017) + + #define HMCBSP_RCER_RCEB7_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCER_RCEB7) + + #define HMCBSP_RCER_RCEB7_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCER_RCEB7,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCER_RCEB8 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCER_RCEB8_MASK (0x01000000) + #define HMCBSP_RCER_RCEB8_SHIFT (0x00000018) + + #define HMCBSP_RCER_RCEB8_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCER_RCEB8) + + #define HMCBSP_RCER_RCEB8_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCER_RCEB8,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCER_RCEB9 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCER_RCEB9_MASK (0x02000000) + #define HMCBSP_RCER_RCEB9_SHIFT (0x00000019) + + #define HMCBSP_RCER_RCEB9_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCER_RCEB9) + + #define HMCBSP_RCER_RCEB9_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCER_RCEB9,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCER_RCEB10 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCER_RCEB10_MASK (0x04000000) + #define HMCBSP_RCER_RCEB10_SHIFT (0x0000001A) + + #define HMCBSP_RCER_RCEB10_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCER_RCEB10) + + #define HMCBSP_RCER_RCEB10_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCER_RCEB10,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCER_RCEB11 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCER_RCEB11_MASK (0x08000000) + #define HMCBSP_RCER_RCEB11_SHIFT (0x0000001B) + + #define HMCBSP_RCER_RCEB11_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCER_RCEB11) + + #define HMCBSP_RCER_RCEB11_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCER_RCEB11,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCER_RCEB12 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCER_RCEB12_MASK (0x10000000) + #define HMCBSP_RCER_RCEB12_SHIFT (0x0000001C) + + #define HMCBSP_RCER_RCEB12_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCER_RCEB12) + + #define HMCBSP_RCER_RCEB12_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCER_RCEB12,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCER_RCEB13 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCER_RCEB13_MASK (0x20000000) + #define HMCBSP_RCER_RCEB13_SHIFT (0x0000001D) + + #define HMCBSP_RCER_RCEB13_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCER_RCEB13) + + #define HMCBSP_RCER_RCEB13_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCER_RCEB13,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCER_RCEB14 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCER_RCEB14_MASK (0x40000000) + #define HMCBSP_RCER_RCEB14_SHIFT (0x0000001E) + + #define HMCBSP_RCER_RCEB14_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCER_RCEB14) + + #define HMCBSP_RCER_RCEB14_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCER_RCEB14,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCER_RCEB15 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCER_RCEB15_MASK (0x80000000) + #define HMCBSP_RCER_RCEB15_SHIFT (0x0000001F) + + #define HMCBSP_RCER_RCEB15_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_RCER_RCEB15) + + #define HMCBSP_RCER_RCEB15_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_RCER_RCEB15,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_RCER +\*----------------------------------------------------------------------------*/ + #define HMCBSP_RCER_GET(RegAddr) HREG32_GET(RegAddr) + #define HMCBSP_RCER_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HMCBSP_RCER_CFG(RegAddr,rcea0,rcea1,rcea2,rcea3,rcea4,rcea5,rcea6,\ + rcea7,rcea8,rcea9,rcea10,rcea11,rcea12,rcea13,rcea14,rcea15,rceb0,rceb1,\ + rceb2,rceb3,rceb4,rceb5,rceb6,rceb7,rceb8,rceb9,rceb10,rceb11,rceb12,rceb13,\ + rceb14,rceb15) REG32(RegAddr)=(UINT32)(\ + HFIELD_SHIFT(HMCBSP_RCER_RCEA0, rcea0 )|\ + HFIELD_SHIFT(HMCBSP_RCER_RCEA1, rcea1 )|\ + HFIELD_SHIFT(HMCBSP_RCER_RCEA2, rcea2 )|\ + HFIELD_SHIFT(HMCBSP_RCER_RCEA3, rcea3 )|\ + HFIELD_SHIFT(HMCBSP_RCER_RCEA4, rcea4 )|\ + HFIELD_SHIFT(HMCBSP_RCER_RCEA5, rcea5 )|\ + HFIELD_SHIFT(HMCBSP_RCER_RCEA6, rcea6 )|\ + HFIELD_SHIFT(HMCBSP_RCER_RCEA7, rcea7 )|\ + HFIELD_SHIFT(HMCBSP_RCER_RCEA8, rcea8 )|\ + HFIELD_SHIFT(HMCBSP_RCER_RCEA9, rcea9 )|\ + HFIELD_SHIFT(HMCBSP_RCER_RCEA10,rcea10)|\ + HFIELD_SHIFT(HMCBSP_RCER_RCEA11,rcea11)|\ + HFIELD_SHIFT(HMCBSP_RCER_RCEA12,rcea12)|\ + HFIELD_SHIFT(HMCBSP_RCER_RCEA13,rcea13)|\ + HFIELD_SHIFT(HMCBSP_RCER_RCEA14,rcea14)|\ + HFIELD_SHIFT(HMCBSP_RCER_RCEA15,rcea15)|\ + HFIELD_SHIFT(HMCBSP_RCER_RCEB0, rceb0 )|\ + HFIELD_SHIFT(HMCBSP_RCER_RCEB1, rceb1 )|\ + HFIELD_SHIFT(HMCBSP_RCER_RCEB2, rceb2 )|\ + HFIELD_SHIFT(HMCBSP_RCER_RCEB3, rceb3 )|\ + HFIELD_SHIFT(HMCBSP_RCER_RCEB4, rceb4 )|\ + HFIELD_SHIFT(HMCBSP_RCER_RCEB5, rceb5 )|\ + HFIELD_SHIFT(HMCBSP_RCER_RCEB6, rceb6 )|\ + HFIELD_SHIFT(HMCBSP_RCER_RCEB7, rceb7 )|\ + HFIELD_SHIFT(HMCBSP_RCER_RCEB8, rceb8 )|\ + HFIELD_SHIFT(HMCBSP_RCER_RCEB9, rceb9 )|\ + HFIELD_SHIFT(HMCBSP_RCER_RCEB10,rceb10)|\ + HFIELD_SHIFT(HMCBSP_RCER_RCEB11,rceb11)|\ + HFIELD_SHIFT(HMCBSP_RCER_RCEB12,rceb12)|\ + HFIELD_SHIFT(HMCBSP_RCER_RCEB13,rceb13)|\ + HFIELD_SHIFT(HMCBSP_RCER_RCEB14,rceb14)|\ + HFIELD_SHIFT(HMCBSP_RCER_RCEB15,rceb15) \ + ) + +/******************************************************************************\ +* HMCBSP_XCER0 - serial port 0 transmit channel enable register +* HMCBSP_XCER1 - serial port 1 transmit channel enable register +* HMCBSP_XCER2 - serial port 2 transmit channel enable register (1) +* +* (1) only on devices with three serial ports +* +* Fields: +* +\******************************************************************************/ + #define HMCBSP_XCER0_ADDR (HMCBSP_BASE0_ADDR+0x0020) + #define HMCBSP_XCER1_ADDR (HMCBSP_BASE1_ADDR+0x0020) + #define HMCBSP_XCER0 REG32(HMCBSP_XCER0_ADDR) + #define HMCBSP_XCER1 REG32(HMCBSP_XCER1_ADDR) + +#if (HMCBSP_PORT_CNT==3) + #define HMCBSP_XCER2_ADDR (HMCBSP_BASE2_ADDR+0x0020) + #define HMCBSP_XCER2 REG32(HMCBSP_XCER2_ADDR) +#endif + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCER_XCEA0 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCER_XCEA0_MASK (0x00000001) + #define HMCBSP_XCER_XCEA0_SHIFT (0x00000000) + + #define HMCBSP_XCER_XCEA0_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCER_XCEA0) + + #define HMCBSP_XCER_XCEA0_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCER_XCEA0,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCER_XCEA1 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCER_XCEA1_MASK (0x00000002) + #define HMCBSP_XCER_XCEA1_SHIFT (0x00000001) + + #define HMCBSP_XCER_XCEA1_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCER_XCEA1) + + #define HMCBSP_XCER_XCEA1_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCER_XCEA1,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCER_XCEA2 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCER_XCEA2_MASK (0x00000004) + #define HMCBSP_XCER_XCEA2_SHIFT (0x00000002) + + #define HMCBSP_XCER_XCEA2_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCER_XCEA2) + + #define HMCBSP_XCER_XCEA2_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCER_XCEA2,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCER_XCEA3 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCER_XCEA3_MASK (0x00000008) + #define HMCBSP_XCER_XCEA3_SHIFT (0x00000003) + + #define HMCBSP_XCER_XCEA3_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCER_XCEA3) + + #define HMCBSP_XCER_XCEA3_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCER_XCEA3,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCER_XCEA4 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCER_XCEA4_MASK (0x00000010) + #define HMCBSP_XCER_XCEA4_SHIFT (0x00000004) + + #define HMCBSP_XCER_XCEA4_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCER_XCEA4) + + #define HMCBSP_XCER_XCEA4_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCER_XCEA4,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCER_XCEA5 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCER_XCEA5_MASK (0x00000020) + #define HMCBSP_XCER_XCEA5_SHIFT (0x00000005) + + #define HMCBSP_XCER_XCEA5_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCER_XCEA5) + + #define HMCBSP_XCER_XCEA5_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCER_XCEA5,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCER_XCEA6 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCER_XCEA6_MASK (0x00000040) + #define HMCBSP_XCER_XCEA6_SHIFT (0x00000006) + + #define HMCBSP_XCER_XCEA6_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCER_XCEA6) + + #define HMCBSP_XCER_XCEA6_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCER_XCEA6,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCER_XCEA7 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCER_XCEA7_MASK (0x00000080) + #define HMCBSP_XCER_XCEA7_SHIFT (0x00000007) + + #define HMCBSP_XCER_XCEA7_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCER_XCEA7) + + #define HMCBSP_XCER_XCEA7_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCER_XCEA7,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCER_XCEA8 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCER_XCEA8_MASK (0x00000100) + #define HMCBSP_XCER_XCEA8_SHIFT (0x00000008) + + #define HMCBSP_XCER_XCEA8_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCER_XCEA8) + + #define HMCBSP_XCER_XCEA8_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCER_XCEA8,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCER_XCEA9 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCER_XCEA9_MASK (0x00000200) + #define HMCBSP_XCER_XCEA9_SHIFT (0x00000009) + + #define HMCBSP_XCER_XCEA9_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCER_XCEA9) + + #define HMCBSP_XCER_XCEA9_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCER_XCEA9,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCER_XCEA10 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCER_XCEA10_MASK (0x00000400) + #define HMCBSP_XCER_XCEA10_SHIFT (0x0000000A) + + #define HMCBSP_XCER_XCEA10_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCER_XCEA10) + + #define HMCBSP_XCER_XCEA10_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCER_XCEA10,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCER_XCEA11 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCER_XCEA11_MASK (0x00000800) + #define HMCBSP_XCER_XCEA11_SHIFT (0x0000000B) + + #define HMCBSP_XCER_XCEA11_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCER_XCEA11) + + #define HMCBSP_XCER_XCEA11_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCER_XCEA11,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCER_XCEA12 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCER_XCEA12_MASK (0x00001000) + #define HMCBSP_XCER_XCEA12_SHIFT (0x0000000C) + + #define HMCBSP_XCER_XCEA12_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCER_XCEA12) + + #define HMCBSP_XCER_XCEA12_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCER_XCEA12,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCER_XCEA13 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCER_XCEA13_MASK (0x00002000) + #define HMCBSP_XCER_XCEA13_SHIFT (0x0000000D) + + #define HMCBSP_XCER_XCEA13_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCER_XCEA13) + + #define HMCBSP_XCER_XCEA13_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCER_XCEA13,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCER_XCEA14 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCER_XCEA14_MASK (0x00004000) + #define HMCBSP_XCER_XCEA14_SHIFT (0x0000000E) + + #define HMCBSP_XCER_XCEA14_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCER_XCEA14) + + #define HMCBSP_XCER_XCEA14_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCER_XCEA14,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCER_XCEA15 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCER_XCEA15_MASK (0x00008000) + #define HMCBSP_XCER_XCEA15_SHIFT (0x0000000F) + + #define HMCBSP_XCER_XCEA15_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCER_XCEA15) + + #define HMCBSP_XCER_XCEA15_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCER_XCEA15,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCER_XCEB0 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCER_XCEB0_MASK (0x00010000) + #define HMCBSP_XCER_XCEB0_SHIFT (0x00000010) + + #define HMCBSP_XCER_XCEB0_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCER_XCEB0) + + #define HMCBSP_XCER_XCEB0_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCER_XCEB0,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCER_XCEB1 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCER_XCEB1_MASK (0x00020000) + #define HMCBSP_XCER_XCEB1_SHIFT (0x00000011) + + #define HMCBSP_XCER_XCEB1_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCER_XCEB1) + + #define HMCBSP_XCER_XCEB1_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCER_XCEB1,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCER_XCEB2 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCER_XCEB2_MASK (0x00040000) + #define HMCBSP_XCER_XCEB2_SHIFT (0x00000012) + + #define HMCBSP_XCER_XCEB2_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCER_XCEB2) + + #define HMCBSP_XCER_XCEB2_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCER_XCEB2,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCER_XCEB3 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCER_XCEB3_MASK (0x00080000) + #define HMCBSP_XCER_XCEB3_SHIFT (0x00000013) + + #define HMCBSP_XCER_XCEB3_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCER_XCEB3) + + #define HMCBSP_XCER_XCEB3_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCER_XCEB3,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCER_XCEB4 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCER_XCEB4_MASK (0x00100000) + #define HMCBSP_XCER_XCEB4_SHIFT (0x00000014) + + #define HMCBSP_XCER_XCEB4_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCER_XCEB4) + + #define HMCBSP_XCER_XCEB4_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCER_XCEB4,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCER_XCEB5 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCER_XCEB5_MASK (0x00200000) + #define HMCBSP_XCER_XCEB5_SHIFT (0x00000015) + + #define HMCBSP_XCER_XCEB5_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCER_XCEB5) + + #define HMCBSP_XCER_XCEB5_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCER_XCEB5,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCER_XCEB6 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCER_XCEB6_MASK (0x00400000) + #define HMCBSP_XCER_XCEB6_SHIFT (0x00000016) + + #define HMCBSP_XCER_XCEB6_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCER_XCEB6) + + #define HMCBSP_XCER_XCEB6_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCER_XCEB6,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCER_XCEB7 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCER_XCEB7_MASK (0x00800000) + #define HMCBSP_XCER_XCEB7_SHIFT (0x00000017) + + #define HMCBSP_XCER_XCEB7_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCER_XCEB7) + + #define HMCBSP_XCER_XCEB7_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCER_XCEB7,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCER_XCEB8 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCER_XCEB8_MASK (0x01000000) + #define HMCBSP_XCER_XCEB8_SHIFT (0x00000018) + + #define HMCBSP_XCER_XCEB8_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCER_XCEB8) + + #define HMCBSP_XCER_XCEB8_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCER_XCEB8,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCER_XCEB9 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCER_XCEB9_MASK (0x02000000) + #define HMCBSP_XCER_XCEB9_SHIFT (0x00000019) + + #define HMCBSP_XCER_XCEB9_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCER_XCEB9) + + #define HMCBSP_XCER_XCEB9_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCER_XCEB9,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCER_XCEB10 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCER_XCEB10_MASK (0x04000000) + #define HMCBSP_XCER_XCEB10_SHIFT (0x0000001A) + + #define HMCBSP_XCER_XCEB10_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCER_XCEB10) + + #define HMCBSP_XCER_XCEB10_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCER_XCEB10,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCER_XCEB11 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCER_XCEB11_MASK (0x08000000) + #define HMCBSP_XCER_XCEB11_SHIFT (0x0000001B) + + #define HMCBSP_XCER_XCEB11_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCER_XCEB11) + + #define HMCBSP_XCER_XCEB11_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCER_XCEB11,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCER_XCEB12 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCER_XCEB12_MASK (0x10000000) + #define HMCBSP_XCER_XCEB12_SHIFT (0x0000001C) + + #define HMCBSP_XCER_XCEB12_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCER_XCEB12) + + #define HMCBSP_XCER_XCEB12_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCER_XCEB12,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCER_XCEB13 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCER_XCEB13_MASK (0x20000000) + #define HMCBSP_XCER_XCEB13_SHIFT (0x0000001D) + + #define HMCBSP_XCER_XCEB13_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCER_XCEB13) + + #define HMCBSP_XCER_XCEB13_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCER_XCEB13,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCER_XCEB14 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCER_XCEB14_MASK (0x40000000) + #define HMCBSP_XCER_XCEB14_SHIFT (0x0000001E) + + #define HMCBSP_XCER_XCEB14_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCER_XCEB14) + + #define HMCBSP_XCER_XCEB14_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCER_XCEB14,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCER_XCEB15 +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCER_XCEB15_MASK (0x80000000) + #define HMCBSP_XCER_XCEB15_SHIFT (0x0000001F) + + #define HMCBSP_XCER_XCEB15_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_XCER_XCEB15) + + #define HMCBSP_XCER_XCEB15_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_XCER_XCEB15,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_XCER +\*----------------------------------------------------------------------------*/ + #define HMCBSP_XCER_GET(RegAddr) HREG32_GET(RegAddr) + #define HMCBSP_XCER_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HMCBSP_XCER_CFG(RegAddr,xcea0,xcea1,xcea2,xcea3,xcea4,xcea5,xcea6,\ + xcea7,xcea8,xcea9,xcea10,xcea11,xcea12,xcea13,xcea14,xcea15,xceb0,xceb1,\ + xceb2,xceb3,xceb4,xceb5,xceb6,xceb7,xceb8,xceb9,xceb10,xceb11,xceb12,xceb13,\ + xceb14,xceb15) REG32(RegAddr)=(UINT32)(\ + HFIELD_SHIFT(HMCBSP_XCER_XCEA0, xcea0 )|\ + HFIELD_SHIFT(HMCBSP_XCER_XCEA1, xcea1 )|\ + HFIELD_SHIFT(HMCBSP_XCER_XCEA2, xcea2 )|\ + HFIELD_SHIFT(HMCBSP_XCER_XCEA3, xcea3 )|\ + HFIELD_SHIFT(HMCBSP_XCER_XCEA4, xcea4 )|\ + HFIELD_SHIFT(HMCBSP_XCER_XCEA5, xcea5 )|\ + HFIELD_SHIFT(HMCBSP_XCER_XCEA6, xcea6 )|\ + HFIELD_SHIFT(HMCBSP_XCER_XCEA7, xcea7 )|\ + HFIELD_SHIFT(HMCBSP_XCER_XCEA8, xcea8 )|\ + HFIELD_SHIFT(HMCBSP_XCER_XCEA9, xcea9 )|\ + HFIELD_SHIFT(HMCBSP_XCER_XCEA10,xcea10)|\ + HFIELD_SHIFT(HMCBSP_XCER_XCEA11,xcea11)|\ + HFIELD_SHIFT(HMCBSP_XCER_XCEA12,xcea12)|\ + HFIELD_SHIFT(HMCBSP_XCER_XCEA13,xcea13)|\ + HFIELD_SHIFT(HMCBSP_XCER_XCEA14,xcea14)|\ + HFIELD_SHIFT(HMCBSP_XCER_XCEA15,xcea15)|\ + HFIELD_SHIFT(HMCBSP_XCER_XCEB0, xceb0 )|\ + HFIELD_SHIFT(HMCBSP_XCER_XCEB1, xceb1 )|\ + HFIELD_SHIFT(HMCBSP_XCER_XCEB2, xceb2 )|\ + HFIELD_SHIFT(HMCBSP_XCER_XCEB3, xceb3 )|\ + HFIELD_SHIFT(HMCBSP_XCER_XCEB4, xceb4 )|\ + HFIELD_SHIFT(HMCBSP_XCER_XCEB5, xceb5 )|\ + HFIELD_SHIFT(HMCBSP_XCER_XCEB6, xceb6 )|\ + HFIELD_SHIFT(HMCBSP_XCER_XCEB7, xceb7 )|\ + HFIELD_SHIFT(HMCBSP_XCER_XCEB8, xceb8 )|\ + HFIELD_SHIFT(HMCBSP_XCER_XCEB9, xceb9 )|\ + HFIELD_SHIFT(HMCBSP_XCER_XCEB10,xceb10)|\ + HFIELD_SHIFT(HMCBSP_XCER_XCEB11,xceb11)|\ + HFIELD_SHIFT(HMCBSP_XCER_XCEB12,xceb12)|\ + HFIELD_SHIFT(HMCBSP_XCER_XCEB13,xceb13)|\ + HFIELD_SHIFT(HMCBSP_XCER_XCEB14,xceb14)|\ + HFIELD_SHIFT(HMCBSP_XCER_XCEB15,xceb15) \ + ) + +/******************************************************************************\ +* HMCBSP_PCR0 - serial port 0 pin control register +* HMCBSP_PCR1 - serial port 1 pin control register +* HMCBSP_PCR2 - serial port 2 pin control register (1) +* +* (1) only on devices with three serial ports +* +* Fields: +* (RW) HMCBSP_PCR_CLKRP +* (RW) HMCBSP_PCR_CLKXP +* (RW) HMCBSP_PCR_FSRP +* (RW) HMCBSP_PCR_FSXP +* (R) HMCBSP_PCR_DRSTAT +* (RW) HMCBSP_PCR_DXSTAT +* (RW) HMCBSP_PCR_CLKSSTAT +* (RW) HMCBSP_PCR_CLKRM +* (RW) HMCBSP_PCR_CLKXM +* (RW) HMCBSP_PCR_FSRM +* (RW) HMCBSP_PCR_FSXM +* (RW) HMCBSP_PCR_RIOEN +* (RW) HMCBSP_PCR_XIOEN +* +\******************************************************************************/ + #define HMCBSP_PCR0_ADDR (HMCBSP_BASE0_ADDR+0x0024) + #define HMCBSP_PCR1_ADDR (HMCBSP_BASE1_ADDR+0x0024) + #define HMCBSP_PCR0 REG32(HMCBSP_PCR0_ADDR) + #define HMCBSP_PCR1 REG32(HMCBSP_PCR1_ADDR) + +#if (HMCBSP_PORT_CNT==3) + #define HMCBSP_PCR2_ADDR (HMCBSP_BASE2_ADDR+0x0024) + #define HMCBSP_PCR2 REG32(HMCBSP_PCR2_ADDR) +#endif + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_PCR_CLKRP +\*----------------------------------------------------------------------------*/ + #define HMCBSP_PCR_CLKRP_MASK (0x00000001) + #define HMCBSP_PCR_CLKRP_SHIFT (0x00000000) + + #define HMCBSP_PCR_CLKRP_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_PCR_CLKRP) + + #define HMCBSP_PCR_CLKRP_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_PCR_CLKRP,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_PCR_CLKXP +\*----------------------------------------------------------------------------*/ + #define HMCBSP_PCR_CLKXP_MASK (0x00000002) + #define HMCBSP_PCR_CLKXP_SHIFT (0x00000001) + + #define HMCBSP_PCR_CLKXP_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_PCR_CLKXP) + + #define HMCBSP_PCR_CLKXP_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_PCR_CLKXP,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_PCR_FSRP +\*----------------------------------------------------------------------------*/ + #define HMCBSP_PCR_FSRP_MASK (0x00000004) + #define HMCBSP_PCR_FSRP_SHIFT (0x00000002) + + #define HMCBSP_PCR_FSRP_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_PCR_FSRP) + + #define HMCBSP_PCR_FSRP_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_PCR_FSRP,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_PCR_FSXP +\*----------------------------------------------------------------------------*/ + #define HMCBSP_PCR_FSXP_MASK (0x00000008) + #define HMCBSP_PCR_FSXP_SHIFT (0x00000003) + + #define HMCBSP_PCR_FSXP_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_PCR_FSXP) + + #define HMCBSP_PCR_FSXP_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_PCR_FSXP,Val) + +/*----------------------------------------------------------------------------*\ +* (R) HMCBSP_PCR_DTSTAT +\*----------------------------------------------------------------------------*/ + #define HMCBSP_PCR_DRSTAT_MASK (0x00000010) + #define HMCBSP_PCR_DRSTAT_SHIFT (0x00000004) + + #define HMCBSP_PCR_DRSTAT_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_PCR_DRSTAT) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_PCR_DXSTAT +\*----------------------------------------------------------------------------*/ + #define HMCBSP_PCR_DXSTAT_MASK (0x00000020) + #define HMCBSP_PCR_DXSTAT_SHIFT (0x00000005) + + #define HMCBSP_PCR_DXSTAT_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_PCR_DXSTAT) + + #define HMCBSP_PCR_DXSTAT_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_PCR_DXSTAT,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_PCR_CLKSSTAT +\*----------------------------------------------------------------------------*/ + #define HMCBSP_PCR_CLKSSTAT_MASK (0x00000040) + #define HMCBSP_PCR_CLKSSTAT_SHIFT (0x00000006) + + #define HMCBSP_PCR_CLKSSTAT_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_PCR_CLKSSTAT) + + #define HMCBSP_PCR_CLKSSTAT_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_PCR_CLKSSTAT,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_PCR_CLKRM +\*----------------------------------------------------------------------------*/ + #define HMCBSP_PCR_CLKRM_MASK (0x00000100) + #define HMCBSP_PCR_CLKRM_SHIFT (0x00000008) + + #define HMCBSP_PCR_CLKRM_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_PCR_CLKRM) + + #define HMCBSP_PCR_CLKRM_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_PCR_CLKRM,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_PCR_CLKXM +\*----------------------------------------------------------------------------*/ + #define HMCBSP_PCR_CLKXM_MASK (0x00000200) + #define HMCBSP_PCR_CLKXM_SHIFT (0x00000009) + + #define HMCBSP_PCR_CLKXM_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_PCR_CLKXM) + + #define HMCBSP_PCR_CLKXM_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_PCR_CLKXM,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_PCR_FSRM +\*----------------------------------------------------------------------------*/ + #define HMCBSP_PCR_FSRM_MASK (0x00000400) + #define HMCBSP_PCR_FSRM_SHIFT (0x0000000A) + + #define HMCBSP_PCR_FSRM_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_PCR_FSRM) + + #define HMCBSP_PCR_FSRM_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_PCR_FSRM,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_PCR_FSXM +\*----------------------------------------------------------------------------*/ + #define HMCBSP_PCR_FSXM_MASK (0x00000800) + #define HMCBSP_PCR_FSXM_SHIFT (0x0000000B) + + #define HMCBSP_PCR_FSXM_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_PCR_FSXM) + + #define HMCBSP_PCR_FSXM_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_PCR_FSXM,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_PCR_RIOEN +\*----------------------------------------------------------------------------*/ + #define HMCBSP_PCR_RIOEN_MASK (0x00001000) + #define HMCBSP_PCR_RIOEN_SHIFT (0x0000000C) + + #define HMCBSP_PCR_RIOEN_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_PCR_RIOEN) + + #define HMCBSP_PCR_RIOEN_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_PCR_RIOEN,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_PCR_XIOEN +\*----------------------------------------------------------------------------*/ + #define HMCBSP_PCR_XIOEN_MASK (0x00002000) + #define HMCBSP_PCR_XIOEN_SHIFT (0x0000000D) + + #define HMCBSP_PCR_XIOEN_GET(RegAddr) \ + HFIELD_GET(RegAddr,HMCBSP_PCR_XIOEN) + + #define HMCBSP_PCR_XIOEN_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HMCBSP_PCR_XIOEN,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HMCBSP_PCR +\*----------------------------------------------------------------------------*/ + #define HMCBSP_PCR_GET(RegAddr) HREG32_GET(RegAddr) + #define HMCBSP_PCR_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HMCBSP_PCR_CFG(RegAddr,clkrp,clkxp,fsrp,fsxp,dxstat,clksstat,clkrm,\ + clkxm,fsrm,fsxm,rioen,xioen) REG32(RegAddr)=(UINT32)(\ + HFIELD_SHIFT(HMCBSP_PCR_CLKRP , clkrp )|\ + HFIELD_SHIFT(HMCBSP_PCR_CLKXP , clkxp )|\ + HFIELD_SHIFT(HMCBSP_PCR_FSRP , fsrp )|\ + HFIELD_SHIFT(HMCBSP_PCR_FSXP , fsxp )|\ + HFIELD_SHIFT(HMCBSP_PCR_DXSTAT , dxstat )|\ + HFIELD_SHIFT(HMCBSP_PCR_CLKSSTAT, clksstat)|\ + HFIELD_SHIFT(HMCBSP_PCR_CLKRM , clkrm )|\ + HFIELD_SHIFT(HMCBSP_PCR_CLKXM , clkxm )|\ + HFIELD_SHIFT(HMCBSP_PCR_FSRM , fsrm )|\ + HFIELD_SHIFT(HMCBSP_PCR_FSXM , fsxm )|\ + HFIELD_SHIFT(HMCBSP_PCR_RIOEN , rioen )|\ + HFIELD_SHIFT(HMCBSP_PCR_XIOEN , xioen ) \ + ) + +/******************************************************************************/ + +#endif /* MCBSP_SUPPORT */ +#endif /* _MCBSPHAL_H_ */ +/******************************************************************************\ +* End of mcbsphal.h +\******************************************************************************/ + +/******************************************************************************\ +* Copyright (C) 1999-2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... pwrhal.h +* DATE CREATED.. 11/11/1999 +* LAST MODIFIED. 03/08/2000 +* +*------------------------------------------------------------------------------ +* DESCRIPTION: (HAL interface file for the PWR module) +* +* Registers Covered: +* (RW) HPWR_PDCTL - power down control register (1) + +* (1) only on CHIP_6202, CHIP_6203 +* +\******************************************************************************/ +#ifndef _PWRHAL_H_ +#define _PWRHAL_H_ + +#if (PWR_SUPPORT) + #define HPWR_BASE_ADDR (HCHIP_PERBASE_ADDR+0x001C0000) + +/******************************************************************************\ +* HPWR_PDCTL - power down control register (1) +* +* Fields: +* (RW) HPWR_PDCTL_DMA +* (RW) HPWR_PDCTL_EMIF +* (RW) HPWR_PDCTL_MCBSP0 +* (RW) HPWR_PDCTL_MCBSP1 +* (RW) HPWR_PDCTL_MCBSP2 +* +\******************************************************************************/ +#if (CHIP_6202) + #define HPWR_PDCTL_ADDR (HPWR_BASE_ADDR+0x0200) + #define HPWR_PDCTL REG32(HPWR_PDCTL_ADDR) +#else + #define HPWR_PDCTL_ADDR (HCHIP_NULL_ADDR) + #define HPWR_PDCTL REG32(HPWR_PDCTL_ADDR) +#endif + +/*----------------------------------------------------------------------------*\ +* (RW) HPWR_PDCTL_DMA +\*----------------------------------------------------------------------------*/ + #define HPWR_PDCTL_DMA_MASK (0x00000001) + #define HPWR_PDCTL_DMA_SHIFT (0x00000000) + + #define HPWR_PDCTL_DMA_GET(RegAddr) \ + HFIELD_GET(RegAddr,HPWR_PDCTL_DMA) + + #define HPWR_PDCTL_DMA_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HPWR_PDCTL_DMA,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HPWR_PDCTL_EMIF +\*----------------------------------------------------------------------------*/ + #define HPWR_PDCTL_EMIF_MASK (0x00000002) + #define HPWR_PDCTL_EMIF_SHIFT (0x00000001) + + #define HPWR_PDCTL_EMIF_GET(RegAddr) \ + HFIELD_GET(RegAddr,HPWR_PDCTL_EMIF) + + #define HPWR_PDCTL_EMIF_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HPWR_PDCTL_EMIF,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HPWR_PDCTL_MCBSP0 +\*----------------------------------------------------------------------------*/ + #define HPWR_PDCTL_MCBSP0_MASK (0x00000004) + #define HPWR_PDCTL_MCBSP0_SHIFT (0x00000002) + + #define HPWR_PDCTL_MCBSP0_GET(RegAddr) \ + HFIELD_GET(RegAddr,HPWR_PDCTL_MCBSP0) + + #define HPWR_PDCTL_MCBSP0_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HPWR_PDCTL_MCBSP0,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HPWR_PDCTL_MCBSP1 +\*----------------------------------------------------------------------------*/ + #define HPWR_PDCTL_MCBSP1_MASK (0x00000008) + #define HPWR_PDCTL_MCBSP1_SHIFT (0x00000003) + + #define HPWR_PDCTL_MCBSP1_GET(RegAddr) \ + HFIELD_GET(RegAddr,HPWR_PDCTL_MCBSP1) + + #define HPWR_PDCTL_MCBSP1_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HPWR_PDCTL_MCBSP1,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HPWR_PDCTL_MCBSP2 +\*----------------------------------------------------------------------------*/ + #define HPWR_PDCTL_MCBSP2_MASK (0x00000010) + #define HPWR_PDCTL_MCBSP2_SHIFT (0x00000004) + + #define HPWR_PDCTL_MCBSP2_GET(RegAddr) \ + HFIELD_GET(RegAddr,HPWR_PDCTL_MCBSP2) + + #define HPWR_PDCTL_MCBSP2_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HPWR_PDCTL_MCBSP2,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) HPWR_PDCTL +\*----------------------------------------------------------------------------*/ + #define HPWR_PDCTL_GET(RegAddr) HREG32_GET(RegAddr) + #define HPWR_PDCTL_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HPWR_PDCTL_CFG(RegAddr,dma,emif,mcbsp0,mcbsp1,mcbsp2)\ + REG32(RegAddr) = (\ + HFIELD_SHIFT(HPWR_PDCTL_DMA,dma)|\ + HFIELD_SHIFT(HPWR_PDCTL_EMIF,emif)|\ + HFIELD_SHIFT(HPWR_PDCTL_MCBSP0,mcbsp0)|\ + HFIELD_SHIFT(HPWR_PDCTL_MCBSP1,mcbsp1)|\ + HFIELD_SHIFT(HPWR_PDCTL_MCBSP2,mcbsp2)\ + ) + +/*----------------------------------------------------------------------------*/ + +#endif /* PWR_SUPPORT */ +#endif /* _PWRHAL_H_ */ +/******************************************************************************\ +* End of pwrhal.h +\******************************************************************************/ + +/******************************************************************************\ +* Copyright (C) 1999-2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... timerhal.h +* DATE CREATED.. 06/20/1999 +* LAST MODIFIED. 03/08/2000 +* +*------------------------------------------------------------------------------ +* DESCRIPTION: (HAL interface file for the TIMER module) +* +* Registers Covered: +* (RW) HTIMER_CTL0 - timer 0 control register +* (RW) HTIMER_CTL1 - timer 1 control register +* (RW) HTIMER_PRD0 - timer 0 period register +* (RW) HTIMER_PRD1 - timer 1 perid register +* (RW) HTIMER_CNT0 - timer 0 count register +* (RW) HTIMER_CNT1 - timer 1 count register +* +\******************************************************************************/ +#ifndef _TIMERHAL_H_ +#define _TIMERHAL_H_ + +#if (TIMER_SUPPORT) +/*============================================================================*\ +* misc declarations +\*============================================================================*/ +#define HTIMER_BASE0_ADDR (HCHIP_PERBASE_ADDR+0x00140000) +#define HTIMER_BASE1_ADDR (HCHIP_PERBASE_ADDR+0x00180000) + +#define HTIMER_DEVICE_CNT (2) + +/******************************************************************************\ +* HTIMER_CTL0 - timer 0 control register +* HTIMER_CTL1 - timer 1 control register +* +* Fields: +* (RW) HTIMER_CTL_FUNC +* (RW) HTIMER_CTL_INVOUT +* (RW) HTIMER_CTL_DATOUT +* (RW) HTIMER_CTL_DATIN +* (RW) HTIMER_CTL_PWID +* (RW) HTIMER_CTL_GO +* (RW) HTIMER_CTL_HLD +* (RW) HTIMER_CTL_CP +* (RW) HTIMER_CTL_CLKSRC +* (RW) HTIMER_CTL_INVINP +* (R) HTIMER_CTL_TSTAT +* +\******************************************************************************/ + #define HTIMER_CTL0_ADDR (HTIMER_BASE0_ADDR+0x0000) + #define HTIMER_CTL1_ADDR (HTIMER_BASE1_ADDR+0x0000) + + #define HTIMER_CTL0 REG32(HTIMER_CTL0_ADDR) + #define HTIMER_CTL1 REG32(HTIMER_CTL1_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) TIMER_CTL_FUNC +\*----------------------------------------------------------------------------*/ + #define HTIMER_CTL_FUNC_MASK (0x00000001) + #define HTIMER_CTL_FUNC_SHIFT (0x00000000) + + #define HTIMER_CTL_FUNC_GET(RegAddr) \ + HFIELD_GET(RegAddr,HTIMER_CTL_FUNC) + + #define HTIMER_CTL_FUNC_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HTIMER_CTL_FUNC,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) TIMER_CTL_INVOUT +\*----------------------------------------------------------------------------*/ + #define HTIMER_CTL_INVOUT_MASK (0x00000002) + #define HTIMER_CTL_INVOUT_SHIFT (0x00000001) + + #define HTIMER_CTL_INVOUT_GET(RegAddr) \ + HFIELD_GET(RegAddr,HTIMER_CTL_INVOUT) + + #define HTIMER_CTL_INVOUT_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HTIMER_CTL_INVOUT,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) TIMER_CTL_DATOUT +\*----------------------------------------------------------------------------*/ + #define HTIMER_CTL_DATOUT_MASK (0x00000004) + #define HTIMER_CTL_DATOUT_SHIFT (0x00000002) + + #define HTIMER_CTL_DATOUT_GET(RegAddr) \ + HFIELD_GET(RegAddr,HTIMER_CTL_DATOUT) + + #define HTIMER_CTL_DATOUT_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HTIMER_CTL_DATOUT,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) TIMER_CTL_DATIN +\*----------------------------------------------------------------------------*/ + #define HTIMER_CTL_DATIN_MASK (0x00000008) + #define HTIMER_CTL_DATIN_SHIFT (0x00000003) + + #define HTIMER_CTL_DATIN_GET(RegAddr) \ + HFIELD_GET(RegAddr,HTIMER_CTL_DATIN) + + #define HTIMER_CTL_DATIN_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HTIMER_CTL_DATIN,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) TIMER_CTL_PWID +\*----------------------------------------------------------------------------*/ + #define HTIMER_CTL_PWID_MASK (0x00000010) + #define HTIMER_CTL_PWID_SHIFT (0x00000004) + + #define HTIMER_CTL_PWID_GET(RegAddr) \ + HFIELD_GET(RegAddr,HTIMER_CTL_PWID) + + #define HTIMER_CTL_PWID_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HTIMER_CTL_PWID,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) TIMER_CTL_GO +\*----------------------------------------------------------------------------*/ + #define HTIMER_CTL_GO_MASK (0x00000040) + #define HTIMER_CTL_GO_SHIFT (0x00000006) + + #define HTIMER_CTL_GO_GET(RegAddr) \ + HFIELD_GET(RegAddr,HTIMER_CTL_GO) + + #define HTIMER_CTL_GO_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HTIMER_CTL_GO,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) TIMER_CTL_HLD +\*----------------------------------------------------------------------------*/ + #define HTIMER_CTL_HLD_MASK (0x00000080) + #define HTIMER_CTL_HLD_SHIFT (0x00000007) + + #define HTIMER_CTL_HLD_GET(RegAddr) \ + HFIELD_GET(RegAddr,HTIMER_CTL_HLD) + + #define HTIMER_CTL_HLD_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HTIMER_CTL_HLD,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) TIMER_CTL_CP +\*----------------------------------------------------------------------------*/ + #define HTIMER_CTL_CP_MASK (0x00000100) + #define HTIMER_CTL_CP_SHIFT (0x00000008) + + #define HTIMER_CTL_CP_GET(RegAddr) \ + HFIELD_GET(RegAddr,HTIMER_CTL_CP) + + #define HTIMER_CTL_CP_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HTIMER_CTL_CP,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) TIMER_CTL_CLKSRC +\*----------------------------------------------------------------------------*/ + #define HTIMER_CTL_CLKSRC_MASK (0x00000200) + #define HTIMER_CTL_CLKSRC_SHIFT (0x00000009) + + #define HTIMER_CTL_CLKSRC_GET(RegAddr) \ + HFIELD_GET(RegAddr,HTIMER_CTL_CLKSRC) + + #define HTIMER_CTL_CLKSRC_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HTIMER_CTL_CLKSRC,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) TIMER_CTL_INVINP +\*----------------------------------------------------------------------------*/ + #define HTIMER_CTL_INVINP_MASK (0x00000400) + #define HTIMER_CTL_INVINP_SHIFT (0x0000000A) + + #define HTIMER_CTL_INVINP_GET(RegAddr) \ + HFIELD_GET(RegAddr,HTIMER_CTL_INVINP) + + #define HTIMER_CTL_INVINP_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HTIMER_CTL_INVINP,Val) + +/*----------------------------------------------------------------------------*\ +* (R) TIMER_CTL_TSTAT +\*----------------------------------------------------------------------------*/ + #define HTIMER_CTL_TSTAT_MASK (0x00000800) + #define HTIMER_CTL_TSTAT_SHIFT (0x0000000B) + + #define HTIMER_CTL_TSTAT_GET(RegAddr) \ + HFIELD_GET(RegAddr,HTIMER_CTL_TSTAT) + +/*----------------------------------------------------------------------------*\ +* (RW) TIMER_CTL +\*----------------------------------------------------------------------------*/ + #define HTIMER_CTL_GET(RegAddr) HREG32_GET(RegAddr) + + #define HTIMER_CTL_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HTIMER_CTL_CFG(RegAddr,func,invout,datout,datin,pwid,go,hld,cp,\ + clksrc,invinp) REG32(RegAddr) = (\ + HFIELD_SHIFT(HTIMER_CTL_FUNC, func) |\ + HFIELD_SHIFT(HTIMER_CTL_DATOUT, datout) |\ + HFIELD_SHIFT(HTIMER_CTL_DATIN, datin) |\ + HFIELD_SHIFT(HTIMER_CTL_GO, go) |\ + HFIELD_SHIFT(HTIMER_CTL_HLD, hld) |\ + HFIELD_SHIFT(HTIMER_CTL_CP, cp) |\ + HFIELD_SHIFT(HTIMER_CTL_PWID, pwid) |\ + HFIELD_SHIFT(HTIMER_CTL_CLKSRC, clksrc) |\ + HFIELD_SHIFT(HTIMER_CTL_INVINP, invinp) |\ + HFIELD_SHIFT(HTIMER_CTL_INVOUT, invout) \ + ) + +/******************************************************************************\ +* HTIMER_PRD0 - timer 0 period register +* HTIMER_PRD1 - timer 1 period register +* +* Fields: +* (RW) PRD +* +\******************************************************************************/ + #define HTIMER_PRD0_ADDR (HTIMER_BASE0_ADDR+0x0004) + #define HTIMER_PRD1_ADDR (HTIMER_BASE1_ADDR+0x0004) + + #define HTIMER_PRD0 REG32(HTIMER_PRD0_ADDR) + #define HTIMER_PRD1 REG32(HTIMER_PRD1_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) TIMER_PRD_PRD +\*----------------------------------------------------------------------------*/ + #define HTIMER_PRD_PRD_MASK (0xFFFFFFFF) + #define HTIMER_PRD_PRD_SHIFT (0x00000000) + + #define HTIMER_PRD_PRD_GET(RegAddr) \ + HFIELD_GET(RegAddr,HTIMER_PRD_PRD) + + #define HTIMER_PRD_PRD_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HTIMER_PRD_PRD,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) TIMER_PRD +\*----------------------------------------------------------------------------*/ + #define HTIMER_PRD_GET(RegAddr) HREG32_GET(RegAddr) + + #define HTIMER_PRD_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HTIMER_PRD_CFG(RegAddr,Prd) REG32(RegAddr) = (UINT32)( \ + HFIELD_SHIFT(HTIMER_PRD_RRD,prd) \ + ) + +/******************************************************************************\ +* HTIMER_CNT0 - timer 0 count register +* HTIMER_CNT1 - timer 1 count register +* +* Fields: +* (RW) CNT +* +\******************************************************************************/ + #define HTIMER_CNT0_ADDR (HTIMER_BASE0_ADDR+0x0008) + #define HTIMER_CNT1_ADDR (HTIMER_BASE1_ADDR+0x0008) + + #define HTIMER_CNT0 REG32(HTIMER_CNT0_ADDR) + #define HTIMER_CNT1 REG32(HTIMER_CNT1_ADDR) + +/*----------------------------------------------------------------------------*\ +* (RW) TIMER_CNT_CNT +\*----------------------------------------------------------------------------*/ + #define HTIMER_CNT_CNT_MASK (0xFFFFFFFF) + #define HTIMER_CNT_CNT_SHIFT (0x00000000) + + #define HTIMER_CNT_CNT_GET(RegAddr) \ + HFIELD_GET(RegAddr,HTIMER_CNT_CNT) + + #define HTIMER_CNT_CNT_SET(RegAddr,Val) \ + HFIELD_SET(RegAddr,HTIMER_CNT_CNT,Val) + +/*----------------------------------------------------------------------------*\ +* (RW) TIMER_CNT +\*----------------------------------------------------------------------------*/ + #define HTIMER_CNT_GET(RegAddr) HREG32_GET(RegAddr) + + #define HTIMER_CNT_SET(RegAddr,Val) HREG32_SET(RegAddr,Val) + + #define HTIMER_CNT_CFG(RegAddr,Cnt) REG32(RegAddr) = (UINT32)( \ + HFIELD_SHIFT(HTIMER_CNT_CNT,cnt) \ + ) + +/*----------------------------------------------------------------------------*/ + +#endif /* TIMER_SUPPORT */ +#endif /* _TIMERHAL_H_ */ +/******************************************************************************\ +* End of timerhal.h +\******************************************************************************/ + + + +#endif /* _CSL_LEGACYHAL_H_ */ +/******************************************************************************\ +* End of csl_legacyhal.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_mcasp.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_mcasp.h new file mode 100644 index 0000000..666612b --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_mcasp.h @@ -0,0 +1,1780 @@ +/******************************************************************************\ +* Copyright (C) 1999-2002 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_mcasp.h +* DATE CREATED.. 08/10/2001 +* LAST MODIFIED. 02/25/2002 _write32, write32Cfg, read32, read32Cfg +* 02/14/2002 _getRbufAddrCfg()/_getXbufAddrCfg() +* MCASP_XBUFx / MCASP_RBUFx macros +* +\******************************************************************************/ +#ifndef _CSL_MCASP_H_ +#define _CSL_MCASP_H_ + +#include +#include +#include + + +#if (MCASP_SUPPORT) +/******************************************************************************\ +* scope and inline control macros +\******************************************************************************/ + +#ifdef __cplusplus +#define CSLAPI extern "C" far +#else +#define CSLAPI extern far +#endif + +#undef USEDEFS +#undef IDECL +#undef IDEF + +#ifdef _MCASP_MOD_ + #define IDECL CSLAPI + #define USEDEFS + #define IDEF +#else + #ifdef _INLINE + #define IDECL static inline + #define USEDEFS + #define IDEF static inline + #else + #define IDECL CSLAPI + #endif +#endif + +/******************************************************************************\ +* global macro declarations +\******************************************************************************/ + +/* MCASP_open() flags */ +#define MCASP_OPEN_RESET (0x00000001) + + +/* device identifiers for MCASP_open() */ +#define MCASP_DEV0 (0) +#if (_MCASP_PORT_CNT == 2) + #define MCASP_DEV1 (1) +#endif + + +/* device identifiers for MCASP_open() */ +#define MCASP_PORT0 MCASP_DEV0 +#if (_MCASP_PORT_CNT == 2) + #define MCASP_PORT1 MCASP_DEV1 +#endif + +/* select DIT vs. TDM mode */ +#define MCASP_XMT_DIT 1 +#define MCASP_XMT_TDM 0 + +/* direction = (transmitter only) MCASP_XMT or (receiver only) MCASP_RCV */ +/* or (both) MCASP_RCVXMT / MCASP_XMTRCV */ +#define MCASP_RCV 1 +#define MCASP_XMT 2 +#define MCASP_RCVXMT 3 +#define MCASP_XMTRCV 3 + +/* Mode for clk */ +#define MCASP_CLK_ASYNC 1 +#define MCASP_CLK_SYNC 0 + + +/* define DSP representation */ +//#define MCASP_DSP_INTEGER 0 +//#define MCASP_DSP_Q31 1 + +/* define Mode BURST or TDM for format*/ +#define MCASP_MODE_BURST 0 +#define MCASP_MODE_TDM 1 + +/* define Mode MSB/LSB first */ +#define MCASP_FORMAT_LSB 0 +#define MCASP_FORMAT_MSB 1 + +/* define Align */ +#define MCASP_FORMAT_LEFT 0 +#define MCASP_FORMAT_RIGHT 1 + + +/* Address Incrementation */ +#define MCASP_XBUF_BUFSIZE 4 +#define MCASP_RBUF_BUFSIZE 4 + +#define MCASP_DITCSR_NUMCHANNELS 6 +#define MCASP_DITCSR_BUFSIZE 4 +#define MCASP_DITCSR_RIGHT_OFFSET (MCASP_DITCSR_BUFSIZE*MCASP_DITCSR_NUMCHANNELS) + +#define MCASP_DITUDR_NUMCHANNELS 6 +#define MCASP_DITUDR_BUFSIZE 4 +#define MCASP_DITUDR_RIGHT_OFFSET (MCASP_DITUDR_BUFSIZE*MCASP_DITUDR_NUMCHANNELS) + +/* Status clear */ +#define MCASP_RSTAT_ROVRN 0 +#define MCASP_RSTAT_RSYNCERR 1 +#define MCASP_RSTAT_RCKFAIL 2 +#define MCASP_RSTAT_REVENSLOT 3 +#define MCASP_RSTAT_RLAST 4 +#define MCASP_RSTAT_RDATA 5 +#define MCASP_RSTAT_RSTAFRM 6 +#define MCASP_RSTAT_RDMAERR 7 +#define MCASP_RSTAT_RERR 8 + +#define MCASP_XSTAT_XUNDRN 0 +#define MCASP_XSTAT_XSYNCERR 1 +#define MCASP_XSTAT_XCKFAIL 2 +#define MCASP_XSTAT_XEVENSLOT 3 +#define MCASP_XSTAT_XLAST 4 +#define MCASP_XSTAT_XDATA 5 +#define MCASP_XSTAT_XSTAFRM 6 +#define MCASP_XSTAT_XDMAERR 7 +#define MCASP_XSTAT_XERR 8 + + +#define MCASP_XBUF0 0 +#define MCASP_XBUF1 1 +#define MCASP_XBUF2 2 +#define MCASP_XBUF3 3 +/* Fields for _MCASP_CHANNEL_CNT == 4 end here*/ + +#if (_MCASP_CHANNEL_CNT > 4) + #define MCASP_XBUF4 4 + #define MCASP_XBUF5 5 +#endif /* _MCASP_CHANNEL_CNT == 6 */ + +#if (_MCASP_CHANNEL_CNT > 6) + #define MCASP_XBUF6 6 + #define MCASP_XBUF7 7 +#endif /* _MCASP_CHANNEL_CNT == 8 */ + +#if (_MCASP_CHANNEL_CNT == 16) + #define MCASP_XBUF8 8 + #define MCASP_XBUF9 9 + #define MCASP_XBUF10 10 + #define MCASP_XBUF11 11 + #define MCASP_XBUF12 12 + #define MCASP_XBUF13 13 + #define MCASP_XBUF14 14 + #define MCASP_XBUF15 15 +#endif /* _MCASP_CHANNEL_CNT == 16 */ + +#define MCASP_RBUF0 0 +#define MCASP_RBUF1 1 +#define MCASP_RBUF2 2 +#define MCASP_RBUF3 3 +/* Fields for _MCASP_CHANNEL_CNT == 4 end here*/ + +#if (_MCASP_CHANNEL_CNT > 4) + #define MCASP_RBUF4 4 + #define MCASP_RBUF5 5 +#endif /* _MCASP_CHANNEL_CNT == 6 */ + +#if (_MCASP_CHANNEL_CNT > 6) + #define MCASP_RBUF6 6 + #define MCASP_RBUF7 7 +#endif /* _MCASP_CHANNEL_CNT == 8 */ + +#if (_MCASP_CHANNEL_CNT == 16) + #define MCASP_RBUF8 8 + #define MCASP_RBUF9 9 + #define MCASP_RBUF10 10 + #define MCASP_RBUF11 11 + #define MCASP_RBUF12 12 + #define MCASP_RBUF13 13 + #define MCASP_RBUF14 14 + #define MCASP_RBUF15 15 +#endif /* _MCASP_CHANNEL_CNT == 16 */ + +/******************************************************************************\ +* global typedef declarations +\******************************************************************************/ + +typedef enum { + MCASP_DSP_INTEGER = 0, + MCASP_DSP_Q31 = 1 +} MCASP_Dsprep; + + +/* device handle object */ +typedef struct { + Uint32 allocated; + Uint32 xmtEventId; + Uint32 rcvEventId; + volatile Uint32 *baseAddr; + Uint32 xbufAddr; + Uint32 xbufAddrCfg; + Uint32 rbufAddr; + Uint32 rbufAddrCfg; + Uint32 ditcsrAddr; + Uint32 ditudrAddr; +} MCASP_Obj, *MCASP_Handle; + +/* device configuration structure */ + +typedef struct { + Uint32 pfunc; + Uint32 pdir; + Uint32 ditctl; + Uint32 dlbctl; + Uint32 amute; +} MCASP_ConfigGbl; + +typedef struct { + Uint32 rmask; + Uint32 rfmt; + Uint32 afsrctl; + Uint32 aclkrctl; + Uint32 ahclkrctl; + Uint32 rtdm; + Uint32 rintctl; + Uint32 rclkchk; +} MCASP_ConfigRcv; + +typedef struct { + Uint32 xmask; + Uint32 xfmt; + Uint32 afsxctl; + Uint32 aclkxctl; + Uint32 ahclkxctl; + Uint32 xtdm; + Uint32 xintctl; + Uint32 xclkchk; +} MCASP_ConfigXmt; + +#if (_MCASP_CHANNEL_CNT == 16) +typedef struct { + Uint32 srctl0; + Uint32 srctl1; + Uint32 srctl2; + Uint32 srctl3; + Uint32 srctl4; + Uint32 srctl5; + Uint32 srctl6; + Uint32 srctl7; + Uint32 srctl8; + Uint32 srctl9; + Uint32 srctl10; + Uint32 srctl11; + Uint32 srctl12; + Uint32 srctl13; + Uint32 srctl14; + Uint32 srctl15; +} MCASP_ConfigSrctl; + +#endif /* _MCASP_CHANNEL_CNT == 16 */ + +#if (_MCASP_CHANNEL_CNT == 8) + +typedef struct { + Uint32 srctl0; + Uint32 srctl1; + Uint32 srctl2; + Uint32 srctl3; + Uint32 srctl4; + Uint32 srctl5; + Uint32 srctl6; + Uint32 srctl7; +} MCASP_ConfigSrctl; + +#endif /* _MCASP_CHANNEL_CNT == 8 */ + +#if (_MCASP_CHANNEL_CNT == 6) +typedef struct { + Uint32 srctl0; + Uint32 srctl1; + Uint32 srctl2; + Uint32 srctl3; + Uint32 srctl4; + Uint32 srctl5; +} MCASP_ConfigSrctl; +#endif /* _MCASP_CHANNEL_CNT == 6 */ + +#if (_MCASP_CHANNEL_CNT == 4) +typedef struct { + Uint32 srctl0; + Uint32 srctl1; + Uint32 srctl2; + Uint32 srctl3; +} MCASP_ConfigSrctl; +#endif /* _MCASP_CHANNEL_CNT == 4 */ + +typedef struct { + MCASP_ConfigGbl *global; + MCASP_ConfigRcv *receive; + MCASP_ConfigXmt *transmit; + MCASP_ConfigSrctl *srctl; +} MCASP_Config; + + +/* Parameter Clock Control : ACLKXCTL - ACLKRCTL */ +typedef struct { + Uint32 syncmode; /* Async 0 /1 : ACLKXCTL */ + Uint32 xclksrc; /* Xmt clock source */ + Uint32 xclkpol; /* Xmt clock polarity */ + Uint32 xclkdiv; /* Xmt clock div */ + Uint32 rclksrc; /* Rcv clock source */ + Uint32 rclkpol; /* Rcv clock polarity */ + Uint32 rclkdiv; /* Rcv clock div */ +}MCASP_SetupClk; + + +/* Parameter High- Freq Clock Control : AHCLKXCTL - AHCLKRCTL */ +typedef struct { + Uint32 xhclksrc; /* Xmt clock source */ + Uint32 xhclkpol; /* Xmt clock polarity */ + Uint32 xhclkdiv; /* Xmt clock div */ + Uint32 rhclksrc; /* Rcv clock source */ + Uint32 rhclkpol; /* Rcv clock polarity */ + Uint32 rhclkdiv; /* Rcv clock div */ +}MCASP_SetupHclk; + + +/* Parameter Frame Sync Control : AFSXCTL - AFSRCTL */ +typedef struct { + Uint32 xmode; /* TDM - BURST : FSXMOD - AFSXCTL reg */ + Uint32 xslotsize; /* slots# for TDM: FSXMOD - AFSXCTL reg */ + Uint32 xfssrc; /* Internal/External AFSXE - AFSXCTL reg */ + Uint32 xfspol; /* Xmt clock polarity FSXPOL - AFSXCTL reg */ + Uint32 fxwid; /* Xmt Frame Duration FXWID - AFSXCTL reg */ + Uint32 rmode; /* TDM - BURST FSRMOD - AFSRCTL reg */ + Uint32 rslotsize; /* slots# for TDM */ + Uint32 rfssrc; /* Rcv Internal/External AFSRE - AFSRCTL reg */ + Uint32 rfspol; /* Rcv clock polarity FSRPOL- AFSRCTL reg */ + Uint32 frwid; /* Rcv Frame Duration FRWID - AFSRCTL reg */ +}MCASP_SetupFsync; + +/* Parameters Data Stream Format: XFMT - RFMT */ +typedef struct { + Uint32 xbusel; /* DAT / CFG bus */ + MCASP_Dsprep xdsprep; /* DSP representation :Q31/Integer */ + Uint32 xslotsize; /* 8-32bits TXSSZ field - XFMT reg */ + Uint32 xwordsize; /* rotation right */ + Uint32 xalign; /* Left/Right Aligned */ + Uint32 xpad; /* Pad value for extra bits */ + Uint32 xpbit; /* which bit to pad the extra bits */ + Uint32 xorder; /* MSB/LSB XRVRS field - XFMT reg */ + Uint32 xdelay; /* Bit delay - XFMT reg */ + Uint32 rbusel; /* DAT / CFG bus */ + MCASP_Dsprep rdsprep; /* DSP representation :Q31/Integer */ + Uint32 rslotsize; /* 8-32bits RXSSZ */ + Uint32 rwordsize; /* rotation right */ + Uint32 ralign; /* Left/Right Aligned */ + Uint32 rpad; /* Pad value for extra bits */ + Uint32 rpbit; /* which bit to pad the extra bits */ + Uint32 rorder; /* MSB/LSB XRVRS field - XFMT reg */ + Uint32 rdelay; /* FSXDLY Bit delay - XFMT reg */ +} MCASP_SetupFormat; + + + + +/******************************************************************************\ +* global variable declarations +\******************************************************************************/ + +/******************************************************************************\ +* global function declarations +\******************************************************************************/ +CSLAPI void MCASP_reset(MCASP_Handle hMcasp); +CSLAPI void MCASP_resetAll(); + +CSLAPI MCASP_Handle MCASP_open(int devNum, Uint32 flags); +CSLAPI void MCASP_close(MCASP_Handle hMcasp); +CSLAPI MCASP_Handle MCASP_getHandle(int devNum); + +CSLAPI Uint32 MCASP_getPins(MCASP_Handle hMcasp); +CSLAPI void MCASP_setPins(MCASP_Handle hMcasp, Uint32 pins); +CSLAPI void MCASP_clearPins(MCASP_Handle hMcasp, Uint32 pins); + +/* direction = (transmitter only) MCASP_XMT - (receiver only) MCASP_RCV - (both) MCASP_RCVXMT */ + +/* active state machine step 8*/ +CSLAPI void MCASP_enableSm(MCASP_Handle hMcasp, Uint32 direction); + +/* enable data serializer step 5*/ +CSLAPI void MCASP_enableSers(MCASP_Handle hMcasp, Uint32 direction); + +/* enable clocks step 4 */ +CSLAPI void MCASP_enableClk(MCASP_Handle hMcasp, Uint32 direction); +CSLAPI void MCASP_enableHclk(MCASP_Handle hMcasp, Uint32 direction); + +/* enable frame sync if receiver with internal frame sync */ +CSLAPI void MCASP_enableFsync(MCASP_Handle hMcasp, Uint32 direction); + + +CSLAPI void MCASP_setupClk(MCASP_Handle hMcasp,MCASP_SetupClk *setupclk, Uint32 direction); +CSLAPI void MCASP_setupHclk(MCASP_Handle hMcasp,MCASP_SetupHclk *setuphclk, Uint32 direction); +CSLAPI void MCASP_setupFsync(MCASP_Handle hMcasp,MCASP_SetupFsync *setupfsync, Uint32 direction); +CSLAPI void MCASP_setupFormat(MCASP_Handle hMcasp,MCASP_SetupFormat *setupFormat, Uint32 direction); + +/* Configuration of DIT mode */ +CSLAPI void MCASP_configDit(MCASP_Handle hMcasp,MCASP_Dsprep dsprep, Uint32 datalen); + +/******************************************************************************\ +* inline function declarations +\******************************************************************************/ +IDECL Uint32 MCASP_getXbufAddrCfg(MCASP_Handle hMcasp, Uint32 xbufNum); +IDECL Uint32 MCASP_getXbufAddr(MCASP_Handle hMcasp); + +IDECL Uint32 MCASP_getRbufAddrCfg(MCASP_Handle hMcasp, Uint32 rbufNum); +IDECL Uint32 MCASP_getRbufAddr(MCASP_Handle hMcasp); + +IDECL Uint32 MCASP_getXmtEventId(MCASP_Handle hMcasp); +IDECL Uint32 MCASP_getRcvEventId(MCASP_Handle hMcasp); + +IDECL Uint32 MCASP_read32Cfg(MCASP_Handle hMcasp, Uint32 rbufNum); +IDECL void MCASP_write32Cfg(MCASP_Handle hMcasp, Uint32 xbufNum, Uint32 val); +/* uses EDMA addresses */ +IDECL Uint32 MCASP_read32(MCASP_Handle hMcasp); +IDECL void MCASP_write32(MCASP_Handle hMcasp,Uint32 val); + +IDECL Uint32 MCASP_rstat(MCASP_Handle hMcasp); + +/******* Not documented ************************/ +IDECL Uint32 MCASP_rovrn(MCASP_Handle hMcasp); +IDECL Uint32 MCASP_rsyncerr(MCASP_Handle hMcasp); +IDECL Uint32 MCASP_rckfail(MCASP_Handle hMcasp); +IDECL Uint32 MCASP_revenslot(MCASP_Handle hMcasp); +IDECL Uint32 MCASP_rlast(MCASP_Handle hMcasp); +IDECL Uint32 MCASP_rdata(MCASP_Handle hMcasp); +IDECL Uint32 MCASP_rstafrm(MCASP_Handle hMcasp); +IDECL Uint32 MCASP_rerr(MCASP_Handle hMcasp); + +IDECL Uint32 MCASP_xstat(MCASP_Handle hMcasp); +/******* Not documented ************************/ +IDECL Uint32 MCASP_xundrn(MCASP_Handle hMcasp); +IDECL Uint32 MCASP_xsyncerr(MCASP_Handle hMcasp); +IDECL Uint32 MCASP_xckfail(MCASP_Handle hMcasp); +IDECL Uint32 MCASP_xevenslot(MCASP_Handle hMcasp); +IDECL Uint32 MCASP_xlast(MCASP_Handle hMcasp); +IDECL Uint32 MCASP_xdata(MCASP_Handle hMcasp); +IDECL Uint32 MCASP_xstafrm(MCASP_Handle hMcasp); +IDECL Uint32 MCASP_xerr(MCASP_Handle hMcasp); + +IDECL Uint32 MCASP_getRslotcnt(MCASP_Handle hMcasp); +IDECL Uint32 MCASP_getXslotcnt(MCASP_Handle hMcasp); +IDECL Uint32 MCASP_getRclkcnt(MCASP_Handle hMcasp); +IDECL Uint32 MCASP_getXclkcnt(MCASP_Handle hMcasp); +IDECL Uint32 MCASP_getMutin(MCASP_Handle hMcasp); + +/*****************************************************/ +IDECL void MCASP_clearRcvStat(MCASP_Handle hMcasp,Uint32 fieldnum); +IDECL void MCASP_clearXmtStat(MCASP_Handle hMcasp,Uint32 fieldnum); + +IDECL Uint32 MCASP_getChanStatusAddr(MCASP_Handle hMcasp, Uint32 chSide, Uint32 chNum); +IDECL Uint32 MCASP_getUserDataAddr(MCASP_Handle hMcasp, Uint32 chSide, Uint32 chNum); + +IDECL void MCASP_config(MCASP_Handle hMcasp, MCASP_Config *config); +IDECL void MCASP_configGbl(MCASP_Handle hMcasp, MCASP_ConfigGbl *config); +IDECL void MCASP_configRcv(MCASP_Handle hMcasp, MCASP_ConfigRcv *config); +IDECL void MCASP_configXmt(MCASP_Handle hMcasp, MCASP_ConfigXmt *config); +IDECL void MCASP_configSrctl(MCASP_Handle hMcasp, MCASP_ConfigSrctl *config); + +/************** Not documented ****************************************/ + +#if (_MCASP_CHANNEL_CNT == 16) +IDECL void MCASP_configArgs(MCASP_Handle hMcasp, Uint32 pfunc, Uint32 pdir, + Uint32 amute, Uint32 dlbctl, Uint32 ditctl, Uint32 rmask, Uint32 rfmt, Uint32 afsrctl, + Uint32 aclkrctl, Uint32 ahclkrctl, Uint32 rtdm, Uint32 rintctl, Uint32 rclkchk, + Uint32 xmask, Uint32 xfmt, Uint32 afsxctl, Uint32 aclkxctl, Uint32 ahclkxctl, Uint32 xtdm, + Uint32 xintctl, Uint32 xclkchk, Uint32 srctl0, Uint32 srctl1, Uint32 srctl2, Uint32 srctl3, + Uint32 srctl4, Uint32 srctl5, Uint32 srctl6, Uint32 srctl7, Uint32 srctl8, Uint32 srctl9, + Uint32 srctl10, Uint32 srctl11, Uint32 srctl12, Uint32 srctl13, Uint32 srctl14, Uint32 srctl15 ); + +#endif /* _MCASP_CHANNEL_CNT == 16 */ + +#if (_MCASP_CHANNEL_CNT == 8) +IDECL void MCASP_configArgs(MCASP_Handle hMcasp, Uint32 pfunc, Uint32 pdir, + Uint32 amute, Uint32 dlbctl, Uint32 ditctl, Uint32 rmask, Uint32 rfmt, Uint32 afsrctl, + Uint32 aclkrctl, Uint32 ahclkrctl, Uint32 rtdm, Uint32 rintctl, Uint32 rclkchk, + Uint32 xmask, Uint32 xfmt, Uint32 afsxctl, Uint32 aclkxctl, Uint32 ahclkxctl, Uint32 xtdm, + Uint32 xintctl, Uint32 xclkchk, Uint32 srctl0, Uint32 srctl1, Uint32 srctl2, Uint32 srctl3, + Uint32 srctl4, Uint32 srctl5, Uint32 srctl6, Uint32 srctl7); +#endif /* _MCASP_CHANNEL_CNT == 8 */ + +#if (_MCASP_CHANNEL_CNT == 6) +IDECL void MCASP_configArgs(MCASP_Handle hMcasp, Uint32 pfunc, Uint32 pdir, + Uint32 amute, Uint32 dlbctl, Uint32 ditctl, Uint32 rmask, Uint32 rfmt, Uint32 afsrctl, + Uint32 aclkrctl, Uint32 ahclkrctl, Uint32 rtdm, Uint32 rintctl, Uint32 rclkchk, + Uint32 xmask, Uint32 xfmt, Uint32 afsxctl, Uint32 aclkxctl, Uint32 ahclkxctl, Uint32 xtdm, + Uint32 xintctl, Uint32 xclkchk, Uint32 srctl0, Uint32 srctl1, Uint32 srctl2, Uint32 srctl3, + Uint32 srctl4, Uint32 srctl5); +#endif /* _MCASP_CHANNEL_CNT == 6 */ + +#if (_MCASP_CHANNEL_CNT == 4) +IDECL void MCASP_configArgs(MCASP_Handle hMcasp, Uint32 pfunc, Uint32 pdir, + Uint32 amute, Uint32 dlbctl, Uint32 ditctl, Uint32 rmask, Uint32 rfmt, Uint32 afsrctl, + Uint32 aclkrctl, Uint32 ahclkrctl, Uint32 rtdm, Uint32 rintctl, Uint32 rclkchk, + Uint32 xmask, Uint32 xfmt, Uint32 afsxctl, Uint32 aclkxctl, Uint32 ahclkxctl, Uint32 xtdm, + Uint32 xintctl, Uint32 xclkchk, Uint32 srctl0, Uint32 srctl1, Uint32 srctl2, Uint32 srctl3); +#endif /* _MCASP_CHANNEL_CNT == 4 */ + +/**********************************************************************/ + +IDECL void MCASP_getConfig(MCASP_Handle hMcasp, MCASP_Config *config); + +IDECL void MCASP_resetXmt(MCASP_Handle hMcasp); +IDECL void MCASP_resetRcv(MCASP_Handle hMcasp); + +/** read GBLCTL register with the right value **/ +IDECL Uint32 MCASP_getGblctl(MCASP_Handle hMcasp, Uint32 direction); + + +/******************************************************************************\ +* inline function definitions +\******************************************************************************/ +#ifdef USEDEFS +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCASP_getXbufAddr(MCASP_Handle hMcasp) { + return (Uint32)(hMcasp->xbufAddr); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCASP_getXbufAddrCfg(MCASP_Handle hMcasp, Uint32 xbufNum) { + return (Uint32)(hMcasp->xbufAddrCfg + (xbufNum*MCASP_XBUF_BUFSIZE)); +} + +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCASP_getRbufAddr(MCASP_Handle hMcasp) { + return (Uint32)(hMcasp->rbufAddr); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCASP_getRbufAddrCfg(MCASP_Handle hMcasp, Uint32 rbufNum) { + return (Uint32)(hMcasp->rbufAddrCfg + (rbufNum*MCASP_RBUF_BUFSIZE)); +} + +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCASP_getGblctl(MCASP_Handle hMcasp,Uint32 direction) { + if (direction == MCASP_XMT) { + return (MCASP_RGETH(hMcasp,XGBLCTL)& 0x0001F00); + } else { + if (direction == MCASP_RCV) { + return (MCASP_RGETH(hMcasp,RGBLCTL)& 0x000001F); + } else { + return (MCASP_RGETH(hMcasp,GBLCTL)); + } + } +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCASP_getXmtEventId(MCASP_Handle hMcasp) { + return (hMcasp->xmtEventId); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCASP_getRcvEventId(MCASP_Handle hMcasp) { + return (hMcasp->rcvEventId); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCASP_read32Cfg(MCASP_Handle hMcasp, Uint32 rbufNum) { + return (*(volatile Uint32 *)(hMcasp->rbufAddrCfg + (rbufNum*MCASP_RBUF_BUFSIZE))); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCASP_read32(MCASP_Handle hMcasp) { + return (*(volatile Uint32 *)(hMcasp->rbufAddr)); +} +/*----------------------------------------------------------------------------*/ +IDEF void MCASP_write32Cfg(MCASP_Handle hMcasp, Uint32 xbufNum, Uint32 val) { + (*(volatile Uint32 *)(hMcasp->xbufAddrCfg + (xbufNum*MCASP_XBUF_BUFSIZE))) = val; +} +/*----------------------------------------------------------------------------*/ +IDEF void MCASP_write32(MCASP_Handle hMcasp, Uint32 val) { + (*(volatile Uint32 *)(hMcasp->xbufAddr)) = val; +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCASP_rstat(MCASP_Handle hMcasp) { + return MCASP_RGETH(hMcasp,RSTAT); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCASP_rovrn(MCASP_Handle hMcasp) { + return MCASP_FGETH(hMcasp,RSTAT,ROVRN); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCASP_rsyncerr(MCASP_Handle hMcasp) { + return MCASP_FGETH(hMcasp,RSTAT,RSYNCERR); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCASP_rckfail(MCASP_Handle hMcasp) { + return MCASP_FGETH(hMcasp,RSTAT,RCKFAIL); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCASP_revenslot(MCASP_Handle hMcasp) { + return MCASP_FGETH(hMcasp,RSTAT,RTDMSLOT); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCASP_rlast(MCASP_Handle hMcasp) { + return MCASP_FGETH(hMcasp,RSTAT,RLAST); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCASP_rdata(MCASP_Handle hMcasp) { + return MCASP_FGETH(hMcasp,RSTAT,RDATA); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCASP_rstafrm(MCASP_Handle hMcasp) { + return MCASP_FGETH(hMcasp,RSTAT,RSTAFRM); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCASP_rerr(MCASP_Handle hMcasp) { + return MCASP_FGETH(hMcasp,RSTAT,RERR); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCASP_xstat(MCASP_Handle hMcasp) { + return MCASP_RGETH(hMcasp,XSTAT); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCASP_xundrn(MCASP_Handle hMcasp) { + return MCASP_FGETH(hMcasp,XSTAT,XUNDRN); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCASP_xsyncerr(MCASP_Handle hMcasp) { + return MCASP_FGETH(hMcasp,XSTAT,XSYNCERR); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCASP_xckfail(MCASP_Handle hMcasp) { + return MCASP_FGETH(hMcasp,XSTAT,XCKFAIL); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCASP_xevenslot(MCASP_Handle hMcasp) { + return MCASP_FGETH(hMcasp,XSTAT,XTDMSLOT); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCASP_xlast(MCASP_Handle hMcasp) { + return MCASP_FGETH(hMcasp,XSTAT,XLAST); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCASP_xdata(MCASP_Handle hMcasp) { + return MCASP_FGETH(hMcasp,XSTAT,XDATA); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCASP_xstafrm(MCASP_Handle hMcasp) { + return MCASP_FGETH(hMcasp,XSTAT,XSTAFRM); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCASP_xerr(MCASP_Handle hMcasp) { + return MCASP_FGETH(hMcasp,XSTAT,XERR); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCASP_getRslotcnt(MCASP_Handle hMcasp) { + return MCASP_FGETH(hMcasp,RSLOT,RSLOTCNT); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCASP_getXslotcnt(MCASP_Handle hMcasp) { + return MCASP_FGETH(hMcasp,XSLOT,XSLOTCNT); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCASP_getRclkcnt(MCASP_Handle hMcasp) { + return MCASP_FGETH(hMcasp,RCLKCHK,RCNT); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCASP_getXclkcnt(MCASP_Handle hMcasp) { + return MCASP_FGETH(hMcasp,XCLKCHK,XCNT); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCASP_getMutin(MCASP_Handle hMcasp) { + return MCASP_FGETH(hMcasp,AMUTE,INSTAT); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCASP_getChanStatusAddr(MCASP_Handle hMcasp, Uint32 chSide, Uint32 chNum) { + return (Uint32)(hMcasp->ditcsrAddr + (chSide*MCASP_DITCSR_RIGHT_OFFSET)+ + (chNum*MCASP_DITCSR_BUFSIZE)); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCASP_getUserDataAddr(MCASP_Handle hMcasp, Uint32 chSide, Uint32 chNum) { + return (Uint32)(hMcasp->ditudrAddr + (chSide*MCASP_DITUDR_RIGHT_OFFSET)+ + (chNum*MCASP_DITUDR_BUFSIZE)); +} +/*----------------------------------------------------------------------------*/ +IDEF void MCASP_clearXmtStat(MCASP_Handle hMcasp, Uint32 fieldnum){ + MCASP_RSETH(hMcasp,XSTAT,1<baseAddr); + register int x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17,x18,x19; + register int x20,x21,x22,x23,x24,x25,x26,x27,x28,x29,x30,x31,x32,x33,x34,x35,x36; + + gie = IRQ_globalDisable(); + + /* the compiler generates more efficient code if the loads */ + /* and stores are grouped together rather than intermixed */ + x0 = config->global->pfunc; + x1 = config->global->pdir; + x2 = config->global->amute; + x3 = config->global->dlbctl; + x4 = config->global->ditctl; + x5 = config->receive->rmask; + x6 = config->receive->rfmt; + x7 = config->receive->afsrctl; + x8 = config->receive->aclkrctl; + x9 = config->receive->ahclkrctl; + x10 = config->receive->rtdm; + x11 = config->receive->rintctl; + x12 = config->receive->rclkchk; + x13 = config->transmit->xmask; + x14 = config->transmit->xfmt; + x15 = config->transmit->afsxctl; + x16 = config->transmit->aclkxctl; + x17 = config->transmit->ahclkxctl; + x18 = config->transmit->xtdm; + x19 = config->transmit->xintctl; + x20 = config->transmit->xclkchk; + x21 = config->srctl->srctl0; + x22 = config->srctl->srctl1; + x23 = config->srctl->srctl2; + x24 = config->srctl->srctl3; + x25 = config->srctl->srctl4; + x26 = config->srctl->srctl5; + x27 = config->srctl->srctl6; + x28 = config->srctl->srctl7; + x29 = config->srctl->srctl8; + x30 = config->srctl->srctl9; + x31 = config->srctl->srctl10; + x32 = config->srctl->srctl11; + x33 = config->srctl->srctl12; + x34 = config->srctl->srctl13; + x35 = config->srctl->srctl14; + x36 = config->srctl->srctl15; + + base[_MCASP_RMASK_OFFSET] = x5; + base[_MCASP_RFMT_OFFSET] = x6; + base[_MCASP_AFSRCTL_OFFSET] = x7; + base[_MCASP_ACLKRCTL_OFFSET]= x8; + base[_MCASP_AHCLKRCTL_OFFSET]= x9; + base[_MCASP_RTDM_OFFSET] = x10; + base[_MCASP_RINTCTL_OFFSET] = x11; + base[_MCASP_RCLKCHK_OFFSET] = x12; + base[_MCASP_XMASK_OFFSET] = x13; + base[_MCASP_XFMT_OFFSET] = x14; + base[_MCASP_AFSXCTL_OFFSET] = x15; + base[_MCASP_ACLKXCTL_OFFSET]= x16; + base[_MCASP_AHCLKXCTL_OFFSET]= x17; + base[_MCASP_XTDM_OFFSET] = x18; + base[_MCASP_XINTCTL_OFFSET] = x19; + base[_MCASP_XCLKCHK_OFFSET] = x20; + base[_MCASP_SRCTL0_OFFSET] = x21; + base[_MCASP_SRCTL1_OFFSET] = x22; + base[_MCASP_SRCTL2_OFFSET] = x23; + base[_MCASP_SRCTL3_OFFSET] = x24; + base[_MCASP_SRCTL4_OFFSET] = x25; + base[_MCASP_SRCTL5_OFFSET] = x26; + base[_MCASP_SRCTL6_OFFSET] = x27; + base[_MCASP_SRCTL7_OFFSET] = x28; + base[_MCASP_SRCTL8_OFFSET] = x29; + base[_MCASP_SRCTL9_OFFSET] = x30; + base[_MCASP_SRCTL10_OFFSET] = x31; + base[_MCASP_SRCTL11_OFFSET] = x32; + base[_MCASP_SRCTL12_OFFSET] = x33; + base[_MCASP_SRCTL13_OFFSET] = x34; + base[_MCASP_SRCTL14_OFFSET] = x35; + base[_MCASP_SRCTL15_OFFSET] = x36; + base[_MCASP_AMUTE_OFFSET] = x2; + base[_MCASP_DLBCTL_OFFSET] = x3; + base[_MCASP_DITCTL_OFFSET] = x4; + base[_MCASP_PFUNC_OFFSET] = x0; + base[_MCASP_PDIR_OFFSET] = x1; + + IRQ_globalRestore(gie); +} + +#endif /* _MCASP_CHANNEL_CNT == 16 */ + +#if (_MCASP_CHANNEL_CNT == 8) +IDEF void MCASP_config(MCASP_Handle hMcasp, MCASP_Config *config) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)(hMcasp->baseAddr); + register int x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17,x18,x19; + register int x20,x21,x22,x23,x24,x25,x26,x27,x28; + + gie = IRQ_globalDisable(); + + /* the compiler generates more efficient code if the loads */ + /* and stores are grouped together rather than intermixed */ + x0 = config->global->pfunc; + x1 = config->global->pdir; + x2 = config->global->amute; + x3 = config->global->dlbctl; + x4 = config->global->ditctl; + x5 = config->receive->rmask; + x6 = config->receive->rfmt; + x7 = config->receive->afsrctl; + x8 = config->receive->aclkrctl; + x9 = config->receive->ahclkrctl; + x10 = config->receive->rtdm; + x11 = config->receive->rintctl; + x12 = config->receive->rclkchk; + x13 = config->transmit->xmask; + x14 = config->transmit->xfmt; + x15 = config->transmit->afsxctl; + x16 = config->transmit->aclkxctl; + x17 = config->transmit->ahclkxctl; + x18 = config->transmit->xtdm; + x19 = config->transmit->xintctl; + x20 = config->transmit->xclkchk; + x21 = config->srctl->srctl0; + x22 = config->srctl->srctl1; + x23 = config->srctl->srctl2; + x24 = config->srctl->srctl3; + x25 = config->srctl->srctl4; + x26 = config->srctl->srctl5; + x27 = config->srctl->srctl6; + x28 = config->srctl->srctl7; + + base[_MCASP_RMASK_OFFSET] = x5; + base[_MCASP_RFMT_OFFSET] = x6; + base[_MCASP_AFSRCTL_OFFSET] = x7; + base[_MCASP_ACLKRCTL_OFFSET]= x8; + base[_MCASP_AHCLKRCTL_OFFSET]= x9; + base[_MCASP_RTDM_OFFSET] = x10; + base[_MCASP_RINTCTL_OFFSET] = x11; + base[_MCASP_RCLKCHK_OFFSET] = x12; + base[_MCASP_XMASK_OFFSET] = x13; + base[_MCASP_XFMT_OFFSET] = x14; + base[_MCASP_AFSXCTL_OFFSET] = x15; + base[_MCASP_ACLKXCTL_OFFSET]= x16; + base[_MCASP_AHCLKXCTL_OFFSET]= x17; + base[_MCASP_XTDM_OFFSET] = x18; + base[_MCASP_XINTCTL_OFFSET] = x19; + base[_MCASP_XCLKCHK_OFFSET] = x20; + base[_MCASP_SRCTL0_OFFSET] = x21; + base[_MCASP_SRCTL1_OFFSET] = x22; + base[_MCASP_SRCTL2_OFFSET] = x23; + base[_MCASP_SRCTL3_OFFSET] = x24; + base[_MCASP_SRCTL4_OFFSET] = x25; + base[_MCASP_SRCTL5_OFFSET] = x26; + base[_MCASP_SRCTL6_OFFSET] = x27; + base[_MCASP_SRCTL7_OFFSET] = x28; + base[_MCASP_AMUTE_OFFSET] = x2; + base[_MCASP_DLBCTL_OFFSET] = x3; + base[_MCASP_DITCTL_OFFSET] = x4; + base[_MCASP_PFUNC_OFFSET] = x0; + base[_MCASP_PDIR_OFFSET] = x1; + + IRQ_globalRestore(gie); +} +#endif /* _MCASP_CHANNEL_CNT == 8 */ + +#if (_MCASP_CHANNEL_CNT == 6) +IDEF void MCASP_config(MCASP_Handle hMcasp, MCASP_Config *config) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)(hMcasp->baseAddr); + register int x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17,x18,x19; + register int x20,x21,x22,x23,x24,x25,x26; + + gie = IRQ_globalDisable(); + + /* the compiler generates more efficient code if the loads */ + /* and stores are grouped together rather than intermixed */ + x0 = config->global->pfunc; + x1 = config->global->pdir; + x2 = config->global->amute; + x3 = config->global->dlbctl; + x4 = config->global->ditctl; + x5 = config->receive->rmask; + x6 = config->receive->rfmt; + x7 = config->receive->afsrctl; + x8 = config->receive->aclkrctl; + x9 = config->receive->ahclkrctl; + x10 = config->receive->rtdm; + x11 = config->receive->rintctl; + x12 = config->receive->rclkchk; + x13 = config->transmit->xmask; + x14 = config->transmit->xfmt; + x15 = config->transmit->afsxctl; + x16 = config->transmit->aclkxctl; + x17 = config->transmit->ahclkxctl; + x18 = config->transmit->xtdm; + x19 = config->transmit->xintctl; + x20 = config->transmit->xclkchk; + x21 = config->srctl->srctl0; + x22 = config->srctl->srctl1; + x23 = config->srctl->srctl2; + x24 = config->srctl->srctl3; + x25 = config->srctl->srctl4; + x26 = config->srctl->srctl5; + + base[_MCASP_RMASK_OFFSET] = x5; + base[_MCASP_RFMT_OFFSET] = x6; + base[_MCASP_AFSRCTL_OFFSET] = x7; + base[_MCASP_ACLKRCTL_OFFSET]= x8; + base[_MCASP_AHCLKRCTL_OFFSET]= x9; + base[_MCASP_RTDM_OFFSET] = x10; + base[_MCASP_RINTCTL_OFFSET] = x11; + base[_MCASP_RCLKCHK_OFFSET] = x12; + base[_MCASP_XMASK_OFFSET] = x13; + base[_MCASP_XFMT_OFFSET] = x14; + base[_MCASP_AFSXCTL_OFFSET] = x15; + base[_MCASP_ACLKXCTL_OFFSET]= x16; + base[_MCASP_AHCLKXCTL_OFFSET]= x17; + base[_MCASP_XTDM_OFFSET] = x18; + base[_MCASP_XINTCTL_OFFSET] = x19; + base[_MCASP_XCLKCHK_OFFSET] = x20; + base[_MCASP_SRCTL0_OFFSET] = x21; + base[_MCASP_SRCTL1_OFFSET] = x22; + base[_MCASP_SRCTL2_OFFSET] = x23; + base[_MCASP_SRCTL3_OFFSET] = x24; + base[_MCASP_SRCTL4_OFFSET] = x25; + base[_MCASP_SRCTL5_OFFSET] = x26; + base[_MCASP_AMUTE_OFFSET] = x2; + base[_MCASP_DLBCTL_OFFSET] = x3; + base[_MCASP_DITCTL_OFFSET] = x4; + base[_MCASP_PFUNC_OFFSET] = x0; + base[_MCASP_PDIR_OFFSET] = x1; + + IRQ_globalRestore(gie); +} +#endif /* _MCASP_CHANNEL_CNT == 6 */ + +#if (_MCASP_CHANNEL_CNT == 4) +IDEF void MCASP_config(MCASP_Handle hMcasp, MCASP_Config *config) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)(hMcasp->baseAddr); + register int x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17,x18,x19; + register int x20,x21,x22,x23,x24; + + gie = IRQ_globalDisable(); + + /* the compiler generates more efficient code if the loads */ + /* and stores are grouped together rather than intermixed */ + x0 = config->global->pfunc; + x1 = config->global->pdir; + x2 = config->global->amute; + x3 = config->global->dlbctl; + x4 = config->global->ditctl; + x5 = config->receive->rmask; + x6 = config->receive->rfmt; + x7 = config->receive->afsrctl; + x8 = config->receive->aclkrctl; + x9 = config->receive->ahclkrctl; + x10 = config->receive->rtdm; + x11 = config->receive->rintctl; + x12 = config->receive->rclkchk; + x13 = config->transmit->xmask; + x14 = config->transmit->xfmt; + x15 = config->transmit->afsxctl; + x16 = config->transmit->aclkxctl; + x17 = config->transmit->ahclkxctl; + x18 = config->transmit->xtdm; + x19 = config->transmit->xintctl; + x20 = config->transmit->xclkchk; + x21 = config->srctl->srctl0; + x22 = config->srctl->srctl1; + x23 = config->srctl->srctl2; + x24 = config->srctl->srctl3; + + base[_MCASP_RMASK_OFFSET] = x5; + base[_MCASP_RFMT_OFFSET] = x6; + base[_MCASP_AFSRCTL_OFFSET] = x7; + base[_MCASP_ACLKRCTL_OFFSET]= x8; + base[_MCASP_AHCLKRCTL_OFFSET]= x9; + base[_MCASP_RTDM_OFFSET] = x10; + base[_MCASP_RINTCTL_OFFSET] = x11; + base[_MCASP_RCLKCHK_OFFSET] = x12; + base[_MCASP_XMASK_OFFSET] = x13; + base[_MCASP_XFMT_OFFSET] = x14; + base[_MCASP_AFSXCTL_OFFSET] = x15; + base[_MCASP_ACLKXCTL_OFFSET]= x16; + base[_MCASP_AHCLKXCTL_OFFSET]= x17; + base[_MCASP_XTDM_OFFSET] = x18; + base[_MCASP_XINTCTL_OFFSET] = x19; + base[_MCASP_XCLKCHK_OFFSET] = x20; + base[_MCASP_SRCTL0_OFFSET] = x21; + base[_MCASP_SRCTL1_OFFSET] = x22; + base[_MCASP_SRCTL2_OFFSET] = x23; + base[_MCASP_SRCTL3_OFFSET] = x24; + base[_MCASP_AMUTE_OFFSET] = x2; + base[_MCASP_DLBCTL_OFFSET] = x3; + base[_MCASP_DITCTL_OFFSET] = x4; + base[_MCASP_PFUNC_OFFSET] = x0; + base[_MCASP_PDIR_OFFSET] = x1; + + IRQ_globalRestore(gie); +} +#endif /* _MCASP_CHANNEL_CNT == 4 */ + + +/*----------------------------------------------------------------------------*/ +IDEF void MCASP_configGbl(MCASP_Handle hMcasp, MCASP_ConfigGbl *config) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)(hMcasp->baseAddr); + register int x0,x1,x2,x3,x4; + + gie = IRQ_globalDisable(); + + /* the compiler generates more efficient code if the loads */ + /* and stores are grouped together rather than intermixed */ + x0 = config->pfunc; + x1 = config->pdir; + x2 = config->amute; + x3 = config->dlbctl; + x4 = config->ditctl; + + base[_MCASP_PFUNC_OFFSET] = x0; + base[_MCASP_AMUTE_OFFSET] = x2; + base[_MCASP_DLBCTL_OFFSET] = x3; + base[_MCASP_DITCTL_OFFSET] = x4; + base[_MCASP_PDIR_OFFSET] = x1; + + IRQ_globalRestore(gie); +} +/*----------------------------------------------------------------------------*/ +IDEF void MCASP_configRcv(MCASP_Handle hMcasp, MCASP_ConfigRcv *config) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)(hMcasp->baseAddr); + register int x5,x6,x7,x8,x9,x10,x11,x12; + + gie = IRQ_globalDisable(); + + /* the compiler generates more efficient code if the loads */ + /* and stores are grouped together rather than intermixed */ + x5 = config->rmask; + x6 = config->rfmt; + x7 = config->afsrctl; + x8 = config->aclkrctl; + x9 = config->ahclkrctl; + x10 = config->rtdm; + x11 = config->rintctl; + x12 = config->rclkchk; + + base[_MCASP_RMASK_OFFSET] = x5; + base[_MCASP_RFMT_OFFSET] = x6; + base[_MCASP_AFSRCTL_OFFSET] = x7; + base[_MCASP_ACLKRCTL_OFFSET]= x8; + base[_MCASP_AHCLKRCTL_OFFSET]= x9; + base[_MCASP_RTDM_OFFSET] = x10; + base[_MCASP_RINTCTL_OFFSET] = x11; + base[_MCASP_RCLKCHK_OFFSET] = x12; + + IRQ_globalRestore(gie); +} +/*----------------------------------------------------------------------------*/ +IDEF void MCASP_configXmt(MCASP_Handle hMcasp, MCASP_ConfigXmt *config) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)(hMcasp->baseAddr); + register int x13,x14,x15,x16,x17,x18,x19,x20; + + gie = IRQ_globalDisable(); + + /* the compiler generates more efficient code if the loads */ + /* and stores are grouped together rather than intermixed */ + x13 = config->xmask; + x14 = config->xfmt; + x15 = config->afsxctl; + x16 = config->aclkxctl; + x17 = config->ahclkxctl; + x18 = config->xtdm; + x19 = config->xintctl; + x20 = config->xclkchk; + + base[_MCASP_XMASK_OFFSET] = x13; + base[_MCASP_XFMT_OFFSET] = x14; + base[_MCASP_AFSXCTL_OFFSET] = x15; + base[_MCASP_ACLKXCTL_OFFSET]= x16; + base[_MCASP_AHCLKXCTL_OFFSET]= x17; + base[_MCASP_XTDM_OFFSET] = x18; + base[_MCASP_XINTCTL_OFFSET] = x19; + base[_MCASP_XCLKCHK_OFFSET] = x20; + + IRQ_globalRestore(gie); +} +/*----------------------------------------------------------------------------*/ +#if (_MCASP_CHANNEL_CNT == 16) +IDEF void MCASP_configSrctl(MCASP_Handle hMcasp, MCASP_ConfigSrctl *config) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)(hMcasp->baseAddr); + register int x21,x22,x23,x24,x25,x26,x27,x28,x29,x30,x31,x32,x33,x34,x35,x36; + + gie = IRQ_globalDisable(); + + /* the compiler generates more efficient code if the loads */ + /* and stores are grouped together rather than intermixed */ + x21 = config->srctl0; + x22 = config->srctl1; + x23 = config->srctl2; + x24 = config->srctl3; + x25 = config->srctl4; + x26 = config->srctl5; + x27 = config->srctl6; + x28 = config->srctl7; + x29 = config->srctl8; + x30 = config->srctl9; + x31 = config->srctl10; + x32 = config->srctl11; + x33 = config->srctl12; + x34 = config->srctl13; + x35 = config->srctl14; + x36 = config->srctl15; + + base[_MCASP_SRCTL0_OFFSET] = x21; + base[_MCASP_SRCTL1_OFFSET] = x22; + base[_MCASP_SRCTL2_OFFSET] = x23; + base[_MCASP_SRCTL3_OFFSET] = x24; + base[_MCASP_SRCTL4_OFFSET] = x25; + base[_MCASP_SRCTL5_OFFSET] = x26; + base[_MCASP_SRCTL6_OFFSET] = x27; + base[_MCASP_SRCTL7_OFFSET] = x28; + base[_MCASP_SRCTL8_OFFSET] = x29; + base[_MCASP_SRCTL9_OFFSET] = x30; + base[_MCASP_SRCTL10_OFFSET] = x31; + base[_MCASP_SRCTL11_OFFSET] = x32; + base[_MCASP_SRCTL12_OFFSET] = x33; + base[_MCASP_SRCTL13_OFFSET] = x34; + base[_MCASP_SRCTL14_OFFSET] = x35; + base[_MCASP_SRCTL15_OFFSET] = x36; + + IRQ_globalRestore(gie); +} +#endif /* _MCASP_CHANNEL_CNT == 16 */ + +#if (_MCASP_CHANNEL_CNT == 8) +IDEF void MCASP_configSrctl(MCASP_Handle hMcasp, MCASP_ConfigSrctl *config) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)(hMcasp->baseAddr); + register int x21,x22,x23,x24,x25,x26,x27,x28; + + gie = IRQ_globalDisable(); + + /* the compiler generates more efficient code if the loads */ + /* and stores are grouped together rather than intermixed */ + x21 = config->srctl0; + x22 = config->srctl1; + x23 = config->srctl2; + x24 = config->srctl3; + x25 = config->srctl4; + x26 = config->srctl5; + x27 = config->srctl6; + x28 = config->srctl7; + + base[_MCASP_SRCTL0_OFFSET] = x21; + base[_MCASP_SRCTL1_OFFSET] = x22; + base[_MCASP_SRCTL2_OFFSET] = x23; + base[_MCASP_SRCTL3_OFFSET] = x24; + base[_MCASP_SRCTL4_OFFSET] = x25; + base[_MCASP_SRCTL5_OFFSET] = x26; + base[_MCASP_SRCTL6_OFFSET] = x27; + base[_MCASP_SRCTL7_OFFSET] = x28; + + IRQ_globalRestore(gie); +} +#endif /* _MCASP_CHANNEL_CNT == 8 */ + +#if (_MCASP_CHANNEL_CNT == 6) +IDEF void MCASP_configSrctl(MCASP_Handle hMcasp, MCASP_ConfigSrctl *config) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)(hMcasp->baseAddr); + register int x21,x22,x23,x24,x25,x26; + + gie = IRQ_globalDisable(); + + /* the compiler generates more efficient code if the loads */ + /* and stores are grouped together rather than intermixed */ + x21 = config->srctl0; + x22 = config->srctl1; + x23 = config->srctl2; + x24 = config->srctl3; + x25 = config->srctl4; + x26 = config->srctl5; + + base[_MCASP_SRCTL0_OFFSET] = x21; + base[_MCASP_SRCTL1_OFFSET] = x22; + base[_MCASP_SRCTL2_OFFSET] = x23; + base[_MCASP_SRCTL3_OFFSET] = x24; + base[_MCASP_SRCTL4_OFFSET] = x25; + base[_MCASP_SRCTL5_OFFSET] = x26; + + IRQ_globalRestore(gie); +} +#endif /* _MCASP_CHANNEL_CNT == 6 */ + +#if (_MCASP_CHANNEL_CNT == 4) +IDEF void MCASP_configSrctl(MCASP_Handle hMcasp, MCASP_ConfigSrctl *config) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)(hMcasp->baseAddr); + register int x21,x22,x23,x24; + + gie = IRQ_globalDisable(); + + /* the compiler generates more efficient code if the loads */ + /* and stores are grouped together rather than intermixed */ + x21 = config->srctl0; + x22 = config->srctl1; + x23 = config->srctl2; + x24 = config->srctl3; + + base[_MCASP_SRCTL0_OFFSET] = x21; + base[_MCASP_SRCTL1_OFFSET] = x22; + base[_MCASP_SRCTL2_OFFSET] = x23; + base[_MCASP_SRCTL3_OFFSET] = x24; + + IRQ_globalRestore(gie); +} +#endif /* _MCASP_CHANNEL_CNT == 4 */ + +/*----------------------------------------------------------------------------*/ +#if (_MCASP_CHANNEL_CNT == 16) +IDEF void MCASP_configArgs(MCASP_Handle hMcasp, Uint32 pfunc, Uint32 pdir, + Uint32 amute, Uint32 dlbctl, Uint32 ditctl, Uint32 rmask, Uint32 rfmt, Uint32 afsrctl, + Uint32 aclkrctl, Uint32 ahclkrctl, Uint32 rtdm, Uint32 rintctl, Uint32 rclkchk, + Uint32 xmask, Uint32 xfmt, Uint32 afsxctl, Uint32 aclkxctl, Uint32 ahclkxctl, Uint32 xtdm, + Uint32 xintctl, Uint32 xclkchk, Uint32 srctl0, Uint32 srctl1, Uint32 srctl2, Uint32 srctl3, + Uint32 srctl4, Uint32 srctl5, Uint32 srctl6, Uint32 srctl7, Uint32 srctl8, Uint32 srctl9, + Uint32 srctl10, Uint32 srctl11, Uint32 srctl12, Uint32 srctl13, Uint32 srctl14, Uint32 srctl15 ) +{ + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)(hMcasp->baseAddr); + + gie = IRQ_globalDisable(); + + base[_MCASP_RMASK_OFFSET] = rmask; + base[_MCASP_RFMT_OFFSET] = rfmt; + base[_MCASP_AFSRCTL_OFFSET] = afsrctl; + base[_MCASP_ACLKRCTL_OFFSET]= aclkrctl; + base[_MCASP_AHCLKRCTL_OFFSET]=ahclkrctl; + base[_MCASP_RTDM_OFFSET] = rtdm; + base[_MCASP_RINTCTL_OFFSET] = rintctl; + base[_MCASP_RCLKCHK_OFFSET] = rclkchk; + base[_MCASP_XMASK_OFFSET] = xmask; + base[_MCASP_XFMT_OFFSET] = xfmt; + base[_MCASP_AFSXCTL_OFFSET] = afsxctl; + base[_MCASP_ACLKXCTL_OFFSET]= aclkxctl; + base[_MCASP_AHCLKXCTL_OFFSET]=ahclkxctl; + base[_MCASP_XTDM_OFFSET] = xtdm; + base[_MCASP_XINTCTL_OFFSET] = xintctl; + base[_MCASP_XCLKCHK_OFFSET] = xclkchk; + base[_MCASP_SRCTL0_OFFSET] = srctl0; + base[_MCASP_SRCTL1_OFFSET] = srctl1; + base[_MCASP_SRCTL2_OFFSET] = srctl2; + base[_MCASP_SRCTL3_OFFSET] = srctl3; + base[_MCASP_SRCTL4_OFFSET] = srctl4; + base[_MCASP_SRCTL5_OFFSET] = srctl5; + base[_MCASP_SRCTL6_OFFSET] = srctl6; + base[_MCASP_SRCTL7_OFFSET] = srctl7; + base[_MCASP_SRCTL8_OFFSET] = srctl8; + base[_MCASP_SRCTL9_OFFSET] = srctl9; + base[_MCASP_SRCTL10_OFFSET] = srctl10; + base[_MCASP_SRCTL11_OFFSET] = srctl11; + base[_MCASP_SRCTL12_OFFSET] = srctl12; + base[_MCASP_SRCTL13_OFFSET] = srctl13; + base[_MCASP_SRCTL14_OFFSET] = srctl14; + base[_MCASP_SRCTL15_OFFSET] = srctl15; + base[_MCASP_AMUTE_OFFSET] = amute; + base[_MCASP_DLBCTL_OFFSET] = dlbctl; + base[_MCASP_DITCTL_OFFSET] = ditctl; + base[_MCASP_PFUNC_OFFSET] = pfunc; + base[_MCASP_PDIR_OFFSET] = pdir; + + IRQ_globalRestore(gie); +} +#endif /* _MCASP_CHANNEL_CNT == 16 */ + +#if (_MCASP_CHANNEL_CNT == 8) +IDEF void MCASP_configArgs(MCASP_Handle hMcasp, Uint32 pfunc, Uint32 pdir, + Uint32 amute, Uint32 dlbctl, Uint32 ditctl, Uint32 rmask, Uint32 rfmt, Uint32 afsrctl, + Uint32 aclkrctl, Uint32 ahclkrctl, Uint32 rtdm, Uint32 rintctl, Uint32 rclkchk, + Uint32 xmask, Uint32 xfmt, Uint32 afsxctl, Uint32 aclkxctl, Uint32 ahclkxctl, Uint32 xtdm, + Uint32 xintctl, Uint32 xclkchk, Uint32 srctl0, Uint32 srctl1, Uint32 srctl2, Uint32 srctl3, + Uint32 srctl4, Uint32 srctl5, Uint32 srctl6, Uint32 srctl7) +{ + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)(hMcasp->baseAddr); + + gie = IRQ_globalDisable(); + + base[_MCASP_RMASK_OFFSET] = rmask; + base[_MCASP_RFMT_OFFSET] = rfmt; + base[_MCASP_AFSRCTL_OFFSET] = afsrctl; + base[_MCASP_ACLKRCTL_OFFSET]= aclkrctl; + base[_MCASP_AHCLKRCTL_OFFSET]=ahclkrctl; + base[_MCASP_RTDM_OFFSET] = rtdm; + base[_MCASP_RINTCTL_OFFSET] = rintctl; + base[_MCASP_RCLKCHK_OFFSET] = rclkchk; + base[_MCASP_XMASK_OFFSET] = xmask; + base[_MCASP_XFMT_OFFSET] = xfmt; + base[_MCASP_AFSXCTL_OFFSET] = afsxctl; + base[_MCASP_ACLKXCTL_OFFSET]= aclkxctl; + base[_MCASP_AHCLKXCTL_OFFSET]=ahclkxctl; + base[_MCASP_XTDM_OFFSET] = xtdm; + base[_MCASP_XINTCTL_OFFSET] = xintctl; + base[_MCASP_XCLKCHK_OFFSET] = xclkchk; + base[_MCASP_SRCTL0_OFFSET] = srctl0; + base[_MCASP_SRCTL1_OFFSET] = srctl1; + base[_MCASP_SRCTL2_OFFSET] = srctl2; + base[_MCASP_SRCTL3_OFFSET] = srctl3; + base[_MCASP_SRCTL4_OFFSET] = srctl4; + base[_MCASP_SRCTL5_OFFSET] = srctl5; + base[_MCASP_SRCTL6_OFFSET] = srctl6; + base[_MCASP_SRCTL7_OFFSET] = srctl7; + base[_MCASP_AMUTE_OFFSET] = amute; + base[_MCASP_DLBCTL_OFFSET] = dlbctl; + base[_MCASP_DITCTL_OFFSET] = ditctl; + base[_MCASP_PFUNC_OFFSET] = pfunc; + base[_MCASP_PDIR_OFFSET] = pdir; + + IRQ_globalRestore(gie); +} +#endif /* _MCASP_CHANNEL_CNT == 8 */ + +#if (_MCASP_CHANNEL_CNT == 6) +IDEF void MCASP_configArgs(MCASP_Handle hMcasp, Uint32 pfunc, Uint32 pdir, + Uint32 amute, Uint32 dlbctl, Uint32 ditctl, Uint32 rmask, Uint32 rfmt, Uint32 afsrctl, + Uint32 aclkrctl, Uint32 ahclkrctl, Uint32 rtdm, Uint32 rintctl, Uint32 rclkchk, + Uint32 xmask, Uint32 xfmt, Uint32 afsxctl, Uint32 aclkxctl, Uint32 ahclkxctl, Uint32 xtdm, + Uint32 xintctl, Uint32 xclkchk, Uint32 srctl0, Uint32 srctl1, Uint32 srctl2, Uint32 srctl3, + Uint32 srctl4, Uint32 srctl5) +{ + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)(hMcasp->baseAddr); + + gie = IRQ_globalDisable(); + + base[_MCASP_RMASK_OFFSET] = rmask; + base[_MCASP_RFMT_OFFSET] = rfmt; + base[_MCASP_AFSRCTL_OFFSET] = afsrctl; + base[_MCASP_ACLKRCTL_OFFSET]= aclkrctl; + base[_MCASP_AHCLKRCTL_OFFSET]= ahclkrctl; + base[_MCASP_RTDM_OFFSET] = rtdm; + base[_MCASP_RINTCTL_OFFSET] = rintctl; + base[_MCASP_RCLKCHK_OFFSET] = rclkchk; + base[_MCASP_XMASK_OFFSET] = xmask; + base[_MCASP_XFMT_OFFSET] = xfmt; + base[_MCASP_AFSXCTL_OFFSET] = afsxctl; + base[_MCASP_ACLKXCTL_OFFSET]= aclkxctl; + base[_MCASP_AHCLKXCTL_OFFSET]=ahclkxctl; + base[_MCASP_XTDM_OFFSET] = xtdm; + base[_MCASP_XINTCTL_OFFSET] = xintctl; + base[_MCASP_XCLKCHK_OFFSET] = xclkchk; + base[_MCASP_SRCTL0_OFFSET] = srctl0; + base[_MCASP_SRCTL1_OFFSET] = srctl1; + base[_MCASP_SRCTL2_OFFSET] = srctl2; + base[_MCASP_SRCTL3_OFFSET] = srctl3; + base[_MCASP_SRCTL4_OFFSET] = srctl4; + base[_MCASP_SRCTL5_OFFSET] = srctl5; + base[_MCASP_AMUTE_OFFSET] = amute; + base[_MCASP_DLBCTL_OFFSET] = dlbctl; + base[_MCASP_DITCTL_OFFSET] = ditctl; + base[_MCASP_PFUNC_OFFSET] = pfunc; + base[_MCASP_PDIR_OFFSET] = pdir; + + IRQ_globalRestore(gie); +} +#endif /* _MCASP_CHANNEL_CNT == 6 */ + +#if (_MCASP_CHANNEL_CNT == 4) +IDEF void MCASP_configArgs(MCASP_Handle hMcasp, Uint32 pfunc, Uint32 pdir, + Uint32 amute, Uint32 dlbctl, Uint32 ditctl, Uint32 rmask, Uint32 rfmt, Uint32 afsrctl, + Uint32 aclkrctl, Uint32 ahclkrctl, Uint32 rtdm, Uint32 rintctl, Uint32 rclkchk, + Uint32 xmask, Uint32 xfmt, Uint32 afsxctl, Uint32 aclkxctl, Uint32 ahclkxctl, Uint32 xtdm, + Uint32 xintctl, Uint32 xclkchk, Uint32 srctl0, Uint32 srctl1, Uint32 srctl2, Uint32 srctl3) +{ + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)(hMcasp->baseAddr); + + gie = IRQ_globalDisable(); + + base[_MCASP_RMASK_OFFSET] = rmask; + base[_MCASP_RFMT_OFFSET] = rfmt; + base[_MCASP_AFSRCTL_OFFSET] = afsrctl; + base[_MCASP_ACLKRCTL_OFFSET]= aclkrctl; + base[_MCASP_AHCLKRCTL_OFFSET]= ahclkrctl; + base[_MCASP_RTDM_OFFSET] = rtdm; + base[_MCASP_RINTCTL_OFFSET] = rintctl; + base[_MCASP_RCLKCHK_OFFSET] = rclkchk; + base[_MCASP_XMASK_OFFSET] = xmask; + base[_MCASP_XFMT_OFFSET] = xfmt; + base[_MCASP_AFSXCTL_OFFSET] = afsxctl; + base[_MCASP_ACLKXCTL_OFFSET]= aclkxctl; + base[_MCASP_AHCLKXCTL_OFFSET]=ahclkxctl; + base[_MCASP_XTDM_OFFSET] = xtdm; + base[_MCASP_XINTCTL_OFFSET] = xintctl; + base[_MCASP_XCLKCHK_OFFSET] = xclkchk; + base[_MCASP_SRCTL0_OFFSET] = srctl0; + base[_MCASP_SRCTL1_OFFSET] = srctl1; + base[_MCASP_SRCTL2_OFFSET] = srctl2; + base[_MCASP_SRCTL3_OFFSET] = srctl3; + base[_MCASP_AMUTE_OFFSET] = amute; + base[_MCASP_DLBCTL_OFFSET] = dlbctl; + base[_MCASP_DITCTL_OFFSET] = ditctl; + base[_MCASP_PFUNC_OFFSET] = pfunc; + base[_MCASP_PDIR_OFFSET] = pdir; + + IRQ_globalRestore(gie); +} +#endif /* _MCASP_CHANNEL_CNT == 4 */ + +/*----------------------------------------------------------------------------*/ +#if (_MCASP_CHANNEL_CNT == 16) +IDEF void MCASP_getConfig(MCASP_Handle hMcasp, MCASP_Config *config) +{ + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)(hMcasp->baseAddr); + volatile MCASP_Config* cfg = (volatile MCASP_Config*)config; + register int x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17,x18,x19; + register int x20,x21,x22,x23,x24,x25,x26,x27,x28,x29,x30,x31,x32,x33,x34,x35,x36; + + gie = IRQ_globalDisable(); + + /* the compiler generates more efficient code if the loads */ + /* and stores are grouped together rather than intermixed */ + + x0 = base[_MCASP_PFUNC_OFFSET]; + x1 = base[_MCASP_PDIR_OFFSET]; + x2 = base[_MCASP_AMUTE_OFFSET]; + x3 = base[_MCASP_DLBCTL_OFFSET]; + x4 = base[_MCASP_DITCTL_OFFSET]; + x5 = base[_MCASP_RMASK_OFFSET]; + x6 = base[_MCASP_RFMT_OFFSET]; + x7 = base[_MCASP_AFSRCTL_OFFSET]; + x8 = base[_MCASP_ACLKRCTL_OFFSET]; + x9 = base[_MCASP_AHCLKRCTL_OFFSET]; + x10 = base[_MCASP_RTDM_OFFSET]; + x11 = base[_MCASP_RINTCTL_OFFSET]; + x12 = base[_MCASP_RCLKCHK_OFFSET]; + x13 = base[_MCASP_XMASK_OFFSET]; + x14 = base[_MCASP_XFMT_OFFSET]; + x15 = base[_MCASP_AFSXCTL_OFFSET]; + x16 = base[_MCASP_ACLKXCTL_OFFSET]; + x17 = base[_MCASP_AHCLKXCTL_OFFSET]; + x18 = base[_MCASP_XTDM_OFFSET]; + x19 = base[_MCASP_XINTCTL_OFFSET]; + x20 = base[_MCASP_XCLKCHK_OFFSET]; + x21 = base[_MCASP_SRCTL0_OFFSET]; + x22 = base[_MCASP_SRCTL1_OFFSET]; + x23 = base[_MCASP_SRCTL2_OFFSET]; + x24 = base[_MCASP_SRCTL3_OFFSET]; + x25 = base[_MCASP_SRCTL4_OFFSET]; + x26 = base[_MCASP_SRCTL5_OFFSET]; + x27 = base[_MCASP_SRCTL6_OFFSET]; + x28 = base[_MCASP_SRCTL7_OFFSET]; + x29 = base[_MCASP_SRCTL8_OFFSET]; + x30 = base[_MCASP_SRCTL9_OFFSET]; + x31 = base[_MCASP_SRCTL10_OFFSET]; + x32 = base[_MCASP_SRCTL11_OFFSET]; + x33 = base[_MCASP_SRCTL12_OFFSET]; + x34 = base[_MCASP_SRCTL13_OFFSET]; + x35 = base[_MCASP_SRCTL14_OFFSET]; + x36 = base[_MCASP_SRCTL15_OFFSET]; + + cfg->global->pfunc = x0; + cfg->global->pdir = x1; + cfg->global->amute = x2; + cfg->global->dlbctl = x3; + cfg->global->ditctl = x4; + cfg->receive->rmask = x5; + cfg->receive->rfmt = x6; + cfg->receive->afsrctl = x7; + cfg->receive->aclkrctl = x8; + cfg->receive->ahclkrctl = x9; + cfg->receive->rtdm = x10; + cfg->receive->rintctl = x11; + cfg->receive->rclkchk = x12; + cfg->transmit->xmask = x13; + cfg->transmit->xfmt = x14; + cfg->transmit->afsxctl = x15; + cfg->transmit->aclkxctl = x16; + cfg->transmit->ahclkxctl = x17; + cfg->transmit->xtdm = x18; + cfg->transmit->xintctl = x19; + cfg->transmit->xclkchk = x20; + cfg->srctl->srctl0 = x21; + cfg->srctl->srctl1 = x22; + cfg->srctl->srctl2 = x23; + cfg->srctl->srctl3 = x24; + cfg->srctl->srctl4 = x25; + cfg->srctl->srctl5 = x26; + cfg->srctl->srctl6 = x27; + cfg->srctl->srctl7 = x28; + cfg->srctl->srctl8 = x29; + cfg->srctl->srctl9 = x30; + cfg->srctl->srctl10 = x31; + cfg->srctl->srctl11 = x32; + cfg->srctl->srctl12 = x33; + cfg->srctl->srctl13 = x34; + cfg->srctl->srctl14 = x35; + cfg->srctl->srctl15 = x36; + + IRQ_globalRestore(gie); +} +#endif /* _MCASP_CHANNEL_CNT == 16 */ + +#if (_MCASP_CHANNEL_CNT == 8) +IDEF void MCASP_getConfig(MCASP_Handle hMcasp, MCASP_Config *config) +{ + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)(hMcasp->baseAddr); + volatile MCASP_Config* cfg = (volatile MCASP_Config*)config; + register int x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17,x18,x19; + register int x20,x21,x22,x23,x24,x25,x26,x27,x28; + + gie = IRQ_globalDisable(); + + /* the compiler generates more efficient code if the loads */ + /* and stores are grouped together rather than intermixed */ + + x0 = base[_MCASP_PFUNC_OFFSET]; + x1 = base[_MCASP_PDIR_OFFSET]; + x2 = base[_MCASP_AMUTE_OFFSET]; + x3 = base[_MCASP_DLBCTL_OFFSET]; + x4 = base[_MCASP_DITCTL_OFFSET]; + x5 = base[_MCASP_RMASK_OFFSET]; + x6 = base[_MCASP_RFMT_OFFSET]; + x7 = base[_MCASP_AFSRCTL_OFFSET]; + x8 = base[_MCASP_ACLKRCTL_OFFSET]; + x9 = base[_MCASP_AHCLKRCTL_OFFSET]; + x10 = base[_MCASP_RTDM_OFFSET]; + x11 = base[_MCASP_RINTCTL_OFFSET]; + x12 = base[_MCASP_RCLKCHK_OFFSET]; + x13 = base[_MCASP_XMASK_OFFSET]; + x14 = base[_MCASP_XFMT_OFFSET]; + x15 = base[_MCASP_AFSXCTL_OFFSET]; + x16 = base[_MCASP_ACLKXCTL_OFFSET]; + x17 = base[_MCASP_AHCLKXCTL_OFFSET]; + x18 = base[_MCASP_XTDM_OFFSET]; + x19 = base[_MCASP_XINTCTL_OFFSET]; + x20 = base[_MCASP_XCLKCHK_OFFSET]; + x21 = base[_MCASP_SRCTL0_OFFSET]; + x22 = base[_MCASP_SRCTL1_OFFSET]; + x23 = base[_MCASP_SRCTL2_OFFSET]; + x24 = base[_MCASP_SRCTL3_OFFSET]; + x25 = base[_MCASP_SRCTL4_OFFSET]; + x26 = base[_MCASP_SRCTL5_OFFSET]; + x27 = base[_MCASP_SRCTL6_OFFSET]; + x28 = base[_MCASP_SRCTL7_OFFSET]; + + cfg->global->pfunc = x0; + cfg->global->pdir = x1; + cfg->global->amute = x2; + cfg->global->dlbctl = x3; + cfg->global->ditctl = x4; + cfg->receive->rmask = x5; + cfg->receive->rfmt = x6; + cfg->receive->afsrctl = x7; + cfg->receive->aclkrctl = x8; + cfg->receive->ahclkrctl = x9; + cfg->receive->rtdm = x10; + cfg->receive->rintctl = x11; + cfg->receive->rclkchk = x12; + cfg->transmit->xmask = x13; + cfg->transmit->xfmt = x14; + cfg->transmit->afsxctl = x15; + cfg->transmit->aclkxctl = x16; + cfg->transmit->ahclkxctl = x17; + cfg->transmit->xtdm = x18; + cfg->transmit->xintctl = x19; + cfg->transmit->xclkchk = x20; + cfg->srctl->srctl0 = x21; + cfg->srctl->srctl1 = x22; + cfg->srctl->srctl2 = x23; + cfg->srctl->srctl3 = x24; + cfg->srctl->srctl4 = x25; + cfg->srctl->srctl5 = x26; + cfg->srctl->srctl6 = x27; + cfg->srctl->srctl7 = x28; + + IRQ_globalRestore(gie); +} +#endif /* _MCASP_CHANNEL_CNT == 8 */ + +#if (_MCASP_CHANNEL_CNT == 6) +IDEF void MCASP_getConfig(MCASP_Handle hMcasp, MCASP_Config *config) +{ + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)(hMcasp->baseAddr); + volatile MCASP_Config* cfg = (volatile MCASP_Config*)config; + register int x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17,x18,x19; + register int x20,x21,x22,x23,x24,x25,x26; + + gie = IRQ_globalDisable(); + + /* the compiler generates more efficient code if the loads */ + /* and stores are grouped together rather than intermixed */ + + x0 = base[_MCASP_PFUNC_OFFSET]; + x1 = base[_MCASP_PDIR_OFFSET]; + x2 = base[_MCASP_AMUTE_OFFSET]; + x3 = base[_MCASP_DLBCTL_OFFSET]; + x4 = base[_MCASP_DITCTL_OFFSET]; + x5 = base[_MCASP_RMASK_OFFSET]; + x6 = base[_MCASP_RFMT_OFFSET]; + x7 = base[_MCASP_AFSRCTL_OFFSET]; + x8 = base[_MCASP_ACLKRCTL_OFFSET]; + x9 = base[_MCASP_AHCLKRCTL_OFFSET]; + x10 = base[_MCASP_RTDM_OFFSET]; + x11 = base[_MCASP_RINTCTL_OFFSET]; + x12 = base[_MCASP_RCLKCHK_OFFSET]; + x13 = base[_MCASP_XMASK_OFFSET]; + x14 = base[_MCASP_XFMT_OFFSET]; + x15 = base[_MCASP_AFSXCTL_OFFSET]; + x16 = base[_MCASP_ACLKXCTL_OFFSET]; + x17 = base[_MCASP_AHCLKXCTL_OFFSET]; + x18 = base[_MCASP_XTDM_OFFSET]; + x19 = base[_MCASP_XINTCTL_OFFSET]; + x20 = base[_MCASP_XCLKCHK_OFFSET]; + x21 = base[_MCASP_SRCTL0_OFFSET]; + x22 = base[_MCASP_SRCTL1_OFFSET]; + x23 = base[_MCASP_SRCTL2_OFFSET]; + x24 = base[_MCASP_SRCTL3_OFFSET]; + x25 = base[_MCASP_SRCTL4_OFFSET]; + x26 = base[_MCASP_SRCTL5_OFFSET]; + + cfg->global->pfunc = x0; + cfg->global->pdir = x1; + cfg->global->amute = x2; + cfg->global->dlbctl = x3; + cfg->global->ditctl = x4; + cfg->receive->rmask = x5; + cfg->receive->rfmt = x6; + cfg->receive->afsrctl = x7; + cfg->receive->aclkrctl = x8; + cfg->receive->ahclkrctl = x9; + cfg->receive->rtdm = x10; + cfg->receive->rintctl = x11; + cfg->receive->rclkchk = x12; + cfg->transmit->xmask = x13; + cfg->transmit->xfmt = x14; + cfg->transmit->afsxctl = x15; + cfg->transmit->aclkxctl = x16; + cfg->transmit->ahclkxctl = x17; + cfg->transmit->xtdm = x18; + cfg->transmit->xintctl = x19; + cfg->transmit->xclkchk = x20; + cfg->srctl->srctl0 = x21; + cfg->srctl->srctl1 = x22; + cfg->srctl->srctl2 = x23; + cfg->srctl->srctl3 = x24; + cfg->srctl->srctl4 = x25; + cfg->srctl->srctl5 = x26; + + IRQ_globalRestore(gie); +} +#endif /* _MCASP_CHANNEL_CNT == 6 */ + +#if (_MCASP_CHANNEL_CNT == 4) +IDEF void MCASP_getConfig(MCASP_Handle hMcasp, MCASP_Config *config) +{ + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)(hMcasp->baseAddr); + volatile MCASP_Config* cfg = (volatile MCASP_Config*)config; + register int x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17,x18,x19; + register int x20,x21,x22,x23,x24; + + gie = IRQ_globalDisable(); + + /* the compiler generates more efficient code if the loads */ + /* and stores are grouped together rather than intermixed */ + + x0 = base[_MCASP_PFUNC_OFFSET]; + x1 = base[_MCASP_PDIR_OFFSET]; + x2 = base[_MCASP_AMUTE_OFFSET]; + x3 = base[_MCASP_DLBCTL_OFFSET]; + x4 = base[_MCASP_DITCTL_OFFSET]; + x5 = base[_MCASP_RMASK_OFFSET]; + x6 = base[_MCASP_RFMT_OFFSET]; + x7 = base[_MCASP_AFSRCTL_OFFSET]; + x8 = base[_MCASP_ACLKRCTL_OFFSET]; + x9 = base[_MCASP_AHCLKRCTL_OFFSET]; + x10 = base[_MCASP_RTDM_OFFSET]; + x11 = base[_MCASP_RINTCTL_OFFSET]; + x12 = base[_MCASP_RCLKCHK_OFFSET]; + x13 = base[_MCASP_XMASK_OFFSET]; + x14 = base[_MCASP_XFMT_OFFSET]; + x15 = base[_MCASP_AFSXCTL_OFFSET]; + x16 = base[_MCASP_ACLKXCTL_OFFSET]; + x17 = base[_MCASP_AHCLKXCTL_OFFSET]; + x18 = base[_MCASP_XTDM_OFFSET]; + x19 = base[_MCASP_XINTCTL_OFFSET]; + x20 = base[_MCASP_XCLKCHK_OFFSET]; + x21 = base[_MCASP_SRCTL0_OFFSET]; + x22 = base[_MCASP_SRCTL1_OFFSET]; + x23 = base[_MCASP_SRCTL2_OFFSET]; + x24 = base[_MCASP_SRCTL3_OFFSET]; + + cfg->global->pfunc = x0; + cfg->global->pdir = x1; + cfg->global->amute = x2; + cfg->global->dlbctl = x3; + cfg->global->ditctl = x4; + cfg->receive->rmask = x5; + cfg->receive->rfmt = x6; + cfg->receive->afsrctl = x7; + cfg->receive->aclkrctl = x8; + cfg->receive->ahclkrctl = x9; + cfg->receive->rtdm = x10; + cfg->receive->rintctl = x11; + cfg->receive->rclkchk = x12; + cfg->transmit->xmask = x13; + cfg->transmit->xfmt = x14; + cfg->transmit->afsxctl = x15; + cfg->transmit->aclkxctl = x16; + cfg->transmit->ahclkxctl = x17; + cfg->transmit->xtdm = x18; + cfg->transmit->xintctl = x19; + cfg->transmit->xclkchk = x20; + cfg->srctl->srctl0 = x21; + cfg->srctl->srctl1 = x22; + cfg->srctl->srctl2 = x23; + cfg->srctl->srctl3 = x24; + + IRQ_globalRestore(gie); +} +#endif /* _MCASP_CHANNEL_CNT == 4 */ + + +/*----------------------------------------------------------------------------*/ +#endif /* USEDEFS */ + + +#endif /* MCASP_SUPPORT */ +#endif /* _CSL_MCASP_H_ */ +/******************************************************************************\ +* End of csl_mcasp.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_mcasphal.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_mcasphal.h new file mode 100644 index 0000000..333b045 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_mcasphal.h @@ -0,0 +1,7292 @@ +/******************************************************************************\ +* Step 1. Copyright (C) 2001 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_mcasphal.h +* DATE CREATED.. 06/28/2001 +* LAST MODIFIED. +* 08/02/2004 - Adding support for C6418 +*------------------------------------------------------------------------------ +*HISTORY......6/29/01, changed RSLOT to RSLOTCNT, XSLOT to XSLOTCNT +* 7/2/01, XFMT: changed XROT field to 0-2 instead of 0-3 +* also added field XDATDLY in bits 17:16 (made appropriate macro changes) +* RFMT: same as above (RROT wasn't specified, but made sense) +* AFSXCTL/AFSRCTL: removed X(R)DATDLY fields and macro entries. +* ACLKRCTL: changed CLKRDIV field to bits 4:0(was 5:0),CLKRM to bit 5(was 6) +* HCLKXDIV/HCLKRDIV: changed field HCLKX(R)DIV to bit 11:0 (was 12:0) +* SCRTL: changed defaults of fields XRDY and RRDY to 0b (was 1b) +* Added register DLBCTL +* Added registers X(R)INTCTL +* 8/6/01 fixed MCASP_RFMT_RPAD_RPBIT; was formerly _XPBIT +* 08/13/01 V.G. Reordered the registers and added OFFSETs +* 08/14/01 V.G. Corrected syntax errors +* 08/20/01 V.G. Added addresses for each register +* +* 17/06/04 Adding support for DM640/641 +* 11/03/01 F.S CRFAIL -> RCKFAIL / CXFAIL -> XCKFAIL +* 11/15/01 F.S PWREMUMGT -> PWRDEMU +* PFUNC / PDIR /PDSOUT /PDSET /PDCLR -> fields renaming +* 11/20/01 F.S GBLCTL / XGBLCTL / RGBLCTL +* RRST -> RSMRST , RGRST -> RCLKRST , HCLKRRST -> RHCLKRST +* XRST -> XSMRST , XGRST -> XCLKRST , HCLKXRST -> XHCLKRST +* 10/22/03 Fixed the typos in MCASP_PDOUT_DEFAULT and MCASP_PDOUT_RMK +* +*------------------------------------------------------------------------------ +* REGISTERS (register list) +* +* PID - Peripheral Identification Register +* PWRDEMU - Power Down and Emulation Management Register +* PFUNC - Pin Function / GPIO Enable Register +* PDIR - Pin Direction Register +* PDAT - Pin Data Register +* PDIN - Pin Data Input Register +* PDOUT - Pin Data Output Register +* PDSET - Pin Data Set Register +* PDCLR - Pin Data Clear Register +* DITCTL - Transmit DIT Control Register +* DLBCTL - Loop Back Control Mode +* XFMT - Transmit Bitstream Format Register +* RFMT - Receive Bitstream Format Register +* XMASK +* RMASK +* AFSXCTL - Transmit Frame Control Register +* AFSRCTL - Receive Frame Control Register +* ACLKXCTL - Transmit Clock Control Register +* ACLKRCTL - Receive Clock Control Register +* AHCLKXCTL - High Frequency Transmit Clock Control Register Description +* AHCLKRCTL - High Frequency Receive Clock Control Register Description +* SRCTL0 - Serializer Control Register 0 +* SRCTL1 - Serializer Control Register 1 +* SRCTL2 - Serializer Control Register 2 +* SRCTL3 - Serializer Control Register 3 +* SRCTL4 - Serializer Control Register 4 +* SRCTL5 - Serializer Control Register 5 +* SRCTL6 - Serializer Control Register 6 +* SRCTL7 - Serializer Control Register 7 +* SRCTL8 - Serializer Control Register 8 (1) +* SRCTL9 - Serializer Control Register 9 (1) +* SRCTL10 - Serializer Control Register 10 (1) +* SRCTL11 - Serializer Control Register 11 (1) +* SRCTL12 - Serializer Control Register 12 (1) +* SRCTL13 - Serializer Control Register 13 (1) +* SRCTL14 - Serializer Control Register 14 (1) +* SRCTL15 - Serializer Control Register 15 (1) +* XTDM - Transmit TDM Register +* RTDM - Receive TDM Register +* GBLCTL - Global Control Register +* XGBLCTL - Global Control Register +* RGBLCTL - Global Control Register +* AMUTE - Mute Control Register +* XINTCTL - Transmitter Interrupt Control Register +* RINTCTL - Receiver Interrupt Control Register +* RSTAT - Receiver Status Register +* XSTAT - Transmitter Status Register +* RSLOTCNT - Receiver TDM Slot Counter +* XSLOTCNT - Transmitter TDM Slot Counter +* XCLKCHK - Transmit Clock Check Control Register +* RCLKCHK - Receive Clock Check Control Register +* XBUF0 - Transmit Buffer for Serializer 0 +* XBUF1 - Transmit Buffer for Serializer 1 +* XBUF2 - Transmit Buffer for Serializer 2 +* XBUF3 - Transmit Buffer for Serializer 3 +* XBUF4 - Transmit Buffer for Serializer 4 +* XBUF5 - Transmit Buffer for Serializer 5 +* XBUF6 - Transmit Buffer for Serializer 6 +* XBUF7 - Transmit Buffer for Serializer 7 +* XBUF8 - Transmit Buffer for Serializer 8 (1) +* XBUF9 - Transmit Buffer for Serializer 9 (1) +* XBUF10 - Transmit Buffer for Serializer 10 (1) +* XBUF11 - Transmit Buffer for Serializer 11 (1) +* XBUF12 - Transmit Buffer for Serializer 12 (1) +* XBUF13 - Transmit Buffer for Serializer 13 (1) +* XBUF14 - Transmit Buffer for Serializer 14 (1) +* XBUF15 - Transmit Buffer for Serializer 15 (1) +* RBUF0 - Receive Buffer for Serializer 0 +* RBUF1 - Receive Buffer for Serializer 1 +* RBUF2 - Receive Buffer for Serializer 2 +* RBUF3 - Receive Buffer for Serializer 3 +* RBUF4 - Receive Buffer for Serializer 4 +* RBUF5 - Receive Buffer for Serializer 5 +* RBUF6 - Receive Buffer for Serializer 6 +* RBUF7 - Receive Buffer for Serializer 7 +* RBUF8 - Receive Buffer for Serializer 8 +* RBUF9 - Receive Buffer for Serializer 9 +* RBUF10 - Receive Buffer for Serializer 10 +* RBUF11 - Receive Buffer for Serializer 11 +* RBUF12 - Receive Buffer for Serializer 12 +* RBUF13 - Receive Buffer for Serializer 13 +* RBUF14 - Receive Buffer for Serializer 14 +* RBUF15 - Receive Buffer for Serializer 15 +* DITCSRA0n - Left (even TDM Slot) Channel Status Register File +* DITCSRA1n +* DITCSRA2n +* DITCSRA3n +* DITCSRA4n +* DITCSRA5n +* DITCSRB0n - Right (even TDM Slot) Channel Status Register File +* DITCSRB1n +* DITCSRB2n +* DITCSRB3n +* DITCSRB4n +* DITCSRB5n +* DITUDRA0n - Left (even TDM Slot) User Data Register File +* DITUDRA1n +* DITUDRA2n +* DITUDRA3n +* DITUDRA4n +* DITUDRA5n +* DITUDRB0n - Right (even TDM Slot) User Data Register File +* DITUDRB1n +* DITUDRB2n +* DITUDRB3n +* DITUDRB4n +* DITUDRB5n +* +* +\******************************************************************************/ +/******************************************************************************\ +* Step 2. Private Macros and Include files +\******************************************************************************/ +#ifndef _CSL_MCASPHAL_H_ +#define _CSL_MCASPHAL_H_ + +#include +#include + +#if (MCASP_SUPPORT) +/******************************************************************************\ +* Step 3. MISC section +* Example: +* #define _MCASP_BASE_GLOBAL 0xXXXXXXXXu +\******************************************************************************/ +#if (CHIP_6713 | CHIP_DA610 | CHIP_6413 | CHIP_6418 | CHIP_6410) + #define _MCASP_PORT_CNT 2 +#endif + +#if (CHIP_DM642 | CHIP_DM641 | CHIP_DM640) + #define _MCASP_PORT_CNT 1 +#endif + +#if (CHIP_DM641 | CHIP_DM640) + #define _MCASP_CHANNEL_CNT 4 +#endif + +#if (CHIP_6413 | CHIP_6418 | CHIP_6410) + #define _MCASP_CHANNEL_CNT 6 +#endif + +#if (CHIP_DM642 | CHIP_6713) + #define _MCASP_CHANNEL_CNT 8 +#endif + +#if (CHIP_DA610) + #define _MCASP_CHANNEL_CNT 16 +#endif + +#define _MCASP_BASE_PORT0 0x01B4C000u +#define _MCASP_BASE_PORT1 0x01B50000u + +/******************************************************************************\ +* Step 4. Module level register/field access macros +\******************************************************************************/ + + /* -------------------------- */ + /* Step 4.1 FIELD MAKE MACROS */ + /* -------------------------- */ + + #define MCASP_FMK(REG,FIELD,x)\ + _PER_FMK(MCASP,##REG,##FIELD,x) + + #define MCASP_FMKS(REG,FIELD,SYM)\ + _PER_FMKS(MCASP,##REG,##FIELD,##SYM) + + + /* ----------------------------------------- */ + /* Step 4.2 RAW REGISTER/FIELD ACCESS MACROS */ + /* ----------------------------------------- */ + + #define MCASP_ADDR(REG)\ + _MCASP_##REG##_ADDR + + #define MCASP_RGET(REG)\ + _PER_RGET(_MCASP_##REG##_ADDR,MCASP,##REG) + + #define MCASP_RSET(REG,x)\ + _PER_RSET(_MCASP_##REG##_ADDR,MCASP,##REG,x) + + #define MCASP_FGET(REG,FIELD)\ + _MCASP_##REG##_FGET(##FIELD) + + #define MCASP_FSET(REG,FIELD,x)\ + _MCASP_##REG##_FSET(##FIELD,x) + + #define MCASP_FSETS(REG,FIELD,SYM)\ + _MCASP_##REG##_FSETS(##FIELD,##SYM) + + + /* --------------------------------------------------- */ + /* Step 4.3 ADDRESS BASED REGISTER/FIELD ACCESS MACROS */ + /* --------------------------------------------------- */ + + #define MCASP_RGETA(addr,REG)\ + _PER_RGET(addr,MCASP,##REG) + + #define MCASP_RSETA(addr,REG,x)\ + _PER_RSET(addr,MCASP,##REG,x) + + #define MCASP_FGETA(addr,REG,FIELD)\ + _PER_FGET(addr,MCASP,##REG,##FIELD) + + #define MCASP_FSETA(addr,REG,FIELD,x)\ + _PER_FSET(addr,MCASP,##REG,##FIELD,x) + + #define MCASP_FSETSA(addr,REG,FIELD,SYM)\ + _PER_FSETS(addr,MCASP,##REG,##FIELD,##SYM) + + /* -------------------------------------------------- */ + /* Step 4.4 HANDLE BASED REGISTER/FIELD ACCESS MACROS */ + /* -------------------------------------------------- */ + + /* For non-handle based Module : remove the following macros (remove me)*/ + /* See CDK Chapter 3. Module specification and CSL definitions ( remove me)*/ + + #define MCASP_ADDRH(h,REG)\ + (Uint32)(&((h)->baseAddr[_MCASP_##REG##_OFFSET])) + + #define MCASP_RGETH(h,REG)\ + MCASP_RGETA(MCASP_ADDRH(h,##REG),##REG) + + #define MCASP_RSETH(h,REG,x)\ + MCASP_RSETA(MCASP_ADDRH(h,##REG),##REG,x) + + #define MCASP_FGETH(h,REG,FIELD)\ + MCASP_FGETA(MCASP_ADDRH(h,##REG),##REG,##FIELD) + + #define MCASP_FSETH(h,REG,FIELD,x)\ + MCASP_FSETA(MCASP_ADDRH(h,##REG),##REG,##FIELD,x) + + #define MCASP_FSETSH(h,REG,FIELD,SYM)\ + MCASP_FSETSA(MCASP_ADDRH(h,##REG),##REG,##FIELD,##SYM) + + + +/******************************************************************************\ +* +* _____________________ +* | | +* | P I D | +* |___________________| +* +* PID - Peripheral Identification Register +* +* FIELDS (msb -> lsb) +* (r) TYPE +* (r) CLASS +* (r) REV +* +\******************************************************************************/ + + #define _MCASP_PID_OFFSET 0 + + #define _MCASP_PID0_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_PID_OFFSET) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_PID1_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_PID_OFFSET) +#endif + + #define _MCASP_PID_TYPE_MASK 0x00FF0000u + #define _MCASP_PID_TYPE_SHIFT 0x00000010u + #define MCASP_PID_TYPE_DEFAULT 0x00000010u + #define MCASP_PID_TYPE_OF(x) _VALUEOF(x) + #define MCASP_PID_TYPE_MCASP 0x00000010u + + + #define _MCASP_PID_CLASS_MASK 0x0000FF00u + #define _MCASP_PID_CLASS_SHIFT 0x00000008u + #define MCASP_PID_CLASS_DEFAULT 0x00000001u + #define MCASP_PID_CLASS_OF(x) _VALUEOF(x) + #define MCASP_PID_CLASS_SERPORT 0x00000001u + + + #define _MCASP_PID_REV_MASK 0x000000FFu + #define _MCASP_PID_REV_SHIFT 0x00000000u + #define MCASP_PID_REV_DEFAULT 0x00000001u + #define MCASP_PID_REV_OF(x) _VALUEOF(x) + #define MCASP_PID_REV_ONE 0x00000001u + + + #define MCASP_PID_OF(x) _VALUEOF(x) + + #define MCASP_PID_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,PID,TYPE)\ + | _PER_FDEFAULT(MCASP,PID,CLASS)\ + | _PER_FDEFAULT(MCASP,PID,REV)\ + ) + + + #define MCASP_PID_RMK(type, class, rev) (Uint32)( \ + _PER_FMK(MCASP,PID,TYPE,type)\ + | _PER_FMK(MCASP,PID,CLASS,class)\ + | _PER_FMK(MCASP,PID,REV,rev)\ + ) + + + #define _MCASP_PID_FGET(N,FIELD)\ + _PER_FGET(_MCASP_PID##N##_ADDR,MCASP,PID,##FIELD) + + #define _MCASP_PID_FSET(N,FIELD,field)\ + _PER_FSET(_MCASP_PID##N##_ADDR,MCASP,PID,##FIELD,field) + + #define _MCASP_PID_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCASP_PID##N##_ADDR,MCASP,PID,##FIELD,##SYM) + + #define _MCASP_PID0_FGET(FIELD) _MCASP_PID_FGET(0,##FIELD) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_PID1_FGET(FIELD) _MCASP_PID_FGET(1,##FIELD) +#endif + + #define _MCASP_PID0_FSET(FIELD,f) _MCASP_PID_FSET(0,##FIELD,f) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_PID1_FSET(FIELD,f) _MCASP_PID_FSET(1,##FIELD,f) +#endif + + #define _MCASP_PID0_FSETS(FIELD,SYM) _MCASP_PID_FSETS(0,##FIELD,##SYM) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_PID1_FSETS(FIELD,SYM) _MCASP_PID_FSETS(1,##FIELD,##SYM) +#endif + +/******************************************************************************\ +* Step 4.5 +* _____________________ +* | | +* | PWRDEMU | +* |___________________| +* +* PWRDEMU - Power Down and Emulation Management +* +* FIELDS (msb -> lsb) +* (rw) FREE +* +\******************************************************************************/ + + #define _MCASP_PWRDEMU_OFFSET 1 + + #define _MCASP_PWRDEMU0_ADDR (_MCASP_BASE_PORT0+4*_MCASP_PWRDEMU_OFFSET) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_PWRDEMU1_ADDR (_MCASP_BASE_PORT1+4*_MCASP_PWRDEMU_OFFSET) +#endif + + #define _MCASP_PWRDEMU_FREE_MASK 0x00000001u + #define _MCASP_PWRDEMU_FREE_SHIFT 0x00000000u + #define MCASP_PWRDEMU_FREE_DEFAULT 0x00000000u + #define MCASP_PWRDEMU_FREE_OF(x) _VALUEOF(x) + #define MCASP_PWRDEMU_FREE_OFF 0x00000000u + #define MCASP_PWRDEMU_FREE_ON 0x00000001u + + #define MCASP_PWRDEMU_OF(x) _VALUEOF(x) + + #define MCASP_PWRDEMU_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,PWRDEMU,FREE)\ + ) + + #define MCASP_PWRDEMU_RMK(free) (Uint32)( \ + _PER_FMK(MCASP,PWRDEMU,FREE,free)\ + ) + + #define _MCASP_PWRDEMU_FGET(N,FIELD)\ + _PER_FGET(_MCASP_PWRDEMU##N##_ADDR,MCASP,PWRDEMU,##FIELD) + + #define _MCASP_PWRDEMU_FSET(N,FIELD,field)\ + _PER_FSET(_MCASP_PWRDEMU##N##_ADDR,MCASP,PWRDEMU,##FIELD,field) + + #define _MCASP_PWRDEMU_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCASP_PWRDEMU##N##_ADDR,MCASP,PWRDEMU,##FIELD,##SYM) + + #define _MCASP_PWRDEMU0_FGET(FIELD) _MCASP_PWRDEMU_FGET(0,##FIELD) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_PWRDEMU1_FGET(FIELD) _MCASP_PWRDEMU_FGET(1,##FIELD) +#endif + + #define _MCASP_PWRDEMU0_FSET(FIELD,f) _MCASP_PWRDEMU_FSET(0,##FIELD,f) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_PWRDEMU1_FSET(FIELD,f) _MCASP_PWRDEMU_FSET(1,##FIELD,f) +#endif + + #define _MCASP_PWRDEMU0_FSETS(FIELD,SYM) _MCASP_PWRDEMU_FSETS(0,##FIELD,##SYM) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_PWRDEMU1_FSETS(FIELD,SYM) _MCASP_PWRDEMU_FSETS(1,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* Step 4.5 +* _____________________ +* | | +* | PFUNC | +* |___________________| +* +* PFUNC - Pin Function / GPIO Enable Register +* +* FIELDS (msb -> lsb) +* (rw) AFSR +* (rw) AHCLKR +* (rw) ACLKR +* (rw) AFSX +* (rw) AHCLKX +* (rw) ACLKX +* (rw) AMUTE +* (rw) AXR0-15 +\******************************************************************************/ + + #define _MCASP_PFUNC_OFFSET 4 + + #define _MCASP_PFUNC0_ADDR (_MCASP_BASE_PORT0+4*_MCASP_PFUNC_OFFSET) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_PFUNC1_ADDR (_MCASP_BASE_PORT1+4*_MCASP_PFUNC_OFFSET) +#endif + #define _MCASP_PFUNC_AXR0_MASK 0x00000001u + #define _MCASP_PFUNC_AXR0_SHIFT 0x00000000u + #define MCASP_PFUNC_AXR0_DEFAULT 0x00000000u + #define MCASP_PFUNC_AXR0_OF(x) _VALUEOF(x) + #define MCASP_PFUNC_AXR0_MCASP 0x00000000u + #define MCASP_PFUNC_AXR0_GPIO 0x00000001u + + #define _MCASP_PFUNC_AXR1_MASK 0x00000002u + #define _MCASP_PFUNC_AXR1_SHIFT 0x00000001u + #define MCASP_PFUNC_AXR1_DEFAULT 0x00000000u + #define MCASP_PFUNC_AXR1_OF(x) _VALUEOF(x) + #define MCASP_PFUNC_AXR1_MCASP 0x00000000u + #define MCASP_PFUNC_AXR1_GPIO 0x00000001u + + #define _MCASP_PFUNC_AXR2_MASK 0x00000004u + #define _MCASP_PFUNC_AXR2_SHIFT 0x00000002u + #define MCASP_PFUNC_AXR2_DEFAULT 0x00000000u + #define MCASP_PFUNC_AXR2_OF(x) _VALUEOF(x) + #define MCASP_PFUNC_AXR2_MCASP 0x00000000u + #define MCASP_PFUNC_AXR2_GPIO 0x00000001u + + #define _MCASP_PFUNC_AXR3_MASK 0x00000008u + #define _MCASP_PFUNC_AXR3_SHIFT 0x00000003u + #define MCASP_PFUNC_AXR3_DEFAULT 0x00000000u + #define MCASP_PFUNC_AXR3_OF(x) _VALUEOF(x) + #define MCASP_PFUNC_AXR3_MCASP 0x00000000u + #define MCASP_PFUNC_AXR3_GPIO 0x00000001u + /* Fields for _MCASP_CHANNEL_CNT == 4 end here*/ + +#if (_MCASP_CHANNEL_CNT > 4) + #define _MCASP_PFUNC_AXR4_MASK 0x00000010u + #define _MCASP_PFUNC_AXR4_SHIFT 0x00000004u + #define MCASP_PFUNC_AXR4_DEFAULT 0x00000000u + #define MCASP_PFUNC_AXR4_OF(x) _VALUEOF(x) + #define MCASP_PFUNC_AXR4_MCASP 0x00000000u + #define MCASP_PFUNC_AXR4_GPIO 0x00000001u + + #define _MCASP_PFUNC_AXR5_MASK 0x00000020u + #define _MCASP_PFUNC_AXR5_SHIFT 0x00000005u + #define MCASP_PFUNC_AXR5_DEFAULT 0x00000000u + #define MCASP_PFUNC_AXR5_OF(x) _VALUEOF(x) + #define MCASP_PFUNC_AXR5_MCASP 0x00000000u + #define MCASP_PFUNC_AXR5_GPIO 0x00000001u +#endif /* _MCASP_CHANNEL_CNT == 6 */ + +#if (_MCASP_CHANNEL_CNT > 6) /* For channel count 8 and 16 */ + #define _MCASP_PFUNC_AXR6_MASK 0x00000040u + #define _MCASP_PFUNC_AXR6_SHIFT 0x00000006u + #define MCASP_PFUNC_AXR6_DEFAULT 0x00000000u + #define MCASP_PFUNC_AXR6_OF(x) _VALUEOF(x) + #define MCASP_PFUNC_AXR6_MCASP 0x00000000u + #define MCASP_PFUNC_AXR6_GPIO 0x00000001u + + #define _MCASP_PFUNC_AXR7_MASK 0x00000080u + #define _MCASP_PFUNC_AXR7_SHIFT 0x00000007u + #define MCASP_PFUNC_AXR7_DEFAULT 0x00000000u + #define MCASP_PFUNC_AXR7_OF(x) _VALUEOF(x) + #define MCASP_PFUNC_AXR7_MCASP 0x00000000u + #define MCASP_PFUNC_AXR7_GPIO 0x00000001u +#endif /* _MCASP_CHANNEL_CNT == 8 */ + +#if (_MCASP_CHANNEL_CNT == 16) + #define _MCASP_PFUNC_AXR8_MASK 0x00000100u + #define _MCASP_PFUNC_AXR8_SHIFT 0x00000008u + #define MCASP_PFUNC_AXR8_DEFAULT 0x00000000u + #define MCASP_PFUNC_AXR8_OF(x) _VALUEOF(x) + #define MCASP_PFUNC_AXR8_MCASP 0x00000000u + #define MCASP_PFUNC_AXR8_GPIO 0x00000001u + + #define _MCASP_PFUNC_AXR9_MASK 0x00000200u + #define _MCASP_PFUNC_AXR9_SHIFT 0x00000009u + #define MCASP_PFUNC_AXR9_DEFAULT 0x00000000u + #define MCASP_PFUNC_AXR9_OF(x) _VALUEOF(x) + #define MCASP_PFUNC_AXR9_MCASP 0x00000000u + #define MCASP_PFUNC_AXR9_GPIO 0x00000001u + + #define _MCASP_PFUNC_AXR10_MASK 0x00000400u + #define _MCASP_PFUNC_AXR10_SHIFT 0x0000000Au + #define MCASP_PFUNC_AXR10_DEFAULT 0x00000000u + #define MCASP_PFUNC_AXR10_OF(x) _VALUEOF(x) + #define MCASP_PFUNC_AXR10_MCASP 0x00000000u + #define MCASP_PFUNC_AXR10_GPIO 0x00000001u + + #define _MCASP_PFUNC_AXR11_MASK 0x00000800u + #define _MCASP_PFUNC_AXR11_SHIFT 0x0000000Bu + #define MCASP_PFUNC_AXR11_DEFAULT 0x00000000u + #define MCASP_PFUNC_AXR11_OF(x) _VALUEOF(x) + #define MCASP_PFUNC_AXR11_MCASP 0x00000000u + #define MCASP_PFUNC_AXR11_GPIO 0x00000001u + + #define _MCASP_PFUNC_AXR12_MASK 0x00001000u + #define _MCASP_PFUNC_AXR12_SHIFT 0x0000000Cu + #define MCASP_PFUNC_AXR12_DEFAULT 0x00000000u + #define MCASP_PFUNC_AXR12_OF(x) _VALUEOF(x) + #define MCASP_PFUNC_AXR12_MCASP 0x00000000u + #define MCASP_PFUNC_AXR12_GPIO 0x00000001u + + #define _MCASP_PFUNC_AXR13_MASK 0x00002000u + #define _MCASP_PFUNC_AXR13_SHIFT 0x0000000Du + #define MCASP_PFUNC_AXR13_DEFAULT 0x00000000u + #define MCASP_PFUNC_AXR13_OF(x) _VALUEOF(x) + #define MCASP_PFUNC_AXR13_MCASP 0x00000000u + #define MCASP_PFUNC_AXR13_GPIO 0x00000001u + + #define _MCASP_PFUNC_AXR14_MASK 0x00004000u + #define _MCASP_PFUNC_AXR14_SHIFT 0x0000000Eu + #define MCASP_PFUNC_AXR14_DEFAULT 0x00000000u + #define MCASP_PFUNC_AXR14_OF(x) _VALUEOF(x) + #define MCASP_PFUNC_AXR14_MCASP 0x00000000u + #define MCASP_PFUNC_AXR14_GPIO 0x00000001u + + #define _MCASP_PFUNC_AXR15_MASK 0x00008000u + #define _MCASP_PFUNC_AXR15_SHIFT 0x0000000Fu + #define MCASP_PFUNC_AXR15_DEFAULT 0x00000000u + #define MCASP_PFUNC_AXR15_OF(x) _VALUEOF(x) + #define MCASP_PFUNC_AXR15_MCASP 0x00000000u + #define MCASP_PFUNC_AXR15_GPIO 0x00000001u +#endif /* _MCASP_CHANNEL_CNT == 16 */ + + #define _MCASP_PFUNC_AMUTE_MASK 0x02000000u + #define _MCASP_PFUNC_AMUTE_SHIFT 0x00000019u + #define MCASP_PFUNC_AMUTE_DEFAULT 0x00000000u + #define MCASP_PFUNC_AMUTE_OF(x) _VALUEOF(x) + #define MCASP_PFUNC_AMUTE_MCASP 0x00000000u + #define MCASP_PFUNC_AMUTE_GPIO 0x00000001u + + #define _MCASP_PFUNC_ACLKX_MASK 0x04000000u + #define _MCASP_PFUNC_ACLKX_SHIFT 0x0000001Au + #define MCASP_PFUNC_ACLKX_DEFAULT 0x00000000u + #define MCASP_PFUNC_ACLKX_OF(x) _VALUEOF(x) + #define MCASP_PFUNC_ACLKX_MCASP 0x00000000u + #define MCASP_PFUNC_ACLKX_GPIO 0x00000001u + + #define _MCASP_PFUNC_AHCLKX_MASK 0x08000000u + #define _MCASP_PFUNC_AHCLKX_SHIFT 0x0000001Bu + #define MCASP_PFUNC_AHCLKX_DEFAULT 0x00000000u + #define MCASP_PFUNC_AHCLKX_OF(x) _VALUEOF(x) + #define MCASP_PFUNC_AHCLKX_MCASP 0x00000000u + #define MCASP_PFUNC_AHCLKX_GPIO 0x00000001u + + #define _MCASP_PFUNC_AFSX_MASK 0x10000000u + #define _MCASP_PFUNC_AFSX_SHIFT 0x0000001Cu + #define MCASP_PFUNC_AFSX_DEFAULT 0x00000000u + #define MCASP_PFUNC_AFSX_OF(x) _VALUEOF(x) + #define MCASP_PFUNC_AFSX_MCASP 0x00000000u + #define MCASP_PFUNC_AFSX_GPIO 0x00000001u + + #define _MCASP_PFUNC_ACLKR_MASK 0x20000000u + #define _MCASP_PFUNC_ACLKR_SHIFT 0x0000001Du + #define MCASP_PFUNC_ACLKR_DEFAULT 0x00000000u + #define MCASP_PFUNC_ACLKR_OF(x) _VALUEOF(x) + #define MCASP_PFUNC_ACLKR_MCASP 0x00000000u + #define MCASP_PFUNC_ACLKR_GPIO 0x00000001u + + #define _MCASP_PFUNC_AHCLKR_MASK 0x40000000u + #define _MCASP_PFUNC_AHCLKR_SHIFT 0x0000001Eu + #define MCASP_PFUNC_AHCLKR_DEFAULT 0x00000000u + #define MCASP_PFUNC_AHCLKR_OF(x) _VALUEOF(x) + #define MCASP_PFUNC_AHCLKR_MCASP 0x00000000u + #define MCASP_PFUNC_AHCLKR_GPIO 0x00000001u + + #define _MCASP_PFUNC_AFSR_MASK 0x80000000u + #define _MCASP_PFUNC_AFSR_SHIFT 0x0000001Fu + #define MCASP_PFUNC_AFSR_DEFAULT 0x00000000u + #define MCASP_PFUNC_AFSR_OF(x) _VALUEOF(x) + #define MCASP_PFUNC_AFSR_MCASP 0x00000000u + #define MCASP_PFUNC_AFSR_GPIO 0x00000001u + + + #define MCASP_PFUNC_OF(x) _VALUEOF(x) + +#if (_MCASP_CHANNEL_CNT == 16) + #define MCASP_PFUNC_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,PFUNC,AXR0)\ + |_PER_FDEFAULT(MCASP,PFUNC,AXR1)\ + |_PER_FDEFAULT(MCASP,PFUNC,AXR2)\ + |_PER_FDEFAULT(MCASP,PFUNC,AXR3)\ + |_PER_FDEFAULT(MCASP,PFUNC,AXR4)\ + |_PER_FDEFAULT(MCASP,PFUNC,AXR5)\ + |_PER_FDEFAULT(MCASP,PFUNC,AXR6)\ + |_PER_FDEFAULT(MCASP,PFUNC,AXR7)\ + |_PER_FDEFAULT(MCASP,PFUNC,AXR8)\ + |_PER_FDEFAULT(MCASP,PFUNC,AXR9)\ + |_PER_FDEFAULT(MCASP,PFUNC,AXR10)\ + |_PER_FDEFAULT(MCASP,PFUNC,AXR11)\ + |_PER_FDEFAULT(MCASP,PFUNC,AXR12)\ + |_PER_FDEFAULT(MCASP,PFUNC,AXR13)\ + |_PER_FDEFAULT(MCASP,PFUNC,AXR14)\ + |_PER_FDEFAULT(MCASP,PFUNC,AXR15)\ + |_PER_FDEFAULT(MCASP,PFUNC,AMUTE)\ + |_PER_FDEFAULT(MCASP,PFUNC,ACLKX)\ + |_PER_FDEFAULT(MCASP,PFUNC,AHCLKX)\ + |_PER_FDEFAULT(MCASP,PFUNC,AFSX)\ + |_PER_FDEFAULT(MCASP,PFUNC,ACLKR)\ + |_PER_FDEFAULT(MCASP,PFUNC,AHCLKR)\ + |_PER_FDEFAULT(MCASP,PFUNC,AFSR)\ + ) + + #define MCASP_PFUNC_RMK(afsr,ahclkr,aclkr,afsx,ahclkx,aclkx,amute, \ + axr15,axr14,axr13,axr12,axr11,axr10,\ + axr9, axr8,axr7,axr6,axr5,axr4,axr3,axr2,axr1, axr0) \ + (Uint32)( \ + _PER_FMK(MCASP,PFUNC,AXR0,axr0)\ + |_PER_FMK(MCASP,PFUNC,AXR1,axr1)\ + |_PER_FMK(MCASP,PFUNC,AXR2,axr2)\ + |_PER_FMK(MCASP,PFUNC,AXR3,axr3)\ + |_PER_FMK(MCASP,PFUNC,AXR4,axr4)\ + |_PER_FMK(MCASP,PFUNC,AXR5,axr5)\ + |_PER_FMK(MCASP,PFUNC,AXR6,axr6)\ + |_PER_FMK(MCASP,PFUNC,AXR7,axr7)\ + |_PER_FMK(MCASP,PFUNC,AXR8,axr8)\ + |_PER_FMK(MCASP,PFUNC,AXR9,axr9)\ + |_PER_FMK(MCASP,PFUNC,AXR10,axr10)\ + |_PER_FMK(MCASP,PFUNC,AXR11,axr11)\ + |_PER_FMK(MCASP,PFUNC,AXR12,axr12)\ + |_PER_FMK(MCASP,PFUNC,AXR13,axr13)\ + |_PER_FMK(MCASP,PFUNC,AXR14,axr14)\ + |_PER_FMK(MCASP,PFUNC,AXR15,axr15)\ + |_PER_FMK(MCASP,PFUNC,AMUTE,amute)\ + |_PER_FMK(MCASP,PFUNC,ACLKX,aclkx)\ + |_PER_FMK(MCASP,PFUNC,AHCLKX,ahclkx)\ + |_PER_FMK(MCASP,PFUNC,AFSX,afsx)\ + |_PER_FMK(MCASP,PFUNC,ACLKR,aclkr)\ + |_PER_FMK(MCASP,PFUNC,AHCLKR,ahclkr)\ + |_PER_FMK(MCASP,PFUNC,AFSR,afsr)\ + ) +#endif /* (_MCASP_CHANNEL_CNT == 16) */ + +#if (_MCASP_CHANNEL_CNT == 8) + #define MCASP_PFUNC_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,PFUNC,AXR0)\ + |_PER_FDEFAULT(MCASP,PFUNC,AXR1)\ + |_PER_FDEFAULT(MCASP,PFUNC,AXR2)\ + |_PER_FDEFAULT(MCASP,PFUNC,AXR3)\ + |_PER_FDEFAULT(MCASP,PFUNC,AXR4)\ + |_PER_FDEFAULT(MCASP,PFUNC,AXR5)\ + |_PER_FDEFAULT(MCASP,PFUNC,AXR6)\ + |_PER_FDEFAULT(MCASP,PFUNC,AXR7)\ + |_PER_FDEFAULT(MCASP,PFUNC,AMUTE)\ + |_PER_FDEFAULT(MCASP,PFUNC,ACLKX)\ + |_PER_FDEFAULT(MCASP,PFUNC,AHCLKX)\ + |_PER_FDEFAULT(MCASP,PFUNC,AFSX)\ + |_PER_FDEFAULT(MCASP,PFUNC,ACLKR)\ + |_PER_FDEFAULT(MCASP,PFUNC,AHCLKR)\ + |_PER_FDEFAULT(MCASP,PFUNC,AFSR)\ + ) + + #define MCASP_PFUNC_RMK(afsr,ahclkr,aclkr,afsx,ahclkx,aclkx,amute, \ + axr7,axr6,axr5,axr4,axr3,axr2,axr1, axr0) \ + (Uint32)( \ + _PER_FMK(MCASP,PFUNC,AXR0,axr0)\ + |_PER_FMK(MCASP,PFUNC,AXR1,axr1)\ + |_PER_FMK(MCASP,PFUNC,AXR2,axr2)\ + |_PER_FMK(MCASP,PFUNC,AXR3,axr3)\ + |_PER_FMK(MCASP,PFUNC,AXR4,axr4)\ + |_PER_FMK(MCASP,PFUNC,AXR5,axr5)\ + |_PER_FMK(MCASP,PFUNC,AXR6,axr6)\ + |_PER_FMK(MCASP,PFUNC,AXR7,axr7)\ + |_PER_FMK(MCASP,PFUNC,AMUTE,amute)\ + |_PER_FMK(MCASP,PFUNC,ACLKX,aclkx)\ + |_PER_FMK(MCASP,PFUNC,AHCLKX,ahclkx)\ + |_PER_FMK(MCASP,PFUNC,AFSX,afsx)\ + |_PER_FMK(MCASP,PFUNC,ACLKR,aclkr)\ + |_PER_FMK(MCASP,PFUNC,AHCLKR,ahclkr)\ + |_PER_FMK(MCASP,PFUNC,AFSR,afsr)\ + ) +#endif /* (_MCASP_CHANNEL_CNT == 8) */ + +#if (_MCASP_CHANNEL_CNT == 6) + #define MCASP_PFUNC_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,PFUNC,AXR0)\ + |_PER_FDEFAULT(MCASP,PFUNC,AXR1)\ + |_PER_FDEFAULT(MCASP,PFUNC,AXR2)\ + |_PER_FDEFAULT(MCASP,PFUNC,AXR3)\ + |_PER_FDEFAULT(MCASP,PFUNC,AXR4)\ + |_PER_FDEFAULT(MCASP,PFUNC,AXR5)\ + |_PER_FDEFAULT(MCASP,PFUNC,AMUTE)\ + |_PER_FDEFAULT(MCASP,PFUNC,ACLKX)\ + |_PER_FDEFAULT(MCASP,PFUNC,AHCLKX)\ + |_PER_FDEFAULT(MCASP,PFUNC,AFSX)\ + |_PER_FDEFAULT(MCASP,PFUNC,ACLKR)\ + |_PER_FDEFAULT(MCASP,PFUNC,AHCLKR)\ + |_PER_FDEFAULT(MCASP,PFUNC,AFSR)\ + ) + + #define MCASP_PFUNC_RMK(afsr,ahclkr,aclkr,afsx,ahclkx,aclkx,amute, \ + axr5,axr4,axr3,axr2,axr1, axr0) \ + (Uint32)( \ + _PER_FMK(MCASP,PFUNC,AXR0,axr0)\ + |_PER_FMK(MCASP,PFUNC,AXR1,axr1)\ + |_PER_FMK(MCASP,PFUNC,AXR2,axr2)\ + |_PER_FMK(MCASP,PFUNC,AXR3,axr3)\ + |_PER_FMK(MCASP,PFUNC,AXR4,axr4)\ + |_PER_FMK(MCASP,PFUNC,AXR5,axr5)\ + |_PER_FMK(MCASP,PFUNC,AMUTE,amute)\ + |_PER_FMK(MCASP,PFUNC,ACLKX,aclkx)\ + |_PER_FMK(MCASP,PFUNC,AHCLKX,ahclkx)\ + |_PER_FMK(MCASP,PFUNC,AFSX,afsx)\ + |_PER_FMK(MCASP,PFUNC,ACLKR,aclkr)\ + |_PER_FMK(MCASP,PFUNC,AHCLKR,ahclkr)\ + |_PER_FMK(MCASP,PFUNC,AFSR,afsr)\ + ) +#endif /* (_MCASP_CHANNEL_CNT == 6) */ + +#if (_MCASP_CHANNEL_CNT == 4) + #define MCASP_PFUNC_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,PFUNC,AXR0)\ + |_PER_FDEFAULT(MCASP,PFUNC,AXR1)\ + |_PER_FDEFAULT(MCASP,PFUNC,AXR2)\ + |_PER_FDEFAULT(MCASP,PFUNC,AXR3)\ + |_PER_FDEFAULT(MCASP,PFUNC,AMUTE)\ + |_PER_FDEFAULT(MCASP,PFUNC,ACLKX)\ + |_PER_FDEFAULT(MCASP,PFUNC,AHCLKX)\ + |_PER_FDEFAULT(MCASP,PFUNC,AFSX)\ + |_PER_FDEFAULT(MCASP,PFUNC,ACLKR)\ + |_PER_FDEFAULT(MCASP,PFUNC,AHCLKR)\ + |_PER_FDEFAULT(MCASP,PFUNC,AFSR)\ + ) + + #define MCASP_PFUNC_RMK(afsr,ahclkr,aclkr,afsx,ahclkx,aclkx,amute, \ + axr3,axr2,axr1, axr0) \ + (Uint32)( \ + _PER_FMK(MCASP,PFUNC,AXR0,axr0)\ + |_PER_FMK(MCASP,PFUNC,AXR1,axr1)\ + |_PER_FMK(MCASP,PFUNC,AXR2,axr2)\ + |_PER_FMK(MCASP,PFUNC,AXR3,axr3)\ + |_PER_FMK(MCASP,PFUNC,AMUTE,amute)\ + |_PER_FMK(MCASP,PFUNC,ACLKX,aclkx)\ + |_PER_FMK(MCASP,PFUNC,AHCLKX,ahclkx)\ + |_PER_FMK(MCASP,PFUNC,AFSX,afsx)\ + |_PER_FMK(MCASP,PFUNC,ACLKR,aclkr)\ + |_PER_FMK(MCASP,PFUNC,AHCLKR,ahclkr)\ + |_PER_FMK(MCASP,PFUNC,AFSR,afsr)\ + ) +#endif /* (_MCASP_CHANNEL_CNT == 4) */ + + + #define _MCASP_PFUNC_FGET(N,FIELD)\ + _PER_FGET(_MCASP_PFUNC##N##_ADDR,MCASP,PFUNC,##FIELD) + + #define _MCASP_PFUNC_FSET(N,FIELD,field)\ + _PER_FSET(_MCASP_PFUNC##N##_ADDR,MCASP,PFUNC,##FIELD,field) + + #define _MCASP_PFUNC_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCASP_PFUNC##N##_ADDR,MCASP,PFUNC,##FIELD,##SYM) + + #define _MCASP_PFUNC0_FGET(FIELD) _MCASP_PFUNC_FGET(0,##FIELD) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_PFUNC1_FGET(FIELD) _MCASP_PFUNC_FGET(1,##FIELD) +#endif + + #define _MCASP_PFUNC0_FSET(FIELD,f) _MCASP_PFUNC_FSET(0,##FIELD,f) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_PFUNC1_FSET(FIELD,f) _MCASP_PFUNC_FSET(1,##FIELD,f) +#endif + + #define _MCASP_PFUNC0_FSETS(FIELD,SYM) _MCASP_PFUNC_FSETS(0,##FIELD,##SYM) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_PFUNC1_FSETS(FIELD,SYM) _MCASP_PFUNC_FSETS(1,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* Step 4.5 +* _____________________ +* | | +* | PDIR | +* |___________________| +* +* PDIR - Pin Direction Register +* +* FIELDS (msb -> lsb) +* (rw) AFSR +* (rw) AHCLKR +* (rw) ACLKR +* (rw) AFSX +* (rw) AHCLKX +* (rw) ACLKX +* (rw) AMUTE +* (rw) AXR0-15 +* +\******************************************************************************/ + + #define _MCASP_PDIR_OFFSET 5 + + #define _MCASP_PDIR0_ADDR (_MCASP_BASE_PORT0+4*_MCASP_PDIR_OFFSET) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_PDIR1_ADDR (_MCASP_BASE_PORT1+4*_MCASP_PDIR_OFFSET) +#endif + + #define _MCASP_PDIR_AXR0_MASK 0x00000001u + #define _MCASP_PDIR_AXR0_SHIFT 0x00000000u + #define MCASP_PDIR_AXR0_DEFAULT 0x00000000u + #define MCASP_PDIR_AXR0_OF(x) _VALUEOF(x) + #define MCASP_PDIR_AXR0_IN 0x00000000u + #define MCASP_PDIR_AXR0_OUT 0x00000001u + + #define _MCASP_PDIR_AXR1_MASK 0x00000002u + #define _MCASP_PDIR_AXR1_SHIFT 0x00000001u + #define MCASP_PDIR_AXR1_DEFAULT 0x00000000u + #define MCASP_PDIR_AXR1_OF(x) _VALUEOF(x) + #define MCASP_PDIR_AXR1_IN 0x00000000u + #define MCASP_PDIR_AXR1_OUT 0x00000001u + + #define _MCASP_PDIR_AXR2_MASK 0x00000004u + #define _MCASP_PDIR_AXR2_SHIFT 0x00000002u + #define MCASP_PDIR_AXR2_DEFAULT 0x00000000u + #define MCASP_PDIR_AXR2_OF(x) _VALUEOF(x) + #define MCASP_PDIR_AXR2_IN 0x00000000u + #define MCASP_PDIR_AXR2_OUT 0x00000001u + + #define _MCASP_PDIR_AXR3_MASK 0x00000008u + #define _MCASP_PDIR_AXR3_SHIFT 0x00000003u + #define MCASP_PDIR_AXR3_DEFAULT 0x00000000u + #define MCASP_PDIR_AXR3_OF(x) _VALUEOF(x) + #define MCASP_PDIR_AXR3_IN 0x00000000u + #define MCASP_PDIR_AXR3_OUT 0x00000001u + /* Fields for _MCASP_CHANNEL_CNT == 4 end here*/ + +#if (_MCASP_CHANNEL_CNT > 4) + #define _MCASP_PDIR_AXR4_MASK 0x00000010u + #define _MCASP_PDIR_AXR4_SHIFT 0x00000004u + #define MCASP_PDIR_AXR4_DEFAULT 0x00000000u + #define MCASP_PDIR_AXR4_OF(x) _VALUEOF(x) + #define MCASP_PDIR_AXR4_IN 0x00000000u + #define MCASP_PDIR_AXR4_OUT 0x00000001u + + #define _MCASP_PDIR_AXR5_MASK 0x00000020u + #define _MCASP_PDIR_AXR5_SHIFT 0x00000005u + #define MCASP_PDIR_AXR5_DEFAULT 0x00000000u + #define MCASP_PDIR_AXR5_OF(x) _VALUEOF(x) + #define MCASP_PDIR_AXR5_IN 0x00000000u + #define MCASP_PDIR_AXR5_OUT 0x00000001u +#endif /* _MCASP_CHANNEL_CNT == 6 */ + +#if (_MCASP_CHANNEL_CNT > 6) /* For channel count 8 and 16 */ + #define _MCASP_PDIR_AXR6_MASK 0x00000040u + #define _MCASP_PDIR_AXR6_SHIFT 0x00000006u + #define MCASP_PDIR_AXR6_DEFAULT 0x00000000u + #define MCASP_PDIR_AXR6_OF(x) _VALUEOF(x) + #define MCASP_PDIR_AXR6_IN 0x00000000u + #define MCASP_PDIR_AXR6_OUT 0x00000001u + + #define _MCASP_PDIR_AXR7_MASK 0x00000080u + #define _MCASP_PDIR_AXR7_SHIFT 0x00000007u + #define MCASP_PDIR_AXR7_DEFAULT 0x00000000u + #define MCASP_PDIR_AXR7_OF(x) _VALUEOF(x) + #define MCASP_PDIR_AXR7_IN 0x00000000u + #define MCASP_PDIR_AXR7_OUT 0x00000001u +#endif /* _MCASP_CHANNEL_CNT == 8 */ + +#if (_MCASP_CHANNEL_CNT == 16) + #define _MCASP_PDIR_AXR8_MASK 0x00000100u + #define _MCASP_PDIR_AXR8_SHIFT 0x00000008u + #define MCASP_PDIR_AXR8_DEFAULT 0x00000000u + #define MCASP_PDIR_AXR8_OF(x) _VALUEOF(x) + #define MCASP_PDIR_AXR8_IN 0x00000000u + #define MCASP_PDIR_AXR8_OUT 0x00000001u + + #define _MCASP_PDIR_AXR9_MASK 0x00000200u + #define _MCASP_PDIR_AXR9_SHIFT 0x00000009u + #define MCASP_PDIR_AXR9_DEFAULT 0x00000000u + #define MCASP_PDIR_AXR9_OF(x) _VALUEOF(x) + #define MCASP_PDIR_AXR9_IN 0x00000000u + #define MCASP_PDIR_AXR9_OUT 0x00000001u + + #define _MCASP_PDIR_AXR10_MASK 0x00000400u + #define _MCASP_PDIR_AXR10_SHIFT 0x0000000Au + #define MCASP_PDIR_AXR10_DEFAULT 0x00000000u + #define MCASP_PDIR_AXR10_OF(x) _VALUEOF(x) + #define MCASP_PDIR_AXR10_IN 0x00000000u + #define MCASP_PDIR_AXR10_OUT 0x00000001u + + #define _MCASP_PDIR_AXR11_MASK 0x00000800u + #define _MCASP_PDIR_AXR11_SHIFT 0x0000000Bu + #define MCASP_PDIR_AXR11_DEFAULT 0x00000000u + #define MCASP_PDIR_AXR11_OF(x) _VALUEOF(x) + #define MCASP_PDIR_AXR11_IN 0x00000000u + #define MCASP_PDIR_AXR11_OUT 0x00000001u + + #define _MCASP_PDIR_AXR12_MASK 0x00001000u + #define _MCASP_PDIR_AXR12_SHIFT 0x0000000Cu + #define MCASP_PDIR_AXR12_DEFAULT 0x00000000u + #define MCASP_PDIR_AXR12_OF(x) _VALUEOF(x) + #define MCASP_PDIR_AXR12_IN 0x00000000u + #define MCASP_PDIR_AXR12_OUT 0x00000001u + + #define _MCASP_PDIR_AXR13_MASK 0x00002000u + #define _MCASP_PDIR_AXR13_SHIFT 0x0000000Du + #define MCASP_PDIR_AXR13_DEFAULT 0x00000000u + #define MCASP_PDIR_AXR13_OF(x) _VALUEOF(x) + #define MCASP_PDIR_AXR13_IN 0x00000000u + #define MCASP_PDIR_AXR13_OUT 0x00000001u + + #define _MCASP_PDIR_AXR14_MASK 0x00004000u + #define _MCASP_PDIR_AXR14_SHIFT 0x0000000Eu + #define MCASP_PDIR_AXR14_DEFAULT 0x00000000u + #define MCASP_PDIR_AXR14_OF(x) _VALUEOF(x) + #define MCASP_PDIR_AXR14_IN 0x00000000u + #define MCASP_PDIR_AXR14_OUT 0x00000001u + + #define _MCASP_PDIR_AXR15_MASK 0x00008000u + #define _MCASP_PDIR_AXR15_SHIFT 0x0000000Fu + #define MCASP_PDIR_AXR15_DEFAULT 0x00000000u + #define MCASP_PDIR_AXR15_OF(x) _VALUEOF(x) + #define MCASP_PDIR_AXR15_IN 0x00000000u + #define MCASP_PDIR_AXR15_OUT 0x00000001u +#endif /* _MCASP_CHANNEL_CNT == 16 */ + + #define _MCASP_PDIR_AMUTE_MASK 0x02000000u + #define _MCASP_PDIR_AMUTE_SHIFT 0x00000019u + #define MCASP_PDIR_AMUTE_DEFAULT 0x00000000u + #define MCASP_PDIR_AMUTE_OF(x) _VALUEOF(x) + #define MCASP_PDIR_AMUTE_IN 0x00000000u + #define MCASP_PDIR_AMUTE_OUT 0x00000001u + + #define _MCASP_PDIR_ACLKX_MASK 0x04000000u + #define _MCASP_PDIR_ACLKX_SHIFT 0x0000001Au + #define MCASP_PDIR_ACLKX_DEFAULT 0x00000000u + #define MCASP_PDIR_ACLKX_OF(x) _VALUEOF(x) + #define MCASP_PDIR_ACLKX_IN 0x00000000u + #define MCASP_PDIR_ACLKX_OUT 0x00000001u + + #define _MCASP_PDIR_AHCLKX_MASK 0x08000000u + #define _MCASP_PDIR_AHCLKX_SHIFT 0x0000001Bu + #define MCASP_PDIR_AHCLKX_DEFAULT 0x00000000u + #define MCASP_PDIR_AHCLKX_OF(x) _VALUEOF(x) + #define MCASP_PDIR_AHCLKX_IN 0x00000000u + #define MCASP_PDIR_AHCLKX_OUT 0x00000001u + + #define _MCASP_PDIR_AFSX_MASK 0x10000000u + #define _MCASP_PDIR_AFSX_SHIFT 0x0000001Cu + #define MCASP_PDIR_AFSX_DEFAULT 0x00000000u + #define MCASP_PDIR_AFSX_OF(x) _VALUEOF(x) + #define MCASP_PDIR_AFSX_IN 0x00000000u + #define MCASP_PDIR_AFSX_OUT 0x00000001u + + #define _MCASP_PDIR_ACLKR_MASK 0x20000000u + #define _MCASP_PDIR_ACLKR_SHIFT 0x0000001Du + #define MCASP_PDIR_ACLKR_DEFAULT 0x00000000u + #define MCASP_PDIR_ACLKR_OF(x) _VALUEOF(x) + #define MCASP_PDIR_ACLKR_IN 0x00000000u + #define MCASP_PDIR_ACLKR_OUT 0x00000001u + + #define _MCASP_PDIR_AHCLKR_MASK 0x40000000u + #define _MCASP_PDIR_AHCLKR_SHIFT 0x0000001Eu + #define MCASP_PDIR_AHCLKR_DEFAULT 0x00000000u + #define MCASP_PDIR_AHCLKR_OF(x) _VALUEOF(x) + #define MCASP_PDIR_AHCLKR_IN 0x00000000u + #define MCASP_PDIR_AHCLKR_OUT 0x00000001u + + #define _MCASP_PDIR_AFSR_MASK 0x80000000u + #define _MCASP_PDIR_AFSR_SHIFT 0x0000001Fu + #define MCASP_PDIR_AFSR_DEFAULT 0x00000000u + #define MCASP_PDIR_AFSR_OF(x) _VALUEOF(x) + #define MCASP_PDIR_AFSR_IN 0x00000000u + #define MCASP_PDIR_AFSR_OUT 0x00000001u + + #define MCASP_PDIR_OF(x) _VALUEOF(x) + +#if (_MCASP_CHANNEL_CNT == 16) + #define MCASP_PDIR_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,PDIR,AXR0)\ + |_PER_FDEFAULT(MCASP,PDIR,AXR1)\ + |_PER_FDEFAULT(MCASP,PDIR,AXR2)\ + |_PER_FDEFAULT(MCASP,PDIR,AXR3)\ + |_PER_FDEFAULT(MCASP,PDIR,AXR4)\ + |_PER_FDEFAULT(MCASP,PDIR,AXR5)\ + |_PER_FDEFAULT(MCASP,PDIR,AXR6)\ + |_PER_FDEFAULT(MCASP,PDIR,AXR7)\ + |_PER_FDEFAULT(MCASP,PDIR,AXR8)\ + |_PER_FDEFAULT(MCASP,PDIR,AXR9)\ + |_PER_FDEFAULT(MCASP,PDIR,AXR10)\ + |_PER_FDEFAULT(MCASP,PDIR,AXR11)\ + |_PER_FDEFAULT(MCASP,PDIR,AXR12)\ + |_PER_FDEFAULT(MCASP,PDIR,AXR13)\ + |_PER_FDEFAULT(MCASP,PDIR,AXR14)\ + |_PER_FDEFAULT(MCASP,PDIR,AXR15)\ + |_PER_FDEFAULT(MCASP,PDIR,AMUTE)\ + |_PER_FDEFAULT(MCASP,PDIR,ACLKX)\ + |_PER_FDEFAULT(MCASP,PDIR,AHCLKX)\ + |_PER_FDEFAULT(MCASP,PDIR,AFSX)\ + |_PER_FDEFAULT(MCASP,PDIR,ACLKR)\ + |_PER_FDEFAULT(MCASP,PDIR,AHCLKR)\ + |_PER_FDEFAULT(MCASP,PDIR,AFSR)\ + ) + + #define MCASP_PDIR_RMK(afsr,ahclkr,aclkr,afsx,ahclkx,aclkx,amute, \ + axr15,axr14,axr13,axr12,axr11,axr10,\ + axr9, axr8,axr7,axr6,axr5,axr4,axr3,axr2,axr1, axr0) \ + (Uint32)( \ + _PER_FMK(MCASP,PDIR,AXR0,axr0)\ + |_PER_FMK(MCASP,PDIR,AXR1,axr1)\ + |_PER_FMK(MCASP,PDIR,AXR2,axr2)\ + |_PER_FMK(MCASP,PDIR,AXR3,axr3)\ + |_PER_FMK(MCASP,PDIR,AXR4,axr4)\ + |_PER_FMK(MCASP,PDIR,AXR5,axr5)\ + |_PER_FMK(MCASP,PDIR,AXR6,axr6)\ + |_PER_FMK(MCASP,PDIR,AXR7,axr7)\ + |_PER_FMK(MCASP,PDIR,AXR8,axr8)\ + |_PER_FMK(MCASP,PDIR,AXR9,axr9)\ + |_PER_FMK(MCASP,PDIR,AXR10,axr10)\ + |_PER_FMK(MCASP,PDIR,AXR11,axr11)\ + |_PER_FMK(MCASP,PDIR,AXR12,axr12)\ + |_PER_FMK(MCASP,PDIR,AXR13,axr13)\ + |_PER_FMK(MCASP,PDIR,AXR14,axr14)\ + |_PER_FMK(MCASP,PDIR,AXR15,axr15)\ + |_PER_FMK(MCASP,PDIR,AMUTE,amute)\ + |_PER_FMK(MCASP,PDIR,ACLKX,aclkx)\ + |_PER_FMK(MCASP,PDIR,AHCLKX,ahclkx)\ + |_PER_FMK(MCASP,PDIR,AFSX,afsx)\ + |_PER_FMK(MCASP,PDIR,ACLKR,aclkr)\ + |_PER_FMK(MCASP,PDIR,AHCLKR,ahclkr)\ + |_PER_FMK(MCASP,PDIR,AFSR,afsr)\ + ) +#endif /* _MCASP_CHANNEL_CNT == 16 */ + +#if (_MCASP_CHANNEL_CNT == 8) + #define MCASP_PDIR_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,PDIR,AXR0)\ + |_PER_FDEFAULT(MCASP,PDIR,AXR1)\ + |_PER_FDEFAULT(MCASP,PDIR,AXR2)\ + |_PER_FDEFAULT(MCASP,PDIR,AXR3)\ + |_PER_FDEFAULT(MCASP,PDIR,AXR4)\ + |_PER_FDEFAULT(MCASP,PDIR,AXR5)\ + |_PER_FDEFAULT(MCASP,PDIR,AXR6)\ + |_PER_FDEFAULT(MCASP,PDIR,AXR7)\ + |_PER_FDEFAULT(MCASP,PDIR,AMUTE)\ + |_PER_FDEFAULT(MCASP,PDIR,ACLKX)\ + |_PER_FDEFAULT(MCASP,PDIR,AHCLKX)\ + |_PER_FDEFAULT(MCASP,PDIR,AFSX)\ + |_PER_FDEFAULT(MCASP,PDIR,ACLKR)\ + |_PER_FDEFAULT(MCASP,PDIR,AHCLKR)\ + |_PER_FDEFAULT(MCASP,PDIR,AFSR)\ + ) + + #define MCASP_PDIR_RMK(afsr,ahclkr,aclkr,afsx,ahclkx,aclkx,amute, \ + axr7,axr6,axr5,axr4,axr3,axr2,axr1, axr0) \ + (Uint32)( \ + _PER_FMK(MCASP,PDIR,AXR0,axr0)\ + |_PER_FMK(MCASP,PDIR,AXR1,axr1)\ + |_PER_FMK(MCASP,PDIR,AXR2,axr2)\ + |_PER_FMK(MCASP,PDIR,AXR3,axr3)\ + |_PER_FMK(MCASP,PDIR,AXR4,axr4)\ + |_PER_FMK(MCASP,PDIR,AXR5,axr5)\ + |_PER_FMK(MCASP,PDIR,AXR6,axr6)\ + |_PER_FMK(MCASP,PDIR,AXR7,axr7)\ + |_PER_FMK(MCASP,PDIR,AMUTE,amute)\ + |_PER_FMK(MCASP,PDIR,ACLKX,aclkx)\ + |_PER_FMK(MCASP,PDIR,AHCLKX,ahclkx)\ + |_PER_FMK(MCASP,PDIR,AFSX,afsx)\ + |_PER_FMK(MCASP,PDIR,ACLKR,aclkr)\ + |_PER_FMK(MCASP,PDIR,AHCLKR,ahclkr)\ + |_PER_FMK(MCASP,PDIR,AFSR,afsr)\ + ) +#endif /* _MCASP_CHANNEL_CNT == 8 */ + +#if (_MCASP_CHANNEL_CNT == 6) + #define MCASP_PDIR_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,PDIR,AXR0)\ + |_PER_FDEFAULT(MCASP,PDIR,AXR1)\ + |_PER_FDEFAULT(MCASP,PDIR,AXR2)\ + |_PER_FDEFAULT(MCASP,PDIR,AXR3)\ + |_PER_FDEFAULT(MCASP,PDIR,AXR4)\ + |_PER_FDEFAULT(MCASP,PDIR,AXR5)\ + |_PER_FDEFAULT(MCASP,PDIR,AMUTE)\ + |_PER_FDEFAULT(MCASP,PDIR,ACLKX)\ + |_PER_FDEFAULT(MCASP,PDIR,AHCLKX)\ + |_PER_FDEFAULT(MCASP,PDIR,AFSX)\ + |_PER_FDEFAULT(MCASP,PDIR,ACLKR)\ + |_PER_FDEFAULT(MCASP,PDIR,AHCLKR)\ + |_PER_FDEFAULT(MCASP,PDIR,AFSR)\ + ) + + #define MCASP_PDIR_RMK(afsr,ahclkr,aclkr,afsx,ahclkx,aclkx,amute, \ + axr5,axr4,axr3,axr2,axr1, axr0) \ + (Uint32)( \ + _PER_FMK(MCASP,PDIR,AXR0,axr0)\ + |_PER_FMK(MCASP,PDIR,AXR1,axr1)\ + |_PER_FMK(MCASP,PDIR,AXR2,axr2)\ + |_PER_FMK(MCASP,PDIR,AXR3,axr3)\ + |_PER_FMK(MCASP,PDIR,AXR4,axr4)\ + |_PER_FMK(MCASP,PDIR,AXR5,axr5)\ + |_PER_FMK(MCASP,PDIR,AMUTE,amute)\ + |_PER_FMK(MCASP,PDIR,ACLKX,aclkx)\ + |_PER_FMK(MCASP,PDIR,AHCLKX,ahclkx)\ + |_PER_FMK(MCASP,PDIR,AFSX,afsx)\ + |_PER_FMK(MCASP,PDIR,ACLKR,aclkr)\ + |_PER_FMK(MCASP,PDIR,AHCLKR,ahclkr)\ + |_PER_FMK(MCASP,PDIR,AFSR,afsr)\ + ) +#endif /* _MCASP_CHANNEL_CNT == 6 */ + +#if (_MCASP_CHANNEL_CNT == 4) + #define MCASP_PDIR_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,PDIR,AXR0)\ + |_PER_FDEFAULT(MCASP,PDIR,AXR1)\ + |_PER_FDEFAULT(MCASP,PDIR,AXR2)\ + |_PER_FDEFAULT(MCASP,PDIR,AXR3)\ + |_PER_FDEFAULT(MCASP,PDIR,AMUTE)\ + |_PER_FDEFAULT(MCASP,PDIR,ACLKX)\ + |_PER_FDEFAULT(MCASP,PDIR,AHCLKX)\ + |_PER_FDEFAULT(MCASP,PDIR,AFSX)\ + |_PER_FDEFAULT(MCASP,PDIR,ACLKR)\ + |_PER_FDEFAULT(MCASP,PDIR,AHCLKR)\ + |_PER_FDEFAULT(MCASP,PDIR,AFSR)\ + ) + + #define MCASP_PDIR_RMK(afsr,ahclkr,aclkr,afsx,ahclkx,aclkx,amute, \ + axr3,axr2,axr1, axr0) \ + (Uint32)( \ + _PER_FMK(MCASP,PDIR,AXR0,axr0)\ + |_PER_FMK(MCASP,PDIR,AXR1,axr1)\ + |_PER_FMK(MCASP,PDIR,AXR2,axr2)\ + |_PER_FMK(MCASP,PDIR,AXR3,axr3)\ + |_PER_FMK(MCASP,PDIR,AMUTE,amute)\ + |_PER_FMK(MCASP,PDIR,ACLKX,aclkx)\ + |_PER_FMK(MCASP,PDIR,AHCLKX,ahclkx)\ + |_PER_FMK(MCASP,PDIR,AFSX,afsx)\ + |_PER_FMK(MCASP,PDIR,ACLKR,aclkr)\ + |_PER_FMK(MCASP,PDIR,AHCLKR,ahclkr)\ + |_PER_FMK(MCASP,PDIR,AFSR,afsr)\ + ) +#endif /* _MCASP_CHANNEL_CNT == 4 */ + + #define _MCASP_PDIR_FGET(N,FIELD)\ + _PER_FGET(_MCASP_PDIR##N##_ADDR,MCASP,PDIR,##FIELD) + + #define _MCASP_PDIR_FSET(N,FIELD,field)\ + _PER_FSET(_MCASP_PDIR##N##_ADDR,MCASP,PDIR,##FIELD,field) + + #define _MCASP_PDIR_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCASP_PDIR##N##_ADDR,MCASP,PDIR,##FIELD,##SYM) + + #define _MCASP_PDIR0_FGET(FIELD) _MCASP_PDIR_FGET(0,##FIELD) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_PDIR1_FGET(FIELD) _MCASP_PDIR_FGET(1,##FIELD) +#endif + + #define _MCASP_PDIR0_FSET(FIELD,f) _MCASP_PDIR_FSET(0,##FIELD,f) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_PDIR1_FSET(FIELD,f) _MCASP_PDIR_FSET(1,##FIELD,f) +#endif + + #define _MCASP_PDIR0_FSETS(FIELD,SYM) _MCASP_PDIR_FSETS(0,##FIELD,##SYM) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_PDIR1_FSETS(FIELD,SYM) _MCASP_PDIR_FSETS(1,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* +* _____________________ +* | | +* | PDOUT | +* |___________________| +* +* PDOUT - Pin Data Output Register +* +* FIELDS (msb -> lsb) +* (rw) AFSR +* (rw) AHCLKR +* (rw) ACLKR +* (rw) AFSX +* (rw) AHCLKX +* (rw) ACLKX +* (rw) AMUTE +* (rw) AXR0-15 +* +\******************************************************************************/ + + #define _MCASP_PDOUT_OFFSET 6 + + #define _MCASP_PDOUT0_ADDR (_MCASP_BASE_PORT0+4*_MCASP_PDOUT_OFFSET) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_PDOUT1_ADDR (_MCASP_BASE_PORT1+4*_MCASP_PDOUT_OFFSET) +#endif + + #define _MCASP_PDOUT_AXR0_MASK 0x00000001u + #define _MCASP_PDOUT_AXR0_SHIFT 0x00000000u + #define MCASP_PDOUT_AXR0_DEFAULT 0x00000000u + #define MCASP_PDOUT_AXR0_OF(x) _VALUEOF(x) + #define MCASP_PDOUT_AXR0_LOW 0x00000000u + #define MCASP_PDOUT_AXR0_HIGH 0x00000001u + + #define _MCASP_PDOUT_AXR1_MASK 0x00000002u + #define _MCASP_PDOUT_AXR1_SHIFT 0x00000001u + #define MCASP_PDOUT_AXR1_DEFAULT 0x00000000u + #define MCASP_PDOUT_AXR1_OF(x) _VALUEOF(x) + #define MCASP_PDOUT_AXR1_LOW 0x00000000u + #define MCASP_PDOUT_AXR1_HIGH 0x00000001u + + #define _MCASP_PDOUT_AXR2_MASK 0x00000004u + #define _MCASP_PDOUT_AXR2_SHIFT 0x00000002u + #define MCASP_PDOUT_AXR2_DEFAULT 0x00000000u + #define MCASP_PDOUT_AXR2_OF(x) _VALUEOF(x) + #define MCASP_PDOUT_AXR2_LOW 0x00000000u + #define MCASP_PDOUT_AXR2_HIGH 0x00000001u + + #define _MCASP_PDOUT_AXR3_MASK 0x00000008u + #define _MCASP_PDOUT_AXR3_SHIFT 0x00000003u + #define MCASP_PDOUT_AXR3_DEFAULT 0x00000000u + #define MCASP_PDOUT_AXR3_OF(x) _VALUEOF(x) + #define MCASP_PDOUT_AXR3_LOW 0x00000000u + #define MCASP_PDOUT_AXR3_HIGH 0x00000001u + /* Fields for _MCASP_CHANNEL_CNT == 4 end here*/ + +#if (_MCASP_CHANNEL_CNT > 4) + #define _MCASP_PDOUT_AXR4_MASK 0x00000010u + #define _MCASP_PDOUT_AXR4_SHIFT 0x00000004u + #define MCASP_PDOUT_AXR4_DEFAULT 0x00000000u + #define MCASP_PDOUT_AXR4_OF(x) _VALUEOF(x) + #define MCASP_PDOUT_AXR4_LOW 0x00000000u + #define MCASP_PDOUT_AXR4_HIGH 0x00000001u + + #define _MCASP_PDOUT_AXR5_MASK 0x00000020u + #define _MCASP_PDOUT_AXR5_SHIFT 0x00000005u + #define MCASP_PDOUT_AXR5_DEFAULT 0x00000000u + #define MCASP_PDOUT_AXR5_OF(x) _VALUEOF(x) + #define MCASP_PDOUT_AXR5_LOW 0x00000000u + #define MCASP_PDOUT_AXR5_HIGH 0x00000001u +#endif /* _MCASP_CHANNEL_CNT == 6 */ + +#if (_MCASP_CHANNEL_CNT > 6) /* For channel count 8 and 16 */ + #define _MCASP_PDOUT_AXR6_MASK 0x00000040u + #define _MCASP_PDOUT_AXR6_SHIFT 0x00000006u + #define MCASP_PDOUT_AXR6_DEFAULT 0x00000000u + #define MCASP_PDOUT_AXR6_OF(x) _VALUEOF(x) + #define MCASP_PDOUT_AXR6_LOW 0x00000000u + #define MCASP_PDOUT_AXR6_HIGH 0x00000001u + + #define _MCASP_PDOUT_AXR7_MASK 0x00000080u + #define _MCASP_PDOUT_AXR7_SHIFT 0x00000007u + #define MCASP_PDOUT_AXR7_DEFAULT 0x00000000u + #define MCASP_PDOUT_AXR7_OF(x) _VALUEOF(x) + #define MCASP_PDOUT_AXR7_LOW 0x00000000u + #define MCASP_PDOUT_AXR7_HIGH 0x00000001u +#endif /* _MCASP_CHANNEL_CNT == 8 */ + +#if (_MCASP_CHANNEL_CNT == 16) + #define _MCASP_PDOUT_AXR8_MASK 0x00000100u + #define _MCASP_PDOUT_AXR8_SHIFT 0x00000008u + #define MCASP_PDOUT_AXR8_DEFAULT 0x00000000u + #define MCASP_PDOUT_AXR8_OF(x) _VALUEOF(x) + #define MCASP_PDOUT_AXR8_LOW 0x00000000u + #define MCASP_PDOUT_AXR8_HIGH 0x00000001u + + #define _MCASP_PDOUT_AXR9_MASK 0x00000200u + #define _MCASP_PDOUT_AXR9_SHIFT 0x00000009u + #define MCASP_PDOUT_AXR9_DEFAULT 0x00000000u + #define MCASP_PDOUT_AXR9_OF(x) _VALUEOF(x) + #define MCASP_PDOUT_AXR9_LOW 0x00000000u + #define MCASP_PDOUT_AXR9_HIGH 0x00000001u + + #define _MCASP_PDOUT_AXR10_MASK 0x00000400u + #define _MCASP_PDOUT_AXR10_SHIFT 0x0000000Au + #define MCASP_PDOUT_AXR10_DEFAULT 0x00000000u + #define MCASP_PDOUT_AXR10_OF(x) _VALUEOF(x) + #define MCASP_PDOUT_AXR10_LOW 0x00000000u + #define MCASP_PDOUT_AXR10_HIGH 0x00000001u + + #define _MCASP_PDOUT_AXR11_MASK 0x00000800u + #define _MCASP_PDOUT_AXR11_SHIFT 0x0000000Bu + #define MCASP_PDOUT_AXR11_DEFAULT 0x00000000u + #define MCASP_PDOUT_AXR11_OF(x) _VALUEOF(x) + #define MCASP_PDOUT_AXR11_LOW 0x00000000u + #define MCASP_PDOUT_AXR11_HIGH 0x00000001u + + #define _MCASP_PDOUT_AXR12_MASK 0x00001000u + #define _MCASP_PDOUT_AXR12_SHIFT 0x0000000Cu + #define MCASP_PDOUT_AXR12_DEFAULT 0x00000000u + #define MCASP_PDOUT_AXR12_OF(x) _VALUEOF(x) + #define MCASP_PDOUT_AXR12_LOW 0x00000000u + #define MCASP_PDOUT_AXR12_HIGH 0x00000001u + + #define _MCASP_PDOUT_AXR13_MASK 0x00002000u + #define _MCASP_PDOUT_AXR13_SHIFT 0x0000000Du + #define MCASP_PDOUT_AXR13_DEFAULT 0x00000000u + #define MCASP_PDOUT_AXR13_OF(x) _VALUEOF(x) + #define MCASP_PDOUT_AXR13_LOW 0x00000000u + #define MCASP_PDOUT_AXR13_HIGH 0x00000001u + + #define _MCASP_PDOUT_AXR14_MASK 0x00004000u + #define _MCASP_PDOUT_AXR14_SHIFT 0x0000000Eu + #define MCASP_PDOUT_AXR14_DEFAULT 0x00000000u + #define MCASP_PDOUT_AXR14_OF(x) _VALUEOF(x) + #define MCASP_PDOUT_AXR14_LOW 0x00000000u + #define MCASP_PDOUT_AXR14_HIGH 0x00000001u + + #define _MCASP_PDOUT_AXR15_MASK 0x00008000u + #define _MCASP_PDOUT_AXR15_SHIFT 0x0000000Fu + #define MCASP_PDOUT_AXR15_DEFAULT 0x00000000u + #define MCASP_PDOUT_AXR15_OF(x) _VALUEOF(x) + #define MCASP_PDOUT_AXR15_LOW 0x00000000u + #define MCASP_PDOUT_AXR15_HIGH 0x00000001u +#endif /* _MCASP_CHANNEL_CNT == 16 */ + + #define _MCASP_PDOUT_AMUTE_MASK 0x02000000u + #define _MCASP_PDOUT_AMUTE_SHIFT 0x00000019u + #define MCASP_PDOUT_AMUTE_DEFAULT 0x00000000u + #define MCASP_PDOUT_AMUTE_OF(x) _VALUEOF(x) + #define MCASP_PDOUT_AMUTE_LOW 0x00000000u + #define MCASP_PDOUT_AMUTE_HIGH 0x00000001u + + #define _MCASP_PDOUT_ACLKX_MASK 0x04000000u + #define _MCASP_PDOUT_ACLKX_SHIFT 0x0000001Au + #define MCASP_PDOUT_ACLKX_DEFAULT 0x00000000u + #define MCASP_PDOUT_ACLKX_OF(x) _VALUEOF(x) + #define MCASP_PDOUT_ACLKX_LOW 0x00000000u + #define MCASP_PDOUT_ACLKX_HIGH 0x00000001u + + #define _MCASP_PDOUT_AHCLKX_MASK 0x08000000u + #define _MCASP_PDOUT_AHCLKX_SHIFT 0x0000001Bu + #define MCASP_PDOUT_AHCLKX_DEFAULT 0x00000000u + #define MCASP_PDOUT_AHCLKX_OF(x) _VALUEOF(x) + #define MCASP_PDOUT_AHCLKX_LOW 0x00000000u + #define MCASP_PDOUT_AHCLKX_HIGH 0x00000001u + + #define _MCASP_PDOUT_AFSX_MASK 0x10000000u + #define _MCASP_PDOUT_AFSX_SHIFT 0x0000001Cu + #define MCASP_PDOUT_AFSX_DEFAULT 0x00000000u + #define MCASP_PDOUT_AFSX_OF(x) _VALUEOF(x) + #define MCASP_PDOUT_AFSX_LOW 0x00000000u + #define MCASP_PDOUT_AFSX_HIGH 0x00000001u + + #define _MCASP_PDOUT_ACLKR_MASK 0x20000000u + #define _MCASP_PDOUT_ACLKR_SHIFT 0x0000001Du + #define MCASP_PDOUT_ACLKR_DEFAULT 0x00000000u + #define MCASP_PDOUT_ACLKR_OF(x) _VALUEOF(x) + #define MCASP_PDOUT_ACLKR_LOW 0x00000000u + #define MCASP_PDOUT_ACLKR_HIGH 0x00000001u + + #define _MCASP_PDOUT_AHCLKR_MASK 0x40000000u + #define _MCASP_PDOUT_AHCLKR_SHIFT 0x0000001Eu + #define MCASP_PDOUT_AHCLKR_DEFAULT 0x00000000u + #define MCASP_PDOUT_AHCLKR_OF(x) _VALUEOF(x) + #define MCASP_PDOUT_AHCLKR_LOW 0x00000000u + #define MCASP_PDOUT_AHCLKR_HIGH 0x00000001u + + #define _MCASP_PDOUT_AFSR_MASK 0x80000000u + #define _MCASP_PDOUT_AFSR_SHIFT 0x0000001Fu + #define MCASP_PDOUT_AFSR_DEFAULT 0x00000000u + #define MCASP_PDOUT_AFSR_OF(x) _VALUEOF(x) + #define MCASP_PDOUT_AFSR_LOW 0x00000000u + #define MCASP_PDOUT_AFSR_HIGH 0x00000001u + + #define MCASP_PDOUT_OF(x) _VALUEOF(x) + +#if (_MCASP_CHANNEL_CNT == 16) + #define MCASP_PDOUT_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,PDOUT,AXR0)\ + |_PER_FDEFAULT(MCASP,PDOUT,AXR1)\ + |_PER_FDEFAULT(MCASP,PDOUT,AXR2)\ + |_PER_FDEFAULT(MCASP,PDOUT,AXR3)\ + |_PER_FDEFAULT(MCASP,PDOUT,AXR4)\ + |_PER_FDEFAULT(MCASP,PDOUT,AXR5)\ + |_PER_FDEFAULT(MCASP,PDOUT,AXR6)\ + |_PER_FDEFAULT(MCASP,PDOUT,AXR7)\ + |_PER_FDEFAULT(MCASP,PDOUT,AXR8)\ + |_PER_FDEFAULT(MCASP,PDOUT,AXR9)\ + |_PER_FDEFAULT(MCASP,PDOUT,AXR10)\ + |_PER_FDEFAULT(MCASP,PDOUT,AXR11)\ + |_PER_FDEFAULT(MCASP,PDOUT,AXR12)\ + |_PER_FDEFAULT(MCASP,PDOUT,AXR13)\ + |_PER_FDEFAULT(MCASP,PDOUT,AXR14)\ + |_PER_FDEFAULT(MCASP,PDOUT,AXR15)\ + |_PER_FDEFAULT(MCASP,PDOUT,AMUTE)\ + |_PER_FDEFAULT(MCASP,PDOUT,ACLKX)\ + |_PER_FDEFAULT(MCASP,PDOUT,AHCLKX)\ + |_PER_FDEFAULT(MCASP,PDOUT,AFSX)\ + |_PER_FDEFAULT(MCASP,PDOUT,ACLKR)\ + |_PER_FDEFAULT(MCASP,PDOUT,AHCLKR)\ + |_PER_FDEFAULT(MCASP,PDOUT,AFSR)\ + ) + + #define MCASP_PDOUT_RMK(afsr,ahclkr,aclkr,afsx,ahclkx,aclkx,amute, \ + axr15,axr14,axr13,axr12,axr11,axr10,\ + axr9, axr8,axr7,axr6,axr5,axr4,axr3,axr2,axr1, axr0) \ + (Uint32)( \ + _PER_FMK(MCASP,PDOUT,AXR0,axr0)\ + |_PER_FMK(MCASP,PDOUT,AXR1,axr1)\ + |_PER_FMK(MCASP,PDOUT,AXR2,axr2)\ + |_PER_FMK(MCASP,PDOUT,AXR3,axr3)\ + |_PER_FMK(MCASP,PDOUT,AXR4,axr4)\ + |_PER_FMK(MCASP,PDOUT,AXR5,axr5)\ + |_PER_FMK(MCASP,PDOUT,AXR6,axr6)\ + |_PER_FMK(MCASP,PDOUT,AXR7,axr7)\ + |_PER_FMK(MCASP,PDOUT,AXR8,axr8)\ + |_PER_FMK(MCASP,PDOUT,AXR9,axr9)\ + |_PER_FMK(MCASP,PDOUT,AXR10,axr10)\ + |_PER_FMK(MCASP,PDOUT,AXR11,axr11)\ + |_PER_FMK(MCASP,PDOUT,AXR12,axr12)\ + |_PER_FMK(MCASP,PDOUT,AXR13,axr13)\ + |_PER_FMK(MCASP,PDOUT,AXR14,axr14)\ + |_PER_FMK(MCASP,PDOUT,AXR15,axr15)\ + |_PER_FMK(MCASP,PDOUT,AMUTE,amute)\ + |_PER_FMK(MCASP,PDOUT,ACLKX,aclkx)\ + |_PER_FMK(MCASP,PDOUT,AHCLKX,ahclkx)\ + |_PER_FMK(MCASP,PDOUT,AFSX,afsx)\ + |_PER_FMK(MCASP,PDOUT,ACLKR,aclkr)\ + |_PER_FMK(MCASP,PDOUT,AHCLKR,ahclkr)\ + |_PER_FMK(MCASP,PDOUT,AFSR,afsr)\ + ) +#endif /* _MCASP_CHANNEL_CNT == 16 */ + +#if (_MCASP_CHANNEL_CNT == 8) + #define MCASP_PDOUT_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,PDOUT,AXR0)\ + |_PER_FDEFAULT(MCASP,PDOUT,AXR1)\ + |_PER_FDEFAULT(MCASP,PDOUT,AXR2)\ + |_PER_FDEFAULT(MCASP,PDOUT,AXR3)\ + |_PER_FDEFAULT(MCASP,PDOUT,AXR4)\ + |_PER_FDEFAULT(MCASP,PDOUT,AXR5)\ + |_PER_FDEFAULT(MCASP,PDOUT,AXR6)\ + |_PER_FDEFAULT(MCASP,PDOUT,AXR7)\ + |_PER_FDEFAULT(MCASP,PDOUT,AMUTE)\ + |_PER_FDEFAULT(MCASP,PDOUT,ACLKX)\ + |_PER_FDEFAULT(MCASP,PDOUT,AHCLKX)\ + |_PER_FDEFAULT(MCASP,PDOUT,AFSX)\ + |_PER_FDEFAULT(MCASP,PDOUT,ACLKR)\ + |_PER_FDEFAULT(MCASP,PDOUT,AHCLKR)\ + |_PER_FDEFAULT(MCASP,PDOUT,AFSR)\ + ) + + #define MCASP_PDOUT_RMK(afsr,ahclkr,aclkr,afsx,ahclkx,aclkx,amute, \ + axr7,axr6,axr5,axr4,axr3,axr2,axr1, axr0) \ + (Uint32)( \ + _PER_FMK(MCASP,PDOUT,AXR0,axr0)\ + |_PER_FMK(MCASP,PDOUT,AXR1,axr1)\ + |_PER_FMK(MCASP,PDOUT,AXR2,axr2)\ + |_PER_FMK(MCASP,PDOUT,AXR3,axr3)\ + |_PER_FMK(MCASP,PDOUT,AXR4,axr4)\ + |_PER_FMK(MCASP,PDOUT,AXR5,axr5)\ + |_PER_FMK(MCASP,PDOUT,AXR6,axr6)\ + |_PER_FMK(MCASP,PDOUT,AXR7,axr7)\ + |_PER_FMK(MCASP,PDOUT,AMUTE,amute)\ + |_PER_FMK(MCASP,PDOUT,ACLKX,aclkx)\ + |_PER_FMK(MCASP,PDOUT,AHCLKX,ahclkx)\ + |_PER_FMK(MCASP,PDOUT,AFSX,afsx)\ + |_PER_FMK(MCASP,PDOUT,ACLKR,aclkr)\ + |_PER_FMK(MCASP,PDOUT,AHCLKR,ahclkr)\ + |_PER_FMK(MCASP,PDOUT,AFSR,afsr)\ + ) +#endif /* _MCASP_CHANNEL_CNT == 8 */ + +#if (_MCASP_CHANNEL_CNT == 6) + #define MCASP_PDOUT_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,PDOUT,AXR0)\ + |_PER_FDEFAULT(MCASP,PDOUT,AXR1)\ + |_PER_FDEFAULT(MCASP,PDOUT,AXR2)\ + |_PER_FDEFAULT(MCASP,PDOUT,AXR3)\ + |_PER_FDEFAULT(MCASP,PDOUT,AXR4)\ + |_PER_FDEFAULT(MCASP,PDOUT,AXR5)\ + |_PER_FDEFAULT(MCASP,PDOUT,AMUTE)\ + |_PER_FDEFAULT(MCASP,PDOUT,ACLKX)\ + |_PER_FDEFAULT(MCASP,PDOUT,AHCLKX)\ + |_PER_FDEFAULT(MCASP,PDOUT,AFSX)\ + |_PER_FDEFAULT(MCASP,PDOUT,ACLKR)\ + |_PER_FDEFAULT(MCASP,PDOUT,AHCLKR)\ + |_PER_FDEFAULT(MCASP,PDOUT,AFSR)\ + ) + + #define MCASP_PDOUT_RMK(afsr,ahclkr,aclkr,afsx,ahclkx,aclkx,amute, \ + axr5,axr4,axr3,axr2,axr1, axr0) \ + (Uint32)( \ + _PER_FMK(MCASP,PDOUT,AXR0,axr0)\ + |_PER_FMK(MCASP,PDOUT,AXR1,axr1)\ + |_PER_FMK(MCASP,PDOUT,AXR2,axr2)\ + |_PER_FMK(MCASP,PDOUT,AXR3,axr3)\ + |_PER_FMK(MCASP,PDOUT,AXR4,axr4)\ + |_PER_FMK(MCASP,PDOUT,AXR5,axr5)\ + |_PER_FMK(MCASP,PDOUT,AMUTE,amute)\ + |_PER_FMK(MCASP,PDOUT,ACLKX,aclkx)\ + |_PER_FMK(MCASP,PDOUT,AHCLKX,ahclkx)\ + |_PER_FMK(MCASP,PDOUT,AFSX,afsx)\ + |_PER_FMK(MCASP,PDOUT,ACLKR,aclkr)\ + |_PER_FMK(MCASP,PDOUT,AHCLKR,ahclkr)\ + |_PER_FMK(MCASP,PDOUT,AFSR,afsr)\ + ) +#endif /* _MCASP_CHANNEL_CNT == 6 */ + +#if (_MCASP_CHANNEL_CNT == 4) + #define MCASP_PDOUT_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,PDOUT,AXR0)\ + |_PER_FDEFAULT(MCASP,PDOUT,AXR1)\ + |_PER_FDEFAULT(MCASP,PDOUT,AXR2)\ + |_PER_FDEFAULT(MCASP,PDOUT,AXR3)\ + |_PER_FDEFAULT(MCASP,PDOUT,AMUTE)\ + |_PER_FDEFAULT(MCASP,PDOUT,ACLKX)\ + |_PER_FDEFAULT(MCASP,PDOUT,AHCLKX)\ + |_PER_FDEFAULT(MCASP,PDOUT,AFSX)\ + |_PER_FDEFAULT(MCASP,PDOUT,ACLKR)\ + |_PER_FDEFAULT(MCASP,PDOUT,AHCLKR)\ + |_PER_FDEFAULT(MCASP,PDOUT,AFSR)\ + ) + + #define MCASP_PDOUT_RMK(afsr,ahclkr,aclkr,afsx,ahclkx,aclkx,amute, \ + axr3,axr2,axr1, axr0) \ + (Uint32)( \ + _PER_FMK(MCASP,PDOUT,AXR0,axr0)\ + |_PER_FMK(MCASP,PDOUT,AXR1,axr1)\ + |_PER_FMK(MCASP,PDOUT,AXR2,axr2)\ + |_PER_FMK(MCASP,PDOUT,AXR3,axr3)\ + |_PER_FMK(MCASP,PDOUT,AMUTE,amute)\ + |_PER_FMK(MCASP,PDOUT,ACLKX,aclkx)\ + |_PER_FMK(MCASP,PDOUT,AHCLKX,ahclkx)\ + |_PER_FMK(MCASP,PDOUT,AFSX,afsx)\ + |_PER_FMK(MCASP,PDOUT,ACLKR,aclkr)\ + |_PER_FMK(MCASP,PDOUT,AHCLKR,ahclkr)\ + |_PER_FMK(MCASP,PDOUT,AFSR,afsr)\ + ) +#endif /* _MCASP_CHANNEL_CNT == 4 */ + + #define _MCASP_PDOUT_FGET(N,FIELD)\ + _PER_FGET(_MCASP_PDOUT##N##_ADDR,MCASP,PDOUT,##FIELD) + + #define _MCASP_PDOUT_FSET(N,FIELD,field)\ + _PER_FSET(_MCASP_PDOUT##N##_ADDR,MCASP,PDOUT,##FIELD,field) + + #define _MCASP_PDOUT_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCASP_PDOUT##N##_ADDR,MCASP,PDOUT,##FIELD,##SYM) + + #define _MCASP_PDOUT0_FGET(FIELD) _MCASP_PDOUT_FGET(0,##FIELD) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_PDOUT1_FGET(FIELD) _MCASP_PDOUT_FGET(1,##FIELD) +#endif + + #define _MCASP_PDOUT0_FSET(FIELD,f) _MCASP_PDOUT_FSET(0,##FIELD,f) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_PDOUT1_FSET(FIELD,f) _MCASP_PDOUT_FSET(1,##FIELD,f) +#endif + + #define _MCASP_PDOUT0_FSETS(FIELD,SYM) _MCASP_PDOUT_FSETS(0,##FIELD,##SYM) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_PDOUT1_FSETS(FIELD,SYM) _MCASP_PDOUT_FSETS(1,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* +* _____________________ +* | | +* | PDIN | +* |___________________| +* +* PDIN - Pin Data Input Register +* +* FIELDS (msb -> lsb) +* (rw) AFSR +* (rw) AHCLKR +* (rw) ACLKR +* (rw) AFSX +* (rw) AHCLKX +* (rw) ACLKX +* (rw) AMUTE +* (rw) AXR0-15 +* +\******************************************************************************/ + + #define _MCASP_PDIN_OFFSET 7 + + #define _MCASP_PDIN0_ADDR (_MCASP_BASE_PORT0+4*_MCASP_PDIN_OFFSET) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_PDIN1_ADDR (_MCASP_BASE_PORT1+4*_MCASP_PDIN_OFFSET) +#endif + + #define _MCASP_PDIN_AXR0_MASK 0x00000001u + #define _MCASP_PDIN_AXR0_SHIFT 0x00000000u + #define MCASP_PDIN_AXR0_DEFAULT 0x00000000u + #define MCASP_PDIN_AXR0_OF(x) _VALUEOF(x) + #define MCASP_PDIN_AXR0_SET 0x00000001u + + #define _MCASP_PDIN_AXR1_MASK 0x00000002u + #define _MCASP_PDIN_AXR1_SHIFT 0x00000001u + #define MCASP_PDIN_AXR1_DEFAULT 0x00000000u + #define MCASP_PDIN_AXR1_OF(x) _VALUEOF(x) + #define MCASP_PDIN_AXR1_SET 0x00000001u + + #define _MCASP_PDIN_AXR2_MASK 0x00000004u + #define _MCASP_PDIN_AXR2_SHIFT 0x00000002u + #define MCASP_PDIN_AXR2_DEFAULT 0x00000000u + #define MCASP_PDIN_AXR2_OF(x) _VALUEOF(x) + #define MCASP_PDIN_AXR2_SET 0x00000001u + + #define _MCASP_PDIN_AXR3_MASK 0x00000008u + #define _MCASP_PDIN_AXR3_SHIFT 0x00000003u + #define MCASP_PDIN_AXR3_DEFAULT 0x00000000u + #define MCASP_PDIN_AXR3_OF(x) _VALUEOF(x) + #define MCASP_PDIN_AXR3_SET 0x00000001u + /* Fields for _MCASP_CHANNEL_CNT == 4 end here*/ + +#if (_MCASP_CHANNEL_CNT > 4) + #define _MCASP_PDIN_AXR4_MASK 0x00000010u + #define _MCASP_PDIN_AXR4_SHIFT 0x00000004u + #define MCASP_PDIN_AXR4_DEFAULT 0x00000000u + #define MCASP_PDIN_AXR4_OF(x) _VALUEOF(x) + #define MCASP_PDIN_AXR4_SET 0x00000001 + + #define _MCASP_PDIN_AXR5_MASK 0x00000020u + #define _MCASP_PDIN_AXR5_SHIFT 0x00000005u + #define MCASP_PDIN_AXR5_DEFAULT 0x00000000u + #define MCASP_PDIN_AXR5_OF(x) _VALUEOF(x) + #define MCASP_PDIN_AXR5_SET 0x00000001u +#endif /* _MCASP_CHANNEL_CNT == 6 */ + +#if (_MCASP_CHANNEL_CNT > 6) /* For channel count 8 and 16 */ + #define _MCASP_PDIN_AXR6_MASK 0x00000040u + #define _MCASP_PDIN_AXR6_SHIFT 0x00000006u + #define MCASP_PDIN_AXR6_DEFAULT 0x00000000u + #define MCASP_PDIN_AXR6_OF(x) _VALUEOF(x) + #define MCASP_PDIN_AXR6_SET 0x00000001u + + #define _MCASP_PDIN_AXR7_MASK 0x00000080u + #define _MCASP_PDIN_AXR7_SHIFT 0x00000007u + #define MCASP_PDIN_AXR7_DEFAULT 0x00000000u + #define MCASP_PDIN_AXR7_OF(x) _VALUEOF(x) + #define MCASP_PDIN_AXR7_SET 0x00000001u +#endif /* _MCASP_CHANNEL_CNT == 8 */ + +#if (_MCASP_CHANNEL_CNT == 16) + #define _MCASP_PDIN_AXR8_MASK 0x00000100u + #define _MCASP_PDIN_AXR8_SHIFT 0x00000008u + #define MCASP_PDIN_AXR8_DEFAULT 0x00000000u + #define MCASP_PDIN_AXR8_OF(x) _VALUEOF(x) + #define MCASP_PDIN_AXR8_SET 0x00000001u + + #define _MCASP_PDIN_AXR9_MASK 0x00000200u + #define _MCASP_PDIN_AXR9_SHIFT 0x00000009u + #define MCASP_PDIN_AXR9_DEFAULT 0x00000000u + #define MCASP_PDIN_AXR9_OF(x) _VALUEOF(x) + #define MCASP_PDIN_AXR9_SET 0x00000001u + + #define _MCASP_PDIN_AXR10_MASK 0x00000400u + #define _MCASP_PDIN_AXR10_SHIFT 0x0000000Au + #define MCASP_PDIN_AXR10_DEFAULT 0x00000000u + #define MCASP_PDIN_AXR10_OF(x) _VALUEOF(x) + #define MCASP_PDIN_AXR10_SET 0x00000001u + + #define _MCASP_PDIN_AXR11_MASK 0x00000800u + #define _MCASP_PDIN_AXR11_SHIFT 0x0000000Bu + #define MCASP_PDIN_AXR11_DEFAULT 0x00000000u + #define MCASP_PDIN_AXR11_OF(x) _VALUEOF(x) + #define MCASP_PDIN_AXR11_SET 0x00000001u + + #define _MCASP_PDIN_AXR12_MASK 0x00001000u + #define _MCASP_PDIN_AXR12_SHIFT 0x0000000Cu + #define MCASP_PDIN_AXR12_DEFAULT 0x00000000u + #define MCASP_PDIN_AXR12_OF(x) _VALUEOF(x) + #define MCASP_PDIN_AXR12_SET 0x00000001u + + #define _MCASP_PDIN_AXR13_MASK 0x00002000u + #define _MCASP_PDIN_AXR13_SHIFT 0x0000000Du + #define MCASP_PDIN_AXR13_DEFAULT 0x00000000u + #define MCASP_PDIN_AXR13_OF(x) _VALUEOF(x) + #define MCASP_PDIN_AXR13_SET 0x00000001u + + #define _MCASP_PDIN_AXR14_MASK 0x00004000u + #define _MCASP_PDIN_AXR14_SHIFT 0x0000000Eu + #define MCASP_PDIN_AXR14_DEFAULT 0x00000000u + #define MCASP_PDIN_AXR14_OF(x) _VALUEOF(x) + #define MCASP_PDIN_AXR14_SET 0x00000001u + + #define _MCASP_PDIN_AXR15_MASK 0x00008000u + #define _MCASP_PDIN_AXR15_SHIFT 0x0000000Fu + #define MCASP_PDIN_AXR15_DEFAULT 0x00000000u + #define MCASP_PDIN_AXR15_OF(x) _VALUEOF(x) + #define MCASP_PDIN_AXR15_SET 0x00000001u +#endif /* _MCASP_CHANNEL_CNT == 16 */ + + #define _MCASP_PDIN_AMUTE_MASK 0x02000000u + #define _MCASP_PDIN_AMUTE_SHIFT 0x00000019u + #define MCASP_PDIN_AMUTE_DEFAULT 0x00000000u + #define MCASP_PDIN_AMUTE_OF(x) _VALUEOF(x) + #define MCASP_PDIN_AMUTE_SET 0x00000001u + + #define _MCASP_PDIN_ACLKX_MASK 0x04000000u + #define _MCASP_PDIN_ACLKX_SHIFT 0x0000001Au + #define MCASP_PDIN_ACLKX_DEFAULT 0x00000000u + #define MCASP_PDIN_ACLKX_OF(x) _VALUEOF(x) + #define MCASP_PDIN_ACLKX_SET 0x00000001u + + #define _MCASP_PDIN_AHCLKX_MASK 0x08000000u + #define _MCASP_PDIN_AHCLKX_SHIFT 0x0000001Bu + #define MCASP_PDIN_AHCLKX_DEFAULT 0x00000000u + #define MCASP_PDIN_AHCLKX_OF(x) _VALUEOF(x) + #define MCASP_PDIN_AHCLKX_SET 0x00000001u + + #define _MCASP_PDIN_AFSX_MASK 0x10000000u + #define _MCASP_PDIN_AFSX_SHIFT 0x0000001Cu + #define MCASP_PDIN_AFSX_DEFAULT 0x00000000u + #define MCASP_PDIN_AFSX_OF(x) _VALUEOF(x) + #define MCASP_PDIN_AFSX_SET 0x00000001u + + #define _MCASP_PDIN_ACLKR_MASK 0x20000000u + #define _MCASP_PDIN_ACLKR_SHIFT 0x0000001Du + #define MCASP_PDIN_ACLKR_DEFAULT 0x00000000u + #define MCASP_PDIN_ACLKR_OF(x) _VALUEOF(x) + #define MCASP_PDIN_ACLKR_SET 0x00000001u + + #define _MCASP_PDIN_AHCLKR_MASK 0x40000000u + #define _MCASP_PDIN_AHCLKR_SHIFT 0x0000001Eu + #define MCASP_PDIN_AHCLKR_DEFAULT 0x00000000u + #define MCASP_PDIN_AHCLKR_OF(x) _VALUEOF(x) + #define MCASP_PDIN_AHCLKR_SET 0x00000001u + + #define _MCASP_PDIN_AFSR_MASK 0x80000000u + #define _MCASP_PDIN_AFSR_SHIFT 0x0000001Fu + #define MCASP_PDIN_AFSR_DEFAULT 0x00000000u + #define MCASP_PDIN_AFSR_OF(x) _VALUEOF(x) + #define MCASP_PDIN_AFSR_SET 0x00000001u + + #define MCASP_PDIN_OF(x) _VALUEOF(x) + +#if (_MCASP_CHANNEL_CNT == 16) + #define MCASP_PDIN_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,PDIN,AXR0)\ + |_PER_FDEFAULT(MCASP,PDIN,AXR1)\ + |_PER_FDEFAULT(MCASP,PDIN,AXR2)\ + |_PER_FDEFAULT(MCASP,PDIN,AXR3)\ + |_PER_FDEFAULT(MCASP,PDIN,AXR4)\ + |_PER_FDEFAULT(MCASP,PDIN,AXR5)\ + |_PER_FDEFAULT(MCASP,PDIN,AXR6)\ + |_PER_FDEFAULT(MCASP,PDIN,AXR7)\ + |_PER_FDEFAULT(MCASP,PDIN,AXR8)\ + |_PER_FDEFAULT(MCASP,PDIN,AXR9)\ + |_PER_FDEFAULT(MCASP,PDIN,AXR10)\ + |_PER_FDEFAULT(MCASP,PDIN,AXR11)\ + |_PER_FDEFAULT(MCASP,PDIN,AXR12)\ + |_PER_FDEFAULT(MCASP,PDIN,AXR13)\ + |_PER_FDEFAULT(MCASP,PDIN,AXR14)\ + |_PER_FDEFAULT(MCASP,PDIN,AXR15)\ + |_PER_FDEFAULT(MCASP,PDIN,AMUTE)\ + |_PER_FDEFAULT(MCASP,PDIN,ACLKX)\ + |_PER_FDEFAULT(MCASP,PDIN,AHCLKX)\ + |_PER_FDEFAULT(MCASP,PDIN,AFSX)\ + |_PER_FDEFAULT(MCASP,PDIN,ACLKR)\ + |_PER_FDEFAULT(MCASP,PDIN,AHCLKR)\ + |_PER_FDEFAULT(MCASP,PDIN,AFSR)\ + ) + + #define MCASP_PDIN_RMK(afsr,ahclkr,aclkr,afsx,ahclkx,aclkx,amute, \ + axr15,axr14,axr13,axr12,axr11,axr10,\ + axr9, axr8,axr7,axr6,axr5,axr4,axr3,axr2,axr1, axr0) \ + (Uint32)( \ + _PER_FMK(MCASP,PDIN,AXR0,axr0)\ + |_PER_FMK(MCASP,PDIN,AXR1,axr1)\ + |_PER_FMK(MCASP,PDIN,AXR2,axr2)\ + |_PER_FMK(MCASP,PDIN,AXR3,axr3)\ + |_PER_FMK(MCASP,PDIN,AXR4,axr4)\ + |_PER_FMK(MCASP,PDIN,AXR5,axr5)\ + |_PER_FMK(MCASP,PDIN,AXR6,axr6)\ + |_PER_FMK(MCASP,PDIN,AXR7,axr7)\ + |_PER_FMK(MCASP,PDIN,AXR8,axr8)\ + |_PER_FMK(MCASP,PDIN,AXR9,axr9)\ + |_PER_FMK(MCASP,PDIN,AXR10,axr10)\ + |_PER_FMK(MCASP,PDIN,AXR11,axr11)\ + |_PER_FMK(MCASP,PDIN,AXR12,axr12)\ + |_PER_FMK(MCASP,PDIN,AXR13,axr13)\ + |_PER_FMK(MCASP,PDIN,AXR14,axr14)\ + |_PER_FMK(MCASP,PDIN,AXR15,axr15)\ + |_PER_FMK(MCASP,PDIN,AMUTE,amute)\ + |_PER_FMK(MCASP,PDIN,ACLKX,aclkx)\ + |_PER_FMK(MCASP,PDIN,AHCLKX,ahclkx)\ + |_PER_FMK(MCASP,PDIN,AFSX,afsx)\ + |_PER_FMK(MCASP,PDIN,ACLKR,aclkr)\ + |_PER_FMK(MCASP,PDIN,AHCLKR,ahclkr)\ + |_PER_FMK(MCASP,PDIN,AFSR,afsr)\ + ) +#endif /* _MCASP_CHANNEL_CNT == 16 */ + +#if (_MCASP_CHANNEL_CNT == 8) + #define MCASP_PDIN_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,PDIN,AXR0)\ + |_PER_FDEFAULT(MCASP,PDIN,AXR1)\ + |_PER_FDEFAULT(MCASP,PDIN,AXR2)\ + |_PER_FDEFAULT(MCASP,PDIN,AXR3)\ + |_PER_FDEFAULT(MCASP,PDIN,AXR4)\ + |_PER_FDEFAULT(MCASP,PDIN,AXR5)\ + |_PER_FDEFAULT(MCASP,PDIN,AXR6)\ + |_PER_FDEFAULT(MCASP,PDIN,AXR7)\ + |_PER_FDEFAULT(MCASP,PDIN,AMUTE)\ + |_PER_FDEFAULT(MCASP,PDIN,ACLKX)\ + |_PER_FDEFAULT(MCASP,PDIN,AHCLKX)\ + |_PER_FDEFAULT(MCASP,PDIN,AFSX)\ + |_PER_FDEFAULT(MCASP,PDIN,ACLKR)\ + |_PER_FDEFAULT(MCASP,PDIN,AHCLKR)\ + |_PER_FDEFAULT(MCASP,PDIN,AFSR)\ + ) + + #define MCASP_PDIN_RMK(afsr,ahclkr,aclkr,afsx,ahclkx,aclkx,amute, \ + axr7,axr6,axr5,axr4,axr3,axr2,axr1, axr0) \ + (Uint32)( \ + _PER_FMK(MCASP,PDIN,AXR0,axr0)\ + |_PER_FMK(MCASP,PDIN,AXR1,axr1)\ + |_PER_FMK(MCASP,PDIN,AXR2,axr2)\ + |_PER_FMK(MCASP,PDIN,AXR3,axr3)\ + |_PER_FMK(MCASP,PDIN,AXR4,axr4)\ + |_PER_FMK(MCASP,PDIN,AXR5,axr5)\ + |_PER_FMK(MCASP,PDIN,AXR6,axr6)\ + |_PER_FMK(MCASP,PDIN,AXR7,axr7)\ + |_PER_FMK(MCASP,PDIN,AMUTE,amute)\ + |_PER_FMK(MCASP,PDIN,ACLKX,aclkx)\ + |_PER_FMK(MCASP,PDIN,AHCLKX,ahclkx)\ + |_PER_FMK(MCASP,PDIN,AFSX,afsx)\ + |_PER_FMK(MCASP,PDIN,ACLKR,aclkr)\ + |_PER_FMK(MCASP,PDIN,AHCLKR,ahclkr)\ + |_PER_FMK(MCASP,PDIN,AFSR,afsr)\ + ) +#endif /* _MCASP_CHANNEL_CNT == 8 */ + +#if (_MCASP_CHANNEL_CNT == 6) + #define MCASP_PDIN_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,PDIN,AXR0)\ + |_PER_FDEFAULT(MCASP,PDIN,AXR1)\ + |_PER_FDEFAULT(MCASP,PDIN,AXR2)\ + |_PER_FDEFAULT(MCASP,PDIN,AXR3)\ + |_PER_FDEFAULT(MCASP,PDIN,AXR4)\ + |_PER_FDEFAULT(MCASP,PDIN,AXR5)\ + |_PER_FDEFAULT(MCASP,PDIN,AMUTE)\ + |_PER_FDEFAULT(MCASP,PDIN,ACLKX)\ + |_PER_FDEFAULT(MCASP,PDIN,AHCLKX)\ + |_PER_FDEFAULT(MCASP,PDIN,AFSX)\ + |_PER_FDEFAULT(MCASP,PDIN,ACLKR)\ + |_PER_FDEFAULT(MCASP,PDIN,AHCLKR)\ + |_PER_FDEFAULT(MCASP,PDIN,AFSR)\ + ) + + #define MCASP_PDIN_RMK(afsr,ahclkr,aclkr,afsx,ahclkx,aclkx,amute, \ + axr5,axr4,axr3,axr2,axr1, axr0) \ + (Uint32)( \ + _PER_FMK(MCASP,PDIN,AXR0,axr0)\ + |_PER_FMK(MCASP,PDIN,AXR1,axr1)\ + |_PER_FMK(MCASP,PDIN,AXR2,axr2)\ + |_PER_FMK(MCASP,PDIN,AXR3,axr3)\ + |_PER_FMK(MCASP,PDIN,AXR4,axr4)\ + |_PER_FMK(MCASP,PDIN,AXR5,axr5)\ + |_PER_FMK(MCASP,PDIN,AMUTE,amute)\ + |_PER_FMK(MCASP,PDIN,ACLKX,aclkx)\ + |_PER_FMK(MCASP,PDIN,AHCLKX,ahclkx)\ + |_PER_FMK(MCASP,PDIN,AFSX,afsx)\ + |_PER_FMK(MCASP,PDIN,ACLKR,aclkr)\ + |_PER_FMK(MCASP,PDIN,AHCLKR,ahclkr)\ + |_PER_FMK(MCASP,PDIN,AFSR,afsr)\ + ) +#endif /* _MCASP_CHANNEL_CNT == 6 */ + +#if (_MCASP_CHANNEL_CNT == 4) + #define MCASP_PDIN_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,PDIN,AXR0)\ + |_PER_FDEFAULT(MCASP,PDIN,AXR1)\ + |_PER_FDEFAULT(MCASP,PDIN,AXR2)\ + |_PER_FDEFAULT(MCASP,PDIN,AXR3)\ + |_PER_FDEFAULT(MCASP,PDIN,AMUTE)\ + |_PER_FDEFAULT(MCASP,PDIN,ACLKX)\ + |_PER_FDEFAULT(MCASP,PDIN,AHCLKX)\ + |_PER_FDEFAULT(MCASP,PDIN,AFSX)\ + |_PER_FDEFAULT(MCASP,PDIN,ACLKR)\ + |_PER_FDEFAULT(MCASP,PDIN,AHCLKR)\ + |_PER_FDEFAULT(MCASP,PDIN,AFSR)\ + ) + + #define MCASP_PDIN_RMK(afsr,ahclkr,aclkr,afsx,ahclkx,aclkx,amute, \ + axr3,axr2,axr1, axr0) \ + (Uint32)( \ + _PER_FMK(MCASP,PDIN,AXR0,axr0)\ + |_PER_FMK(MCASP,PDIN,AXR1,axr1)\ + |_PER_FMK(MCASP,PDIN,AXR2,axr2)\ + |_PER_FMK(MCASP,PDIN,AXR3,axr3)\ + |_PER_FMK(MCASP,PDIN,AMUTE,amute)\ + |_PER_FMK(MCASP,PDIN,ACLKX,aclkx)\ + |_PER_FMK(MCASP,PDIN,AHCLKX,ahclkx)\ + |_PER_FMK(MCASP,PDIN,AFSX,afsx)\ + |_PER_FMK(MCASP,PDIN,ACLKR,aclkr)\ + |_PER_FMK(MCASP,PDIN,AHCLKR,ahclkr)\ + |_PER_FMK(MCASP,PDIN,AFSR,afsr)\ + ) +#endif /* _MCASP_CHANNEL_CNT == 4 */ + + #define _MCASP_PDIN_FGET(N,FIELD)\ + _PER_FGET(_MCASP_PDIN##N##_ADDR,MCASP,PDIN,##FIELD) + + #define _MCASP_PDIN_FSET(N,FIELD,field)\ + _PER_FSET(_MCASP_PDIN##N##_ADDR,MCASP,PDIN,##FIELD,field) + + #define _MCASP_PDIN_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCASP_PDIN##N##_ADDR,MCASP,PDIN,##FIELD,##SYM) + + #define _MCASP_PDIN0_FGET(FIELD) _MCASP_PDIN_FGET(0,##FIELD) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_PDIN1_FGET(FIELD) _MCASP_PDIN_FGET(1,##FIELD) +#endif + + #define _MCASP_PDIN0_FSET(FIELD,f) _MCASP_PDIN_FSET(0,##FIELD,f) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_PDIN1_FSET(FIELD,f) _MCASP_PDIN_FSET(1,##FIELD,f) +#endif + + #define _MCASP_PDIN0_FSETS(FIELD,SYM) _MCASP_PDIN_FSETS(0,##FIELD,##SYM) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_PDIN1_FSETS(FIELD,SYM) _MCASP_PDIN_FSETS(1,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* +* _____________________ +* | | +* | PDSET | +* |___________________| +* +* PDSET - Pin Data Input Register +* +* FIELDS (msb -> lsb) +* (rw) AFSR +* (rw) AHCLKR +* (rw) ACLKR +* (rw) AFSX +* (rw) AHCLKX +* (rw) ACLKX +* (rw) AMUTE +* (rw) AXR0-15 +* +\******************************************************************************/ + + #define _MCASP_PDSET_OFFSET 7 + + #define _MCASP_PDSET0_ADDR (_MCASP_BASE_PORT0+4*_MCASP_PDSET_OFFSET) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_PDSET1_ADDR (_MCASP_BASE_PORT1+4*_MCASP_PDSET_OFFSET) +#endif + + + #define _MCASP_PDSET_AXR0_MASK 0x00000001u + #define _MCASP_PDSET_AXR0_SHIFT 0x00000000u + #define MCASP_PDSET_AXR0_DEFAULT 0x00000000u + #define MCASP_PDSET_AXR0_OF(x) _VALUEOF(x) + #define MCASP_PDSET_AXR0_SET 0x00000001u + + #define _MCASP_PDSET_AXR1_MASK 0x00000002u + #define _MCASP_PDSET_AXR1_SHIFT 0x00000001u + #define MCASP_PDSET_AXR1_DEFAULT 0x00000000u + #define MCASP_PDSET_AXR1_OF(x) _VALUEOF(x) + #define MCASP_PDSET_AXR1_SET 0x00000001u + + #define _MCASP_PDSET_AXR2_MASK 0x00000004u + #define _MCASP_PDSET_AXR2_SHIFT 0x00000002u + #define MCASP_PDSET_AXR2_DEFAULT 0x00000000u + #define MCASP_PDSET_AXR2_OF(x) _VALUEOF(x) + #define MCASP_PDSET_AXR2_SET 0x00000001u + + #define _MCASP_PDSET_AXR3_MASK 0x00000008u + #define _MCASP_PDSET_AXR3_SHIFT 0x00000003u + #define MCASP_PDSET_AXR3_DEFAULT 0x00000000u + #define MCASP_PDSET_AXR3_OF(x) _VALUEOF(x) + #define MCASP_PDSET_AXR3_SET 0x00000001u + /* Fields for _MCASP_CHANNEL_CNT == 4 end here*/ + +#if (_MCASP_CHANNEL_CNT > 4) + #define _MCASP_PDSET_AXR4_MASK 0x00000010u + #define _MCASP_PDSET_AXR4_SHIFT 0x00000004u + #define MCASP_PDSET_AXR4_DEFAULT 0x00000000u + #define MCASP_PDSET_AXR4_OF(x) _VALUEOF(x) + #define MCASP_PDSET_AXR4_SET 0x00000001u + + #define _MCASP_PDSET_AXR5_MASK 0x00000020u + #define _MCASP_PDSET_AXR5_SHIFT 0x00000005u + #define MCASP_PDSET_AXR5_DEFAULT 0x00000000u + #define MCASP_PDSET_AXR5_OF(x) _VALUEOF(x) + #define MCASP_PDSET_AXR5_SET 0x00000001u +#endif /* _MCASP_CHANNEL_CNT == 6 */ + +#if (_MCASP_CHANNEL_CNT > 6) /* For channel count 8 and 16 */ + #define _MCASP_PDSET_AXR6_MASK 0x00000040u + #define _MCASP_PDSET_AXR6_SHIFT 0x00000006u + #define MCASP_PDSET_AXR6_DEFAULT 0x00000000u + #define MCASP_PDSET_AXR6_OF(x) _VALUEOF(x) + #define MCASP_PDSET_AXR6_SET 0x00000001u + + #define _MCASP_PDSET_AXR7_MASK 0x00000080u + #define _MCASP_PDSET_AXR7_SHIFT 0x00000007u + #define MCASP_PDSET_AXR7_DEFAULT 0x00000000u + #define MCASP_PDSET_AXR7_OF(x) _VALUEOF(x) + #define MCASP_PDSET_AXR7_SET 0x00000001u +#endif /* _MCASP_CHANNEL_CNT == 8 */ + +#if (_MCASP_CHANNEL_CNT == 16) + #define _MCASP_PDSET_AXR8_MASK 0x00000100u + #define _MCASP_PDSET_AXR8_SHIFT 0x00000008u + #define MCASP_PDSET_AXR8_DEFAULT 0x00000000u + #define MCASP_PDSET_AXR8_OF(x) _VALUEOF(x) + #define MCASP_PDSET_AXR8_SET 0x00000001u + + #define _MCASP_PDSET_AXR9_MASK 0x00000200u + #define _MCASP_PDSET_AXR9_SHIFT 0x00000009u + #define MCASP_PDSET_AXR9_DEFAULT 0x00000000u + #define MCASP_PDSET_AXR9_OF(x) _VALUEOF(x) + #define MCASP_PDSET_AXR9_SET 0x00000001u + + #define _MCASP_PDSET_AXR10_MASK 0x00000400u + #define _MCASP_PDSET_AXR10_SHIFT 0x0000000Au + #define MCASP_PDSET_AXR10_DEFAULT 0x00000000u + #define MCASP_PDSET_AXR10_OF(x) _VALUEOF(x) + #define MCASP_PDSET_AXR10_SET 0x00000001u + + #define _MCASP_PDSET_AXR11_MASK 0x00000800u + #define _MCASP_PDSET_AXR11_SHIFT 0x0000000Bu + #define MCASP_PDSET_AXR11_DEFAULT 0x00000000u + #define MCASP_PDSET_AXR11_OF(x) _VALUEOF(x) + #define MCASP_PDSET_AXR11_SET 0x00000001u + + #define _MCASP_PDSET_AXR12_MASK 0x00001000u + #define _MCASP_PDSET_AXR12_SHIFT 0x0000000Cu + #define MCASP_PDSET_AXR12_DEFAULT 0x00000000u + #define MCASP_PDSET_AXR12_OF(x) _VALUEOF(x) + #define MCASP_PDSET_AXR12_SET 0x00000001u + + #define _MCASP_PDSET_AXR13_MASK 0x00002000u + #define _MCASP_PDSET_AXR13_SHIFT 0x0000000Du + #define MCASP_PDSET_AXR13_DEFAULT 0x00000000u + #define MCASP_PDSET_AXR13_OF(x) _VALUEOF(x) + #define MCASP_PDSET_AXR13_SET 0x00000001u + + #define _MCASP_PDSET_AXR14_MASK 0x00004000u + #define _MCASP_PDSET_AXR14_SHIFT 0x0000000Eu + #define MCASP_PDSET_AXR14_DEFAULT 0x00000000u + #define MCASP_PDSET_AXR14_OF(x) _VALUEOF(x) + #define MCASP_PDSET_AXR14_SET 0x00000001u + + #define _MCASP_PDSET_AXR15_MASK 0x00008000u + #define _MCASP_PDSET_AXR15_SHIFT 0x0000000Fu + #define MCASP_PDSET_AXR15_DEFAULT 0x00000000u + #define MCASP_PDSET_AXR15_OF(x) _VALUEOF(x) + #define MCASP_PDSET_AXR15_SET 0x00000001u +#endif /* _MCASP_CHANNEL_CNT == 16 */ + + #define _MCASP_PDSET_AMUTE_MASK 0x02000000u + #define _MCASP_PDSET_AMUTE_SHIFT 0x00000019u + #define MCASP_PDSET_AMUTE_DEFAULT 0x00000000u + #define MCASP_PDSET_AMUTE_OF(x) _VALUEOF(x) + #define MCASP_PDSET_AMUTE_SET 0x00000001u + + #define _MCASP_PDSET_ACLKX_MASK 0x04000000u + #define _MCASP_PDSET_ACLKX_SHIFT 0x0000001Au + #define MCASP_PDSET_ACLKX_DEFAULT 0x00000000u + #define MCASP_PDSET_ACLKX_OF(x) _VALUEOF(x) + #define MCASP_PDSET_ACLKX_SET 0x00000001u + + #define _MCASP_PDSET_AHCLKX_MASK 0x08000000u + #define _MCASP_PDSET_AHCLKX_SHIFT 0x0000001Bu + #define MCASP_PDSET_AHCLKX_DEFAULT 0x00000000u + #define MCASP_PDSET_AHCLKX_OF(x) _VALUEOF(x) + #define MCASP_PDSET_AHCLKX_SET 0x00000001u + + #define _MCASP_PDSET_AFSX_MASK 0x10000000u + #define _MCASP_PDSET_AFSX_SHIFT 0x0000001Cu + #define MCASP_PDSET_AFSX_DEFAULT 0x00000000u + #define MCASP_PDSET_AFSX_OF(x) _VALUEOF(x) + #define MCASP_PDSET_AFSX_SET 0x00000001u + + #define _MCASP_PDSET_ACLKR_MASK 0x20000000u + #define _MCASP_PDSET_ACLKR_SHIFT 0x0000001Du + #define MCASP_PDSET_ACLKR_DEFAULT 0x00000000u + #define MCASP_PDSET_ACLKR_OF(x) _VALUEOF(x) + #define MCASP_PDSET_ACLKR_SET 0x00000001u + + #define _MCASP_PDSET_AHCLKR_MASK 0x40000000u + #define _MCASP_PDSET_AHCLKR_SHIFT 0x0000001Eu + #define MCASP_PDSET_AHCLKR_DEFAULT 0x00000000u + #define MCASP_PDSET_AHCLKR_OF(x) _VALUEOF(x) + #define MCASP_PDSET_AHCLKR_SET 0x00000001u + + #define _MCASP_PDSET_AFSR_MASK 0x80000000u + #define _MCASP_PDSET_AFSR_SHIFT 0x0000001Fu + #define MCASP_PDSET_AFSR_DEFAULT 0x00000000u + #define MCASP_PDSET_AFSR_OF(x) _VALUEOF(x) + #define MCASP_PDSET_AFSR_SET 0x00000001u + + + + #define MCASP_PDSET_OF(x) _VALUEOF(x) + +#if (_MCASP_CHANNEL_CNT == 16) + #define MCASP_PDSET_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,PDSET,AXR0)\ + |_PER_FDEFAULT(MCASP,PDSET,AXR1)\ + |_PER_FDEFAULT(MCASP,PDSET,AXR2)\ + |_PER_FDEFAULT(MCASP,PDSET,AXR3)\ + |_PER_FDEFAULT(MCASP,PDSET,AXR4)\ + |_PER_FDEFAULT(MCASP,PDSET,AXR5)\ + |_PER_FDEFAULT(MCASP,PDSET,AXR6)\ + |_PER_FDEFAULT(MCASP,PDSET,AXR7)\ + |_PER_FDEFAULT(MCASP,PDSET,AXR8)\ + |_PER_FDEFAULT(MCASP,PDSET,AXR9)\ + |_PER_FDEFAULT(MCASP,PDSET,AXR10)\ + |_PER_FDEFAULT(MCASP,PDSET,AXR11)\ + |_PER_FDEFAULT(MCASP,PDSET,AXR12)\ + |_PER_FDEFAULT(MCASP,PDSET,AXR13)\ + |_PER_FDEFAULT(MCASP,PDSET,AXR14)\ + |_PER_FDEFAULT(MCASP,PDSET,AXR15)\ + |_PER_FDEFAULT(MCASP,PDSET,AMUTE)\ + |_PER_FDEFAULT(MCASP,PDSET,ACLKX)\ + |_PER_FDEFAULT(MCASP,PDSET,AHCLKX)\ + |_PER_FDEFAULT(MCASP,PDSET,AFSX)\ + |_PER_FDEFAULT(MCASP,PDSET,ACLKR)\ + |_PER_FDEFAULT(MCASP,PDSET,AHCLKR)\ + |_PER_FDEFAULT(MCASP,PDSET,AFSR)\ + ) + + #define MCASP_PDSET_RMK(afsr,ahclkr,aclkr,afsx,ahclkx,aclkx,amute, \ + axr15,axr14,axr13,axr12,axr11,axr10,\ + axr9, axr8,axr7,axr6,axr5,axr4,axr3,axr2,axr1, axr0) \ + (Uint32)( \ + _PER_FMK(MCASP,PDSET,AXR0,axr0)\ + |_PER_FMK(MCASP,PDSET,AXR1,axr1)\ + |_PER_FMK(MCASP,PDSET,AXR2,axr2)\ + |_PER_FMK(MCASP,PDSET,AXR3,axr3)\ + |_PER_FMK(MCASP,PDSET,AXR4,axr4)\ + |_PER_FMK(MCASP,PDSET,AXR5,axr5)\ + |_PER_FMK(MCASP,PDSET,AXR6,axr6)\ + |_PER_FMK(MCASP,PDSET,AXR7,axr7)\ + |_PER_FMK(MCASP,PDSET,AXR8,axr8)\ + |_PER_FMK(MCASP,PDSET,AXR9,axr9)\ + |_PER_FMK(MCASP,PDSET,AXR10,axr10)\ + |_PER_FMK(MCASP,PDSET,AXR11,axr11)\ + |_PER_FMK(MCASP,PDSET,AXR12,axr12)\ + |_PER_FMK(MCASP,PDSET,AXR13,axr13)\ + |_PER_FMK(MCASP,PDSET,AXR14,axr14)\ + |_PER_FMK(MCASP,PDSET,AXR15,axr15)\ + |_PER_FMK(MCASP,PDSET,AMUTE,amute)\ + |_PER_FMK(MCASP,PDSET,ACLKX,aclkx)\ + |_PER_FMK(MCASP,PDSET,AHCLKX,ahclkx)\ + |_PER_FMK(MCASP,PDSET,AFSX,afsx)\ + |_PER_FMK(MCASP,PDSET,ACLKR,aclkr)\ + |_PER_FMK(MCASP,PDSET,AHCLKR,ahclkr)\ + |_PER_FMK(MCASP,PDSET,AFSR,afsr)\ + ) +#endif /* _MCASP_CHANNEL_CNT == 16 */ + +#if (_MCASP_CHANNEL_CNT == 8) + #define MCASP_PDSET_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,PDSET,AXR0)\ + |_PER_FDEFAULT(MCASP,PDSET,AXR1)\ + |_PER_FDEFAULT(MCASP,PDSET,AXR2)\ + |_PER_FDEFAULT(MCASP,PDSET,AXR3)\ + |_PER_FDEFAULT(MCASP,PDSET,AXR4)\ + |_PER_FDEFAULT(MCASP,PDSET,AXR5)\ + |_PER_FDEFAULT(MCASP,PDSET,AXR6)\ + |_PER_FDEFAULT(MCASP,PDSET,AXR7)\ + |_PER_FDEFAULT(MCASP,PDSET,AMUTE)\ + |_PER_FDEFAULT(MCASP,PDSET,ACLKX)\ + |_PER_FDEFAULT(MCASP,PDSET,AHCLKX)\ + |_PER_FDEFAULT(MCASP,PDSET,AFSX)\ + |_PER_FDEFAULT(MCASP,PDSET,ACLKR)\ + |_PER_FDEFAULT(MCASP,PDSET,AHCLKR)\ + |_PER_FDEFAULT(MCASP,PDSET,AFSR)\ + ) + + #define MCASP_PDSET_RMK(afsr,ahclkr,aclkr,afsx,ahclkx,aclkx,amute, \ + axr7,axr6,axr5,axr4,axr3,axr2,axr1, axr0) \ + (Uint32)( \ + _PER_FMK(MCASP,PDSET,AXR0,axr0)\ + |_PER_FMK(MCASP,PDSET,AXR1,axr1)\ + |_PER_FMK(MCASP,PDSET,AXR2,axr2)\ + |_PER_FMK(MCASP,PDSET,AXR3,axr3)\ + |_PER_FMK(MCASP,PDSET,AXR4,axr4)\ + |_PER_FMK(MCASP,PDSET,AXR5,axr5)\ + |_PER_FMK(MCASP,PDSET,AXR6,axr6)\ + |_PER_FMK(MCASP,PDSET,AXR7,axr7)\ + |_PER_FMK(MCASP,PDSET,AMUTE,amute)\ + |_PER_FMK(MCASP,PDSET,ACLKX,aclkx)\ + |_PER_FMK(MCASP,PDSET,AHCLKX,ahclkx)\ + |_PER_FMK(MCASP,PDSET,AFSX,afsx)\ + |_PER_FMK(MCASP,PDSET,ACLKR,aclkr)\ + |_PER_FMK(MCASP,PDSET,AHCLKR,ahclkr)\ + |_PER_FMK(MCASP,PDSET,AFSR,afsr)\ + ) +#endif /* _MCASP_CHANNEL_CNT == 8 */ + +#if (_MCASP_CHANNEL_CNT == 6) + #define MCASP_PDSET_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,PDSET,AXR0)\ + |_PER_FDEFAULT(MCASP,PDSET,AXR1)\ + |_PER_FDEFAULT(MCASP,PDSET,AXR2)\ + |_PER_FDEFAULT(MCASP,PDSET,AXR3)\ + |_PER_FDEFAULT(MCASP,PDSET,AXR4)\ + |_PER_FDEFAULT(MCASP,PDSET,AXR5)\ + |_PER_FDEFAULT(MCASP,PDSET,AMUTE)\ + |_PER_FDEFAULT(MCASP,PDSET,ACLKX)\ + |_PER_FDEFAULT(MCASP,PDSET,AHCLKX)\ + |_PER_FDEFAULT(MCASP,PDSET,AFSX)\ + |_PER_FDEFAULT(MCASP,PDSET,ACLKR)\ + |_PER_FDEFAULT(MCASP,PDSET,AHCLKR)\ + |_PER_FDEFAULT(MCASP,PDSET,AFSR)\ + ) + + #define MCASP_PDSET_RMK(afsr,ahclkr,aclkr,afsx,ahclkx,aclkx,amute, \ + axr5,axr4,axr3,axr2,axr1, axr0) \ + (Uint32)( \ + _PER_FMK(MCASP,PDSET,AXR0,axr0)\ + |_PER_FMK(MCASP,PDSET,AXR1,axr1)\ + |_PER_FMK(MCASP,PDSET,AXR2,axr2)\ + |_PER_FMK(MCASP,PDSET,AXR3,axr3)\ + |_PER_FMK(MCASP,PDSET,AXR4,axr4)\ + |_PER_FMK(MCASP,PDSET,AXR5,axr5)\ + |_PER_FMK(MCASP,PDSET,AMUTE,amute)\ + |_PER_FMK(MCASP,PDSET,ACLKX,aclkx)\ + |_PER_FMK(MCASP,PDSET,AHCLKX,ahclkx)\ + |_PER_FMK(MCASP,PDSET,AFSX,afsx)\ + |_PER_FMK(MCASP,PDSET,ACLKR,aclkr)\ + |_PER_FMK(MCASP,PDSET,AHCLKR,ahclkr)\ + |_PER_FMK(MCASP,PDSET,AFSR,afsr)\ + ) +#endif /* _MCASP_CHANNEL_CNT == 6 */ + +#if (_MCASP_CHANNEL_CNT == 4) + #define MCASP_PDSET_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,PDSET,AXR0)\ + |_PER_FDEFAULT(MCASP,PDSET,AXR1)\ + |_PER_FDEFAULT(MCASP,PDSET,AXR2)\ + |_PER_FDEFAULT(MCASP,PDSET,AXR3)\ + |_PER_FDEFAULT(MCASP,PDSET,AMUTE)\ + |_PER_FDEFAULT(MCASP,PDSET,ACLKX)\ + |_PER_FDEFAULT(MCASP,PDSET,AHCLKX)\ + |_PER_FDEFAULT(MCASP,PDSET,AFSX)\ + |_PER_FDEFAULT(MCASP,PDSET,ACLKR)\ + |_PER_FDEFAULT(MCASP,PDSET,AHCLKR)\ + |_PER_FDEFAULT(MCASP,PDSET,AFSR)\ + ) + + #define MCASP_PDSET_RMK(afsr,ahclkr,aclkr,afsx,ahclkx,aclkx,amute, \ + axr3,axr2,axr1, axr0) \ + (Uint32)( \ + _PER_FMK(MCASP,PDSET,AXR0,axr0)\ + |_PER_FMK(MCASP,PDSET,AXR1,axr1)\ + |_PER_FMK(MCASP,PDSET,AXR2,axr2)\ + |_PER_FMK(MCASP,PDSET,AXR3,axr3)\ + |_PER_FMK(MCASP,PDSET,AMUTE,amute)\ + |_PER_FMK(MCASP,PDSET,ACLKX,aclkx)\ + |_PER_FMK(MCASP,PDSET,AHCLKX,ahclkx)\ + |_PER_FMK(MCASP,PDSET,AFSX,afsx)\ + |_PER_FMK(MCASP,PDSET,ACLKR,aclkr)\ + |_PER_FMK(MCASP,PDSET,AHCLKR,ahclkr)\ + |_PER_FMK(MCASP,PDSET,AFSR,afsr)\ + ) +#endif /* _MCASP_CHANNEL_CNT == 4 */ + + #define _MCASP_PDSET_FGET(N,FIELD)\ + _PER_FGET(_MCASP_PDSET##N##_ADDR,MCASP,PDSET,##FIELD) + + #define _MCASP_PDSET_FSET(N,FIELD,field)\ + _PER_FSET(_MCASP_PDSET##N##_ADDR,MCASP,PDSET,##FIELD,field) + + #define _MCASP_PDSET_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCASP_PDSET##N##_ADDR,MCASP,PDSET,##FIELD,##SYM) + + #define _MCASP_PDSET0_FGET(FIELD) _MCASP_PDSET_FGET(0,##FIELD) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_PDSET1_FGET(FIELD) _MCASP_PDSET_FGET(1,##FIELD) +#endif + + #define _MCASP_PDSET0_FSET(FIELD,f) _MCASP_PDSET_FSET(0,##FIELD,f) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_PDSET1_FSET(FIELD,f) _MCASP_PDSET_FSET(1,##FIELD,f) +#endif + + #define _MCASP_PDSET0_FSETS(FIELD,SYM) _MCASP_PDSET_FSETS(0,##FIELD,##SYM) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_PDSET1_FSETS(FIELD,SYM) _MCASP_PDSET_FSETS(1,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* +* _____________________ +* | | +* | P D C L R | +* |___________________| +* +* PDCLR - Pin Data Clear Register +* +* FIELDS (msb -> lsb) +* (rw) AFSR +* (rw) AHCLKR +* (rw) ACLKR +* (rw) AFSX +* (rw) AHCLKX +* (rw) ACLKX +* (rw) AMUTE +* (rw) AXR0-15 +* +\******************************************************************************/ + + #define _MCASP_PDCLR_OFFSET 8 + + #define _MCASP_PDCLR0_ADDR (_MCASP_BASE_PORT0+4*_MCASP_PDCLR_OFFSET) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_PDCLR1_ADDR (_MCASP_BASE_PORT1+4*_MCASP_PDCLR_OFFSET) +#endif + + #define _MCASP_PDCLR_AXR0_MASK 0x00000001u + #define _MCASP_PDCLR_AXR0_SHIFT 0x00000000u + #define MCASP_PDCLR_AXR0_DEFAULT 0x00000000u + #define MCASP_PDCLR_AXR0_OF(x) _VALUEOF(x) + #define MCASP_PDCLR_AXR0_CLR 0x00000001u + + #define _MCASP_PDCLR_AXR1_MASK 0x00000002u + #define _MCASP_PDCLR_AXR1_SHIFT 0x00000001u + #define MCASP_PDCLR_AXR1_DEFAULT 0x00000000u + #define MCASP_PDCLR_AXR1_OF(x) _VALUEOF(x) + #define MCASP_PDCLR_AXR1_CLR 0x00000001u + + #define _MCASP_PDCLR_AXR2_MASK 0x00000004u + #define _MCASP_PDCLR_AXR2_SHIFT 0x00000002u + #define MCASP_PDCLR_AXR2_DEFAULT 0x00000000u + #define MCASP_PDCLR_AXR2_OF(x) _VALUEOF(x) + #define MCASP_PDCLR_AXR2_CLR 0x00000001u + + #define _MCASP_PDCLR_AXR3_MASK 0x00000008u + #define _MCASP_PDCLR_AXR3_SHIFT 0x00000003u + #define MCASP_PDCLR_AXR3_DEFAULT 0x00000000u + #define MCASP_PDCLR_AXR3_OF(x) _VALUEOF(x) + #define MCASP_PDCLR_AXR3_CLR 0x00000001u + /* Fields for _MCASP_CHANNEL_CNT == 4 end here*/ + +#if (_MCASP_CHANNEL_CNT > 4) + #define _MCASP_PDCLR_AXR4_MASK 0x00000010u + #define _MCASP_PDCLR_AXR4_SHIFT 0x00000004u + #define MCASP_PDCLR_AXR4_DEFAULT 0x00000000u + #define MCASP_PDCLR_AXR4_OF(x) _VALUEOF(x) + #define MCASP_PDCLR_AXR4_CLR 0x00000001u + + #define _MCASP_PDCLR_AXR5_MASK 0x00000020u + #define _MCASP_PDCLR_AXR5_SHIFT 0x00000005u + #define MCASP_PDCLR_AXR5_DEFAULT 0x00000000u + #define MCASP_PDCLR_AXR5_OF(x) _VALUEOF(x) + #define MCASP_PDCLR_AXR5_CLR 0x00000001u +#endif /* _MCASP_CHANNEL_CNT == 6 */ + +#if (_MCASP_CHANNEL_CNT > 6) /* For channel count 8 and 16 */ + #define _MCASP_PDCLR_AXR6_MASK 0x00000040u + #define _MCASP_PDCLR_AXR6_SHIFT 0x00000006u + #define MCASP_PDCLR_AXR6_DEFAULT 0x00000000u + #define MCASP_PDCLR_AXR6_OF(x) _VALUEOF(x) + #define MCASP_PDCLR_AXR6_CLR 0x00000001u + + #define _MCASP_PDCLR_AXR7_MASK 0x00000080u + #define _MCASP_PDCLR_AXR7_SHIFT 0x00000007u + #define MCASP_PDCLR_AXR7_DEFAULT 0x00000000u + #define MCASP_PDCLR_AXR7_OF(x) _VALUEOF(x) + #define MCASP_PDCLR_AXR7_CLR 0x00000001u +#endif /* _MCASP_CHANNEL_CNT == 8 */ + +#if (_MCASP_CHANNEL_CNT == 16) + #define _MCASP_PDCLR_AXR8_MASK 0x00000100u + #define _MCASP_PDCLR_AXR8_SHIFT 0x00000008u + #define MCASP_PDCLR_AXR8_DEFAULT 0x00000000u + #define MCASP_PDCLR_AXR8_OF(x) _VALUEOF(x) + #define MCASP_PDCLR_AXR8_CLR 0x00000001u + + #define _MCASP_PDCLR_AXR9_MASK 0x00000200u + #define _MCASP_PDCLR_AXR9_SHIFT 0x00000009u + #define MCASP_PDCLR_AXR9_DEFAULT 0x00000000u + #define MCASP_PDCLR_AXR9_OF(x) _VALUEOF(x) + #define MCASP_PDCLR_AXR9_CLR 0x00000001u + + #define _MCASP_PDCLR_AXR10_MASK 0x00000400u + #define _MCASP_PDCLR_AXR10_SHIFT 0x0000000Au + #define MCASP_PDCLR_AXR10_DEFAULT 0x00000000u + #define MCASP_PDCLR_AXR10_OF(x) _VALUEOF(x) + #define MCASP_PDCLR_AXR10_CLR 0x00000001u + + #define _MCASP_PDCLR_AXR11_MASK 0x00000800u + #define _MCASP_PDCLR_AXR11_SHIFT 0x0000000Bu + #define MCASP_PDCLR_AXR11_DEFAULT 0x00000000u + #define MCASP_PDCLR_AXR11_OF(x) _VALUEOF(x) + #define MCASP_PDCLR_AXR11_CLR 0x00000001u + + #define _MCASP_PDCLR_AXR12_MASK 0x00001000u + #define _MCASP_PDCLR_AXR12_SHIFT 0x0000000Cu + #define MCASP_PDCLR_AXR12_DEFAULT 0x00000000u + #define MCASP_PDCLR_AXR12_OF(x) _VALUEOF(x) + #define MCASP_PDCLR_AXR12_CLR 0x00000001u + + #define _MCASP_PDCLR_AXR13_MASK 0x00002000u + #define _MCASP_PDCLR_AXR13_SHIFT 0x0000000Du + #define MCASP_PDCLR_AXR13_DEFAULT 0x00000000u + #define MCASP_PDCLR_AXR13_OF(x) _VALUEOF(x) + #define MCASP_PDCLR_AXR13_CLR 0x00000001u + + #define _MCASP_PDCLR_AXR14_MASK 0x00004000u + #define _MCASP_PDCLR_AXR14_SHIFT 0x0000000Eu + #define MCASP_PDCLR_AXR14_DEFAULT 0x00000000u + #define MCASP_PDCLR_AXR14_OF(x) _VALUEOF(x) + #define MCASP_PDCLR_AXR14_CLR 0x00000001u + + #define _MCASP_PDCLR_AXR15_MASK 0x00008000u + #define _MCASP_PDCLR_AXR15_SHIFT 0x0000000Fu + #define MCASP_PDCLR_AXR15_DEFAULT 0x00000000u + #define MCASP_PDCLR_AXR15_OF(x) _VALUEOF(x) + #define MCASP_PDCLR_AXR15_CLR 0x00000001u +#endif /* _MCASP_CHANNEL_CNT == 16 */ + + #define _MCASP_PDCLR_AMUTE_MASK 0x02000000u + #define _MCASP_PDCLR_AMUTE_SHIFT 0x00000019u + #define MCASP_PDCLR_AMUTE_DEFAULT 0x00000000u + #define MCASP_PDCLR_AMUTE_OF(x) _VALUEOF(x) + #define MCASP_PDCLR_AMUTE_CLR 0x00000001u + + #define _MCASP_PDCLR_ACLKX_MASK 0x04000000u + #define _MCASP_PDCLR_ACLKX_SHIFT 0x0000001Au + #define MCASP_PDCLR_ACLKX_DEFAULT 0x00000000u + #define MCASP_PDCLR_ACLKX_OF(x) _VALUEOF(x) + #define MCASP_PDCLR_ACLKX_CLR 0x00000001u + + #define _MCASP_PDCLR_AHCLKX_MASK 0x08000000u + #define _MCASP_PDCLR_AHCLKX_SHIFT 0x0000001Bu + #define MCASP_PDCLR_AHCLKX_DEFAULT 0x00000000u + #define MCASP_PDCLR_AHCLKX_OF(x) _VALUEOF(x) + #define MCASP_PDCLR_AHCLKX_CLR 0x00000001u + + #define _MCASP_PDCLR_AFSX_MASK 0x10000000u + #define _MCASP_PDCLR_AFSX_SHIFT 0x0000001Cu + #define MCASP_PDCLR_AFSX_DEFAULT 0x00000000u + #define MCASP_PDCLR_AFSX_OF(x) _VALUEOF(x) + #define MCASP_PDCLR_AFSX_CLR 0x00000001u + + #define _MCASP_PDCLR_ACLKR_MASK 0x20000000u + #define _MCASP_PDCLR_ACLKR_SHIFT 0x0000001Du + #define MCASP_PDCLR_ACLKR_DEFAULT 0x00000000u + #define MCASP_PDCLR_ACLKR_OF(x) _VALUEOF(x) + #define MCASP_PDCLR_ACLKR_CLR 0x00000001u + + + #define _MCASP_PDCLR_AHCLKR_MASK 0x40000000u + #define _MCASP_PDCLR_AHCLKR_SHIFT 0x0000001Eu + #define MCASP_PDCLR_AHCLKR_DEFAULT 0x00000000u + #define MCASP_PDCLR_AHCLKR_OF(x) _VALUEOF(x) + #define MCASP_PDCLR_AHCLKR_CLR 0x00000001u + + #define _MCASP_PDCLR_AFSR_MASK 0x80000000u + #define _MCASP_PDCLR_AFSR_SHIFT 0x0000001Fu + #define MCASP_PDCLR_AFSR_DEFAULT 0x00000000u + #define MCASP_PDCLR_AFSR_OF(x) _VALUEOF(x) + #define MCASP_PDCLR_AFSR_CLR 0x00000001u + + #define MCASP_PDCLR_OF(x) _VALUEOF(x) + +#if (_MCASP_CHANNEL_CNT == 16) + #define MCASP_PDCLR_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,PDCLR,AXR0)\ + |_PER_FDEFAULT(MCASP,PDCLR,AXR1)\ + |_PER_FDEFAULT(MCASP,PDCLR,AXR2)\ + |_PER_FDEFAULT(MCASP,PDCLR,AXR3)\ + |_PER_FDEFAULT(MCASP,PDCLR,AXR4)\ + |_PER_FDEFAULT(MCASP,PDCLR,AXR5)\ + |_PER_FDEFAULT(MCASP,PDCLR,AXR6)\ + |_PER_FDEFAULT(MCASP,PDCLR,AXR7)\ + |_PER_FDEFAULT(MCASP,PDCLR,AXR8)\ + |_PER_FDEFAULT(MCASP,PDCLR,AXR9)\ + |_PER_FDEFAULT(MCASP,PDCLR,AXR10)\ + |_PER_FDEFAULT(MCASP,PDCLR,AXR11)\ + |_PER_FDEFAULT(MCASP,PDCLR,AXR12)\ + |_PER_FDEFAULT(MCASP,PDCLR,AXR13)\ + |_PER_FDEFAULT(MCASP,PDCLR,AXR14)\ + |_PER_FDEFAULT(MCASP,PDCLR,AXR15)\ + |_PER_FDEFAULT(MCASP,PDCLR,AMUTE)\ + |_PER_FDEFAULT(MCASP,PDCLR,ACLKX)\ + |_PER_FDEFAULT(MCASP,PDCLR,AHCLKX)\ + |_PER_FDEFAULT(MCASP,PDCLR,AFSX)\ + |_PER_FDEFAULT(MCASP,PDCLR,ACLKR)\ + |_PER_FDEFAULT(MCASP,PDCLR,AHCLKR)\ + |_PER_FDEFAULT(MCASP,PDCLR,AFSR)\ + ) + + #define MCASP_PDCLR_RMK(afsr,ahclkr,aclkr,afsx,ahclkx,aclkx,amute, \ + axr15,axr14,axr13,axr12,axr11,axr10,\ + axr9, axr8,axr7,axr6,axr5,axr4,axr3,axr2,axr1, axr0) \ + (Uint32)( \ + _PER_FMK(MCASP,PDCLR,AXR0,axr0)\ + |_PER_FMK(MCASP,PDCLR,AXR1,axr1)\ + |_PER_FMK(MCASP,PDCLR,AXR2,axr2)\ + |_PER_FMK(MCASP,PDCLR,AXR3,axr3)\ + |_PER_FMK(MCASP,PDCLR,AXR4,axr4)\ + |_PER_FMK(MCASP,PDCLR,AXR5,axr5)\ + |_PER_FMK(MCASP,PDCLR,AXR6,axr6)\ + |_PER_FMK(MCASP,PDCLR,AXR7,axr7)\ + |_PER_FMK(MCASP,PDCLR,AXR8,axr8)\ + |_PER_FMK(MCASP,PDCLR,AXR9,axr9)\ + |_PER_FMK(MCASP,PDCLR,AXR10,axr10)\ + |_PER_FMK(MCASP,PDCLR,AXR11,axr11)\ + |_PER_FMK(MCASP,PDCLR,AXR12,axr12)\ + |_PER_FMK(MCASP,PDCLR,AXR13,axr13)\ + |_PER_FMK(MCASP,PDCLR,AXR14,axr14)\ + |_PER_FMK(MCASP,PDCLR,AXR15,axr15)\ + |_PER_FMK(MCASP,PDCLR,AMUTE,amute)\ + |_PER_FMK(MCASP,PDCLR,ACLKX,aclkx)\ + |_PER_FMK(MCASP,PDCLR,AHCLKX,ahclkx)\ + |_PER_FMK(MCASP,PDCLR,AFSX,afsx)\ + |_PER_FMK(MCASP,PDCLR,ACLKR,aclkr)\ + |_PER_FMK(MCASP,PDCLR,AHCLKR,ahclkr)\ + |_PER_FMK(MCASP,PDCLR,AFSR,afsr)\ + ) +#endif /* _MCASP_CHANNEL_CNT == 16 */ + +#if (_MCASP_CHANNEL_CNT == 8) + #define MCASP_PDCLR_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,PDCLR,AXR0)\ + |_PER_FDEFAULT(MCASP,PDCLR,AXR1)\ + |_PER_FDEFAULT(MCASP,PDCLR,AXR2)\ + |_PER_FDEFAULT(MCASP,PDCLR,AXR3)\ + |_PER_FDEFAULT(MCASP,PDCLR,AXR4)\ + |_PER_FDEFAULT(MCASP,PDCLR,AXR5)\ + |_PER_FDEFAULT(MCASP,PDCLR,AXR6)\ + |_PER_FDEFAULT(MCASP,PDCLR,AXR7)\ + |_PER_FDEFAULT(MCASP,PDCLR,AMUTE)\ + |_PER_FDEFAULT(MCASP,PDCLR,ACLKX)\ + |_PER_FDEFAULT(MCASP,PDCLR,AHCLKX)\ + |_PER_FDEFAULT(MCASP,PDCLR,AFSX)\ + |_PER_FDEFAULT(MCASP,PDCLR,ACLKR)\ + |_PER_FDEFAULT(MCASP,PDCLR,AHCLKR)\ + |_PER_FDEFAULT(MCASP,PDCLR,AFSR)\ + ) + + #define MCASP_PDCLR_RMK(afsr,ahclkr,aclkr,afsx,ahclkx,aclkx,amute, \ + axr7,axr6,axr5,axr4,axr3,axr2,axr1, axr0) \ + (Uint32)( \ + _PER_FMK(MCASP,PDCLR,AXR0,axr0)\ + |_PER_FMK(MCASP,PDCLR,AXR1,axr1)\ + |_PER_FMK(MCASP,PDCLR,AXR2,axr2)\ + |_PER_FMK(MCASP,PDCLR,AXR3,axr3)\ + |_PER_FMK(MCASP,PDCLR,AXR4,axr4)\ + |_PER_FMK(MCASP,PDCLR,AXR5,axr5)\ + |_PER_FMK(MCASP,PDCLR,AXR6,axr6)\ + |_PER_FMK(MCASP,PDCLR,AXR7,axr7)\ + |_PER_FMK(MCASP,PDCLR,AMUTE,amute)\ + |_PER_FMK(MCASP,PDCLR,ACLKX,aclkx)\ + |_PER_FMK(MCASP,PDCLR,AHCLKX,ahclkx)\ + |_PER_FMK(MCASP,PDCLR,AFSX,afsx)\ + |_PER_FMK(MCASP,PDCLR,ACLKR,aclkr)\ + |_PER_FMK(MCASP,PDCLR,AHCLKR,ahclkr)\ + |_PER_FMK(MCASP,PDCLR,AFSR,afsr)\ + ) +#endif /* _MCASP_CHANNEL_CNT == 8 */ + +#if (_MCASP_CHANNEL_CNT == 6) + #define MCASP_PDCLR_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,PDCLR,AXR0)\ + |_PER_FDEFAULT(MCASP,PDCLR,AXR1)\ + |_PER_FDEFAULT(MCASP,PDCLR,AXR2)\ + |_PER_FDEFAULT(MCASP,PDCLR,AXR3)\ + |_PER_FDEFAULT(MCASP,PDCLR,AXR4)\ + |_PER_FDEFAULT(MCASP,PDCLR,AXR5)\ + |_PER_FDEFAULT(MCASP,PDCLR,AMUTE)\ + |_PER_FDEFAULT(MCASP,PDCLR,ACLKX)\ + |_PER_FDEFAULT(MCASP,PDCLR,AHCLKX)\ + |_PER_FDEFAULT(MCASP,PDCLR,AFSX)\ + |_PER_FDEFAULT(MCASP,PDCLR,ACLKR)\ + |_PER_FDEFAULT(MCASP,PDCLR,AHCLKR)\ + |_PER_FDEFAULT(MCASP,PDCLR,AFSR)\ + ) + + #define MCASP_PDCLR_RMK(afsr,ahclkr,aclkr,afsx,ahclkx,aclkx,amute, \ + axr5,axr4,axr3,axr2,axr1, axr0) \ + (Uint32)( \ + _PER_FMK(MCASP,PDCLR,AXR0,axr0)\ + |_PER_FMK(MCASP,PDCLR,AXR1,axr1)\ + |_PER_FMK(MCASP,PDCLR,AXR2,axr2)\ + |_PER_FMK(MCASP,PDCLR,AXR3,axr3)\ + |_PER_FMK(MCASP,PDCLR,AXR4,axr4)\ + |_PER_FMK(MCASP,PDCLR,AXR5,axr5)\ + |_PER_FMK(MCASP,PDCLR,AMUTE,amute)\ + |_PER_FMK(MCASP,PDCLR,ACLKX,aclkx)\ + |_PER_FMK(MCASP,PDCLR,AHCLKX,ahclkx)\ + |_PER_FMK(MCASP,PDCLR,AFSX,afsx)\ + |_PER_FMK(MCASP,PDCLR,ACLKR,aclkr)\ + |_PER_FMK(MCASP,PDCLR,AHCLKR,ahclkr)\ + |_PER_FMK(MCASP,PDCLR,AFSR,afsr)\ + ) +#endif /* _MCASP_CHANNEL_CNT == 6 */ + +#if (_MCASP_CHANNEL_CNT == 4) + #define MCASP_PDCLR_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,PDCLR,AXR0)\ + |_PER_FDEFAULT(MCASP,PDCLR,AXR1)\ + |_PER_FDEFAULT(MCASP,PDCLR,AXR2)\ + |_PER_FDEFAULT(MCASP,PDCLR,AXR3)\ + |_PER_FDEFAULT(MCASP,PDCLR,AMUTE)\ + |_PER_FDEFAULT(MCASP,PDCLR,ACLKX)\ + |_PER_FDEFAULT(MCASP,PDCLR,AHCLKX)\ + |_PER_FDEFAULT(MCASP,PDCLR,AFSX)\ + |_PER_FDEFAULT(MCASP,PDCLR,ACLKR)\ + |_PER_FDEFAULT(MCASP,PDCLR,AHCLKR)\ + |_PER_FDEFAULT(MCASP,PDCLR,AFSR)\ + ) + + #define MCASP_PDCLR_RMK(afsr,ahclkr,aclkr,afsx,ahclkx,aclkx,amute, \ + axr3,axr2,axr1, axr0) \ + (Uint32)( \ + _PER_FMK(MCASP,PDCLR,AXR0,axr0)\ + |_PER_FMK(MCASP,PDCLR,AXR1,axr1)\ + |_PER_FMK(MCASP,PDCLR,AXR2,axr2)\ + |_PER_FMK(MCASP,PDCLR,AXR3,axr3)\ + |_PER_FMK(MCASP,PDCLR,AMUTE,amute)\ + |_PER_FMK(MCASP,PDCLR,ACLKX,aclkx)\ + |_PER_FMK(MCASP,PDCLR,AHCLKX,ahclkx)\ + |_PER_FMK(MCASP,PDCLR,AFSX,afsx)\ + |_PER_FMK(MCASP,PDCLR,ACLKR,aclkr)\ + |_PER_FMK(MCASP,PDCLR,AHCLKR,ahclkr)\ + |_PER_FMK(MCASP,PDCLR,AFSR,afsr)\ + ) +#endif /* _MCASP_CHANNEL_CNT == 4 */ + + #define _MCASP_PDCLR_FGET(N,FIELD)\ + _PER_FGET(_MCASP_PDCLR##N##_ADDR,MCASP,PDCLR,##FIELD) + + #define _MCASP_PDCLR_FSET(N,FIELD,field)\ + _PER_FSET(_MCASP_PDCLR##N##_ADDR,MCASP,PDCLR,##FIELD,field) + + #define _MCASP_PDCLR_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCASP_PDCLR##N##_ADDR,MCASP,PDCLR,##FIELD,##SYM) + + + #define _MCASP_PDCLR0_FGET(FIELD) _MCASP_PDCLR_FGET(0,##FIELD) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_PDCLR1_FGET(FIELD) _MCASP_PDCLR_FGET(1,##FIELD) +#endif + + #define _MCASP_PDCLR0_FSET(FIELD,f) _MCASP_PDCLR_FSET(0,##FIELD,f) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_PDCLR1_FSET(FIELD,f) _MCASP_PDCLR_FSET(1,##FIELD,f) +#endif + + #define _MCASP_PDCLR0_FSETS(FIELD,SYM) _MCASP_PDCLR_FSETS(0,##FIELD,##SYM) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_PDCLR1_FSETS(FIELD,SYM) _MCASP_PDCLR_FSETS(1,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* +* _____________________ +* | | +* | GBLCTL | +* |___________________| +* +* GBLCTL - Global Control Register +* +* FIELDS (msb -> lsb) +* (rw) XFRST +* (rw) XSMRST +* (rw) XSRCLR +* (rw) XHCLKRST +* (rw) XCLKRST +* (rw) RFRST +* (rw) RSMRST +* (rw) RSRCLR +* (rw) RHCLKRST +* (rw) RCLKRST +* +\******************************************************************************/ + + #define _MCASP_GBLCTL_OFFSET 17 + + #define _MCASP_GBLCTL0_ADDR (_MCASP_BASE_PORT0+4*_MCASP_GBLCTL_OFFSET) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_GBLCTL1_ADDR (_MCASP_BASE_PORT1+4*_MCASP_GBLCTL_OFFSET) +#endif + + #define _MCASP_GBLCTL_XFRST_MASK 0x00001000u + #define _MCASP_GBLCTL_XFRST_SHIFT 0x0000000Cu + #define MCASP_GBLCTL_XFRST_DEFAULT 0x00000000u + #define MCASP_GBLCTL_XFRST_OF(x) _VALUEOF(x) + #define MCASP_GBLCTL_XFRST_RESET 0x00000000u + #define MCASP_GBLCTL_XFRST_ACTIVE 0x00000001u + + + #define _MCASP_GBLCTL_XSMRST_MASK 0x00000800u + #define _MCASP_GBLCTL_XSMRST_SHIFT 0x0000000Bu + #define MCASP_GBLCTL_XSMRST_DEFAULT 0x00000000u + #define MCASP_GBLCTL_XSMRST_OF(x) _VALUEOF(x) + #define MCASP_GBLCTL_XSMRST_RESET 0x00000000u + #define MCASP_GBLCTL_XSMRST_ACTIVE 0x00000001u + + + #define _MCASP_GBLCTL_XSRCLR_MASK 0x00000400u + #define _MCASP_GBLCTL_XSRCLR_SHIFT 0x0000000Au + #define MCASP_GBLCTL_XSRCLR_DEFAULT 0x00000000u + #define MCASP_GBLCTL_XSRCLR_OF(x) _VALUEOF(x) + #define MCASP_GBLCTL_XSRCLR_CLEAR 0x00000000u + #define MCASP_GBLCTL_XSRCLR_ACTIVE 0x00000001u + + + #define _MCASP_GBLCTL_XHCLKRST_MASK 0x00000200u + #define _MCASP_GBLCTL_XHCLKRST_SHIFT 0x00000009u + #define MCASP_GBLCTL_XHCLKRST_DEFAULT 0x00000000u + #define MCASP_GBLCTL_XHCLKRST_OF(x) _VALUEOF(x) + #define MCASP_GBLCTL_XHCLKRST_RESET 0x00000000u + #define MCASP_GBLCTL_XHCLKRST_ACTIVE 0x00000001u + + + #define _MCASP_GBLCTL_XCLKRST_MASK 0x00000100u + #define _MCASP_GBLCTL_XCLKRST_SHIFT 0x00000008u + #define MCASP_GBLCTL_XCLKRST_DEFAULT 0x00000000u + #define MCASP_GBLCTL_XCLKRST_OF(x) _VALUEOF(x) + #define MCASP_GBLCTL_XCLKRST_RESET 0x00000000u + #define MCASP_GBLCTL_XCLKRST_ACTIVE 0x00000001u + + #define _MCASP_GBLCTL_RFRST_MASK 0x00000010u + #define _MCASP_GBLCTL_RFRST_SHIFT 0x00000004u + #define MCASP_GBLCTL_RFRST_DEFAULT 0x00000000u + #define MCASP_GBLCTL_RFRST_OF(x) _VALUEOF(x) + #define MCASP_GBLCTL_RFRST_RESET 0x00000000u + #define MCASP_GBLCTL_RFRST_ACTIVE 0x00000001u + + #define _MCASP_GBLCTL_RSMRST_MASK 0x00000008u + #define _MCASP_GBLCTL_RSMRST_SHIFT 0x00000003u + #define MCASP_GBLCTL_RSMRST_DEFAULT 0x00000000u + #define MCASP_GBLCTL_RSMRST_OF(x) _VALUEOF(x) + #define MCASP_GBLCTL_RSMRST_RESET 0x00000000u + #define MCASP_GBLCTL_RSMRST_ACTIVE 0x00000001u + + + #define _MCASP_GBLCTL_RSRCLR_MASK 0x00000004u + #define _MCASP_GBLCTL_RSRCLR_SHIFT 0x00000002u + #define MCASP_GBLCTL_RSRCLR_DEFAULT 0x00000000u + #define MCASP_GBLCTL_RSRCLR_OF(x) _VALUEOF(x) + #define MCASP_GBLCTL_RSRCLR_CLEAR 0x00000000u + #define MCASP_GBLCTL_RSRCLR_ACTIVE 0x00000001u + + + #define _MCASP_GBLCTL_RHCLKRST_MASK 0x00000002u + #define _MCASP_GBLCTL_RHCLKRST_SHIFT 0x00000001u + #define MCASP_GBLCTL_RHCLKRST_DEFAULT 0x00000000u + #define MCASP_GBLCTL_RHCLKRST_OF(x) _VALUEOF(x) + #define MCASP_GBLCTL_RHCLKRST_RESET 0x00000000u + #define MCASP_GBLCTL_RHCLKRST_ACTIVE 0x00000001u + + + #define _MCASP_GBLCTL_RCLKRST_MASK 0x00000001u + #define _MCASP_GBLCTL_RCLKRST_SHIFT 0x00000000u + #define MCASP_GBLCTL_RCLKRST_DEFAULT 0x00000000u + #define MCASP_GBLCTL_RCLKRST_OF(x) _VALUEOF(x) + #define MCASP_GBLCTL_RCLKRST_RESET 0x00000000u + #define MCASP_GBLCTL_RCLKRST_ACTIVE 0x00000001u + + + #define MCASP_GBLCTL_OF(x) _VALUEOF(x) + + #define MCASP_GBLCTL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,GBLCTL,XFRST)\ + |_PER_FDEFAULT(MCASP,GBLCTL,XSMRST)\ + |_PER_FDEFAULT(MCASP,GBLCTL,XSRCLR)\ + |_PER_FDEFAULT(MCASP,GBLCTL,XHCLKRST)\ + |_PER_FDEFAULT(MCASP,GBLCTL,XCLKRST)\ + |_PER_FDEFAULT(MCASP,GBLCTL,RFRST)\ + |_PER_FDEFAULT(MCASP,GBLCTL,RSMRST)\ + |_PER_FDEFAULT(MCASP,GBLCTL,RSRCLR)\ + |_PER_FDEFAULT(MCASP,GBLCTL,RHCLKRST)\ + |_PER_FDEFAULT(MCASP,GBLCTL,RCLKRST)\ + ) + + + #define MCASP_GBLCTL_RMK(xfrst, xsmrst, xsrclr, xhclkrst, xclkrst, rfrst, rsmrst, rsrclr, rhclkrst, rclkrst) (Uint32)( \ + _PER_FMK(MCASP,GBLCTL,XFRST,xfrst)\ + |_PER_FMK(MCASP,GBLCTL,XSMRST,xsmrst)\ + |_PER_FMK(MCASP,GBLCTL,XSRCLR,xsrclr)\ + |_PER_FMK(MCASP,GBLCTL,XHCLKRST,xhclkrst)\ + |_PER_FMK(MCASP,GBLCTL,XCLKRST,xclkrst)\ + |_PER_FMK(MCASP,GBLCTL,RFRST,rfrst)\ + |_PER_FMK(MCASP,GBLCTL,RSMRST,rsmrst)\ + |_PER_FMK(MCASP,GBLCTL,RSRCLR,rsrclr)\ + |_PER_FMK(MCASP,GBLCTL,RHCLKRST,rhclkrst)\ + |_PER_FMK(MCASP,GBLCTL,RCLKRST,rclkrst)\ + ) + + + #define _MCASP_GBLCTL_FGET(N,FIELD)\ + _PER_FGET(_MCASP_GBLCTL##N##_ADDR,MCASP,GBLCTL,##FIELD) + + #define _MCASP_GBLCTL_FSET(N,FIELD,field)\ + _PER_FSET(_MCASP_GBLCTL##N##_ADDR,MCASP,GBLCTL,##FIELD,field) + + #define _MCASP_GBLCTL_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCASP_GBLCTL##N##_ADDR,MCASP,GBLCTL,##FIELD,##SYM) + + + #define _MCASP_GBLCTL0_FGET(FIELD) _MCASP_GBLCTL_FGET(0,##FIELD) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_GBLCTL1_FGET(FIELD) _MCASP_GBLCTL_FGET(1,##FIELD) +#endif + + #define _MCASP_GBLCTL0_FSET(FIELD,f) _MCASP_GBLCTL_FSET(0,##FIELD,f) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_GBLCTL1_FSET(FIELD,f) _MCASP_GBLCTL_FSET(1,##FIELD,f) +#endif + + #define _MCASP_GBLCTL0_FSETS(FIELD,SYM) _MCASP_GBLCTL_FSETS(0,##FIELD,##SYM) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_GBLCTL1_FSETS(FIELD,SYM) _MCASP_GBLCTL_FSETS(1,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* +* _____________________ +* | | +* | AMUTE | +* |___________________| +* +* AMUTE - register name +* +* FIELDS (msb -> lsb) +* (rw) XDMAERR +* (rw) RDMAERR +* (rw) XCKFAIL +* (rw) RCKFAIL +* (rw) XSYNCERR +* (rw) RSYNCERR +* (rw) XUNDRN +* (rw) ROVRN +* (r ) INSTAT +* (rw) INEN +* (r ) INPOL +* (rw) MUTEN +\******************************************************************************/ + + #define _MCASP_AMUTE_OFFSET 18 + + #define _MCASP_AMUTE0_ADDR (_MCASP_BASE_PORT0+4*_MCASP_AMUTE_OFFSET) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_AMUTE1_ADDR (_MCASP_BASE_PORT1+4*_MCASP_AMUTE_OFFSET) +#endif + + #define _MCASP_AMUTE_XDMAERR_MASK 0x00001000u + #define _MCASP_AMUTE_XDMAERR_SHIFT 0x0000000Cu + #define MCASP_AMUTE_XDMAERR_DEFAULT 0x00000000u + #define MCASP_AMUTE_XDMAERR_OF(x) _VALUEOF(x) + #define MCASP_AMUTE_XDMAERR_DISABLE 0x00000000u + #define MCASP_AMUTE_XDMAERR_ENABLE 0x00000001u + + #define _MCASP_AMUTE_RDMAERR_MASK 0x00000800u + #define _MCASP_AMUTE_RDMAERR_SHIFT 0x0000000Bu + #define MCASP_AMUTE_RDMAERR_DEFAULT 0x00000000u + #define MCASP_AMUTE_RDMAERR_OF(x) _VALUEOF(x) + #define MCASP_AMUTE_RDMAERR_DISABLE 0x00000000u + #define MCASP_AMUTE_RDMAERR_ENABLE 0x00000001u + + #define _MCASP_AMUTE_XCKFAIL_MASK 0x00000400u + #define _MCASP_AMUTE_XCKFAIL_SHIFT 0x0000000Au + #define MCASP_AMUTE_XCKFAIL_DEFAULT 0x00000000u + #define MCASP_AMUTE_XCKFAIL_OF(x) _VALUEOF(x) + #define MCASP_AMUTE_XCKFAIL_DISABLE 0x00000000u + #define MCASP_AMUTE_XCKFAIL_ENABLE 0x00000001u + + + #define _MCASP_AMUTE_RCKFAIL_MASK 0x00000200u + #define _MCASP_AMUTE_RCKFAIL_SHIFT 0x00000009u + #define MCASP_AMUTE_RCKFAIL_DEFAULT 0x00000000u + #define MCASP_AMUTE_RCKFAIL_OF(x) _VALUEOF(x) + #define MCASP_AMUTE_RCKFAIL_DISABLE 0x00000000u + #define MCASP_AMUTE_RCKFAIL_ENABLE 0x00000001u + + + #define _MCASP_AMUTE_XSYNCERR_MASK 0x00000100u + #define _MCASP_AMUTE_XSYNCERR_SHIFT 0x00000008u + #define MCASP_AMUTE_XSYNCERR_DEFAULT 0x00000000u + #define MCASP_AMUTE_XSYNCERR_OF(x) _VALUEOF(x) + #define MCASP_AMUTE_XSYNCERR_DISABLE 0x00000000u + #define MCASP_AMUTE_XSYNCERR_ENABLE 0x00000001u + + + #define _MCASP_AMUTE_RSYNCERR_MASK 0x00000080u + #define _MCASP_AMUTE_RSYNCERR_SHIFT 0x00000007u + #define MCASP_AMUTE_RSYNCERR_DEFAULT 0x00000000u + #define MCASP_AMUTE_RSYNCERR_OF(x) _VALUEOF(x) + #define MCASP_AMUTE_RSYNCERR_DISABLE 0x00000000u + #define MCASP_AMUTE_RSYNCERR_ENABLE 0x00000001u + + + #define _MCASP_AMUTE_XUNDRN_MASK 0x00000040u + #define _MCASP_AMUTE_XUNDRN_SHIFT 0x00000006u + #define MCASP_AMUTE_XUNDRN_DEFAULT 0x00000000u + #define MCASP_AMUTE_XUNDRN_OF(x) _VALUEOF(x) + #define MCASP_AMUTE_XUNDRN_DISABLE 0x00000000u + #define MCASP_AMUTE_XUNDRN_ENABLE 0x00000001u + + + #define _MCASP_AMUTE_ROVRN_MASK 0x00000020u + #define _MCASP_AMUTE_ROVRN_SHIFT 0x00000005u + #define MCASP_AMUTE_ROVRN_DEFAULT 0x00000000u + #define MCASP_AMUTE_ROVRN_OF(x) _VALUEOF(x) + #define MCASP_AMUTE_ROVRN_DISABLE 0x00000000u + #define MCASP_AMUTE_ROVRN_ENABLE 0x00000001u + + + #define _MCASP_AMUTE_INSTAT_MASK 0x00000010u + #define _MCASP_AMUTE_INSTAT_SHIFT 0x00000004u + #define MCASP_AMUTE_INSTAT_DEFAULT 0x00000000u + #define MCASP_AMUTE_INSTAT_OF(x) _VALUEOF(x) + + + #define _MCASP_AMUTE_INEN_MASK 0x00000008u + #define _MCASP_AMUTE_INEN_SHIFT 0x00000003u + #define MCASP_AMUTE_INEN_DEFAULT 0x00000000u + #define MCASP_AMUTE_INEN_OF(x) _VALUEOF(x) + #define MCASP_AMUTE_INEN_DISABLE 0x00000000u + #define MCASP_AMUTE_INEN_ENABLE 0x00000001u + + + #define _MCASP_AMUTE_INPOL_MASK 0x00000004u + #define _MCASP_AMUTE_INPOL_SHIFT 0x00000002u + #define MCASP_AMUTE_INPOL_DEFAULT 0x00000000u + #define MCASP_AMUTE_INPOL_OF(x) _VALUEOF(x) + #define MCASP_AMUTE_INPOL_ACTHIGH 0x00000000u + #define MCASP_AMUTE_INPOL_ACTLOW 0x00000001u + + + #define _MCASP_AMUTE_MUTEN_MASK 0x00000003u + #define _MCASP_AMUTE_MUTEN_SHIFT 0x00000000u + #define MCASP_AMUTE_MUTEN_DEFAULT 0x00000000u + #define MCASP_AMUTE_MUTEN_OF(x) _VALUEOF(x) + #define MCASP_AMUTE_MUTEN_DISABLE 0x00000000u + #define MCASP_AMUTE_MUTEN_ERRHIGH 0x00000001u + #define MCASP_AMUTE_MUTEN_ERRLOW 0x00000002u + + #define MCASP_AMUTE_OF(x) _VALUEOF(x) + + #define MCASP_AMUTE_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,AMUTE,XDMAERR)\ + | _PER_FDEFAULT(MCASP,AMUTE,RDMAERR)\ + | _PER_FDEFAULT(MCASP,AMUTE,XCKFAIL)\ + | _PER_FDEFAULT(MCASP,AMUTE,RCKFAIL)\ + | _PER_FDEFAULT(MCASP,AMUTE,XSYNCERR )\ + | _PER_FDEFAULT(MCASP,AMUTE,RSYNCERR)\ + | _PER_FDEFAULT(MCASP,AMUTE,XUNDRN)\ + | _PER_FDEFAULT(MCASP,AMUTE,ROVRN)\ + | _PER_FDEFAULT(MCASP,AMUTE,INSTAT)\ + | _PER_FDEFAULT(MCASP,AMUTE,INEN)\ + | _PER_FDEFAULT(MCASP,AMUTE,MUTEN)\ + ) + + #define MCASP_AMUTE_RMK(xdmaerr,rdmaerr,xckfail, rckfail, xsyncerr, rsyncerr, xundrn, rovrn,inen, muten) (Uint32)( \ + _PER_FMK(MCASP,AMUTE,XDMAERR,xdmaerr)\ + | _PER_FMK(MCASP,AMUTE,RDMAERR,rdmaerr)\ + | _PER_FMK(MCASP,AMUTE,XCKFAIL,xckfail)\ + | _PER_FMK(MCASP,AMUTE,RCKFAIL,rckfail)\ + | _PER_FMK(MCASP,AMUTE,XSYNCERR ,xsyncerr)\ + | _PER_FMK(MCASP,AMUTE,RSYNCERR,rsyncerr)\ + | _PER_FMK(MCASP,AMUTE,XUNDRN,xundrn)\ + | _PER_FMK(MCASP,AMUTE,ROVRN,rovrn)\ + | _PER_FMK(MCASP,AMUTE,INEN,inen)\ + | _PER_FMK(MCASP,AMUTE,MUTEN,muten)\ + ) + + + #define _MCASP_AMUTE_FGET(N,FIELD)\ + _PER_FGET(_MCASP_AMUTE##N##_ADDR,MCASP,AMUTE,##FIELD) + + #define _MCASP_AMUTE_FSET(N,FIELD,field)\ + _PER_FSET(_MCASP_AMUTE##N##_ADDR,MCASP,AMUTE,##FIELD,field) + + #define _MCASP_AMUTE_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCASP_AMUTE##N##_ADDR,MCASP,AMUTE,##FIELD,##SYM) + + #define _MCASP_AMUTE0_FGET(FIELD) _MCASP_AMUTE_FGET(0,##FIELD) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_AMUTE1_FGET(FIELD) _MCASP_AMUTE_FGET(1,##FIELD) +#endif + + #define _MCASP_AMUTE0_FSET(FIELD,f) _MCASP_AMUTE_FSET(0,##FIELD,f) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_AMUTE1_FSET(FIELD,f) _MCASP_AMUTE_FSET(1,##FIELD,f) +#endif + + #define _MCASP_AMUTE0_FSETS(FIELD,SYM) _MCASP_AMUTE_FSETS(0,##FIELD,##SYM) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_AMUTE1_FSETS(FIELD,SYM) _MCASP_AMUTE_FSETS(1,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* +* _____________________ +* | | +* | DLBCTL | +* |___________________| +* +* DLBCTL - Digital Loopback Control Register +* +* FIELDS (msb -> lsb) +* (rw) MODE +* (rw) ORD +* (rw) DLBEN +\******************************************************************************/ + + #define _MCASP_DLBCTL_OFFSET 19 + + #define _MCASP_DLBCTL0_ADDR (_MCASP_BASE_PORT0+4*_MCASP_DLBCTL_OFFSET) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_DLBCTL1_ADDR (_MCASP_BASE_PORT1+4*_MCASP_DLBCTL_OFFSET) +#endif + + #define _MCASP_DLBCTL_MODE_MASK 0x0000000Cu + #define _MCASP_DLBCTL_MODE_SHIFT 0x00000002u + #define MCASP_DLBCTL_MODE_DEFAULT 0x00000000u + #define MCASP_DLBCTL_MODE_OF(x) _VALUEOF(x) + #define MCASP_DLBCTL_MODE_XMTCLK 0x00000001u + + #define _MCASP_DLBCTL_ORD_MASK 0x00000002u + #define _MCASP_DLBCTL_ORD_SHIFT 0x00000001u + #define MCASP_DLBCTL_ORD_DEFAULT 0x00000000u + #define MCASP_DLBCTL_ORD_OF(x) _VALUEOF(x) + #define MCASP_DLBCTL_ORD_XMTODD 0x00000000u + #define MCASP_DLBCTL_ORD_XMTEVEN 0x00000001u + + + #define _MCASP_DLBCTL_DLBEN_MASK 0x00000001u + #define _MCASP_DLBCTL_DLBEN_SHIFT 0x00000000u + #define MCASP_DLBCTL_DLBEN_DEFAULT 0x00000000u + #define MCASP_DLBCTL_DLBEN_OF(x) _VALUEOF(x) + #define MCASP_DLBCTL_DLBEN_DISABLE 0x00000000u + #define MCASP_DLBCTL_DLBEN_ENABLE 0x00000001u + + #define MCASP_DLBCTL_OF(x) _VALUEOF(x) + + #define MCASP_DLBCTL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,DLBCTL,MODE)\ + |_PER_FDEFAULT(MCASP,DLBCTL,ORD)\ + |_PER_FDEFAULT(MCASP,DLBCTL,DLBEN)\ + ) + + #define MCASP_DLBCTL_RMK(mode, ord, dlben) (Uint32)( \ + _PER_FMK(MCASP,DLBCTL,MODE,mode)\ + |_PER_FMK(MCASP,DLBCTL,ORD,ord)\ + |_PER_FMK(MCASP,DLBCTL,DLBEN,dlben)\ + ) + + + #define _MCASP_DLBCTL_FGET(N,FIELD)\ + _PER_FGET(_MCASP_DLBCTL##N##_ADDR,MCASP,DLBCTL,##FIELD) + + #define _MCASP_DLBCTL_FSET(N,FIELD,field)\ + _PER_FSET(_MCASP_DLBCTL##N##_ADDR,MCASP,DLBCTL,##FIELD,field) + + #define _MCASP_DLBCTL_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCASP_DLBCTL##N##_ADDR,MCASP,DLBCTL,##FIELD,##SYM) + + + #define _MCASP_DLBCTL0_FGET(FIELD) _MCASP_DLBCTL_FGET(0,##FIELD) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_DLBCTL1_FGET(FIELD) _MCASP_DLBCTL_FGET(1,##FIELD) +#endif + + #define _MCASP_DLBCTL0_FSET(FIELD,f) _MCASP_DLBCTL_FSET(0,##FIELD,f) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_DLBCTL1_FSET(FIELD,f) _MCASP_DLBCTL_FSET(1,##FIELD,f) +#endif + + #define _MCASP_DLBCTL0_FSETS(FIELD,SYM) _MCASP_DLBCTL_FSETS(0,##FIELD,##SYM) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_DLBCTL1_FSETS(FIELD,SYM) _MCASP_DLBCTL_FSETS(1,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* +* _____________________ +* | | +* | DITCTL | +* |___________________| +* +* DITCTL - Transmit DIT Control Register +* +* FIELDS (msb -> lsb) +* (rw) VB +* (rw) VA +* (rw) DITEN +* +\******************************************************************************/ + + #define _MCASP_DITCTL_OFFSET 20 + + #define _MCASP_DITCTL0_ADDR (_MCASP_BASE_PORT0+4*_MCASP_DITCTL_OFFSET) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_DITCTL1_ADDR (_MCASP_BASE_PORT1+4*_MCASP_DITCTL_OFFSET) +#endif + + #define _MCASP_DITCTL_VB_MASK 0x00000008u + #define _MCASP_DITCTL_VB_SHIFT 0x00000003u + #define MCASP_DITCTL_VB_DEFAULT 0x00000000u + #define MCASP_DITCTL_VB_OF(x) _VALUEOF(x) + #define MCASP_DITCTL_VB_ZERO 0x00000000u + #define MCASP_DITCTL_VB_ONE 0x00000001u + + #define _MCASP_DITCTL_VA_MASK 0x00000004u + #define _MCASP_DITCTL_VA_SHIFT 0x00000002u + #define MCASP_DITCTL_VA_DEFAULT 0x00000000u + #define MCASP_DITCTL_VA_OF(x) _VALUEOF(x) + #define MCASP_DITCTL_VA_ZERO 0x00000000u + #define MCASP_DITCTL_VA_ONE 0x00000001u + + #define _MCASP_DITCTL_DITEN_MASK 0x00000001u + #define _MCASP_DITCTL_DITEN_SHIFT 0x00000000u + #define MCASP_DITCTL_DITEN_DEFAULT 0x00000000u + #define MCASP_DITCTL_DITEN_OF(x) _VALUEOF(x) + #define MCASP_DITCTL_DITEN_TDM 0x00000000u + #define MCASP_DITCTL_DITEN_DIT 0x00000001u + + #define MCASP_DITCTL_OF(x) _VALUEOF(x) + + #define MCASP_DITCTL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,DITCTL,VB)\ + |_PER_FDEFAULT(MCASP,DITCTL,VA)\ + |_PER_FDEFAULT(MCASP,DITCTL,DITEN)\ + ) + + #define MCASP_DITCTL_RMK(vb,va,diten) (Uint32)( \ + _PER_FMK(MCASP,DITCTL,VB,vb)\ + |_PER_FMK(MCASP,DITCTL,VA,va)\ + |_PER_FMK(MCASP,DITCTL,DITEN,diten)\ + ) + + #define _MCASP_DITCTL_FGET(N,FIELD)\ + _PER_FGET(_MCASP_DITCTL##N##_ADDR,MCASP,DITCTL,##FIELD) + + #define _MCASP_DITCTL_FSET(N,FIELD,field)\ + _PER_FSET(_MCASP_DITCTL##N##_ADDR,MCASP,DITCTL,##FIELD,field) + + #define _MCASP_DITCTL_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCASP_DITCTL##N##_ADDR,MCASP,DITCTL,##FIELD,##SYM) + + #define _MCASP_DITCTL0_FGET(FIELD) _MCASP_DITCTL_FGET(0,##FIELD) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_DITCTL1_FGET(FIELD) _MCASP_DITCTL_FGET(1,##FIELD) +#endif + + #define _MCASP_DITCTL0_FSET(FIELD,f) _MCASP_DITCTL_FSET(0,##FIELD,f) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_DITCTL1_FSET(FIELD,f) _MCASP_DITCTL_FSET(1,##FIELD,f) +#endif + + #define _MCASP_DITCTL0_FSETS(FIELD,SYM) _MCASP_DITCTL_FSETS(0,##FIELD,##SYM) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_DITCTL1_FSETS(FIELD,SYM) _MCASP_DITCTL_FSETS(1,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* +* _____________________ +* | | +* | RGBLCTL | +* |___________________| +* +* RGBLCTL - Global Control Register +* +* FIELDS (msb -> lsb) +* (r) XFRST +* (r) XSMRST +* (r) XSRCLR +* (r) XHCLKRST +* (r) XCLKRST +* (rw) RFRST +* (rw) RSMRST +* (rw) RSRCLR +* (rw) RHCLKRST +* (rw) RCLKRST +* +\******************************************************************************/ + + #define _MCASP_RGBLCTL_OFFSET 24 + + #define _MCASP_RGBLCTL0_ADDR (_MCASP_BASE_PORT0+4*_MCASP_RGBLCTL_OFFSET) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_RGBLCTL1_ADDR (_MCASP_BASE_PORT1+4*_MCASP_RGBLCTL_OFFSET) +#endif + + #define _MCASP_RGBLCTL_XFRST_MASK 0x00001000u + #define _MCASP_RGBLCTL_XFRST_SHIFT 0x0000000Cu + #define MCASP_RGBLCTL_XFRST_DEFAULT 0x00000000u + #define MCASP_RGBLCTL_XFRST_OF(x) _VALUEOF(x) + #define MCASP_RGBLCTL_XFRST_RESET 0x00000000u + #define MCASP_RGBLCTL_XFRST_ACTIVE 0x00000001u + + #define _MCASP_RGBLCTL_XSMRST_MASK 0x00000800u + #define _MCASP_RGBLCTL_XSMRST_SHIFT 0x0000000Bu + #define MCASP_RGBLCTL_XSMRST_DEFAULT 0x00000000u + #define MCASP_RGBLCTL_XSMRST_OF(x) _VALUEOF(x) + #define MCASP_RGBLCTL_XSMRST_RESET 0x00000000u + #define MCASP_RGBLCTL_XSMRST_ACTIVE 0x00000001u + + #define _MCASP_RGBLCTL_XSRCLR_MASK 0x00000400u + #define _MCASP_RGBLCTL_XSRCLR_SHIFT 0x0000000Au + #define MCASP_RGBLCTL_XSRCLR_DEFAULT 0x00000000u + #define MCASP_RGBLCTL_XSRCLR_OF(x) _VALUEOF(x) + #define MCASP_RGBLCTL_XSRCLR_CLEAR 0x00000000u + #define MCASP_RGBLCTL_XSRCLR_ACTIVE 0x00000001u + + #define _MCASP_RGBLCTL_XHCLKRST_MASK 0x00000200u + #define _MCASP_RGBLCTL_XHCLKRST_SHIFT 0x00000009u + #define MCASP_RGBLCTL_XHCLKRST_DEFAULT 0x00000000u + #define MCASP_RGBLCTL_XHCLKRST_OF(x) _VALUEOF(x) + #define MCASP_RGBLCTL_XHCLKRST_RESET 0x00000000u + #define MCASP_RGBLCTL_XHCLKRST_ACTIVE 0x00000001u + + #define _MCASP_RGBLCTL_XCLKRST_MASK 0x00000100u + #define _MCASP_RGBLCTL_XCLKRST_SHIFT 0x00000008u + #define MCASP_RGBLCTL_XCLKRST_DEFAULT 0x00000000u + #define MCASP_RGBLCTL_XCLKRST_OF(x) _VALUEOF(x) + #define MCASP_RGBLCTL_XCLKRST_RESET 0x00000000u + #define MCASP_RGBLCTL_XCLKRST_ACTIVE 0x00000001u + + #define _MCASP_RGBLCTL_RFRST_MASK 0x00000010u + #define _MCASP_RGBLCTL_RFRST_SHIFT 0x00000004u + #define MCASP_RGBLCTL_RFRST_DEFAULT 0x00000000u + #define MCASP_RGBLCTL_RFRST_OF(x) _VALUEOF(x) + #define MCASP_RGBLCTL_RFRST_RESET 0x00000000u + #define MCASP_RGBLCTL_RFRST_ACTIVE 0x00000001u + + #define _MCASP_RGBLCTL_RSMRST_MASK 0x00000008u + #define _MCASP_RGBLCTL_RSMRST_SHIFT 0x00000003u + #define MCASP_RGBLCTL_RSMRST_DEFAULT 0x00000000u + #define MCASP_RGBLCTL_RSMRST_OF(x) _VALUEOF(x) + #define MCASP_RGBLCTL_RSMRST_RESET 0x00000000u + #define MCASP_RGBLCTL_RSMRST_ACTIVE 0x00000001u + + #define _MCASP_RGBLCTL_RSRCLR_MASK 0x00000004u + #define _MCASP_RGBLCTL_RSRCLR_SHIFT 0x00000002u + #define MCASP_RGBLCTL_RSRCLR_DEFAULT 0x00000000u + #define MCASP_RGBLCTL_RSRCLR_OF(x) _VALUEOF(x) + #define MCASP_RGBLCTL_RSRCLR_CLEAR 0x00000000u + #define MCASP_RGBLCTL_RSRCLR_ACTIVE 0x00000001u + + #define _MCASP_RGBLCTL_RHCLKRST_MASK 0x00000002u + #define _MCASP_RGBLCTL_RHCLKRST_SHIFT 0x00000001u + #define MCASP_RGBLCTL_RHCLKRST_DEFAULT 0x00000000u + #define MCASP_RGBLCTL_RHCLKRST_OF(x) _VALUEOF(x) + #define MCASP_RGBLCTL_RHCLKRST_RESET 0x00000000u + #define MCASP_RGBLCTL_RHCLKRST_ACTIVE 0x00000001u + + #define _MCASP_RGBLCTL_RCLKRST_MASK 0x00000001u + #define _MCASP_RGBLCTL_RCLKRST_SHIFT 0x00000000u + #define MCASP_RGBLCTL_RCLKRST_DEFAULT 0x00000000u + #define MCASP_RGBLCTL_RCLKRST_OF(x) _VALUEOF(x) + #define MCASP_RGBLCTL_RCLKRST_RESET 0x00000000u + #define MCASP_RGBLCTL_RCLKRST_ACTIVE 0x00000001u + + + #define MCASP_RGBLCTL_OF(x) _VALUEOF(x) + + #define MCASP_RGBLCTL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,RGBLCTL,RFRST)\ + |_PER_FDEFAULT(MCASP,RGBLCTL,RSMRST)\ + |_PER_FDEFAULT(MCASP,RGBLCTL,RSRCLR)\ + |_PER_FDEFAULT(MCASP,RGBLCTL,RHCLKRST)\ + |_PER_FDEFAULT(MCASP,RGBLCTL,RCLKRST)\ + ) + + + #define MCASP_RGBLCTL_RMK(rfrst, rsmrst, rsrclr, rhclkrst, rclkrst) (Uint32)( \ + _PER_FMK(MCASP,RGBLCTL,RFRST,rfrst)\ + |_PER_FMK(MCASP,RGBLCTL,RSMRST,rsmrst)\ + |_PER_FMK(MCASP,RGBLCTL,RSRCLR,rsrclr)\ + |_PER_FMK(MCASP,RGBLCTL,RHCLKRST,rhclkrst)\ + |_PER_FMK(MCASP,RGBLCTL,RCLKRST,rclkrst)\ + ) + + + #define _MCASP_RGBLCTL_FGET(N,FIELD)\ + _PER_FGET(_MCASP_RGBLCTL##N##_ADDR,MCASP,RGBLCTL,##FIELD) + + #define _MCASP_RGBLCTL_FSET(N,FIELD,field)\ + _PER_FSET(_MCASP_RGBLCTL##N##_ADDR,MCASP,RGBLCTL,##FIELD,field) + + #define _MCASP_RGBLCTL_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCASP_RGBLCTL##N##_ADDR,MCASP,RGBLCTL,##FIELD,##SYM) + + #define _MCASP_RGBLCTL0_FGET(FIELD) _MCASP_RGBLCTL_FGET(0,##FIELD) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_RGBLCTL1_FGET(FIELD) _MCASP_RGBLCTL_FGET(1,##FIELD) +#endif + + #define _MCASP_RGBLCTL0_FSET(FIELD,f) _MCASP_RGBLCTL_FSET(0,##FIELD,f) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_RGBLCTL1_FSET(FIELD,f) _MCASP_RGBLCTL_FSET(1,##FIELD,f) +#endif + + #define _MCASP_RGBLCTL0_FSETS(FIELD,SYM) _MCASP_RGBLCTL_FSETS(0,##FIELD,##SYM) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_RGBLCTL1_FSETS(FIELD,SYM) _MCASP_RGBLCTL_FSETS(1,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* +* _____________________ +* | | +* | RMASK | +* |___________________| +* +* RMASK - Pin Data Output Register +* +* FIELDS (msb -> lsb) +* (rw) RMASKn n:0 to 31 +* +\******************************************************************************/ + + #define _MCASP_RMASK_OFFSET 25 + + #define _MCASP_RMASK0_ADDR (_MCASP_BASE_PORT0+4*_MCASP_RMASK_OFFSET) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_RMASK1_ADDR (_MCASP_BASE_PORT1+4*_MCASP_RMASK_OFFSET) +#endif + + #define _MCASP_RMASK_RMASK0_MASK 0x00000001u + #define _MCASP_RMASK_RMASK0_SHIFT 0x00000000u + #define MCASP_RMASK_RMASK0_DEFAULT 0x00000000u + #define MCASP_RMASK_RMASK0_OF(x) _VALUEOF(x) + #define MCASP_RMASK_RMASK0_USEMASK 0x00000000u + #define MCASP_RMASK_RMASK0_NOMASK 0x00000001u + + #define _MCASP_RMASK_RMASK1_MASK 0x00000002u + #define _MCASP_RMASK_RMASK1_SHIFT 0x00000001u + #define MCASP_RMASK_RMASK1_DEFAULT 0x00000000u + #define MCASP_RMASK_RMASK1_OF(x) _VALUEOF(x) + #define MCASP_RMASK_RMASK1_USEMASK 0x00000000u + #define MCASP_RMASK_RMASK1_NOMASK 0x00000001u + + #define _MCASP_RMASK_RMASK2_MASK 0x00000004u + #define _MCASP_RMASK_RMASK2_SHIFT 0x00000002u + #define MCASP_RMASK_RMASK2_DEFAULT 0x00000000u + #define MCASP_RMASK_RMASK2_OF(x) _VALUEOF(x) + #define MCASP_RMASK_RMASK2_USEMASK 0x00000000u + #define MCASP_RMASK_RMASK2_NOMASK 0x00000001u + + #define _MCASP_RMASK_RMASK3_MASK 0x00000008u + #define _MCASP_RMASK_RMASK3_SHIFT 0x00000003u + #define MCASP_RMASK_RMASK3_DEFAULT 0x00000000u + #define MCASP_RMASK_RMASK3_OF(x) _VALUEOF(x) + #define MCASP_RMASK_RMASK3_USEMASK 0x00000000u + #define MCASP_RMASK_RMASK3_NOMASK 0x00000001u + + #define _MCASP_RMASK_RMASK4_MASK 0x00000010u + #define _MCASP_RMASK_RMASK4_SHIFT 0x00000004u + #define MCASP_RMASK_RMASK4_DEFAULT 0x00000000u + #define MCASP_RMASK_RMASK4_OF(x) _VALUEOF(x) + #define MCASP_RMASK_RMASK4_USEMASK 0x00000000u + #define MCASP_RMASK_RMASK4_NOMASK 0x00000001u + + #define _MCASP_RMASK_RMASK5_MASK 0x00000020u + #define _MCASP_RMASK_RMASK5_SHIFT 0x00000005u + #define MCASP_RMASK_RMASK5_DEFAULT 0x00000000u + #define MCASP_RMASK_RMASK5_OF(x) _VALUEOF(x) + #define MCASP_RMASK_RMASK5_USEMASK 0x00000000u + #define MCASP_RMASK_RMASK5_NOMASK 0x00000001u + + #define _MCASP_RMASK_RMASK6_MASK 0x00000040u + #define _MCASP_RMASK_RMASK6_SHIFT 0x00000006u + #define MCASP_RMASK_RMASK6_DEFAULT 0x00000000u + #define MCASP_RMASK_RMASK6_OF(x) _VALUEOF(x) + #define MCASP_RMASK_RMASK6_USEMASK 0x00000000u + #define MCASP_RMASK_RMASK6_NOMASK 0x00000001u + + #define _MCASP_RMASK_RMASK7_MASK 0x00000080u + #define _MCASP_RMASK_RMASK7_SHIFT 0x00000007u + #define MCASP_RMASK_RMASK7_DEFAULT 0x00000000u + #define MCASP_RMASK_RMASK7_OF(x) _VALUEOF(x) + #define MCASP_RMASK_RMASK7_USEMASK 0x00000000u + #define MCASP_RMASK_RMASK7_NOMASK 0x00000001u + + #define _MCASP_RMASK_RMASK8_MASK 0x00000100u + #define _MCASP_RMASK_RMASK8_SHIFT 0x00000008u + #define MCASP_RMASK_RMASK8_DEFAULT 0x00000000u + #define MCASP_RMASK_RMASK8_OF(x) _VALUEOF(x) + #define MCASP_RMASK_RMASK8_USEMASK 0x00000000u + #define MCASP_RMASK_RMASK8_NOMASK 0x00000001u + + #define _MCASP_RMASK_RMASK9_MASK 0x00000200u + #define _MCASP_RMASK_RMASK9_SHIFT 0x00000009u + #define MCASP_RMASK_RMASK9_DEFAULT 0x00000000u + #define MCASP_RMASK_RMASK9_OF(x) _VALUEOF(x) + #define MCASP_RMASK_RMASK9_USEMASK 0x00000000u + #define MCASP_RMASK_RMASK9_NOMASK 0x00000001u + + #define _MCASP_RMASK_RMASK10_MASK 0x00000400u + #define _MCASP_RMASK_RMASK10_SHIFT 0x0000000Au + #define MCASP_RMASK_RMASK10_DEFAULT 0x00000000u + #define MCASP_RMASK_RMASK10_OF(x) _VALUEOF(x) + #define MCASP_RMASK_RMASK10_USEMASK 0x00000000u + #define MCASP_RMASK_RMASK10_NOMASK 0x00000001u + + #define _MCASP_RMASK_RMASK11_MASK 0x00000800u + #define _MCASP_RMASK_RMASK11_SHIFT 0x0000000Bu + #define MCASP_RMASK_RMASK11_DEFAULT 0x00000000u + #define MCASP_RMASK_RMASK11_OF(x) _VALUEOF(x) + #define MCASP_RMASK_RMASK11_USEMASK 0x00000000u + #define MCASP_RMASK_RMASK11_NOMASK 0x00000001u + + #define _MCASP_RMASK_RMASK12_MASK 0x00001000u + #define _MCASP_RMASK_RMASK12_SHIFT 0x0000000Cu + #define MCASP_RMASK_RMASK12_DEFAULT 0x00000000u + #define MCASP_RMASK_RMASK12_OF(x) _VALUEOF(x) + #define MCASP_RMASK_RMASK12_USEMASK 0x00000000u + #define MCASP_RMASK_RMASK12_NOMASK 0x00000001u + + #define _MCASP_RMASK_RMASK13_MASK 0x00002000u + #define _MCASP_RMASK_RMASK13_SHIFT 0x0000000Du + #define MCASP_RMASK_RMASK13_DEFAULT 0x00000000u + #define MCASP_RMASK_RMASK13_OF(x) _VALUEOF(x) + #define MCASP_RMASK_RMASK13_USEMASK 0x00000000u + #define MCASP_RMASK_RMASK13_NOMASK 0x00000001u + + #define _MCASP_RMASK_RMASK14_MASK 0x00004000u + #define _MCASP_RMASK_RMASK14_SHIFT 0x0000000Eu + #define MCASP_RMASK_RMASK14_DEFAULT 0x00000000u + #define MCASP_RMASK_RMASK14_OF(x) _VALUEOF(x) + #define MCASP_RMASK_RMASK14_USEMASK 0x00000000u + #define MCASP_RMASK_RMASK14_NOMASK 0x00000001u + + #define _MCASP_RMASK_RMASK15_MASK 0x00008000u + #define _MCASP_RMASK_RMASK15_SHIFT 0x0000000Fu + #define MCASP_RMASK_RMASK15_DEFAULT 0x00000000u + #define MCASP_RMASK_RMASK15_OF(x) _VALUEOF(x) + #define MCASP_RMASK_RMASK15_USEMASK 0x00000000u + #define MCASP_RMASK_RMASK15_NOMASK 0x00000001u + + #define _MCASP_RMASK_RMASK16_MASK 0x00010000u + #define _MCASP_RMASK_RMASK16_SHIFT 0x00000010u + #define MCASP_RMASK_RMASK16_DEFAULT 0x00000000u + #define MCASP_RMASK_RMASK16_OF(x) _VALUEOF(x) + #define MCASP_RMASK_RMASK16_USEMASK 0x00000000u + #define MCASP_RMASK_RMASK16_NOMASK 0x00000001u + + #define _MCASP_RMASK_RMASK17_MASK 0x00020000u + #define _MCASP_RMASK_RMASK17_SHIFT 0x00000011u + #define MCASP_RMASK_RMASK17_DEFAULT 0x00000000u + #define MCASP_RMASK_RMASK17_OF(x) _VALUEOF(x) + #define MCASP_RMASK_RMASK17_USEMASK 0x00000000u + #define MCASP_RMASK_RMASK17_NOMASK 0x00000001u + + #define _MCASP_RMASK_RMASK18_MASK 0x00040000u + #define _MCASP_RMASK_RMASK18_SHIFT 0x00000012u + #define MCASP_RMASK_RMASK18_DEFAULT 0x00000000u + #define MCASP_RMASK_RMASK18_OF(x) _VALUEOF(x) + #define MCASP_RMASK_RMASK18_USEMASK 0x00000000u + #define MCASP_RMASK_RMASK18_NOMASK 0x00000001u + + #define _MCASP_RMASK_RMASK19_MASK 0x00080000u + #define _MCASP_RMASK_RMASK19_SHIFT 0x00000013u + #define MCASP_RMASK_RMASK19_DEFAULT 0x00000000u + #define MCASP_RMASK_RMASK19_OF(x) _VALUEOF(x) + #define MCASP_RMASK_RMASK19_USEMASK 0x00000000u + #define MCASP_RMASK_RMASK19_NOMASK 0x00000001u + + #define _MCASP_RMASK_RMASK20_MASK 0x00100000u + #define _MCASP_RMASK_RMASK20_SHIFT 0x00000014u + #define MCASP_RMASK_RMASK20_DEFAULT 0x00000000u + #define MCASP_RMASK_RMASK20_OF(x) _VALUEOF(x) + #define MCASP_RMASK_RMASK20_USEMASK 0x00000000u + #define MCASP_RMASK_RMASK20_NOMASK 0x00000001u + + #define _MCASP_RMASK_RMASK21_MASK 0x00200000u + #define _MCASP_RMASK_RMASK21_SHIFT 0x00000015u + #define MCASP_RMASK_RMASK21_DEFAULT 0x00000000u + #define MCASP_RMASK_RMASK21_OF(x) _VALUEOF(x) + #define MCASP_RMASK_RMASK21_USEMASK 0x00000000u + #define MCASP_RMASK_RMASK21_NOMASK 0x00000001u + + #define _MCASP_RMASK_RMASK22_MASK 0x00400000u + #define _MCASP_RMASK_RMASK22_SHIFT 0x00000016u + #define MCASP_RMASK_RMASK22_DEFAULT 0x00000000u + #define MCASP_RMASK_RMASK22_OF(x) _VALUEOF(x) + #define MCASP_RMASK_RMASK22_USEMASK 0x00000000u + #define MCASP_RMASK_RMASK22_NOMASK 0x00000001u + + #define _MCASP_RMASK_RMASK23_MASK 0x00800000u + #define _MCASP_RMASK_RMASK23_SHIFT 0x00000017u + #define MCASP_RMASK_RMASK23_DEFAULT 0x00000000u + #define MCASP_RMASK_RMASK23_OF(x) _VALUEOF(x) + #define MCASP_RMASK_RMASK23_USEMASK 0x00000000u + #define MCASP_RMASK_RMASK23_NOMASK 0x00000001u + + #define _MCASP_RMASK_RMASK24_MASK 0x01000000u + #define _MCASP_RMASK_RMASK24_SHIFT 0x00000018u + #define MCASP_RMASK_RMASK24_DEFAULT 0x00000000u + #define MCASP_RMASK_RMASK24_OF(x) _VALUEOF(x) + #define MCASP_RMASK_RMASK24_USEMASK 0x00000000u + #define MCASP_RMASK_RMASK24_NOMASK 0x00000001u + + #define _MCASP_RMASK_RMASK25_MASK 0x02000000u + #define _MCASP_RMASK_RMASK25_SHIFT 0x00000019u + #define MCASP_RMASK_RMASK25_DEFAULT 0x00000000u + #define MCASP_RMASK_RMASK25_OF(x) _VALUEOF(x) + #define MCASP_RMASK_RMASK25_USEMASK 0x00000000u + #define MCASP_RMASK_RMASK25_NOMASK 0x00000001u + + #define _MCASP_RMASK_RMASK26_MASK 0x04000000u + #define _MCASP_RMASK_RMASK26_SHIFT 0x0000001Au + #define MCASP_RMASK_RMASK26_DEFAULT 0x00000000u + #define MCASP_RMASK_RMASK26_OF(x) _VALUEOF(x) + #define MCASP_RMASK_RMASK26_USEMASK 0x00000000u + #define MCASP_RMASK_RMASK26_NOMASK 0x00000001u + + #define _MCASP_RMASK_RMASK27_MASK 0x08000000u + #define _MCASP_RMASK_RMASK27_SHIFT 0x0000001Bu + #define MCASP_RMASK_RMASK27_DEFAULT 0x00000000u + #define MCASP_RMASK_RMASK27_OF(x) _VALUEOF(x) + #define MCASP_RMASK_RMASK27_USEMASK 0x00000000u + #define MCASP_RMASK_RMASK27_NOMASK 0x00000001u + + #define _MCASP_RMASK_RMASK28_MASK 0x10000000u + #define _MCASP_RMASK_RMASK28_SHIFT 0x0000001Cu + #define MCASP_RMASK_RMASK28_DEFAULT 0x00000000u + #define MCASP_RMASK_RMASK28_OF(x) _VALUEOF(x) + #define MCASP_RMASK_RMASK28_USEMASK 0x00000000u + #define MCASP_RMASK_RMASK28_NOMASK 0x00000001u + + #define _MCASP_RMASK_RMASK29_MASK 0x20000000u + #define _MCASP_RMASK_RMASK29_SHIFT 0x0000001Du + #define MCASP_RMASK_RMASK29_DEFAULT 0x00000000u + #define MCASP_RMASK_RMASK29_OF(x) _VALUEOF(x) + #define MCASP_RMASK_RMASK29_USEMASK 0x00000000u + #define MCASP_RMASK_RMASK29_NOMASK 0x00000001u + + #define _MCASP_RMASK_RMASK30_MASK 0x40000000u + #define _MCASP_RMASK_RMASK30_SHIFT 0x0000001Eu + #define MCASP_RMASK_RMASK30_DEFAULT 0x00000000u + #define MCASP_RMASK_RMASK30_OF(x) _VALUEOF(x) + #define MCASP_RMASK_RMASK30_USEMASK 0x00000000u + #define MCASP_RMASK_RMASK30_NOMASK 0x00000001u + + #define _MCASP_RMASK_RMASK31_MASK 0x80000000u + #define _MCASP_RMASK_RMASK31_SHIFT 0x0000001Fu + #define MCASP_RMASK_RMASK31_DEFAULT 0x00000000u + #define MCASP_RMASK_RMASK31_OF(x) _VALUEOF(x) + #define MCASP_RMASK_RMASK31_USEMASK 0x00000000u + #define MCASP_RMASK_RMASK31_NOMASK 0x00000001u + + + + #define MCASP_RMASK_OF(x) _VALUEOF(x) + + #define MCASP_RMASK_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,RMASK,RMASK0)\ + |_PER_FDEFAULT(MCASP,RMASK,RMASK1)\ + |_PER_FDEFAULT(MCASP,RMASK,RMASK2)\ + |_PER_FDEFAULT(MCASP,RMASK,RMASK3)\ + |_PER_FDEFAULT(MCASP,RMASK,RMASK4)\ + |_PER_FDEFAULT(MCASP,RMASK,RMASK5)\ + |_PER_FDEFAULT(MCASP,RMASK,RMASK6)\ + |_PER_FDEFAULT(MCASP,RMASK,RMASK7)\ + |_PER_FDEFAULT(MCASP,RMASK,RMASK8)\ + |_PER_FDEFAULT(MCASP,RMASK,RMASK9)\ + |_PER_FDEFAULT(MCASP,RMASK,RMASK10)\ + |_PER_FDEFAULT(MCASP,RMASK,RMASK11)\ + |_PER_FDEFAULT(MCASP,RMASK,RMASK12)\ + |_PER_FDEFAULT(MCASP,RMASK,RMASK13)\ + |_PER_FDEFAULT(MCASP,RMASK,RMASK14)\ + |_PER_FDEFAULT(MCASP,RMASK,RMASK15)\ + |_PER_FDEFAULT(MCASP,RMASK,RMASK16)\ + |_PER_FDEFAULT(MCASP,RMASK,RMASK17)\ + |_PER_FDEFAULT(MCASP,RMASK,RMASK18)\ + |_PER_FDEFAULT(MCASP,RMASK,RMASK19)\ + |_PER_FDEFAULT(MCASP,RMASK,RMASK20)\ + |_PER_FDEFAULT(MCASP,RMASK,RMASK21)\ + |_PER_FDEFAULT(MCASP,RMASK,RMASK22)\ + |_PER_FDEFAULT(MCASP,RMASK,RMASK23)\ + |_PER_FDEFAULT(MCASP,RMASK,RMASK24)\ + |_PER_FDEFAULT(MCASP,RMASK,RMASK25)\ + |_PER_FDEFAULT(MCASP,RMASK,RMASK26)\ + |_PER_FDEFAULT(MCASP,RMASK,RMASK27)\ + |_PER_FDEFAULT(MCASP,RMASK,RMASK28)\ + |_PER_FDEFAULT(MCASP,RMASK,RMASK29)\ + |_PER_FDEFAULT(MCASP,RMASK,RMASK30)\ + |_PER_FDEFAULT(MCASP,RMASK,RMASK31)\ + ) + + #define MCASP_RMASK_RMK(rmask31, rmask30,rmask29,rmask28,rmask27,rmask26,rmask25,\ + rmask24,rmask23,rmask22,rmask21,rmask20,rmask19,rmask18,rmask17,\ + rmask16,rmask15,rmask14,rmask13,rmask12,rmask11,rmask10,rmask9,\ + rmask8, rmask7, rmask6, rmask5,rmask4, rmask3, rmask2, rmask1, rmask0 ) \ +(Uint32)( \ + _PER_FMK(MCASP,RMASK,RMASK0,rmask0)\ + |_PER_FMK(MCASP,RMASK,RMASK1,rmask1)\ + |_PER_FMK(MCASP,RMASK,RMASK2,rmask2)\ + |_PER_FMK(MCASP,RMASK,RMASK3,rmask3)\ + |_PER_FMK(MCASP,RMASK,RMASK4,rmask4)\ + |_PER_FMK(MCASP,RMASK,RMASK5,rmask5)\ + |_PER_FMK(MCASP,RMASK,RMASK6,rmask6)\ + |_PER_FMK(MCASP,RMASK,RMASK7,rmask7)\ + |_PER_FMK(MCASP,RMASK,RMASK8,rmask8)\ + |_PER_FMK(MCASP,RMASK,RMASK9,rmask9)\ + |_PER_FMK(MCASP,RMASK,RMASK10,rmask10)\ + |_PER_FMK(MCASP,RMASK,RMASK11,rmask11)\ + |_PER_FMK(MCASP,RMASK,RMASK12,rmask12)\ + |_PER_FMK(MCASP,RMASK,RMASK13,rmask13)\ + |_PER_FMK(MCASP,RMASK,RMASK14,rmask14)\ + |_PER_FMK(MCASP,RMASK,RMASK15,rmask15)\ + |_PER_FMK(MCASP,RMASK,RMASK16,rmask16)\ + |_PER_FMK(MCASP,RMASK,RMASK17,rmask17)\ + |_PER_FMK(MCASP,RMASK,RMASK18,rmask18)\ + |_PER_FMK(MCASP,RMASK,RMASK19,rmask19)\ + |_PER_FMK(MCASP,RMASK,RMASK20,rmask20)\ + |_PER_FMK(MCASP,RMASK,RMASK21,rmask21)\ + |_PER_FMK(MCASP,RMASK,RMASK22,rmask22)\ + |_PER_FMK(MCASP,RMASK,RMASK23,rmask23)\ + |_PER_FMK(MCASP,RMASK,RMASK24,rmask24)\ + |_PER_FMK(MCASP,RMASK,RMASK25,rmask25)\ + |_PER_FMK(MCASP,RMASK,RMASK26,rmask26)\ + |_PER_FMK(MCASP,RMASK,RMASK27,rmask27)\ + |_PER_FMK(MCASP,RMASK,RMASK28,rmask28)\ + |_PER_FMK(MCASP,RMASK,RMASK29,rmask29)\ + |_PER_FMK(MCASP,RMASK,RMASK30,rmask30)\ + |_PER_FMK(MCASP,RMASK,RMASK31,rmask31)\ + ) + + #define _MCASP_RMASK_FGET(N,FIELD)\ + _PER_FGET(_MCASP_RMASK##N##_ADDR,MCASP,RMASK,##FIELD) + + #define _MCASP_RMASK_FSET(N,FIELD,field)\ + _PER_FSET(_MCASP_RMASK##N##_ADDR,MCASP,RMASK,##FIELD,field) + + #define _MCASP_RMASK_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCASP_RMASK##N##_ADDR,MCASP,RMASK,##FIELD,##SYM) + + #define _MCASP_RMASK0_FGET(FIELD) _MCASP_RMASK_FGET(0,##FIELD) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_RMASK1_FGET(FIELD) _MCASP_RMASK_FGET(1,##FIELD) +#endif + + #define _MCASP_RMASK0_FSET(FIELD,f) _MCASP_RMASK_FSET(0,##FIELD,f) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_RMASK1_FSET(FIELD,f) _MCASP_RMASK_FSET(1,##FIELD,f) +#endif + + #define _MCASP_RMASK0_FSETS(FIELD,SYM) _MCASP_RMASK_FSETS(0,##FIELD,##SYM) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_RMASK1_FSETS(FIELD,SYM) _MCASP_RMASK_FSETS(1,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* +* _____________________ +* | | +* | RFMT | +* |___________________| +* +* RFMT - Receive Bitstream Format Register +* +* FIELDS (msb -> lsb) +* (rw) RDATDLY +* (rw) RRVRS +* (rw) RPAD +* (rw) RPBIT +* (rw) RSSZ +* (rw) RBUSEL +* (rw) RROT +* +\******************************************************************************/ + + #define _MCASP_RFMT_OFFSET 26 + + #define _MCASP_RFMT0_ADDR (_MCASP_BASE_PORT0+4*_MCASP_RFMT_OFFSET) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_RFMT1_ADDR (_MCASP_BASE_PORT1+4*_MCASP_RFMT_OFFSET) +#endif + + #define _MCASP_RFMT_RDATDLY_MASK 0x00030000u + #define _MCASP_RFMT_RDATDLY_SHIFT 0x00000010u + #define MCASP_RFMT_RDATDLY_DEFAULT 0x00000000u + #define MCASP_RFMT_RDATDLY_OF(x) _VALUEOF(x) + #define MCASP_RFMT_RDATDLY_0BIT 0x00000000u + #define MCASP_RFMT_RDATDLY_1BIT 0x00000001u + #define MCASP_RFMT_RDATDLY_2BIT 0x00000002u + + + #define _MCASP_RFMT_RRVRS_MASK 0x00008000u + #define _MCASP_RFMT_RRVRS_SHIFT 0x0000000Fu + #define MCASP_RFMT_RRVRS_DEFAULT 0x00000000u + #define MCASP_RFMT_RRVRS_OF(x) _VALUEOF(x) + #define MCASP_RFMT_RRVRS_LSBFIRST 0x00000000u + #define MCASP_RFMT_RRVRS_MSBFIRST 0x00000001u + + #define _MCASP_RFMT_RPAD_MASK 0x00006000u + #define _MCASP_RFMT_RPAD_SHIFT 0x0000000Du + #define MCASP_RFMT_RPAD_DEFAULT 0x00000000u + #define MCASP_RFMT_RPAD_OF(x) _VALUEOF(x) + #define MCASP_RFMT_RPAD_ZERO 0x00000000u + #define MCASP_RFMT_RPAD_ONE 0x00000001u + #define MCASP_RFMT_RPAD_RPBIT 0x00000002u + + #define _MCASP_RFMT_RPBIT_MASK 0x00001F00u + #define _MCASP_RFMT_RPBIT_SHIFT 0x00000008u + #define MCASP_RFMT_RPBIT_DEFAULT 0x00000000u + #define MCASP_RFMT_RPBIT_OF(x) _VALUEOF(x) + + #define _MCASP_RFMT_RSSZ_MASK 0x000000F0u + #define _MCASP_RFMT_RSSZ_SHIFT 0x00000004u + #define MCASP_RFMT_RSSZ_DEFAULT 0x00000000u + #define MCASP_RFMT_RSSZ_OF(x) _VALUEOF(x) + #define MCASP_RFMT_RSSZ_8BITS 0x00000003u + #define MCASP_RFMT_RSSZ_12BITS 0x00000005u + #define MCASP_RFMT_RSSZ_16BITS 0x00000007u + #define MCASP_RFMT_RSSZ_20BITS 0x00000009u + #define MCASP_RFMT_RSSZ_24BITS 0x0000000Bu + #define MCASP_RFMT_RSSZ_28BITS 0x0000000Du + #define MCASP_RFMT_RSSZ_32BITS 0x0000000Fu + + #define _MCASP_RFMT_RBUSEL_MASK 0x00000008u + #define _MCASP_RFMT_RBUSEL_SHIFT 0x00000003u + #define MCASP_RFMT_RBUSEL_DEFAULT 0x00000000u + #define MCASP_RFMT_RBUSEL_OF(x) _VALUEOF(x) + #define MCASP_RFMT_RBUSEL_DAT 0x00000000u + #define MCASP_RFMT_RBUSEL_CFG 0x00000001u + + + #define _MCASP_RFMT_RROT_MASK 0x00000007u + #define _MCASP_RFMT_RROT_SHIFT 0x00000000u + #define MCASP_RFMT_RROT_DEFAULT 0x00000000u + #define MCASP_RFMT_RROT_OF(x) _VALUEOF(x) + #define MCASP_RFMT_RROT_NONE 0x00000000u + #define MCASP_RFMT_RROT_4BITS 0x00000001u + #define MCASP_RFMT_RROT_8BITS 0x00000002u + #define MCASP_RFMT_RROT_12BITS 0x00000003u + #define MCASP_RFMT_RROT_16BITS 0x00000004u + #define MCASP_RFMT_RROT_20BITS 0x00000005u + #define MCASP_RFMT_RROT_24BITS 0x00000006u + #define MCASP_RFMT_RROT_28BITS 0x00000007u + + #define MCASP_RFMT_OF(x) _VALUEOF(x) + + #define MCASP_RFMT_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,RFMT,RDATDLY)\ + |_PER_FDEFAULT(MCASP,RFMT,RRVRS)\ + |_PER_FDEFAULT(MCASP,RFMT,RPAD)\ + |_PER_FDEFAULT(MCASP,RFMT,RPBIT)\ + |_PER_FDEFAULT(MCASP,RFMT,RSSZ)\ + |_PER_FDEFAULT(MCASP,RFMT,RBUSEL)\ + |_PER_FDEFAULT(MCASP,RFMT,RROT)\ + ) + + #define MCASP_RFMT_RMK(rdatdly,rrvrs,rpad,rpbit,rssz,rbusel,rrot) (Uint32)( \ + _PER_FMK(MCASP,RFMT,RDATDLY,rdatdly)\ + |_PER_FMK(MCASP,RFMT,RRVRS,rrvrs)\ + |_PER_FMK(MCASP,RFMT,RPAD,rpad)\ + |_PER_FMK(MCASP,RFMT,RPBIT,rpbit)\ + |_PER_FMK(MCASP,RFMT,RSSZ,rssz)\ + |_PER_FMK(MCASP,RFMT,RBUSEL,rbusel)\ + |_PER_FMK(MCASP,RFMT,RROT,rrot)\ + ) + + #define _MCASP_RFMT_FGET(N,FIELD)\ + _PER_FGET(_MCASP_RFMT##N##_ADDR,MCASP,RFMT,##FIELD) + + #define _MCASP_RFMT_FSET(N,FIELD,field)\ + _PER_FSET(_MCASP_RFMT##N##_ADDR,MCASP,RFMT,##FIELD,field) + + #define _MCASP_RFMT_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCASP_RFMT##N##_ADDR,MCASP,RFMT,##FIELD,##SYM) + + #define _MCASP_RFMT0_FGET(FIELD) _MCASP_RFMT_FGET(0,##FIELD) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_RFMT1_FGET(FIELD) _MCASP_RFMT_FGET(1,##FIELD) +#endif + + #define _MCASP_RFMT0_FSET(FIELD,f) _MCASP_RFMT_FSET(0,##FIELD,f) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_RFMT1_FSET(FIELD,f) _MCASP_RFMT_FSET(1,##FIELD,f) +#endif + + #define _MCASP_RFMT0_FSETS(FIELD,SYM) _MCASP_RFMT_FSETS(0,##FIELD,##SYM) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_RFMT1_FSETS(FIELD,SYM) _MCASP_RFMT_FSETS(1,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* +* _____________________ +* | | +* | AFSRCTL | +* |___________________| +* +* AFSRCTL - Receive Frame Control Register +* +* FIELDS (msb -> lsb) +* (rw) RMOD +* (rw) FRWID +* (rw) FSRM +* (rw) FSRP +* +\******************************************************************************/ + + #define _MCASP_AFSRCTL_OFFSET 27 + + #define _MCASP_AFSRCTL0_ADDR (_MCASP_BASE_PORT0+4*_MCASP_AFSRCTL_OFFSET) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_AFSRCTL1_ADDR (_MCASP_BASE_PORT1+4*_MCASP_AFSRCTL_OFFSET) +#endif + + #define _MCASP_AFSRCTL_RMOD_MASK 0x0000FF80u + #define _MCASP_AFSRCTL_RMOD_SHIFT 0x00000007u + #define MCASP_AFSRCTL_RMOD_DEFAULT 0x00000000u + #define MCASP_AFSRCTL_RMOD_OF(x) _VALUEOF(x) + #define MCASP_AFSRCTL_RMOD_BURST 0x00000000u + + #define _MCASP_AFSRCTL_FRWID_MASK 0x00000010u + #define _MCASP_AFSRCTL_FRWID_SHIFT 0x00000004u + #define MCASP_AFSRCTL_FRWID_DEFAULT 0x00000000u + #define MCASP_AFSRCTL_FRWID_OF(x) _VALUEOF(x) + #define MCASP_AFSRCTL_FRWID_BIT 0x00000000u + #define MCASP_AFSRCTL_FRWID_WORD 0x00000001u + + + #define _MCASP_AFSRCTL_FSRM_MASK 0x00000002u + #define _MCASP_AFSRCTL_FSRM_SHIFT 0x00000001u + #define MCASP_AFSRCTL_FSRM_DEFAULT 0x00000000u + #define MCASP_AFSRCTL_FSRM_OF(x) _VALUEOF(x) + #define MCASP_AFSRCTL_FSRM_EXTERNAL 0x00000000u + #define MCASP_AFSRCTL_FSRM_INTERNAL 0x00000001u + + + #define _MCASP_AFSRCTL_FSRP_MASK 0x00000001u + #define _MCASP_AFSRCTL_FSRP_SHIFT 0x00000000u + #define MCASP_AFSRCTL_FSRP_DEFAULT 0x00000000u + #define MCASP_AFSRCTL_FSRP_OF(x) _VALUEOF(x) + #define MCASP_AFSRCTL_FSRP_ACTIVEHIGH 0x00000000u + #define MCASP_AFSRCTL_FSRP_ACTIVELOW 0x00000001u + + + #define MCASP_AFSRCTL_OF(x) _VALUEOF(x) + + #define MCASP_AFSRCTL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,AFSRCTL,RMOD)\ + | _PER_FDEFAULT(MCASP,AFSRCTL,FRWID)\ + | _PER_FDEFAULT(MCASP,AFSRCTL,FSRM)\ + | _PER_FDEFAULT(MCASP,AFSRCTL,FSRP)\ + ) + + #define MCASP_AFSRCTL_RMK(rmod, frwid, fsrm, fsrp) (Uint32)( \ + _PER_FMK(MCASP,AFSRCTL,RMOD,rmod)\ + | _PER_FMK(MCASP,AFSRCTL,FRWID,frwid)\ + | _PER_FMK(MCASP,AFSRCTL,FSRM,fsrm)\ + | _PER_FMK(MCASP,AFSRCTL,FSRP,fsrp)\ + ) + + #define _MCASP_AFSRCTL_FGET(N,FIELD)\ + _PER_FGET(_MCASP_AFSRCTL##N##_ADDR,MCASP,AFSRCTL,##FIELD) + + #define _MCASP_AFSRCTL_FSET(N,FIELD,field)\ + _PER_FSET(_MCASP_AFSRCTL##N##_ADDR,MCASP,AFSRCTL,##FIELD,field) + + #define _MCASP_AFSRCTL_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCAS_AFSRCTL##N##_ADDR,MCASP,AFSRCTL,##FIELD,##SYM) + + #define _MCASP_AFSRCTL0_FGET(FIELD) _MCASP_AFSRCTL_FGET(0,##FIELD) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_AFSRCTL1_FGET(FIELD) _MCASP_AFSRCTL_FGET(1,##FIELD) +#endif + + #define _MCASP_AFSRCTL0_FSET(FIELD,f) _MCASP_AFSRCTL_FSET(0,##FIELD,f) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_AFSRCTL1_FSET(FIELD,f) _MCASP_AFSRCTL_FSET(1,##FIELD,f) +#endif + + #define _MCASP_AFSRCTL0_FSETS(FIELD,SYM) _MCASP_AFSRCTL_FSETS(0,##FIELD,##SYM) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_AFSRCTL1_FSETS(FIELD,SYM) _MCASP_AFSRCTL_FSETS(1,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* +* _____________________ +* | | +* | ACLKRCTL | +* |___________________| +* +* ACLKRCTL - Receive Clock Control Register +* +* FIELDS (msb -> lsb) +* (rw) CLKRP +* (rw) CLKRM +* (rw) CLKRDIV +* +\******************************************************************************/ + + #define _MCASP_ACLKRCTL_OFFSET 28 + + #define _MCASP_ACLKRCTL0_ADDR (_MCASP_BASE_PORT0+4*_MCASP_ACLKRCTL_OFFSET) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_ACLKRCTL1_ADDR (_MCASP_BASE_PORT1+4*_MCASP_ACLKRCTL_OFFSET) +#endif + + #define _MCASP_ACLKRCTL_CLKRP_MASK 0x00000080u + #define _MCASP_ACLKRCTL_CLKRP_SHIFT 0x00000007u + #define MCASP_ACLKRCTL_CLKRP_DEFAULT 0x00000000u + #define MCASP_ACLKRCTL_CLKRP_OF(x) _VALUEOF(x) + #define MCASP_ACLKRCTL_CLKRP_RISING 0x00000001u + #define MCASP_ACLKRCTL_CLKRP_FALLING 0x00000000u + + + #define _MCASP_ACLKRCTL_CLKRM_MASK 0x00000020u + #define _MCASP_ACLKRCTL_CLKRM_SHIFT 0x00000005u + #define MCASP_ACLKRCTL_CLKRM_DEFAULT 0x00000001u + #define MCASP_ACLKRCTL_CLKRM_OF(x) _VALUEOF(x) + #define MCASP_ACLKRCTL_CLKRM_EXTERNAL 0x00000000u + #define MCASP_ACLKRCTL_CLKRM_INTERNAL 0x00000001u + + + #define _MCASP_ACLKRCTL_CLKRDIV_MASK 0x0000001Fu + #define _MCASP_ACLKRCTL_CLKRDIV_SHIFT 0x00000000u + #define MCASP_ACLKRCTL_CLKRDIV_DEFAULT 0x00000000u + #define MCASP_ACLKRCTL_CLKRDIV_OF(x) _VALUEOF(x) + + #define MCASP_ACLKRCTL_OF(x) _VALUEOF(x) + + #define MCASP_ACLKRCTL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,ACLKRCTL,CLKRP)\ + | _PER_FDEFAULT(MCASP,ACLKRCTL,CLKRM)\ + | _PER_FDEFAULT(MCASP,ACLKRCTL,CLKRDIV)\ + ) + + #define MCASP_ACLKRCTL_RMK(clkrp, clkrm, clkrdiv) (Uint32)( \ + _PER_FMK(MCASP,ACLKRCTL,CLKRP,clkrp)\ + | _PER_FMK(MCASP,ACLKRCTL,CLKRM,clkrm)\ + | _PER_FMK(MCASP,ACLKRCTL,CLKRDIV,clkrdiv)\ + ) + + + #define _MCASP_ACLKRCTL_FGET(N,FIELD)\ + _PER_FGET(_MCASP_ACLKRCTL##N##_ADDR,MCASP,ACLKRCTL,##FIELD) + + #define _MCASP_ACLKRCTL_FSET(N,FIELD,field)\ + _PER_FSET(_MCASP_ACLKRCTL##N##_ADDR,MCASP,ACLKRCTL,##FIELD,field) + + #define _MCASP_ACLKRCTL_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCASP_ACLKRCTL##N##_ADDR,MCASP,ACLKRCTL,##FIELD,##SYM) + + #define _MCASP_ACLKRCTL0_FGET(FIELD) _MCASP_ACLKRCTL_FGET(0,##FIELD) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_ACLKRCTL1_FGET(FIELD) _MCASP_ACLKRCTL_FGET(1,##FIELD) +#endif + + #define _MCASP_ACLKRCTL0_FSET(FIELD,f) _MCASP_ACLKRCTL_FSET(0,##FIELD,f) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_ACLKRCTL1_FSET(FIELD,f) _MCASP_ACLKRCTL_FSET(1,##FIELD,f) +#endif + + #define _MCASP_ACLKRCTL0_FSETS(FIELD,SYM) _MCASP_ACLKRCTL_FSETS(0,##FIELD,##SYM) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_ACLKRCTL1_FSETS(FIELD,SYM) _MCASP_ACLKRCTL_FSETS(1,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* +* _____________________ +* | | +* | AHCLKRCTL | +* |___________________| +* +* AHCLKRCTL - High Frequency Receive Clock Control Register +* +* FIELDS (msb -> lsb) +* (rw) HCLKRM +* (rw) HCLKRP +* (rw) HCLKRDIV +* +\******************************************************************************/ + + #define _MCASP_AHCLKRCTL_OFFSET 29 + + #define _MCASP_AHCLKRCTL0_ADDR (_MCASP_BASE_PORT0+4*_MCASP_AHCLKRCTL_OFFSET) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_AHCLKRCTL1_ADDR (_MCASP_BASE_PORT1+4*_MCASP_AHCLKRCTL_OFFSET) +#endif + + #define _MCASP_AHCLKRCTL_HCLKRM_MASK 0x00008000u + #define _MCASP_AHCLKRCTL_HCLKRM_SHIFT 0x0000000Fu + #define MCASP_AHCLKRCTL_HCLKRM_DEFAULT 0x00000001u + #define MCASP_AHCLKRCTL_HCLKRM_OF(x) _VALUEOF(x) + #define MCASP_AHCLKRCTL_HCLKRM_EXTERNAL 0x00000000u + #define MCASP_AHCLKRCTL_HCLKRM_INTERNAL 0x00000001u + + #define _MCASP_AHCLKRCTL_HCLKRP_MASK 0x00004000u + #define _MCASP_AHCLKRCTL_HCLKRP_SHIFT 0x0000000Eu + #define MCASP_AHCLKRCTL_HCLKRP_DEFAULT 0x00000000u + #define MCASP_AHCLKRCTL_HCLKRP_OF(x) _VALUEOF(x) + #define MCASP_AHCLKRCTL_HCLKRP_RISING 0x00000000u + #define MCASP_AHCLKRCTL_HCLKRP_FALLING 0x00000001u + + #define _MCASP_AHCLKRCTL_HCLKRDIV_MASK 0x00000FFFu + #define _MCASP_AHCLKRCTL_HCLKRDIV_SHIFT 0x00000000u + #define MCASP_AHCLKRCTL_HCLKRDIV_DEFAULT 0x00000000u + #define MCASP_AHCLKRCTL_HCLKRDIV_OF(x) _VALUEOF(x) + + + #define MCASP_AHCLKRCTL_OF(x) _VALUEOF(x) + + #define MCASP_AHCLKRCTL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,AHCLKRCTL,HCLKRM)\ + | _PER_FDEFAULT(MCASP,AHCLKRCTL,HCLKRP)\ + | _PER_FDEFAULT(MCASP,AHCLKRCTL,HCLKRDIV)\ + ) + + #define MCASP_AHCLKRCTL_RMK(hclkrm, hclkrp, hclkrdiv) (Uint32)( \ + _PER_FMK(MCASP,AHCLKRCTL,HCLKRM,hclkrm)\ + | _PER_FMK(MCASP,AHCLKRCTL,HCLKRP,hclkrp)\ + | _PER_FMK(MCASP,AHCLKRCTL,HCLKRDIV,hclkrdiv)\ + ) + + #define _MCASP_AHCLKRCTL_FGET(N,FIELD)\ + _PER_FGET(_MCASP_AHCLKRCTL##N##_ADDR,MCASP,AHCLKRCTL,##FIELD) + + #define _MCASP_AHCLKRCTL_FSET(N,FIELD,field)\ + _PER_FSET(_MCASP_AHCLKRCTL##N##_ADDR,MCASP,AHCLKRCTL,##FIELD,field) + + #define _MCASP_AHCLKRCTL_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCASP_AHCLKRCTL##N##_ADDR,MCASP,AHCLKRCTL,##FIELD,##SYM) + + #define _MCASP_AHCLKRCTL0_FGET(FIELD) _MCASP_AHCLKRCTL_FGET(0,##FIELD) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_AHCLKRCTL1_FGET(FIELD) _MCASP_AHCLKRCTL_FGET(1,##FIELD) +#endif + + #define _MCASP_AHCLKRCTL0_FSET(FIELD,f) _MCASP_AHCLKRCTL_FSET(0,##FIELD,f) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_AHCLKRCTL1_FSET(FIELD,f) _MCASP_AHCLKRCTL_FSET(1,##FIELD,f) +#endif + + #define _MCASP_AHCLKRCTL0_FSETS(FIELD,SYM) _MCASP_AHCLKRCTL_FSETS(0,##FIELD,##SYM) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_AHCLKRCTL1_FSETS(FIELD,SYM) _MCASP_AHCLKRCTL_FSETS(1,##FIELD,##SYM) +#endif + +/******************************************************************************\ +* +* _____________________ +* | | +* | R T D M | +* |___________________| +* +* RTDM - Receive TDM register +* +* FIELDS (msb -> lsb) +* (rw) RTDMS0 +* (rw) RTDMS1 +* . +* . +* . +* (rw) RTDMS31 +* +\******************************************************************************/ + + #define _MCASP_RTDM_OFFSET 30 + + #define _MCASP_RTDM0_ADDR (_MCASP_BASE_PORT0+4*_MCASP_RTDM_OFFSET) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_RTDM1_ADDR (_MCASP_BASE_PORT1+4*_MCASP_RTDM_OFFSET) +#endif + + #define _MCASP_RTDM_RTDMS31_MASK 0x80000000u + #define _MCASP_RTDM_RTDMS31_SHIFT 0x0000001Fu + #define MCASP_RTDM_RTDMS31_DEFAULT 0x00000000u + #define MCASP_RTDM_RTDMS31_OF(x) _VALUEOF(x) + #define MCASP_RTDM_RTDMS31_INACTIVE 0x00000000u + #define MCASP_RTDM_RTDMS31_ACTIVE 0x00000001u + + #define _MCASP_RTDM_RTDMS30_MASK 0x40000000u + #define _MCASP_RTDM_RTDMS30_SHIFT 0x0000001Eu + #define MCASP_RTDM_RTDMS30_DEFAULT 0x00000000u + #define MCASP_RTDM_RTDMS30_OF(x) _VALUEOF(x) + #define MCASP_RTDM_RTDMS30_INACTIVE 0x00000000u + #define MCASP_RTDM_RTDMS30_ACTIVE 0x00000001u + + #define _MCASP_RTDM_RTDMS29_MASK 0x20000000u + #define _MCASP_RTDM_RTDMS29_SHIFT 0x0000001Du + #define MCASP_RTDM_RTDMS29_DEFAULT 0x00000000u + #define MCASP_RTDM_RTDMS29_OF(x) _VALUEOF(x) + #define MCASP_RTDM_RTDMS29_INACTIVE 0x00000000u + #define MCASP_RTDM_RTDMS29_ACTIVE 0x00000001u + + #define _MCASP_RTDM_RTDMS28_MASK 0x10000000u + #define _MCASP_RTDM_RTDMS28_SHIFT 0x0000001Cu + #define MCASP_RTDM_RTDMS28_DEFAULT 0x00000000u + #define MCASP_RTDM_RTDMS28_OF(x) _VALUEOF(x) + #define MCASP_RTDM_RTDMS28_INACTIVE 0x00000000u + #define MCASP_RTDM_RTDMS28_ACTIVE 0x00000001u + + #define _MCASP_RTDM_RTDMS27_MASK 0x08000000u + #define _MCASP_RTDM_RTDMS27_SHIFT 0x0000001Bu + #define MCASP_RTDM_RTDMS27_DEFAULT 0x00000000u + #define MCASP_RTDM_RTDMS27_OF(x) _VALUEOF(x) + #define MCASP_RTDM_RTDMS27_INACTIVE 0x00000000u + #define MCASP_RTDM_RTDMS27_ACTIVE 0x00000001u + + #define _MCASP_RTDM_RTDMS26_MASK 0x04000000u + #define _MCASP_RTDM_RTDMS26_SHIFT 0x0000001Au + #define MCASP_RTDM_RTDMS26_DEFAULT 0x00000000u + #define MCASP_RTDM_RTDMS26_OF(x) _VALUEOF(x) + #define MCASP_RTDM_RTDMS26_INACTIVE 0x00000000u + #define MCASP_RTDM_RTDMS26_ACTIVE 0x00000001u + + #define _MCASP_RTDM_RTDMS25_MASK 0x02000000u + #define _MCASP_RTDM_RTDMS25_SHIFT 0x00000019u + #define MCASP_RTDM_RTDMS25_DEFAULT 0x00000000u + #define MCASP_RTDM_RTDMS25_OF(x) _VALUEOF(x) + #define MCASP_RTDM_RTDMS25_INACTIVE 0x00000000u + #define MCASP_RTDM_RTDMS25_ACTIVE 0x00000001u + + #define _MCASP_RTDM_RTDMS24_MASK 0x01000000u + #define _MCASP_RTDM_RTDMS24_SHIFT 0x00000018u + #define MCASP_RTDM_RTDMS24_DEFAULT 0x00000000u + #define MCASP_RTDM_RTDMS24_OF(x) _VALUEOF(x) + #define MCASP_RTDM_RTDMS24_INACTIVE 0x00000000u + #define MCASP_RTDM_RTDMS24_ACTIVE 0x00000001u + + #define _MCASP_RTDM_RTDMS23_MASK 0x00800000u + #define _MCASP_RTDM_RTDMS23_SHIFT 0x00000017u + #define MCASP_RTDM_RTDMS23_DEFAULT 0x00000000u + #define MCASP_RTDM_RTDMS23_OF(x) _VALUEOF(x) + #define MCASP_RTDM_RTDMS23_INACTIVE 0x00000000u + #define MCASP_RTDM_RTDMS23_ACTIVE 0x00000001u + + #define _MCASP_RTDM_RTDMS22_MASK 0x00400000u + #define _MCASP_RTDM_RTDMS22_SHIFT 0x00000016u + #define MCASP_RTDM_RTDMS22_DEFAULT 0x00000000u + #define MCASP_RTDM_RTDMS22_OF(x) _VALUEOF(x) + #define MCASP_RTDM_RTDMS22_INACTIVE 0x00000000u + #define MCASP_RTDM_RTDMS22_ACTIVE 0x00000001u + + #define _MCASP_RTDM_RTDMS21_MASK 0x00200000u + #define _MCASP_RTDM_RTDMS21_SHIFT 0x00000015u + #define MCASP_RTDM_RTDMS21_DEFAULT 0x00000000u + #define MCASP_RTDM_RTDMS21_OF(x) _VALUEOF(x) + #define MCASP_RTDM_RTDMS21_INACTIVE 0x00000000u + #define MCASP_RTDM_RTDMS21_ACTIVE 0x00000001u + + #define _MCASP_RTDM_RTDMS20_MASK 0x00100000u + #define _MCASP_RTDM_RTDMS20_SHIFT 0x00000014u + #define MCASP_RTDM_RTDMS20_DEFAULT 0x00000000u + #define MCASP_RTDM_RTDMS20_OF(x) _VALUEOF(x) + #define MCASP_RTDM_RTDMS20_INACTIVE 0x00000000u + #define MCASP_RTDM_RTDMS20_ACTIVE 0x00000001u + + #define _MCASP_RTDM_RTDMS19_MASK 0x00080000u + #define _MCASP_RTDM_RTDMS19_SHIFT 0x00000013u + #define MCASP_RTDM_RTDMS19_DEFAULT 0x00000000u + #define MCASP_RTDM_RTDMS19_OF(x) _VALUEOF(x) + #define MCASP_RTDM_RTDMS19_INACTIVE 0x00000000u + #define MCASP_RTDM_RTDMS19_ACTIVE 0x00000001u + + #define _MCASP_RTDM_RTDMS18_MASK 0x00040000u + #define _MCASP_RTDM_RTDMS18_SHIFT 0x00000012u + #define MCASP_RTDM_RTDMS18_DEFAULT 0x00000000u + #define MCASP_RTDM_RTDMS18_OF(x) _VALUEOF(x) + #define MCASP_RTDM_RTDMS18_INACTIVE 0x00000000u + #define MCASP_RTDM_RTDMS18_ACTIVE 0x00000001u + + #define _MCASP_RTDM_RTDMS17_MASK 0x00020000u + #define _MCASP_RTDM_RTDMS17_SHIFT 0x00000011u + #define MCASP_RTDM_RTDMS17_DEFAULT 0x00000000u + #define MCASP_RTDM_RTDMS17_OF(x) _VALUEOF(x) + #define MCASP_RTDM_RTDMS17_INACTIVE 0x00000000u + #define MCASP_RTDM_RTDMS17_ACTIVE 0x00000001u + + #define _MCASP_RTDM_RTDMS16_MASK 0x00010000u + #define _MCASP_RTDM_RTDMS16_SHIFT 0x00000010u + #define MCASP_RTDM_RTDMS16_DEFAULT 0x00000000u + #define MCASP_RTDM_RTDMS16_OF(x) _VALUEOF(x) + #define MCASP_RTDM_RTDMS16_INACTIVE 0x00000000u + #define MCASP_RTDM_RTDMS16_ACTIVE 0x00000001u + + #define _MCASP_RTDM_RTDMS15_MASK 0x00008000u + #define _MCASP_RTDM_RTDMS15_SHIFT 0x0000000Fu + #define MCASP_RTDM_RTDMS15_DEFAULT 0x00000000u + #define MCASP_RTDM_RTDMS15_OF(x) _VALUEOF(x) + #define MCASP_RTDM_RTDMS15_INACTIVE 0x00000000u + #define MCASP_RTDM_RTDMS15_ACTIVE 0x00000001u + + #define _MCASP_RTDM_RTDMS14_MASK 0x00004000u + #define _MCASP_RTDM_RTDMS14_SHIFT 0x0000000Eu + #define MCASP_RTDM_RTDMS14_DEFAULT 0x00000000u + #define MCASP_RTDM_RTDMS14_OF(x) _VALUEOF(x) + #define MCASP_RTDM_RTDMS14_INACTIVE 0x00000000u + #define MCASP_RTDM_RTDMS14_ACTIVE 0x00000001u + + #define _MCASP_RTDM_RTDMS13_MASK 0x00002000u + #define _MCASP_RTDM_RTDMS13_SHIFT 0x0000000Du + #define MCASP_RTDM_RTDMS13_DEFAULT 0x00000000u + #define MCASP_RTDM_RTDMS13_OF(x) _VALUEOF(x) + #define MCASP_RTDM_RTDMS13_INACTIVE 0x00000000u + #define MCASP_RTDM_RTDMS13_ACTIVE 0x00000001u + + #define _MCASP_RTDM_RTDMS12_MASK 0x00001000u + #define _MCASP_RTDM_RTDMS12_SHIFT 0x0000000Cu + #define MCASP_RTDM_RTDMS12_DEFAULT 0x00000000u + #define MCASP_RTDM_RTDMS12_OF(x) _VALUEOF(x) + #define MCASP_RTDM_RTDMS12_INACTIVE 0x00000000u + #define MCASP_RTDM_RTDMS12_ACTIVE 0x00000001u + + #define _MCASP_RTDM_RTDMS11_MASK 0x00000800u + #define _MCASP_RTDM_RTDMS11_SHIFT 0x0000000Bu + #define MCASP_RTDM_RTDMS11_DEFAULT 0x00000000u + #define MCASP_RTDM_RTDMS11_OF(x) _VALUEOF(x) + #define MCASP_RTDM_RTDMS11_INACTIVE 0x00000000u + #define MCASP_RTDM_RTDMS11_ACTIVE 0x00000001u + + #define _MCASP_RTDM_RTDMS10_MASK 0x00000400u + #define _MCASP_RTDM_RTDMS10_SHIFT 0x0000000Au + #define MCASP_RTDM_RTDMS10_DEFAULT 0x00000000u + #define MCASP_RTDM_RTDMS10_OF(x) _VALUEOF(x) + #define MCASP_RTDM_RTDMS10_INACTIVE 0x00000000u + #define MCASP_RTDM_RTDMS10_ACTIVE 0x00000001u + + #define _MCASP_RTDM_RTDMS9_MASK 0x00000200u + #define _MCASP_RTDM_RTDMS9_SHIFT 0x00000009u + #define MCASP_RTDM_RTDMS9_DEFAULT 0x00000000u + #define MCASP_RTDM_RTDMS9_OF(x) _VALUEOF(x) + #define MCASP_RTDM_RTDMS9_INACTIVE 0x00000000u + #define MCASP_RTDM_RTDMS9_ACTIVE 0x00000001u + + #define _MCASP_RTDM_RTDMS8_MASK 0x00000100u + #define _MCASP_RTDM_RTDMS8_SHIFT 0x00000008u + #define MCASP_RTDM_RTDMS8_DEFAULT 0x00000000u + #define MCASP_RTDM_RTDMS8_OF(x) _VALUEOF(x) + #define MCASP_RTDM_RTDMS8_INACTIVE 0x00000000u + #define MCASP_RTDM_RTDMS8_ACTIVE 0x00000001u + + #define _MCASP_RTDM_RTDMS7_MASK 0x00000080u + #define _MCASP_RTDM_RTDMS7_SHIFT 0x00000007u + #define MCASP_RTDM_RTDMS7_DEFAULT 0x00000000u + #define MCASP_RTDM_RTDMS7_OF(x) _VALUEOF(x) + #define MCASP_RTDM_RTDMS7_INACTIVE 0x00000000u + #define MCASP_RTDM_RTDMS7_ACTIVE 0x00000001u + + #define _MCASP_RTDM_RTDMS6_MASK 0x00000040u + #define _MCASP_RTDM_RTDMS6_SHIFT 0x00000006u + #define MCASP_RTDM_RTDMS6_DEFAULT 0x00000000u + #define MCASP_RTDM_RTDMS6_OF(x) _VALUEOF(x) + #define MCASP_RTDM_RTDMS6_INACTIVE 0x00000000u + #define MCASP_RTDM_RTDMS6_ACTIVE 0x00000001u + + #define _MCASP_RTDM_RTDMS5_MASK 0x00000020u + #define _MCASP_RTDM_RTDMS5_SHIFT 0x00000005u + #define MCASP_RTDM_RTDMS5_DEFAULT 0x00000000u + #define MCASP_RTDM_RTDMS5_OF(x) _VALUEOF(x) + #define MCASP_RTDM_RTDMS5_INACTIVE 0x00000000u + #define MCASP_RTDM_RTDMS5_ACTIVE 0x00000001u + + #define _MCASP_RTDM_RTDMS4_MASK 0x00000010u + #define _MCASP_RTDM_RTDMS4_SHIFT 0x00000004u + #define MCASP_RTDM_RTDMS4_DEFAULT 0x00000000u + #define MCASP_RTDM_RTDMS4_OF(x) _VALUEOF(x) + #define MCASP_RTDM_RTDMS4_INACTIVE 0x00000000u + #define MCASP_RTDM_RTDMS4_ACTIVE 0x00000001u + + #define _MCASP_RTDM_RTDMS3_MASK 0x00000008u + #define _MCASP_RTDM_RTDMS3_SHIFT 0x00000003u + #define MCASP_RTDM_RTDMS3_DEFAULT 0x00000000u + #define MCASP_RTDM_RTDMS3_OF(x) _VALUEOF(x) + #define MCASP_RTDM_RTDMS3_INACTIVE 0x00000000u + #define MCASP_RTDM_RTDMS3_ACTIVE 0x00000001u + + #define _MCASP_RTDM_RTDMS2_MASK 0x00000004u + #define _MCASP_RTDM_RTDMS2_SHIFT 0x00000002u + #define MCASP_RTDM_RTDMS2_DEFAULT 0x00000000u + #define MCASP_RTDM_RTDMS2_OF(x) _VALUEOF(x) + #define MCASP_RTDM_RTDMS2_INACTIVE 0x00000000u + #define MCASP_RTDM_RTDMS2_ACTIVE 0x00000001u + + #define _MCASP_RTDM_RTDMS1_MASK 0x00000002u + #define _MCASP_RTDM_RTDMS1_SHIFT 0x00000001u + #define MCASP_RTDM_RTDMS1_DEFAULT 0x00000000u + #define MCASP_RTDM_RTDMS1_OF(x) _VALUEOF(x) + #define MCASP_RTDM_RTDMS1_INACTIVE 0x00000000u + #define MCASP_RTDM_RTDMS1_ACTIVE 0x00000001u + + #define _MCASP_RTDM_RTDMS0_MASK 0x00000001u + #define _MCASP_RTDM_RTDMS0_SHIFT 0x00000000u + #define MCASP_RTDM_RTDMS0_DEFAULT 0x00000000u + #define MCASP_RTDM_RTDMS0_OF(x) _VALUEOF(x) + #define MCASP_RTDM_RTDMS0_INACTIVE 0x00000000u + #define MCASP_RTDM_RTDMS0_ACTIVE 0x00000001u + + #define MCASP_RTDM_OF(x) _VALUEOF(x) + + #define MCASP_RTDM_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,RTDM,RTDMS31)\ + | _PER_FDEFAULT(MCASP,RTDM,RTDMS30)\ + | _PER_FDEFAULT(MCASP,RTDM,RTDMS29)\ + | _PER_FDEFAULT(MCASP,RTDM,RTDMS28)\ + | _PER_FDEFAULT(MCASP,RTDM,RTDMS27)\ + | _PER_FDEFAULT(MCASP,RTDM,RTDMS26)\ + | _PER_FDEFAULT(MCASP,RTDM,RTDMS25)\ + | _PER_FDEFAULT(MCASP,RTDM,RTDMS24)\ + | _PER_FDEFAULT(MCASP,RTDM,RTDMS23)\ + | _PER_FDEFAULT(MCASP,RTDM,RTDMS22)\ + | _PER_FDEFAULT(MCASP,RTDM,RTDMS21)\ + | _PER_FDEFAULT(MCASP,RTDM,RTDMS20)\ + | _PER_FDEFAULT(MCASP,RTDM,RTDMS19)\ + | _PER_FDEFAULT(MCASP,RTDM,RTDMS18)\ + | _PER_FDEFAULT(MCASP,RTDM,RTDMS17)\ + | _PER_FDEFAULT(MCASP,RTDM,RTDMS16)\ + | _PER_FDEFAULT(MCASP,RTDM,RTDMS15)\ + | _PER_FDEFAULT(MCASP,RTDM,RTDMS14)\ + | _PER_FDEFAULT(MCASP,RTDM,RTDMS13)\ + | _PER_FDEFAULT(MCASP,RTDM,RTDMS12)\ + | _PER_FDEFAULT(MCASP,RTDM,RTDMS11)\ + | _PER_FDEFAULT(MCASP,RTDM,RTDMS10)\ + | _PER_FDEFAULT(MCASP,RTDM,RTDMS9)\ + | _PER_FDEFAULT(MCASP,RTDM,RTDMS8)\ + | _PER_FDEFAULT(MCASP,RTDM,RTDMS7)\ + | _PER_FDEFAULT(MCASP,RTDM,RTDMS6)\ + | _PER_FDEFAULT(MCASP,RTDM,RTDMS5)\ + | _PER_FDEFAULT(MCASP,RTDM,RTDMS4)\ + | _PER_FDEFAULT(MCASP,RTDM,RTDMS3)\ + | _PER_FDEFAULT(MCASP,RTDM,RTDMS2)\ + | _PER_FDEFAULT(MCASP,RTDM,RTDMS1)\ + | _PER_FDEFAULT(MCASP,RTDM,RTDMS0)\ + ) + + #define MCASP_RTDM_RMK(rtdms31, rtdms30, rtdms29, rtdms28, rtdms27, rtdms26, rtdms25, rtdms24, rtdms23, rtdms22, rtdms21, rtdms20, rtdms19, rtdms18, rtdms17, rtdms16, rtdms15, rtdms14, rtdms13, rtdms12, rtdms11, rtdms10, rtdms9, rtdms8, rtdms7, rtdms6, rtdms5, rtdms4, rtdms3, rtdms2, rtdms1, rtdms0) (Uint32)( \ + _PER_FMK(MCASP,RTDM,RTDMS31,rtdms31)\ + | _PER_FMK(MCASP,RTDM,RTDMS30,rtdms30)\ + | _PER_FMK(MCASP,RTDM,RTDMS29,rtdms29)\ + | _PER_FMK(MCASP,RTDM,RTDMS28,rtdms28)\ + | _PER_FMK(MCASP,RTDM,RTDMS27,rtdms27)\ + | _PER_FMK(MCASP,RTDM,RTDMS26,rtdms26)\ + | _PER_FMK(MCASP,RTDM,RTDMS25,rtdms25)\ + | _PER_FMK(MCASP,RTDM,RTDMS24,rtdms24)\ + | _PER_FMK(MCASP,RTDM,RTDMS23,rtdms23)\ + | _PER_FMK(MCASP,RTDM,RTDMS22,rtdms22)\ + | _PER_FMK(MCASP,RTDM,RTDMS21,rtdms21)\ + | _PER_FMK(MCASP,RTDM,RTDMS20,rtdms20)\ + | _PER_FMK(MCASP,RTDM,RTDMS19,rtdms19)\ + | _PER_FMK(MCASP,RTDM,RTDMS18,rtdms18)\ + | _PER_FMK(MCASP,RTDM,RTDMS17,rtdms17)\ + | _PER_FMK(MCASP,RTDM,RTDMS16,rtdms16)\ + | _PER_FMK(MCASP,RTDM,RTDMS15,rtdms15)\ + | _PER_FMK(MCASP,RTDM,RTDMS14,rtdms14)\ + | _PER_FMK(MCASP,RTDM,RTDMS13,rtdms13)\ + | _PER_FMK(MCASP,RTDM,RTDMS12,rtdms12)\ + | _PER_FMK(MCASP,RTDM,RTDMS11,rtdms11)\ + | _PER_FMK(MCASP,RTDM,RTDMS10,rtdms10)\ + | _PER_FMK(MCASP,RTDM,RTDMS9,rtdms9)\ + | _PER_FMK(MCASP,RTDM,RTDMS8,rtdms8)\ + | _PER_FMK(MCASP,RTDM,RTDMS7,rtdms7)\ + | _PER_FMK(MCASP,RTDM,RTDMS6,rtdms6)\ + | _PER_FMK(MCASP,RTDM,RTDMS5,rtdms5)\ + | _PER_FMK(MCASP,RTDM,RTDMS4,rtdms4)\ + | _PER_FMK(MCASP,RTDM,RTDMS3,rtdms3)\ + | _PER_FMK(MCASP,RTDM,RTDMS2,rtdms2)\ + | _PER_FMK(MCASP,RTDM,RTDMS1,rtdms1)\ + | _PER_FMK(MCASP,RTDM,RTDMS0,rtdms0)\ + ) + + + #define _MCASP_RTDM_FGET(N,FIELD)\ + _PER_FGET(_MCASP_RTDM##N##_ADDR,MCASP,RTDM,##FIELD) + + #define _MCASP_RTDM_FSET(N,FIELD,field)\ + _PER_FSET(_MCASP_RTDM##N##_ADDR,MCASP,RTDM,##FIELD,field) + + #define _MCASP_RTDM_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCASP_RTDM##N##_ADDR,MCASP,RTDM,##FIELD,##SYM) + + #define _MCASP_RTDM0_FGET(FIELD) _MCASP_RTDM_FGET(0,##FIELD) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_RTDM1_FGET(FIELD) _MCASP_RTDM_FGET(1,##FIELD) +#endif + + #define _MCASP_RTDM0_FSET(FIELD,f) _MCASP_RTDM_FSET(0,##FIELD,f) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_RTDM1_FSET(FIELD,f) _MCASP_RTDM_FSET(1,##FIELD,f) +#endif + + #define _MCASP_RTDM0_FSETS(FIELD,SYM) _MCASP_RTDM_FSETS(0,##FIELD,##SYM) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_RTDM1_FSETS(FIELD,SYM) _MCASP_RTDM_FSETS(1,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* +* _____________________ +* | | +* | RINTCTL | +* |___________________| +* +* RINTCTL - Receiver Interrupt Control Register +* +* FIELDS (msb -> lsb) +* (rw) RSTAFRM +* (rw) RDATA +* (rw) RLAST +* (rw) RDMAERR +* (rw) RCKFAIL +* (rw) RSYNCERR +* (rw) ROVRN +* +\******************************************************************************/ + + #define _MCASP_RINTCTL_OFFSET 31 + + #define _MCASP_RINTCTL0_ADDR (_MCASP_BASE_PORT0+4*_MCASP_RINTCTL_OFFSET) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_RINTCTL1_ADDR (_MCASP_BASE_PORT1+4*_MCASP_RINTCTL_OFFSET) +#endif + + #define _MCASP_RINTCTL_RSTAFRM_MASK 0x00000080u + #define _MCASP_RINTCTL_RSTAFRM_SHIFT 0x00000007u + #define MCASP_RINTCTL_RSTAFRM_DEFAULT 0x00000000u + #define MCASP_RINTCTL_RSTAFRM_OF(x) _VALUEOF(x) + #define MCASP_RINTCTL_RSTAFRM_DISABLE 0x00000000u + #define MCASP_RINTCTL_RSTAFRM_ENABLE 0x00000001u + + + #define _MCASP_RINTCTL_RDATA_MASK 0x00000020u + #define _MCASP_RINTCTL_RDATA_SHIFT 0x00000005u + #define MCASP_RINTCTL_RDATA_DEFAULT 0x00000000u + #define MCASP_RINTCTL_RDATA_OF(x) _VALUEOF(x) + #define MCASP_RINTCTL_RDATA_DISABLE 0x00000000u + #define MCASP_RINTCTL_RDATA_ENABLE 0x00000001u + + + #define _MCASP_RINTCTL_RLAST_MASK 0x00000010u + #define _MCASP_RINTCTL_RLAST_SHIFT 0x00000004u + #define MCASP_RINTCTL_RLAST_DEFAULT 0x00000000u + #define MCASP_RINTCTL_RLAST_OF(x) _VALUEOF(x) + #define MCASP_RINTCTL_RLAST_DISABLE 0x00000000u + #define MCASP_RINTCTL_RLAST_ENABLE 0x00000001u + + #define _MCASP_RINTCTL_RDMAERR_MASK 0x0000008u + #define _MCASP_RINTCTL_RDMAERR_SHIFT 0x00000003u + #define MCASP_RINTCTL_RDMAERR_DEFAULT 0x00000000u + #define MCASP_RINTCTL_RDMAERR_OF(x) _VALUEOF(x) + #define MCASP_RINTCTL_RDMAERR_DISABLE 0x00000000u + #define MCASP_RINTCTL_RDMAERR_ENABLE 0x00000001u + + #define _MCASP_RINTCTL_RCKFAIL_MASK 0x00000004u + #define _MCASP_RINTCTL_RCKFAIL_SHIFT 0x00000002u + #define MCASP_RINTCTL_RCKFAIL_DEFAULT 0x00000000u + #define MCASP_RINTCTL_RCKFAIL_OF(x) _VALUEOF(x) + #define MCASP_RINTCTL_RCKFAIL_DISABLE 0x00000000u + #define MCASP_RINTCTL_RCKFAIL_ENABLE 0x00000001u + + + #define _MCASP_RINTCTL_RSYNCERR_MASK 0x00000002u + #define _MCASP_RINTCTL_RSYNCERR_SHIFT 0x00000001u + #define MCASP_RINTCTL_RSYNCERR_DEFAULT 0x00000000u + #define MCASP_RINTCTL_RSYNCERR_OF(x) _VALUEOF(x) + #define MCASP_RINTCTL_RSYNCERR_DISABLE 0x00000000u + #define MCASP_RINTCTL_RSYNCERR_ENABLE 0x00000001u + + + #define _MCASP_RINTCTL_ROVRN_MASK 0x00000001u + #define _MCASP_RINTCTL_ROVRN_SHIFT 0x00000000u + #define MCASP_RINTCTL_ROVRN_DEFAULT 0x00000000u + #define MCASP_RINTCTL_ROVRN_OF(x) _VALUEOF(x) + #define MCASP_RINTCTL_ROVRN_DISABLE 0x00000000u + #define MCASP_RINTCTL_ROVRN_ENABLE 0x00000001u + + + #define MCASP_RINTCTL_OF(x) _VALUEOF(x) + + + #define MCASP_RINTCTL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,RINTCTL,RSTAFRM)\ + |_PER_FDEFAULT(MCASP,RINTCTL,RDATA)\ + |_PER_FDEFAULT(MCASP,RINTCTL,RLAST)\ + |_PER_FDEFAULT(MCASP,RINTCTL,RDMAERR)\ + |_PER_FDEFAULT(MCASP,RINTCTL,RCKFAIL)\ + |_PER_FDEFAULT(MCASP,RINTCTL,RSYNCERR)\ + |_PER_FDEFAULT(MCASP,RINTCTL,ROVRN)\ + ) + + + #define MCASP_RINTCTL_RMK(rstafrm, rdata, rlast, rdmaerr, rckfail,rsyncerr, rovrn) (Uint32)( \ + _PER_FMK(MCASP,RINTCTL,RSTAFRM,rstafrm)\ + |_PER_FMK(MCASP,RINTCTL,RDATA,rdata)\ + |_PER_FMK(MCASP,RINTCTL,RLAST,rlast)\ + |_PER_FMK(MCASP,RINTCTL,RDMAERR,rdmaerr)\ + |_PER_FMK(MCASP,RINTCTL,RCKFAIL,rckfail)\ + |_PER_FMK(MCASP,RINTCTL,RSYNCERR,rsyncerr)\ + |_PER_FMK(MCASP,RINTCTL,ROVRN,rovrn)\ + ) + + + #define _MCASP_RINTCTL_FGET(N,FIELD)\ + _PER_FGET(_MCASP_RINTCTL##N##_ADDR,MCASP,RINTCTL,##FIELD) + + #define _MCASP_RINTCTL_FSET(N,FIELD,field)\ + _PER_FSET(_MCASP_RINTCTL##N##_ADDR,MCASP,RINTCTL,##FIELD,field) + + #define _MCASP_RINTCTL_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCASP_RINTCTL##N##_ADDR,MCASP,RINTCTL,##FIELD,##SYM) + + #define _MCASP_RINTCTL0_FGET(FIELD) _MCASP_RINTCTL_FGET(0,##FIELD) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_RINTCTL1_FGET(FIELD) _MCASP_RINTCTL_FGET(1,##FIELD) +#endif + + #define _MCASP_RINTCTL0_FSET(FIELD,f) _MCASP_RINTCTL_FSET(0,##FIELD,f) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_RINTCTL1_FSET(FIELD,f) _MCASP_RINTCTL_FSET(1,##FIELD,f) +#endif + + #define _MCASP_RINTCTL0_FSETS(FIELD,SYM) _MCASP_RINTCTL_FSETS(0,##FIELD,##SYM) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_RINTCTL1_FSETS(FIELD,SYM) _MCASP_RINTCTL_FSETS(1,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* +* _____________________ +* | | +* | RSTAT | +* |___________________| +* +* RSTAT - Receiver Status Register +* +* FIELDS (msb -> lsb) +* (r) RERR +* (r) RDMAERR +* (r) RSTAFRM +* (r) RDAT +* (r) RLAST +* (r) RTDMSLOT +* (r) RCKFAIL +* (r) RSYNCERR +* (r) ROVRN +* +\******************************************************************************/ + + #define _MCASP_RSTAT_OFFSET 32 + + #define _MCASP_RSTAT0_ADDR (_MCASP_BASE_PORT0+4*_MCASP_RSTAT_OFFSET) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_RSTAT1_ADDR (_MCASP_BASE_PORT1+4*_MCASP_RSTAT_OFFSET) +#endif + + #define _MCASP_RSTAT_RERR_MASK 0x00000100u + #define _MCASP_RSTAT_RERR_SHIFT 0x00000008u + #define MCASP_RSTAT_RERR_DEFAULT 0x00000000u + #define MCASP_RSTAT_RERR_OF(x) _VALUEOF(x) + + #define _MCASP_RSTAT_RDMAERR_MASK 0x00000080u + #define _MCASP_RSTAT_RDMAERR_SHIFT 0x00000007u + #define MCASP_RSTAT_RDMAERR_DEFAULT 0x00000000u + #define MCASP_RSTAT_RDMAERR_OF(x) _VALUEOF(x) + + #define _MCASP_RSTAT_RSTAFRM_MASK 0x00000040u + #define _MCASP_RSTAT_RSTAFRM_SHIFT 0x00000006u + #define MCASP_RSTAT_RSTAFRM_DEFAULT 0x00000000u + #define MCASP_RSTAT_RSTAFRM_OF(x) _VALUEOF(x) + #define MCASP_RSTAT_RSTAFRM_0 0x00000000u + #define MCASP_RSTAT_RSTAFRM_1 0x00000001u + #define MCASP_RSTAT_RSTAFRM_NO 0x00000000u + #define MCASP_RSTAT_RSTAFRM_YES 0x00000001u + + + #define _MCASP_RSTAT_RDATA_MASK 0x00000020u + #define _MCASP_RSTAT_RDATA_SHIFT 0x00000005u + #define MCASP_RSTAT_RDATA_DEFAULT 0x00000000u + #define MCASP_RSTAT_RDATA_OF(x) _VALUEOF(x) + #define MCASP_RSTAT_RDATA_0 0x00000000u + #define MCASP_RSTAT_RDATA_1 0x00000001u + #define MCASP_RSTAT_RDATA_NO 0x00000000u + #define MCASP_RSTAT_RDATA_YES 0x00000001u + + + #define _MCASP_RSTAT_RLAST_MASK 0x00000010u + #define _MCASP_RSTAT_RLAST_SHIFT 0x00000004u + #define MCASP_RSTAT_RLAST_DEFAULT 0x00000000u + #define MCASP_RSTAT_RLAST_OF(x) _VALUEOF(x) + #define MCASP_RSTAT_RLAST_0 0x00000000u + #define MCASP_RSTAT_RLAST_1 0x00000001u + #define MCASP_RSTAT_RLAST_NO 0x00000000u + #define MCASP_RSTAT_RLAST_YES 0x00000001u + + #define _MCASP_RSTAT_RTDMSLOT_MASK 0x00000008u + #define _MCASP_RSTAT_RTDMSLOT_SHIFT 0x00000003u + #define MCASP_RSTAT_RTDMSLOT_DEFAULT 0x00000000u + #define MCASP_RSTAT_RTDMSLOT_OF(x) _VALUEOF(x) + + + #define _MCASP_RSTAT_RCKFAIL_MASK 0x00000004u + #define _MCASP_RSTAT_RCKFAIL_SHIFT 0x00000002u + #define MCASP_RSTAT_RCKFAIL_DEFAULT 0x00000000u + #define MCASP_RSTAT_RCKFAIL_OF(x) _VALUEOF(x) + #define MCASP_RSTAT_RCKFAIL_0 0x00000000u + #define MCASP_RSTAT_RCKFAIL_1 0x00000001u + #define MCASP_RSTAT_RCKFAIL_NO 0x00000000u + #define MCASP_RSTAT_RCKFAIL_YES 0x00000001u + + + #define _MCASP_RSTAT_RSYNCERR_MASK 0x00000002u + #define _MCASP_RSTAT_RSYNCERR_SHIFT 0x00000001u + #define MCASP_RSTAT_RSYNCERR_DEFAULT 0x00000000u + #define MCASP_RSTAT_RSYNCERR_OF(x) _VALUEOF(x) + #define MCASP_RSTAT_RSYNCERR_0 0x00000000u + #define MCASP_RSTAT_RSYNCERR_1 0x00000001u + #define MCASP_RSTAT_RSYNCERR_NO 0x00000000u + #define MCASP_RSTAT_RSYNCERR_YES 0x00000001u + + #define _MCASP_RSTAT_ROVRN_MASK 0x00000001u + #define _MCASP_RSTAT_ROVRN_SHIFT 0x00000000u + #define MCASP_RSTAT_ROVRN_DEFAULT 0x00000000u + #define MCASP_RSTAT_ROVRN_OF(x) _VALUEOF(x) + #define MCASP_RSTAT_ROVRN_0 0x00000000u + #define MCASP_RSTAT_ROVRN_1 0x00000001u + #define MCASP_RSTAT_ROVRN_NO 0x00000000u + #define MCASP_RSTAT_ROVRN_YES 0x00000001u + + #define MCASP_RSTAT_OF(x) _VALUEOF(x) + + #define MCASP_RSTAT_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,RSTAT,RERR)\ + | _PER_FDEFAULT(MCASP,RSTAT,RDMAERR)\ + | _PER_FDEFAULT(MCASP,RSTAT,RSTAFRM)\ + | _PER_FDEFAULT(MCASP,RSTAT,RDATA)\ + | _PER_FDEFAULT(MCASP,RSTAT,RLAST)\ + | _PER_FDEFAULT(MCASP,RSTAT,RTDMSLOT)\ + | _PER_FDEFAULT(MCASP,RSTAT,RCKFAIL)\ + | _PER_FDEFAULT(MCASP,RSTAT,RSYNCERR)\ + | _PER_FDEFAULT(MCASP,RSTAT,ROVRN)\ + ) + + #define MCASP_RSTAT_RMK(rerr, rdmaerr, rstafrm, rdata, rlast, rtdmslot, rckfail, rsyncerr, rovrn) (Uint32)( \ + _PER_FMK(MCASP,RSTAT,RERR,rerr)\ + | _PER_FMK(MCASP,RSTAT,RDMAERR,rdmaerr)\ + | _PER_FMK(MCASP,RSTAT,RSTAFRM,rstafrm)\ + | _PER_FMK(MCASP,RSTAT,RDATA,rdata)\ + | _PER_FMK(MCASP,RSTAT,RLAST,rlast)\ + | _PER_FMK(MCASP,RSTAT,RTDMSLOT,rtdmslot)\ + | _PER_FMK(MCASP,RSTAT,RCKFAIL,rckfail)\ + | _PER_FMK(MCASP,RSTAT,RSYNCERR,rsyncerr)\ + | _PER_FMK(MCASP,RSTAT,ROVRN,rovrn)\ + ) + + #define _MCASP_RSTAT_FGET(N,FIELD)\ + _PER_FGET(_MCASP_RSTAT##N##_ADDR,MCASP,RSTAT,##FIELD) + + #define _MCASP_RSTAT_FSET(N,FIELD,field)\ + _PER_FSET(_MCASP_RSTAT##N##_ADDR,MCASP,RSTAT,##FIELD,field) + + #define _MCASP_RSTAT_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCASP_RSTAT##N##_ADDR,MCASP,RSTAT,##FIELD,##SYM) + + #define _MCASP_RSTAT0_FGET(FIELD) _MCASP_RSTAT_FGET(0,##FIELD) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_RSTAT1_FGET(FIELD) _MCASP_RSTAT_FGET(1,##FIELD) +#endif + + #define _MCASP_RSTAT0_FSET(FIELD,f) _MCASP_RSTAT_FSET(0,##FIELD,f) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_RSTAT1_FSET(FIELD,f) _MCASP_RSTAT_FSET(1,##FIELD,f) +#endif + + #define _MCASP_RSTAT0_FSETS(FIELD,SYM) _MCASP_RSTAT_FSETS(0,##FIELD,##SYM) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_RSTAT1_FSETS(FIELD,SYM) _MCASP_RSTAT_FSETS(1,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* +* _____________________ +* | | +* | RSLOT | +* |___________________| +* +* RSLOT0 - Receiver TDM Slot Counter MCASP0 +* RSLOT1 - Receiver TDM Slot Counter MCASP1 +* +* FIELDS (msb -> lsb) +* (r ) RSLOTCNT +* +\******************************************************************************/ + + #define _MCASP_RSLOT_OFFSET 33 + + #define _MCASP_RSLOT0_ADDR (_MCASP_BASE_PORT0+4*_MCASP_RSLOT_OFFSET) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_RSLOT1_ADDR (_MCASP_BASE_PORT1+4*_MCASP_RSLOT_OFFSET) +#endif + + + #define _MCASP_RSLOT_RSLOTCNT_MASK 0x000003FFu + #define _MCASP_RSLOT_RSLOTCNT_SHIFT 0x00000000u + #define MCASP_RSLOT_RSLOTCNT_DEFAULT 0x00000000u + #define MCASP_RSLOT_RSLOTCNT_OF(x) _VALUEOF(x) + + #define MCASP_RSLOT_OF(x) _VALUEOF(x) + + #define MCASP_RSLOT_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,RSLOT,RSLOTCNT)\ + ) + + #define MCASP_RSLOT_RMK(rslotcnt) (Uint32)( \ + _PER_FMK(MCASP,RSLOT,RSLOTCNT,rslotcnt)\ + ) + + + #define _MCASP_RSLOT_FGET(N,FIELD)\ + _PER_FGET(_MCASP_RSLOT##N##_ADDR,MCASP,RSLOT,##FIELD) + + #define _MCASP_RSLOT_FSET(N,FIELD,field)\ + _PER_FSET(_MCASP_RSLOT##N##_ADDR,MCASP,RSLOT,##FIELD,field) + + #define _MCASP_RSLOT_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCASP_RSLOT##N##_ADDR,MCASP,RSLOT,##FIELD,##SYM) + + #define _MCASP_RSLOT0_FGET(FIELD) _MCASP_RSLOT_FGET(0,##FIELD) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_RSLOT1_FGET(FIELD) _MCASP_RSLOT_FGET(1,##FIELD) +#endif + + #define _MCASP_RSLOT0_FSET(FIELD,f) _MCASP_RSLOT_FSET(0,##FIELD,f) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_RSLOT1_FSET(FIELD,f) _MCASP_RSLOT_FSET(1,##FIELD,f) +#endif + + #define _MCASP_RSLOT0_FSETS(FIELD,SYM) _MCASP_RSLOT_FSETS(0,##FIELD,##SYM) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_RSLOT1_FSETS(FIELD,SYM) _MCASP_RSLOT_FSETS(1,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* +* _____________________ +* | | +* | RCLKCHK | +* |___________________| +* +* RCLKCHK - Receiver Clock Check Control Register +* +* FIELDS (msb -> lsb) +* (r ) RCNT +* (rw) RMAX +* (rw) RMIN +* (rw) RPS +\******************************************************************************/ + + #define _MCASP_RCLKCHK_OFFSET 34 + + #define _MCASP_RCLKCHK0_ADDR (_MCASP_BASE_PORT0+4*_MCASP_RCLKCHK_OFFSET) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_RCLKCHK1_ADDR (_MCASP_BASE_PORT1+4*_MCASP_RCLKCHK_OFFSET) +#endif + + #define _MCASP_RCLKCHK_RCNT_MASK 0xFF000000u + #define _MCASP_RCLKCHK_RCNT_SHIFT 0x00000018u + #define MCASP_RCLKCHK_RCNT_DEFAULT 0x00000000u + #define MCASP_RCLKCHK_RCNT_OF(x) _VALUEOF(x) + + + #define _MCASP_RCLKCHK_RMAX_MASK 0x00FF0000u + #define _MCASP_RCLKCHK_RMAX_SHIFT 0x00000010u + #define MCASP_RCLKCHK_RMAX_DEFAULT 0x00000000u + #define MCASP_RCLKCHK_RMAX_OF(x) _VALUEOF(x) + + + #define _MCASP_RCLKCHK_RMIN_MASK 0x0000FF00u + #define _MCASP_RCLKCHK_RMIN_SHIFT 0x00000008u + #define MCASP_RCLKCHK_RMIN_DEFAULT 0x00000000u + #define MCASP_RCLKCHK_RMIN_OF(x) _VALUEOF(x) + + + #define _MCASP_RCLKCHK_RPS_MASK 0x0000000Fu + #define _MCASP_RCLKCHK_RPS_SHIFT 0x00000000u + #define MCASP_RCLKCHK_RPS_DEFAULT 0x00000000u + #define MCASP_RCLKCHK_RPS_OF(x) _VALUEOF(x) + #define MCASP_RCLKCHK_RPS_DIVBY1 0x00000000u + #define MCASP_RCLKCHK_RPS_DIVBY2 0x00000001u + #define MCASP_RCLKCHK_RPS_DIVBY4 0x00000002u + #define MCASP_RCLKCHK_RPS_DIVBY8 0x00000003u + #define MCASP_RCLKCHK_RPS_DIVBY16 0x00000004u + #define MCASP_RCLKCHK_RPS_DIVBY32 0x00000005u + #define MCASP_RCLKCHK_RPS_DIVBY64 0x00000006u + #define MCASP_RCLKCHK_RPS_DIVBY128 0x00000007u + #define MCASP_RCLKCHK_RPS_DIVBY256 0x00000008u + + + #define MCASP_RCLKCHK_OF(x) _VALUEOF(x) + + #define MCASP_RCLKCHK_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,RCLKCHK,RCNT)\ + | _PER_FDEFAULT(MCASP,RCLKCHK,RMAX)\ + | _PER_FDEFAULT(MCASP,RCLKCHK,RMIN)\ + | _PER_FDEFAULT(MCASP,RCLKCHK,RPS)\ + ) + + #define MCASP_RCLKCHK_RMK(rcnt, rmax, rmin, rps) (Uint32)( \ + _PER_FMK(MCASP,RCLKCHK,RCNT,rcnt)\ + | _PER_FMK(MCASP,RCLKCHK,RMAX,rmax)\ + | _PER_FMK(MCASP,RCLKCHK,RMIN,rmin)\ + | _PER_FMK(MCASP,RCLKCHK,RPS,rps)\ + ) + + #define _MCASP_RCLKCHK_FGET(N,FIELD)\ + _PER_FGET(_MCASP_RCLKCHK##N##_ADDR,MCASP,RCLKCHK,##FIELD) + + #define _MCASP_RCLKCHK_FSET(N,FIELD,field)\ + _PER_FSET(_MCASP_RCLKCHK##N##_ADDR,MCASP,RCLKCHK,##FIELD,field) + + #define _MCASP_RCLKCHK_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCASP_RCLKCHK##N##_ADDR,MCASP,RCLKCHK,##FIELD,##SYM) + + #define _MCASP_RCLKCHK0_FGET(FIELD) _MCASP_RCLKCHK_FGET(0,##FIELD) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_RCLKCHK1_FGET(FIELD) _MCASP_RCLKCHK_FGET(1,##FIELD) +#endif + + #define _MCASP_RCLKCHK0_FSET(FIELD,f) _MCASP_RCLKCHK_FSET(0,##FIELD,f) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_RCLKCHK1_FSET(FIELD,f) _MCASP_RCLKCHK_FSET(1,##FIELD,f) +#endif + + #define _MCASP_RCLKCHK0_FSETS(FIELD,SYM) _MCASP_RCLKCHK_FSETS(0,##FIELD,##SYM) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_RCLKCHK1_FSETS(FIELD,SYM) _MCASP_RCLKCHK_FSETS(1,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* +* _____________________ +* | | +* | XGBLCTL | +* |___________________| +* +* XGBLCTL - Global Control Register +* +* FIELDS (msb -> lsb) +* (rw) XFRST +* (rw) XSMRST +* (rw) XSRCLR +* (rw) XHCLKRST +* (rw) XCLKRST +* (rw) RFRST +* (rw) RSMRST +* (rw) RSRCLR +* (rw) RHCLKRST +* (rw) RCLKRST +* +\******************************************************************************/ + + #define _MCASP_XGBLCTL_OFFSET 40 + + #define _MCASP_XGBLCTL0_ADDR (_MCASP_BASE_PORT0+4*_MCASP_XGBLCTL_OFFSET) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_XGBLCTL1_ADDR (_MCASP_BASE_PORT1+4*_MCASP_XGBLCTL_OFFSET) +#endif + + #define _MCASP_XGBLCTL_XFRST_MASK 0x00001000u + #define _MCASP_XGBLCTL_XFRST_SHIFT 0x0000000Cu + #define MCASP_XGBLCTL_XFRST_DEFAULT 0x00000000u + #define MCASP_XGBLCTL_XFRST_OF(x) _VALUEOF(x) + #define MCASP_XGBLCTL_XFRST_RESET 0x00000000u + #define MCASP_XGBLCTL_XFRST_ACTIVE 0x00000001u + + #define _MCASP_XGBLCTL_XSMRST_MASK 0x00000800u + #define _MCASP_XGBLCTL_XSMRST_SHIFT 0x0000000Bu + #define MCASP_XGBLCTL_XSMRST_DEFAULT 0x00000000u + #define MCASP_XGBLCTL_XSMRST_OF(x) _VALUEOF(x) + #define MCASP_XGBLCTL_XSMRST_RESET 0x00000000u + #define MCASP_XGBLCTL_XSMRST_ACTIVE 0x00000001u + + #define _MCASP_XGBLCTL_XSRCLR_MASK 0x00000400u + #define _MCASP_XGBLCTL_XSRCLR_SHIFT 0x0000000Au + #define MCASP_XGBLCTL_XSRCLR_DEFAULT 0x00000000u + #define MCASP_XGBLCTL_XSRCLR_OF(x) _VALUEOF(x) + #define MCASP_XGBLCTL_XSRCLR_CLEAR 0x00000000u + #define MCASP_XGBLCTL_XSRCLR_ACTIVE 0x00000001u + + #define _MCASP_XGBLCTL_XHCLKRST_MASK 0x00000200u + #define _MCASP_XGBLCTL_XHCLKRST_SHIFT 0x00000009u + #define MCASP_XGBLCTL_XHCLKRST_DEFAULT 0x00000000u + #define MCASP_XGBLCTL_XHCLKRST_OF(x) _VALUEOF(x) + #define MCASP_XGBLCTL_XHCLKRST_RESET 0x00000000u + #define MCASP_XGBLCTL_XHCLKRST_ACTIVE 0x00000001u + + #define _MCASP_XGBLCTL_XCLKRST_MASK 0x00000100u + #define _MCASP_XGBLCTL_XCLKRST_SHIFT 0x00000008u + #define MCASP_XGBLCTL_XCLKRST_DEFAULT 0x00000000u + #define MCASP_XGBLCTL_XCLKRST_OF(x) _VALUEOF(x) + #define MCASP_XGBLCTL_XCLKRST_RESET 0x00000000u + #define MCASP_XGBLCTL_XCLKRST_ACTIVE 0x00000001u + + #define _MCASP_XGBLCTL_RFRST_MASK 0x00000010u + #define _MCASP_XGBLCTL_RFRST_SHIFT 0x00000004u + #define MCASP_XGBLCTL_RFRST_DEFAULT 0x00000000u + #define MCASP_XGBLCTL_RFRST_OF(x) _VALUEOF(x) + #define MCASP_XGBLCTL_RFRST_RESET 0x00000000u + #define MCASP_XGBLCTL_RFRST_ACTIVE 0x00000001u + + #define _MCASP_XGBLCTL_RSMRST_MASK 0x00000008u + #define _MCASP_XGBLCTL_RSMRST_SHIFT 0x00000003u + #define MCASP_XGBLCTL_RSMRST_DEFAULT 0x00000000u + #define MCASP_XGBLCTL_RSMRST_OF(x) _VALUEOF(x) + #define MCASP_XGBLCTL_RSMRST_RESET 0x00000000u + #define MCASP_XGBLCTL_RSMRST_ACTIVE 0x00000001u + + #define _MCASP_XGBLCTL_RSRCLR_MASK 0x00000004u + #define _MCASP_XGBLCTL_RSRCLR_SHIFT 0x00000002u + #define MCASP_XGBLCTL_RSRCLR_DEFAULT 0x00000000u + #define MCASP_XGBLCTL_RSRCLR_OF(x) _VALUEOF(x) + #define MCASP_XGBLCTL_RSRCLR_CLEAR 0x00000000u + #define MCASP_XGBLCTL_RSRCLR_ACTIVE 0x00000001u + + #define _MCASP_XGBLCTL_RHCLKRST_MASK 0x00000002u + #define _MCASP_XGBLCTL_RHCLKRST_SHIFT 0x00000001u + #define MCASP_XGBLCTL_RHCLKRST_DEFAULT 0x00000000u + #define MCASP_XGBLCTL_RHCLKRST_OF(x) _VALUEOF(x) + #define MCASP_XGBLCTL_RHCLKRST_RESET 0x00000000u + #define MCASP_XGBLCTL_RHCLKRST_ACTIVE 0x00000001u + + #define _MCASP_XGBLCTL_RCLKRST_MASK 0x00000001u + #define _MCASP_XGBLCTL_RCLKRST_SHIFT 0x00000000u + #define MCASP_XGBLCTL_RCLKRST_DEFAULT 0x00000000u + #define MCASP_XGBLCTL_RCLKRST_OF(x) _VALUEOF(x) + #define MCASP_XGBLCTL_RCLKRST_RESET 0x00000000u + #define MCASP_XGBLCTL_RCLKRST_ACTIVE 0x00000001u + + #define MCASP_XGBLCTL_OF(x) _VALUEOF(x) + + #define MCASP_XGBLCTL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,XGBLCTL,XFRST)\ + |_PER_FDEFAULT(MCASP,XGBLCTL,XSMRST)\ + |_PER_FDEFAULT(MCASP,XGBLCTL,XSRCLR)\ + |_PER_FDEFAULT(MCASP,XGBLCTL,xXHCLKRST)\ + |_PER_FDEFAULT(MCASP,XGBLCTL,XCLKRST)\ + ) + + + #define MCASP_XGBLCTL_RMK(xfrst, xsmrst, xsrclr, xhclkrst, xclkrst) (Uint32)( \ + _PER_FMK(MCASP,XGBLCTL,XFRST,xfrst)\ + |_PER_FMK(MCASP,XGBLCTL,XSMRST,xsmrst)\ + |_PER_FMK(MCASP,XGBLCTL,XSRCLR,xsrclr)\ + |_PER_FMK(MCASP,XGBLCTL,XHCLKRST,xhclkrst)\ + |_PER_FMK(MCASP,XGBLCTL,XCLKRST,xclkrst)\ + ) + + + #define _MCASP_XGBLCTL_FGET(N,FIELD)\ + _PER_FGET(_MCASP_XGBLCTL##N##_ADDR,MCASP,XGBLCTL,##FIELD) + + #define _MCASP_XGBLCTL_FSET(N,FIELD,field)\ + _PER_FSET(_MCASP_XGBLCTL##N##_ADDR,MCASP,XGBLCTL,##FIELD,field) + + #define _MCASP_XGBLCTL_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCASP_XGBLCTL##N##_ADDR,MCASP,XGBLCTL,##FIELD,##SYM) + + #define _MCASP_XGBLCTL0_FGET(FIELD) _MCASP_XGBLCTL_FGET(0,##FIELD) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_XGBLCTL1_FGET(FIELD) _MCASP_XGBLCTL_FGET(1,##FIELD) +#endif + + #define _MCASP_XGBLCTL0_FSET(FIELD,f) _MCASP_XGBLCTL_FSET(0,##FIELD,f) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_XGBLCTL1_FSET(FIELD,f) _MCASP_XGBLCTL_FSET(1,##FIELD,f) +#endif + + #define _MCASP_XGBLCTL0_FSETS(FIELD,SYM) _MCASP_XGBLCTL_FSETS(0,##FIELD,##SYM) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_XGBLCTL1_FSETS(FIELD,SYM) _MCASP_XGBLCTL_FSETS(1,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* +* _____________________ +* | | +* | XMASK | +* |___________________| +* +* XMASK - Pin Data Output Register +* +* FIELDS (msb -> lsb) +* (rw) XMASKn n:0 to 31 +* +\******************************************************************************/ + + #define _MCASP_XMASK_OFFSET 41 + + #define _MCASP_XMASK0_ADDR (_MCASP_BASE_PORT0+4*_MCASP_XMASK_OFFSET) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_XMASK1_ADDR (_MCASP_BASE_PORT1+4*_MCASP_XMASK_OFFSET) +#endif + + #define _MCASP_XMASK_XMASK0_MASK 0x00000001u + #define _MCASP_XMASK_XMASK0_SHIFT 0x00000000u + #define MCASP_XMASK_XMASK0_DEFAULT 0x00000000u + #define MCASP_XMASK_XMASK0_OF(x) _VALUEOF(x) + #define MCASP_XMASK_XMASK0_USEMASK 0x00000000u + #define MCASP_XMASK_XMASK0_NOMASK 0x00000001u + + #define _MCASP_XMASK_XMASK1_MASK 0x00000002u + #define _MCASP_XMASK_XMASK1_SHIFT 0x00000001u + #define MCASP_XMASK_XMASK1_DEFAULT 0x00000000u + #define MCASP_XMASK_XMASK1_OF(x) _VALUEOF(x) + #define MCASP_XMASK_XMASK1_USEMASK 0x00000000u + #define MCASP_XMASK_XMASK1_NOMASK 0x00000001u + + #define _MCASP_XMASK_XMASK2_MASK 0x00000004u + #define _MCASP_XMASK_XMASK2_SHIFT 0x00000002u + #define MCASP_XMASK_XMASK2_DEFAULT 0x00000000u + #define MCASP_XMASK_XMASK2_OF(x) _VALUEOF(x) + #define MCASP_XMASK_XMASK2_USEMASK 0x00000000u + #define MCASP_XMASK_XMASK2_NOMASK 0x00000001u + + #define _MCASP_XMASK_XMASK3_MASK 0x00000008u + #define _MCASP_XMASK_XMASK3_SHIFT 0x00000003u + #define MCASP_XMASK_XMASK3_DEFAULT 0x00000000u + #define MCASP_XMASK_XMASK3_OF(x) _VALUEOF(x) + #define MCASP_XMASK_XMASK3_USEMASK 0x00000000u + #define MCASP_XMASK_XMASK3_NOMASK 0x00000001u + + #define _MCASP_XMASK_XMASK4_MASK 0x00000010u + #define _MCASP_XMASK_XMASK4_SHIFT 0x00000004u + #define MCASP_XMASK_XMASK4_DEFAULT 0x00000000u + #define MCASP_XMASK_XMASK4_OF(x) _VALUEOF(x) + #define MCASP_XMASK_XMASK4_USEMASK 0x00000000u + #define MCASP_XMASK_XMASK4_NOMASK 0x00000001u + + #define _MCASP_XMASK_XMASK5_MASK 0x00000020u + #define _MCASP_XMASK_XMASK5_SHIFT 0x00000005u + #define MCASP_XMASK_XMASK5_DEFAULT 0x00000000u + #define MCASP_XMASK_XMASK5_OF(x) _VALUEOF(x) + #define MCASP_XMASK_XMASK5_USEMASK 0x00000000u + #define MCASP_XMASK_XMASK5_NOMASK 0x00000001u + + #define _MCASP_XMASK_XMASK6_MASK 0x00000040u + #define _MCASP_XMASK_XMASK6_SHIFT 0x00000006u + #define MCASP_XMASK_XMASK6_DEFAULT 0x00000000u + #define MCASP_XMASK_XMASK6_OF(x) _VALUEOF(x) + #define MCASP_XMASK_XMASK6_USEMASK 0x00000000u + #define MCASP_XMASK_XMASK6_NOMASK 0x00000001u + + #define _MCASP_XMASK_XMASK7_MASK 0x00000080u + #define _MCASP_XMASK_XMASK7_SHIFT 0x00000007u + #define MCASP_XMASK_XMASK7_DEFAULT 0x00000000u + #define MCASP_XMASK_XMASK7_OF(x) _VALUEOF(x) + #define MCASP_XMASK_XMASK7_USEMASK 0x00000000u + #define MCASP_XMASK_XMASK7_NOMASK 0x00000001u + + #define _MCASP_XMASK_XMASK8_MASK 0x00000100u + #define _MCASP_XMASK_XMASK8_SHIFT 0x00000008u + #define MCASP_XMASK_XMASK8_DEFAULT 0x00000000u + #define MCASP_XMASK_XMASK8_OF(x) _VALUEOF(x) + #define MCASP_XMASK_XMASK8_USEMASK 0x00000000u + #define MCASP_XMASK_XMASK8_NOMASK 0x00000001u + + #define _MCASP_XMASK_XMASK9_MASK 0x00000200u + #define _MCASP_XMASK_XMASK9_SHIFT 0x00000009u + #define MCASP_XMASK_XMASK9_DEFAULT 0x00000000u + #define MCASP_XMASK_XMASK9_OF(x) _VALUEOF(x) + #define MCASP_XMASK_XMASK9_USEMASK 0x00000000u + #define MCASP_XMASK_XMASK9_NOMASK 0x00000001u + + #define _MCASP_XMASK_XMASK10_MASK 0x00000400u + #define _MCASP_XMASK_XMASK10_SHIFT 0x0000000Au + #define MCASP_XMASK_XMASK10_DEFAULT 0x00000000u + #define MCASP_XMASK_XMASK10_OF(x) _VALUEOF(x) + #define MCASP_XMASK_XMASK10_USEMASK 0x00000000u + #define MCASP_XMASK_XMASK10_NOMASK 0x00000001u + + #define _MCASP_XMASK_XMASK11_MASK 0x00000800u + #define _MCASP_XMASK_XMASK11_SHIFT 0x0000000Bu + #define MCASP_XMASK_XMASK11_DEFAULT 0x00000000u + #define MCASP_XMASK_XMASK11_OF(x) _VALUEOF(x) + #define MCASP_XMASK_XMASK11_USEMASK 0x00000000u + #define MCASP_XMASK_XMASK11_NOMASK 0x00000001u + + #define _MCASP_XMASK_XMASK12_MASK 0x00001000u + #define _MCASP_XMASK_XMASK12_SHIFT 0x0000000Cu + #define MCASP_XMASK_XMASK12_DEFAULT 0x00000000u + #define MCASP_XMASK_XMASK12_OF(x) _VALUEOF(x) + #define MCASP_XMASK_XMASK12_USEMASK 0x00000000u + #define MCASP_XMASK_XMASK12_NOMASK 0x00000001u + + #define _MCASP_XMASK_XMASK13_MASK 0x00002000u + #define _MCASP_XMASK_XMASK13_SHIFT 0x0000000Du + #define MCASP_XMASK_XMASK13_DEFAULT 0x00000000u + #define MCASP_XMASK_XMASK13_OF(x) _VALUEOF(x) + #define MCASP_XMASK_XMASK13_USEMASK 0x00000000u + #define MCASP_XMASK_XMASK13_NOMASK 0x00000001u + + #define _MCASP_XMASK_XMASK14_MASK 0x00004000u + #define _MCASP_XMASK_XMASK14_SHIFT 0x0000000Eu + #define MCASP_XMASK_XMASK14_DEFAULT 0x00000000u + #define MCASP_XMASK_XMASK14_OF(x) _VALUEOF(x) + #define MCASP_XMASK_XMASK14_USEMASK 0x00000000u + #define MCASP_XMASK_XMASK14_NOMASK 0x00000001u + + #define _MCASP_XMASK_XMASK15_MASK 0x00008000u + #define _MCASP_XMASK_XMASK15_SHIFT 0x0000000Fu + #define MCASP_XMASK_XMASK15_DEFAULT 0x00000000u + #define MCASP_XMASK_XMASK15_OF(x) _VALUEOF(x) + #define MCASP_XMASK_XMASK15_USEMASK 0x00000000u + #define MCASP_XMASK_XMASK15_NOMASK 0x00000001u + + #define _MCASP_XMASK_XMASK16_MASK 0x00010000u + #define _MCASP_XMASK_XMASK16_SHIFT 0x00000010u + #define MCASP_XMASK_XMASK16_DEFAULT 0x00000000u + #define MCASP_XMASK_XMASK16_OF(x) _VALUEOF(x) + #define MCASP_XMASK_XMASK16_USEMASK 0x00000000u + #define MCASP_XMASK_XMASK16_NOMASK 0x00000001u + + #define _MCASP_XMASK_XMASK17_MASK 0x00020000u + #define _MCASP_XMASK_XMASK17_SHIFT 0x00000011u + #define MCASP_XMASK_XMASK17_DEFAULT 0x00000000u + #define MCASP_XMASK_XMASK17_OF(x) _VALUEOF(x) + #define MCASP_XMASK_XMASK17_USEMASK 0x00000000u + #define MCASP_XMASK_XMASK17_NOMASK 0x00000001u + + #define _MCASP_XMASK_XMASK18_MASK 0x00040000u + #define _MCASP_XMASK_XMASK18_SHIFT 0x00000012u + #define MCASP_XMASK_XMASK18_DEFAULT 0x00000000u + #define MCASP_XMASK_XMASK18_OF(x) _VALUEOF(x) + #define MCASP_XMASK_XMASK18_USEMASK 0x00000000u + #define MCASP_XMASK_XMASK18_NOMASK 0x00000001u + + #define _MCASP_XMASK_XMASK19_MASK 0x00080000u + #define _MCASP_XMASK_XMASK19_SHIFT 0x00000013u + #define MCASP_XMASK_XMASK19_DEFAULT 0x00000000u + #define MCASP_XMASK_XMASK19_OF(x) _VALUEOF(x) + #define MCASP_XMASK_XMASK19_USEMASK 0x00000000u + #define MCASP_XMASK_XMASK19_NOMASK 0x00000001u + + #define _MCASP_XMASK_XMASK20_MASK 0x00100000u + #define _MCASP_XMASK_XMASK20_SHIFT 0x00000014u + #define MCASP_XMASK_XMASK20_DEFAULT 0x00000000u + #define MCASP_XMASK_XMASK20_OF(x) _VALUEOF(x) + #define MCASP_XMASK_XMASK20_USEMASK 0x00000000u + #define MCASP_XMASK_XMASK20_NOMASK 0x00000001u + + #define _MCASP_XMASK_XMASK21_MASK 0x00200000u + #define _MCASP_XMASK_XMASK21_SHIFT 0x00000015u + #define MCASP_XMASK_XMASK21_DEFAULT 0x00000000u + #define MCASP_XMASK_XMASK21_OF(x) _VALUEOF(x) + #define MCASP_XMASK_XMASK21_USEMASK 0x00000000u + #define MCASP_XMASK_XMASK21_NOMASK 0x00000001u + + #define _MCASP_XMASK_XMASK22_MASK 0x00400000u + #define _MCASP_XMASK_XMASK22_SHIFT 0x00000016u + #define MCASP_XMASK_XMASK22_DEFAULT 0x00000000u + #define MCASP_XMASK_XMASK22_OF(x) _VALUEOF(x) + #define MCASP_XMASK_XMASK22_USEMASK 0x00000000u + #define MCASP_XMASK_XMASK22_NOMASK 0x00000001u + + #define _MCASP_XMASK_XMASK23_MASK 0x00800000u + #define _MCASP_XMASK_XMASK23_SHIFT 0x00000017u + #define MCASP_XMASK_XMASK23_DEFAULT 0x00000000u + #define MCASP_XMASK_XMASK23_OF(x) _VALUEOF(x) + #define MCASP_XMASK_XMASK23_USEMASK 0x00000000u + #define MCASP_XMASK_XMASK23_NOMASK 0x00000001u + + #define _MCASP_XMASK_XMASK24_MASK 0x01000000u + #define _MCASP_XMASK_XMASK24_SHIFT 0x00000018u + #define MCASP_XMASK_XMASK24_DEFAULT 0x00000000u + #define MCASP_XMASK_XMASK24_OF(x) _VALUEOF(x) + #define MCASP_XMASK_XMASK24_USEMASK 0x00000000u + #define MCASP_XMASK_XMASK24_NOMASK 0x00000001u + + #define _MCASP_XMASK_XMASK25_MASK 0x02000000u + #define _MCASP_XMASK_XMASK25_SHIFT 0x00000019u + #define MCASP_XMASK_XMASK25_DEFAULT 0x00000000u + #define MCASP_XMASK_XMASK25_OF(x) _VALUEOF(x) + #define MCASP_XMASK_XMASK25_USEMASK 0x00000000u + #define MCASP_XMASK_XMASK25_NOMASK 0x00000001u + + #define _MCASP_XMASK_XMASK26_MASK 0x04000000u + #define _MCASP_XMASK_XMASK26_SHIFT 0x0000001Au + #define MCASP_XMASK_XMASK26_DEFAULT 0x00000000u + #define MCASP_XMASK_XMASK26_OF(x) _VALUEOF(x) + #define MCASP_XMASK_XMASK26_USEMASK 0x00000000u + #define MCASP_XMASK_XMASK26_NOMASK 0x00000001u + + #define _MCASP_XMASK_XMASK27_MASK 0x08000000u + #define _MCASP_XMASK_XMASK27_SHIFT 0x0000001Bu + #define MCASP_XMASK_XMASK27_DEFAULT 0x00000000u + #define MCASP_XMASK_XMASK27_OF(x) _VALUEOF(x) + #define MCASP_XMASK_XMASK27_USEMASK 0x00000000u + #define MCASP_XMASK_XMASK27_NOMASK 0x00000001u + + #define _MCASP_XMASK_XMASK28_MASK 0x10000000u + #define _MCASP_XMASK_XMASK28_SHIFT 0x0000001Cu + #define MCASP_XMASK_XMASK28_DEFAULT 0x00000000u + #define MCASP_XMASK_XMASK28_OF(x) _VALUEOF(x) + #define MCASP_XMASK_XMASK28_USEMASK 0x00000000u + #define MCASP_XMASK_XMASK28_NOMASK 0x00000001u + + #define _MCASP_XMASK_XMASK29_MASK 0x20000000u + #define _MCASP_XMASK_XMASK29_SHIFT 0x0000001Du + #define MCASP_XMASK_XMASK29_DEFAULT 0x00000000u + #define MCASP_XMASK_XMASK29_OF(x) _VALUEOF(x) + #define MCASP_XMASK_XMASK29_USEMASK 0x00000000u + #define MCASP_XMASK_XMASK29_NOMASK 0x00000001u + + #define _MCASP_XMASK_XMASK30_MASK 0x40000000u + #define _MCASP_XMASK_XMASK30_SHIFT 0x0000001Eu + #define MCASP_XMASK_XMASK30_DEFAULT 0x00000000u + #define MCASP_XMASK_XMASK30_OF(x) _VALUEOF(x) + #define MCASP_XMASK_XMASK30_USEMASK 0x00000000u + #define MCASP_XMASK_XMASK30_NOMASK 0x00000001u + + #define _MCASP_XMASK_XMASK31_MASK 0x80000000u + #define _MCASP_XMASK_XMASK31_SHIFT 0x0000001Fu + #define MCASP_XMASK_XMASK31_DEFAULT 0x00000000u + #define MCASP_XMASK_XMASK31_OF(x) _VALUEOF(x) + #define MCASP_XMASK_XMASK31_USEMASK 0x00000000u + #define MCASP_XMASK_XMASK31_NOMASK 0x00000001u + + #define MCASP_XMASK_OF(x) _VALUEOF(x) + + #define MCASP_XMASK_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,XMASK,XMASK0)\ + |_PER_FDEFAULT(MCASP,XMASK,XMASK1)\ + |_PER_FDEFAULT(MCASP,XMASK,XMASK2)\ + |_PER_FDEFAULT(MCASP,XMASK,XMASK3)\ + |_PER_FDEFAULT(MCASP,XMASK,XMASK4)\ + |_PER_FDEFAULT(MCASP,XMASK,XMASK5)\ + |_PER_FDEFAULT(MCASP,XMASK,XMASK6)\ + |_PER_FDEFAULT(MCASP,XMASK,XMASK7)\ + |_PER_FDEFAULT(MCASP,XMASK,XMASK8)\ + |_PER_FDEFAULT(MCASP,XMASK,XMASK9)\ + |_PER_FDEFAULT(MCASP,XMASK,XMASK10)\ + |_PER_FDEFAULT(MCASP,XMASK,XMASK11)\ + |_PER_FDEFAULT(MCASP,XMASK,XMASK12)\ + |_PER_FDEFAULT(MCASP,XMASK,XMASK13)\ + |_PER_FDEFAULT(MCASP,XMASK,XMASK14)\ + |_PER_FDEFAULT(MCASP,XMASK,XMASK15)\ + |_PER_FDEFAULT(MCASP,XMASK,XMASK16)\ + |_PER_FDEFAULT(MCASP,XMASK,XMASK17)\ + |_PER_FDEFAULT(MCASP,XMASK,XMASK18)\ + |_PER_FDEFAULT(MCASP,XMASK,XMASK19)\ + |_PER_FDEFAULT(MCASP,XMASK,XMASK20)\ + |_PER_FDEFAULT(MCASP,XMASK,XMASK21)\ + |_PER_FDEFAULT(MCASP,XMASK,XMASK22)\ + |_PER_FDEFAULT(MCASP,XMASK,XMASK23)\ + |_PER_FDEFAULT(MCASP,XMASK,XMASK24)\ + |_PER_FDEFAULT(MCASP,XMASK,XMASK25)\ + |_PER_FDEFAULT(MCASP,XMASK,XMASK26)\ + |_PER_FDEFAULT(MCASP,XMASK,XMASK27)\ + |_PER_FDEFAULT(MCASP,XMASK,XMASK28)\ + |_PER_FDEFAULT(MCASP,XMASK,XMASK29)\ + |_PER_FDEFAULT(MCASP,XMASK,XMASK30)\ + |_PER_FDEFAULT(MCASP,XMASK,XMASK31)\ + ) + + #define MCASP_XMASK_RMK(xmask31, xmask30,xmask29,xmask28,xmask27,xmask26,xmask25,\ + xmask24,xmask23,xmask22,xmask21,xmask20,xmask19,xmask18,xmask17,\ + xmask16,xmask15,xmask14,xmask13,xmask12,xmask11,xmask10,xmask9,\ + xmask8, xmask7, xmask6, xmask5,xmask4, xmask3, xmask2, xmask1, xmask0 ) \ + (Uint32)( \ + _PER_FMK(MCASP,XMASK,XMASK0,xmask0)\ + |_PER_FMK(MCASP,XMASK,XMASK1,xmask1)\ + |_PER_FMK(MCASP,XMASK,XMASK2,xmask2)\ + |_PER_FMK(MCASP,XMASK,XMASK3,xmask3)\ + |_PER_FMK(MCASP,XMASK,XMASK4,xmask4)\ + |_PER_FMK(MCASP,XMASK,XMASK5,xmask5)\ + |_PER_FMK(MCASP,XMASK,XMASK6,xmask6)\ + |_PER_FMK(MCASP,XMASK,XMASK7,xmask7)\ + |_PER_FMK(MCASP,XMASK,XMASK8,xmask8)\ + |_PER_FMK(MCASP,XMASK,XMASK9,xmask9)\ + |_PER_FMK(MCASP,XMASK,XMASK10,xmask10)\ + |_PER_FMK(MCASP,XMASK,XMASK11,xmask11)\ + |_PER_FMK(MCASP,XMASK,XMASK12,xmask12)\ + |_PER_FMK(MCASP,XMASK,XMASK13,xmask13)\ + |_PER_FMK(MCASP,XMASK,XMASK14,xmask14)\ + |_PER_FMK(MCASP,XMASK,XMASK15,xmask15)\ + |_PER_FMK(MCASP,XMASK,XMASK16,xmask16)\ + |_PER_FMK(MCASP,XMASK,XMASK17,xmask17)\ + |_PER_FMK(MCASP,XMASK,XMASK18,xmask18)\ + |_PER_FMK(MCASP,XMASK,XMASK19,xmask19)\ + |_PER_FMK(MCASP,XMASK,XMASK20,xmask20)\ + |_PER_FMK(MCASP,XMASK,XMASK21,xmask21)\ + |_PER_FMK(MCASP,XMASK,XMASK22,xmask22)\ + |_PER_FMK(MCASP,XMASK,XMASK23,xmask23)\ + |_PER_FMK(MCASP,XMASK,XMASK24,xmask24)\ + |_PER_FMK(MCASP,XMASK,XMASK25,xmask25)\ + |_PER_FMK(MCASP,XMASK,XMASK26,xmask26)\ + |_PER_FMK(MCASP,XMASK,XMASK27,xmask27)\ + |_PER_FMK(MCASP,XMASK,XMASK28,xmask28)\ + |_PER_FMK(MCASP,XMASK,XMASK29,xmask29)\ + |_PER_FMK(MCASP,XMASK,XMASK30,xmask30)\ + |_PER_FMK(MCASP,XMASK,XMASK31,xmask31)\ + ) + + #define _MCASP_XMASK_FGET(N,FIELD)\ + _PER_FGET(_MCASP_XMASK##N##_ADDR,MCASP,XMASK,##FIELD) + + #define _MCASP_XMASK_FSET(N,FIELD,field)\ + _PER_FSET(_MCASP_XMASK##N##_ADDR,MCASP,XMASK,##FIELD,field) + + #define _MCASP_XMASK_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCASP_XMASK##N##_ADDR,MCASP,XMASK,##FIELD,##SYM) + + #define _MCASP_XMASK0_FGET(FIELD) _MCASP_XMASK_FGET(0,##FIELD) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_XMASK1_FGET(FIELD) _MCASP_XMASK_FGET(1,##FIELD) +#endif + + #define _MCASP_XMASK0_FSET(FIELD,f) _MCASP_XMASK_FSET(0,##FIELD,f) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_XMASK1_FSET(FIELD,f) _MCASP_XMASK_FSET(1,##FIELD,f) +#endif + + #define _MCASP_XMASK0_FSETS(FIELD,SYM) _MCASP_XMASK_FSETS(0,##FIELD,##SYM) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_XMASK1_FSETS(FIELD,SYM) _MCASP_XMASK_FSETS(1,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* +* _____________________ +* | | +* | XFMT | +* |___________________| +* +* XFMT - Transmit Bitstream Format Register +* +* FIELDS (msb -> lsb) +* (rw) XDATDLY +* (rw) XRVRS +* (rw) XPAD +* (rw) XPBIT +* (rw) XSSZ +* (rw) XBUSEL +* (rw) XROT +* +\******************************************************************************/ + + #define _MCASP_XFMT_OFFSET 42 + + #define _MCASP_XFMT0_ADDR (_MCASP_BASE_PORT0+4*_MCASP_XFMT_OFFSET) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_XFMT1_ADDR (_MCASP_BASE_PORT1+4*_MCASP_XFMT_OFFSET) +#endif + + #define _MCASP_XFMT_XDATDLY_MASK 0x00030000u + #define _MCASP_XFMT_XDATDLY_SHIFT 0x00000010u + #define MCASP_XFMT_XDATDLY_DEFAULT 0x00000000u + #define MCASP_XFMT_XDATDLY_OF(x) _VALUEOF(x) + #define MCASP_XFMT_XDATDLY_0BIT 0x00000000u + #define MCASP_XFMT_XDATDLY_1BIT 0x00000001u + #define MCASP_XFMT_XDATDLY_2BIT 0x00000002u + + + #define _MCASP_XFMT_XRVRS_MASK 0x00008000u + #define _MCASP_XFMT_XRVRS_SHIFT 0x0000000Fu + #define MCASP_XFMT_XRVRS_DEFAULT 0x00000000u + #define MCASP_XFMT_XRVRS_OF(x) _VALUEOF(x) + #define MCASP_XFMT_XRVRS_LSBFIRST 0x00000000u + #define MCASP_XFMT_XRVRS_MSBFIRST 0x00000001u + + #define _MCASP_XFMT_XPAD_MASK 0x00006000u + #define _MCASP_XFMT_XPAD_SHIFT 0x0000000Du + #define MCASP_XFMT_XPAD_DEFAULT 0x00000000u + #define MCASP_XFMT_XPAD_OF(x) _VALUEOF(x) + #define MCASP_XFMT_XPAD_ZERO 0x00000000u + #define MCASP_XFMT_XPAD_ONE 0x00000001u + #define MCASP_XFMT_XPAD_XPBIT 0x00000002u + + #define _MCASP_XFMT_XPBIT_MASK 0x00001F00u + #define _MCASP_XFMT_XPBIT_SHIFT 0x00000008u + #define MCASP_XFMT_XPBIT_DEFAULT 0x00000000u + #define MCASP_XFMT_XPBIT_OF(x) _VALUEOF(x) + + #define _MCASP_XFMT_XSSZ_MASK 0x000000F0u + #define _MCASP_XFMT_XSSZ_SHIFT 0x00000004u + #define MCASP_XFMT_XSSZ_DEFAULT 0x00000000u + #define MCASP_XFMT_XSSZ_OF(x) _VALUEOF(x) + #define MCASP_XFMT_XSSZ_8BITS 0x00000003u + #define MCASP_XFMT_XSSZ_12BITS 0x00000005u + #define MCASP_XFMT_XSSZ_16BITS 0x00000007u + #define MCASP_XFMT_XSSZ_20BITS 0x00000009u + #define MCASP_XFMT_XSSZ_24BITS 0x0000000Bu + #define MCASP_XFMT_XSSZ_28BITS 0x0000000Du + #define MCASP_XFMT_XSSZ_32BITS 0x0000000Fu + + #define _MCASP_XFMT_XBUSEL_MASK 0x00000008u + #define _MCASP_XFMT_XBUSEL_SHIFT 0x00000003u + #define MCASP_XFMT_XBUSEL_DEFAULT 0x00000000u + #define MCASP_XFMT_XBUSEL_OF(x) _VALUEOF(x) + #define MCASP_XFMT_XBUSEL_DAT 0x00000000u + #define MCASP_XFMT_XBUSEL_CFG 0x00000001u + + #define _MCASP_XFMT_XROT_MASK 0x00000007u + #define _MCASP_XFMT_XROT_SHIFT 0x00000000u + #define MCASP_XFMT_XROT_DEFAULT 0x00000000u + #define MCASP_XFMT_XROT_OF(x) _VALUEOF(x) + #define MCASP_XFMT_XROT_NONE 0x00000000u + #define MCASP_XFMT_XROT_4BITS 0x00000001u + #define MCASP_XFMT_XROT_8BITS 0x00000002u + #define MCASP_XFMT_XROT_12BITS 0x00000003u + #define MCASP_XFMT_XROT_16BITS 0x00000004u + #define MCASP_XFMT_XROT_20BITS 0x00000005u + #define MCASP_XFMT_XROT_24BITS 0x00000006u + #define MCASP_XFMT_XROT_28BITS 0x00000007u + + #define MCASP_XFMT_OF(x) _VALUEOF(x) + + #define MCASP_XFMT_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,XFMT,XDATDLY)\ + |_PER_FDEFAULT(MCASP,XFMT,XRVRS)\ + |_PER_FDEFAULT(MCASP,XFMT,XPAD)\ + |_PER_FDEFAULT(MCASP,XFMT,XPBIT)\ + |_PER_FDEFAULT(MCASP,XFMT,XSSZ)\ + |_PER_FDEFAULT(MCASP,XFMT,XBUSEL)\ + |_PER_FDEFAULT(MCASP,XFMT,XROT)\ + ) + + #define MCASP_XFMT_RMK(xdatdly,xrvrs,xpad,xpbit,xssz,xbusel,xrot) (Uint32)( \ + _PER_FMK(MCASP,XFMT,XDATDLY,xdatdly)\ + |_PER_FMK(MCASP,XFMT,XRVRS,xrvrs)\ + |_PER_FMK(MCASP,XFMT,XPAD,xpad)\ + |_PER_FMK(MCASP,XFMT,XPBIT,xpbit)\ + |_PER_FMK(MCASP,XFMT,XSSZ,xssz)\ + |_PER_FMK(MCASP,XFMT,XBUSEL,xbusel)\ + |_PER_FMK(MCASP,XFMT,XROT,xrot)\ + ) + + #define _MCASP_XFMT_FGET(N,FIELD)\ + _PER_FGET(_MCASP_XFMT##N##_ADDR,MCASP,XFMT,##FIELD) + + #define _MCASP_XFMT_FSET(N,FIELD,field)\ + _PER_FSET(_MCASP_XFMT##N##_ADDR,MCASP,XFMT,##FIELD,field) + + #define _MCASP_XFMT_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCASP_XFMT##N##_ADDR,MCASP,XFMT,##FIELD,##SYM) + + #define _MCASP_XFMT0_FGET(FIELD) _MCASP_XFMT_FGET(0,##FIELD) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_XFMT1_FGET(FIELD) _MCASP_XFMT_FGET(1,##FIELD) +#endif + + #define _MCASP_XFMT0_FSET(FIELD,f) _MCASP_XFMT_FSET(0,##FIELD,f) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_XFMT1_FSET(FIELD,f) _MCASP_XFMT_FSET(1,##FIELD,f) +#endif + + #define _MCASP_XFMT0_FSETS(FIELD,SYM) _MCASP_XFMT_FSETS(0,##FIELD,##SYM) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_XFMT1_FSETS(FIELD,SYM) _MCASP_XFMT_FSETS(1,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* +* _____________________ +* | | +* | AFSXCTL | +* |___________________| +* +* AFSXCTL - Transmit Frame Control Register +* +* FIELDS (msb -> lsb) +* (rw) XMOD +* (rw) FXWID +* (rw) FSXM +* (rw) FSXP +* +\******************************************************************************/ + + #define _MCASP_AFSXCTL_OFFSET 43 + + #define _MCASP_AFSXCTL0_ADDR (_MCASP_BASE_PORT0+4*_MCASP_AFSXCTL_OFFSET) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_AFSXCTL1_ADDR (_MCASP_BASE_PORT1+4*_MCASP_AFSXCTL_OFFSET) +#endif + + #define _MCASP_AFSXCTL_XMOD_MASK 0x0000FF80u + #define _MCASP_AFSXCTL_XMOD_SHIFT 0x00000007u + #define MCASP_AFSXCTL_XMOD_DEFAULT 0x00000000u + #define MCASP_AFSXCTL_XMOD_OF(x) _VALUEOF(x) + #define MCASP_AFSXCTL_XMOD_BURST 0x00000000u + + #define _MCASP_AFSXCTL_FXWID_MASK 0x00000010u + #define _MCASP_AFSXCTL_FXWID_SHIFT 0x00000004u + #define MCASP_AFSXCTL_FXWID_DEFAULT 0x00000000u + #define MCASP_AFSXCTL_FXWID_OF(x) _VALUEOF(x) + #define MCASP_AFSXCTL_FXWID_BIT 0x00000000u + #define MCASP_AFSXCTL_FXWID_WORD 0x00000001u + + #define _MCASP_AFSXCTL_FSXM_MASK 0x00000002u + #define _MCASP_AFSXCTL_FSXM_SHIFT 0x00000001u + #define MCASP_AFSXCTL_FSXM_DEFAULT 0x00000000u + #define MCASP_AFSXCTL_FSXM_OF(x) _VALUEOF(x) + #define MCASP_AFSXCTL_FSXM_EXTERNAL 0x00000000u + #define MCASP_AFSXCTL_FSXM_INTERNAL 0x00000001u + + + #define _MCASP_AFSXCTL_FSXP_MASK 0x00000001u + #define _MCASP_AFSXCTL_FSXP_SHIFT 0x00000000u + #define MCASP_AFSXCTL_FSXP_DEFAULT 0x00000000u + #define MCASP_AFSXCTL_FSXP_OF(x) _VALUEOF(x) + #define MCASP_AFSXCTL_FSXP_ACTIVEHIGH 0x00000000u + #define MCASP_AFSXCTL_FSXP_ACTIVELOW 0x00000001u + + + #define MCASP_AFSXCTL_OF(x) _VALUEOF(x) + + #define MCASP_AFSXCTL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,AFSXCTL,XMOD)\ + | _PER_FDEFAULT(MCASP,AFSXCTL,FXWID)\ + | _PER_FDEFAULT(MCASP,AFSXCTL,FSXM)\ + | _PER_FDEFAULT(MCASP,AFSXCTL,FSXP)\ + ) + + #define MCASP_AFSXCTL_RMK(xmod, fxwid, fsxm, fsxp) (Uint32)( \ + _PER_FMK(MCASP,AFSXCTL,XMOD,xmod)\ + | _PER_FMK(MCASP,AFSXCTL,FXWID,fxwid)\ + | _PER_FMK(MCASP,AFSXCTL,FSXM,fsxm)\ + | _PER_FMK(MCASP,AFSXCTL,FSXP,fsxp)\ + ) + + #define _MCASP_AFSXCTL_FGET(N,FIELD)\ + _PER_FGET(_MCASP_AFSXCTL##N##_ADDR,MCASP,AFSXCTL,##FIELD) + + #define _MCASP_AFSXCTL_FSET(N,FIELD,field)\ + _PER_FSET(_MCASP_AFSXCTL##N##_ADDR,MCASP,AFSXCTL,##FIELD,field) + + #define _MCASP_AFSXCTL_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCASP_AFSXCTL##N##_ADDR,MCASP,AFSXCTL,##FIELD,##SYM) + + #define _MCASP_AFSXCTL0_FGET(FIELD) _MCASP_AFSXCTL_FGET(0,##FIELD) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_AFSXCTL1_FGET(FIELD) _MCASP_AFSXCTL_FGET(1,##FIELD) +#endif + + #define _MCASP_AFSXCTL0_FSET(FIELD,f) _MCASP_AFSXCTL_FSET(0,##FIELD,f) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_AFSXCTL1_FSET(FIELD,f) _MCASP_AFSXCTL_FSET(1,##FIELD,f) +#endif + + #define _MCASP_AFSXCTL0_FSETS(FIELD,SYM) _MCASP_AFSXCTL_FSETS(0,##FIELD,##SYM) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_AFSXCTL1_FSETS(FIELD,SYM) _MCASP_AFSXCTL_FSETS(1,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* +* _____________________ +* | | +* | ACLKXCTL | +* |___________________| +* +* ACLKXCTL - Transmit Clock Control Register +* +* FIELDS (msb -> lsb) +* (rw) CLKXP +* (rw) ASYNC +* (rw) CLKXM +* (rw) CLKXDIV +* +* +\******************************************************************************/ + + #define _MCASP_ACLKXCTL_OFFSET 44 + + #define _MCASP_ACLKXCTL0_ADDR (_MCASP_BASE_PORT0+4*_MCASP_ACLKXCTL_OFFSET) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_ACLKXCTL1_ADDR (_MCASP_BASE_PORT1+4*_MCASP_ACLKXCTL_OFFSET) +#endif + + + #define _MCASP_ACLKXCTL_CLKXP_MASK 0x00000080u + #define _MCASP_ACLKXCTL_CLKXP_SHIFT 0x00000007u + #define MCASP_ACLKXCTL_CLKXP_DEFAULT 0x00000000u + #define MCASP_ACLKXCTL_CLKXP_OF(x) _VALUEOF(x) + #define MCASP_ACLKXCTL_CLKXP_RISING 0x00000000u + #define MCASP_ACLKXCTL_CLKXP_FALLING 0x00000001u + + + #define _MCASP_ACLKXCTL_ASYNC_MASK 0x00000040u + #define _MCASP_ACLKXCTL_ASYNC_SHIFT 0x00000006u + #define MCASP_ACLKXCTL_ASYNC_DEFAULT 0x00000001u + #define MCASP_ACLKXCTL_ASYNC_OF(x) _VALUEOF(x) + #define MCASP_ACLKXCTL_ASYNC_SYNC 0x00000000u + #define MCASP_ACLKXCTL_ASYNC_ASYNC 0x00000001u + + + #define _MCASP_ACLKXCTL_CLKXM_MASK 0x00000020u + #define _MCASP_ACLKXCTL_CLKXM_SHIFT 0x00000005u + #define MCASP_ACLKXCTL_CLKXM_DEFAULT 0x00000001u + #define MCASP_ACLKXCTL_CLKXM_OF(x) _VALUEOF(x) + #define MCASP_ACLKXCTL_CLKXM_EXTERNAL 0x00000000u + #define MCASP_ACLKXCTL_CLKXM_INTERNAL 0x00000001u + + + #define _MCASP_ACLKXCTL_CLKXDIV_MASK 0x0000001Fu + #define _MCASP_ACLKXCTL_CLKXDIV_SHIFT 0x00000000u + #define MCASP_ACLKXCTL_CLKXDIV_DEFAULT 0x00000000u + #define MCASP_ACLKXCTL_CLKXDIV_OF(x) _VALUEOF(x) + + #define MCASP_ACLKXCTL_OF(x) _VALUEOF(x) + + #define MCASP_ACLKXCTL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,ACLKXCTL,CLKXP)\ + | _PER_FDEFAULT(MCASP,ACLKXCTL,ASYNC)\ + | _PER_FDEFAULT(MCASP,ACLKXCTL,CLKXM)\ + | _PER_FDEFAULT(MCASP,ACLKXCTL,CLKXDIV)\ + ) + + #define MCASP_ACLKXCTL_RMK(clkxp, async, clkxm, clkxdiv) (Uint32)( \ + _PER_FMK(MCASP,ACLKXCTL,CLKXP,clkxp)\ + | _PER_FMK(MCASP,ACLKXCTL,ASYNC,async)\ + | _PER_FMK(MCASP,ACLKXCTL,CLKXM,clkxm)\ + | _PER_FMK(MCASP,ACLKXCTL,CLKXDIV,clkxdiv)\ + ) + + + #define _MCASP_ACLKXCTL_FGET(N,FIELD)\ + _PER_FGET(_MCASP_ACLKXCTL##N##_ADDR,MCASP,ACLKXCTL,##FIELD) + + #define _MCASP_ACLKXCTL_FSET(N,FIELD,field)\ + _PER_FSET(_MCASP_ACLKXCTL##N##_ADDR,MCASP,ACLKXCTL,##FIELD,field) + + #define _MCASP_ACLKXCTL_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCASP_ACLKXCTL##N##_ADDR,MCASP,ACLKXCTL,##FIELD,##SYM) + + #define _MCASP_ACLKXCTL0_FGET(FIELD) _MCASP_ACLKXCTL_FGET(0,##FIELD) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_ACLKXCTL1_FGET(FIELD) _MCASP_ACLKXCTL_FGET(1,##FIELD) +#endif + + #define _MCASP_ACLKXCTL0_FSET(FIELD,f) _MCASP_ACLKXCTL_FSET(0,##FIELD,f) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_ACLKXCTL1_FSET(FIELD,f) _MCASP_ACLKXCTL_FSET(1,##FIELD,f) +#endif + + #define _MCASP_ACLKXCTL0_FSETS(FIELD,SYM) _MCASP_ACLKXCTL_FSETS(0,##FIELD,##SYM) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_ACLKXCTL1_FSETS(FIELD,SYM) _MCASP_ACLKXCTL_FSETS(1,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* +* _____________________ +* | | +* | AHCLKXCTL | +* |___________________| +* +* AHCLKXCTL - High Frequency Transmit Clock Control Register +* +* FIELDS (msb -> lsb) +* (rw) HCLKXM +* (rw) HCLKXDIV +* +\******************************************************************************/ + + #define _MCASP_AHCLKXCTL_OFFSET 45 + + #define _MCASP_AHCLKXCTL0_ADDR (_MCASP_BASE_PORT0+4*_MCASP_AHCLKXCTL_OFFSET) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_AHCLKXCTL1_ADDR (_MCASP_BASE_PORT1+4*_MCASP_AHCLKXCTL_OFFSET) +#endif + + #define _MCASP_AHCLKXCTL_HCLKXM_MASK 0x00008000u + #define _MCASP_AHCLKXCTL_HCLKXM_SHIFT 0x0000000Fu + #define MCASP_AHCLKXCTL_HCLKXM_DEFAULT 0x00000001u + #define MCASP_AHCLKXCTL_HCLKXM_OF(x) _VALUEOF(x) + #define MCASP_AHCLKXCTL_HCLKXM_EXTERNAL 0x00000000u + #define MCASP_AHCLKXCTL_HCLKXM_INTERNAL 0x00000001u + + #define _MCASP_AHCLKXCTL_HCLKXP_MASK 0x00004000u + #define _MCASP_AHCLKXCTL_HCLKXP_SHIFT 0x0000000Eu + #define MCASP_AHCLKXCTL_HCLKXP_DEFAULT 0x00000000u + #define MCASP_AHCLKXCTL_HCLKXP_OF(x) _VALUEOF(x) + #define MCASP_AHCLKXCTL_HCLKXP_RISING 0x00000000u + #define MCASP_AHCLKXCTL_HCLKXP_FALLING 0x00000001u + + #define _MCASP_AHCLKXCTL_HCLKXDIV_MASK 0x00000FFFu + #define _MCASP_AHCLKXCTL_HCLKXDIV_SHIFT 0x00000000u + #define MCASP_AHCLKXCTL_HCLKXDIV_DEFAULT 0x00000000u + #define MCASP_AHCLKXCTL_HCLKXDIV_OF(x) _VALUEOF(x) + + + #define MCASP_AHCLKXCTL_OF(x) _VALUEOF(x) + + #define MCASP_AHCLKXCTL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,AHCLKXCTL,HCLKXM)\ + | _PER_FDEFAULT(MCASP,AHCLKXCTL,HCLKXP)\ + | _PER_FDEFAULT(MCASP,AHCLKXCTL,HCLKXDIV)\ + ) + + #define MCASP_AHCLKXCTL_RMK(hclkxm,hclkxp,hclkxdiv) (Uint32)( \ + _PER_FMK(MCASP,AHCLKXCTL,HCLKXM,hclkxm)\ + | _PER_FMK(MCASP,AHCLKXCTL,HCLKXP,hclkxp)\ + | _PER_FMK(MCASP,AHCLKXCTL,HCLKXDIV,hclkxdiv)\ + ) + + #define _MCASP_AHCLKXCTL_FGET(N,FIELD)\ + _PER_FGET(_MCASP_AHCLKXCTL##N##_ADDR,MCASP,AHCLKXCTL,##FIELD) + + #define _MCASP_AHCLKXCTL_FSET(N,FIELD,field)\ + _PER_FSET(_MCASP_AHCLKXCTL##N##_ADDR,MCASP,AHCLKXCTL,##FIELD,field) + + #define _MCASP_AHCLKXCTL_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCASP_AHCLKXCTL##N##_ADDR,MCASP,AHCLKXCTL,##FIELD,##SYM) + + #define _MCASP_AHCLKXCTL0_FGET(FIELD) _MCASP_AHCLKXCTL_FGET(0,##FIELD) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_AHCLKXCTL1_FGET(FIELD) _MCASP_AHCLKXCTL_FGET(1,##FIELD) +#endif + + #define _MCASP_AHCLKXCTL0_FSET(FIELD,f) _MCASP_AHCLKXCTL_FSET(0,##FIELD,f) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_AHCLKXCTL1_FSET(FIELD,f) _MCASP_AHCLKXCTL_FSET(1,##FIELD,f) +#endif + + #define _MCASP_AHCLKXCTL0_FSETS(FIELD,SYM) _MCASP_AHCLKXCTL_FSETS(0,##FIELD,##SYM) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_AHCLKXCTL1_FSETS(FIELD,SYM) _MCASP_AHCLKXCTL_FSETS(1,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* +* _____________________ +* | | +* | X T D M | +* |___________________| +* +* XTDM - Transmit TDM register +* +* FIELDS (msb -> lsb) +* (rw) XTDMS0 +* (rw) XTDMS1 +* . +* . +* . +* (rw) XTDMS31 +* +\******************************************************************************/ + + #define _MCASP_XTDM_OFFSET 46 + + #define _MCASP_XTDM0_ADDR (_MCASP_BASE_PORT0+4*_MCASP_XTDM_OFFSET) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_XTDM1_ADDR (_MCASP_BASE_PORT1+4*_MCASP_XTDM_OFFSET) +#endif + + #define _MCASP_XTDM_XTDMS31_MASK 0x80000000u + #define _MCASP_XTDM_XTDMS31_SHIFT 0x0000001Fu + #define MCASP_XTDM_XTDMS31_DEFAULT 0x00000000u + #define MCASP_XTDM_XTDMS31_OF(x) _VALUEOF(x) + #define MCASP_XTDM_XTDMS31_INACTIVE 0x00000000u + #define MCASP_XTDM_XTDMS31_ACTIVE 0x00000001u + + + #define _MCASP_XTDM_XTDMS30_MASK 0x40000000u + #define _MCASP_XTDM_XTDMS30_SHIFT 0x0000001Eu + #define MCASP_XTDM_XTDMS30_DEFAULT 0x00000000u + #define MCASP_XTDM_XTDMS30_OF(x) _VALUEOF(x) + #define MCASP_XTDM_XTDMS30_INACTIVE 0x00000000u + #define MCASP_XTDM_XTDMS30_ACTIVE 0x00000001u + + + #define _MCASP_XTDM_XTDMS29_MASK 0x20000000u + #define _MCASP_XTDM_XTDMS29_SHIFT 0x0000001Du + #define MCASP_XTDM_XTDMS29_DEFAULT 0x00000000u + #define MCASP_XTDM_XTDMS29_OF(x) _VALUEOF(x) + #define MCASP_XTDM_XTDMS29_INACTIVE 0x00000000u + #define MCASP_XTDM_XTDMS29_ACTIVE 0x00000001u + + + #define _MCASP_XTDM_XTDMS28_MASK 0x10000000u + #define _MCASP_XTDM_XTDMS28_SHIFT 0x0000001Cu + #define MCASP_XTDM_XTDMS28_DEFAULT 0x00000000u + #define MCASP_XTDM_XTDMS28_OF(x) _VALUEOF(x) + #define MCASP_XTDM_XTDMS28_INACTIVE 0x00000000u + #define MCASP_XTDM_XTDMS28_ACTIVE 0x00000001u + + + #define _MCASP_XTDM_XTDMS27_MASK 0x08000000u + #define _MCASP_XTDM_XTDMS27_SHIFT 0x0000001Bu + #define MCASP_XTDM_XTDMS27_DEFAULT 0x00000000u + #define MCASP_XTDM_XTDMS27_OF(x) _VALUEOF(x) + #define MCASP_XTDM_XTDMS27_INACTIVE 0x00000000u + #define MCASP_XTDM_XTDMS27_ACTIVE 0x00000001u + + + #define _MCASP_XTDM_XTDMS26_MASK 0x04000000u + #define _MCASP_XTDM_XTDMS26_SHIFT 0x0000001Au + #define MCASP_XTDM_XTDMS26_DEFAULT 0x00000000u + #define MCASP_XTDM_XTDMS26_OF(x) _VALUEOF(x) + #define MCASP_XTDM_XTDMS26_INACTIVE 0x00000000u + #define MCASP_XTDM_XTDMS26_ACTIVE 0x00000001u + + + #define _MCASP_XTDM_XTDMS25_MASK 0x02000000u + #define _MCASP_XTDM_XTDMS25_SHIFT 0x00000019u + #define MCASP_XTDM_XTDMS25_DEFAULT 0x00000000u + #define MCASP_XTDM_XTDMS25_OF(x) _VALUEOF(x) + #define MCASP_XTDM_XTDMS25_INACTIVE 0x00000000u + #define MCASP_XTDM_XTDMS25_ACTIVE 0x00000001u + + + #define _MCASP_XTDM_XTDMS24_MASK 0x01000000u + #define _MCASP_XTDM_XTDMS24_SHIFT 0x00000018u + #define MCASP_XTDM_XTDMS24_DEFAULT 0x00000000u + #define MCASP_XTDM_XTDMS24_OF(x) _VALUEOF(x) + #define MCASP_XTDM_XTDMS24_INACTIVE 0x00000000u + #define MCASP_XTDM_XTDMS24_ACTIVE 0x00000001u + + + #define _MCASP_XTDM_XTDMS23_MASK 0x00800000u + #define _MCASP_XTDM_XTDMS23_SHIFT 0x00000017u + #define MCASP_XTDM_XTDMS23_DEFAULT 0x00000000u + #define MCASP_XTDM_XTDMS23_OF(x) _VALUEOF(x) + #define MCASP_XTDM_XTDMS23_INACTIVE 0x00000000u + #define MCASP_XTDM_XTDMS23_ACTIVE 0x00000001u + + + #define _MCASP_XTDM_XTDMS22_MASK 0x00400000u + #define _MCASP_XTDM_XTDMS22_SHIFT 0x00000016u + #define MCASP_XTDM_XTDMS22_DEFAULT 0x00000000u + #define MCASP_XTDM_XTDMS22_OF(x) _VALUEOF(x) + #define MCASP_XTDM_XTDMS22_INACTIVE 0x00000000u + #define MCASP_XTDM_XTDMS22_ACTIVE 0x00000001u + + + #define _MCASP_XTDM_XTDMS21_MASK 0x00200000u + #define _MCASP_XTDM_XTDMS21_SHIFT 0x00000015u + #define MCASP_XTDM_XTDMS21_DEFAULT 0x00000000u + #define MCASP_XTDM_XTDMS21_OF(x) _VALUEOF(x) + #define MCASP_XTDM_XTDMS21_INACTIVE 0x00000000u + #define MCASP_XTDM_XTDMS21_ACTIVE 0x00000001u + + + #define _MCASP_XTDM_XTDMS20_MASK 0x00100000u + #define _MCASP_XTDM_XTDMS20_SHIFT 0x00000014u + #define MCASP_XTDM_XTDMS20_DEFAULT 0x00000000u + #define MCASP_XTDM_XTDMS20_OF(x) _VALUEOF(x) + #define MCASP_XTDM_XTDMS20_INACTIVE 0x00000000u + #define MCASP_XTDM_XTDMS20_ACTIVE 0x00000001u + + + #define _MCASP_XTDM_XTDMS19_MASK 0x00080000u + #define _MCASP_XTDM_XTDMS19_SHIFT 0x00000013u + #define MCASP_XTDM_XTDMS19_DEFAULT 0x00000000u + #define MCASP_XTDM_XTDMS19_OF(x) _VALUEOF(x) + #define MCASP_XTDM_XTDMS19_INACTIVE 0x00000000u + #define MCASP_XTDM_XTDMS19_ACTIVE 0x00000001u + + + #define _MCASP_XTDM_XTDMS18_MASK 0x00040000u + #define _MCASP_XTDM_XTDMS18_SHIFT 0x00000012u + #define MCASP_XTDM_XTDMS18_DEFAULT 0x00000000u + #define MCASP_XTDM_XTDMS18_OF(x) _VALUEOF(x) + #define MCASP_XTDM_XTDMS18_INACTIVE 0x00000000u + #define MCASP_XTDM_XTDMS18_ACTIVE 0x00000001u + + + #define _MCASP_XTDM_XTDMS17_MASK 0x00020000u + #define _MCASP_XTDM_XTDMS17_SHIFT 0x00000011u + #define MCASP_XTDM_XTDMS17_DEFAULT 0x00000000u + #define MCASP_XTDM_XTDMS17_OF(x) _VALUEOF(x) + #define MCASP_XTDM_XTDMS17_INACTIVE 0x00000000u + #define MCASP_XTDM_XTDMS17_ACTIVE 0x00000001u + + + #define _MCASP_XTDM_XTDMS16_MASK 0x00010000u + #define _MCASP_XTDM_XTDMS16_SHIFT 0x00000010u + #define MCASP_XTDM_XTDMS16_DEFAULT 0x00000000u + #define MCASP_XTDM_XTDMS16_OF(x) _VALUEOF(x) + #define MCASP_XTDM_XTDMS16_INACTIVE 0x00000000u + #define MCASP_XTDM_XTDMS16_ACTIVE 0x00000001u + + + #define _MCASP_XTDM_XTDMS15_MASK 0x00008000u + #define _MCASP_XTDM_XTDMS15_SHIFT 0x0000000Fu + #define MCASP_XTDM_XTDMS15_DEFAULT 0x00000000u + #define MCASP_XTDM_XTDMS15_OF(x) _VALUEOF(x) + #define MCASP_XTDM_XTDMS15_INACTIVE 0x00000000u + #define MCASP_XTDM_XTDMS15_ACTIVE 0x00000001u + + + #define _MCASP_XTDM_XTDMS14_MASK 0x00004000u + #define _MCASP_XTDM_XTDMS14_SHIFT 0x0000000Eu + #define MCASP_XTDM_XTDMS14_DEFAULT 0x00000000u + #define MCASP_XTDM_XTDMS14_OF(x) _VALUEOF(x) + #define MCASP_XTDM_XTDMS14_INACTIVE 0x00000000u + #define MCASP_XTDM_XTDMS14_ACTIVE 0x00000001u + + + #define _MCASP_XTDM_XTDMS13_MASK 0x00002000u + #define _MCASP_XTDM_XTDMS13_SHIFT 0x0000000Du + #define MCASP_XTDM_XTDMS13_DEFAULT 0x00000000u + #define MCASP_XTDM_XTDMS13_OF(x) _VALUEOF(x) + #define MCASP_XTDM_XTDMS13_INACTIVE 0x00000000u + #define MCASP_XTDM_XTDMS13_ACTIVE 0x00000001u + + + #define _MCASP_XTDM_XTDMS12_MASK 0x00001000u + #define _MCASP_XTDM_XTDMS12_SHIFT 0x0000000Cu + #define MCASP_XTDM_XTDMS12_DEFAULT 0x00000000u + #define MCASP_XTDM_XTDMS12_OF(x) _VALUEOF(x) + #define MCASP_XTDM_XTDMS12_INACTIVE 0x00000000u + #define MCASP_XTDM_XTDMS12_ACTIVE 0x00000001u + + + #define _MCASP_XTDM_XTDMS11_MASK 0x00000800u + #define _MCASP_XTDM_XTDMS11_SHIFT 0x0000000Bu + #define MCASP_XTDM_XTDMS11_DEFAULT 0x00000000u + #define MCASP_XTDM_XTDMS11_OF(x) _VALUEOF(x) + #define MCASP_XTDM_XTDMS11_INACTIVE 0x00000000u + #define MCASP_XTDM_XTDMS11_ACTIVE 0x00000001u + + + #define _MCASP_XTDM_XTDMS10_MASK 0x00000400u + #define _MCASP_XTDM_XTDMS10_SHIFT 0x0000000Au + #define MCASP_XTDM_XTDMS10_DEFAULT 0x00000000u + #define MCASP_XTDM_XTDMS10_OF(x) _VALUEOF(x) + #define MCASP_XTDM_XTDMS10_INACTIVE 0x00000000u + #define MCASP_XTDM_XTDMS10_ACTIVE 0x00000001u + + + #define _MCASP_XTDM_XTDMS9_MASK 0x00000200u + #define _MCASP_XTDM_XTDMS9_SHIFT 0x00000009u + #define MCASP_XTDM_XTDMS9_DEFAULT 0x00000000u + #define MCASP_XTDM_XTDMS9_OF(x) _VALUEOF(x) + #define MCASP_XTDM_XTDMS9_INACTIVE 0x00000000u + #define MCASP_XTDM_XTDMS9_ACTIVE 0x00000001u + + + #define _MCASP_XTDM_XTDMS8_MASK 0x00000100u + #define _MCASP_XTDM_XTDMS8_SHIFT 0x00000008u + #define MCASP_XTDM_XTDMS8_DEFAULT 0x00000000u + #define MCASP_XTDM_XTDMS8_OF(x) _VALUEOF(x) + #define MCASP_XTDM_XTDMS8_INACTIVE 0x00000000u + #define MCASP_XTDM_XTDMS8_ACTIVE 0x00000001u + + + #define _MCASP_XTDM_XTDMS7_MASK 0x00000080u + #define _MCASP_XTDM_XTDMS7_SHIFT 0x00000007u + #define MCASP_XTDM_XTDMS7_DEFAULT 0x00000000u + #define MCASP_XTDM_XTDMS7_OF(x) _VALUEOF(x) + #define MCASP_XTDM_XTDMS7_INACTIVE 0x00000000u + #define MCASP_XTDM_XTDMS7_ACTIVE 0x00000001u + + + #define _MCASP_XTDM_XTDMS6_MASK 0x00000040u + #define _MCASP_XTDM_XTDMS6_SHIFT 0x00000006u + #define MCASP_XTDM_XTDMS6_DEFAULT 0x00000000u + #define MCASP_XTDM_XTDMS6_OF(x) _VALUEOF(x) + #define MCASP_XTDM_XTDMS6_INACTIVE 0x00000000u + #define MCASP_XTDM_XTDMS6_ACTIVE 0x00000001u + + + #define _MCASP_XTDM_XTDMS5_MASK 0x00000020u + #define _MCASP_XTDM_XTDMS5_SHIFT 0x00000005u + #define MCASP_XTDM_XTDMS5_DEFAULT 0x00000000u + #define MCASP_XTDM_XTDMS5_OF(x) _VALUEOF(x) + #define MCASP_XTDM_XTDMS5_INACTIVE 0x00000000u + #define MCASP_XTDM_XTDMS5_ACTIVE 0x00000001u + + + #define _MCASP_XTDM_XTDMS4_MASK 0x00000010u + #define _MCASP_XTDM_XTDMS4_SHIFT 0x00000004u + #define MCASP_XTDM_XTDMS4_DEFAULT 0x00000000u + #define MCASP_XTDM_XTDMS4_OF(x) _VALUEOF(x) + #define MCASP_XTDM_XTDMS4_INACTIVE 0x00000000u + #define MCASP_XTDM_XTDMS4_ACTIVE 0x00000001u + + + #define _MCASP_XTDM_XTDMS3_MASK 0x00000008u + #define _MCASP_XTDM_XTDMS3_SHIFT 0x00000003u + #define MCASP_XTDM_XTDMS3_DEFAULT 0x00000000u + #define MCASP_XTDM_XTDMS3_OF(x) _VALUEOF(x) + #define MCASP_XTDM_XTDMS3_INACTIVE 0x00000000u + #define MCASP_XTDM_XTDMS3_ACTIVE 0x00000001u + + + #define _MCASP_XTDM_XTDMS2_MASK 0x00000004u + #define _MCASP_XTDM_XTDMS2_SHIFT 0x00000002u + #define MCASP_XTDM_XTDMS2_DEFAULT 0x00000000u + #define MCASP_XTDM_XTDMS2_OF(x) _VALUEOF(x) + #define MCASP_XTDM_XTDMS2_INACTIVE 0x00000000u + #define MCASP_XTDM_XTDMS2_ACTIVE 0x00000001u + + + #define _MCASP_XTDM_XTDMS1_MASK 0x00000002u + #define _MCASP_XTDM_XTDMS1_SHIFT 0x00000001u + #define MCASP_XTDM_XTDMS1_DEFAULT 0x00000000u + #define MCASP_XTDM_XTDMS1_OF(x) _VALUEOF(x) + #define MCASP_XTDM_XTDMS1_INACTIVE 0x00000000u + #define MCASP_XTDM_XTDMS1_ACTIVE 0x00000001u + + + #define _MCASP_XTDM_XTDMS0_MASK 0x00000001u + #define _MCASP_XTDM_XTDMS0_SHIFT 0x00000000u + #define MCASP_XTDM_XTDMS0_DEFAULT 0x00000000u + #define MCASP_XTDM_XTDMS0_OF(x) _VALUEOF(x) + #define MCASP_XTDM_XTDMS0_INACTIVE 0x00000000u + #define MCASP_XTDM_XTDMS0_ACTIVE 0x00000001u + + + #define MCASP_XTDM_OF(x) _VALUEOF(x) + + #define MCASP_XTDM_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,XTDM,XTDMS31)\ + | _PER_FDEFAULT(MCASP,XTDM,XTDMS30)\ + | _PER_FDEFAULT(MCASP,XTDM,XTDMS29)\ + | _PER_FDEFAULT(MCASP,XTDM,XTDMS28)\ + | _PER_FDEFAULT(MCASP,XTDM,XTDMS27)\ + | _PER_FDEFAULT(MCASP,XTDM,XTDMS26)\ + | _PER_FDEFAULT(MCASP,XTDM,XTDMS25)\ + | _PER_FDEFAULT(MCASP,XTDM,XTDMS24)\ + | _PER_FDEFAULT(MCASP,XTDM,XTDMS23)\ + | _PER_FDEFAULT(MCASP,XTDM,XTDMS22)\ + | _PER_FDEFAULT(MCASP,XTDM,XTDMS21)\ + | _PER_FDEFAULT(MCASP,XTDM,XTDMS20)\ + | _PER_FDEFAULT(MCASP,XTDM,XTDMS19)\ + | _PER_FDEFAULT(MCASP,XTDM,XTDMS18)\ + | _PER_FDEFAULT(MCASP,XTDM,XTDMS17)\ + | _PER_FDEFAULT(MCASP,XTDM,XTDMS16)\ + | _PER_FDEFAULT(MCASP,XTDM,XTDMS15)\ + | _PER_FDEFAULT(MCASP,XTDM,XTDMS14)\ + | _PER_FDEFAULT(MCASP,XTDM,XTDMS13)\ + | _PER_FDEFAULT(MCASP,XTDM,XTDMS12)\ + | _PER_FDEFAULT(MCASP,XTDM,XTDMS11)\ + | _PER_FDEFAULT(MCASP,XTDM,XTDMS10)\ + | _PER_FDEFAULT(MCASP,XTDM,XTDMS9)\ + | _PER_FDEFAULT(MCASP,XTDM,XTDMS8)\ + | _PER_FDEFAULT(MCASP,XTDM,XTDMS7)\ + | _PER_FDEFAULT(MCASP,XTDM,XTDMS6)\ + | _PER_FDEFAULT(MCASP,XTDM,XTDMS5)\ + | _PER_FDEFAULT(MCASP,XTDM,XTDMS4)\ + | _PER_FDEFAULT(MCASP,XTDM,XTDMS3)\ + | _PER_FDEFAULT(MCASP,XTDM,XTDMS2)\ + | _PER_FDEFAULT(MCASP,XTDM,XTDMS1)\ + | _PER_FDEFAULT(MCASP,XTDM,XTDMS0)\ + ) + + #define MCASP_XTDM_RMK(xtdms31, xtdms30, xtdms29, xtdms28, xtdms27, xtdms26, xtdms25, xtdms24, xtdms23, xtdms22, xtdms21, xtdms20, xtdms19, xtdms18, xtdms17, xtdms16, xtdms15, xtdms14, xtdms13, xtdms12, xtdms11, xtdms10, xtdms9, xtdms8, xtdms7, xtdms6, xtdms5, xtdms4, xtdms3, xtdms2, xtdms1, xtdms0) (Uint32)( \ + _PER_FMK(MCASP,XTDM,XTDMS31,xtdms31)\ + | _PER_FMK(MCASP,XTDM,XTDMS30,xtdms30)\ + | _PER_FMK(MCASP,XTDM,XTDMS29,xtdms29)\ + | _PER_FMK(MCASP,XTDM,XTDMS28,xtdms28)\ + | _PER_FMK(MCASP,XTDM,XTDMS27,xtdms27)\ + | _PER_FMK(MCASP,XTDM,XTDMS26,xtdms26)\ + | _PER_FMK(MCASP,XTDM,XTDMS25,xtdms25)\ + | _PER_FMK(MCASP,XTDM,XTDMS24,xtdms24)\ + | _PER_FMK(MCASP,XTDM,XTDMS23,xtdms23)\ + | _PER_FMK(MCASP,XTDM,XTDMS22,xtdms22)\ + | _PER_FMK(MCASP,XTDM,XTDMS21,xtdms21)\ + | _PER_FMK(MCASP,XTDM,XTDMS20,xtdms20)\ + | _PER_FMK(MCASP,XTDM,XTDMS19,xtdms19)\ + | _PER_FMK(MCASP,XTDM,XTDMS18,xtdms18)\ + | _PER_FMK(MCASP,XTDM,XTDMS17,xtdms17)\ + | _PER_FMK(MCASP,XTDM,XTDMS16,xtdms16)\ + | _PER_FMK(MCASP,XTDM,XTDMS15,xtdms15)\ + | _PER_FMK(MCASP,XTDM,XTDMS14,xtdms14)\ + | _PER_FMK(MCASP,XTDM,XTDMS13,xtdms13)\ + | _PER_FMK(MCASP,XTDM,XTDMS12,xtdms12)\ + | _PER_FMK(MCASP,XTDM,XTDMS11,xtdms11)\ + | _PER_FMK(MCASP,XTDM,XTDMS10,xtdms10)\ + | _PER_FMK(MCASP,XTDM,XTDMS9,xtdms9)\ + | _PER_FMK(MCASP,XTDM,XTDMS8,xtdms8)\ + | _PER_FMK(MCASP,XTDM,XTDMS7,xtdms7)\ + | _PER_FMK(MCASP,XTDM,XTDMS6,xtdms6)\ + | _PER_FMK(MCASP,XTDM,XTDMS5,xtdms5)\ + | _PER_FMK(MCASP,XTDM,XTDMS4,xtdms4)\ + | _PER_FMK(MCASP,XTDM,XTDMS3,xtdms3)\ + | _PER_FMK(MCASP,XTDM,XTDMS2,xtdms2)\ + | _PER_FMK(MCASP,XTDM,XTDMS1,xtdms1)\ + | _PER_FMK(MCASP,XTDM,XTDMS0,xtdms0)\ + ) + + + #define _MCASP_XTDM_FGET(N,FIELD)\ + _PER_FGET(_MCASP_XTDM##N##_ADDR,MCASP,XTDM,##FIELD) + + #define _MCASP_XTDM_FSET(N,FIELD,field)\ + _PER_FSET(_MCASP_XTDM##N##_ADDR,MCASP,XTDM,##FIELD,field) + + #define _MCASP_XTDM_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCASP_XTDM##N##_ADDR,MCASP,XTDM,##FIELD,##SYM) + + #define _MCASP_XTDM0_FGET(FIELD) _MCASP_XTDM_FGET(0,##FIELD) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_XTDM1_FGET(FIELD) _MCASP_XTDM_FGET(1,##FIELD) +#endif + + #define _MCASP_XTDM0_FSET(FIELD,f) _MCASP_XTDM_FSET(0,##FIELD,f) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_XTDM1_FSET(FIELD,f) _MCASP_XTDM_FSET(1,##FIELD,f) +#endif + + #define _MCASP_XTDM0_FSETS(FIELD,SYM) _MCASP_XTDM_FSETS(0,##FIELD,##SYM) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_XTDM1_FSETS(FIELD,SYM) _MCASP_XTDM_FSETS(1,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* +* _____________________ +* | | +* | XINTCTL | +* |___________________| +* +* XINTCTL - Transmitter Interrupt Control Register +* +* FIELDS (msb -> lsb) +* (rw) XSTAFRM +* (rw) XDATA +* (rw) XLAST +* (rw) XDMAERR +* (rw) XCKFAIL +* (rw) XSYNCERR +* (rw) XUNDRN +* +\******************************************************************************/ + + #define _MCASP_XINTCTL_OFFSET 47 + + #define _MCASP_XINTCTL0_ADDR (_MCASP_BASE_PORT0+4*_MCASP_XINTCTL_OFFSET) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_XINTCTL1_ADDR (_MCASP_BASE_PORT1+4*_MCASP_XINTCTL_OFFSET) +#endif + + #define _MCASP_XINTCTL_XSTAFRM_MASK 0x00000080u + #define _MCASP_XINTCTL_XSTAFRM_SHIFT 0x00000007u + #define MCASP_XINTCTL_XSTAFRM_DEFAULT 0x00000000u + #define MCASP_XINTCTL_XSTAFRM_OF(x) _VALUEOF(x) + #define MCASP_XINTCTL_XSTAFRM_DISABLE 0x00000000u + #define MCASP_XINTCTL_XSTAFRM_ENABLE 0x00000001u + + + #define _MCASP_XINTCTL_XDATA_MASK 0x00000020u + #define _MCASP_XINTCTL_XDATA_SHIFT 0x00000005u + #define MCASP_XINTCTL_XDATA_DEFAULT 0x00000000u + #define MCASP_XINTCTL_XDATA_OF(x) _VALUEOF(x) + #define MCASP_XINTCTL_XDATA_DISABLE 0x00000000u + #define MCASP_XINTCTL_XDATA_ENABLE 0x00000001u + + + #define _MCASP_XINTCTL_XLAST_MASK 0x00000010u + #define _MCASP_XINTCTL_XLAST_SHIFT 0x00000004u + #define MCASP_XINTCTL_XLAST_DEFAULT 0x00000000u + #define MCASP_XINTCTL_XLAST_OF(x) _VALUEOF(x) + #define MCASP_XINTCTL_XLAST_DISABLE 0x00000000u + #define MCASP_XINTCTL_XLAST_ENABLE 0x00000001u + + + #define _MCASP_XINTCTL_XDMAERR_MASK 0x00000008u + #define _MCASP_XINTCTL_XDMAERR_SHIFT 0x00000003u + #define MCASP_XINTCTL_XDMAERR_DEFAULT 0x00000000u + #define MCASP_XINTCTL_XDMAERR_OF(x) _VALUEOF(x) + #define MCASP_XINTCTL_XDMAERR_DISABLE 0x00000000u + #define MCASP_XINTCTL_XDMAERR_ENABLE 0x00000001u + + + #define _MCASP_XINTCTL_XCKFAIL_MASK 0x00000004u + #define _MCASP_XINTCTL_XCKFAIL_SHIFT 0x00000002u + #define MCASP_XINTCTL_XCKFAIL_DEFAULT 0x00000000u + #define MCASP_XINTCTL_XCKFAIL_OF(x) _VALUEOF(x) + #define MCASP_XINTCTL_XCKFAIL_DISABLE 0x00000000u + #define MCASP_XINTCTL_XCKFAIL_ENABLE 0x00000001u + + + #define _MCASP_XINTCTL_XSYNCERR_MASK 0x00000002u + #define _MCASP_XINTCTL_XSYNCERR_SHIFT 0x00000001u + #define MCASP_XINTCTL_XSYNCERR_DEFAULT 0x00000000u + #define MCASP_XINTCTL_XSYNCERR_OF(x) _VALUEOF(x) + #define MCASP_XINTCTL_XSYNCERR_DISABLE 0x00000000u + #define MCASP_XINTCTL_XSYNCERR_ENABLE 0x00000001u + + + #define _MCASP_XINTCTL_XUNDRN_MASK 0x00000001u + #define _MCASP_XINTCTL_XUNDRN_SHIFT 0x00000000u + #define MCASP_XINTCTL_XUNDRN_DEFAULT 0x00000000u + #define MCASP_XINTCTL_XUNDRN_OF(x) _VALUEOF(x) + #define MCASP_XINTCTL_XUNDRN_DISABLE 0x00000000u + #define MCASP_XINTCTL_XUNDRN_ENABLE 0x00000001u + + + #define MCASP_XINTCTL_OF(x) _VALUEOF(x) + + + + #define MCASP_XINTCTL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,XINTCTL,XSTAFRM)\ + |_PER_FDEFAULT(MCASP,XINTCTL,XDATA)\ + |_PER_FDEFAULT(MCASP,XINTCTL,XLAST)\ + |_PER_FDEFAULT(MCASP,XINTCTL,XDMAERR)\ + |_PER_FDEFAULT(MCASP,XINTCTL,XCKFAIL)\ + |_PER_FDEFAULT(MCASP,XINTCTL,XSYNCERR)\ + |_PER_FDEFAULT(MCASP,XINTCTL,XUNDRN)\ + ) + + + #define MCASP_XINTCTL_RMK(xstafrm, xdata, xlast, xdmaerr, xckfail, xsyncerr, xundrn) (Uint32)( \ + _PER_FMK(MCASP,XINTCTL,XSTAFRM,xstafrm)\ + |_PER_FMK(MCASP,XINTCTL,XDATA,xdata)\ + |_PER_FMK(MCASP,XINTCTL,XLAST,xlast)\ + |_PER_FMK(MCASP,XINTCTL,XDMAERR,xdmaerr)\ + |_PER_FMK(MCASP,XINTCTL,XCKFAIL,xckfail)\ + |_PER_FMK(MCASP,XINTCTL,XSYNCERR,xsyncerr)\ + |_PER_FMK(MCASP,XINTCTL,XUNDRN,xundrn)\ + ) + + + #define _MCASP_XINTCTL_FGET(N,FIELD)\ + _PER_FGET(_MCASP_XINTCTL##N##_ADDR,MCASP,XINTCTL,##FIELD) + + #define _MCASP_XINTCTL_FSET(N,FIELD,field)\ + _PER_FSET(_MCASP_XINTCTL##N##_ADDR,MCASP,XINTCTL,##FIELD,field) + + #define _MCASP_XINTCTL_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCASP_XINTCTL##N##_ADDR,MCASP,XINTCTL,##FIELD,##SYM) + + #define _MCASP_XINTCTL0_FGET(FIELD) _MCASP_XINTCTL_FGET(0,##FIELD) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_XINTCTL1_FGET(FIELD) _MCASP_XINTCTL_FGET(1,##FIELD) +#endif + + #define _MCASP_XINTCTL0_FSET(FIELD,f) _MCASP_XINTCTL_FSET(0,##FIELD,f) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_XINTCTL1_FSET(FIELD,f) _MCASP_XINTCTL_FSET(1,##FIELD,f) +#endif + + #define _MCASP_XINTCTL0_FSETS(FIELD,SYM) _MCASP_XINTCTL_FSETS(0,##FIELD,##SYM) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_XINTCTL1_FSETS(FIELD,SYM) _MCASP_XINTCTL_FSETS(1,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* +* _____________________ +* | | +* | XSTAT | +* |___________________| +* +* XSTAT - Transmitter Status Register +* +* FIELDS (msb -> lsb) +* (r) XERR +* (r) XDMAERR +* (r) XSTAFRM +* (r) XDATA +* (r) XLAST +* (r) XTDMSLOT +* (r) XCKFAIL +* (r) XSYNCERR +* (r) XUNDRN +* +\******************************************************************************/ + + #define _MCASP_XSTAT_OFFSET 48 + + #define _MCASP_XSTAT0_ADDR (_MCASP_BASE_PORT0+4*_MCASP_XSTAT_OFFSET) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_XSTAT1_ADDR (_MCASP_BASE_PORT1+4*_MCASP_XSTAT_OFFSET) +#endif + + #define _MCASP_XSTAT_XERR_MASK 0x00000100u + #define _MCASP_XSTAT_XERR_SHIFT 0x00000008u + #define MCASP_XSTAT_XERR_DEFAULT 0x00000000u + #define MCASP_XSTAT_XERR_OF(x) _VALUEOF(x) + + #define _MCASP_XSTAT_XDMAERR_MASK 0x0000080u + #define _MCASP_XSTAT_XDMAERR_SHIFT 0x00000007u + #define MCASP_XSTAT_XDMAERR_DEFAULT 0x00000000u + #define MCASP_XSTAT_XDMAERR_OF(x) _VALUEOF(x) + + #define _MCASP_XSTAT_XSTAFRM_MASK 0x00000040u + #define _MCASP_XSTAT_XSTAFRM_SHIFT 0x00000006u + #define MCASP_XSTAT_XSTAFRM_DEFAULT 0x00000000u + #define MCASP_XSTAT_XSTAFRM_OF(x) _VALUEOF(x) + #define MCASP_XSTAT_XSTAFRM_NO 0x00000000u + #define MCASP_XSTAT_XSTAFRM_YES 0x00000001u + #define MCASP_XSTAT_XSTAFRM_0 0x00000000u + #define MCASP_XSTAT_XSTAFRM_1 0x00000001u + + + #define _MCASP_XSTAT_XDATA_MASK 0x00000020u + #define _MCASP_XSTAT_XDATA_SHIFT 0x00000005u + #define MCASP_XSTAT_XDATA_DEFAULT 0x00000000u + #define MCASP_XSTAT_XDATA_OF(x) _VALUEOF(x) + #define MCASP_XSTAT_XDATA_NO 0x00000000u + #define MCASP_XSTAT_XDATA_YES 0x00000001u + #define MCASP_XSTAT_XDATA_0 0x00000000u + #define MCASP_XSTAT_XDATA_1 0x00000001u + + #define _MCASP_XSTAT_XLAST_MASK 0x00000010u + #define _MCASP_XSTAT_XLAST_SHIFT 0x00000004u + #define MCASP_XSTAT_XLAST_DEFAULT 0x00000000u + #define MCASP_XSTAT_XLAST_OF(x) _VALUEOF(x) + #define MCASP_XSTAT_XLAST_NO 0x00000000u + #define MCASP_XSTAT_XLAST_YES 0x00000001u + #define MCASP_XSTAT_XLAST_0 0x00000000u + #define MCASP_XSTAT_XLAST_1 0x00000001u + + + #define _MCASP_XSTAT_XTDMSLOT_MASK 0x00000008u + #define _MCASP_XSTAT_XTDMSLOT_SHIFT 0x00000003u + #define MCASP_XSTAT_XTDMSLOT_DEFAULT 0x00000000u + #define MCASP_XSTAT_XTDMSLOT_OF(x) _VALUEOF(x) + + + #define _MCASP_XSTAT_XCKFAIL_MASK 0x00000004u + #define _MCASP_XSTAT_XCKFAIL_SHIFT 0x00000002u + #define MCASP_XSTAT_XCKFAIL_DEFAULT 0x00000000u + #define MCASP_XSTAT_XCKFAIL_OF(x) _VALUEOF(x) + #define MCASP_XSTAT_XCKFAIL_NO 0x00000000u + #define MCASP_XSTAT_XCKFAIL_YES 0x00000001u + #define MCASP_XSTAT_XCKFAIL_0 0x00000000u + #define MCASP_XSTAT_XCKFAIL_1 0x00000001u + + + #define _MCASP_XSTAT_XSYNCERR_MASK 0x00000002u + #define _MCASP_XSTAT_XSYNCERR_SHIFT 0x00000001u + #define MCASP_XSTAT_XSYNCERR_DEFAULT 0x00000000u + #define MCASP_XSTAT_XSYNCERR_OF(x) _VALUEOF(x) + #define MCASP_XSTAT_XSYNCERR_NO 0x00000000u + #define MCASP_XSTAT_XSYNCERR_YES 0x00000001u + #define MCASP_XSTAT_XSYNCERR_0 0x00000000u + #define MCASP_XSTAT_XSYNCERR_1 0x00000001u + + + #define _MCASP_XSTAT_XUNDRN_MASK 0x00000001u + #define _MCASP_XSTAT_XUNDRN_SHIFT 0x00000000u + #define MCASP_XSTAT_XUNDRN_DEFAULT 0x00000000u + #define MCASP_XSTAT_XUNDRN_OF(x) _VALUEOF(x) + #define MCASP_XSTAT_XUNDRN_NO 0x00000000u + #define MCASP_XSTAT_XUNDRN_YES 0x00000001u + #define MCASP_XSTAT_XUNDRN_0 0x00000000u + #define MCASP_XSTAT_XUNDRN_1 0x00000001u + + + #define MCASP_XSTAT_OF(x) _VALUEOF(x) + + #define MCASP_XSTAT_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,XSTAT,XERR)\ + | _PER_FDEFAULT(MCASP,XSTAT,XDMAERR)\ + | _PER_FDEFAULT(MCASP,XSTAT,XSTAFRM)\ + | _PER_FDEFAULT(MCASP,XSTAT,XDATA)\ + | _PER_FDEFAULT(MCASP,XSTAT,XLAST)\ + | _PER_FDEFAULT(MCASP,XSTAT,XTDMSLOT)\ + | _PER_FDEFAULT(MCASP,XSTAT,XCKFAIL)\ + | _PER_FDEFAULT(MCASP,XSTAT,XSYNCERR)\ + | _PER_FDEFAULT(MCASP,XSTAT,XUNDRN)\ + ) + + #define MCASP_XSTAT_RMK(xerr, xdmaerr, xstafrm, xdata, xlast, xtdmslot, xckfail, xsyncerr, xundrn) (Uint32)( \ + _PER_FMK(MCASP,XSTAT,XERR,xerr)\ + | _PER_FMK(MCASP,XSTAT,XDMAERR,xdmaerr)\ + | _PER_FMK(MCASP,XSTAT,XSTAFRM,xstafrm)\ + | _PER_FMK(MCASP,XSTAT,XDATA,xdata)\ + | _PER_FMK(MCASP,XSTAT,XLAST,xlast)\ + | _PER_FMK(MCASP,XSTAT,XTDMSLOT,xtdmslot)\ + | _PER_FMK(MCASP,XSTAT,XCKFAIL,xckfail)\ + | _PER_FMK(MCASP,XSTAT,XSYNCERR,xsyncerr)\ + | _PER_FMK(MCASP,XSTAT,XUNDRN,xundrn)\ + ) + + #define _MCASP_XSTAT_FGET(N,FIELD)\ + _PER_FGET(_MCASP_XSTAT##N##_ADDR,MCASP,XSTAT,##FIELD) + + #define _MCASP_XSTAT_FSET(N,FIELD,field)\ + _PER_FSET(_MCASP_XSTAT##N##_ADDR,MCASP,XSTAT,##FIELD,field) + + #define _MCASP_XSTAT_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCASP_XSTAT##N##_ADDR,MCASP,XSTAT,##FIELD,##SYM) + + #define _MCASP_XSTAT0_FGET(FIELD) _MCASP_XSTAT_FGET(0,##FIELD) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_XSTAT1_FGET(FIELD) _MCASP_XSTAT_FGET(1,##FIELD) +#endif + + #define _MCASP_XSTAT0_FSET(FIELD,f) _MCASP_XSTAT_FSET(0,##FIELD,f) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_XSTAT1_FSET(FIELD,f) _MCASP_XSTAT_FSET(1,##FIELD,f) +#endif + + #define _MCASP_XSTAT0_FSETS(FIELD,SYM) _MCASP_XSTAT_FSETS(0,##FIELD,##SYM) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_XSTAT1_FSETS(FIELD,SYM) _MCASP_XSTAT_FSETS(1,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* +* _____________________ +* | | +* | XSLOT | +* |___________________| +* +* XSLOT - Transmitter TDM Slot Counter +* +* FIELDS (msb -> lsb) +* (r ) XSLOTCNT +* +\******************************************************************************/ + + #define _MCASP_XSLOT_OFFSET 49 + + #define _MCASP_XSLOT0_ADDR (_MCASP_BASE_PORT0+4*_MCASP_XSLOT_OFFSET) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_XSLOT1_ADDR (_MCASP_BASE_PORT1+4*_MCASP_XSLOT_OFFSET) +#endif + + #define _MCASP_XSLOT_XSLOTCNT_MASK 0x000003FFu + #define _MCASP_XSLOT_XSLOTCNT_SHIFT 0x00000000u + #define MCASP_XSLOT_XSLOTCNT_DEFAULT 0x0000017Fu /*383*/ + #define MCASP_XSLOT_XSLOTCNT_OF(x) _VALUEOF(x) + + #define MCASP_XSLOT_OF(x) _VALUEOF(x) + + #define MCASP_XSLOT_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,XSLOT,XSLOTCNT)\ + ) + + #define MCASP_XSLOT_RMK(xslotcnt) (Uint32)( \ + _PER_FMK(MCASP,XSLOT,XSLOTCNT,xslotcnt)\ + ) + + #define _MCASP_XSLOT_FGET(N,FIELD)\ + _PER_FGET(_MCASP_XSLOT##N##_ADDR,MCASP,XSLOT,##FIELD) + + #define _MCASP_XSLOT_FSET(N,FIELD,field)\ + _PER_FSET(_MCASP_XSLOT##N##_ADDR,MCASP,XSLOT,##FIELD,field) + + #define _MCASP_XSLOT_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCASP_XSLOT##N##_ADDR,MCASP,XSLOT,##FIELD,##SYM) + + #define _MCASP_XSLOT0_FGET(FIELD) _MCASP_XSLOT_FGET(0,##FIELD) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_XSLOT1_FGET(FIELD) _MCASP_XSLOT_FGET(1,##FIELD) +#endif + + #define _MCASP_XSLOT0_FSET(FIELD,f) _MCASP_XSLOT_FSET(0,##FIELD,f) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_XSLOT1_FSET(FIELD,f) _MCASP_XSLOT_FSET(1,##FIELD,f) +#endif + + #define _MCASP_XSLOT0_FSETS(FIELD,SYM) _MCASP_XSLOT_FSETS(0,##FIELD,##SYM) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_XSLOT1_FSETS(FIELD,SYM) _MCASP_XSLOT_FSETS(1,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* +* _____________________ +* | | +* | XCLKCHK | +* |___________________| +* +* XCLKCHK - Transmit Clock Check Control Register +* +* FIELDS (msb -> lsb) +* (r ) XCNT +* (rw) XMAX +* (rw) XMIN +* (rw) XFAILSW +* (rw) XPS +\******************************************************************************/ + + #define _MCASP_XCLKCHK_OFFSET 50 + + #define _MCASP_XCLKCHK0_ADDR (_MCASP_BASE_PORT0+4*_MCASP_XCLKCHK_OFFSET) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_XCLKCHK1_ADDR (_MCASP_BASE_PORT1+4*_MCASP_XCLKCHK_OFFSET) +#endif + + #define _MCASP_XCLKCHK_XCNT_MASK 0xFF000000u + #define _MCASP_XCLKCHK_XCNT_SHIFT 0x00000018u + #define MCASP_XCLKCHK_XCNT_DEFAULT 0x00000000u + #define MCASP_XCLKCHK_XCNT_OF(x) _VALUEOF(x) + + + #define _MCASP_XCLKCHK_XMAX_MASK 0x00FF0000u + #define _MCASP_XCLKCHK_XMAX_SHIFT 0x00000010u + #define MCASP_XCLKCHK_XMAX_DEFAULT 0x00000000u + #define MCASP_XCLKCHK_XMAX_OF(x) _VALUEOF(x) + + #define _MCASP_XCLKCHK_XMIN_MASK 0x0000FF00u + #define _MCASP_XCLKCHK_XMIN_SHIFT 0x00000008u + #define MCASP_XCLKCHK_XMIN_DEFAULT 0x00000000u + #define MCASP_XCLKCHK_XMIN_OF(x) _VALUEOF(x) + + #define _MCASP_XCLKCHK_XCKFAILSW_MASK 0x00000080u + #define _MCASP_XCLKCHK_XCKFAILSW_SHIFT 0x00000007u + #define MCASP_XCLKCHK_XCKFAILSW_DEFAULT 0x00000000u + #define MCASP_XCLKCHK_XCKFAILSW_OF(x) _VALUEOF(x) + #define MCASP_XCLKCHK_XCKFAILSW_DISABLE 0x00000000u + #define MCASP_XCLKCHK_XCKFAILSW_ENABLE 0x00000001u + + + #define _MCASP_XCLKCHK_XPS_MASK 0x0000000Fu + #define _MCASP_XCLKCHK_XPS_SHIFT 0x00000000u + #define MCASP_XCLKCHK_XPS_DEFAULT 0x00000000u + #define MCASP_XCLKCHK_XPS_OF(x) _VALUEOF(x) + #define MCASP_XCLKCHK_XPS_DIVBY1 0x00000000u + #define MCASP_XCLKCHK_XPS_DIVBY2 0x00000001u + #define MCASP_XCLKCHK_XPS_DIVBY4 0x00000002u + #define MCASP_XCLKCHK_XPS_DIVBY8 0x00000003u + #define MCASP_XCLKCHK_XPS_DIVBY16 0x00000004u + #define MCASP_XCLKCHK_XPS_DIVBY32 0x00000005u + #define MCASP_XCLKCHK_XPS_DIVBY64 0x00000006u + #define MCASP_XCLKCHK_XPS_DIVBY128 0x00000007u + #define MCASP_XCLKCHK_XPS_DIVBY256 0x00000008u + + + #define MCASP_XCLKCHK_OF(x) _VALUEOF(x) + + #define MCASP_XCLKCHK_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,XCLKCHK,XCNT)\ + | _PER_FDEFAULT(MCASP,XCLKCHK,XMAX)\ + | _PER_FDEFAULT(MCASP,XCLKCHK,XMIN)\ + | _PER_FDEFAULT(MCASP,XCLKCHK,XCKFAILSW)\ + | _PER_FDEFAULT(MCASP,XCLKCHK,XPS)\ + ) + + #define MCASP_XCLKCHK_RMK(xcnt, xmax, xmin, xckfailsw, xps) (Uint32)( \ + _PER_FMK(MCASP,XCLKCHK,XCNT,xcnt)\ + | _PER_FMK(MCASP,XCLKCHK,XMAX,xmax)\ + | _PER_FMK(MCASP,XCLKCHK,XMIN,xmin)\ + | _PER_FMK(MCASP,XCLKCHK,XCKFAILSW,xckfailsw)\ + | _PER_FMK(MCASP,XCLKCHK,XPS,xps)\ + ) + + #define _MCASP_XCLKCHK_FGET(N,FIELD)\ + _PER_FGET(_MCASP_XCLKCHK##N##_ADDR,MCASP,XCLKCHK,##FIELD) + + #define _MCASP_XCLKCHK_FSET(N,FIELD,field)\ + _PER_FSET(_MCASP_XCLKCHK##N##_ADDR,MCASP,XCLKCHK,##FIELD,field) + + #define _MCASP_XCLKCHK_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCASP_XCLKCHK##N##_ADDR,MCASP,XCLKCHK,##FIELD,##SYM) + + #define _MCASP_XCLKCHK0_FGET(FIELD) _MCASP_XCLKCHK_FGET(0,##FIELD) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_XCLKCHK1_FGET(FIELD) _MCASP_XCLKCHK_FGET(1,##FIELD) +#endif + + #define _MCASP_XCLKCHK0_FSET(FIELD,f) _MCASP_XCLKCHK_FSET(0,##FIELD,f) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_XCLKCHK1_FSET(FIELD,f) _MCASP_XCLKCHK_FSET(1,##FIELD,f) +#endif + + #define _MCASP_XCLKCHK0_FSETS(FIELD,SYM) _MCASP_XCLKCHK_FSETS(0,##FIELD,##SYM) +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_XCLKCHK1_FSETS(FIELD,SYM) _MCASP_XCLKCHK_FSETS(1,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* +* _____________________ +* | | +* | DITCSR | +* |_______n: 0-15_____| +* +* DITCSR - Channel Status Register File +* +* FIELDS (msb -> lsb) +* (rw) DITCSRA0 - Left (even TDM slot) +* (rw) DITCSRA1 +* (rw) DITCSRA2 +* (rw) DITCSRA3 +* (rw) DITCSRA4 +* (rw) DITCSRA5 +* (rw) DITCSRB0 - Right (odd TDM slot) +* (rw) DITCSRB1 +* (rw) DITCSRB2 +* (rw) DITCSRB3 +* (rw) DITCSRB4 +* (rw) DITCSRB5 +* +\******************************************************************************/ + + #define _MCASP_DITCSRA0_OFFSET 64 + #define _MCASP_DITCSRA1_OFFSET 65 + #define _MCASP_DITCSRA2_OFFSET 66 + #define _MCASP_DITCSRA3_OFFSET 67 + #define _MCASP_DITCSRA4_OFFSET 68 + #define _MCASP_DITCSRA5_OFFSET 69 + + #define _MCASP_DITCSRB0_OFFSET 70 + #define _MCASP_DITCSRB1_OFFSET 71 + #define _MCASP_DITCSRB2_OFFSET 72 + #define _MCASP_DITCSRB3_OFFSET 73 + #define _MCASP_DITCSRB4_OFFSET 74 + #define _MCASP_DITCSRB5_OFFSET 75 + +/* registers for MCASP0 */ + #define _MCASP_DITCSR0_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_DITCSRA0_OFFSET) + #define _MCASP_DITCSRA00_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_DITCSRA0_OFFSET) + #define _MCASP_DITCSRA10_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_DITCSRA1_OFFSET) + #define _MCASP_DITCSRA20_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_DITCSRA2_OFFSET) + #define _MCASP_DITCSRA30_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_DITCSRA3_OFFSET) + #define _MCASP_DITCSRA40_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_DITCSRA4_OFFSET) + #define _MCASP_DITCSRA50_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_DITCSRA5_OFFSET) + + #define _MCASP_DITCSRB00_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_DITCSRB0_OFFSET) + #define _MCASP_DITCSRB10_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_DITCSRB1_OFFSET) + #define _MCASP_DITCSRB20_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_DITCSRB2_OFFSET) + #define _MCASP_DITCSRB30_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_DITCSRB3_OFFSET) + #define _MCASP_DITCSRB40_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_DITCSRB4_OFFSET) + #define _MCASP_DITCSRB50_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_DITCSRB5_OFFSET) + +/* registers for MCASP1 */ +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_DITCSR1_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_DITCSRA0_OFFSET) + #define _MCASP_DITCSRA01_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_DITCSRA0_OFFSET) + #define _MCASP_DITCSRA11_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_DITCSRA1_OFFSET) + #define _MCASP_DITCSRA21_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_DITCSRA2_OFFSET) + #define _MCASP_DITCSRA31_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_DITCSRA3_OFFSET) + #define _MCASP_DITCSRA41_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_DITCSRA4_OFFSET) + #define _MCASP_DITCSRA51_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_DITCSRA5_OFFSET) + + #define _MCASP_DITCSRB01_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_DITCSRB0_OFFSET) + #define _MCASP_DITCSRB11_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_DITCSRB1_OFFSET) + #define _MCASP_DITCSRB21_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_DITCSRB2_OFFSET) + #define _MCASP_DITCSRB31_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_DITCSRB3_OFFSET) + #define _MCASP_DITCSRB41_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_DITCSRB4_OFFSET) + #define _MCASP_DITCSRB51_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_DITCSRB5_OFFSET) +#endif + + +/******************************************************************************\ +* +* _____________________ +* | | +* | DITUDR | +* |_______n: 0-15_____| +* +* DITUDR - User Data Register File +* +* FIELDS (msb -> lsb) +* (rw) DITUDRA0 - Left (even TDM slot) +* (rw) DITUDRA1 +* (rw) DITUDRA2 +* (rw) DITUDRA3 +* (rw) DITUDRA4 +* (rw) DITUDRA5 +* (rw) DITUDRB0 - Right (odd TDM slot) +* (rw) DITUDRB1 +* (rw) DITUDRB2 +* (rw) DITUDRB3 +* (rw) DITUDRB4 +* (rw) DITUDRB5 +* +\******************************************************************************/ + + #define _MCASP_DITUDRA0_OFFSET 76 + #define _MCASP_DITUDRA1_OFFSET 77 + #define _MCASP_DITUDRA2_OFFSET 78 + #define _MCASP_DITUDRA3_OFFSET 79 + #define _MCASP_DITUDRA4_OFFSET 80 + #define _MCASP_DITUDRA5_OFFSET 81 + + #define _MCASP_DITUDRB0_OFFSET 82 + #define _MCASP_DITUDRB1_OFFSET 83 + #define _MCASP_DITUDRB2_OFFSET 84 + #define _MCASP_DITUDRB3_OFFSET 85 + #define _MCASP_DITUDRB4_OFFSET 86 + #define _MCASP_DITUDRB5_OFFSET 87 + + #define _MCASP_DITUDR0_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_DITUDRA0_OFFSET) + /* registers for MCASP0 */ + #define _MCASP_DITUDRA00_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_DITUDRA0_OFFSET) + #define _MCASP_DITUDRA10_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_DITUDRA1_OFFSET) + #define _MCASP_DITUDRA20_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_DITUDRA2_OFFSET) + #define _MCASP_DITUDRA30_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_DITUDRA3_OFFSET) + #define _MCASP_DITUDRA40_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_DITUDRA4_OFFSET) + #define _MCASP_DITUDRA50_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_DITUDRA5_OFFSET) + + #define _MCASP_DITUDRB00_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_DITUDRB0_OFFSET) + #define _MCASP_DITUDRB10_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_DITUDRB1_OFFSET) + #define _MCASP_DITUDRB20_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_DITUDRB2_OFFSET) + #define _MCASP_DITUDRB30_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_DITUDRB3_OFFSET) + #define _MCASP_DITUDRB40_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_DITUDRB4_OFFSET) + #define _MCASP_DITUDRB50_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_DITUDRB5_OFFSET) + +/* registers for MCASP1 */ +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_DITUDR1_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_DITUDRA0_OFFSET) + #define _MCASP_DITUDRA01_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_DITUDRA0_OFFSET) + #define _MCASP_DITUDRA11_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_DITUDRA1_OFFSET) + #define _MCASP_DITUDRA21_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_DITUDRA2_OFFSET) + #define _MCASP_DITUDRA31_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_DITUDRA3_OFFSET) + #define _MCASP_DITUDRA41_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_DITUDRA4_OFFSET) + #define _MCASP_DITUDRA51_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_DITUDRA5_OFFSET) + #define _MCASP_DITUDRB01_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_DITUDRB0_OFFSET) + #define _MCASP_DITUDRB11_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_DITUDRB1_OFFSET) + #define _MCASP_DITUDRB21_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_DITUDRB2_OFFSET) + #define _MCASP_DITUDRB31_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_DITUDRB3_OFFSET) + #define _MCASP_DITUDRB41_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_DITUDRB4_OFFSET) + #define _MCASP_DITUDRB51_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_DITUDRB5_OFFSET) +#endif + + +/******************************************************************************\ +* +* _____________________ +* | | +* | SRCTL | +* |_______n: 0-15_____| +* +* SRCTL - Serializer Control Registers +* +* FIELDS (msb -> lsb) +* (r ) RRDY +* (r ) XRDY +* (rw) DISMOD +* (rw) SRMOD +* +\******************************************************************************/ + + #define _MCASP_SRCTL0_OFFSET 96 + #define _MCASP_SRCTL1_OFFSET 97 + #define _MCASP_SRCTL2_OFFSET 98 + #define _MCASP_SRCTL3_OFFSET 99 + /* Fields for _MCASP_CHANNEL_CNT == 4 end here*/ + +#if (_MCASP_CHANNEL_CNT > 4) + #define _MCASP_SRCTL4_OFFSET 100 + #define _MCASP_SRCTL5_OFFSET 101 +#endif /* _MCASP_CHANNEL_CNT == 6 */ + +#if (_MCASP_CHANNEL_CNT > 6) /* For channel count 8 and 16 */ + #define _MCASP_SRCTL6_OFFSET 102 + #define _MCASP_SRCTL7_OFFSET 103 +#endif /* _MCASP_CHANNEL_CNT == 8 */ + +#if (_MCASP_CHANNEL_CNT == 16) + #define _MCASP_SRCTL8_OFFSET 104 + #define _MCASP_SRCTL9_OFFSET 105 + #define _MCASP_SRCTL10_OFFSET 106 + #define _MCASP_SRCTL11_OFFSET 107 + #define _MCASP_SRCTL12_OFFSET 108 + #define _MCASP_SRCTL13_OFFSET 109 + #define _MCASP_SRCTL14_OFFSET 110 + #define _MCASP_SRCTL15_OFFSET 111 +#endif /* _MCASP_CHANNEL_CNT == 16 */ + + #define _MCASP_SRCTL0_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_SRCTL0_OFFSET) + /* registers for MCASP0 */ + + #define _MCASP_SRCTL00_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_SRCTL0_OFFSET) + #define _MCASP_SRCTL10_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_SRCTL1_OFFSET) + #define _MCASP_SRCTL20_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_SRCTL2_OFFSET) + #define _MCASP_SRCTL30_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_SRCTL3_OFFSET) + /* Fields for _MCASP_CHANNEL_CNT == 4 end here*/ + +#if (_MCASP_CHANNEL_CNT > 4) + #define _MCASP_SRCTL40_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_SRCTL4_OFFSET) + #define _MCASP_SRCTL50_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_SRCTL5_OFFSET) +#endif /* _MCASP_CHANNEL_CNT == 6 */ + +#if (_MCASP_CHANNEL_CNT > 6) /* For channel count 8 and 16 */ + #define _MCASP_SRCTL60_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_SRCTL6_OFFSET) + #define _MCASP_SRCTL70_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_SRCTL7_OFFSET) +#endif /* _MCASP_CHANNEL_CNT == 8 */ + +#if (_MCASP_CHANNEL_CNT == 16) + #define _MCASP_SRCTL80_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_SRCTL8_OFFSET) + #define _MCASP_SRCTL90_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_SRCTL9_OFFSET) + #define _MCASP_SRCTL100_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_SRCTL10_OFFSET) + #define _MCASP_SRCTL110_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_SRCTL11_OFFSET) + #define _MCASP_SRCTL120_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_SRCTL12_OFFSET) + #define _MCASP_SRCTL130_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_SRCTL13_OFFSET) + #define _MCASP_SRCTL140_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_SRCTL14_OFFSET) + #define _MCASP_SRCTL150_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_SRCTL15_OFFSET) +#endif /* _MCASP_CHANNEL_CNT == 16 */ + +/* registers for MCASP1 */ +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_SRCTL1_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_SRCTL0_OFFSET) + #define _MCASP_SRCTL01_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_SRCTL0_OFFSET) + #define _MCASP_SRCTL11_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_SRCTL1_OFFSET) + #define _MCASP_SRCTL21_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_SRCTL2_OFFSET) + #define _MCASP_SRCTL31_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_SRCTL3_OFFSET) + /* Fields for _MCASP_CHANNEL_CNT == 4 end here*/ + + #if (_MCASP_CHANNEL_CNT > 4) + #define _MCASP_SRCTL41_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_SRCTL4_OFFSET) + #define _MCASP_SRCTL51_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_SRCTL5_OFFSET) + #endif /* _MCASP_CHANNEL_CNT == 6 */ + + #if (_MCASP_CHANNEL_CNT > 6) /* For channel count 8 and 16 */ + #define _MCASP_SRCTL61_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_SRCTL6_OFFSET) + #define _MCASP_SRCTL71_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_SRCTL7_OFFSET) + #endif /* _MCASP_CHANNEL_CNT == 8 */ + + #if (_MCASP_CHANNEL_CNT == 16) + #define _MCASP_SRCTL81_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_SRCTL8_OFFSET) + #define _MCASP_SRCTL91_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_SRCTL9_OFFSET) + #define _MCASP_SRCTL101_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_SRCTL10_OFFSET) + #define _MCASP_SRCTL111_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_SRCTL11_OFFSET) + #define _MCASP_SRCTL121_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_SRCTL12_OFFSET) + #define _MCASP_SRCTL131_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_SRCTL13_OFFSET) + #define _MCASP_SRCTL141_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_SRCTL14_OFFSET) + #define _MCASP_SRCTL151_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_SRCTL15_OFFSET) + #endif /* _MCASP_CHANNEL_CNT == 16 */ +#endif + + #define _MCASP_SRCTL_RRDY_MASK 0x00000020u + #define _MCASP_SRCTL_RRDY_SHIFT 0x00000005u + #define MCASP_SRCTL_RRDY_DEFAULT 0x00000000u + #define MCASP_SRCTL_RRDY_OF(x) _VALUEOF(x) + + #define _MCASP_SRCTL_XRDY_MASK 0x00000010u + #define _MCASP_SRCTL_XRDY_SHIFT 0x00000004u + #define MCASP_SRCTL_XRDY_DEFAULT 0x00000000u + #define MCASP_SRCTL_XRDY_OF(x) _VALUEOF(x) + + + #define _MCASP_SRCTL_DISMOD_MASK 0x0000000Cu + #define _MCASP_SRCTL_DISMOD_SHIFT 0x00000002u + #define MCASP_SRCTL_DISMOD_DEFAULT 0x00000000u + #define MCASP_SRCTL_DISMOD_OF(x) _VALUEOF(x) + #define MCASP_SRCTL_DISMOD_LOW 0x00000002u + #define MCASP_SRCTL_DISMOD_HIGH 0x00000003u + #define MCASP_SRCTL_DISMOD_3STATE 0x00000000u + + + #define _MCASP_SRCTL_SRMOD_MASK 0x00000003u + #define _MCASP_SRCTL_SRMOD_SHIFT 0x00000000u + #define MCASP_SRCTL_SRMOD_DEFAULT 0x00000000u + #define MCASP_SRCTL_SRMOD_OF(x) _VALUEOF(x) + #define MCASP_SRCTL_SRMOD_INACTIVE 0x00000000u + #define MCASP_SRCTL_SRMOD_XMT 0x00000001u + #define MCASP_SRCTL_SRMOD_RCV 0x00000002u + + #define MCASP_SRCTL_OF(x) _VALUEOF(x) + + #define MCASP_SRCTL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(MCASP,SRCTL,RRDY)\ +| _PER_FDEFAULT(MCASP,SRCTL,XRDY)\ +| _PER_FDEFAULT(MCASP,SRCTL,DISMOD)\ +| _PER_FDEFAULT(MCASP,SRCTL,SRMOD)\ + ) + + #define MCASP_SRCTL_RMK(dismod, srmod) (Uint32)( \ + _PER_FMK(MCASP,SRCTL,DISMOD,dismod)\ + | _PER_FMK(MCASP,SRCTL,SRMOD,srmod)\ + ) + + + #define _MCASP_SRCTL_FGET(M,N,FIELD)\ + _PER_FGET(_MCASP_SRCTL##M##N##_ADDR,MCASP,SRCTL,##FIELD) + + #define _MCASP_SRCTL_FSET(M,N,FIELD,f)\ + _PER_FSET(_MCASP_SRCTL##M##N##_ADDR,MCASP,SRCTL,##FIELD,f) + + #define _MCASP_SRCTL_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCASP_SRCTL##M##N##_ADDR,MCASP,SRCTL,##FIELD,##SYM) + + #define _MCASP_SRCTL00_FGET(FIELD) _MCASP_SRCTL_FGET(0,0,##FIELD) + #define _MCASP_SRCTL10_FGET(FIELD) _MCASP_SRCTL_FGET(1,0,##FIELD) + #define _MCASP_SRCTL20_FGET(FIELD) _MCASP_SRCTL_FGET(2,0,##FIELD) + #define _MCASP_SRCTL30_FGET(FIELD) _MCASP_SRCTL_FGET(3,0,##FIELD) + /* Fields for _MCASP_CHANNEL_CNT == 4 end here*/ + +#if (_MCASP_CHANNEL_CNT > 4) + #define _MCASP_SRCTL40_FGET(FIELD) _MCASP_SRCTL_FGET(4,0,##FIELD) + #define _MCASP_SRCTL50_FGET(FIELD) _MCASP_SRCTL_FGET(5,0,##FIELD) +#endif /* _MCASP_CHANNEL_CNT == 6 */ + +#if (_MCASP_CHANNEL_CNT > 6) /* For channel count 8 and 16 */ + #define _MCASP_SRCTL60_FGET(FIELD) _MCASP_SRCTL_FGET(6,0,##FIELD) + #define _MCASP_SRCTL70_FGET(FIELD) _MCASP_SRCTL_FGET(7,0,##FIELD) +#endif /* _MCASP_CHANNEL_CNT == 8 */ + +#if (_MCASP_CHANNEL_CNT == 16) + #define _MCASP_SRCTL80_FGET(FIELD) _MCASP_SRCTL_FGET(8,0,##FIELD) + #define _MCASP_SRCTL90_FGET(FIELD) _MCASP_SRCTL_FGET(9,0,##FIELD) + #define _MCASP_SRCTL100_FGET(FIELD) _MCASP_SRCTL_FGET(10,0,##FIELD) + #define _MCASP_SRCTL110_FGET(FIELD) _MCASP_SRCTL_FGET(11,0,##FIELD) + #define _MCASP_SRCTL120_FGET(FIELD) _MCASP_SRCTL_FGET(12,0,##FIELD) + #define _MCASP_SRCTL130_FGET(FIELD) _MCASP_SRCTL_FGET(13,0,##FIELD) + #define _MCASP_SRCTL140_FGET(FIELD) _MCASP_SRCTL_FGET(14,0,##FIELD) + #define _MCASP_SRCTL150_FGET(FIELD) _MCASP_SRCTL_FGET(15,0,##FIELD) +#endif /* _MCASP_CHANNEL_CNT == 16 */ + + #define _MCASP_SRCTL00_FSET(FIELD,f) _MCASP_SRCTL_FSET(0,0,##FIELD,f) + #define _MCASP_SRCTL10_FSET(FIELD,f) _MCASP_SRCTL_FSET(1,0,##FIELD,f) + #define _MCASP_SRCTL20_FSET(FIELD,f) _MCASP_SRCTL_FSET(2,0,##FIELD,f) + #define _MCASP_SRCTL30_FSET(FIELD,f) _MCASP_SRCTL_FSET(3,0,##FIELD,f) + /* Fields for _MCASP_CHANNEL_CNT == 4 end here*/ + +#if (_MCASP_CHANNEL_CNT > 4) + #define _MCASP_SRCTL40_FSET(FIELD,f) _MCASP_SRCTL_FSET(4,0,##FIELD,f) + #define _MCASP_SRCTL50_FSET(FIELD,f) _MCASP_SRCTL_FSET(5,0,##FIELD,f) +#endif /* _MCASP_CHANNEL_CNT == 6 */ + +#if (_MCASP_CHANNEL_CNT > 6) /* For channel count 8 and 16 */ + #define _MCASP_SRCTL60_FSET(FIELD,f) _MCASP_SRCTL_FSET(6,0,##FIELD,f) + #define _MCASP_SRCTL70_FSET(FIELD,f) _MCASP_SRCTL_FSET(7,0,##FIELD,f) +#endif /* _MCASP_CHANNEL_CNT == 8 */ + +#if (_MCASP_CHANNEL_CNT == 16) + #define _MCASP_SRCTL80_FSET(FIELD,f) _MCASP_SRCTL_FSET(8,0,##FIELD,f) + #define _MCASP_SRCTL90_FSET(FIELD,f) _MCASP_SRCTL_FSET(9,0,##FIELD,f) + #define _MCASP_SRCTL100_FSET(FIELD,f) _MCASP_SRCTL_FSET(10,0,##FIELD,f) + #define _MCASP_SRCTL110_FSET(FIELD,f) _MCASP_SRCTL_FSET(11,0,##FIELD,f) + #define _MCASP_SRCTL120_FSET(FIELD,f) _MCASP_SRCTL_FSET(12,0,##FIELD,f) + #define _MCASP_SRCTL130_FSET(FIELD,f) _MCASP_SRCTL_FSET(13,0,##FIELD,f) + #define _MCASP_SRCTL140_FSET(FIELD,f) _MCASP_SRCTL_FSET(14,0,##FIELD,f) + #define _MCASP_SRCTL150_FSET(FIELD,f) _MCASP_SRCTL_FSET(15,0,##FIELD,f) +#endif /* _MCASP_CHANNEL_CNT == 16 */ + + #define _MCASP_SRCTL00_FSETS(FIELD,SYM) _MCASP_SRCTL_FSETS(0,0,##FIELD,##SYM) + #define _MCASP_SRCTL10_FSETS(FIELD,SYM) _MCASP_SRCTL_FSETS(1,0,##FIELD,##SYM) + #define _MCASP_SRCTL20_FSETS(FIELD,SYM) _MCASP_SRCTL_FSETS(2,0,##FIELD,##SYM) + #define _MCASP_SRCTL30_FSETS(FIELD,SYM) _MCASP_SRCTL_FSETS(3,0,##FIELD,##SYM) + /* Fields for _MCASP_CHANNEL_CNT == 4 end here*/ + +#if (_MCASP_CHANNEL_CNT > 4) + #define _MCASP_SRCTL40_FSETS(FIELD,SYM) _MCASP_SRCTL_FSETS(4,0,##FIELD,##SYM) + #define _MCASP_SRCTL50_FSETS(FIELD,SYM) _MCASP_SRCTL_FSETS(5,0,##FIELD,##SYM) +#endif /* _MCASP_CHANNEL_CNT == 6 */ + +#if (_MCASP_CHANNEL_CNT > 6) /* For channel count 8 and 16 */ + #define _MCASP_SRCTL60_FSETS(FIELD,SYM) _MCASP_SRCTL_FSETS(6,0,##FIELD,##SYM) + #define _MCASP_SRCTL70_FSETS(FIELD,SYM) _MCASP_SRCTL_FSETS(7,0,##FIELD,##SYM) +#endif /* _MCASP_CHANNEL_CNT == 8 */ + +#if (_MCASP_CHANNEL_CNT == 16) + #define _MCASP_SRCTL80_FSETS(FIELD,SYM) _MCASP_SRCTL_FSETS(8,0,##FIELD,##SYM) + #define _MCASP_SRCTL90_FSETS(FIELD,SYM) _MCASP_SRCTL_FSETS(9,0,##FIELD,##SYM) + #define _MCASP_SRCTL100_FSETS(FIELD,SYM) _MCASP_SRCTL_FSETS(10,0,##FIELD,##SYM) + #define _MCASP_SRCTL110_FSETS(FIELD,SYM) _MCASP_SRCTL_FSETS(11,0,##FIELD,##SYM) + #define _MCASP_SRCTL120_FSETS(FIELD,SYM) _MCASP_SRCTL_FSETS(12,0,##FIELD,##SYM) + #define _MCASP_SRCTL130_FSETS(FIELD,SYM) _MCASP_SRCTL_FSETS(13,0,##FIELD,##SYM) + #define _MCASP_SRCTL140_FSETS(FIELD,SYM) _MCASP_SRCTL_FSETS(14,0,##FIELD,##SYM) + #define _MCASP_SRCTL150_FSETS(FIELD,SYM) _MCASP_SRCTL_FSETS(15,0,##FIELD,##SYM) +#endif /* _MCASP_CHANNEL_CNT == 16 */ + +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_SRCTL01_FGET(FIELD) _MCASP_SRCTL_FGET(0,1,##FIELD) + #define _MCASP_SRCTL11_FGET(FIELD) _MCASP_SRCTL_FGET(1,1,##FIELD) + #define _MCASP_SRCTL21_FGET(FIELD) _MCASP_SRCTL_FGET(2,1,##FIELD) + #define _MCASP_SRCTL31_FGET(FIELD) _MCASP_SRCTL_FGET(3,1,##FIELD) + /* Fields for _MCASP_CHANNEL_CNT == 4 end here*/ + + #if (_MCASP_CHANNEL_CNT > 4) + #define _MCASP_SRCTL41_FGET(FIELD) _MCASP_SRCTL_FGET(4,1,##FIELD) + #define _MCASP_SRCTL51_FGET(FIELD) _MCASP_SRCTL_FGET(5,1,##FIELD) + #endif /* _MCASP_CHANNEL_CNT == 6 */ + + #if (_MCASP_CHANNEL_CNT > 6) /* For channel count 8 and 16 */ + #define _MCASP_SRCTL61_FGET(FIELD) _MCASP_SRCTL_FGET(6,1,##FIELD) + #define _MCASP_SRCTL71_FGET(FIELD) _MCASP_SRCTL_FGET(7,1,##FIELD) + #endif /* _MCASP_CHANNEL_CNT == 8 */ + + #if (_MCASP_CHANNEL_CNT == 16) + #define _MCASP_SRCTL81_FGET(FIELD) _MCASP_SRCTL_FGET(8,1,##FIELD) + #define _MCASP_SRCTL91_FGET(FIELD) _MCASP_SRCTL_FGET(9,1,##FIELD) + #define _MCASP_SRCTL101_FGET(FIELD) _MCASP_SRCTL_FGET(10,1,##FIELD) + #define _MCASP_SRCTL111_FGET(FIELD) _MCASP_SRCTL_FGET(11,1,##FIELD) + #define _MCASP_SRCTL121_FGET(FIELD) _MCASP_SRCTL_FGET(12,1,##FIELD) + #define _MCASP_SRCTL131_FGET(FIELD) _MCASP_SRCTL_FGET(13,1,##FIELD) + #define _MCASP_SRCTL141_FGET(FIELD) _MCASP_SRCTL_FGET(14,1,##FIELD) + #define _MCASP_SRCTL151_FGET(FIELD) _MCASP_SRCTL_FGET(15,1,##FIELD) + #endif /* _MCASP_CHANNEL_CNT == 16 */ + + #define _MCASP_SRCTL01_FSET(FIELD,f) _MCASP_SRCTL_FSET(0,1,##FIELD,f) + #define _MCASP_SRCTL11_FSET(FIELD,f) _MCASP_SRCTL_FSET(1,1,##FIELD,f) + #define _MCASP_SRCTL21_FSET(FIELD,f) _MCASP_SRCTL_FSET(2,1,##FIELD,f) + #define _MCASP_SRCTL31_FSET(FIELD,f) _MCASP_SRCTL_FSET(3,1,##FIELD,f) + /* Fields for _MCASP_CHANNEL_CNT == 4 end here*/ + + #if (_MCASP_CHANNEL_CNT > 4) + #define _MCASP_SRCTL41_FSET(FIELD,f) _MCASP_SRCTL_FSET(4,1,##FIELD,f) + #define _MCASP_SRCTL51_FSET(FIELD,f) _MCASP_SRCTL_FSET(5,1,##FIELD,f) + #endif /* _MCASP_CHANNEL_CNT == 6 */ + + #if (_MCASP_CHANNEL_CNT > 6) /* For channel count 8 and 16 */ + #define _MCASP_SRCTL61_FSET(FIELD,f) _MCASP_SRCTL_FSET(6,1,##FIELD,f) + #define _MCASP_SRCTL71_FSET(FIELD,f) _MCASP_SRCTL_FSET(7,1,##FIELD,f) + #endif /* _MCASP_CHANNEL_CNT == 8 */ + + #if (_MCASP_CHANNEL_CNT == 16) + #define _MCASP_SRCTL81_FSET(FIELD,f) _MCASP_SRCTL_FSET(8,1,##FIELD,f) + #define _MCASP_SRCTL91_FSET(FIELD,f) _MCASP_SRCTL_FSET(9,1,##FIELD,f) + #define _MCASP_SRCTL101_FSET(FIELD,f) _MCASP_SRCTL_FSET(10,1,##FIELD,f) + #define _MCASP_SRCTL111_FSET(FIELD,f) _MCASP_SRCTL_FSET(11,1,##FIELD,f) + #define _MCASP_SRCTL121_FSET(FIELD,f) _MCASP_SRCTL_FSET(12,1,##FIELD,f) + #define _MCASP_SRCTL131_FSET(FIELD,f) _MCASP_SRCTL_FSET(13,1,##FIELD,f) + #define _MCASP_SRCTL141_FSET(FIELD,f) _MCASP_SRCTL_FSET(14,1,##FIELD,f) + #define _MCASP_SRCTL151_FSET(FIELD,f) _MCASP_SRCTL_FSET(15,1,##FIELD,f) + #endif /* _MCASP_CHANNEL_CNT == 16 */ + + #define _MCASP_SRCTL01_FSETS(FIELD,SYM) _MCASP_SRCTL_FSETS(0,1,##FIELD,##SYM) + #define _MCASP_SRCTL11_FSETS(FIELD,SYM) _MCASP_SRCTL_FSETS(1,1,##FIELD,##SYM) + #define _MCASP_SRCTL21_FSETS(FIELD,SYM) _MCASP_SRCTL_FSETS(2,1,##FIELD,##SYM) + #define _MCASP_SRCTL31_FSETS(FIELD,SYM) _MCASP_SRCTL_FSETS(3,1,##FIELD,##SYM) + /* Fields for _MCASP_CHANNEL_CNT == 4 end here*/ + + #if (_MCASP_CHANNEL_CNT > 4) + #define _MCASP_SRCTL41_FSETS(FIELD,SYM) _MCASP_SRCTL_FSETS(4,1,##FIELD,##SYM) + #define _MCASP_SRCTL51_FSETS(FIELD,SYM) _MCASP_SRCTL_FSETS(5,1,##FIELD,##SYM) + #endif /* _MCASP_CHANNEL_CNT == 6 */ + + #if (_MCASP_CHANNEL_CNT > 6) /* For channel count 8 and 16 */ + #define _MCASP_SRCTL61_FSETS(FIELD,SYM) _MCASP_SRCTL_FSETS(6,1,##FIELD,##SYM) + #define _MCASP_SRCTL71_FSETS(FIELD,SYM) _MCASP_SRCTL_FSETS(7,1,##FIELD,##SYM) + #endif /* _MCASP_CHANNEL_CNT == 8 */ + + #if (_MCASP_CHANNEL_CNT == 16) + #define _MCASP_SRCTL81_FSETS(FIELD,SYM) _MCASP_SRCTL_FSETS(8,1,##FIELD,##SYM) + #define _MCASP_SRCTL91_FSETS(FIELD,SYM) _MCASP_SRCTL_FSETS(9,1,##FIELD,##SYM) + #define _MCASP_SRCTL101_FSETS(FIELD,SYM) _MCASP_SRCTL_FSETS(10,1,##FIELD,##SYM) + #define _MCASP_SRCTL111_FSETS(FIELD,SYM) _MCASP_SRCTL_FSETS(11,1,##FIELD,##SYM) + #define _MCASP_SRCTL121_FSETS(FIELD,SYM) _MCASP_SRCTL_FSETS(12,1,##FIELD,##SYM) + #define _MCASP_SRCTL131_FSETS(FIELD,SYM) _MCASP_SRCTL_FSETS(13,1,##FIELD,##SYM) + #define _MCASP_SRCTL141_FSETS(FIELD,SYM) _MCASP_SRCTL_FSETS(14,1,##FIELD,##SYM) + #define _MCASP_SRCTL151_FSETS(FIELD,SYM) _MCASP_SRCTL_FSETS(15,1,##FIELD,##SYM) + #endif /* _MCASP_CHANNEL_CNT == 16 */ +#endif + + +/******************************************************************************\ +* +* _____________________ +* | | +* | XBUF | +* |_______n: 0-15_____| +* +* XBUF - Transmit Buffer for Serializers +* +* +\******************************************************************************/ + + #define _MCASP_XBUF0_ADDR 0x3C000000u +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_XBUF1_ADDR 0x3C100000u +#endif + + #define _MCASP_XBUF0_OFFSET 128 + #define _MCASP_XBUF1_OFFSET 129 + #define _MCASP_XBUF2_OFFSET 130 + #define _MCASP_XBUF3_OFFSET 131 + /* Fields for _MCASP_CHANNEL_CNT == 4 end here*/ + +#if (_MCASP_CHANNEL_CNT > 4) + #define _MCASP_XBUF4_OFFSET 132 + #define _MCASP_XBUF5_OFFSET 133 +#endif /* _MCASP_CHANNEL_CNT == 6 */ + +#if (_MCASP_CHANNEL_CNT > 6) /* For channel count 8 and 16 */ + #define _MCASP_XBUF6_OFFSET 134 + #define _MCASP_XBUF7_OFFSET 135 +#endif /* _MCASP_CHANNEL_CNT == 8 */ + +#if (_MCASP_CHANNEL_CNT == 16) + #define _MCASP_XBUF8_OFFSET 136 + #define _MCASP_XBUF9_OFFSET 137 + #define _MCASP_XBUF10_OFFSET 138 + #define _MCASP_XBUF11_OFFSET 139 + #define _MCASP_XBUF12_OFFSET 140 + #define _MCASP_XBUF13_OFFSET 141 + #define _MCASP_XBUF14_OFFSET 142 + #define _MCASP_XBUF15_OFFSET 143 +#endif /* _MCASP_CHANNEL_CNT == 16 */ + + + #define _MCASP_XBUF00_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_XBUF0_OFFSET) + #define _MCASP_XBUF10_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_XBUF1_OFFSET) + #define _MCASP_XBUF20_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_XBUF2_OFFSET) + #define _MCASP_XBUF30_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_XBUF3_OFFSET) + /* Fields for _MCASP_CHANNEL_CNT == 4 end here*/ + +#if (_MCASP_CHANNEL_CNT > 4) + #define _MCASP_XBUF40_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_XBUF4_OFFSET) + #define _MCASP_XBUF50_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_XBUF5_OFFSET) +#endif /* _MCASP_CHANNEL_CNT == 6 */ + +#if (_MCASP_CHANNEL_CNT > 6) /* For channel count 8 and 16 */ + #define _MCASP_XBUF60_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_XBUF6_OFFSET) + #define _MCASP_XBUF70_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_XBUF7_OFFSET) +#endif /* _MCASP_CHANNEL_CNT == 8 */ + +#if (_MCASP_CHANNEL_CNT == 16) + #define _MCASP_XBUF80_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_XBUF8_OFFSET) + #define _MCASP_XBUF90_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_XBUF9_OFFSET) + #define _MCASP_XBUF100_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_XBUF10_OFFSET) + #define _MCASP_XBUF110_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_XBUF11_OFFSET) + #define _MCASP_XBUF120_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_XBUF12_OFFSET) + #define _MCASP_XBUF130_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_XBUF13_OFFSET) + #define _MCASP_XBUF140_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_XBUF14_OFFSET) + #define _MCASP_XBUF150_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_XBUF15_OFFSET) +#endif /* _MCASP_CHANNEL_CNT == 16 */ + +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_XBUF01_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_XBUF0_OFFSET) + #define _MCASP_XBUF11_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_XBUF1_OFFSET) + #define _MCASP_XBUF21_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_XBUF2_OFFSET) + #define _MCASP_XBUF31_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_XBUF3_OFFSET) + /* Fields for _MCASP_CHANNEL_CNT == 4 end here*/ + + #if (_MCASP_CHANNEL_CNT > 4) + #define _MCASP_XBUF41_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_XBUF4_OFFSET) + #define _MCASP_XBUF51_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_XBUF5_OFFSET) + #endif /* _MCASP_CHANNEL_CNT == 6 */ + + #if (_MCASP_CHANNEL_CNT > 6) /* For channel count 8 and 16 */ + #define _MCASP_XBUF61_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_XBUF6_OFFSET) + #define _MCASP_XBUF71_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_XBUF7_OFFSET) + #endif /* _MCASP_CHANNEL_CNT == 8 */ + + #if (_MCASP_CHANNEL_CNT == 16) + #define _MCASP_XBUF81_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_XBUF8_OFFSET) + #define _MCASP_XBUF91_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_XBUF9_OFFSET) + #define _MCASP_XBUF101_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_XBUF10_OFFSET) + #define _MCASP_XBUF111_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_XBUF11_OFFSET) + #define _MCASP_XBUF121_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_XBUF12_OFFSET) + #define _MCASP_XBUF131_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_XBUF13_OFFSET) + #define _MCASP_XBUF141_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_XBUF14_OFFSET) + #define _MCASP_XBUF151_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_XBUF15_OFFSET) + #endif /* _MCASP_CHANNEL_CNT == 16 */ +#endif + + +/******************************************************************************\ +* +* _____________________ +* | | +* | RBUF | +* |_______n: 0-15_____| +* +* RBUF - Receive Buffer for Serializers +* +* +\******************************************************************************/ + + #define _MCASP_RBUF0_ADDR 0x3C000000u +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_RBUF1_ADDR 0x3C100000u +#endif + + + #define _MCASP_RBUF0_OFFSET 160 + #define _MCASP_RBUF1_OFFSET 161 + #define _MCASP_RBUF2_OFFSET 162 + #define _MCASP_RBUF3_OFFSET 163 + /* Fields for _MCASP_CHANNEL_CNT == 4 end here*/ + +#if (_MCASP_CHANNEL_CNT > 4) + #define _MCASP_RBUF4_OFFSET 164 + #define _MCASP_RBUF5_OFFSET 165 +#endif /* _MCASP_CHANNEL_CNT == 6 */ + +#if (_MCASP_CHANNEL_CNT > 6) /* For channel count 8 and 16 */ + #define _MCASP_RBUF6_OFFSET 166 + #define _MCASP_RBUF7_OFFSET 167 +#endif /* _MCASP_CHANNEL_CNT == 8 */ + +#if (_MCASP_CHANNEL_CNT == 16) + #define _MCASP_RBUF8_OFFSET 168 + #define _MCASP_RBUF9_OFFSET 169 + #define _MCASP_RBUF10_OFFSET 170 + #define _MCASP_RBUF11_OFFSET 171 + #define _MCASP_RBUF12_OFFSET 172 + #define _MCASP_RBUF13_OFFSET 173 + #define _MCASP_RBUF14_OFFSET 174 + #define _MCASP_RBUF15_OFFSET 175 +#endif /* _MCASP_CHANNEL_CNT == 16 */ + + #define _MCASP_RBUF00_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_RBUF0_OFFSET) + #define _MCASP_RBUF10_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_RBUF1_OFFSET) + #define _MCASP_RBUF20_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_RBUF2_OFFSET) + #define _MCASP_RBUF30_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_RBUF3_OFFSET) + /* Fields for _MCASP_CHANNEL_CNT == 4 end here*/ + +#if (_MCASP_CHANNEL_CNT > 4) + #define _MCASP_RBUF40_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_RBUF4_OFFSET) + #define _MCASP_RBUF50_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_RBUF5_OFFSET) +#endif /* _MCASP_CHANNEL_CNT == 6 */ + +#if (_MCASP_CHANNEL_CNT > 6) /* For channel count 8 and 16 */ + #define _MCASP_RBUF60_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_RBUF6_OFFSET) + #define _MCASP_RBUF70_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_RBUF7_OFFSET) +#endif /* _MCASP_CHANNEL_CNT == 8 */ + +#if (_MCASP_CHANNEL_CNT == 16) + #define _MCASP_RBUF80_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_RBUF8_OFFSET) + #define _MCASP_RBUF90_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_RBUF9_OFFSET) + #define _MCASP_RBUF100_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_RBUF10_OFFSET) + #define _MCASP_RBUF110_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_RBUF11_OFFSET) + #define _MCASP_RBUF120_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_RBUF12_OFFSET) + #define _MCASP_RBUF130_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_RBUF13_OFFSET) + #define _MCASP_RBUF140_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_RBUF14_OFFSET) + #define _MCASP_RBUF150_ADDR (_MCASP_BASE_PORT0 + 4*_MCASP_RBUF15_OFFSET) +#endif /* _MCASP_CHANNEL_CNT == 16 */ + +#if (_MCASP_PORT_CNT > 1) + #define _MCASP_RBUF01_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_RBUF0_OFFSET) + #define _MCASP_RBUF11_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_RBUF1_OFFSET) + #define _MCASP_RBUF21_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_RBUF2_OFFSET) + #define _MCASP_RBUF31_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_RBUF3_OFFSET) + /* Fields for _MCASP_CHANNEL_CNT == 4 end here*/ + + #if (_MCASP_CHANNEL_CNT > 4) + #define _MCASP_RBUF41_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_RBUF4_OFFSET) + #define _MCASP_RBUF51_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_RBUF5_OFFSET) + #endif /* _MCASP_CHANNEL_CNT == 6 */ + + #if (_MCASP_CHANNEL_CNT > 6) /* For channel count 8 and 16 */ + #define _MCASP_RBUF61_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_RBUF6_OFFSET) + #define _MCASP_RBUF71_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_RBUF7_OFFSET) + #endif /* _MCASP_CHANNEL_CNT == 8 */ + + #if (_MCASP_CHANNEL_CNT == 16) + #define _MCASP_RBUF81_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_RBUF8_OFFSET) + #define _MCASP_RBUF91_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_RBUF9_OFFSET) + #define _MCASP_RBUF101_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_RBUF10_OFFSET) + #define _MCASP_RBUF111_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_RBUF11_OFFSET) + #define _MCASP_RBUF121_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_RBUF12_OFFSET) + #define _MCASP_RBUF131_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_RBUF13_OFFSET) + #define _MCASP_RBUF141_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_RBUF14_OFFSET) + #define _MCASP_RBUF151_ADDR (_MCASP_BASE_PORT1 + 4*_MCASP_RBUF15_OFFSET) + #endif /* _MCASP_CHANNEL_CNT == 16 */ +#endif + + +/******************************************************************\ +* Step 5. #endif MODULE_SUPPORT and _CSL_MODULELHAL_H_ +\******************************************************************/ + +#endif /* (MODULE_SUPPORT) */ +#endif /* _CSL_MCASPHAL_H_ */ +/******************************************************************************\ +* End of csl_mcasphal.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_mcbsp.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_mcbsp.h new file mode 100644 index 0000000..f371bf8 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_mcbsp.h @@ -0,0 +1,488 @@ +/******************************************************************************\ +* Copyright (C) 1999-2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_mcbsp.h +* DATE CREATED.. 06/11/1999 +* LAST MODIFIED. 09/26/2005 Changed the MCBSP_SRGR_DEFAULT_DELAY macro value +* to 0xFFFF. +* 09/24/2001 +* - MCBSP_read32 / MCBSP_write32 +\******************************************************************************/ +#ifndef _CSL_MCBSP_H_ +#define _CSL_MCBSP_H_ + +#include +#include +#include + + +#if (MCBSP_SUPPORT) +/******************************************************************************\ +* scope and inline control macros +\******************************************************************************/ +#ifdef __cplusplus +#define CSLAPI extern "C" far +#else +#define CSLAPI extern far +#endif + +#undef USEDEFS +#undef IDECL +#undef IDEF + +#ifdef _MCBSP_MOD_ + #define IDECL CSLAPI + #define USEDEFS + #define IDEF +#else + #ifdef _INLINE + #define IDECL static inline + #define USEDEFS + #define IDEF static inline + #else + #define IDECL CSLAPI + #endif +#endif + + +/******************************************************************************\ +* global macro declarations +\******************************************************************************/ + +/* MCBSP_open() flags */ +#define MCBSP_OPEN_RESET (0x00000001) + +/* Renaming MCBSP_read/write */ +#define MCBSP_read32 MCBSP_read +#define MCBSP_write32 MCBSP_write + + +/* pin identifiers used with MCBSP_getPins() and MCBSP_setPins() */ +#define MCBSP_PIN_CLKX _MCBSP_PCR_CLKXP_MASK +#define MCBSP_PIN_FSX _MCBSP_PCR_FSXP_MASK +#define MCBSP_PIN_DX _MCBSP_PCR_DXSTAT_MASK +#define MCBSP_PIN_CLKR _MCBSP_PCR_CLKRP_MASK +#define MCBSP_PIN_FSR _MCBSP_PCR_FSRP_MASK +#define MCBSP_PIN_DR _MCBSP_PCR_DRSTAT_MASK +#define MCBSP_PIN_CLKS _MCBSP_PCR_CLKSSTAT_MASK + +/* device identifiers for MCBSP_open() */ +#define MCBSP_DEV0 (0) +#define MCBSP_DEV1 (1) +#if (_MCBSP_PORT_CNT == 3) + #define MCBSP_DEV2 (2) +#endif + +/* device identifiers for MCBSP_open() */ +#define MCBSP_PORT0 MCBSP_DEV0 +#define MCBSP_PORT1 MCBSP_DEV1 +#if (_MCBSP_PORT_CNT == 3) + #define MCBSP_PORT2 MCBSP_DEV2 +#endif + +/* Constants for MCBSP_start */ +#define MCBSP_RCV_START (1u) +#define MCBSP_XMIT_START (2u) +#define MCBSP_SRGR_START (4u) +#define MCBSP_SRGR_FRAMESYNC (8u) +#define MCBSP_SRGR_DEFAULT_DELAY (0xFFFFu) /* default delay value*/ + +/******************************************************************************\ +* global typedef declarations +\******************************************************************************/ + +/* device handle object */ +typedef struct { + Uint32 allocated; + Uint32 xmtEventId; + Uint32 rcvEventId; + volatile Uint32 *baseAddr; + Uint32 drrAddr; + Uint32 dxrAddr; +} MCBSP_Obj, *MCBSP_Handle; + +/* device configuration structure */ +#if (!C64_SUPPORT) +typedef struct { + Uint32 spcr; + Uint32 rcr; + Uint32 xcr; + Uint32 srgr; + Uint32 mcr; + Uint32 rcer; + Uint32 xcer; + Uint32 pcr; +} MCBSP_Config; +#else +typedef struct { + Uint32 spcr; + Uint32 rcr; + Uint32 xcr; + Uint32 srgr; + Uint32 mcr; + Uint32 rcere0; + Uint32 rcere1; + Uint32 rcere2; + Uint32 rcere3; + Uint32 xcere0; + Uint32 xcere1; + Uint32 xcere2; + Uint32 xcere3; + Uint32 pcr; +} MCBSP_Config; +#endif + +/******************************************************************************\ +* global variable declarations +\******************************************************************************/ + +/* predefined deviced handles for legacy - should not be used*/ +extern far MCBSP_Handle _MCBSP_hDev0; +extern far MCBSP_Handle _MCBSP_hDev1; +#if (_MCBSP_PORT_CNT == 3) + extern far MCBSP_Handle _MCBSP_hDev2; +#endif + + + +/******************************************************************************\ +* global function declarations +\******************************************************************************/ +CSLAPI void MCBSP_reset(MCBSP_Handle hMcbsp); +CSLAPI void MCBSP_resetAll(); +CSLAPI void MCBSP_start(MCBSP_Handle hMcbsp, Uint32 startMask, Uint32 sampleratedelay); + +CSLAPI MCBSP_Handle MCBSP_open(int devNum, Uint32 flags); +CSLAPI void MCBSP_close(MCBSP_Handle hMcbsp); + +CSLAPI Uint32 MCBSP_getPins(MCBSP_Handle hMcbsp); +CSLAPI void MCBSP_setPins(MCBSP_Handle hMcbsp, Uint32 pins); + + +/******************************************************************************\ +* inline function declarations +\******************************************************************************/ +IDECL Uint32 MCBSP_getXmtAddr(MCBSP_Handle hMcbsp); +IDECL Uint32 MCBSP_getRcvAddr(MCBSP_Handle hMcbsp); +IDECL Uint32 MCBSP_getXmtEventId(MCBSP_Handle hMcbsp); +IDECL Uint32 MCBSP_getRcvEventId(MCBSP_Handle hMcbsp); + +IDECL Uint32 MCBSP_read(MCBSP_Handle hMcbsp); +IDECL void MCBSP_write(MCBSP_Handle hMcbsp, Uint32 val); + +IDECL void MCBSP_enableXmt(MCBSP_Handle hMcbsp); +IDECL void MCBSP_enableRcv(MCBSP_Handle hMcbsp); +IDECL void MCBSP_enableFsync(MCBSP_Handle hMcbsp); +IDECL void MCBSP_enableSrgr(MCBSP_Handle hMcbsp); + +IDECL Uint32 MCBSP_xrdy(MCBSP_Handle hMcbsp); +IDECL Uint32 MCBSP_rrdy(MCBSP_Handle hMcbsp); +IDECL Uint32 MCBSP_xempty(MCBSP_Handle hMcbsp); +IDECL Uint32 MCBSP_rfull(MCBSP_Handle hMcbsp); +IDECL Uint32 MCBSP_xsyncerr(MCBSP_Handle hMcbsp); +IDECL Uint32 MCBSP_rsyncerr(MCBSP_Handle hMcbsp); + +IDECL void MCBSP_config(MCBSP_Handle hMcbsp, MCBSP_Config *config); + +#if (!C64_SUPPORT) /* ?? added C64_SUPPORT */ +IDECL void MCBSP_configArgs(MCBSP_Handle hMcbsp, Uint32 spcr, Uint32 rcr, + Uint32 xcr, Uint32 srgr, Uint32 mcr, Uint32 rcer, Uint32 xcer, Uint32 pcr); +#else /* (C64_SUPPORT) */ +IDECL void MCBSP_configArgs(MCBSP_Handle hMcbsp, Uint32 spcr, Uint32 rcr, + Uint32 xcr, Uint32 srgr, Uint32 mcr, Uint32 rcere0, Uint32 rcere1, + Uint32 rcere2, Uint32 rcere3, Uint32 xcere0, Uint32 xcere1, Uint32 xcere2, + Uint32 xcere3, Uint32 pcr); +#endif + +IDECL void MCBSP_getConfig(MCBSP_Handle hMcbsp, MCBSP_Config *config); + + +/******************************************************************************\ +* inline function definitions +\******************************************************************************/ +#ifdef USEDEFS +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCBSP_getXmtAddr(MCBSP_Handle hMcbsp) { + return (Uint32)(hMcbsp->dxrAddr); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCBSP_getRcvAddr(MCBSP_Handle hMcbsp) { + return (Uint32)(hMcbsp->drrAddr); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCBSP_getXmtEventId(MCBSP_Handle hMcbsp) { + return (hMcbsp->xmtEventId); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCBSP_getRcvEventId(MCBSP_Handle hMcbsp) { + return (hMcbsp->rcvEventId); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCBSP_read(MCBSP_Handle hMcbsp) { + return (*(volatile Uint32 *)(hMcbsp->drrAddr)); +} +/*----------------------------------------------------------------------------*/ +IDEF void MCBSP_write(MCBSP_Handle hMcbsp, Uint32 val) { + (*(volatile Uint32 *)(hMcbsp->dxrAddr)) = val; +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCBSP_xrdy(MCBSP_Handle hMcbsp) { + return MCBSP_FGETH(hMcbsp,SPCR,XRDY); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCBSP_rrdy(MCBSP_Handle hMcbsp) { + return MCBSP_FGETH(hMcbsp,SPCR,RRDY); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCBSP_xempty(MCBSP_Handle hMcbsp) { + return MCBSP_FGETH(hMcbsp,SPCR,XEMPTY); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCBSP_rfull(MCBSP_Handle hMcbsp) { + return MCBSP_FGETH(hMcbsp,SPCR,RFULL); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCBSP_xsyncerr(MCBSP_Handle hMcbsp) { + return MCBSP_FGETH(hMcbsp,SPCR,XSYNCERR); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 MCBSP_rsyncerr(MCBSP_Handle hMcbsp) { + return MCBSP_FGETH(hMcbsp,SPCR,RSYNCERR); +} +/*----------------------------------------------------------------------------*/ +IDEF void MCBSP_enableXmt(MCBSP_Handle hMcbsp) { + MCBSP_FSETSH(hMcbsp,SPCR,XRST,NO); +} +/*----------------------------------------------------------------------------*/ +IDEF void MCBSP_enableRcv(MCBSP_Handle hMcbsp) { + MCBSP_FSETSH(hMcbsp,SPCR,RRST,NO); +} +/*----------------------------------------------------------------------------*/ +IDEF void MCBSP_enableFsync(MCBSP_Handle hMcbsp) { + MCBSP_FSETSH(hMcbsp,SPCR,FRST,NO); +} +/*----------------------------------------------------------------------------*/ +IDEF void MCBSP_enableSrgr(MCBSP_Handle hMcbsp) { + MCBSP_FSETSH(hMcbsp,SPCR,GRST,NO); +} +/*----------------------------------------------------------------------------*/ +#if(!C64_SUPPORT) /* ?? added C64_SUPPORT */ +IDEF void MCBSP_config(MCBSP_Handle hMcbsp, MCBSP_Config *config) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)(hMcbsp->baseAddr); + register int x0,x1,x2,x3,x4,x5,x6,x7; + + gie = IRQ_globalDisable(); + + /* the compiler generates more efficient code if the loads */ + /* and stores are grouped together rather than intermixed */ + x0 = config->spcr; + x1 = config->rcr; + x2 = config->xcr; + x3 = config->srgr; + x4 = config->mcr; + x5 = config->rcer; + x6 = config->xcer; + x7 = config->pcr; + + base[_MCBSP_SPCR_OFFSET] = 0x00000000; + base[_MCBSP_RCR_OFFSET] = x1; + base[_MCBSP_XCR_OFFSET] = x2; + base[_MCBSP_SRGR_OFFSET] = x3; + base[_MCBSP_MCR_OFFSET] = x4; + base[_MCBSP_RCER_OFFSET] = x5; + base[_MCBSP_XCER_OFFSET] = x6; + base[_MCBSP_PCR_OFFSET] = x7; + base[_MCBSP_SPCR_OFFSET] = x0; + + IRQ_globalRestore(gie); +} +#else /* (C64_SUPPORT)*/ +IDEF void MCBSP_config(MCBSP_Handle hMcbsp, MCBSP_Config *config) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)(hMcbsp->baseAddr); + register int x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13; + + gie = IRQ_globalDisable(); + + /* the compiler generates more efficient code if the loads */ + /* and stores are grouped together rather than intermixed */ + x0 = config->spcr; + x1 = config->rcr; + x2 = config->xcr; + x3 = config->srgr; + x4 = config->mcr; + x5 = config->rcere0; + x6 = config->rcere1; + x7 = config->rcere2; + x8 = config->rcere3; + x9 = config->xcere0; + x10 = config->xcere1; + x11 = config->xcere2; + x12 = config->xcere3; + x13 = config->pcr; + + base[_MCBSP_SPCR_OFFSET] = 0x00000000; + base[_MCBSP_RCR_OFFSET] = x1; + base[_MCBSP_XCR_OFFSET] = x2; + base[_MCBSP_SRGR_OFFSET] = x3; + base[_MCBSP_MCR_OFFSET] = x4; + base[_MCBSP_RCERE0_OFFSET] = x5; + base[_MCBSP_RCERE1_OFFSET] = x6; + base[_MCBSP_RCERE2_OFFSET] = x7; + base[_MCBSP_RCERE3_OFFSET] = x8; + base[_MCBSP_XCERE0_OFFSET] = x9; + base[_MCBSP_XCERE1_OFFSET] = x10; + base[_MCBSP_XCERE2_OFFSET] = x11; + base[_MCBSP_XCERE3_OFFSET] = x12; + base[_MCBSP_PCR_OFFSET] = x13; + base[_MCBSP_SPCR_OFFSET] = x0; + + IRQ_globalRestore(gie); +} +#endif /* C64_SUPPORT */ +/*----------------------------------------------------------------------------*/ +#if (!C64_SUPPORT) /* ?? added C64_SUPPORT */ +IDEF void MCBSP_configArgs(MCBSP_Handle hMcbsp, Uint32 spcr, Uint32 rcr, + Uint32 xcr, Uint32 srgr, Uint32 mcr, Uint32 rcer, Uint32 xcer, Uint32 pcr) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)(hMcbsp->baseAddr); + + gie = IRQ_globalDisable(); + + base[_MCBSP_SPCR_OFFSET] = 0x00000000; + base[_MCBSP_RCR_OFFSET] = rcr; + base[_MCBSP_XCR_OFFSET] = xcr; + base[_MCBSP_SRGR_OFFSET] = srgr; + base[_MCBSP_MCR_OFFSET] = mcr; + base[_MCBSP_RCER_OFFSET] = rcer; + base[_MCBSP_XCER_OFFSET] = xcer; + base[_MCBSP_PCR_OFFSET] = pcr; + base[_MCBSP_SPCR_OFFSET] = spcr; + + IRQ_globalRestore(gie); +} +#else /* (C64_SUPPORT) */ +IDEF void MCBSP_configArgs(MCBSP_Handle hMcbsp, Uint32 spcr, Uint32 rcr, + Uint32 xcr, Uint32 srgr, Uint32 mcr, Uint32 rcere0, Uint32 rcere1, + Uint32 rcere2, Uint32 rcere3, Uint32 xcere0, Uint32 xcere1, Uint32 xcere2, + Uint32 xcere3, Uint32 pcr) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)(hMcbsp->baseAddr); + + gie = IRQ_globalDisable(); + + base[_MCBSP_SPCR_OFFSET] = 0x00000000; + base[_MCBSP_RCR_OFFSET] = rcr; + base[_MCBSP_XCR_OFFSET] = xcr; + base[_MCBSP_SRGR_OFFSET] = srgr; + base[_MCBSP_MCR_OFFSET] = mcr; + base[_MCBSP_RCERE0_OFFSET] = rcere0; + base[_MCBSP_RCERE1_OFFSET] = rcere1; + base[_MCBSP_RCERE2_OFFSET] = rcere2; + base[_MCBSP_RCERE3_OFFSET] = rcere3; + base[_MCBSP_XCERE0_OFFSET] = xcere0; + base[_MCBSP_XCERE1_OFFSET] = xcere1; + base[_MCBSP_XCERE2_OFFSET] = xcere2; + base[_MCBSP_XCERE3_OFFSET] = xcere3; + base[_MCBSP_PCR_OFFSET] = pcr; + base[_MCBSP_SPCR_OFFSET] = spcr; + + IRQ_globalRestore(gie); +} +#endif /* C64_SUPPORT */ +/*----------------------------------------------------------------------------*/ +#if (!C64_SUPPORT) /* ?? added C64_SUPPORT */ +IDEF void MCBSP_getConfig(MCBSP_Handle hMcbsp, MCBSP_Config *config) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)(hMcbsp->baseAddr); + volatile MCBSP_Config* cfg = (volatile MCBSP_Config*)config; + register int x0,x1,x2,x3,x4,x5,x6,x7; + + gie = IRQ_globalDisable(); + + /* the compiler generates more efficient code if the loads */ + /* and stores are grouped together rather than intermixed */ + + x0 = base[_MCBSP_SPCR_OFFSET]; + x1 = base[_MCBSP_RCR_OFFSET]; + x2 = base[_MCBSP_XCR_OFFSET]; + x3 = base[_MCBSP_SRGR_OFFSET]; + x4 = base[_MCBSP_MCR_OFFSET]; + x5 = base[_MCBSP_RCER_OFFSET]; + x6 = base[_MCBSP_XCER_OFFSET]; + x7 = base[_MCBSP_PCR_OFFSET]; + + cfg->spcr = x0; + cfg->rcr = x1; + cfg->xcr = x2; + cfg->srgr = x3; + cfg->mcr = x4; + cfg->rcer = x5; + cfg->xcer = x6; + cfg->pcr = x7; + + IRQ_globalRestore(gie); +} +#else /* (C64_SUPPORT) */ +IDEF void MCBSP_getConfig(MCBSP_Handle hMcbsp, MCBSP_Config *config) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)(hMcbsp->baseAddr); + volatile MCBSP_Config* cfg = (volatile MCBSP_Config*)config; + register int x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13; + + gie = IRQ_globalDisable(); + + /* the compiler generates more efficient code if the loads */ + /* and stores are grouped together rather than intermixed */ + + x0 = base[_MCBSP_SPCR_OFFSET]; + x1 = base[_MCBSP_RCR_OFFSET]; + x2 = base[_MCBSP_XCR_OFFSET]; + x3 = base[_MCBSP_SRGR_OFFSET]; + x4 = base[_MCBSP_MCR_OFFSET]; + x5 = base[_MCBSP_RCERE0_OFFSET]; + x6 = base[_MCBSP_RCERE1_OFFSET]; + x7 = base[_MCBSP_RCERE2_OFFSET]; + x8 = base[_MCBSP_RCERE3_OFFSET]; + x9 = base[_MCBSP_XCERE0_OFFSET]; + x10 = base[_MCBSP_XCERE1_OFFSET]; + x11 = base[_MCBSP_XCERE2_OFFSET]; + x12 = base[_MCBSP_XCERE3_OFFSET]; + x13 = base[_MCBSP_PCR_OFFSET]; + + cfg->spcr = x0; + cfg->rcr = x1; + cfg->xcr = x2; + cfg->srgr = x3; + cfg->mcr = x4; + cfg->rcere0 = x5; + cfg->rcere1 = x6; + cfg->rcere2 = x7; + cfg->rcere3 = x8; + cfg->xcere0 = x9; + cfg->xcere1 = x10; + cfg->xcere2 = x11; + cfg->xcere3 = x12; + cfg->pcr = x13; + + IRQ_globalRestore(gie); +} +#endif /* C64_SUPPORT */ +/*----------------------------------------------------------------------------*/ +#endif /* USEDEFS */ + + +#endif /* MCBSP_SUPPORT */ +#endif /* _CSL_MCBSP_H_ */ +/******************************************************************************\ +* End of csl_mcbsp.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_mcbsphal.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_mcbsphal.h new file mode 100644 index 0000000..38f88d6 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_mcbsphal.h @@ -0,0 +1,2251 @@ +/******************************************************************************\ +* Copyright (C) 1999-2001 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_mcbsphal.h +* DATE CREATED.. 06/12/1999 +* LAST MODIFIED. 08/02/2004 - Adding support for C6418 +* 10/02/2001 +* - 6713 device addition +* 04/21/2004 - Fixed XCR0 bad address +*------------------------------------------------------------------------------ +* REGISTERS +* +* DRR0 - serial port 0 data receive register +* DRR1 - serial port 1 data receive register +* DRR2 - serial port 2 data receive register (1) +* DXR0 - serial port 0 data transmit register +* DXR1 - serial port 1 data transmit register +* DXR2 - serial port 2 data transmit register (1) +* SPCR0 - serial port 0 control register +* SPCR1 - serial port 1 control register +* SPCR2 - serial port 2 control register (1) +* RCR0 - serial port 0 receive control register +* RCR1 - serial port 1 receive control register +* RCR2 - serial port 2 receive control register (1) +* XCR0 - serial port 0 transmit control register +* XCR1 - serial port 1 transmit control register +* XCR2 - serial port 2 transmit control register (1) +* SRGR0 - serial port 0 sample rate generator register +* SRGR1 - serial port 1 sample rate generator register +* SRGR2 - serial port 2 sample rate generator register (1) +* MCR0 - serial port 0 multichannel control register +* MCR1 - serial port 1 multichannel control register +* MCR2 - serial port 2 multichannel control register (1) +* RCER0 - serial port 0 receive channel enable register +* RCER1 - serial port 1 receive channel enable register +* RCER2 - serial port 2 receive channel enable register (1) +* XCER0 - serial port 0 transmit channel enable register +* XCER1 - serial port 1 transmit channel enable register +* XCER2 - serial port 2 transmit channel enable register (1) +* RCERE00 - serial port 0 Enhanced receive channel enable register 0 (2) +* RCERE01 - serial port 1 Enhanced receive channel enable register 0 (2) +* RCERE02 - serial port 2 Enhanced receive channel enable register 0 (2) +* RCERE10 - serial port 0 Enhanced receive channel enable register 1 (2) +* RCERE11 - serial port 1 Enhanced receive channel enable register 1 (2) +* RCERE12 - serial port 2 Enhanced receive channel enable register 1 (2) +* RCERE20 - serial port 0 Enhanced receive channel enable register 2 (2) +* RCERE21 - serial port 1 Enhanced receive channel enable register 2 (2) +* RCERE22 - serial port 2 Enhanced receive channel enable register 2 (2) +* RCERE30 - serial port 0 Enhanced receive channel enable register 3 (2) +* RCERE31 - serial port 1 Enhanced receive channel enable register 3 (2) +* RCERE32 - serial port 2 Enhanced receive channel enable register 3 (2) +* XCERE00 - serial port 0 Enhanced transmit channel enable register 0 (2) +* XCERE01 - serial port 1 Enhanced transmit channel enable register 0 (2) +* XCERE02 - serial port 2 Enhanced transmit channel enable register 0 (2) +* XCERE10 - serial port 0 Enhanced transmit channel enable register 1 (2) +* XCERE11 - serial port 1 Enhanced transmit channel enable register 1 (2) +* XCERE12 - serial port 2 Enhanced transmit channel enable register 1 (2) +* XCERE20 - serial port 0 Enhanced transmit channel enable register 2 (2) +* XCERE21 - serial port 1 Enhanced transmit channel enable register 2 (2) +* XCERE22 - serial port 2 Enhanced transmit channel enable register 2 (2) +* XCERE30 - serial port 0 Enhanced transmit channel enable register 3 (2) +* XCERE31 - serial port 1 Enhanced transmit channel enable register 3 (2) +* XCERE32 - serial port 2 Enhanced transmit channel enable register 3 (2) +* PCR0 - serial port 0 pin control register +* PCR1 - serial port 1 pin control register +* PCR2 - serial port 2 pin control register (1) +* +* (1) only supported on devices with three serial ports +* (2) supported by C64x devices (RCERx replaced by RCERE0x, XCERx replaced by XCERE0x) +* +\******************************************************************************/ +#ifndef _CSL_MCBSPHAL_H_ +#define _CSL_MCBSPHAL_H_ + +#include +#include + +#if (MCBSP_SUPPORT) +/******************************************************************************\ +* MISC section +\******************************************************************************/ + +#if (CHIP_6202|CHIP_6203|CHIP_6414|CHIP_6415|CHIP_6416) + #define _MCBSP_PORT_CNT 3 + #define _MCBSP_BASE_PORT0 0x018C0000u + #define _MCBSP_BASE_PORT1 0x01900000u + #define _MCBSP_BASE_PORT2 0x01A40000u +#else + #define _MCBSP_PORT_CNT 2 + #define _MCBSP_BASE_PORT0 0x018C0000u + #define _MCBSP_BASE_PORT1 0x01900000u +#endif + + +/******************************************************************************\ +* module level register/field access macros +\******************************************************************************/ + + /* ----------------- */ + /* FIELD MAKE MACROS */ + /* ----------------- */ + + #define MCBSP_FMK(REG,FIELD,x)\ + _PER_FMK(MCBSP,##REG,##FIELD,x) + + #define MCBSP_FMKS(REG,FIELD,SYM)\ + _PER_FMKS(MCBSP,##REG,##FIELD,##SYM) + + + /* -------------------------------- */ + /* RAW REGISTER/FIELD ACCESS MACROS */ + /* -------------------------------- */ + + #define MCBSP_ADDR(REG)\ + _MCBSP_##REG##_ADDR + + #define MCBSP_RGET(REG)\ + _PER_RGET(_MCBSP_##REG##_ADDR,MCBSP,##REG) + + #define MCBSP_RSET(REG,x)\ + _PER_RSET(_MCBSP_##REG##_ADDR,MCBSP,##REG,x) + + #define MCBSP_FGET(REG,FIELD)\ + _MCBSP_##REG##_FGET(##FIELD) + + #define MCBSP_FSET(REG,FIELD,x)\ + _MCBSP_##REG##_FSET(##FIELD,##x) + + #define MCBSP_FSETS(REG,FIELD,SYM)\ + _MCBSP_##REG##_FSETS(##FIELD,##SYM) + + + /* ------------------------------------------ */ + /* ADDRESS BASED REGISTER/FIELD ACCESS MACROS */ + /* ------------------------------------------ */ + + #define MCBSP_RGETA(addr,REG)\ + _PER_RGET(addr,MCBSP,##REG) + + #define MCBSP_RSETA(addr,REG,x)\ + _PER_RSET(addr,MCBSP,##REG,x) + + #define MCBSP_FGETA(addr,REG,FIELD)\ + _PER_FGET(addr,MCBSP,##REG,##FIELD) + + #define MCBSP_FSETA(addr,REG,FIELD,x)\ + _PER_FSET(addr,MCBSP,##REG,##FIELD,x) + + #define MCBSP_FSETSA(addr,REG,FIELD,SYM)\ + _PER_FSETS(addr,MCBSP,##REG,##FIELD,##SYM) + + + /* ----------------------------------------- */ + /* HANDLE BASED REGISTER/FIELD ACCESS MACROS */ + /* ----------------------------------------- */ + + #define MCBSP_ADDRH(h,REG)\ + (Uint32)(&((h)->baseAddr[_MCBSP_##REG##_OFFSET])) + + #define MCBSP_RGETH(h,REG)\ + MCBSP_RGETA(MCBSP_ADDRH(h,##REG),##REG) + + + #define MCBSP_RSETH(h,REG,x)\ + MCBSP_RSETA(MCBSP_ADDRH(h,##REG),##REG,x) + + + #define MCBSP_FGETH(h,REG,FIELD)\ + MCBSP_FGETA(MCBSP_ADDRH(h,##REG),##REG,##FIELD) + + + #define MCBSP_FSETH(h,REG,FIELD,x)\ + MCBSP_FSETA(MCBSP_ADDRH(h,##REG),##REG,##FIELD,x) + + + #define MCBSP_FSETSH(h,REG,FIELD,SYM)\ + MCBSP_FSETSA(MCBSP_ADDRH(h,##REG),##REG,##FIELD,##SYM) + + + +/******************************************************************************\ +* _____________________ +* | | +* | D R R | +* |___________________| +* +* DRR0 - serial port 0 data receive register +* DRR1 - serial port 1 data receive register +* DRR2 - serial port 2 data receive register (1) +* +* (1) only supported on devices with three serial ports +* +* FIELDS (msb -> lsb) +* (r) DR +* +\******************************************************************************/ + #define _MCBSP_DRR_OFFSET 0 + +#if (C11_SUPPORT | C64_SUPPORT) + #define _MCBSP_DRR0_ADDR 0x30000000u + #define _MCBSP_DRR1_ADDR 0x34000000u +#else + #define _MCBSP_DRR0_ADDR 0x018C0000u + #define _MCBSP_DRR1_ADDR 0x01900000u +#endif + +#if (_MCBSP_PORT_CNT==3 && (CHIP_6202 | CHIP_6203 ) ) + #define _MCBSP_DRR2_ADDR 0x01A40000u +#endif + +#if (_MCBSP_PORT_CNT==3 && (CHIP_6414 | CHIP_6415 | CHIP_6416)) + #define _MCBSP_DRR2_ADDR 0x38000000u +#endif + + #define _MCBSP_DRR_DR_MASK 0xFFFFFFFFu + #define _MCBSP_DRR_DR_SHIFT 0x00000000u + #define MCBSP_DRR_DR_DEFAULT 0x00000000u + #define MCBSP_DRR_DR_OF(x) _VALUEOF(x) + + #define MCBSP_DRR_OF(x) _VALUEOF(x) + + #define MCBSP_DRR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(MCBSP,DRR,DR)\ + ) + + #if (CHIP_6413 | CHIP_6418 | CHIP_6410) + #define MCBSP_DRR_RMK(dr) (Uint32)(\ + _PER_FMK(MCBSP,DRR,DR,dr)\ + ) + #endif + + #define _MCBSP_DRR_FGET(N,FIELD)\ + _PER_FGET(_MCBSP_DRR##N##_ADDR,MCBSP,DRR,##FIELD) + #define _MCBSP_DRR_FSET(N,FIELD,field)\ + _PER_FSET(_MCBSP_DRR##N##_ADDR,MCBSP,DRR,##FIELD,field) + #define _MCBSP_DRR_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCBSP_DRR##N##_ADDR,MCBSP,DRR,##FIELD,##SYM) + #define _MCBSP_DRR0_FGET(FIELD) _MCBSP_DRR_FGET(0,##FIELD) + #define _MCBSP_DRR1_FGET(FIELD) _MCBSP_DRR_FGET(1,##FIELD) +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_DRR2_FGET(FIELD) _MCBSP_DRR_FGET(2,##FIELD) +#endif + #define _MCBSP_DRR0_FSET(FIELD,f) _MCBSP_DRR_FSET(0,##FIELD,f) + #define _MCBSP_DRR1_FSET(FIELD,f) _MCBSP_DRR_FSET(1,##FIELD,f) +#if(_MCBSP_PORT_CNT==3) + #define _MCBSP_DRR2_FSET(FIELD,f) _MCBSP_DRR_FSET(2,##FIELD,f) +#endif + #define _MCBSP_DRR0_FSETS(FIELD,SYM) _MCBSP_DRR_FSETS(0,##FIELD,##SYM) + #define _MCBSP_DRR1_FSETS(FIELD,SYM) _MCBSP_DRR_FSETS(1,##FIELD,##SYM) +#if(_MCBSP_PORT_CNT==3) + #define _MCBSP_DRR2_FSETS(FIELD,SYM) _MCBSP_DRR_FSETS(2,##FIELD,##SYM) +#endif +/******************************************************************************\ +* _____________________ +* | | +* | D X R | +* |___________________| +* +* DXR0 - serial port 0 data transmit register +* DXR1 - serial port 1 data transmit register +* DXR2 - serial port 2 data transmit register (1) +* +* (1) only supported on devices with three serial ports +* +* FIELDS (msb -> lsb) +* (w) DX +* +\******************************************************************************/ + #define _MCBSP_DXR_OFFSET 1 + +#if (C11_SUPPORT | C64_SUPPORT) + #define _MCBSP_DXR0_ADDR 0x30000000u + #define _MCBSP_DXR1_ADDR 0x34000000u +#else + #define _MCBSP_DXR0_ADDR 0x018C0004u + #define _MCBSP_DXR1_ADDR 0x01900004u +#endif + +#if (_MCBSP_PORT_CNT==3 && (CHIP_6202 | CHIP_6203) ) + #define _MCBSP_DXR2_ADDR 0x01A40004u +#endif + +#if (_MCBSP_PORT_CNT==3 && (CHIP_6414 | CHIP_6415 | CHIP_6416)) + #define _MCBSP_DXR2_ADDR 0x38000000u +#endif + + #define _MCBSP_DXR_DX_MASK 0xFFFFFFFFu + #define _MCBSP_DXR_DX_SHIFT 0x00000000u + #define MCBSP_DXR_DX_DEFAULT 0x00000000u + #define MCBSP_DXR_DX_OF(x) _VALUEOF(x) + + #define MCBSP_DXR_OF(x) _VALUEOF(x) + + #define MCBSP_DXR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(MCBSP,DXR,DX)\ + ) + + #define MCBSP_DXR_RMK(dr) (Uint32)(\ + _PER_FMK(MCBSP,DXR,DX,dr)\ + ) + + #define _MCBSP_DXR_FGET(N,FIELD)\ + _PER_FGET(_MCBSP_DXR##N##_ADDR,MCBSP,DXR,##FIELD) + + #define _MCBSP_DXR_FSET(N,FIELD,field)\ + _PER_FSET(_MCBSP_DXR##N##_ADDR,MCBSP,DXR,##FIELD,field) + + #define _MCBSP_DXR_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCBSP_DXR##N##_ADDR,MCBSP,DXR,##FIELD,##SYM) + + #define _MCBSP_DXR0_FGET(FIELD) _MCBSP_DXR_FGET(0,##FIELD) + #define _MCBSP_DXR1_FGET(FIELD) _MCBSP_DXR_FGET(1,##FIELD) +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_DXR2_FGET(FIELD) _MCBSP_DXR_FGET(2,##FIELD) +#endif + + #define _MCBSP_DXR0_FSET(FIELD,f) _MCBSP_DXR_FSET(0,##FIELD,f) + #define _MCBSP_DXR1_FSET(FIELD,f) _MCBSP_DXR_FSET(1,##FIELD,f) +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_DXR2_FSET(FIELD,f) _MCBSP_DXR_FSET(2,##FIELD,f) +#endif + + #define _MCBSP_DXR0_FSETS(FIELD,SYM) _MCBSP_DXR_FSETS(0,##FIELD,##SYM) + #define _MCBSP_DXR1_FSETS(FIELD,SYM) _MCBSP_DXR_FSETS(1,##FIELD,##SYM) +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_DXR2_FSETS(FIELD,SYM) _MCBSP_DXR_FSETS(2,##FIELD,##SYM) +#endif + +/******************************************************************************\ +* _____________________ +* | | +* | S P C R | +* |___________________| +* +* SPCR0 - serial port 0 control register +* SPCR1 - serial port 1 control register +* SPCR2 - serial port 2 control register (1) +* +* (1) only supported on devices with three serial ports +* +* FIELDS (msb -> lsb) +* (rw) FREE (2) +* (rw) SOFT (2) +* (rw) FRST +* (rw) GRST +* (rw) XINTM +* (rw) XSYNCERR +* (r) XEMPTY +* (r) XRDY +* (rw) XRST +* (rw) DLB +* (rw) RJUST +* (rw) CLKSTP +* (rw) DXENA (2) +* (rw) RINTM +* (rw) RSYNCERR +* (r) RFULL +* (r) RRDY +* (rw) RRST +* +* (2) - C11_SUPPORT/C64_SUPPORT only +* +\******************************************************************************/ + #define _MCBSP_SPCR_OFFSET 2 + + #define _MCBSP_SPCR0_ADDR 0x018C0008u + #define _MCBSP_SPCR1_ADDR 0x01900008u + +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_SPCR2_ADDR 0x01A40008u +#endif + +#if (C11_SUPPORT | C64_SUPPORT) + #define _MCBSP_SPCR_FREE_MASK 0x02000000u + #define _MCBSP_SPCR_FREE_SHIFT 0x00000019u + #define MCBSP_SPCR_FREE_DEFAULT 0x00000000u + #define MCBSP_SPCR_FREE_OF(x) _VALUEOF(x) + #define MCBSP_SPCR_FREE_NO 0x00000000u + #define MCBSP_SPCR_FREE_YES 0x00000001u + + #define _MCBSP_SPCR_SOFT_MASK 0x01000000u + #define _MCBSP_SPCR_SOFT_SHIFT 0x00000018u + #define MCBSP_SPCR_SOFT_DEFAULT 0x00000000u + #define MCBSP_SPCR_SOFT_OF(x) _VALUEOF(x) + #define MCBSP_SPCR_SOFT_NO 0x00000000u + #define MCBSP_SPCR_SOFT_YES 0x00000001u + +#endif + + #define _MCBSP_SPCR_FRST_MASK 0x00800000u + #define _MCBSP_SPCR_FRST_SHIFT 0x00000017u + #define MCBSP_SPCR_FRST_DEFAULT 0x00000000u + #define MCBSP_SPCR_FRST_OF(x) _VALUEOF(x) + #define MCBSP_SPCR_FRST_YES 0x00000000u + #define MCBSP_SPCR_FRST_0 0x00000000u + #define MCBSP_SPCR_FRST_NO 0x00000001u + #define MCBSP_SPCR_FRST_1 0x00000001u + + #define _MCBSP_SPCR_GRST_MASK 0x00400000u + #define _MCBSP_SPCR_GRST_SHIFT 0x00000016u + #define MCBSP_SPCR_GRST_DEFAULT 0x00000000u + #define MCBSP_SPCR_GRST_OF(x) _VALUEOF(x) + #define MCBSP_SPCR_GRST_YES 0x00000000u + #define MCBSP_SPCR_GRST_0 0x00000000u + #define MCBSP_SPCR_GRST_NO 0x00000001u + #define MCBSP_SPCR_GRST_1 0x00000001u + + #define _MCBSP_SPCR_XINTM_MASK 0x00300000u + #define _MCBSP_SPCR_XINTM_SHIFT 0x00000014u + #define MCBSP_SPCR_XINTM_DEFAULT 0x00000000u + #define MCBSP_SPCR_XINTM_OF(x) _VALUEOF(x) + #define MCBSP_SPCR_XINTM_XRDY 0x00000000u + #define MCBSP_SPCR_XINTM_EOS 0x00000001u + #define MCBSP_SPCR_XINTM_FRM 0x00000002u + #define MCBSP_SPCR_XINTM_XSYNCERR 0x00000003u + + #define _MCBSP_SPCR_XSYNCERR_MASK 0x00080000u + #define _MCBSP_SPCR_XSYNCERR_SHIFT 0x00000013u + #define MCBSP_SPCR_XSYNCERR_DEFAULT 0x00000000u + #define MCBSP_SPCR_XSYNCERR_OF(x) _VALUEOF(x) + #define MCBSP_SPCR_XSYNCERR_NO 0x00000000u + #define MCBSP_SPCR_XSYNCERR_0 0x00000000u + #define MCBSP_SPCR_XSYNCERR_YES 0x00000001u + #define MCBSP_SPCR_XSYNCERR_1 0x00000001u + + #define _MCBSP_SPCR_XEMPTY_MASK 0x00040000u + #define _MCBSP_SPCR_XEMPTY_SHIFT 0x00000012u + #define MCBSP_SPCR_XEMPTY_DEFAULT 0x00000000u + #define MCBSP_SPCR_XEMPTY_OF(x) _VALUEOF(x) + #define MCBSP_SPCR_XEMPTY_YES 0x00000000u + #define MCBSP_SPCR_XEMPTY_0 0x00000000u + #define MCBSP_SPCR_XEMPTY_NO 0x00000001u + #define MCBSP_SPCR_XEMPTY_1 0x00000001u + + #define _MCBSP_SPCR_XRDY_MASK 0x00020000u + #define _MCBSP_SPCR_XRDY_SHIFT 0x00000011u + #define MCBSP_SPCR_XRDY_DEFAULT 0x00000000u + #define MCBSP_SPCR_XRDY_OF(x) _VALUEOF(x) + #define MCBSP_SPCR_XRDY_NO 0x00000000u + #define MCBSP_SPCR_XRDY_YES 0x00000001u + + #define _MCBSP_SPCR_XRST_MASK 0x00010000u + #define _MCBSP_SPCR_XRST_SHIFT 0x00000010u + #define MCBSP_SPCR_XRST_DEFAULT 0x00000000u + #define MCBSP_SPCR_XRST_OF(x) _VALUEOF(x) + #define MCBSP_SPCR_XRST_YES 0x00000000u + #define MCBSP_SPCR_XRST_0 0x00000000u + #define MCBSP_SPCR_XRST_NO 0x00000001u + #define MCBSP_SPCR_XRST_1 0x00000001u + + #define _MCBSP_SPCR_DLB_MASK 0x00008000u + #define _MCBSP_SPCR_DLB_SHIFT 0x0000000Fu + #define MCBSP_SPCR_DLB_DEFAULT 0x00000000u + #define MCBSP_SPCR_DLB_OF(x) _VALUEOF(x) + #define MCBSP_SPCR_DLB_OFF 0x00000000u + #define MCBSP_SPCR_DLB_ON 0x00000001u + + #define _MCBSP_SPCR_RJUST_MASK 0x00006000u + #define _MCBSP_SPCR_RJUST_SHIFT 0x0000000Du + #define MCBSP_SPCR_RJUST_DEFAULT 0x00000000u + #define MCBSP_SPCR_RJUST_OF(x) _VALUEOF(x) + #define MCBSP_SPCR_RJUST_RZF 0x00000000u + #define MCBSP_SPCR_RJUST_RSE 0x00000001u + #define MCBSP_SPCR_RJUST_LZF 0x00000002u + + #define _MCBSP_SPCR_CLKSTP_MASK 0x00001800u + #define _MCBSP_SPCR_CLKSTP_SHIFT 0x0000000Bu + #define MCBSP_SPCR_CLKSTP_DEFAULT 0x00000000u + #define MCBSP_SPCR_CLKSTP_OF(x) _VALUEOF(x) + #define MCBSP_SPCR_CLKSTP_DISABLE 0x00000000u + #define MCBSP_SPCR_CLKSTP_NODELAY 0x00000002u + #define MCBSP_SPCR_CLKSTP_DELAY 0x00000003u + +#if (C11_SUPPORT | C64_SUPPORT) + #define _MCBSP_SPCR_DXENA_MASK 0x00000080u + #define _MCBSP_SPCR_DXENA_SHIFT 0x00000007u + #define MCBSP_SPCR_DXENA_DEFAULT 0x00000000u + #define MCBSP_SPCR_DXENA_OF(x) _VALUEOF(x) + #define MCBSP_SPCR_DXENA_OFF 0x00000000u + #define MCBSP_SPCR_DXENA_ON 0x00000001u +#endif + + #define _MCBSP_SPCR_RINTM_MASK 0x00000030u + #define _MCBSP_SPCR_RINTM_SHIFT 0x00000004u + #define MCBSP_SPCR_RINTM_DEFAULT 0x00000000u + #define MCBSP_SPCR_RINTM_OF(x) _VALUEOF(x) + #define MCBSP_SPCR_RINTM_RRDY 0x00000000u + #define MCBSP_SPCR_RINTM_EOS 0x00000001u + #define MCBSP_SPCR_RINTM_FRM 0x00000002u + #define MCBSP_SPCR_RINTM_RSYNCERR 0x00000003u + + #define _MCBSP_SPCR_RSYNCERR_MASK 0x00000008u + #define _MCBSP_SPCR_RSYNCERR_SHIFT 0x00000003u + #define MCBSP_SPCR_RSYNCERR_DEFAULT 0x00000000u + #define MCBSP_SPCR_RSYNCERR_OF(x) _VALUEOF(x) + #define MCBSP_SPCR_RSYNCERR_NO 0x00000000u + #define MCBSP_SPCR_RSYNCERR_0 0x00000000u + #define MCBSP_SPCR_RSYNCERR_YES 0x00000001u + #define MCBSP_SPCR_RSYNCERR_1 0x00000001u + + #define _MCBSP_SPCR_RFULL_MASK 0x00000004u + #define _MCBSP_SPCR_RFULL_SHIFT 0x00000002u + #define MCBSP_SPCR_RFULL_DEFAULT 0x00000000u + #define MCBSP_SPCR_RFULL_OF(x) _VALUEOF(x) + #define MCBSP_SPCR_RFULL_NO 0x00000000u + #define MCBSP_SPCR_RFULL_YES 0x00000001u + + #define _MCBSP_SPCR_RRDY_MASK 0x00000002u + #define _MCBSP_SPCR_RRDY_SHIFT 0x00000001u + #define MCBSP_SPCR_RRDY_DEFAULT 0x00000000u + #define MCBSP_SPCR_RRDY_OF(x) _VALUEOF(x) + #define MCBSP_SPCR_RRDY_NO 0x00000000u + #define MCBSP_SPCR_RRDY_YES 0x00000001u + + #define _MCBSP_SPCR_RRST_MASK 0x00000001u + #define _MCBSP_SPCR_RRST_SHIFT 0x00000000u + #define MCBSP_SPCR_RRST_DEFAULT 0x00000000u + #define MCBSP_SPCR_RRST_OF(x) _VALUEOF(x) + #define MCBSP_SPCR_RRST_YES 0x00000000u + #define MCBSP_SPCR_RRST_0 0x00000000u + #define MCBSP_SPCR_RRST_NO 0x00000001u + #define MCBSP_SPCR_RRST_1 0x00000001u + + #define MCBSP_SPCR_OF(x) _VALUEOF(x) + +#if (C11_SUPPORT | C64_SUPPORT) + #define MCBSP_SPCR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(MCBSP,SPCR,FREE)\ + |_PER_FDEFAULT(MCBSP,SPCR,SOFT)\ + |_PER_FDEFAULT(MCBSP,SPCR,FRST)\ + |_PER_FDEFAULT(MCBSP,SPCR,GRST)\ + |_PER_FDEFAULT(MCBSP,SPCR,XINTM)\ + |_PER_FDEFAULT(MCBSP,SPCR,XSYNCERR)\ + |_PER_FDEFAULT(MCBSP,SPCR,XEMPTY)\ + |_PER_FDEFAULT(MCBSP,SPCR,XRDY)\ + |_PER_FDEFAULT(MCBSP,SPCR,XRST)\ + |_PER_FDEFAULT(MCBSP,SPCR,DLB)\ + |_PER_FDEFAULT(MCBSP,SPCR,RJUST)\ + |_PER_FDEFAULT(MCBSP,SPCR,CLKSTP)\ + |_PER_FDEFAULT(MCBSP,SPCR,DXENA)\ + |_PER_FDEFAULT(MCBSP,SPCR,RINTM)\ + |_PER_FDEFAULT(MCBSP,SPCR,RSYNCERR)\ + |_PER_FDEFAULT(MCBSP,SPCR,RFULL)\ + |_PER_FDEFAULT(MCBSP,SPCR,RRDY)\ + |_PER_FDEFAULT(MCBSP,SPCR,RRST)\ + ) + + #define MCBSP_SPCR_RMK(free,soft,frst,grst,xintm,xsyncerr,xrst,dlb,rjust,\ + clkstp,dxena,rintm,rsyncerr,rrst) (Uint32)(\ + _PER_FMK(MCBSP,SPCR,FREE,free)\ + |_PER_FMK(MCBSP,SPCR,SOFT,soft)\ + |_PER_FMK(MCBSP,SPCR,FRST,frst)\ + |_PER_FMK(MCBSP,SPCR,GRST,grst)\ + |_PER_FMK(MCBSP,SPCR,XINTM,xintm)\ + |_PER_FMK(MCBSP,SPCR,XSYNCERR,xsyncerr)\ + |_PER_FMK(MCBSP,SPCR,XRST,xrst)\ + |_PER_FMK(MCBSP,SPCR,DLB,dlb)\ + |_PER_FMK(MCBSP,SPCR,RJUST,rjust)\ + |_PER_FMK(MCBSP,SPCR,CLKSTP,clkstp)\ + |_PER_FMK(MCBSP,SPCR,DXENA,dxena)\ + |_PER_FMK(MCBSP,SPCR,RINTM,rintm)\ + |_PER_FMK(MCBSP,SPCR,RSYNCERR,rsyncerr)\ + |_PER_FMK(MCBSP,SPCR,RRST,rrst)\ + ) +#endif + +#if (!C11_SUPPORT && !C64_SUPPORT) + #define MCBSP_SPCR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(MCBSP,SPCR,FRST)\ + |_PER_FDEFAULT(MCBSP,SPCR,GRST)\ + |_PER_FDEFAULT(MCBSP,SPCR,XINTM)\ + |_PER_FDEFAULT(MCBSP,SPCR,XSYNCERR)\ + |_PER_FDEFAULT(MCBSP,SPCR,XEMPTY)\ + |_PER_FDEFAULT(MCBSP,SPCR,XRDY)\ + |_PER_FDEFAULT(MCBSP,SPCR,XRST)\ + |_PER_FDEFAULT(MCBSP,SPCR,DLB)\ + |_PER_FDEFAULT(MCBSP,SPCR,RJUST)\ + |_PER_FDEFAULT(MCBSP,SPCR,CLKSTP)\ + |_PER_FDEFAULT(MCBSP,SPCR,RINTM)\ + |_PER_FDEFAULT(MCBSP,SPCR,RSYNCERR)\ + |_PER_FDEFAULT(MCBSP,SPCR,RFULL)\ + |_PER_FDEFAULT(MCBSP,SPCR,RRDY)\ + |_PER_FDEFAULT(MCBSP,SPCR,RRST)\ + ) + + #define MCBSP_SPCR_RMK(frst,grst,xintm,xsyncerr,xrst,dlb,rjust,\ + clkstp,rintm,rsyncerr,rrst) (Uint32)(\ + _PER_FMK(MCBSP,SPCR,FRST,frst)\ + |_PER_FMK(MCBSP,SPCR,GRST,grst)\ + |_PER_FMK(MCBSP,SPCR,XINTM,xintm)\ + |_PER_FMK(MCBSP,SPCR,XSYNCERR,xsyncerr)\ + |_PER_FMK(MCBSP,SPCR,XRST,xrst)\ + |_PER_FMK(MCBSP,SPCR,DLB,dlb)\ + |_PER_FMK(MCBSP,SPCR,RJUST,rjust)\ + |_PER_FMK(MCBSP,SPCR,CLKSTP,clkstp)\ + |_PER_FMK(MCBSP,SPCR,RINTM,rintm)\ + |_PER_FMK(MCBSP,SPCR,RSYNCERR,rsyncerr)\ + |_PER_FMK(MCBSP,SPCR,RRST,rrst)\ + ) +#endif + + #define _MCBSP_SPCR_FGET(N,FIELD)\ + _PER_FGET(_MCBSP_SPCR##N##_ADDR,MCBSP,SPCR,##FIELD) + + #define _MCBSP_SPCR_FSET(N,FIELD,field)\ + _PER_FSET(_MCBSP_SPCR##N##_ADDR,MCBSP,SPCR,##FIELD,field) + + #define _MCBSP_SPCR_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCBSP_SPCR##N##_ADDR,MCBSP,SPCR,##FIELD,##SYM) + + #define _MCBSP_SPCR0_FGET(FIELD) _MCBSP_SPCR_FGET(0,##FIELD) + #define _MCBSP_SPCR1_FGET(FIELD) _MCBSP_SPCR_FGET(1,##FIELD) +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_SPCR2_FGET(FIELD) _MCBSP_SPCR_FGET(2,##FIELD) +#endif + + #define _MCBSP_SPCR0_FSET(FIELD,f) _MCBSP_SPCR_FSET(0,##FIELD,f) + #define _MCBSP_SPCR1_FSET(FIELD,f) _MCBSP_SPCR_FSET(1,##FIELD,f) +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_SPCR2_FSET(FIELD,f) _MCBSP_SPCR_FSET(2,##FIELD,f) +#endif + + #define _MCBSP_SPCR0_FSETS(FIELD,SYM) _MCBSP_SPCR_FSETS(0,##FIELD,##SYM) + #define _MCBSP_SPCR1_FSETS(FIELD,SYM) _MCBSP_SPCR_FSETS(1,##FIELD,##SYM) +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_SPCR2_FSETS(FIELD,SYM) _MCBSP_SPCR_FSETS(2,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* _____________________ +* | | +* | R C R | +* |___________________| +* +* RCR0 - serial port 0 receive control register +* RCR1 - serial port 1 receive control register +* RCR2 - serial port 2 receive control register (1) +* +* (1) only supported on devices with three serial ports +* +* FIELDS (msb -> lsb) +* (rw) RPHASE +* (rw) RFRLEN2 +* (rw) RWDLEN2 +* (rw) RCOMPAND +* (rw) RFIG +* (rw) RDATDLY +* (rw) RFRLEN1 +* (rw) RWDLEN1 +* (rw) RWDREVRS (2) +* +* (2) - C11_SUPPORT / C64_SUPPORT only +* +\******************************************************************************/ + #define _MCBSP_RCR_OFFSET 3 + + #define _MCBSP_RCR0_ADDR 0x018C000Cu + #define _MCBSP_RCR1_ADDR 0x0190000Cu + +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_RCR2_ADDR 0x01A4000Cu +#endif + + #define _MCBSP_RCR_RPHASE_MASK 0x80000000u + #define _MCBSP_RCR_RPHASE_SHIFT 0x0000001Fu + #define MCBSP_RCR_RPHASE_DEFAULT 0x00000000u + #define MCBSP_RCR_RPHASE_OF(x) _VALUEOF(x) + #define MCBSP_RCR_RPHASE_SINGLE 0x00000000u + #define MCBSP_RCR_RPHASE_DUAL 0x00000001u + + #define _MCBSP_RCR_RFRLEN2_MASK 0x7F000000u + #define _MCBSP_RCR_RFRLEN2_SHIFT 0x00000018u + #define MCBSP_RCR_RFRLEN2_DEFAULT 0x00000000u + #define MCBSP_RCR_RFRLEN2_OF(x) _VALUEOF(x) + + #define _MCBSP_RCR_RWDLEN2_MASK 0x00E00000u + #define _MCBSP_RCR_RWDLEN2_SHIFT 0x00000015u + #define MCBSP_RCR_RWDLEN2_DEFAULT 0x00000000u + #define MCBSP_RCR_RWDLEN2_OF(x) _VALUEOF(x) + #define MCBSP_RCR_RWDLEN2_8BIT 0x00000000u + #define MCBSP_RCR_RWDLEN2_12BIT 0x00000001u + #define MCBSP_RCR_RWDLEN2_16BIT 0x00000002u + #define MCBSP_RCR_RWDLEN2_20BIT 0x00000003u + #define MCBSP_RCR_RWDLEN2_24BIT 0x00000004u + #define MCBSP_RCR_RWDLEN2_32BIT 0x00000005u + + #define _MCBSP_RCR_RCOMPAND_MASK 0x00180000u + #define _MCBSP_RCR_RCOMPAND_SHIFT 0x00000013u + #define MCBSP_RCR_RCOMPAND_DEFAULT 0x00000000u + #define MCBSP_RCR_RCOMPAND_OF(x) _VALUEOF(x) + #define MCBSP_RCR_RCOMPAND_MSB 0x00000000u + #define MCBSP_RCR_RCOMPAND_8BITLSB 0x00000001u + #define MCBSP_RCR_RCOMPAND_ULAW 0x00000002u + #define MCBSP_RCR_RCOMPAND_ALAW 0x00000003u + + #define _MCBSP_RCR_RFIG_MASK 0x00040000u + #define _MCBSP_RCR_RFIG_SHIFT 0x00000012u + #define MCBSP_RCR_RFIG_DEFAULT 0x00000000u + #define MCBSP_RCR_RFIG_OF(x) _VALUEOF(x) + #define MCBSP_RCR_RFIG_NO 0x00000000u + #define MCBSP_RCR_RFIG_YES 0x00000001u + + #define _MCBSP_RCR_RDATDLY_MASK 0x00030000u + #define _MCBSP_RCR_RDATDLY_SHIFT 0x00000010u + #define MCBSP_RCR_RDATDLY_DEFAULT 0x00000000u + #define MCBSP_RCR_RDATDLY_OF(x) _VALUEOF(x) + #define MCBSP_RCR_RDATDLY_0BIT 0x00000000u + #define MCBSP_RCR_RDATDLY_1BIT 0x00000001u + #define MCBSP_RCR_RDATDLY_2BIT 0x00000002u + + #define _MCBSP_RCR_RFRLEN1_MASK 0x00007F00u + #define _MCBSP_RCR_RFRLEN1_SHIFT 0x00000008u + #define MCBSP_RCR_RFRLEN1_DEFAULT 0x00000000u + #define MCBSP_RCR_RFRLEN1_OF(x) _VALUEOF(x) + + #define _MCBSP_RCR_RWDLEN1_MASK 0x000000E0u + #define _MCBSP_RCR_RWDLEN1_SHIFT 0x00000005u + #define MCBSP_RCR_RWDLEN1_DEFAULT 0x00000000u + #define MCBSP_RCR_RWDLEN1_OF(x) _VALUEOF(x) + #define MCBSP_RCR_RWDLEN1_8BIT 0x00000000u + #define MCBSP_RCR_RWDLEN1_12BIT 0x00000001u + #define MCBSP_RCR_RWDLEN1_16BIT 0x00000002u + #define MCBSP_RCR_RWDLEN1_20BIT 0x00000003u + #define MCBSP_RCR_RWDLEN1_24BIT 0x00000004u + #define MCBSP_RCR_RWDLEN1_32BIT 0x00000005u + +#if (C11_SUPPORT | C64_SUPPORT) + #define _MCBSP_RCR_RWDREVRS_MASK 0x00000010u + #define _MCBSP_RCR_RWDREVRS_SHIFT 0x00000004u + #define MCBSP_RCR_RWDREVRS_DEFAULT 0x00000000u + #define MCBSP_RCR_RWDREVRS_OF(x) _VALUEOF(x) + #define MCBSP_RCR_RWDREVRS_DISABLE 0x00000000u + #define MCBSP_RCR_RWDREVRS_ENABLE 0x00000001u +#endif + + #define MCBSP_RCR_OF(x) _VALUEOF(x) + +#if (C11_SUPPORT | C64_SUPPORT) + #define MCBSP_RCR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(MCBSP,RCR,RPHASE)\ + |_PER_FDEFAULT(MCBSP,RCR,RFRLEN2)\ + |_PER_FDEFAULT(MCBSP,RCR,RWDLEN2)\ + |_PER_FDEFAULT(MCBSP,RCR,RCOMPAND)\ + |_PER_FDEFAULT(MCBSP,RCR,RFIG)\ + |_PER_FDEFAULT(MCBSP,RCR,RDATDLY)\ + |_PER_FDEFAULT(MCBSP,RCR,RFRLEN1)\ + |_PER_FDEFAULT(MCBSP,RCR,RWDLEN1)\ + |_PER_FDEFAULT(MCBSP,RCR,RWDREVRS)\ + ) + + #define MCBSP_RCR_RMK(rphase,rfrlen2,rwdlen2,rcompand,rfig,\ + rdatdly,rfrlen1,rwdlen1,rwdrevrs) (Uint32)(\ + _PER_FMK(MCBSP,RCR,RPHASE,rphase)\ + |_PER_FMK(MCBSP,RCR,RFRLEN2,rfrlen2)\ + |_PER_FMK(MCBSP,RCR,RWDLEN2,rwdlen2)\ + |_PER_FMK(MCBSP,RCR,RCOMPAND,rcompand)\ + |_PER_FMK(MCBSP,RCR,RFIG,rfig)\ + |_PER_FMK(MCBSP,RCR,RDATDLY,rdatdly)\ + |_PER_FMK(MCBSP,RCR,RFRLEN1,rfrlen1)\ + |_PER_FMK(MCBSP,RCR,RWDLEN1,rwdlen1)\ + |_PER_FMK(MCBSP,RCR,RWDREVRS,rwdrevrs)\ + ) +#endif + +#if (!C11_SUPPORT && !C64_SUPPORT) + #define MCBSP_RCR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(MCBSP,RCR,RPHASE)\ + |_PER_FDEFAULT(MCBSP,RCR,RFRLEN2)\ + |_PER_FDEFAULT(MCBSP,RCR,RWDLEN2)\ + |_PER_FDEFAULT(MCBSP,RCR,RCOMPAND)\ + |_PER_FDEFAULT(MCBSP,RCR,RFIG)\ + |_PER_FDEFAULT(MCBSP,RCR,RDATDLY)\ + |_PER_FDEFAULT(MCBSP,RCR,RFRLEN1)\ + |_PER_FDEFAULT(MCBSP,RCR,RWDLEN1)\ + ) + + #define MCBSP_RCR_RMK(rphase,rfrlen2,rwdlen2,rcompand,rfig,\ + rdatdly,rfrlen1,rwdlen1) (Uint32)(\ + _PER_FMK(MCBSP,RCR,RPHASE,rphase)\ + |_PER_FMK(MCBSP,RCR,RFRLEN2,rfrlen2)\ + |_PER_FMK(MCBSP,RCR,RWDLEN2,rwdlen2)\ + |_PER_FMK(MCBSP,RCR,RCOMPAND,rcompand)\ + |_PER_FMK(MCBSP,RCR,RFIG,rfig)\ + |_PER_FMK(MCBSP,RCR,RDATDLY,rdatdly)\ + |_PER_FMK(MCBSP,RCR,RFRLEN1,rfrlen1)\ + |_PER_FMK(MCBSP,RCR,RWDLEN1,rwdlen1)\ + ) +#endif + + #define _MCBSP_RCR_FGET(N,FIELD)\ + _PER_FGET(_MCBSP_RCR##N##_ADDR,MCBSP,RCR,##FIELD) + + #define _MCBSP_RCR_FSET(N,FIELD,field)\ + _PER_FSET(_MCBSP_RCR##N##_ADDR,MCBSP,RCR,##FIELD,field) + + #define _MCBSP_RCR_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCBSP_RCR##N##_ADDR,MCBSP,RCR,##FIELD,##SYM) + + #define _MCBSP_RCR0_FGET(FIELD) _MCBSP_RCR_FGET(0,##FIELD) + #define _MCBSP_RCR1_FGET(FIELD) _MCBSP_RCR_FGET(1,##FIELD) +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_RCR2_FGET(FIELD) _MCBSP_RCR_FGET(2,##FIELD) +#endif + + #define _MCBSP_RCR0_FSET(FIELD,f) _MCBSP_RCR_FSET(0,##FIELD,f) + #define _MCBSP_RCR1_FSET(FIELD,f) _MCBSP_RCR_FSET(1,##FIELD,f) +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_RCR2_FSET(FIELD,f) _MCBSP_RCR_FSET(2,##FIELD,f) +#endif + + #define _MCBSP_RCR0_FSETS(FIELD,SYM) _MCBSP_RCR_FSETS(0,##FIELD,##SYM) + #define _MCBSP_RCR1_FSETS(FIELD,SYM) _MCBSP_RCR_FSETS(1,##FIELD,##SYM) +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_RCR2_FSETS(FIELD,SYM) _MCBSP_RCR_FSETS(2,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* _____________________ +* | | +* | X C R | +* |___________________| +* +* XCR0 - serial port 0 transmit control register +* XCR1 - serial port 1 transmit control register +* XCR2 - serial port 2 transmit control register (1) +* +* (1) only supported on devices with three serial ports +* +* FIELDS (msb -> lsb) +* (rw) XPHASE +* (rw) XFRLEN2 +* (rw) XWDLEN2 +* (rw) XCOMPAND +* (rw) XFIG +* (rw) XDATDLY +* (rw) XFRLEN1 +* (rw) XWDLEN1 +* (rw) XWDREVRS (2) +* +* (2) - C11_SUPPORT /C64_SUPPORT only +* +\******************************************************************************/ + #define _MCBSP_XCR_OFFSET 4 + + #define _MCBSP_XCR0_ADDR 0x018C0010u + #define _MCBSP_XCR1_ADDR 0x01900010u + +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_XCR2_ADDR 0x01A40010u +#endif + + #define _MCBSP_XCR_XPHASE_MASK 0x80000000u + #define _MCBSP_XCR_XPHASE_SHIFT 0x0000001Fu + #define MCBSP_XCR_XPHASE_DEFAULT 0x00000000u + #define MCBSP_XCR_XPHASE_OF(x) _VALUEOF(x) + #define MCBSP_XCR_XPHASE_SINGLE 0x00000000u + #define MCBSP_XCR_XPHASE_DUAL 0x00000001u + + #define _MCBSP_XCR_XFRLEN2_MASK 0x7F000000u + #define _MCBSP_XCR_XFRLEN2_SHIFT 0x00000018u + #define MCBSP_XCR_XFRLEN2_DEFAULT 0x00000000u + #define MCBSP_XCR_XFRLEN2_OF(x) _VALUEOF(x) + + #define _MCBSP_XCR_XWDLEN2_MASK 0x00E00000u + #define _MCBSP_XCR_XWDLEN2_SHIFT 0x00000015u + #define MCBSP_XCR_XWDLEN2_DEFAULT 0x00000000u + #define MCBSP_XCR_XWDLEN2_OF(x) _VALUEOF(x) + #define MCBSP_XCR_XWDLEN2_8BIT 0x00000000u + #define MCBSP_XCR_XWDLEN2_12BIT 0x00000001u + #define MCBSP_XCR_XWDLEN2_16BIT 0x00000002u + #define MCBSP_XCR_XWDLEN2_20BIT 0x00000003u + #define MCBSP_XCR_XWDLEN2_24BIT 0x00000004u + #define MCBSP_XCR_XWDLEN2_32BIT 0x00000005u + + #define _MCBSP_XCR_XCOMPAND_MASK 0x00180000u + #define _MCBSP_XCR_XCOMPAND_SHIFT 0x00000013u + #define MCBSP_XCR_XCOMPAND_DEFAULT 0x00000000u + #define MCBSP_XCR_XCOMPAND_OF(x) _VALUEOF(x) + #define MCBSP_XCR_XCOMPAND_MSB 0x00000000u + #define MCBSP_XCR_XCOMPAND_8BITLSB 0x00000001u + #define MCBSP_XCR_XCOMPAND_ULAW 0x00000002u + #define MCBSP_XCR_XCOMPAND_ALAW 0x00000003u + + #define _MCBSP_XCR_XFIG_MASK 0x00040000u + #define _MCBSP_XCR_XFIG_SHIFT 0x00000012u + #define MCBSP_XCR_XFIG_DEFAULT 0x00000000u + #define MCBSP_XCR_XFIG_OF(x) _VALUEOF(x) + #define MCBSP_XCR_XFIG_NO 0x00000000u + #define MCBSP_XCR_XFIG_YES 0x00000001u + + #define _MCBSP_XCR_XDATDLY_MASK 0x00030000u + #define _MCBSP_XCR_XDATDLY_SHIFT 0x00000010u + #define MCBSP_XCR_XDATDLY_DEFAULT 0x00000000u + #define MCBSP_XCR_XDATDLY_OF(x) _VALUEOF(x) + #define MCBSP_XCR_XDATDLY_0BIT 0x00000000u + #define MCBSP_XCR_XDATDLY_1BIT 0x00000001u + #define MCBSP_XCR_XDATDLY_2BIT 0x00000002u + + #define _MCBSP_XCR_XFRLEN1_MASK 0x00007F00u + #define _MCBSP_XCR_XFRLEN1_SHIFT 0x00000008u + #define MCBSP_XCR_XFRLEN1_DEFAULT 0x00000000u + #define MCBSP_XCR_XFRLEN1_OF(x) _VALUEOF(x) + + #define _MCBSP_XCR_XWDLEN1_MASK 0x000000E0u + #define _MCBSP_XCR_XWDLEN1_SHIFT 0x00000005u + #define MCBSP_XCR_XWDLEN1_DEFAULT 0x00000000u + #define MCBSP_XCR_XWDLEN1_OF(x) _VALUEOF(x) + #define MCBSP_XCR_XWDLEN1_8BIT 0x00000000u + #define MCBSP_XCR_XWDLEN1_12BIT 0x00000001u + #define MCBSP_XCR_XWDLEN1_16BIT 0x00000002u + #define MCBSP_XCR_XWDLEN1_20BIT 0x00000003u + #define MCBSP_XCR_XWDLEN1_24BIT 0x00000004u + #define MCBSP_XCR_XWDLEN1_32BIT 0x00000005u + +#if (C11_SUPPORT | C64_SUPPORT) + #define _MCBSP_XCR_XWDREVRS_MASK 0x00000010u + #define _MCBSP_XCR_XWDREVRS_SHIFT 0x00000004u + #define MCBSP_XCR_XWDREVRS_DEFAULT 0x00000000u + #define MCBSP_XCR_XWDREVRS_OF(x) _VALUEOF(x) + #define MCBSP_XCR_XWDREVRS_DISABLE 0x00000000u + #define MCBSP_XCR_XWDREVRS_ENABLE 0x00000001u +#endif + + #define MCBSP_XCR_OF(x) _VALUEOF(x) + +#if (C11_SUPPORT | C64_SUPPORT) + #define MCBSP_XCR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(MCBSP,XCR,XPHASE)\ + |_PER_FDEFAULT(MCBSP,XCR,XFRLEN2)\ + |_PER_FDEFAULT(MCBSP,XCR,XWDLEN2)\ + |_PER_FDEFAULT(MCBSP,XCR,XCOMPAND)\ + |_PER_FDEFAULT(MCBSP,XCR,XFIG)\ + |_PER_FDEFAULT(MCBSP,XCR,XDATDLY)\ + |_PER_FDEFAULT(MCBSP,XCR,XFRLEN1)\ + |_PER_FDEFAULT(MCBSP,XCR,XWDLEN1)\ + |_PER_FDEFAULT(MCBSP,XCR,XWDREVRS)\ + ) + + #define MCBSP_XCR_RMK(xphase,xfrlen2,xwdlen2,xcompand,xfig,\ + xdatdly,xfrlen1,xwdlen1,xwdrevrs) (Uint32)(\ + _PER_FMK(MCBSP,XCR,XPHASE,xphase)\ + |_PER_FMK(MCBSP,XCR,XFRLEN2,xfrlen2)\ + |_PER_FMK(MCBSP,XCR,XWDLEN2,xwdlen2)\ + |_PER_FMK(MCBSP,XCR,XCOMPAND,xcompand)\ + |_PER_FMK(MCBSP,XCR,XFIG,xfig)\ + |_PER_FMK(MCBSP,XCR,XDATDLY,xdatdly)\ + |_PER_FMK(MCBSP,XCR,XFRLEN1,xfrlen1)\ + |_PER_FMK(MCBSP,XCR,XWDLEN1,xwdlen1)\ + |_PER_FMK(MCBSP,XCR,XWDREVRS,xwdrevrs)\ + ) +#endif + +#if (!C11_SUPPORT && !C64_SUPPORT) + #define MCBSP_XCR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(MCBSP,XCR,XPHASE)\ + |_PER_FDEFAULT(MCBSP,XCR,XFRLEN2)\ + |_PER_FDEFAULT(MCBSP,XCR,XWDLEN2)\ + |_PER_FDEFAULT(MCBSP,XCR,XCOMPAND)\ + |_PER_FDEFAULT(MCBSP,XCR,XFIG)\ + |_PER_FDEFAULT(MCBSP,XCR,XDATDLY)\ + |_PER_FDEFAULT(MCBSP,XCR,XFRLEN1)\ + |_PER_FDEFAULT(MCBSP,XCR,XWDLEN1)\ + ) + + #define MCBSP_XCR_RMK(xphase,xfrlen2,xwdlen2,xcompand,xfig,\ + xdatdly,xfrlen1,xwdlen1) (Uint32)(\ + _PER_FMK(MCBSP,XCR,XPHASE,xphase)\ + |_PER_FMK(MCBSP,XCR,XFRLEN2,xfrlen2)\ + |_PER_FMK(MCBSP,XCR,XWDLEN2,xwdlen2)\ + |_PER_FMK(MCBSP,XCR,XCOMPAND,xcompand)\ + |_PER_FMK(MCBSP,XCR,XFIG,xfig)\ + |_PER_FMK(MCBSP,XCR,XDATDLY,xdatdly)\ + |_PER_FMK(MCBSP,XCR,XFRLEN1,xfrlen1)\ + |_PER_FMK(MCBSP,XCR,XWDLEN1,xwdlen1)\ + ) +#endif + + #define _MCBSP_XCR_FGET(N,FIELD)\ + _PER_FGET(_MCBSP_XCR##N##_ADDR,MCBSP,XCR,##FIELD) + + #define _MCBSP_XCR_FSET(N,FIELD,field)\ + _PER_FSET(_MCBSP_XCR##N##_ADDR,MCBSP,XCR,##FIELD,field) + + #define _MCBSP_XCR_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCBSP_XCR##N##_ADDR,MCBSP,XCR,##FIELD,##SYM) + + #define _MCBSP_XCR0_FGET(FIELD) _MCBSP_XCR_FGET(0,##FIELD) + #define _MCBSP_XCR1_FGET(FIELD) _MCBSP_XCR_FGET(1,##FIELD) +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_XCR2_FGET(FIELD) _MCBSP_XCR_FGET(2,##FIELD) +#endif + + #define _MCBSP_XCR0_FSET(FIELD,f) _MCBSP_XCR_FSET(0,##FIELD,f) + #define _MCBSP_XCR1_FSET(FIELD,f) _MCBSP_XCR_FSET(1,##FIELD,f) +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_XCR2_FSET(FIELD,f) _MCBSP_XCR_FSET(2,##FIELD,f) +#endif + + #define _MCBSP_XCR0_FSETS(FIELD,SYM) _MCBSP_XCR_FSETS(0,##FIELD,##SYM) + #define _MCBSP_XCR1_FSETS(FIELD,SYM) _MCBSP_XCR_FSETS(1,##FIELD,##SYM) +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_XCR2_FSETS(FIELD,SYM) _MCBSP_XCR_FSETS(2,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* _____________________ +* | | +* | S R G R | +* |___________________| +* +* SRGR0 - serial port 0 sample rate generator register +* SRGR1 - serial port 1 sample rate generator register +* SRGR2 - serial port 2 sample rate generator register (1) +* +* (1) only supported on devices with three serial ports +* +* FIELDS (msb -> lsb) +* (rw) GSYNC +* (rw) CLKSP +* (rw) CLKSM +* (rw) FSGM +* (rw) FPER +* (rw) FWID +* (rw) CLKGDV +* +\******************************************************************************/ + #define _MCBSP_SRGR_OFFSET 5 + + #define _MCBSP_SRGR0_ADDR 0x018C0014u + #define _MCBSP_SRGR1_ADDR 0x01900014u + +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_SRGR2_ADDR 0x01A40014u +#endif + + #define _MCBSP_SRGR_GSYNC_MASK 0x80000000u + #define _MCBSP_SRGR_GSYNC_SHIFT 0x0000001Fu + #define MCBSP_SRGR_GSYNC_DEFAULT 0x00000000u + #define MCBSP_SRGR_GSYNC_OF(x) _VALUEOF(x) + #define MCBSP_SRGR_GSYNC_FREE 0x00000000u + #define MCBSP_SRGR_GSYNC_SYNC 0x00000001u + + #define _MCBSP_SRGR_CLKSP_MASK 0x40000000u + #define _MCBSP_SRGR_CLKSP_SHIFT 0x0000001Eu + #define MCBSP_SRGR_CLKSP_DEFAULT 0x00000000u + #define MCBSP_SRGR_CLKSP_OF(x) _VALUEOF(x) + #define MCBSP_SRGR_CLKSP_RISING 0x00000000u + #define MCBSP_SRGR_CLKSP_FALLING 0x00000001u + + #define _MCBSP_SRGR_CLKSM_MASK 0x20000000u + #define _MCBSP_SRGR_CLKSM_SHIFT 0x0000001Du + #define MCBSP_SRGR_CLKSM_DEFAULT 0x00000001u + #define MCBSP_SRGR_CLKSM_OF(x) _VALUEOF(x) + #define MCBSP_SRGR_CLKSM_CLKS 0x00000000u + #define MCBSP_SRGR_CLKSM_INTERNAL 0x00000001u + + #define _MCBSP_SRGR_FSGM_MASK 0x10000000u + #define _MCBSP_SRGR_FSGM_SHIFT 0x0000001Cu + #define MCBSP_SRGR_FSGM_DEFAULT 0x00000000u + #define MCBSP_SRGR_FSGM_OF(x) _VALUEOF(x) + #define MCBSP_SRGR_FSGM_DXR2XSR 0x00000000u + #define MCBSP_SRGR_FSGM_FSG 0x00000001u + + #define _MCBSP_SRGR_FPER_MASK 0x0FFF0000u + #define _MCBSP_SRGR_FPER_SHIFT 0x00000010u + #define MCBSP_SRGR_FPER_DEFAULT 0x00000000u + #define MCBSP_SRGR_FPER_OF(x) _VALUEOF(x) + + #define _MCBSP_SRGR_FWID_MASK 0x0000FF00u + #define _MCBSP_SRGR_FWID_SHIFT 0x00000008u + #define MCBSP_SRGR_FWID_DEFAULT 0x00000000u + #define MCBSP_SRGR_FWID_OF(x) _VALUEOF(x) + + #define _MCBSP_SRGR_CLKGDV_MASK 0x000000FFu + #define _MCBSP_SRGR_CLKGDV_SHIFT 0x00000000u + #define MCBSP_SRGR_CLKGDV_DEFAULT 0x00000001u + #define MCBSP_SRGR_CLKGDV_OF(x) _VALUEOF(x) + + #define MCBSP_SRGR_OF(x) _VALUEOF(x) + + #define MCBSP_SRGR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(MCBSP,SRGR,GSYNC)\ + |_PER_FDEFAULT(MCBSP,SRGR,CLKSP)\ + |_PER_FDEFAULT(MCBSP,SRGR,CLKSM)\ + |_PER_FDEFAULT(MCBSP,SRGR,FSGM)\ + |_PER_FDEFAULT(MCBSP,SRGR,FPER)\ + |_PER_FDEFAULT(MCBSP,SRGR,FWID)\ + |_PER_FDEFAULT(MCBSP,SRGR,CLKGDV)\ + ) + + #define MCBSP_SRGR_RMK(gsync,clksp,clksm,fsgm,fper,fwid,clkgdv) (Uint32)(\ + _PER_FMK(MCBSP,SRGR,GSYNC,gsync)\ + |_PER_FMK(MCBSP,SRGR,CLKSP,clksp)\ + |_PER_FMK(MCBSP,SRGR,CLKSM,clksm)\ + |_PER_FMK(MCBSP,SRGR,FSGM,fsgm)\ + |_PER_FMK(MCBSP,SRGR,FPER,fper)\ + |_PER_FMK(MCBSP,SRGR,FWID,fwid)\ + |_PER_FMK(MCBSP,SRGR,CLKGDV,clkgdv)\ + ) + + #define _MCBSP_SRGR_FGET(N,FIELD)\ + _PER_FGET(_MCBSP_SRGR##N##_ADDR,MCBSP,SRGR,##FIELD) + + #define _MCBSP_SRGR_FSET(N,FIELD,field)\ + _PER_FSET(_MCBSP_SRGR##N##_ADDR,MCBSP,SRGR,##FIELD,field) + + #define _MCBSP_SRGR_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCBSP_SRGR##N##_ADDR,MCBSP,SRGR,##FIELD,##SYM) + + #define _MCBSP_SRGR0_FGET(FIELD) _MCBSP_SRGR_FGET(0,##FIELD) + #define _MCBSP_SRGR1_FGET(FIELD) _MCBSP_SRGR_FGET(1,##FIELD) +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_SRGR2_FGET(FIELD) _MCBSP_SRGR_FGET(2,##FIELD) +#endif + + #define _MCBSP_SRGR0_FSET(FIELD,f) _MCBSP_SRGR_FSET(0,##FIELD,f) + #define _MCBSP_SRGR1_FSET(FIELD,f) _MCBSP_SRGR_FSET(1,##FIELD,f) +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_SRGR2_FSET(FIELD,f) _MCBSP_SRGR_FSET(2,##FIELD,f) +#endif + + #define _MCBSP_SRGR0_FSETS(FIELD,SYM) _MCBSP_SRGR_FSETS(0,##FIELD,##SYM) + #define _MCBSP_SRGR1_FSETS(FIELD,SYM) _MCBSP_SRGR_FSETS(1,##FIELD,##SYM) +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_SRGR2_FSETS(FIELD,SYM) _MCBSP_SRGR_FSETS(2,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* _____________________ +* | | +* | M C R | +* |___________________| +* +* MCR0 - serial port 0 multichannel control register +* MCR1 - serial port 1 multichannel control register +* MCR2 - serial port 2 multichannel control register (1) +* +* (1) only supported on devices with three serial ports +* +* FIELDS (msb -> lsb) +* (rw) XMCME (1) +* (rw) XPBBLK +* (rw) XPABLK +* (r) XCBLK +* (rw) XMCM +* (rw) RMCME (1) +* (rw) RPBBLK +* (rw) RPABLK +* (r) RCBLK +* (rw) RMCM +* +* (1) C64_SUPPORT only +\******************************************************************************/ + #define _MCBSP_MCR_OFFSET 6 + + #define _MCBSP_MCR0_ADDR 0x018C0018u + #define _MCBSP_MCR1_ADDR 0x01900018u + +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_MCR2_ADDR 0x01A40018u +#endif + +#if (C64_SUPPORT) + #define _MCBSP_MCR_XMCME_MASK 0x02000000u + #define _MCBSP_MCR_XMCME_SHIFT 0x00000019u + #define MCBSP_MCR_XMCME_DEFAULT 0x00000000u + #define MCBSP_MCR_XMCME_OF(x) _VALUEOF(x) + #define MCBSP_MCR_XMCME_NORMAL 0x00000000u + #define MCBSP_MCR_XMCME_ENHANCED 0x00000001u +#endif + + #define _MCBSP_MCR_XPBBLK_MASK 0x01800000u + #define _MCBSP_MCR_XPBBLK_SHIFT 0x00000017u + #define MCBSP_MCR_XPBBLK_DEFAULT 0x00000000u + #define MCBSP_MCR_XPBBLK_OF(x) _VALUEOF(x) + #define MCBSP_MCR_XPBBLK_SF1 0x00000000u + #define MCBSP_MCR_XPBBLK_SF3 0x00000001u + #define MCBSP_MCR_XPBBLK_SF5 0x00000002u + #define MCBSP_MCR_XPBBLK_SF7 0x00000003u + + #define _MCBSP_MCR_XPABLK_MASK 0x00600000u + #define _MCBSP_MCR_XPABLK_SHIFT 0x00000015u + #define MCBSP_MCR_XPABLK_DEFAULT 0x00000000u + #define MCBSP_MCR_XPABLK_OF(x) _VALUEOF(x) + #define MCBSP_MCR_XPABLK_SF0 0x00000000u + #define MCBSP_MCR_XPABLK_SF2 0x00000001u + #define MCBSP_MCR_XPABLK_SF4 0x00000002u + #define MCBSP_MCR_XPABLK_SF6 0x00000003u + + #define _MCBSP_MCR_XCBLK_MASK 0x001C0000u + #define _MCBSP_MCR_XCBLK_SHIFT 0x00000012u + #define MCBSP_MCR_XCBLK_DEFAULT 0x00000000u + #define MCBSP_MCR_XCBLK_OF(x) _VALUEOF(x) + #define MCBSP_MCR_XCBLK_SF0 0x00000000u + #define MCBSP_MCR_XCBLK_SF1 0x00000001u + #define MCBSP_MCR_XCBLK_SF2 0x00000002u + #define MCBSP_MCR_XCBLK_SF3 0x00000003u + #define MCBSP_MCR_XCBLK_SF4 0x00000004u + #define MCBSP_MCR_XCBLK_SF5 0x00000005u + #define MCBSP_MCR_XCBLK_SF6 0x00000006u + #define MCBSP_MCR_XCBLK_SF7 0x00000007u + + #define _MCBSP_MCR_XMCM_MASK 0x00030000u + #define _MCBSP_MCR_XMCM_SHIFT 0x00000010u + #define MCBSP_MCR_XMCM_DEFAULT 0x00000000u + #define MCBSP_MCR_XMCM_OF(x) _VALUEOF(x) + #define MCBSP_MCR_XMCM_ENNOMASK 0x00000000u + #define MCBSP_MCR_XMCM_DISXP 0x00000001u + #define MCBSP_MCR_XMCM_ENMASK 0x00000002u + #define MCBSP_MCR_XMCM_DISRP 0x00000003u + +#if (C64_SUPPORT) + #define _MCBSP_MCR_RMCME_MASK 0x00000200u + #define _MCBSP_MCR_RMCME_SHIFT 0x00000009u + #define MCBSP_MCR_RMCME_DEFAULT 0x00000000u + #define MCBSP_MCR_RMCME_OF(x) _VALUEOF(x) + #define MCBSP_MCR_RMCME_NORMAL 0x00000000u + #define MCBSP_MCR_RMCME_ENHANCED 0x00000001u +#endif + + #define _MCBSP_MCR_RPBBLK_MASK 0x00000180u + #define _MCBSP_MCR_RPBBLK_SHIFT 0x00000007u + #define MCBSP_MCR_RPBBLK_DEFAULT 0x00000000u + #define MCBSP_MCR_RPBBLK_OF(x) _VALUEOF(x) + #define MCBSP_MCR_RPBBLK_SF1 0x00000000u + #define MCBSP_MCR_RPBBLK_SF3 0x00000001u + #define MCBSP_MCR_RPBBLK_SF5 0x00000002u + #define MCBSP_MCR_RPBBLK_SF7 0x00000003u + + #define _MCBSP_MCR_RPABLK_MASK 0x00000060u + #define _MCBSP_MCR_RPABLK_SHIFT 0x00000005u + #define MCBSP_MCR_RPABLK_DEFAULT 0x00000000u + #define MCBSP_MCR_RPABLK_OF(x) _VALUEOF(x) + #define MCBSP_MCR_RPABLK_SF0 0x00000000u + #define MCBSP_MCR_RPABLK_SF2 0x00000001u + #define MCBSP_MCR_RPABLK_SF4 0x00000002u + #define MCBSP_MCR_RPABLK_SF6 0x00000003u + + #define _MCBSP_MCR_RCBLK_MASK 0x0000001Cu + #define _MCBSP_MCR_RCBLK_SHIFT 0x00000002u + #define MCBSP_MCR_RCBLK_DEFAULT 0x00000000u + #define MCBSP_MCR_RCBLK_OF(x) _VALUEOF(x) + #define MCBSP_MCR_RCBLK_SF0 0x00000000u + #define MCBSP_MCR_RCBLK_SF1 0x00000001u + #define MCBSP_MCR_RCBLK_SF2 0x00000002u + #define MCBSP_MCR_RCBLK_SF3 0x00000003u + #define MCBSP_MCR_RCBLK_SF4 0x00000004u + #define MCBSP_MCR_RCBLK_SF5 0x00000005u + #define MCBSP_MCR_RCBLK_SF6 0x00000006u + #define MCBSP_MCR_RCBLK_SF7 0x00000007u + + #define _MCBSP_MCR_RMCM_MASK 0x00000001u + #define _MCBSP_MCR_RMCM_SHIFT 0x00000000u + #define MCBSP_MCR_RMCM_DEFAULT 0x00000000u + #define MCBSP_MCR_RMCM_OF(x) _VALUEOF(x) + #define MCBSP_MCR_RMCM_CHENABLE 0x00000000u + #define MCBSP_MCR_RMCM_ELDISABLE 0x00000001u + + #define MCBSP_MCR_OF(x) _VALUEOF(x) + + +#if (!C64_SUPPORT) + #define MCBSP_MCR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(MCBSP,MCR,XPBBLK)\ + |_PER_FDEFAULT(MCBSP,MCR,XPABLK)\ + |_PER_FDEFAULT(MCBSP,MCR,XCBLK)\ + |_PER_FDEFAULT(MCBSP,MCR,XMCM)\ + |_PER_FDEFAULT(MCBSP,MCR,RPBBLK)\ + |_PER_FDEFAULT(MCBSP,MCR,RPABLK)\ + |_PER_FDEFAULT(MCBSP,MCR,RCBLK)\ + |_PER_FDEFAULT(MCBSP,MCR,RMCM)\ + ) + + #define MCBSP_MCR_RMK(xpbblk,xpablk,xmcm,rpbblk,rpablk,rmcm) (Uint32)(\ + _PER_FMK(MCBSP,MCR,XPBBLK,xpbblk)\ + |_PER_FMK(MCBSP,MCR,XPABLK,xpablk)\ + |_PER_FMK(MCBSP,MCR,XMCM,xmcm)\ + |_PER_FMK(MCBSP,MCR,RPBBLK,rpbblk)\ + |_PER_FMK(MCBSP,MCR,RPABLK,rpablk)\ + |_PER_FMK(MCBSP,MCR,RMCM,rmcm)\ + ) +#endif + +#if (C64_SUPPORT) + #define MCBSP_MCR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(MCBSP,MCR,XMCME)\ + |_PER_FDEFAULT(MCBSP,MCR,XPBBLK)\ + |_PER_FDEFAULT(MCBSP,MCR,XPABLK)\ + |_PER_FDEFAULT(MCBSP,MCR,XCBLK)\ + |_PER_FDEFAULT(MCBSP,MCR,XMCM)\ + |_PER_FDEFAULT(MCBSP,MCR,RMCME)\ + |_PER_FDEFAULT(MCBSP,MCR,RPBBLK)\ + |_PER_FDEFAULT(MCBSP,MCR,RPABLK)\ + |_PER_FDEFAULT(MCBSP,MCR,RCBLK)\ + |_PER_FDEFAULT(MCBSP,MCR,RMCM)\ + ) + + #define MCBSP_MCR_RMK(xmcme,xpbblk,xpablk,xmcm,rmcme,rpbblk,rpablk,rmcm) (Uint32)(\ + _PER_FMK(MCBSP,MCR,XMCME,xmcme)\ + |_PER_FMK(MCBSP,MCR,XPBBLK,xpbblk)\ + |_PER_FMK(MCBSP,MCR,XPABLK,xpablk)\ + |_PER_FMK(MCBSP,MCR,XMCM,xmcm)\ + |_PER_FMK(MCBSP,MCR,RMCME,rmcme)\ + |_PER_FMK(MCBSP,MCR,RPBBLK,rpbblk)\ + |_PER_FMK(MCBSP,MCR,RPABLK,rpablk)\ + |_PER_FMK(MCBSP,MCR,RMCM,rmcm)\ + ) +#endif + + #define _MCBSP_MCR_FGET(N,FIELD)\ + _PER_FGET(_MCBSP_MCR##N##_ADDR,MCBSP,MCR,##FIELD) + + #define _MCBSP_MCR_FSET(N,FIELD,field)\ + _PER_FSET(_MCBSP_MCR##N##_ADDR,MCBSP,MCR,##FIELD,field) + + #define _MCBSP_MCR_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCBSP_MCR##N##_ADDR,MCBSP,MCR,##FIELD,##SYM) + + #define _MCBSP_MCR0_FGET(FIELD) _MCBSP_MCR_FGET(0,##FIELD) + #define _MCBSP_MCR1_FGET(FIELD) _MCBSP_MCR_FGET(1,##FIELD) +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_MCR2_FGET(FIELD) _MCBSP_MCR_FGET(2,##FIELD) +#endif + + #define _MCBSP_MCR0_FSET(FIELD,f) _MCBSP_MCR_FSET(0,##FIELD,f) + #define _MCBSP_MCR1_FSET(FIELD,f) _MCBSP_MCR_FSET(1,##FIELD,f) +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_MCR2_FSET(FIELD,f) _MCBSP_MCR_FSET(2,##FIELD,f) +#endif + + #define _MCBSP_MCR0_FSETS(FIELD,SYM) _MCBSP_MCR_FSETS(0,##FIELD,##SYM) + #define _MCBSP_MCR1_FSETS(FIELD,SYM) _MCBSP_MCR_FSETS(1,##FIELD,##SYM) +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_MCR2_FSETS(FIELD,SYM) _MCBSP_MCR_FSETS(2,##FIELD,##SYM) +#endif + + +/******************************************************************************\ +* _____________________ +* | | +* | R C E R | +* |___________________| +* +* RCER0 - serial port 0 receive channel enable register +* RCER1 - serial port 1 receive channel enable register +* RCER2 - serial port 2 receive channel enable register (1) +* +* (1) only supported on devices with three serial ports +* +* FIELDS (msb -> lsb) +* (rw) RCEB +* (rw) RCEA +* +\******************************************************************************/ +#if (!C64_SUPPORT) + #define _MCBSP_RCER_OFFSET 7 + + #define _MCBSP_RCER0_ADDR 0x018C001Cu + #define _MCBSP_RCER1_ADDR 0x0190001Cu + +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_RCER2_ADDR 0x01A4001Cu +#endif + + #define _MCBSP_RCER_RCEB_MASK 0xFFFF0000u + #define _MCBSP_RCER_RCEB_SHIFT 0x00000010u + #define MCBSP_RCER_RCEB_DEFAULT 0x00000000u + #define MCBSP_RCER_RCEB_OF(x) _VALUEOF(x) + + #define _MCBSP_RCER_RCEA_MASK 0x0000FFFFu + #define _MCBSP_RCER_RCEA_SHIFT 0x00000000u + #define MCBSP_RCER_RCEA_DEFAULT 0x00000000u + #define MCBSP_RCER_RCEA_OF(x) _VALUEOF(x) + + + #define MCBSP_RCER_OF(x) _VALUEOF(x) + + + #define MCBSP_RCER_DEFAULT (Uint32)(\ + _PER_FDEFAULT(MCBSP,RCER,RCEB)\ + |_PER_FDEFAULT(MCBSP,RCER,RCEA)\ + ) + + #define MCBSP_RCER_RMK(rceb,rcea) (Uint32)(\ + _PER_FMK(MCBSP,RCER,RCEB,rceb)\ + |_PER_FMK(MCBSP,RCER,RCEA,rcea)\ + ) + + + #define _MCBSP_RCER_FGET(N,FIELD)\ + _PER_FGET(_MCBSP_RCER##N##_ADDR,MCBSP,RCER,##FIELD) + + #define _MCBSP_RCER_FSET(N,FIELD,field)\ + _PER_FSET(_MCBSP_RCER##N##_ADDR,MCBSP,RCER,##FIELD,field) + + #define _MCBSP_RCER_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCBSP_RCER##N##_ADDR,MCBSP,RCER,##FIELD,##SYM) + + #define _MCBSP_RCER0_FGET(FIELD) _MCBSP_RCER_FGET(0,##FIELD) + #define _MCBSP_RCER1_FGET(FIELD) _MCBSP_RCER_FGET(1,##FIELD) +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_RCER2_FGET(FIELD) _MCBSP_RCER_FGET(2,##FIELD) +#endif + + #define _MCBSP_RCER0_FSET(FIELD,f) _MCBSP_RCER_FSET(0,##FIELD,f) + #define _MCBSP_RCER1_FSET(FIELD,f) _MCBSP_RCER_FSET(1,##FIELD,f) +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_RCER2_FSET(FIELD,f) _MCBSP_RCER_FSET(2,##FIELD,f) +#endif + + #define _MCBSP_RCER0_FSETS(FIELD,SYM) _MCBSP_RCER_FSETS(0,##FIELD,##SYM) + #define _MCBSP_RCER1_FSETS(FIELD,SYM) _MCBSP_RCER_FSETS(1,##FIELD,##SYM) +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_RCER2_FSETS(FIELD,SYM) _MCBSP_RCER_FSETS(2,##FIELD,##SYM) +#endif + +#endif /* !C64_SUPPORT */ + +/******************************************************************************\ +* _____________________ +* | | +* | R C E R E 0 | +* |___________________| +* +* RCERE00 - serial port 0 enhanced receive channel enable register 0 +* RCERE01 - serial port 1 enhanced receive channel enable register 0 +* RCERE02 - serial port 2 enhanced receive channel enable register 0 +* +* FIELDS (msb -> lsb) +* (rw) RCE +* +\******************************************************************************/ +#if (C64_SUPPORT) + #define _MCBSP_RCERE0_OFFSET 7 + + #define _MCBSP_RCERE00_ADDR 0x018C001Cu + #define _MCBSP_RCERE01_ADDR 0x0190001Cu +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_RCERE02_ADDR 0x01A4001Cu +#endif + #define _MCBSP_RCERE0_RCE_MASK 0xFFFFFFFFu + #define _MCBSP_RCERE0_RCE_SHIFT 0x00000000u + #define MCBSP_RCERE0_RCE_DEFAULT 0x00000000u + #define MCBSP_RCERE0_RCE_OF(x) _VALUEOF(x) + + #define MCBSP_RCERE0_OF(x) _VALUEOF(x) + + #define MCBSP_RCERE0_DEFAULT (Uint32)(\ + _PER_FDEFAULT(MCBSP,RCERE0,RCE)\ + ) + + #define MCBSP_RCERE0_RMK(rce) (Uint32)(\ + _PER_FMK(MCBSP,RCERE0,RCE,rce) \ + ) + + #define _MCBSP_RCERE0_FGET(N,FIELD)\ + _PER_FGET(_MCBSP_RCERE0##N##_ADDR,MCBSP,RCERE0,FIELD) + + #define _MCBSP_RCERE0_FSET(N,FIELD,field)\ + _PER_FSET(_MCBSP_RCERE0##N##_ADDR,MCBSP,RCERE0,FIELD,field) + + #define _MCBSP_RCERE0_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCBSP_RCERE0##N##_ADDR,MCBSP,RCERE0,FIELD,##SYM) + + #define _MCBSP_RCERE00_FGET(FIELD) _MCBSP_RCERE0_FGET(0,##FIELD) + #define _MCBSP_RCERE01_FGET(FIELD) _MCBSP_RCERE0_FGET(1,##FIELD) + #if (_MCBSP_PORT_CNT==3) + #define _MCBSP_RCERE02_FGET(FIELD) _MCBSP_RCERE0_FGET(2,##FIELD) + #endif + + #define _MCBSP_RCERE00_FSET(FIELD,f) _MCBSP_RCERE0_FSET(0,##FIELD,f) + #define _MCBSP_RCERE01_FSET(FIELD,f) _MCBSP_RCERE0_FSET(1,##FIELD,f) + #if (_MCBSP_PORT_CNT==3) + #define _MCBSP_RCERE02_FSET(FIELD,f) _MCBSP_RCERE0_FSET(2,##FIELD,f) + #endif + + #define _MCBSP_RCERE00_FSETS(FIELD,SYM) _MCBSP_RCERE0_FSETS(0,##FIELD,##SYM) + #define _MCBSP_RCERE01_FSETS(FIELD,SYM) _MCBSP_RCERE0_FSETS(1,##FIELD,##SYM) + #if (_MCBSP_PORT_CNT==3) + #define _MCBSP_RCERE02_FSETS(FIELD,SYM) _MCBSP_RCERE0_FSETS(2,##FIELD,##SYM) + #endif +#endif /* C64_SUPPORT */ + + +/******************************************************************************\ +* _____________________ +* | | +* | R C E R E 1 | +* |___________________| +* +* RCERE10 - serial port 0 enhanced receive channel enable register 1 +* RCERE11 - serial port 1 enhanced receive channel enable register 1 +* RCERE12 - serial port 2 enhanced receive channel enable register 1 +* +* FIELDS (msb -> lsb) +* (rw) RCE +* +\******************************************************************************/ +#if (C64_SUPPORT) + #define _MCBSP_RCERE1_OFFSET 10 + + #define _MCBSP_RCERE10_ADDR 0x018C0028u + #define _MCBSP_RCERE11_ADDR 0x01900028u + #if (_MCBSP_PORT_CNT==3) + #define _MCBSP_RCERE12_ADDR 0x01A40028u + #endif + + #define _MCBSP_RCERE1_RCE_MASK 0xFFFFFFFFu + #define _MCBSP_RCERE1_RCE_SHIFT 0x00000000u + #define MCBSP_RCERE1_RCE_DEFAULT 0x00000000u + #define MCBSP_RCERE1_RCE_OF(x) _VALUEOF(x) + + #define MCBSP_RCERE1_OF(x) _VALUEOF(x) + + #define MCBSP_RCERE1_DEFAULT (Uint32)(\ + _PER_FDEFAULT(MCBSP,RCERE1,RCE)\ + ) + + #define MCBSP_RCERE1_RMK(rce) (Uint32)(\ + _PER_FMK(MCBSP,RCERE1,RCE,rce)\ + ) + + #define _MCBSP_RCERE1_FGET(N,FIELD)\ + _PER_FGET(_MCBSP_RCERE1##N##_ADDR,MCBSP,RCERE1,FIELD) + + #define _MCBSP_RCERE1_FSET(N,FIELD,field)\ + _PER_FSET(_MCBSP_RCERE1##N##_ADDR,MCBSP,RCERE1,FIELD,field) + + #define _MCBSP_RCERE1_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCBSP_RCERE1##N##_ADDR,MCBSP,RCERE1,FIELD,##SYM) + + #define _MCBSP_RCERE10_FGET(FIELD) _MCBSP_RCERE1_FGET(0,##FIELD) + #define _MCBSP_RCERE11_FGET(FIELD) _MCBSP_RCERE1_FGET(1,##FIELD) + #if (_MCBSP_PORT_CNT==3) + #define _MCBSP_RCERE12_FGET(FIELD) _MCBSP_RCERE1_FGET(2,##FIELD) + #endif + + #define _MCBSP_RCERE10_FSET(FIELD,f) _MCBSP_RCERE1_FSET(0,##FIELD,f) + #define _MCBSP_RCERE11_FSET(FIELD,f) _MCBSP_RCERE1_FSET(1,##FIELD,f) + #if (_MCBSP_PORT_CNT==3) + #define _MCBSP_RCERE12_FSET(FIELD,f) _MCBSP_RCERE1_FSET(2,##FIELD,f) + #endif + + #define _MCBSP_RCERE10_FSETS(FIELD,SYM) _MCBSP_RCERE1_FSETS(0,##FIELD,##SYM) + #define _MCBSP_RCERE11_FSETS(FIELD,SYM) _MCBSP_RCERE1_FSETS(1,##FIELD,##SYM) + #if (_MCBSP_PORT_CNT==3) + #define _MCBSP_RCERE12_FSETS(FIELD,SYM) _MCBSP_RCERE1_FSETS(2,##FIELD,##SYM) + #endif +#endif /* C64_SUPPORT */ + + +/******************************************************************************\ +* _____________________ +* | | +* | R C E R E 2 | +* |___________________| +* +* RCERE20 - serial port 0 enhanced receive channel enable register 2 +* RCERE21 - serial port 1 enhanced receive channel enable register 2 +* RCERE22 - serial port 2 enhanced receive channel enable register 2 +* +* FIELDS (msb -> lsb) +* (rw) RCE +* +\******************************************************************************/ +#if (C64_SUPPORT) + #define _MCBSP_RCERE2_OFFSET 0xC + + #define _MCBSP_RCERE20_ADDR 0x018C0030u + #define _MCBSP_RCERE21_ADDR 0x01900030u + #if (_MCBSP_PORT_CNT==3) + #define _MCBSP_RCERE22_ADDR 0x01A40030u + #endif + + #define _MCBSP_RCERE2_RCE_MASK 0xFFFFFFFFu + #define _MCBSP_RCERE2_RCE_SHIFT 0x00000000u + #define MCBSP_RCERE2_RCE_DEFAULT 0x00000000u + #define MCBSP_RCERE2_RCE_OF(x) _VALUEOF(x) + + #define MCBSP_RCERE2_OF(x) _VALUEOF(x) + + #define MCBSP_RCERE2_DEFAULT (Uint32)(\ + _PER_FDEFAULT(MCBSP,RCERE2,RCE)\ + ) + + #define MCBSP_RCERE2_RMK(rce) (Uint32)(\ + _PER_FMK(MCBSP,RCERE2,RCE,rce) \ + ) + + #define _MCBSP_RCERE2_FGET(N,FIELD)\ + _PER_FGET(_MCBSP_RCERE2##N##_ADDR,MCBSP,RCERE2,FIELD) + + #define _MCBSP_RCERE2_FSET(N,FIELD,field)\ + _PER_FSET(_MCBSP_RCERE2##N##_ADDR,MCBSP,RCERE2,FIELD,field) + + #define _MCBSP_RCERE2_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCBSP_RCERE2##N##_ADDR,MCBSP,RCERE2,FIELD,##SYM) + + #define _MCBSP_RCERE20_FGET(FIELD) _MCBSP_RCERE2_FGET(0,##FIELD) + #define _MCBSP_RCERE21_FGET(FIELD) _MCBSP_RCERE2_FGET(1,##FIELD) + #if (_MCBSP_PORT_CNT==3) + #define _MCBSP_RCERE22_FGET(FIELD) _MCBSP_RCERE2_FGET(2,##FIELD) + #endif + + #define _MCBSP_RCERE20_FSET(FIELD,f) _MCBSP_RCERE2_FSET(0,##FIELD,f) + #define _MCBSP_RCERE21_FSET(FIELD,f) _MCBSP_RCERE2_FSET(1,##FIELD,f) + #if (_MCBSP_PORT_CNT==3) + #define _MCBSP_RCERE22_FSET(FIELD,f) _MCBSP_RCERE2_FSET(2,##FIELD,f) + #endif + + #define _MCBSP_RCERE20_FSETS(FIELD,SYM) _MCBSP_RCERE2_FSETS(0,##FIELD,##SYM) + #define _MCBSP_RCERE21_FSETS(FIELD,SYM) _MCBSP_RCERE2_FSETS(1,##FIELD,##SYM) + #if (_MCBSP_PORT_CNT==3) + #define _MCBSP_RCERE22_FSETS(FIELD,SYM) _MCBSP_RCERE2_FSETS(2,##FIELD,##SYM) + #endif +#endif /* C64_SUPPORT */ + + +/******************************************************************************\ +* _____________________ +* | | +* | R C E R E 3 | +* |___________________| +* +* RCERE30 - serial port 0 enhanced receive channel enable register 3 +* RCERE31 - serial port 1 enhanced receive channel enable register 3 +* RCERE32 - serial port 2 enhanced receive channel enable register 3 +* +* FIELDS (msb -> lsb) +* (rw) RCE +* +\******************************************************************************/ +#if (C64_SUPPORT) + #define _MCBSP_RCERE3_OFFSET 0xE + + #define _MCBSP_RCERE30_ADDR 0x018C0038u + #define _MCBSP_RCERE31_ADDR 0x01900038u + #if (_MCBSP_PORT_CNT==3) + #define _MCBSP_RCERE32_ADDR 0x01A40038u + #endif + + #define _MCBSP_RCERE3_RCE_MASK 0xFFFFFFFFu + #define _MCBSP_RCERE3_RCE_SHIFT 0x00000000u + #define MCBSP_RCERE3_RCE_DEFAULT 0x00000000u + #define MCBSP_RCERE3_RCE_OF(x) _VALUEOF(x) + + #define MCBSP_RCERE3_OF(x) _VALUEOF(x) + + #define MCBSP_RCERE3_DEFAULT (Uint32)(\ + _PER_FDEFAULT(MCBSP,RCERE3,RCE)\ + ) + + #define MCBSP_RCERE3_RMK(rce) (Uint32)(\ + _PER_FMK(MCBSP,RCERE3,RCE,rce)\ + ) + + #define _MCBSP_RCERE3_FGET(N,FIELD)\ + _PER_FGET(_MCBSP_RCERE3##N##_ADDR,MCBSP,RCERE3,FIELD) + + #define _MCBSP_RCERE3_FSET(N,FIELD,field)\ + _PER_FSET(_MCBSP_RCERE3##N##_ADDR,MCBSP,RCERE3,FIELD,field) + + #define _MCBSP_RCERE3_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCBSP_RCERE3##N##_ADDR,MCBSP,RCERE3,FIELD,##SYM) + + #define _MCBSP_RCERE30_FGET(FIELD) _MCBSP_RCERE3_FGET(0,##FIELD) + #define _MCBSP_RCERE31_FGET(FIELD) _MCBSP_RCERE3_FGET(1,##FIELD) + #if (_MCBSP_PORT_CNT==3) + #define _MCBSP_RCERE32_FGET(FIELD) _MCBSP_RCERE3_FGET(2,##FIELD) + #endif + + #define _MCBSP_RCERE30_FSET(FIELD,f) _MCBSP_RCERE3_FSET(0,##FIELD,f) + #define _MCBSP_RCERE31_FSET(FIELD,f) _MCBSP_RCERE3_FSET(1,##FIELD,f) + #if (_MCBSP_PORT_CNT==3) + #define _MCBSP_RCERE32_FSET(FIELD,f) _MCBSP_RCERE3_FSET(2,##FIELD,f) + #endif + + #define _MCBSP_RCERE30_FSETS(FIELD,SYM) _MCBSP_RCERE3_FSETS(0,##FIELD,##SYM) + #define _MCBSP_RCERE31_FSETS(FIELD,SYM) _MCBSP_RCERE3_FSETS(1,##FIELD,##SYM) + #if (_MCBSP_PORT_CNT==3) + #define _MCBSP_RCERE32_FSETS(FIELD,SYM) _MCBSP_RCERE3_FSETS(2,##FIELD,##SYM) + #endif +#endif /* C64_SUPPORT */ + +/******************************************************************************\ +* _____________________ +* | | +* | X C E R | +* |___________________| +* +* XCER0 - serial port 0 transmit channel enable register +* XCER1 - serial port 1 transmit channel enable register +* XCER2 - serial port 2 transmit channel enable register (1) +* +* (1) only supported on devices with three serial ports +* +* FIELDS (msb -> lsb) +* (rw) XCEB +* (rw) XCEA +* +\******************************************************************************/ + #if (!C64_SUPPORT) + #define _MCBSP_XCER_OFFSET 8 + + #define _MCBSP_XCER0_ADDR 0x018C0020u + #define _MCBSP_XCER1_ADDR 0x01900020u + +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_XCER2_ADDR 0x01A40020u +#endif + + + #define _MCBSP_XCER_XCEB_MASK 0xFFFF0000u + #define _MCBSP_XCER_XCEB_SHIFT 0x00000010u + #define MCBSP_XCER_XCEB_DEFAULT 0x00000000u + #define MCBSP_XCER_XCEB_OF(x) _VALUEOF(x) + + #define _MCBSP_XCER_XCEA_MASK 0x0000FFFFu + #define _MCBSP_XCER_XCEA_SHIFT 0x00000000u + #define MCBSP_XCER_XCEA_DEFAULT 0x00000000u + #define MCBSP_XCER_XCEA_OF(x) _VALUEOF(x) + + #define MCBSP_XCER_OF(x) _VALUEOF(x) + + + #define MCBSP_XCER_DEFAULT (Uint32)(\ + _PER_FDEFAULT(MCBSP,XCER,XCEB)\ + |_PER_FDEFAULT(MCBSP,XCER,XCEA)\ + ) + + #define MCBSP_XCER_RMK(xceb,xcea) (Uint32)(\ + _PER_FMK(MCBSP,XCER,XCEB,xceb)\ + |_PER_FMK(MCBSP,XCER,XCEA,xcea)\ + ) + + #define _MCBSP_XCER_FGET(N,FIELD)\ + _PER_FGET(_MCBSP_XCER##N##_ADDR,MCBSP,XCER,##FIELD) + + #define _MCBSP_XCER_FSET(N,FIELD,field)\ + _PER_FSET(_MCBSP_XCER##N##_ADDR,MCBSP,XCER,##FIELD,field) + + #define _MCBSP_XCER_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCBSP_XCER##N##_ADDR,MCBSP,XCER,##FIELD,##SYM) + + #define _MCBSP_XCER0_FGET(FIELD) _MCBSP_XCER_FGET(0,##FIELD) + #define _MCBSP_XCER1_FGET(FIELD) _MCBSP_XCER_FGET(1,##FIELD) +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_XCER2_FGET(FIELD) _MCBSP_XCER_FGET(2,##FIELD) +#endif + + #define _MCBSP_XCER0_FSET(FIELD,f) _MCBSP_XCER_FSET(0,##FIELD,f) + #define _MCBSP_XCER1_FSET(FIELD,f) _MCBSP_XCER_FSET(1,##FIELD,f) +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_XCER2_FSET(FIELD,f) _MCBSP_XCER_FSET(2,##FIELD,f) +#endif + + #define _MCBSP_XCER0_FSETS(FIELD,SYM) _MCBSP_XCER_FSETS(0,##FIELD,##SYM) + #define _MCBSP_XCER1_FSETS(FIELD,SYM) _MCBSP_XCER_FSETS(1,##FIELD,##SYM) +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_XCER2_FSETS(FIELD,SYM) _MCBSP_XCER_FSETS(2,##FIELD,##SYM) +#endif + +#endif + + +/******************************************************************************\ +* _____________________ +* | | +* | X C E R E 0 | +* |___________________| +* +* XCERE00 - serial port 0 enhanced transmit channel enable register 0 +* XCERE01 - serial port 1 enhanced transmit channel enable register 0 +* XCERE02 - serial port 2 enhanced transmit channel enable register 0 +* +* FIELDS (msb -> lsb) +* (rw) XCE +* +\******************************************************************************/ +#if (C64_SUPPORT) + #define _MCBSP_XCERE0_OFFSET 8 + + #define _MCBSP_XCERE00_ADDR 0x018C0020u + #define _MCBSP_XCERE01_ADDR 0x01900020u + #if (_MCBSP_PORT_CNT==3) + #define _MCBSP_XCERE02_ADDR 0x01A40020u + #endif + + #define _MCBSP_XCERE0_XCE_MASK 0xFFFFFFFFu + #define _MCBSP_XCERE0_XCE_SHIFT 0x00000000u + #define MCBSP_XCERE0_XCE_DEFAULT 0x00000000u + #define MCBSP_XCERE0_XCE_OF(x) _VALUEOF(x) + + #define MCBSP_XCERE0_OF(x) _VALUEOF(x) + + #define MCBSP_XCERE0_DEFAULT (Uint32)(\ + _PER_FDEFAULT(MCBSP,XCERE0,XCE)\ + ) + + #define MCBSP_XCERE0_RMK(xce) (Uint32)(\ + _PER_FMK(MCBSP,XCERE0,XCE,xce) \ + ) + + #define _MCBSP_XCERE0_FGET(N,FIELD)\ + _PER_FGET(_MCBSP_XCERE0##N##_ADDR,MCBSP,XCERE0,FIELD) + + #define _MCBSP_XCERE0_FSET(N,FIELD,field)\ + _PER_FSET(_MCBSP_XCERE0##N##_ADDR,MCBSP,XCERE0,FIELD,field) + + #define _MCBSP_XCERE0_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCBSP_XCERE0##N##_ADDR,MCBSP,XCERE0,FIELD,##SYM) + + #define _MCBSP_XCERE00_FGET(FIELD) _MCBSP_XCERE0_FGET(0,##FIELD) + #define _MCBSP_XCERE01_FGET(FIELD) _MCBSP_XCERE0_FGET(1,##FIELD) + #if (_MCBSP_PORT_CNT==3) + #define _MCBSP_XCERE02_FGET(FIELD) _MCBSP_XCERE0_FGET(2,##FIELD) + #endif + + #define _MCBSP_XCERE00_FSET(FIELD,f) _MCBSP_XCERE0_FSET(0,##FIELD,f) + #define _MCBSP_XCERE01_FSET(FIELD,f) _MCBSP_XCERE0_FSET(1,##FIELD,f) + #if (_MCBSP_PORT_CNT==3) + #define _MCBSP_XCERE02_FSET(FIELD,f) _MCBSP_XCERE0_FSET(2,##FIELD,f) + #endif + + #define _MCBSP_XCERE00_FSETS(FIELD,SYM) _MCBSP_XCERE0_FSETS(0,##FIELD,##SYM) + #define _MCBSP_XCERE01_FSETS(FIELD,SYM) _MCBSP_XCERE0_FSETS(1,##FIELD,##SYM) + #if (_MCBSP_PORT_CNT==3) + #define _MCBSP_XCERE02_FSETS(FIELD,SYM) _MCBSP_XCERE0_FSETS(2,##FIELD,##SYM) + #endif +#endif /* C64_SUPPORT */ + + +/******************************************************************************\ +* _____________________ +* | | +* | X C E R E 1 | +* |___________________| +* +* XCERE10 - serial port 0 enhanced transmit channel enable register 1 +* XCERE11 - serial port 1 enhanced transmit channel enable register 1 +* XCERE12 - serial port 2 enhanced transmit channel enable register 1 +* +* FIELDS (msb -> lsb) +* (rw) XCE +* +\******************************************************************************/ +#if (C64_SUPPORT) + #define _MCBSP_XCERE1_OFFSET 0xB + + #define _MCBSP_XCERE10_ADDR 0x018C002Cu + #define _MCBSP_XCERE11_ADDR 0x0190002Cu + #if (_MCBSP_PORT_CNT==3) + #define _MCBSP_XCERE12_ADDR 0x01A4002Cu + #endif + + #define _MCBSP_XCERE1_XCE_MASK 0xFFFFFFFFu + #define _MCBSP_XCERE1_XCE_SHIFT 0x00000000u + #define MCBSP_XCERE1_XCE_DEFAULT 0x00000000u + #define MCBSP_XCERE1_XCE_OF(x) _VALUEOF(x) + + #define MCBSP_XCERE1_OF(x) _VALUEOF(x) + + #define MCBSP_XCERE1_DEFAULT (Uint32)(\ + _PER_FDEFAULT(MCBSP,XCERE1,XCE)\ + ) + + #define MCBSP_XCERE1_RMK(xce) (Uint32)(\ + _PER_FMK(MCBSP,XCERE1,XCE,xce)\ + ) + + #define _MCBSP_XCERE1_FGET(N,FIELD)\ + _PER_FGET(_MCBSP_XCERE1##N##_ADDR,MCBSP,XCERE1,FIELD) + + #define _MCBSP_XCERE1_FSET(N,FIELD,field)\ + _PER_FSET(_MCBSP_XCERE1##N##_ADDR,MCBSP,XCERE1,FIELD,field) + + #define _MCBSP_XCERE1_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCBSP_XCERE1##N##_ADDR,MCBSP,XCERE1,FIELD,##SYM) + + #define _MCBSP_XCERE10_FGET(FIELD) _MCBSP_XCERE1_FGET(0,##FIELD) + #define _MCBSP_XCERE11_FGET(FIELD) _MCBSP_XCERE1_FGET(1,##FIELD) + #if (_MCBSP_PORT_CNT==3) + #define _MCBSP_XCERE12_FGET(FIELD) _MCBSP_XCERE1_FGET(2,##FIELD) + #endif + + #define _MCBSP_XCERE10_FSET(FIELD,f) _MCBSP_XCERE1_FSET(0,##FIELD,f) + #define _MCBSP_XCERE11_FSET(FIELD,f) _MCBSP_XCERE1_FSET(1,##FIELD,f) + #if (_MCBSP_PORT_CNT==3) + #define _MCBSP_XCERE12_FSET(FIELD,f) _MCBSP_XCERE1_FSET(2,##FIELD,f) + #endif + + #define _MCBSP_XCERE10_FSETS(FIELD,SYM) _MCBSP_XCERE1_FSETS(0,##FIELD,##SYM) + #define _MCBSP_XCERE11_FSETS(FIELD,SYM) _MCBSP_XCERE1_FSETS(1,##FIELD,##SYM) + #if (_MCBSP_PORT_CNT==3) + #define _MCBSP_XCERE12_FSETS(FIELD,SYM) _MCBSP_XCERE1_FSETS(2,##FIELD,##SYM) + #endif +#endif /* C64_SUPPORT */ + + +/******************************************************************************\ +* _____________________ +* | | +* | X C E R E 2 | +* |___________________| +* +* XCERE20 - serial port 0 enhanced transmit channel enable register 2 +* XCERE21 - serial port 1 enhanced transmit channel enable register 2 +* XCERE22 - serial port 2 enhanced transmit channel enable register 2 +* +* FIELDS (msb -> lsb) +* (rw) XCE +* +\******************************************************************************/ +#if (C64_SUPPORT) + #define _MCBSP_XCERE2_OFFSET 0xD + + #define _MCBSP_XCERE20_ADDR 0x018C0034u + #define _MCBSP_XCERE21_ADDR 0x01900034u + #if (_MCBSP_PORT_CNT==3) + #define _MCBSP_XCERE22_ADDR 0x01A40034u + #endif + + #define _MCBSP_XCERE2_XCE_MASK 0xFFFFFFFFu + #define _MCBSP_XCERE2_XCE_SHIFT 0x00000000u + #define MCBSP_XCERE2_XCE_DEFAULT 0x00000000u + #define MCBSP_XCERE2_XCE_OF(x) _VALUEOF(x) + + #define MCBSP_XCERE2_OF(x) _VALUEOF(x) + + #define MCBSP_XCERE2_DEFAULT (Uint32)(\ + _PER_FDEFAULT(MCBSP,XCERE2,XCE)\ + ) + + #define MCBSP_XCERE2_RMK(xce) (Uint32)(\ + _PER_FMK(MCBSP,XCERE2,XCE,xce)\ + ) + + #define _MCBSP_XCERE2_FGET(N,FIELD)\ + _PER_FGET(_MCBSP_XCERE2##N##_ADDR,MCBSP,XCERE2,FIELD) + + #define _MCBSP_XCERE2_FSET(N,FIELD,field)\ + _PER_FSET(_MCBSP_XCERE2##N##_ADDR,MCBSP,XCERE2,FIELD,field) + + #define _MCBSP_XCERE2_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCBSP_XCERE2##N##_ADDR,MCBSP,XCERE2,FIELD,##SYM) + + #define _MCBSP_XCERE20_FGET(FIELD) _MCBSP_XCERE2_FGET(0,##FIELD) + #define _MCBSP_XCERE21_FGET(FIELD) _MCBSP_XCERE2_FGET(1,##FIELD) + #if (_MCBSP_PORT_CNT==3) + #define _MCBSP_XCERE22_FGET(FIELD) _MCBSP_XCERE2_FGET(2,##FIELD) + #endif + + #define _MCBSP_XCERE20_FSET(FIELD,f) _MCBSP_XCERE2_FSET(0,##FIELD,f) + #define _MCBSP_XCERE21_FSET(FIELD,f) _MCBSP_XCERE2_FSET(1,##FIELD,f) + #if (_MCBSP_PORT_CNT==3) + #define _MCBSP_XCERE22_FSET(FIELD,f) _MCBSP_XCERE2_FSET(2,##FIELD,f) + #endif + + #define _MCBSP_XCERE20_FSETS(FIELD,SYM) _MCBSP_XCERE2_FSETS(0,##FIELD,##SYM) + #define _MCBSP_XCERE21_FSETS(FIELD,SYM) _MCBSP_XCERE2_FSETS(1,##FIELD,##SYM) + #if (_MCBSP_PORT_CNT==3) + #define _MCBSP_XCERE22_FSETS(FIELD,SYM) _MCBSP_XCERE2_FSETS(2,##FIELD,##SYM) + #endif +#endif /* C64_SUPPORT */ + + +/******************************************************************************\ +* _____________________ +* | | +* | X C E R E 3 | +* |___________________| +* +* XCERE30 - serial port 0 enhanced transmit channel enable register 3 +* XCERE31 - serial port 1 enhanced transmit channel enable register 3 +* XCERE32 - serial port 2 enhanced transmit channel enable register 3 +* +* FIELDS (msb -> lsb) +* (rw) XCE +* +\******************************************************************************/ +#if (C64_SUPPORT) + #define _MCBSP_XCERE3_OFFSET 0xF + + #define _MCBSP_XCERE30_ADDR 0x018C003Cu + #define _MCBSP_XCERE31_ADDR 0x0190003Cu + #if (_MCBSP_PORT_CNT==3) + #define _MCBSP_XCERE32_ADDR 0x01A4003Cu + #endif + + #define _MCBSP_XCERE3_XCE_MASK 0xFFFFFFFFu + #define _MCBSP_XCERE3_XCE_SHIFT 0x00000000u + #define MCBSP_XCERE3_XCE_DEFAULT 0x00000000u + #define MCBSP_XCERE3_XCE_OF(x) _VALUEOF(x) + + #define MCBSP_XCERE3_OF(x) _VALUEOF(x) + + #define MCBSP_XCERE3_DEFAULT (Uint32)(\ + _PER_FDEFAULT(MCBSP,XCERE3,XCE)\ + ) + + #define MCBSP_XCERE3_RMK(xce) (Uint32)(\ + _PER_FMK(MCBSP,XCERE3,XCE,xce)\ + ) + + #define _MCBSP_XCERE3_FGET(N,FIELD)\ + _PER_FGET(_MCBSP_XCERE3##N##_ADDR,MCBSP,XCERE3,FIELD) + + #define _MCBSP_XCERE3_FSET(N,FIELD,field)\ + _PER_FSET(_MCBSP_XCERE3##N##_ADDR,MCBSP,XCERE3,FIELD,field) + + #define _MCBSP_XCERE3_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCBSP_XCERE3##N##_ADDR,MCBSP,XCERE3,FIELD,##SYM) + + #define _MCBSP_XCERE30_FGET(FIELD) _MCBSP_XCERE3_FGET(0,##FIELD) + #define _MCBSP_XCERE31_FGET(FIELD) _MCBSP_XCERE3_FGET(1,##FIELD) + #if (_MCBSP_PORT_CNT==3) + #define _MCBSP_XCERE32_FGET(FIELD) _MCBSP_XCERE3_FGET(2,##FIELD) + #endif + + #define _MCBSP_XCERE30_FSET(FIELD,f) _MCBSP_XCERE3_FSET(0,##FIELD,f) + #define _MCBSP_XCERE31_FSET(FIELD,f) _MCBSP_XCERE3_FSET(1,##FIELD,f) + #if (_MCBSP_PORT_CNT==3) + #define _MCBSP_XCERE32_FSET(FIELD,f) _MCBSP_XCERE3_FSET(2,##FIELD,f) + #endif + + #define _MCBSP_XCERE30_FSETS(FIELD,SYM) _MCBSP_XCERE3_FSETS(0,##FIELD,##SYM) + #define _MCBSP_XCERE31_FSETS(FIELD,SYM) _MCBSP_XCERE3_FSETS(1,##FIELD,##SYM) + #if (_MCBSP_PORT_CNT==3) + #define _MCBSP_XCERE32_FSETS(FIELD,SYM) _MCBSP_XCERE3_FSETS(2,##FIELD,##SYM) + #endif +#endif /* C64_SUPPORT */ + +/******************************************************************************\ +* _____________________ +* | | +* | P C R | +* |___________________| +* +* PCR0 - serial port 0 pin control register +* PCR1 - serial port 1 pin control register +* PCR2 - serial port 2 pin control register (1) +* +* (1) only supported on devices with three serial ports +* +* FIELDS (msb -> lsb) +* (rw) XIOEN +* (rw) RIOEN +* (rw) FSXM +* (rw) FSRM +* (rw) CLKXM +* (rw) CLKRM +* (r) CLKSSTAT +* (rw) DXSTAT +* (r) DRSTAT +* (rw) FSXP +* (rw) FSRP +* (rw) CLKXP +* (rw) CLKRP +* +\******************************************************************************/ + #define _MCBSP_PCR_OFFSET 9 + + #define _MCBSP_PCR0_ADDR 0x018C0024u + #define _MCBSP_PCR1_ADDR 0x01900024u + +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_PCR2_ADDR 0x01A40024u +#endif + + #define _MCBSP_PCR_XIOEN_MASK 0x00002000u + #define _MCBSP_PCR_XIOEN_SHIFT 0x0000000Du + #define MCBSP_PCR_XIOEN_DEFAULT 0x00000000u + #define MCBSP_PCR_XIOEN_OF(x) _VALUEOF(x) + #define MCBSP_PCR_XIOEN_SP 0x00000000u + #define MCBSP_PCR_XIOEN_GPIO 0x00000001u + + #define _MCBSP_PCR_RIOEN_MASK 0x00001000u + #define _MCBSP_PCR_RIOEN_SHIFT 0x0000000Cu + #define MCBSP_PCR_RIOEN_DEFAULT 0x00000000u + #define MCBSP_PCR_RIOEN_OF(x) _VALUEOF(x) + #define MCBSP_PCR_RIOEN_SP 0x00000000u + #define MCBSP_PCR_RIOEN_GPIO 0x00000001u + + #define _MCBSP_PCR_FSXM_MASK 0x00000800u + #define _MCBSP_PCR_FSXM_SHIFT 0x0000000Bu + #define MCBSP_PCR_FSXM_DEFAULT 0x00000000u + #define MCBSP_PCR_FSXM_OF(x) _VALUEOF(x) + #define MCBSP_PCR_FSXM_EXTERNAL 0x00000000u + #define MCBSP_PCR_FSXM_INTERNAL 0x00000001u + + #define _MCBSP_PCR_FSRM_MASK 0x00000400u + #define _MCBSP_PCR_FSRM_SHIFT 0x0000000Au + #define MCBSP_PCR_FSRM_DEFAULT 0x00000000u + #define MCBSP_PCR_FSRM_OF(x) _VALUEOF(x) + #define MCBSP_PCR_FSRM_EXTERNAL 0x00000000u + #define MCBSP_PCR_FSRM_INTERNAL 0x00000001u + + #define _MCBSP_PCR_CLKXM_MASK 0x00000200u + #define _MCBSP_PCR_CLKXM_SHIFT 0x00000009u + #define MCBSP_PCR_CLKXM_DEFAULT 0x00000000u + #define MCBSP_PCR_CLKXM_OF(x) _VALUEOF(x) + #define MCBSP_PCR_CLKXM_INPUT 0x00000000u + #define MCBSP_PCR_CLKXM_OUTPUT 0x00000001u + + #define _MCBSP_PCR_CLKRM_MASK 0x00000100u + #define _MCBSP_PCR_CLKRM_SHIFT 0x00000008u + #define MCBSP_PCR_CLKRM_DEFAULT 0x00000000u + #define MCBSP_PCR_CLKRM_OF(x) _VALUEOF(x) + #define MCBSP_PCR_CLKRM_INPUT 0x00000000u + #define MCBSP_PCR_CLKRM_OUTPUT 0x00000001u + + #define _MCBSP_PCR_CLKSSTAT_MASK 0x00000040u + #define _MCBSP_PCR_CLKSSTAT_SHIFT 0x00000006u + #define MCBSP_PCR_CLKSSTAT_DEFAULT 0x00000000u + #define MCBSP_PCR_CLKSSTAT_OF(x) _VALUEOF(x) + #define MCBSP_PCR_CLKSSTAT_0 0x00000000u + #define MCBSP_PCR_CLKSSTAT_1 0x00000001u + + #define _MCBSP_PCR_DXSTAT_MASK 0x00000020u + #define _MCBSP_PCR_DXSTAT_SHIFT 0x00000005u + #define MCBSP_PCR_DXSTAT_DEFAULT 0x00000000u + #define MCBSP_PCR_DXSTAT_OF(x) _VALUEOF(x) + #define MCBSP_PCR_DXSTAT_0 0x00000000u + #define MCBSP_PCR_DXSTAT_1 0x00000001u + + #define _MCBSP_PCR_DRSTAT_MASK 0x00000010u + #define _MCBSP_PCR_DRSTAT_SHIFT 0x00000004u + #define MCBSP_PCR_DRSTAT_DEFAULT 0x00000000u + #define MCBSP_PCR_DRSTAT_OF(x) _VALUEOF(x) + #define MCBSP_PCR_DRSTAT_0 0x00000000u + #define MCBSP_PCR_DRSTAT_1 0x00000001u + + #define _MCBSP_PCR_FSXP_MASK 0x00000008u + #define _MCBSP_PCR_FSXP_SHIFT 0x00000003u + #define MCBSP_PCR_FSXP_DEFAULT 0x00000000u + #define MCBSP_PCR_FSXP_OF(x) _VALUEOF(x) + #define MCBSP_PCR_FSXP_ACTIVEHIGH 0x00000000u + #define MCBSP_PCR_FSXP_ACTIVELOW 0x00000001u + + #define _MCBSP_PCR_FSRP_MASK 0x00000004u + #define _MCBSP_PCR_FSRP_SHIFT 0x00000002u + #define MCBSP_PCR_FSRP_DEFAULT 0x00000000u + #define MCBSP_PCR_FSRP_OF(x) _VALUEOF(x) + #define MCBSP_PCR_FSRP_ACTIVEHIGH 0x00000000u + #define MCBSP_PCR_FSRP_ACTIVELOW 0x00000001u + + #define _MCBSP_PCR_CLKXP_MASK 0x00000002u + #define _MCBSP_PCR_CLKXP_SHIFT 0x00000001u + #define MCBSP_PCR_CLKXP_DEFAULT 0x00000000u + #define MCBSP_PCR_CLKXP_OF(x) _VALUEOF(x) + #define MCBSP_PCR_CLKXP_RISING 0x00000000u + #define MCBSP_PCR_CLKXP_FALLING 0x00000001u + + #define _MCBSP_PCR_CLKRP_MASK 0x00000001u + #define _MCBSP_PCR_CLKRP_SHIFT 0x00000000u + #define MCBSP_PCR_CLKRP_DEFAULT 0x00000000u + #define MCBSP_PCR_CLKRP_OF(x) _VALUEOF(x) + #define MCBSP_PCR_CLKRP_FALLING 0x00000000u + #define MCBSP_PCR_CLKRP_RISING 0x00000001u + + #define MCBSP_PCR_OF(x) _VALUEOF(x) + + #define MCBSP_PCR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(MCBSP,PCR,XIOEN)\ + |_PER_FDEFAULT(MCBSP,PCR,RIOEN)\ + |_PER_FDEFAULT(MCBSP,PCR,FSXM)\ + |_PER_FDEFAULT(MCBSP,PCR,FSRM)\ + |_PER_FDEFAULT(MCBSP,PCR,CLKXM)\ + |_PER_FDEFAULT(MCBSP,PCR,CLKRM)\ + |_PER_FDEFAULT(MCBSP,PCR,CLKSSTAT)\ + |_PER_FDEFAULT(MCBSP,PCR,DXSTAT)\ + |_PER_FDEFAULT(MCBSP,PCR,DRSTAT)\ + |_PER_FDEFAULT(MCBSP,PCR,FSXP)\ + |_PER_FDEFAULT(MCBSP,PCR,FSRP)\ + |_PER_FDEFAULT(MCBSP,PCR,CLKXP)\ + |_PER_FDEFAULT(MCBSP,PCR,CLKRP)\ + ) + + #if (CHIP_6410 | CHIP_6413 | CHIP_6418) + #define MCBSP_PCR_RMK(xioen,rioen,fsxm,fsrm,clkxm,clkrm,\ + dxstat,fsxp,fsrp,clkxp,clkrp) (Uint32)(\ + _PER_FMK(MCBSP,PCR,XIOEN,xioen)\ + |_PER_FMK(MCBSP,PCR,RIOEN,rioen)\ + |_PER_FMK(MCBSP,PCR,FSXM,fsxm)\ + |_PER_FMK(MCBSP,PCR,FSRM,fsrm)\ + |_PER_FMK(MCBSP,PCR,CLKXM,clkxm)\ + |_PER_FMK(MCBSP,PCR,CLKRM,clkrm)\ + |_PER_FMK(MCBSP,PCR,DXSTAT,dxstat)\ + |_PER_FMK(MCBSP,PCR,FSXP,fsxp)\ + |_PER_FMK(MCBSP,PCR,FSRP,fsrp)\ + |_PER_FMK(MCBSP,PCR,CLKXP,clkxp)\ + |_PER_FMK(MCBSP,PCR,CLKRP,clkrp)\ + ) + #else + #define MCBSP_PCR_RMK(xioen,rioen,fsxm,fsrm,clkxm,clkrm,clksstat,\ + dxstat,fsxp,fsrp,clkxp,clkrp) (Uint32)(\ + _PER_FMK(MCBSP,PCR,XIOEN,xioen)\ + |_PER_FMK(MCBSP,PCR,RIOEN,rioen)\ + |_PER_FMK(MCBSP,PCR,FSXM,fsxm)\ + |_PER_FMK(MCBSP,PCR,FSRM,fsrm)\ + |_PER_FMK(MCBSP,PCR,CLKXM,clkxm)\ + |_PER_FMK(MCBSP,PCR,CLKRM,clkrm)\ + |_PER_FMK(MCBSP,PCR,CLKSSTAT,clksstat)\ + |_PER_FMK(MCBSP,PCR,DXSTAT,dxstat)\ + |_PER_FMK(MCBSP,PCR,FSXP,fsxp)\ + |_PER_FMK(MCBSP,PCR,FSRP,fsrp)\ + |_PER_FMK(MCBSP,PCR,CLKXP,clkxp)\ + |_PER_FMK(MCBSP,PCR,CLKRP,clkrp)\ + ) + #endif + #define _MCBSP_PCR_FGET(N,FIELD)\ + _PER_FGET(_MCBSP_PCR##N##_ADDR,MCBSP,PCR,##FIELD) + + #define _MCBSP_PCR_FSET(N,FIELD,field)\ + _PER_FSET(_MCBSP_PCR##N##_ADDR,MCBSP,PCR,##FIELD,field) + + #define _MCBSP_PCR_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_MCBSP_PCR##N##_ADDR,MCBSP,PCR,##FIELD,##SYM) + + #define _MCBSP_PCR0_FGET(FIELD) _MCBSP_PCR_FGET(0,##FIELD) + #define _MCBSP_PCR1_FGET(FIELD) _MCBSP_PCR_FGET(1,##FIELD) +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_PCR2_FGET(FIELD) _MCBSP_PCR_FGET(2,##FIELD) +#endif + + #define _MCBSP_PCR0_FSET(FIELD,f) _MCBSP_PCR_FSET(0,##FIELD,f) + #define _MCBSP_PCR1_FSET(FIELD,f) _MCBSP_PCR_FSET(1,##FIELD,f) +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_PCR2_FSET(FIELD,f) _MCBSP_PCR_FSET(2,##FIELD,f) +#endif + + #define _MCBSP_PCR0_FSETS(FIELD,SYM) _MCBSP_PCR_FSETS(0,##FIELD,##SYM) + #define _MCBSP_PCR1_FSETS(FIELD,SYM) _MCBSP_PCR_FSETS(1,##FIELD,##SYM) +#if (_MCBSP_PORT_CNT==3) + #define _MCBSP_PCR2_FSETS(FIELD,SYM) _MCBSP_PCR_FSETS(2,##FIELD,##SYM) +#endif + + +/*----------------------------------------------------------------------------*/ + +#endif /* MCBSP_SUPPORT */ +#endif /* _CSL_MCBSPHAL_H_ */ +/******************************************************************************\ +* End of csl_mcbsphal.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_mdio.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_mdio.h new file mode 100644 index 0000000..58ccca7 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_mdio.h @@ -0,0 +1,144 @@ +/*****************************************************************************\ +* Copyright (C) 1999-2003 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_mdio.h +* DATE CREATED.. 02/08/2002 +* LAST MODIFIED. 05/09/2003 +*------------------------------------------------------------------------------ +* NOTE: +* When used in an multitasking environment, no MDIO function may be +* called while another MDIO function is operating on the same device +* handle in another thread. It is the responsibility of the application +* to assure adherence to this restriction. +* +* ALSO NOTE: +* When using the CSL EMAC module, the EMAC module will make use of this +* MDIO module. It is not necessary for the application to call any MDIO +* functions directly when the CSL EMAC module is in use. +* +\******************************************************************************/ +#ifndef _CSL_MDIO_H +#define _CSL_MDIO_H_ + +#include +#include +#include +#include + + +#if (MDIO_SUPPORT) +/*-----------------------------------------------------------------------*\ +* NEW TYPES +\*-----------------------------------------------------------------------*/ +#ifndef _CSL_EMAC_TYPES +#define _CSL_EMAC_TYPES +typedef unsigned int uint; +typedef void * Handle; +#endif + +/*-----------------------------------------------------------------------*\ +* MDIO Configuration Mode Flags +* +* These flags determine how the MDIO module behaves +\*-----------------------------------------------------------------------*/ +#define MDIO_MODEFLG_AUTONEG 0x0001 /* Use Autonegotiate */ +/* The following bits are used for manual and fallback configuration */ +#define MDIO_MODEFLG_HD10 0x0002 /* Use 10Mb/s Half Duplex */ +#define MDIO_MODEFLG_FD10 0x0004 /* Use 10Mb/s Full Duplex */ +#define MDIO_MODEFLG_HD100 0x0008 /* Use 100Mb/s Half Duplex */ +#define MDIO_MODEFLG_FD100 0x0010 /* Use 100Mb/s Full Duplex */ +#define MDIO_MODEFLG_LOOPBACK 0x0020 /* Use PHY Loopback */ +/* The following bits are reserved for use by the MDIO module */ +#define MDIO_MODEFLG_NWAYACTIVE 0x0040 /* NWAY is currently active */ + +/*-----------------------------------------------------------------------*\ +* MDIO Link Status Values +* +* These values indicate current PHY link status +\*-----------------------------------------------------------------------*/ +#define MDIO_LINKSTATUS_NOLINK 0 +#define MDIO_LINKSTATUS_HD10 1 +#define MDIO_LINKSTATUS_FD10 2 +#define MDIO_LINKSTATUS_HD100 3 +#define MDIO_LINKSTATUS_FD100 4 + +/*-----------------------------------------------------------------------*\ +* MDIO Events +* +* These events are returned by MDIO_timerTick() to allow the application +* (or EMAC) to track MDIO status. +\*-----------------------------------------------------------------------*/ +#define MDIO_EVENT_NOCHANGE 0 /* No change from previous status */ +#define MDIO_EVENT_LINKDOWN 1 /* Link down event */ +#define MDIO_EVENT_LINKUP 2 /* Link (or re-link) event */ +#define MDIO_EVENT_PHYERROR 3 /* No PHY connected */ + + +/*-----------------------------------------------------------------------*\ +* MDIO_open() +* +* Opens the MDIO peripheral and start searching for a PHY device. +* +* It is assumed that the MDIO module is reset prior to calling this +* function. +\*-----------------------------------------------------------------------*/ +CSLAPI Handle MDIO_open( uint mdioModeFlags ); + +/*-----------------------------------------------------------------------*\ +* MDIO_close() +* +* Close the MDIO peripheral and disable further operation. +\*-----------------------------------------------------------------------*/ +CSLAPI void MDIO_close( Handle hMDIO ); + +/*-----------------------------------------------------------------------*\ +* MDIO_getStatus() +* +* Called to get the status of the MDIO/PHY +\*-----------------------------------------------------------------------*/ +CSLAPI void MDIO_getStatus( Handle hMDIO, uint *pPhy, uint *pLinkStatus ); + +/*-----------------------------------------------------------------------*\ +* MDIO_timerTick() +* +* Called to signify that approx 100mS have elapsed +* +* Returns an MDIO event code (see MDIO Events in CSL_MDIO.H). +\*-----------------------------------------------------------------------*/ +CSLAPI uint MDIO_timerTick( Handle hMDIO ); + +/*-----------------------------------------------------------------------*\ +* MDIO_initPHY() +* +* Force a switch to the specified PHY, and start negotiation. +* +* This call is only used to override the normal PHY detection process. +* +* Returns 1 if the PHY selection completed OK, else 0 +\*-----------------------------------------------------------------------*/ +CSLAPI uint MDIO_initPHY( Handle hMDIO, uint phyAddr ); + +/*-----------------------------------------------------------------------*\ +* MDIO_phyRegRead() +* +* Raw data read of a PHY register. +* +* Returns 1 if the PHY ACK'd the read, else 0 +\*-----------------------------------------------------------------------*/ +CSLAPI uint MDIO_phyRegRead( uint phyIdx, uint phyReg, Uint16 *pData ); + +/*-----------------------------------------------------------------------*\ +* MDIO_phyRegWrite() +* +* Raw data write of a PHY register. +* +* Returns 1 if the PHY ACK'd the write, else 0 +\*-----------------------------------------------------------------------*/ +CSLAPI uint MDIO_phyRegWrite( uint phyIdx, uint phyReg, Uint16 data ); + +#endif /* MDIO_SUPPORT */ +#endif /* _CSL_MDIO_H_ */ +/******************************************************************************\ +* End of mdio.h +\******************************************************************************/ diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_mdiohal.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_mdiohal.h new file mode 100644 index 0000000..aab95d5 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_mdiohal.h @@ -0,0 +1,524 @@ +/*****************************************************************************\ +* Copyright (C) 1999-2003 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_mdiohal.h +* DATE CREATED.. 02/08/2002 +* LAST MODIFIED. 03/05/2003 +*------------------------------------------------------------------------------ +* REGISTERS/PARAMETERS +* +* VERSION - Module Version Register +* CONTROL - Module Control Register +* ALIVE - PHY "Alive" Indication Register +* LINK - PHY Link Status Register +* LINKINTRAW - Link Status Change Interrupt Register +* LINKINTMASKED - Link Status Change Interrupt Register (Masked) +* USERINTRAW - User Command Complete Interrupt +* USERINTMASKED - User Command Complete Interrupt (Masked) +* USERINTMASKSET - Enable User Command Complete Interrupt Mask +* USERINTMASKCLEAR - Disable User Command Complete Interrupt Mask +* USERACCESS0 - User Access Register 0 +* USERPHYSEL0 - User PHY Select Register 0 +* USERACCESS1 - User Access Register 1 +* USERPHYSEL1 - User PHY Select Register 1 +* +*\******************************************************************************/ +#ifndef _CSL_MDIOHAL_H +#define _CSL_MDIOHAL_H_ + +#include +#include + +#if (MDIO_SUPPORT) + +/******************************************************************************\ +* MDIO Register section +\******************************************************************************/ + +#define _MDIO_BASE_ADDR 0x01c83800u + + +/******************************************************************************\ +* module level register/field access macros +\******************************************************************************/ + +/* ----------------- */ +/* FIELD MAKE MACROS */ +/* ----------------- */ + +// User Supplied Value +#define MDIO_FMK(REG,FIELD,x)\ + ((x<<_MDIO_##REG##_##FIELD##_SHIFT)&_MDIO_##REG##_##FIELD##_MASK) + +// Symbolic Value Name +#define MDIO_FMKS(REG,FIELD,SYM)\ + ((MDIO_##REG##_##FIELD##_##SYM<<_MDIO_##REG##_##FIELD##_SHIFT)\ + &_MDIO_##REG##_##FIELD##_MASK) + +// MAC Index Flag Flag +#define MDIO_FMKMIF(MACINDEX) (1u<<(MACINDEX)) + + +/* -------------------------------- */ +/* RAW REGISTER/FIELD ACCESS MACROS */ +/* -------------------------------- */ + +#define MDIO_ADDR(REG)\ + _MDIO_##REG##_ADDR + +#define MDIO_REG(REG)\ + *(volatile Uint32*)(_MDIO_##REG##_ADDR) + +// Standard Registers +#define MDIO_RGET(REG)\ + (*(volatile Uint32*)(_MDIO_##REG##_ADDR)) + +#define MDIO_RSET(REG,x)\ + (*(volatile Uint32*)(_MDIO_##REG##_ADDR)=(x)) + +#define MDIO_FGET(REG,FIELD)\ + ((MDIO_RGET(REG)&_MDIO_##REG##_##FIELD##_MASK)\ + >>_MDIO_##REG##_##FIELD##_SHIFT) + +#define MDIO_FSET(REG,FIELD,x)\ + MDIO_RSET(REG,(MDIO_RGET(REG)&~_MDIO_##REG##_##FIELD##_MASK)|\ + MDIO_FMK(REG,FIELD,x)) + +#define MDIO_FSETS(REG,FIELD,SYM)\ + MDIO_RSET(REG,(MDIO_RGET(REG)&~_MDIO_##REG##_##FIELD##_MASK)|\ + MDIO_FMKS(REG,FIELD,SYM)) + + + +/******************************************************************************\ +* _____________________ +* | | +* | VERSION | +* |___________________| +* +* TXIDVER - TX Identification and Version Register +* +* FIELDS (msb -> lsb) +* (r) MODID - Module Id +* (r) REVMAJ - Major Revision +* (r) REVMIN - Minor Revision +* +* MACROS SUPPORTED +* MDIO_FMK y +* MDIO_FMKS . +* MDIO_FMKMIF . +* MDIO_ADDR y +* MDIO_REG y +* MDIO_RGET y +* MDIO_RSET y +* MDIO_FGET y +* MDIO_FSET y +* MDIO_FSETS . +* +\******************************************************************************/ +#define _MDIO_VERSION_ADDR (_MDIO_BASE_ADDR+0x0000u) + +#define MDIO_VERSION MDIO_REG(VERSION) + +#define _MDIO_VERSION_MODID_MASK 0xFFFF0000u +#define _MDIO_VERSION_MODID_SHIFT 16u +#define MDIO_VERSION_MODID_DEFAULT 0x00000007u + +#define _MDIO_VERSION_REVMAJ_MASK 0x0000FF00u +#define _MDIO_VERSION_REVMAJ_SHIFT 8u +#define MDIO_VERSION_REVMAJ_DEFAULT 0x00000000u + +#define _MDIO_VERSION_REVMIN_MASK 0x000000FFu +#define _MDIO_VERSION_REVMIN_SHIFT 0u +#define MDIO_VERSION_REVMIN_DEFAULT 0x00000000u + + + +/******************************************************************************\ +* _____________________ +* | | +* | CONTROL | +* |___________________| +* +* CONTROL - MDIO Control Register +* +* FIELDS (msb -> lsb) +* (r) IDLE - MDIO State Machine Idle +* (rw) ENABLE - Enable Control +* (rw) PREAMBLE - Preamble Disable +* (rwc) FAULT - Fault Indicator +* (rw) FAULTENB - Fault Detect Enable +* (rw) INTTESTENB - Link Test Enable +* (rw) CLKDIV - Clock Divider +* +* +* MACROS SUPPORTED +* MDIO_FMK y +* MDIO_FMKS y +* MDIO_FMKMIF . +* MDIO_ADDR y +* MDIO_REG y +* MDIO_RGET y +* MDIO_RSET y +* MDIO_FGET y +* MDIO_FSET y +* MDIO_FSETS y +* +\******************************************************************************/ +#define _MDIO_CONTROL_ADDR (_MDIO_BASE_ADDR+0x0004u) + +#define MDIO_CONTROL MDIO_REG(TXCONTROL) + +#define _MDIO_CONTROL_IDLE_MASK 0x80000000u +#define _MDIO_CONTROL_IDLE_SHIFT 31u +#define MDIO_CONTROL_IDLE_DEFAULT 0x00000001u +#define MDIO_CONTROL_IDLE_YES 1u +#define MDIO_CONTROL_IDLE_NO 0u + +#define _MDIO_CONTROL_ENABLE_MASK 0x40000000u +#define _MDIO_CONTROL_ENABLE_SHIFT 30u +#define MDIO_CONTROL_ENABLE_DEFAULT 0x00000000u +#define MDIO_CONTROL_ENABLE_YES 1u +#define MDIO_CONTROL_ENABLE_NO 0u + +#define _MDIO_CONTROL_PREAMBLE_MASK 0x00100000u +#define _MDIO_CONTROL_PREAMBLE_SHIFT 20u +#define MDIO_CONTROL_PREAMBLE_DEFAULT 0x00000000u +#define MDIO_CONTROL_PREAMBLE_DISABLED 1u +#define MDIO_CONTROL_PREAMBLE_ENABLED 0u + +#define _MDIO_CONTROL_FAULT_MASK 0x00080000u +#define _MDIO_CONTROL_FAULT_SHIFT 19u +#define MDIO_CONTROL_FAULT_DEFAULT 0x00000000u +#define MDIO_CONTROL_FAULT_YES 1u +#define MDIO_CONTROL_FAULT_NO 0u + +#define _MDIO_CONTROL_FAULTENB_MASK 0x00040000u +#define _MDIO_CONTROL_FAULTENB_SHIFT 18u +#define MDIO_CONTROL_FAULTENB_DEFAULT 0x00000000u +#define MDIO_CONTROL_FAULTENB_YES 1u +#define MDIO_CONTROL_FAULTENB_NO 0u + +#define _MDIO_CONTROL_INTTESTENB_MASK 0x00020000u +#define _MDIO_CONTROL_INTTESTENB_SHIFT 17u +#define MDIO_CONTROL_INTTESTENB_DEFAULT 0x00000000u +#define MDIO_CONTROL_INTTESTENB_YES 1u +#define MDIO_CONTROL_INTTESTENB_NO 0u + +#define _MDIO_CONTROL_CLKDIV_MASK 0x000000FFu +#define _MDIO_CONTROL_CLKDIV_SHIFT 0u +#define MDIO_CONTROL_CLKDIV_DEFAULT 0x000000FFu + + + +/******************************************************************************\ +* _____________________ +* | | +* | ALIVE | +* | LINK | +* |___________________| +* +* ALIVE - PHY "Alive" Indication Register +* LINK - PHY Link Status Register +* +* FIELDS (msb -> lsb) +* PHY Index Flags (0-31) (use MDIO_FMKMIF) +* +* MACROS SUPPORTED +* MDIO_FMK . +* MDIO_FMKS . +* MDIO_FMKMIF y +* MDIO_ADDR y +* MDIO_REG y +* MDIO_RGET y +* MDIO_RSET y +* MDIO_FGET . +* MDIO_FSET . +* MDIO_FSETS . +* +\******************************************************************************/ +#define _MDIO_ALIVE_ADDR (_MDIO_BASE_ADDR+0x0008u) +#define _MDIO_LINK_ADDR (_MDIO_BASE_ADDR+0x000Cu) + +#define MDIO_ALIVE MDIO_REG(ALIVE) +#define MDIO_LINK MDIO_REG(LINK) + + + +/******************************************************************************\ +* _____________________ +* | | +* | LINKINTRAW | +* | LINKINTMASKED | +* | USERINTRAW | +* | USERINTMASKED | +* | USERINTMASKSET | +* | USERINTMASKCLEAR | +* |___________________| +* +* LINKINTRAW - Link Status Change Interrupt Register +* LINKINTMASKED - Link Status Change Interrupt Register (Masked) +* USERINTRAW - User Command Complete Interrupt +* USERINTMASKED - User Command Complete Interrupt (Masked) +* USERINTMASKSET - Enable User Command Complete Interrupt Mask +* USERINTMASKCLEAR - Disable User Command Complete Interrupt Mask +* +* FIELDS (msb -> lsb) +* MAC0 - Mac 0 Flag (yes/no) +* MAC1 - Mac 1 Flag (yes/no) +* +* MACROS SUPPORTED +* MDIO_FMK y +* MDIO_FMKS y +* MDIO_FMKMIF . +* MDIO_ADDR y +* MDIO_REG y +* MDIO_RGET y +* MDIO_RSET y +* MDIO_FGET y +* MDIO_FSET y +* MDIO_FSETS . +* +\******************************************************************************/ +#define _MDIO_LINKINTRAW_ADDR (_MDIO_BASE_ADDR+0x0010u) +#define _MDIO_LINKINTMASKED_ADDR (_MDIO_BASE_ADDR+0x0014u) +#define _MDIO_USERINTRAW_ADDR (_MDIO_BASE_ADDR+0x0020u) +#define _MDIO_USERINTMASKED_ADDR (_MDIO_BASE_ADDR+0x0024u) +#define _MDIO_USERINTMASKSET_ADDR (_MDIO_BASE_ADDR+0x0028u) +#define _MDIO_USERINTMASKCLEAR_ADDR (_MDIO_BASE_ADDR+0x002Cu) + +#define MDIO_LINKINTRAW MDIO_REG(LINKINT) +#define MDIO_LINKINTMASKED MDIO_REG(LINKINTMASKED) +#define MDIO_USERINTRAW MDIO_REG(USERINTRAW) +#define MDIO_USERINTMASKED MDIO_REG(USERINTMASKED) +#define MDIO_USERINTMASKSET MDIO_REG(USERINTMASKSET) +#define MDIO_USERINTMASKCLEAR MDIO_REG(USERINTMASKCLEAR) + +#define _MDIO_LINKINTRAW_MAC0_MASK 0x00000001u +#define _MDIO_LINKINTRAW_MAC0_SHIFT 0u +#define MDIO_LINKINTRAW_MAC0_DEFAULT 0x00000000u +#define _MDIO_LINKINTRAW_MAC1_MASK 0x00000002u +#define _MDIO_LINKINTRAW_MAC1_SHIFT 1u +#define MDIO_LINKINTRAW_MAC1_DEFAULT 0x00000000u + +#define MDIO_LINKINTRAW_MAC0_YES 1u +#define MDIO_LINKINTRAW_MAC0_NO 0u +#define MDIO_LINKINTRAW_MAC1_YES 1u +#define MDIO_LINKINTRAW_MAC1_NO 0u + +#define _MDIO_LINKINTMASKED_MAC0_MASK 0x00000001u +#define _MDIO_LINKINTMASKED_MAC0_SHIFT 0u +#define MDIO_LINKINTMASKED_MAC0_DEFAULT 0x00000000u +#define _MDIO_LINKINTMASKED_MAC1_MASK 0x00000002u +#define _MDIO_LINKINTMASKED_MAC1_SHIFT 1u +#define MDIO_LINKINTMASKED_MAC1_DEFAULT 0x00000000u + +#define MDIO_LINKINTMASKED_MAC0_YES 1u +#define MDIO_LINKINTMASKED_MAC0_NO 0u +#define MDIO_LINKINTMASKED_MAC1_YES 1u +#define MDIO_LINKINTMASKED_MAC1_NO 0u + +#define _MDIO_USERINTRAW_MAC0_MASK 0x00000001u +#define _MDIO_USERINTRAW_MAC0_SHIFT 0u +#define MDIO_USERINTRAW_MAC0_DEFAULT 0x00000000u +#define _MDIO_USERINTRAW_MAC1_MASK 0x00000002u +#define _MDIO_USERINTRAW_MAC1_SHIFT 1u +#define MDIO_USERINTRAW_MAC1_DEFAULT 0x00000000u + +#define MDIO_USERINTRAW_MAC0_YES 1u +#define MDIO_USERINTRAW_MAC0_NO 0u +#define MDIO_USERINTRAW_MAC1_YES 1u +#define MDIO_USERINTRAW_MAC1_NO 0u + +#define _MDIO_USERINTMASKED_MAC0_MASK 0x00000001u +#define _MDIO_USERINTMASKED_MAC0_SHIFT 0u +#define MDIO_USERINTMASKED_MAC0_DEFAULT 0x00000000u +#define _MDIO_USERINTMASKED_MAC1_MASK 0x00000002u +#define _MDIO_USERINTMASKED_MAC1_SHIFT 1u +#define MDIO_USERINTMASKED_MAC1_DEFAULT 0x00000000u + +#define MDIO_USERINTMASKED_MAC0_YES 1u +#define MDIO_USERINTMASKED_MAC0_NO 0u +#define MDIO_USERINTMASKED_MAC1_YES 1u +#define MDIO_USERINTMASKED_MAC1_NO 0u + +#define _MDIO_USERINTMASKSET_MAC0_MASK 0x00000001u +#define _MDIO_USERINTMASKSET_MAC0_SHIFT 0u +#define MDIO_USERINTMASKSET_MAC0_DEFAULT 0x00000000u +#define _MDIO_USERINTMASKSET_MAC1_MASK 0x00000002u +#define _MDIO_USERINTMASKSET_MAC1_SHIFT 1u +#define MDIO_USERINTMASKSET_MAC1_DEFAULT 0x00000000u + +#define MDIO_USERINTMASKSET_MAC0_YES 1u +#define MDIO_USERINTMASKSET_MAC0_NO 0u +#define MDIO_USERINTMASKSET_MAC1_YES 1u +#define MDIO_USERINTMASKSET_MAC1_NO 0u + +#define _MDIO_USERINTMASKCLEAR_MAC0_MASK 0x00000001u +#define _MDIO_USERINTMASKCLEAR_MAC0_SHIFT 0u +#define MDIO_USERINTMASKCLEAR_MAC0_DEFAULT 0x00000000u +#define _MDIO_USERINTMASKCLEAR_MAC1_MASK 0x00000002u +#define _MDIO_USERINTMASKCLEAR_MAC1_SHIFT 1u +#define MDIO_USERINTMASKCLEAR_MAC1_DEFAULT 0x00000000u + +#define MDIO_USERINTMASKCLEAR_MAC0_YES 1u +#define MDIO_USERINTMASKCLEAR_MAC0_NO 0u +#define MDIO_USERINTMASKCLEAR_MAC1_YES 1u +#define MDIO_USERINTMASKCLEAR_MAC1_NO 0u + + + +/******************************************************************************\ +* _____________________ +* | | +* | USERACCESS0 | +* | USERACCESS1 | +* |___________________| +* +* USERACCESS0 - User Access Register 0 +* USERACCESS1 - User Access Register 1 +* +* FIELDS (msb -> lsb) +* (rws) GO - Go Bit +* (rw) WRITE - Write Enable +* (r) ACK - Acknowledge +* (rw) REGADR - PHY Register Address +* (rw) PHYADR - PHY Device Address +* (rw) DATA - User Data to Read/Write +* +* MACROS SUPPORTED +* MDIO_FMK y +* MDIO_FMKS . +* MDIO_FMKMIF . +* MDIO_ADDR y +* MDIO_REG y +* MDIO_RGET y +* MDIO_RSET y +* MDIO_FGET y +* MDIO_FSET y +* MDIO_FSETS . +* +\******************************************************************************/ +#define _MDIO_USERACCESS0_ADDR (_MDIO_BASE_ADDR+0x0080u) +#define _MDIO_USERACCESS1_ADDR (_MDIO_BASE_ADDR+0x0088u) + +#define MDIO_USERACCESS0 MDIO_REG(USERACCESS0) +#define MDIO_USERACCESS1 MDIO_REG(USERACCESS1) + +#define _MDIO_USERACCESS0_GO_MASK 0x80000000u +#define _MDIO_USERACCESS0_GO_SHIFT 31u +#define MDIO_USERACCESS0_GO_DEFAULT 0x00000000u +#define _MDIO_USERACCESS0_WRITE_MASK 0x40000000u +#define _MDIO_USERACCESS0_WRITE_SHIFT 30u +#define MDIO_USERACCESS0_WRITE_DEFAULT 0x00000000u +#define _MDIO_USERACCESS0_ACK_MASK 0x20000000u +#define _MDIO_USERACCESS0_ACK_SHIFT 29u +#define MDIO_USERACCESS0_ACK_DEFAULT 0x00000000u +#define _MDIO_USERACCESS0_REGADR_MASK 0x03E00000u +#define _MDIO_USERACCESS0_REGADR_SHIFT 21u +#define MDIO_USERACCESS0_REGADR_DEFAULT 0x00000000u +#define _MDIO_USERACCESS0_PHYADR_MASK 0x001F0000u +#define _MDIO_USERACCESS0_PHYADR_SHIFT 16u +#define MDIO_USERACCESS0_PHYADR_DEFAULT 0x00000000u +#define _MDIO_USERACCESS0_DATA_MASK 0x0000FFFFu +#define _MDIO_USERACCESS0_DATA_SHIFT 0u +#define MDIO_USERACCESS0_DATA_DEFAULT 0x00000000u + +#define _MDIO_USERACCESS1_GO_MASK 0x80000000u +#define _MDIO_USERACCESS1_GO_SHIFT 31u +#define MDIO_USERACCESS1_GO_DEFAULT 0x00000000u +#define _MDIO_USERACCESS1_WRITE_MASK 0x40000000u +#define _MDIO_USERACCESS1_WRITE_SHIFT 30u +#define MDIO_USERACCESS1_WRITE_DEFAULT 0x00000000u +#define _MDIO_USERACCESS1_ACK_MASK 0x20000000u +#define _MDIO_USERACCESS1_ACK_SHIFT 29u +#define MDIO_USERACCESS1_ACK_DEFAULT 0x00000000u +#define _MDIO_USERACCESS1_REGADR_MASK 0x03E00000u +#define _MDIO_USERACCESS1_REGADR_SHIFT 21u +#define MDIO_USERACCESS1_REGADR_DEFAULT 0x00000000u +#define _MDIO_USERACCESS1_PHYADR_MASK 0x001F0000u +#define _MDIO_USERACCESS1_PHYADR_SHIFT 16u +#define MDIO_USERACCESS1_PHYADR_DEFAULT 0x00000000u +#define _MDIO_USERACCESS1_DATA_MASK 0x0000FFFFu +#define _MDIO_USERACCESS1_DATA_SHIFT 0u +#define MDIO_USERACCESS1_DATA_DEFAULT 0x00000000u + + +/******************************************************************************\ +* _____________________ +* | | +* | USERPHYSEL0 | +* | USERPHYSEL1 | +* |___________________| +* +* USERPHYSEL0 - User PHY Select Register 0 +* USERPHYSEL1 - User PHY Select Register 1 +* +* FIELDS (msb -> lsb) +* (rw) LINKSEL - Link Detect Type Selection +* (rw) LINKINTENB - Link Interrupt Enable +* (rw) PHYADDR - Address (0-31) of Phy to Use +* +* MACROS SUPPORTED +* MDIO_FMK y +* MDIO_FMKS y +* MDIO_FMKMIF . +* MDIO_ADDR y +* MDIO_REG y +* MDIO_RGET y +* MDIO_RSET y +* MDIO_FGET y +* MDIO_FSET y +* MDIO_FSETS y +* +\******************************************************************************/ +#define _MDIO_USERPHYSEL0_ADDR (_MDIO_BASE_ADDR+0x0084u) +#define _MDIO_USERPHYSEL1_ADDR (_MDIO_BASE_ADDR+0x008Cu) + +#define MDIO_USERPHYSEL0 MDIO_REG(USERPHYSEL0) +#define MDIO_USERPHYSEL1 MDIO_REG(USERPHYSEL1) + +#define _MDIO_USERPHYSEL0_LINKSEL_MASK 0x00000080u +#define _MDIO_USERPHYSEL0_LINKSEL_SHIFT 7u +#define MDIO_USERPHYSEL0_LINKSEL_DEFAULT 0x00000000u +#define MDIO_USERPHYSEL0_LINKSEL_MLINK 1u +#define MDIO_USERPHYSEL0_LINKSEL_MDIO 0u + +#define _MDIO_USERPHYSEL0_LINKINTENB_MASK 0x00000040u +#define _MDIO_USERPHYSEL0_LINKINTENB_SHIFT 6u +#define MDIO_USERPHYSEL0_LINKINTENB_DEFAULT 0x00000000u +#define MDIO_USERPHYSEL0_LINKINTENB_ENABLE 1u +#define MDIO_USERPHYSEL0_LINKINTENB_DISABLE 0u + +#define _MDIO_USERPHYSEL0_PHYADDR_MASK 0x0000001Fu +#define _MDIO_USERPHYSEL0_PHYADDR_SHIFT 0u +#define MDIO_USERPHYSEL0_PHYADDR_DEFAULT 0x00000000u + +#define _MDIO_USERPHYSEL1_LINKSEL_MASK 0x00000080u +#define _MDIO_USERPHYSEL1_LINKSEL_SHIFT 7u +#define MDIO_USERPHYSEL1_LINKSEL_DEFAULT 0x00000000u +#define MDIO_USERPHYSEL1_LINKSEL_MLINK 1u +#define MDIO_USERPHYSEL1_LINKSEL_MDIO 0u + +#define _MDIO_USERPHYSEL1_LINKINTENB_MASK 0x00000040u +#define _MDIO_USERPHYSEL1_LINKINTENB_SHIFT 6u +#define MDIO_USERPHYSEL1_LINKINTENB_DEFAULT 0x00000000u +#define MDIO_USERPHYSEL1_LINKINTENB_ENABLE 1u +#define MDIO_USERPHYSEL1_LINKINTENB_DISABLE 0u + +#define _MDIO_USERPHYSEL1_PHYADDR_MASK 0x0000001Fu +#define _MDIO_USERPHYSEL1_PHYADDR_SHIFT 0u +#define MDIO_USERPHYSEL1_PHYADDR_DEFAULT 0x00000000u + + +#endif /* MDIO_SUPPORT */ + +#endif /* _CSL_MDIOHAL_H_ */ +/******************************************************************************\ +* End of csl_mdiohal.h +\******************************************************************************/ + + + + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_pci.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_pci.h new file mode 100644 index 0000000..0d8f0e1 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_pci.h @@ -0,0 +1,414 @@ +/******************************************************************************\ +* Copyright (C) 2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_pci.h +* DATE CREATED.. Mon 06/12/2000 +* LAST MODIFIED. 02/12/2002 PCI_intClear() +* 04/20/2001 (C64x compatibility) +* 06/20/2003 TRCTL enhancement +* +\******************************************************************************/ +#ifndef _CSL_PCI_H_ +#define _CSL_PCI_H_ + +#include +#include +#include +#include + +#if (PCI_SUPPORT) +/****************************************\ +* PCI scope and inline control macros +\****************************************/ +#ifdef __cplusplus +#define CSLAPI extern "C" far +#else +#define CSLAPI extern far +#endif + +#undef USEDEFS +#undef IDECL +#undef IDEF + +#ifdef _PCI_MOD_ + #define IDECL extern far + #define USEDEFS + #define IDEF +#else + #ifdef _INLINE + #define IDECL static inline + #define USEDEFS + #define IDEF static inline + #else + #define IDECL extern far + #endif +#endif + +/****************************************\ +* PCI global macro declarations +\****************************************/ +#define PCI_EVENT_CNT 11 + +/* eventPci definitions */ +#define PCI_EVT_DMAHALTED 12 +#define PCI_EVT_PRST 11 +#define PCI_EVT_EERDY 9 +#define PCI_EVT_CFGERR 8 +#define PCI_EVT_CFGDONE 7 +#define PCI_EVT_MASTEROK 6 +#define PCI_EVT_PWRHL 5 +#define PCI_EVT_PWRLH 4 +#define PCI_EVT_HOSTSW 3 +#define PCI_EVT_PCIMASTER 2 +#define PCI_EVT_PCITARGET 1 +#define PCI_EVT_PWRMGMT 0 + + +/* mode StarttXfr definitions */ +#define PCI_WRITE 0x1u +#define PCI_READ_PREF 0x2u +#define PCI_READ_NOPREF 0x3u + +/* EEPROM sizes */ + #define PCI_EEPROM_NONE 0x00000000u + #define PCI_EEPROM_4K 0x00000011u +#if (!C64_SUPPORT) + #define PCI_EEPROM_1K 0x00000001u + #define PCI_EEPROM_2K 0x00000010u + #define PCI_EEPROM_16K 0x00000100u +#endif + +/****************************************\ +* PCI global typedef declarations +\****************************************/ +#if(!C64_SUPPORT) +typedef struct { + Uint32 dspma; + Uint32 pcima; + Uint32 pcimc; +} PCI_ConfigXfr; +#else +typedef struct { + Uint32 dspma; + Uint32 pcima; + Uint32 pcimc; + Uint32 trctl; +} PCI_ConfigXfr; +#endif + +/****************************************\ +* PCI global variable declarations +\****************************************/ +extern far Uint32 _PCI_maskTable[13]; + + + +/*_PCI_maskTable[PCI_EVT_PWRMGMT]= _PCI_PCIIEN_PWRMGMT_MASK; +_PCI_maskTable[PCI_EVT_PCITARGET]= _PCI_PCIIEN_PCITARGET_MASK; +_PCI_maskTable[PCI_EVT_PCIMASTER]= _PCI_PCIIEN_PCIMASTER_MASK; +_PCI_maskTable[PCI_EVT_HOSTSW]= _PCI_PCIIEN_PWRLH_MASK; +_PCI_maskTable[PCI_EVT_PWRLH]= _PCI_PCIIEN_PWRLH_MASK; +_PCI_maskTable[PCI_EVT_PWRHL]= _PCI_PCIIEN_PWRHL_MASK; +_PCI_maskTable[PCI_EVT_MASTEROK]= _PCI_PCIIEN_MASTEROK_MASK; +_PCI_maskTable[PCI_EVT_CFGDONE]= _PCI_PCIIEN_CFGDONE_MASK; +_PCI_maskTable[PCI_EVT_CFGERR]= _PCI_PCIIEN_CFGERR_MASK; +_PCI_maskTable[PCI_EVT_EERDY]= _PCI_PCIIEN_EERDY_MASK; +_PCI_maskTable[PCI_EVT_PRST]= _PCI_PCIIEN_PRST_MASK; +_PCI_maskTable[PCI_EVT_DMAHALTED]= _PCI_PCIIS_DMAHALTED_MASK; + */ + +/****************************************\ +* PCI global function declarations +\****************************************/ +extern far Uint32 _PCI_eepromEnableWrite(); +extern far Uint32 PCI_eepromWrite(Uint32 eeaddr,Uint16 eedata); +extern far Uint32 PCI_eepromWriteAll(Uint16 eedata); +extern far Uint16 PCI_eepromRead(Uint32 eeaddr); +extern far Uint32 PCI_eepromErase(Uint32 eeaddr); +extern far Uint32 PCI_eepromEraseAll(); +/****************************************\ +* PCI inline function declarations +\****************************************/ + +/* Master transfer functions */ +IDECL void PCI_xfrStart(Uint32 modeXfr); +IDECL void PCI_xfrFlush(); // Field START=00 - flush current Transaction +IDECL int PCI_xfrTest(); // test if the transfer is done - wait the Start field back to 00 */ +IDECL void PCI_xfrByteCntSet(Uint16 nbbyte); // set field CNT - # of bytes to be transfered + +/* Halt function (HALT register ) */ +#if (!C64_SUPPORT) +IDECL void PCI_xfrHalt(); +IDECL void PCI_xfrEnable(); +#endif + + +IDECL Uint32 PCI_curDspAddrGet(); +IDECL Uint32 PCI_curPciAddrGet(); +IDECL Uint32 PCI_curByteCntGet(); +#if(!C64_SUPPORT) +IDECL void PCI_xfrConfig(PCI_ConfigXfr *config); +IDECL void PCI_xfrConfigArgs(Uint32 dspma, Uint32 pcima, Uint32 pcimc); +IDECL void PCI_xfrGetConfig(PCI_ConfigXfr *config); +#else +IDECL void PCI_xfrConfig(PCI_ConfigXfr *config); +IDECL void PCI_xfrConfigArgs(Uint32 dspma, Uint32 pcima, Uint32 pcimc , Uint32 trctl); +IDECL void PCI_xfrGetConfig(PCI_ConfigXfr *config); +#endif +/* PCI Interrupt Enable/Reporting functions */ +IDECL void PCI_intEnable(Uint32 eventPci); +IDECL void PCI_intDisable(Uint32 eventPci); +IDECL Uint32 PCI_intTest(Uint32 eventPci); +IDECL void PCI_intClear(Uint32 eventPci); + +IDECL void PCI_dspIntReqSet(); +IDECL void PCI_dspIntReqClear(); + +/* DSP EEPROM interface functions */ +IDECL Uint32 PCI_eepromSize(); /* reads fieds EESZ of EECTL reg */ +IDECL Uint32 PCI_eepromTest(); /* returns success if EESZ != 0 - EEPROM present */ +IDECL Uint32 PCI_eepromIsAutoCfg(); /* reads the EEAI bit status of EECTL- AutoCfgEnable */ + +/* Power Management functions */ +#if (!C64_SUPPORT) +IDECL void PCI_pwrStatUpdate(); +IDECL Uint32 PCI_pwrStatTest(); +#endif + + +/****************************************\ +* PCI inline function definitions +\****************************************/ +#ifdef USEDEFS +/*----------------------------------------------------------------------------*/ +IDEF void PCI_xfrStart(Uint32 modeXfr) { + PCI_FSET(PCIMC,START,modeXfr) ; +} +/*----------------------------------------------------------------------------*/ +#if (!C64_SUPPORT) +IDEF void PCI_xfrHalt(){ + PCI_FSET(HALT,HALT,1); +} +/*----------------------------------------------------------------------------*/ +IDEF void PCI_xfrEnable(){ + PCI_FSET(HALT,HALT,0); +} +#endif /* !C64_SUPPORT */ +/*----------------------------------------------------------------------------*/ +IDEF void PCI_xfrFlush(){ + PCI_FSET(PCIMC,START,0); +} +/*----------------------------------------------------------------------------*/ +IDEF int PCI_xfrTest(){ + return PCI_FGET(PCIMC,START); +} +/*----------------------------------------------------------------------------*/ +IDEF void PCI_xfrByteCntSet(Uint16 nbbyte){ + PCI_FSET(PCIMC,CNT,nbbyte); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 PCI_curDspAddrGet() { + return PCI_FGET(CDSPA,CDSPA); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 PCI_curPciAddrGet() { + return PCI_FGET(CPCIA,CPCIA); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 PCI_curByteCntGet() { + return PCI_FGET(CCNT,CCNT); +} +/*----------------------------------------------------------------------------*/ +#if(!C64_SUPPORT) +IDEF void PCI_xfrConfig(PCI_ConfigXfr *config) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *) _PCI_BASE1_GLOBAL; + register int x0,x1,x2; + + gie = IRQ_globalDisable(); + + x0 = config->dspma; + x1 = config->pcima; + x2 = config->pcimc; + + base[_PCI_PCIMC_OFFSET] = 0x00000000; + base[_PCI_DSPMA_OFFSET] = x0; + base[_PCI_PCIMA_OFFSET] = x1; + base[_PCI_PCIMC_OFFSET] = x2; + + IRQ_globalRestore(gie); +} +/*----------------------------------------------------------------------------*/ +IDEF void PCI_xfrConfigArgs(Uint32 dspma,Uint32 pcima,Uint32 pcimc) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *) _PCI_BASE1_GLOBAL; + + gie = IRQ_globalDisable(); + + base[_PCI_PCIMC_OFFSET] = 0x00000000u; + base[_PCI_DSPMA_OFFSET] = dspma; + base[_PCI_PCIMA_OFFSET] = pcima; + base[_PCI_PCIMC_OFFSET] = pcimc; + + IRQ_globalRestore(gie); +} + +/*----------------------------------------------------------------------------*/ +IDEF void PCI_xfrGetConfig(PCI_ConfigXfr *config) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *) _PCI_BASE1_GLOBAL; + volatile PCI_ConfigXfr *cfg = (volatile PCI_ConfigXfr*)config; + register int x0,x1,x2; + + gie = IRQ_globalDisable(); + + x0 = base[_PCI_DSPMA_OFFSET]; + x1 = base[_PCI_PCIMA_OFFSET]; + x2 = base[_PCI_PCIMC_OFFSET]; + + cfg->dspma = x0; + cfg->pcima = x1; + cfg->pcimc = x2; + + IRQ_globalRestore(gie); +} +#else +IDEF void PCI_xfrConfig(PCI_ConfigXfr *config) { + + Uint32 gie; + volatile Uint32 *base1 = (volatile Uint32 *) _PCI_BASE1_GLOBAL; + volatile Uint32 *base2 = (volatile Uint32 *) _PCI_BASE3_GLOBAL; + + register int x0,x1,x2,x3; + + gie = IRQ_globalDisable(); + + x0 = config->dspma; + x1 = config->pcima; + x2 = config->pcimc; + x3 = config->trctl; + + base1[_PCI_PCIMC_OFFSET] = 0x00000000; + base1[_PCI_DSPMA_OFFSET] = x0; + base1[_PCI_PCIMA_OFFSET] = x1; + base1[_PCI_PCIMC_OFFSET] = x2; + base2[_PCI_TRCTL_OFFSET] = x3; + + + IRQ_globalRestore(gie); +} +/*----------------------------------------------------------------------------*/ +IDEF void PCI_xfrConfigArgs(Uint32 dspma,Uint32 pcima,Uint32 pcimc,Uint32 trctl) { + + Uint32 gie; + volatile Uint32 *base1 = (volatile Uint32 *) _PCI_BASE1_GLOBAL; + volatile Uint32 *base2 = (volatile Uint32 *) _PCI_BASE3_GLOBAL; + + gie = IRQ_globalDisable(); + + base1[_PCI_PCIMC_OFFSET] = 0x00000000u; + base1[_PCI_DSPMA_OFFSET] = dspma; + base1[_PCI_PCIMA_OFFSET] = pcima; + base1[_PCI_PCIMC_OFFSET] = pcimc; + base2[_PCI_TRCTL_OFFSET] = trctl; + + IRQ_globalRestore(gie); +} + +/*----------------------------------------------------------------------------*/ +IDEF void PCI_xfrGetConfig(PCI_ConfigXfr *config) { + + Uint32 gie; + volatile Uint32 *base1 = (volatile Uint32 *) _PCI_BASE1_GLOBAL; + volatile Uint32 *base2 = (volatile Uint32 *) _PCI_BASE3_GLOBAL; + volatile PCI_ConfigXfr *cfg = (volatile PCI_ConfigXfr*)config; + register int x0,x1,x2,x3; + + gie = IRQ_globalDisable(); + + x0 = base1[_PCI_DSPMA_OFFSET]; + x1 = base1[_PCI_PCIMA_OFFSET]; + x2 = base1[_PCI_PCIMC_OFFSET]; + x3 = base2[_PCI_TRCTL_OFFSET]; + + cfg->dspma = x0; + cfg->pcima = x1; + cfg->pcimc = x2; + cfg->trctl = x3; + + IRQ_globalRestore(gie); +} +#endif +/*----------------------------------------------------------------------------*/ +IDEF void PCI_intEnable(Uint32 eventPci) { + volatile Uint32 value ; + value= PCI_RGET(PCIIEN); + /* Set bit of eventPCi */ + PCI_RSET(PCIIEN,(value | _PCI_maskTable[eventPci])); +} +/*----------------------------------------------------------------------------*/ +IDEF void PCI_intDisable(Uint32 eventPci) { + volatile Uint32 value; + value =( PCI_RGET(PCIIEN) &= ~_PCI_maskTable[eventPci]); /* Set the opposite mask of eventPci */ + PCI_RSET(PCIIEN,value); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 PCI_intTest(Uint32 eventPci) { + return ( ( PCI_RGET(PCIIS) & _PCI_maskTable[eventPci]) >> eventPci ); +} +/*----------------------------------------------------------------------------*/ +IDEF void PCI_intClear(Uint32 eventPci) { + PCI_RSET(PCIIS, PCI_RGET(PCIIS) & _PCI_maskTable[eventPci]) ; +} +/*----------------------------------------------------------------------------*/ +IDEF void PCI_dspIntReqSet(){ + PCI_FSET(RSTSRC,INTREQ,1); +} +/*----------------------------------------------------------------------------*/ +IDEF void PCI_dspIntReqClear(){ + PCI_FSET(RSTSRC,INTRST,1); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 PCI_eepromSize(){ + return (PCI_FGET(EECTL,EESZ)); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 PCI_eepromTest(){ + volatile Uint32 test = 0; + if ( (PCI_FGET(EECTL,EESZ) != 0)) + { + test = 1; + } + return test; +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 PCI_eepromIsAutoCfg() { + return((Uint32) PCI_FGET(EECTL,EEAI)); +} +/*----------------------------------------------------------------------------*/ +#if (!C64_SUPPORT) +IDEF void PCI_pwrStatUpdate() { + PCI_FSET(PMDCSR,CURSTATE,PCI_FGET(PMDCSR,REQSTATE)); /* update value */ +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 PCI_pwrStatTest() { + volatile Uint32 status; + status= PCI_FGET(PCIIS,PWRMGMT) | (PCI_FGET(PMDCSR,D2WARMONWKP)<<1) \ + | ((PCI_FGET(PMDCSR,D3WARMONWKP)<<1) + 1); + return( status ); +} +#endif /* !C64_SUPPORT */ + +/*----------------------------------------------------------------------------*/ +#endif /* USEDEFS */ + +#endif /* PCI_SUPPORT */ +#endif /* _PCI_H_ */ +/******************************************************************************\ +* End of csl_pci.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_pcihal.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_pcihal.h new file mode 100644 index 0000000..7a6e4bf --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_pcihal.h @@ -0,0 +1,1232 @@ +/******************************************************************************\ +* Copyright (C) 2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_pcihal.h +* DATE CREATED.. 10/02/2000 +* LAST MODIFIED. 26/07/2005 - Changed the field value from DMA to PCI in _PER_FMK +* and _PER_FMKS macro. +* 08/02/2004 - Adding support for C6418 +* 06/09/2003 +*------------------------------------------------------------------------------ +* REGISTERS +* +* RSTSRC - Reset Source/Status register +* PMDCSR - Power Management DSP Control/Status register +* PCIIS - PCI Interrupt Source register +* PCIIEN - PCI Interrupt Enable register +* DSPMA - DSP Master Address register +* PCIMA - PCI Master Address register +* PCIMC - PCI Master Control register +* CDSPA - Current DSP Address register +* CPCIA - Current PCI Address regsiter +* CCNT - Current Byte Count register +* HALT - PCI Transfer Halt register (1) +* EEADD - EEPROM Address register +* EEDAT - EEPROM Date register +* EECTL - EEPROM Control register +* TRCTL - Transfer request control register(C64x Only) +* +* (1) not supported by C64x devices +\******************************************************************************/ +#ifndef _CSL_PCIHAL_H_ +#define _CSL_PCIHAL_H_ + +#include + + +#if (PCI_SUPPORT) +/******************************************************************************\ +* MISC section +\******************************************************************************/ +#if (C64_SUPPORT) + #define _PCI_BASE1_GLOBAL 0x01C00000u + #define _PCI_BASE2_GLOBAL 0x01C20000u + #define _PCI_BASE3_GLOBAL 0x01C30000u +#else + #define _PCI_BASE1_GLOBAL 0x01A40000u + #define _PCI_BASE2_GLOBAL 0x01A80000u +#endif + +/******************************************************************************\ +* module level register/field access macros +\******************************************************************************/ + + /* ----------------- */ + /* FIELD MAKE MACROS */ + /* ----------------- */ + + #define PCI_FMK(REG,FIELD,x)\ + _PER_FMK(PCI,##REG,##FIELD,x) + + #define PCI_FMKS(REG,FIELD,SYM)\ + _PER_FMKS(PCI,##REG,##FIELD,##SYM) + + + /* -------------------------------- */ + /* RAW REGISTER/FIELD ACCESS MACROS */ + /* -------------------------------- */ + + #define PCI_ADDR(REG)\ + _PCI_##REG##_ADDR + + #define PCI_RGET(REG)\ + _PER_RGET(_PCI_##REG##_ADDR,PCI,##REG) + + #define PCI_RSET(REG,x)\ + _PER_RSET(_PCI_##REG##_ADDR,PCI,##REG,x) + + #define PCI_FGET(REG,FIELD)\ + _PCI_##REG##_FGET(##FIELD) + + #define PCI_FSET(REG,FIELD,x)\ + _PCI_##REG##_FSET(##FIELD,##x) + + #define PCI_FSETS(REG,FIELD,SYM)\ + _PCI_##REG##_FSETS(##FIELD,##SYM) + + + /* ------------------------------------------ */ + /* ADDRESS BASED REGISTER/FIELD ACCESS MACROS */ + /* ------------------------------------------ */ + + #define PCI_RGETA(addr,REG)\ + _PER_RGET(addr,PCI,##REG) + + #define PCI_RSETA(addr,REG,x)\ + _PER_RSET(addr,PCI,##REG,x) + + #define PCI_FGETA(addr,REG,FIELD)\ + _PER_FGET(addr,PCI,##REG,##FIELD) + + #define PCI_FSETA(addr,REG,FIELD,x)\ + _PER_FSET(addr,PCI,##REG,##FIELD,x) + + #define PCI_FSETSA(addr,REG,FIELD,SYM)\ + _PER_FSETS(addr,PCI,##REG,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | R S T S R C | +* |___________________| +* +* RSTSRC - DSP Reset Source-Status Regsiter +* +* FIELDS (msb -> lsb) +* (r) CFGERR +* (r) CFGDONE +* (w) INTRST +* (w) INTREQ +* (r) WARMRST +* (r) PRST +* (r) RST +* +\******************************************************************************/ + #define _PCI_RSTSRC_OFFSET 0 + + #if (C64_SUPPORT) + #define _PCI_RSTSRC_ADDR 0x01C00000u + #else + #define _PCI_RSTSRC_ADDR 0x01A40000u + #endif + + #define _PCI_RSTSRC_CFGERR_MASK 0x00000040u + #define _PCI_RSTSRC_CFGERR_SHIFT 0x00000006u + #define PCI_RSTSRC_CFGERR_DEFAULT 0x00000000u + #define PCI_RSTSRC_CFGERR_OF(x) _VALUEOF(x) + + + #define _PCI_RSTSRC_CFGDONE_MASK 0x00000020u + #define _PCI_RSTSRC_CFGDONE_SHIFT 0x00000005u + #define PCI_RSTSRC_CFGDONE_DEFAULT 0x00000000u + #define PCI_RSTSRC_CFGDONE_OF(x) _VALUEOF(x) + + #define _PCI_RSTSRC_INTRST_MASK 0x00000010u + #define _PCI_RSTSRC_INTRST_SHIFT 0x00000004u + #define PCI_RSTSRC_INTRST_DEFAULT 0x00000000u + #define PCI_RSTSRC_INTRST_OF(x) _VALUEOF(x) + #define PCI_RSTSRC_INTRST_YES 0x00000001u + #define PCI_RSTSRC_INTRST_NO 0x00000000u + + #define _PCI_RSTSRC_INTREQ_MASK 0x00000008u + #define _PCI_RSTSRC_INTREQ_SHIFT 0x00000003u + #define PCI_RSTSRC_INTREQ_DEFAULT 0x00000000u + #define PCI_RSTSRC_INTREQ_OF(x) _VALUEOF(x) + #define PCI_RSTSRC_INTREQ_YES 0x00000001u + #define PCI_RSTSRC_INTREQ_NO 0x00000000u + + #define _PCI_RSTSRC_WARMRST_MASK 0x00000004u + #define _PCI_RSTSRC_WARMRST_SHIFT 0x00000002u + #define PCI_RSTSRC_WARMRST_DEFAULT 0x00000000u + #define PCI_RSTSRC_WARMRST_OF(x) _VALUEOF(x) + + + #define _PCI_RSTSRC_PRST_MASK 0x00000002u + #define _PCI_RSTSRC_PRST_SHIFT 0x00000001u + #define PCI_RSTSRC_PRST_DEFAULT 0x00000000u + #define PCI_RSTSRC_PRST_OF(x) _VALUEOF(x) + + #define _PCI_RSTSRC_RST_MASK 0x00000001u + #define _PCI_RSTSRC_RST_SHIFT 0x00000000u + #define PCI_RSTSRC_RST_DEFAULT 0x00000001u + #define PCI_RSTSRC_RST_OF(x) _VALUEOF(x) + + #define PCI_RSTSRC_OF(x) _VALUEOF(x) + + + #define PCI_RSTRC_DEFAULT (Uint32)( \ + _PER_FDEFAULT(PCI,RSTSRC,CFGERR) \ + |_PER_FDEFAULT(PCI,RSTSRC,CFGDONE) \ + |_PER_FDEFAULT(PCI,RSTSRC,INTRST) \ + |_PER_FDEFAULT(PCI,RSTSRC,INTREQ) \ + |_PER_FDEFAULT(PCI,RSTSRC,WARMRST) \ + |_PER_FDEFAULT(PCI,RSTSRC,PRST) \ + |_PER_FDEFAULT(PCI,RSTSRC,RST) \ + ) + + #define PCI_RSTSRC_RMK(intrst,intreq) \ + (Uint32)( \ + _PER_FMK(PCI,RSTSRC,INTRST,intrst) \ + |_PER_FMK(PCI,RSTSRC,INTREQ,intreq) \ + ) + + #define _PCI_RSTSRC_FGET(FIELD)\ + _PER_FGET(_PCI_RSTSRC_ADDR,PCI,RSTSRC,##FIELD) + + #define _PCI_RSTSRC_FSET(FIELD,field)\ + _PER_FSET(_PCI_RSTSRC_ADDR,PCI,RSTSRC,##FIELD,field) + + #define _PCI_RSTSRC_FSETS(FIELD,SYM)\ + _PER_FSETS(_PCI_RSTSRC_ADDR,PCI,RSTSRC,##FIELD,##SYM) + + + +/******************************************************************************\ +* _____________________ +* | | +* | P M D C S R | +* |___________________| +* +* PMDCSR - Power Management DSP Control-Status Register +* +* FIELDS (msb -> lsb) +* (rw) HWPMECTL +* (r) D3WARMONWKP +* (r) D2WARMONWKP +* (rw) PMEEN +* (r) PWRWKP +* (rw) PMESTAT +* (r) PMEDRVN +* (r) AUXDETECT +* (rw) CURSTATE +* (r) REQSTATE +* +\******************************************************************************/ + #define _PCI_PMDCSR_OFFSET 1 + + #if (C64_SUPPORT) + #define _PCI_PMDCSR_ADDR 0x01C00004u + #else + #define _PCI_PMDCSR_ADDR 0x01A40004u + #endif + + + #define _PCI_PMDCSR_HWPMECTL_MASK 0x0007F800u + #define _PCI_PMDCSR_HWPMECTL_SHIFT 0x0000000Bu + #define PCI_PMDCSR_HWPMECTL_DEFAULT 0x00000088u + #define PCI_PMDCSR_HWPMECTL_OF(x) _VALUEOF(x) + #define PCI_PMDCSR_HWPMECTL_REQD0 0x00000001u + #define PCI_PMDCSR_HWPMECTL_REQD1 0x00000002u + #define PCI_PMDCSR_HWPMECTL_REQD2 0x00000003u + #define PCI_PMDCSR_HWPMECTL_REQD3 0x00000004u + + #define _PCI_PMDCSR_D3WARMONWKP_MASK 0x00000400u + #define _PCI_PMDCSR_D3WARMONWKP_SHIFT 0x0000000Au + #define PCI_PMDCSR_D3WARMONWKP_DEFAULT 0x00000000u + #define PCI_PMDCSR_D3WARMONWKP_OF(x) _VALUEOF(x) + + #define _PCI_PMDCSR_D2WARMONWKP_MASK 0x00000200u + #define _PCI_PMDCSR_D2WARMONWKP_SHIFT 0x00000009u + #define PCI_PMDCSR_D2WARMONWKP_DEFAULT 0x00000000u + #define PCI_PMDCSR_D2WARMONWKP_OF(x) _VALUEOF(x) + + #define _PCI_PMDCSR_PMEEN_MASK 0x00000100u + #define _PCI_PMDCSR_PMEEN_SHIFT 0x00000008u + #define PCI_PMDCSR_PMEEN_DEFAULT 0x00000000u + #define PCI_PMDCSR_PMEEN_OF(x) _VALUEOF(x) + #define PCI_PMDCSR_PMEEN_CLR 0x00000001u + + #define _PCI_PMDCSR_PMEWKP_MASK 0x00000080u + #define _PCI_PMDCSR_PMEWKP_SHIFT 0x00000007u + #define PCI_PMDCSR_PMEWKP_DEFAULT 0x00000000u + #define PCI_PMDCSR_PMEWKP_OF(x) _VALUEOF(x) + + #define _PCI_PMDCSR_PMESTAT_MASK 0x00000040u + #define _PCI_PMDCSR_PMESTAT_SHIFT 0x00000006u + #define PCI_PMDCSR_PMESTAT_DEFAULT 0x00000000u + #define PCI_PMDCSR_PMESTAT_OF(x) _VALUEOF(x) + #define PCI_PMDCSR_PMESTAT_SET 0x00000001u + + #define _PCI_PMDCSR_PMEDRVN_MASK 0x00000020u + #define _PCI_PMDCSR_PMEDRVN_SHIFT 0x00000005u + #define PCI_PMDCSR_PMEDRVN_DEFAULT 0x00000000u + #define PCI_PMDCSR_PMEDRVN_OF(x) _VALUEOF(x) + + #define _PCI_PMDCSR_AUXDETECT_MASK 0x00000010u + #define _PCI_PMDCSR_AUXDETECT_SHIFT 0x00000004u + #define PCI_PMDCSR_AUXDETECT_DEFAULT 0x00000000u + #define PCI_PMDCSR_AUXDETECT_OF(x) _VALUEOF(x) + + #define _PCI_PMDCSR_CURSTATE_MASK 0x0000000Cu + #define _PCI_PMDCSR_CURSTATE_SHIFT 0x00000002u + #define PCI_PMDCSR_CURSTATE_DEFAULT 0x00000000u + #define PCI_PMDCSR_CURSTATE_OF(x) _VALUEOF(x) + #define PCI_PMDCSR_CURSTATE_D0 0x00000000u + #define PCI_PMDCSR_CURSTATE_D1 0x00000001u + #define PCI_PMDCSR_CURSTATE_D2 0x00000002u + #define PCI_PMDCSR_CURSTATE_D3 0x00000003u + + #define _PCI_PMDCSR_REQSTATE_MASK 0x00000003u + #define _PCI_PMDCSR_REQSTATE_SHIFT 0x00000000u + #define PCI_PMDCSR_REQSTATE_DEFAULT 0x00000000u + #define PCI_PMDCSR_REQSTATE_OF(x) _VALUEOF(x) + + #define PCI_PMDCSR_OF(x) _VALUEOF(x) + + #define PCI_PMDCSR_DEFAULT (Uint32)( \ + _PER_FDEFAULT(PCI,PMDCSR,HWPMECTL) \ + |_PER_FMK(PCI,PMDCSR,D3WARMONWKP) \ + |_PER_FMK(PCI,PMDCSR,D2WARMONWKP) \ + |_PER_FDEFAULT(PCI,PMDCSR,PMEEN) \ + |_PER_FDEFAULT(PCI,PMDCSR,PMEWKP) \ + |_PER_FDEFAULT(PCI,PMDCSR,PMESTAT) \ + |_PER_FDEFAULT(PCI,PMDCSR,PMEDRVN) \ + |_PER_FDEFAULT(PCI,PMDCSR,AUXDETECT) \ + |_PER_FDEFAULT(PCI,PMDCSR,CURSTATE) \ + |_PER_FDEFAULT(PCI,PMDCSR,REQSTATE) \ + ) + + #define PCI_PMDCSR_RMK(hwpmectl,pmeen,pmestat,curstate) \ + (Uint32)( \ + _PER_FMK(PCI,PMDCSR,HWPMECTL,hwpmectl) \ + |_PER_FMK(PCI,PMDCSR,PMEEN,pmeena) \ + |_PER_FMK(PCI,PMDCSR,PMESTAT,pmestat) \ + |_PER_FMK(PCI,PMDCSR,CURSTATE,curstate) \ + ) + + #define _PCI_PMDCSR_FGET(FIELD)\ + _PER_FGET(_PCI_PMDCSR_ADDR,PCI,PMDCSR,##FIELD) + + #define _PCI_PMDCSR_FSET(FIELD,field)\ + _PER_FSET(_PCI_PMDCSR_ADDR,PCI,PMDCSR,##FIELD,field) + + #define _PCI_PMDCSR_FSETS(FIELD,SYM)\ + _PER_FSETS(_PCI_PMDCSR_ADDR,PCI,PMDCSR,##FIELD,##SYM) + + + + +/******************************************************************************\ +* _____________________ +* | | +* | P C I I S | +* |___________________| +* +* PCIIS - PCI Interrupt Source Register +* +* FIELDS (msb -> lsb) +* (rw) DMAHALTED +* (rw) PRST +* (rw) EERDY +* (rw) CFGERR +* (rw) CFGDONE +* (rw) MASTEROK +* (rw) PWRHL +* (rw) PWRLH +* (rw) HOSTSW +* (rw) PCIMASTER +* (rw) PCITARGET +* (rw) PWRMGMT +* +\******************************************************************************/ + #define _PCI_PCIIS_OFFSET 2 + + #if (C64_SUPPORT) + #define _PCI_PCIIS_ADDR 0x01C00008u + #else + #define _PCI_PCIIS_ADDR 0x01A40008u + #endif + + + #define _PCI_PCIIS_DMAHALTED_MASK 0x00001000u + #define _PCI_PCIIS_DMAHALTED_SHIFT 0x0000000Cu + #define PCI_PCIIS_DMAHALTED_DEFAULT 0x00000000u + #define PCI_PCIIS_DMAHALTED_OF(x) _VALUEOF(x) + #define PCI_PCIIS_DMAHALTED_CLR 0x00000001u + + #define _PCI_PCIIS_PRST_MASK 0x00000800u + #define _PCI_PCIIS_PRST_SHIFT 0x0000000Bu + #define PCI_PCIIS_PRST_DEFAULT 0x00000000u + #define PCI_PCIIS_PRST_OF(x) _VALUEOF(x) + #define PCI_PCIIS_PRST_CHGSTATE 0x00000001u + #define PCI_PCIIS_PRST_NOCHG 0x00000000u + + #define _PCI_PCIIS_EERDY_MASK 0x00000200u + #define _PCI_PCIIS_EERDY_SHIFT 0x00000009u + #define PCI_PCIIS_EERDY_DEFAULT 0x00000000u + #define PCI_PCIIS_EERDY_OF(x) _VALUEOF(x) + #define PCI_PCIIS_EERDY_CLR 0x00000001u + + + #define _PCI_PCIIS_CFGERR_MASK 0x00000100u + #define _PCI_PCIIS_CFGERR_SHIFT 0x00000008u + #define PCI_PCIIS_CFGERR_DEFAULT 0x00000000u + #define PCI_PCIIS_CFGERR_OF(x) _VALUEOF(x) + #define PCI_PCIIS_CFGERR_CLR 0x00000001u + + #define _PCI_PCIIS_CFGDONE_MASK 0x00000080u + #define _PCI_PCIIS_CFGDONE_SHIFT 0x00000007u + #define PCI_PCIIS_CFGDONE_DEFAULT 0x00000000u + #define PCI_PCIIS_CFGDONE_OF(x) _VALUEOF(x) + #define PCI_PCIIS_CFGDONE_CLR 0x00000001u + + #define _PCI_PCIIS_MASTEROK_MASK 0x00000040u + #define _PCI_PCIIS_MASTEROK_SHIFT 0x00000006u + #define PCI_PCIIS_MASTEROK_DEFAULT 0x00000000u + #define PCI_PCIIS_MASTEROK_OF(x) _VALUEOF(x) + #define PCI_PCIIS_MASTEROK_CLR 0x00000001u + + #define _PCI_PCIIS_PWRHL_MASK 0x00000020u + #define _PCI_PCIIS_PWRHL_SHIFT 0x00000005u + #define PCI_PCIIS_PWRHL_DEFAULT 0x00000000u + #define PCI_PCIIS_PWRHL_OF(x) _VALUEOF(x) + #define PCI_PCIIS_PWRHL_CLR 0x00000001u + + #define _PCI_PCIIS_PWRLH_MASK 0x00000010u + #define _PCI_PCIIS_PWRLH_SHIFT 0x00000004u + #define PCI_PCIIS_PWRLH_DEFAULT 0x00000000u + #define PCI_PCIIS_PWRLH_OF(x) _VALUEOF(x) + #define PCI_PCIIS_PWRLH_CLR 0x00000001u + + #define _PCI_PCIIS_HOSTSW_MASK 0x00000008u + #define _PCI_PCIIS_HOSTSW_SHIFT 0x00000003u + #define PCI_PCIIS_HOSTSW_DEFAULT 0x00000000u + #define PCI_PCIIS_HOSTSW_OF(x) _VALUEOF(x) + #define PCI_PCIIS_HOSTSW_CLR 0x00000001u + + #define _PCI_PCIIS_PCIMASTER_MASK 0x00000004u + #define _PCI_PCIIS_PCIMASTER_SHIFT 0x00000002u + #define PCI_PCIIS_PCIMASTER_DEFAULT 0x00000000u + #define PCI_PCIIS_PCIMASTER_OF(x) _VALUEOF(x) + #define PCI_PCIIS_PCIMASTER_CLR 0x00000001u + + #define _PCI_PCIIS_PCITARGET_MASK 0x00000002u + #define _PCI_PCIIS_PCITARGET_SHIFT 0x00000001u + #define PCI_PCIIS_PCITARGET_DEFAULT 0x00000000u + #define PCI_PCIIS_PCITARGET_OF(x) _VALUEOF(x) + #define PCI_PCIIS_PCITARGET_CLR 0x00000001u + + #define _PCI_PCIIS_PWRMGMT_MASK 0x00000001u + #define _PCI_PCIIS_PWRMGMT_SHIFT 0x00000000u + #define PCI_PCIIS_PWRMGMT_DEFAULT 0x00000000u + #define PCI_PCIIS_PWRMGMT_OF(x) _VALUEOF(x) + #define PCI_PCIIS_PWRMGMT_CLR 0x00000001u + + #define PCI_PCIIS_OF(x) _VALUEOF(x) + + #define PCI_PCIIS_DEFAULT (Uint32)( \ + _PER_FDEFAULT(PCI,PCIIS,DMAHALTED) \ + |_PER_FDEFAULT(PCI,PCIIS,PRST) \ + |_PER_FDEFAULT(PCI,PCIIS,EERDY) \ + |_PER_FDEFAULT(PCI,PCIIS,CFGERR) \ + |_PER_FDEFAULT(PCI,PCIIS,CFGDONE) \ + |_PER_FDEFAULT(PCI,PCIIS,MASTEROK) \ + |_PER_FDEFAULT(PCI,PCIIS,PWRHL) \ + |_PER_FDEFAULT(PCI,PCIIS,PWRLH) \ + |_PER_FDEFAULT(PCI,PCIIS,HOSTSW) \ + |_PER_FDEFAULT(PCI,PCIIS,PCIMASTER) \ + |_PER_FDEFAULT(PCI,PCIIS,PCITARGET) \ + |_PER_FDEFAULT(PCI,PCIIS,PWRMGMT) \ + ) + + #define PCI_PCIIS_RMK(dmahalted,prst,eerdy,cfgerr,cfgdone,masterok, \ + pwrhl,pwrlh,hostsw,pcimaster,pcitarget,pwrmgmt)\ + (Uint32)( \ + _PER_FMK(PCI,PCIIS,DMAHALTED,dmahalted) \ + |_PER_FMK(PCI,PCIIS,PRST,prst) \ + |_PER_FMK(PCI,PCIIS,EERDY,eerdy) \ + |_PER_FMK(PCI,PCIIS,CFGERR,cfgerr) \ + |_PER_FMK(PCI,PCIIS,CFGDONE,cfgdone) \ + |_PER_FMK(PCI,PCIIS,MASTEROK,masterok) \ + |_PER_FMK(PCI,PCIIS,PWRHL,pwrhl) \ + |_PER_FMK(PCI,PCIIS,PWRLH,pwrlh) \ + |_PER_FMK(PCI,PCIIS,HOSTSW,hostsw) \ + |_PER_FMK(PCI,PCIIS,PCIMASTER,pcimaster) \ + |_PER_FMK(PCI,PCIIS,PCITARGET,pcitarget) \ + |_PER_FMK(PCI,PCIIS,PWRMGMT,pwrmgmt) \ + ) + + #define _PCI_PCIIS_FGET(FIELD)\ + _PER_FGET(_PCI_PCIIS_ADDR,PCI,PCIIS,##FIELD) + + #define _PCI_PCIIS_FSET(FIELD,field)\ + _PER_FSET(_PCI_PCIIS_ADDR,PCI,PCIIS,##FIELD,field) + + #define _PCI_PCIIS_FSETS(FIELD,SYM)\ + _PER_FSETS(_PCI_PCIIS_ADDR,PCI,PCIIS,##FIELD,##SYM) + + + +/******************************************************************************\ +* _____________________ +* | | +* | P C I I E N | +* |___________________| +* +* PCIIEN - PCI Interrupt Enable Register +* +* FIELDS (msb -> lsb) +* (rw) PRST +* (rw) EERDY +* (rw) CFGERR +* (rw) CFGDONE +* (rw) MASTEROK +* (rw) PWRHL +* (rw) PWRLH +* (rw) HOSTSW +* (rw) PCIMASTER +* (rw) PCITARGET +* (rw) PWRMGMT +* +\******************************************************************************/ + #define _PCI_PCIIEN_OFFSET 3 + + #if (C64_SUPPORT) + #define _PCI_PCIIEN_ADDR 0x01C0000Cu + #else + #define _PCI_PCIIEN_ADDR 0x01A4000Cu + #endif + + + + #define _PCI_PCIIEN_PRST_MASK 0x00000800u + #define _PCI_PCIIEN_PRST_SHIFT 0x0000000Bu + #define PCI_PCIIEN_PRST_DEFAULT 0x00000000u + #define PCI_PCIIEN_PRST_OF(x) _VALUEOF(x) + #define PCI_PCIIEN_PRST_DISABLE 0x00000000u + #define PCI_PCIIEN_PRST_ENABLE 0x00000001u + + #define _PCI_PCIIEN_EERDY_MASK 0x00000200u + #define _PCI_PCIIEN_EERDY_SHIFT 0x00000009u + #define PCI_PCIIEN_EERDY_DEFAULT 0x00000000u + #define PCI_PCIIEN_EERDY_OF(x) _VALUEOF(x) + #define PCI_PCIIEN_EERDY_DISABLE 0x00000000u + #define PCI_PCIIEN_EERDY_ENABLE 0x00000001u + + + #define _PCI_PCIIEN_CFGERR_MASK 0x00000100u + #define _PCI_PCIIEN_CFGERR_SHIFT 0x00000008u + #define PCI_PCIIEN_CFGERR_DEFAULT 0x00000000u + #define PCI_PCIIEN_CFGERR_OF(x) _VALUEOF(x) + #define PCI_PCIIEN_CFGERR_DISABLE 0x00000000u + #define PCI_PCIIEN_CFGERR_ENABLE 0x00000001u + + #define _PCI_PCIIEN_CFGDONE_MASK 0x00000080u + #define _PCI_PCIIEN_CFGDONE_SHIFT 0x00000007u + #define PCI_PCIIEN_CFGDONE_DEFAULT 0x00000000u + #define PCI_PCIIEN_CFGDONE_OF(x) _VALUEOF(x) + #define PCI_PCIIEN_CFGDONE_DISABLE 0x00000000u + #define PCI_PCIIEN_CFGDONE_ENABLE 0x00000001u + + #define _PCI_PCIIEN_MASTEROK_MASK 0x00000040u + #define _PCI_PCIIEN_MASTEROK_SHIFT 0x00000006u + #define PCI_PCIIEN_MASTEROK_DEFAULT 0x00000000u + #define PCI_PCIIEN_MASTEROK_OF(x) _VALUEOF(x) + #define PCI_PCIIEN_MASTEROK_DISABLE 0x00000000u + #define PCI_PCIIEN_MASTEROK_ENABLE 0x00000001u + + #define _PCI_PCIIEN_PWRHL_MASK 0x00000020u + #define _PCI_PCIIEN_PWRHL_SHIFT 0x00000005u + #define PCI_PCIIEN_PWRHL_DEFAULT 0x00000000u + #define PCI_PCIIEN_PWRHL_OF(x) _VALUEOF(x) + #define PCI_PCIIEN_PWRHL_DISABLE 0x00000000u + #define PCI_PCIIEN_PWRHL_ENABLE 0x00000001u + + #define _PCI_PCIIEN_PWRLH_MASK 0x00000010u + #define _PCI_PCIIEN_PWRLH_SHIFT 0x00000004u + #define PCI_PCIIEN_PWRLH_DEFAULT 0x00000000u + #define PCI_PCIIEN_PWRLH_OF(x) _VALUEOF(x) + #define PCI_PCIIEN_PWRLH_DISABLE 0x00000000u + #define PCI_PCIIEN_PWRLH_ENABLE 0x00000001u + + #define _PCI_PCIIEN_HOSTSW_MASK 0x00000008u + #define _PCI_PCIIEN_HOSTSW_SHIFT 0x00000003u + #define PCI_PCIIEN_HOSTSW_DEFAULT 0x00000008u + #define PCI_PCIIEN_HOSTSW_OF(x) _VALUEOF(x) + #define PCI_PCIIEN_HOSTSW_DISABLE 0x00000000u + #define PCI_PCIIEN_HOSTSW_ENABLE 0x00000001u + + #define _PCI_PCIIEN_PCIMASTER_MASK 0x00000004u + #define _PCI_PCIIEN_PCIMASTER_SHIFT 0x00000002u + #define PCI_PCIIEN_PCIMASTER_DEFAULT 0x00000000u + #define PCI_PCIIEN_PCIMASTER_OF(x) _VALUEOF(x) + #define PCI_PCIIEN_PCIMASTER_DISABLE 0x00000000u + #define PCI_PCIIEN_PCIMASTER_ENABLE 0x00000001u + + #define _PCI_PCIIEN_PCITARGET_MASK 0x00000002u + #define _PCI_PCIIEN_PCITARGET_SHIFT 0x00000001u + #define PCI_PCIIEN_PCITARGET_DEFAULT 0x00000000u + #define PCI_PCIIEN_PCITARGET_OF(x) _VALUEOF(x) + #define PCI_PCIIEN_PCITARGET_DISABLE 0x00000000u + #define PCI_PCIIEN_PCITARGET_ENABLE 0x00000001u + + #define _PCI_PCIIEN_PWRMGMT_MASK 0x00000001u + #define _PCI_PCIIEN_PWRMGMT_SHIFT 0x00000000u + #define PCI_PCIIEN_PWRMGMT_DEFAULT 0x00000000u + #define PCI_PCIIEN_PWRMGMT_OF(x) _VALUEOF(x) + #define PCI_PCIIEN_PWRMGMT_DISABLE 0x00000000u + #define PCI_PCIIEN_PWRMGMT_ENABLE 0x00000001u + + #define PCI_PCIIEN_OF(x) _VALUEOF(x) + + #define PCI_PCIIEN_DEFAULT (Uint32)( \ + _PER_FDEFAULT(PCI,PCIIEN,PRST) \ + |_PER_FDEFAULT(PCI,PCIIEN,EERDY) \ + |_PER_FDEFAULT(PCI,PCIIEN,CFGERR) \ + |_PER_FDEFAULT(PCI,PCIIEN,CFGDONE) \ + |_PER_FDEFAULT(PCI,PCIIEN,MASTEROK) \ + |_PER_FDEFAULT(PCI,PCIIEN,PWRHL) \ + |_PER_FDEFAULT(PCI,PCIIEN,PWRLH) \ + |_PER_FDEFAULT(PCI,PCIIEN,HOSTSW) \ + |_PER_FDEFAULT(PCI,PCIIEN,PCIMASTER) \ + |_PER_FDEFAULT(PCI,PCIIEN,PCITARGET) \ + |_PER_FDEFAULT(PCI,PCIIEN,PWRMGMT) \ + ) + + #define PCI_PCIIEN_RMK(prst,eerdy,cfgerr,cfgdone,masterok, \ + pwrhl,pwrlh,hostsw,pcimaster,pcitarget,pwrmgmt)\ + (Uint32)( \ + _PER_FMK(PCI,PCIIEN,PRST,prst) \ + |_PER_FMK(PCI,PCIIEN,EERDY,eerdy) \ + |_PER_FMK(PCI,PCIIEN,CFGERR,cfgerr) \ + |_PER_FMK(PCI,PCIIEN,CFGDONE,cfgdone) \ + |_PER_FMK(PCI,PCIIEN,MASTEROK,masterok) \ + |_PER_FMK(PCI,PCIIEN,PWRHL,pwrhl) \ + |_PER_FMK(PCI,PCIIEN,PWRLH,pwrlh) \ + |_PER_FMK(PCI,PCIIEN,HOSTSW,hostsw) \ + |_PER_FMK(PCI,PCIIEN,PCIMASTER,pcimaster) \ + |_PER_FMK(PCI,PCIIEN,PCITARGET,pcitarget) \ + |_PER_FMK(PCI,PCIIEN,PWRMGMT,pwrmgmt) \ + ) + + #define _PCI_PCIIEN_FGET(FIELD)\ + _PER_FGET(_PCI_PCIIEN_ADDR,PCI,PCIIEN,##FIELD) + + #define _PCI_PCIIEN_FSET(FIELD,field)\ + _PER_FSET(_PCI_PCIIEN_ADDR,PCI,PCIIEN,##FIELD,field) + + #define _PCI_PCIIEN_FSETS(FIELD,SYM)\ + _PER_FSETS(_PCI_PCIIEN_ADDR,PCI,PCIIEN,##FIELD,##SYM) + +/******************************************************************************\ +* _____________________ +* | | +* | D S P M A | +* |___________________| +* +* DSPMA - DSP Master Address Register +* +* FIELDS (msb -> lsb) +* (rw) ADDRMA +* (rw) AINC +* +\******************************************************************************/ + #define _PCI_DSPMA_OFFSET 4 + + + #if (C64_SUPPORT) + #define _PCI_DSPMA_ADDR 0x01C00010u + #else + #define _PCI_DSPMA_ADDR 0x01A40010u + #endif + + #define _PCI_DSPMA_ADDRMA_MASK 0xFFFFFFFCu + #define _PCI_DSPMA_ADDRMA_SHIFT 0x00000002u + #define PCI_DSPMA_ADDRMA_DEFAULT 0x00000000u + #define PCI_DSPMA_ADDRMA_OF(x) _VALUEOF(x) + + #define _PCI_DSPMA_AINC_MASK 0x00000002u + #define _PCI_DSPMA_AINC_SHIFT 0x00000001u + #define PCI_DSPMA_AINC_DEFAULT 0x00000000u + #define PCI_DSPMA_AINC_OF(x) _VALUEOF(x) + #define PCI_DSPMA_AINC_ENABLE 0x00000000u + #define PCI_DSPMA_AINC_DISABLE 0x00000001u + + #define PCI_DSPMA_OF(x) _VALUEOF(x) + + #define PCI_DSPMA_DEFAULT (Uint32)( \ + _PER_FDEFAULT(PCI,DSPMA,ADDRMA) \ + |_PER_FDEFAULT(PCI,DSPMA,AINC) \ + ) + + #define PCI_DSPMA_RMK(addrma,ainc)\ + (Uint32)( \ + _PER_FMK(PCI,DSPMA,ADDRMA,addrma) \ + |_PER_FMK(PCI,DSPMA,AINC,ainc) \ + ) + + #define _PCI_DSPMA_FGET(FIELD)\ + _PER_FGET(_PCI_DSPMA_ADDR,PCI,DSPMA,##FIELD) + + #define _PCI_DSPMA_FSET(FIELD,field)\ + _PER_FSET(_PCI_DSPMA_ADDR,PCI,DSPMA,##FIELD,field) + + #define _PCI_DSPMA_FSETS(FIELD,SYM)\ + _PER_FSETS(_PCI_DSPMA_ADDR,PCI,DSPMA,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | P C I M A | +* |___________________| +* +* PCIMA - PCI Master Address Register +* +* FIELDS (msb -> lsb) +* (rw) ADDRMA +* +\******************************************************************************/ + #define _PCI_PCIMA_OFFSET 5 + + #if (C64_SUPPORT) + #define _PCI_PCIMA_ADDR 0x01C00014u + #else + #define _PCI_PCIMA_ADDR 0x01A40014u + #endif + + #define _PCI_PCIMA_ADDRMA_MASK 0xFFFFFFFCu + #define _PCI_PCIMA_ADDRMA_SHIFT 0x00000002u + #define PCI_PCIMA_ADDRMA_DEFAULT 0x00000000u + #define PCI_PCIMA_ADDRMA_OF(x) _VALUEOF(x) + + #define PCI_PCIMA_OF(x) _VALUEOF(x) + + #define PCI_PCIMA_DEFAULT (Uint32)( \ + _PER_FDEFAULT(PCI,PCIMA,ADDRMA) \ + ) + + #define PCI_PCIMA_RMK(addrma)\ + (Uint32)( \ + _PER_FMK(PCI,PCIMA,ADDRMA,addrma) \ + ) + + #define _PCI_PCIMA_FGET(FIELD)\ + _PER_FGET(_PCI_PCIMA_ADDR,PCI,PCIMA,##FIELD) + + #define _PCI_PCIMA_FSET(FIELD,field)\ + _PER_FSET(_PCI_PCIMA_ADDR,PCI,PCIMA,##FIELD,field) + + #define _PCI_PCIMA_FSETS(FIELD,SYM)\ + _PER_FSETS(_PCI_PCIMA_ADDR,PCI,PCIMA,##FIELD,##SYM) + + + + +/******************************************************************************\ +* _____________________ +* | | +* | P C I M C | +* |___________________| +* +* PCIMC - PCI Master Control Register +* +* FIELDS (msb -> lsb) +* (rw) CNT +* (rw) START +* +\******************************************************************************/ + #define _PCI_PCIMC_OFFSET 6 + + #if (C64_SUPPORT) + #define _PCI_PCIMC_ADDR 0x01C00018u + #else + #define _PCI_PCIMC_ADDR 0x01A40018u + #endif + + #define _PCI_PCIMC_CNT_MASK 0xFFFF0000u + #define _PCI_PCIMC_CNT_SHIFT 0x00000010u + #define PCI_PCIMC_CNT_DEFAULT 0x00000000u + #define PCI_PCIMC_CNT_OF(x) _VALUEOF(x) + + + #define _PCI_PCIMC_START_MASK 0x00000007u + #define _PCI_PCIMC_START_SHIFT 0x00000000u + #define PCI_PCIMC_START_DEFAULT 0x00000000u + #define PCI_PCIMC_START_OF(x) _VALUEOF(x) + #define PCI_PCIMC_START_FLUSH 0x00000000u + #define PCI_PCIMC_START_WRITE 0x00000001u + #define PCI_PCIMC_START_READPREF 0x00000002u + #define PCI_PCIMC_START_READNOPREF 0x00000003u + #define PCI_PCIMC_START_CONFIGWRITE 0x00000004u + #define PCI_PCIMC_START_CONFIGREAD 0x00000005u + #define PCI_PCIMC_START_IOWRITE 0x00000006u + #define PCI_PCIMC_START_IOREAD 0x00000007u + + + #define PCI_PCIMC_OF(x) _VALUEOF(x) + + #define PCI_PCIMC_DEFAULT (Uint32)( \ + _PER_FDEFAULT(PCI,PCIMC,CNT) \ + |_PER_FDEFAULT(PCI,PCIMC,START) \ + ) + + #define PCI_PCIMC_RMK(cnt,start)\ + (Uint32)( \ + _PER_FMK(PCI,PCIMC,CNT,cnt) \ + |_PER_FMK(PCI,PCIMC,START,start) \ + ) + #define _PCI_PCIMC_FGET(FIELD)\ + _PER_FGET(_PCI_PCIMC_ADDR,PCI,PCIMC,##FIELD) + + #define _PCI_PCIMC_FSET(FIELD,field)\ + _PER_FSET(_PCI_PCIMC_ADDR,PCI,PCIMC,##FIELD,field) + + #define _PCI_PCIMC_FSETS(FIELD,SYM)\ + _PER_FSETS(_PCI_PCIMC_ADDR,PCI,PCIMC,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | C D S P A | +* |___________________| +* +* CDSPA - Current DSP Address Register +* +* FIELDS (msb -> lsb) +* (r) CDSPA +* +\******************************************************************************/ + #define _PCI_CDSPA_OFFSET 7 + + #if (C64_SUPPORT) + #define _PCI_CDSPA_ADDR 0x01C0001Cu + #else + #define _PCI_CDSPA_ADDR 0x01A4001Cu + #endif + + #define _PCI_CDSPA_CDSPA_MASK 0xFFFFFFFFu + #define _PCI_CDSPA_CDSPA_SHIFT 0x00000000u + #define PCI_CDSPA_CDSPA_DEFAULT 0x00000000u + #define PCI_CDSPA_CDSPA_OF(x) _VALUEOF(x) + + #define PCI_CDSPA_OF(x) _VALUEOF(x) + + #define PCI_CDSPA_DEFAULT (Uint32)( \ + _PER_FDEFAULT(PCI,CDSPA,CDSPA) \ + ) +#if (!(CHIP_6413 | CHIP_6418 | CHIP_6410)) + #define PCI_CDSPA_RMK(cdspa)\ + (Uint32)(\ + _PER_FMK(PCI,CDSPA,CDSPA,cdspa)\ + ) +#endif + #define _PCI_CDSPA_FGET(FIELD)\ + _PER_FGET(_PCI_CDSPA_ADDR,PCI,CDSPA,##FIELD) + +/******************************************************************************\ +* _____________________ +* | | +* | C P C I A | +* |___________________| +* +* CPCIA - Current PCI Address Register +* +* FIELDS (msb -> lsb) +* (r) CPCIA +* +\******************************************************************************/ + #define _PCI_CPCIA_OFFSET 8 + + #if (C64_SUPPORT) + #define _PCI_CPCIA_ADDR 0x01C00020u + #else + #define _PCI_CPCIA_ADDR 0x01A40020u + #endif + + #define _PCI_CPCIA_CPCIA_MASK 0xFFFFFFFFu + #define _PCI_CPCIA_CPCIA_SHIFT 0x00000000u + #define PCI_CPCIA_CPCIA_DEFAULT 0x00000000u + #define PCI_CPCIA_CPCIA_OF(x) _VALUEOF(x) + + #define PCI_CPCIA_OF(x) _VALUEOF(x) + + #define PCI_CPCIA_DEFAULT (Uint32)( \ + _PER_FDEFAULT(PCI,CPCIA,CPCIA) \ + ) +#if (!(CHIP_6413 | CHIP_6418 | CHIP_6410)) + #define PCI_CPCIA_RMK(cpcia)\ + (Uint32)(\ + _PER_FMK(PCI,CPCIA,CPCIA,cpcia)\ + ) +#endif + #define _PCI_CPCIA_FGET(FIELD)\ + _PER_FGET(_PCI_CPCIA_ADDR,PCI,CPCIA,##FIELD) + +/******************************************************************************\ +* _____________________ +* | | +* | C C N T | +* |___________________| +* +* CCNT - Current Byte Counter Register +* +* FIELDS (msb -> lsb) +* (r) CCNT +* +\******************************************************************************/ + #define _PCI_CCNT_OFFSET 9 + + #if (C64_SUPPORT) + #define _PCI_CCNT_ADDR 0x01C00024u + #else + #define _PCI_CCNT_ADDR 0x01A40024u + #endif + + #define _PCI_CCNT_CCNT_MASK 0x0000FFFFu + #define _PCI_CCNT_CCNT_SHIFT 0x00000000u + #define PCI_CCNT_CCNT_DEFAULT 0x00000000u + #define PCI_CCNT_CCNT_OF(x) _VALUEOF(x) + + #define PCI_CCNT_OF(x) _VALUEOF(x) + + #define PCI_CCNT_DEFAULT (Uint32)( \ + _PER_FDEFAULT(PCI,CCNT,CCNT) \ + ) +#if (!(CHIP_6413 | CHIP_6418 | CHIP_6410)) + #define PCI_CCNT_RMK(ccnt) (Uint32)(\ + _PER_FMK(PCI,CCNT,CCNT,ccnt)\ + ) +#endif + #define _PCI_CCNT_FGET(FIELD)\ + _PER_FGET(_PCI_CCNT_ADDR,PCI,CCNT,##FIELD) + + +/****************************************************************************\ +* _____________________ +* | | +* | H A L T | +* |___________________| +* +* HALT - PCI Transfer Halt Register +* +* FIELDS (msb -> lsb) +* (rw) HALT +* +\******************************************************************************/ +#define _PCI_HALT_OFFSET 10 + + #if (C64_SUPPORT) + #define _PCI_HALT_ADDR 0x01C00028u + #else + #define _PCI_HALT_ADDR 0x01A40028u + #endif + + #if (C64_SUPPORT) + #define _PCI_HALT_HALT_MASK 0x00000000u + #define _PCI_HALT_HALT_SHIFT 0x00000000u + #define PCI_HALT_HALT_DEFAULT 0x00000000u + #define PCI_HALT_HALT_OF(x) _VALUEOF(x) +#else + #define _PCI_HALT_HALT_MASK 0x00000001u + #define _PCI_HALT_HALT_SHIFT 0x00000000u + #define PCI_HALT_HALT_DEFAULT 0x00000000u + #define PCI_HALT_HALT_DEFAULT 0x00000000u + #define PCI_HALT_HALT_OF(x) _VALUEOF(x) + #define PCI_HALT_HALT_SET 0x00000001u + #endif + + #define PCI_HALT_OF(x) _VALUEOF(x) + + #define PCI_HALT_RMK(halt)\ + (Uint32)( \ + _PER_FMK(PCI,HALT,HALT,halt) \ + ) + + #define PCI_HALT_DEFAULT (Uint32)( \ + _PER_FDEFAULT(PCI,HALT,HALT) \ + ) + + #define _PCI_HALT_FGET(FIELD)\ + _PER_FGET(_PCI_HALT_ADDR,PCI,HALT,##FIELD) + + #define _PCI_HALT_FSET(FIELD,field)\ + _PER_FSET(_PCI_HALT_ADDR,PCI,HALT,##FIELD,field) + + #define _PCI_HALT_FSETS(FIELD,SYM)\ + _PER_FSETS(_PCI_HALT_ADDR,PCI,HALT,##FIELD,##SYM) + +/****************************************************************************\ +* _____________________ +* | | +* | E E A D D | +* |___________________| +* +* EEADD - EEPROM Address Register +* +* FIELDS (msb -> lsb) +* (rw) EEADD +* +\******************************************************************************/ + + #define _PCI_EEADD_OFFSET 0 + + + #if (C64_SUPPORT) + #define _PCI_EEADD_ADDR 0x01C20000u + #else + #define _PCI_EEADD_ADDR 0x01A80000u + #endif + + #define _PCI_EEADD_EEADD_MASK 0x000003FFu + #define _PCI_EEADD_EEADD_SHIFT 0x00000000u + #define PCI_EEADD_EEADD_DEFAULT 0x00000000u + #define PCI_EEADD_EEADD_OF(x) _VALUEOF(x) + + #define PCI_EEADD_OF(x) _VALUEOF(x) + + #define PCI_EEADD_DEFAULT (Uint32)( \ + _PER_FDEFAULT(PCI,EEADD,EEADD) \ + ) + + #define PCI_EEADD_RMK(eeadd) \ + (Uint32)( \ + _PER_FMK(PCI,EEADD,EEADD,eeadd) \ + ) + + #define _PCI_EEADD_FGET(FIELD)\ + _PER_FGET(_PCI_EEADD_ADDR,PCI,EEADD,##FIELD) + + #define _PCI_EEADD_FSET(FIELD,field)\ + _PER_FSET(_PCI_EEADD_ADDR,PCI,EEADD,##FIELD,field) + + #define _PCI_EEADD_FSETS(FIELD,SYM)\ + _PER_FSETS(_PCI_EEADD_ADDR,PCI,EEADD,##FIELD,##SYM) + +/****************************************************************************\ +* _____________________ +* | | +* | E E D A T | +* |___________________| +* +* EEDAT - EEPROM Data Register +* +* FIELDS (msb -> lsb) +* (rw) EEDAT +* +\*****************************************************************************/ + + #define _PCI_EEDAT_OFFSET 1 + + + #if (C64_SUPPORT) + #define _PCI_EEDAT_ADDR 0x01C20004u + #else + #define _PCI_EEDAT_ADDR 0x01A80004u + #endif + + #define _PCI_EEDAT_EEDAT_MASK 0x0000FFFFu + #define _PCI_EEDAT_EEDAT_SHIFT 0x00000000u + #define PCI_EEDAT_EEDAT_DEFAULT 0x00000000u + #define PCI_EEDAT_EEDAT_OF(x) _VALUEOF(x) + + #define PCI_EEDAT_OF(x) _VALUEOF(x) + + #define PCI_EEDAT_DEFAULT (Uint32)( \ + _PER_FDEFAULT(PCI,EEDAT,EEDAT) \ + ) + + #define PCI_EEDAT_RMK(eedat) \ + (Uint32)( \ + _PER_FMK(PCI,EEDAT,EEDAT,eedat) \ + ) + + #define _PCI_EEDAT_FGET(FIELD)\ + _PER_FGET(_PCI_EEDAT_ADDR,PCI,EEDAT,##FIELD) + + #define _PCI_EEDAT_FSET(FIELD,field)\ + _PER_FSET(_PCI_EEDAT_ADDR,PCI,EEDAT,##FIELD,field) + + #define _PCI_EEDAT_FSETS(FIELD,SYM)\ + _PER_FSETS(_PCI_EEDAT_ADDR,PCI,EEDAT,##FIELD,##SYM) + + + +/****************************************************************************\ +* _____________________ +* | | +* | E E C T L | +* |___________________| +* +* EECTL - EEPROM Control Register +* +* FIELDS (msb -> lsb) +* (r) CFGDONE +* (r) CFGERR +* (r) EEAI +* (r) EESZ +* (r) READY +* (rw) EECNT +* +\******************************************************************************/ + #define _PCI_EECTL_OFFSET 2 + + + #if (C64_SUPPORT) + #define _PCI_EECTL_ADDR 0x01C20008u + #else + #define _PCI_EECTL_ADDR 0x01A80008u + #endif + + #define _PCI_EECTL_CFGDONE_MASK 0x00000100u + #define _PCI_EECTL_CFGDONE_SHIFT 0x00000008u + #define PCI_EECTL_CFGDONE_DEFAULT 0x00000000u + #define PCI_EECTL_CFGDONE_OF(x) _VALUEOF(x) + + + #define _PCI_EECTL_CFGERR_MASK 0x00000080u + #define _PCI_EECTL_CFGERR_SHIFT 0x00000007u + #define PCI_EECTL_CFGERR_DEFAULT 0x00000000u + #define PCI_EECTL_CFGERR_OF(x) _VALUEOF(x) + + + #define _PCI_EECTL_EEAI_MASK 0x00000040u + #define _PCI_EECTL_EEAI_SHIFT 0x00000006u + #define PCI_EECTL_EEAI_DEFAULT 0x00000000u + #define PCI_EECTL_EEAI_OF(x) _VALUEOF(x) + + + #define _PCI_EECTL_EESZ_MASK 0x00000038u + #define _PCI_EECTL_EESZ_SHIFT 0x00000003u + #define PCI_EECTL_EESZ_DEFAULT 0x00000000u + #define PCI_EECTL_EESZ_OF(x) _VALUEOF(x) + + + #define _PCI_EECTL_READY_MASK 0x00000004u + #define _PCI_EECTL_READY_SHIFT 0x00000002u + #define PCI_EECTL_READY_DEFAULT 0x00000000u + #define PCI_EECTL_READY_OF(x) _VALUEOF(x) + + + #define _PCI_EECTL_EECNT_MASK 0x00000003u + #define _PCI_EECTL_EECNT_SHIFT 0x00000000u + #define PCI_EECTL_EECNT_DEFAULT 0x00000000u + #define PCI_EECTL_EECNT_OF(x) _VALUEOF(x) + #define PCI_EECTL_EECNT_EWEN 0x00000000u + #define PCI_EECTL_EECNT_ERAL 0x00000000u + #define PCI_EECTL_EECNT_WRAL 0x00000000u + #define PCI_EECTL_EECNT_EWDS 0x00000000u + #define PCI_EECTL_EECNT_WRITE 0x00000001u + #define PCI_EECTL_EECNT_READ 0x00000002u + #define PCI_EECTL_EECNT_ERASE 0x00000003u + + #define PCI_EECTL_OF(x) _VALUEOF(x) + + #define PCI_EECTL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(PCI,EECTL,CFGDONE) \ + |_PER_FDEFAULT(PCI,EECTL,CFGERR) \ + |_PER_FDEFAULT(PCI,EECTL,EEAI) \ + |_PER_FDEFAULT(PCI,EECTL,EESZ) \ + |_PER_FDEFAULT(PCI,EECTL,READY) \ + |_PER_FDEFAULT(PCI,EECTL,EECNT) \ + ) + + #define PCI_EECTL_RMK(eecnt) \ + (Uint32)( \ + _PER_FMK(PCI,EECTL,EECNT,eecnt) \ + ) + + #define _PCI_EECTL_FGET(FIELD)\ + _PER_FGET(_PCI_EECTL_ADDR,PCI,EECTL,##FIELD) + + #define _PCI_EECTL_FSET(FIELD,field)\ + _PER_FSET(_PCI_EECTL_ADDR,PCI,EECTL,##FIELD,field) + + #define _PCI_EECTL_FSETS(FIELD,SYM)\ + _PER_FSETS(_PCI_EECTL_ADDR,PCI,EECTL,##FIELD,##SYM) + + + +/****************************************************************************\ +* _____________________ +* | | +* | T R C T L | +* |___________________| +* +* TRCTL - TR Control Register +* +* FIELDS (msb -> lsb) +* (rw) TRSTALL +* (rw) PRI +* (rw) PALLOC +* +\*****************************************************************************/ +#if (C64_SUPPORT) + #define _PCI_TRCTL_OFFSET 0 + + + + #define _PCI_TRCTL_ADDR 0x01C30000u + + + #define _PCI_TRCTL_TRSTALL_MASK 0x00000100u + #define _PCI_TRCTL_TRSTALL_SHIFT 0x00000008u + #define PCI_TRCTL_TRSTALL_DEFAULT 0x00000000u + #define PCI_TRCTL_TRSTALL_OF(x) _VALUEOF(x) + + #define _PCI_TRCTL_PRI_MASK 0x00000030u + #define _PCI_TRCTL_PRI_SHIFT 0x00000004u + #define PCI_TRCTL_PRI_DEFAULT 0x00000002u + #define PCI_TRCTL_PRI_OF(x) _VALUEOF(x) + + #define _PCI_TRCTL_PALLOC_MASK 0x0000000Fu + #define _PCI_TRCTL_PALLOC_SHIFT 0x00000000u + #define PCI_TRCTL_PALLOC_DEFAULT 0x00000004u + #define PCI_TRCTL_PALLOC_OF(x) _VALUEOF(x) + + #define PCI_TRCTL_OF(x) _VALUEOF(x) + + #define PCI_TRCTL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(PCI,TRCTL,TRSTALL) \ + |_PER_FDEFAULT(PCI,TRCTL,PRI) \ + |_PER_FDEFAULT(PCI,TRCTL,PALLOC) \ + ) + + #define PCI_TRCTL_RMK(trstall,pri,palloc) \ + (Uint32)( \ + _PER_FMK(PCI,TRCTL,TRSTALL,trctl) \ + |_PER_FMK(PCI,TRCTL,PRI,pri) \ + |_PER_FMK(PCI,TRCTL,PALLOC,palloc) \ + ) + + #define _PCI_TRCTL_FGET(FIELD)\ + _PER_FGET(_PCI_TRCTL_ADDR,PCI,TRCTL,##FIELD) + + #define _PCI_TRCTL_FSET(FIELD,field)\ + _PER_FSET(_PCI_TRCTL_ADDR,PCI,TRCTL,##FIELD,field) + + #define _PCI_TRCTL_FSETS(FIELD,SYM)\ + _PER_FSETS(_PCI_TRCTL_ADDR,PCI,TRCTL,##FIELD,##SYM) + + #endif +/******************************************************************************/ + +#endif /* PCI_SUPPORT */ +#endif /* _CSL_PCIHAL_H_ */ +/******************************************************************************\ +* End of pcihal.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_pll.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_pll.h new file mode 100644 index 0000000..0340697 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_pll.h @@ -0,0 +1,376 @@ +/******************************************************************************\ +* Step 1. Copyright (C) 2001 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_pll.h +* DATE CREATED.. 10/29/2001 +* LAST MODIFIED. 11/30/2001 +* 11/30/2003 Modified PLL_init() sequence to fix the PLL +* initialization problem +* 4/13/2005 Modified the sequence of the plldiv1 and plldiv2 +* according to the data sheet in PLL_config() and +* PLL_configArgs(). +\******************************************************************************/ + +/******************************************************************************\ +* Step 2. Private Macros - Include files - PLL_SUPPORT +\******************************************************************************/ +#ifndef _CSL_PLL_H_ +#define _CSL_PLL_H_ + +#include +#include +#include + +#if (PLL_SUPPORT) +/******************************************************************************\ +* Step 3. scope and inline control macros +\******************************************************************************/ +#ifdef __cplusplus +#define CSLAPI extern "C" far +#else +#define CSLAPI extern far +#endif + +#undef USEDEFS +#undef IDECL +#undef IDEF + +#ifdef _PLL_MOD_ + #define IDECL CSLAPI + #define USEDEFS + #define IDEF +#else + #ifdef _INLINE + #define IDECL static inline + #define USEDEFS + #define IDEF static inline + #else + #define IDECL CSLAPI + #endif +#endif + +/******************************************************************************\ +* Step 4. global macro declarations +\******************************************************************************/ +#define PLL_DIV0 0 +#define PLL_DIV1 1 +#define PLL_DIV2 2 +#define PLL_DIV3 3 + + +/*****************************************************************************\ +* Step 5. global typedef declarations +* Example : Config structure +* typedef struct { +* Uint32 rg1; +* Uint32 rg2; +* } PLL_Config; +\******************************************************************************/ +typedef struct{ + Uint32 pllcsr; + Uint32 pllm; + Uint32 plldiv0; + Uint32 plldiv1; + Uint32 plldiv2; + Uint32 plldiv3; + Uint32 oscdiv1; +}PLL_Config; + + +typedef struct { + Uint32 mdiv; + Uint32 d0ratio; + Uint32 d1ratio; + Uint32 d2ratio; + Uint32 d3ratio; + Uint32 od1ratio; + }PLL_Init; + +/******************************************************************************\ +* Step 6. global variable declarations +\******************************************************************************/ +/* private vars */ +extern far Uint32 _PLL_divAddr[4]; + + +/******************************************************************************\ +* Step 7. global function declarations +\******************************************************************************/ + +/* Private functions (If applicable)*/ + +static void plldelay(Uint32 count); + +/* API functions (Non-Inline function : Source file) */ +CSLAPI void PLL_wait100(); +CSLAPI Uint32 PLL_wait1(); + +/******************************************************************************\ +* Step 8. inline function declarations ( IDECL keyword) +\******************************************************************************/ +IDECL void PLL_config(PLL_Config *config); +IDECL void PLL_configArgs(Uint32 pllcsr, Uint32 pllm, Uint32 plldiv0, Uint32 plldiv1, Uint32 plldiv2, Uint32 plldiv3,Uint32 oscdiv1); +IDECL void PLL_getConfig(PLL_Config *config); + +IDECL void PLL_init(PLL_Init *init); + +IDECL void PLL_pwrdwn(); +IDECL void PLL_operational(); +IDECL void PLL_enable(); +IDECL void PLL_bypass(); +IDECL void PLL_reset(); +IDECL void PLL_deassert(); + + +IDECL Uint32 PLL_clkTest(); + +IDECL void PLL_enablePllDiv(Uint32 divId); +IDECL void PLL_disablePllDiv(Uint32 divId); + +IDECL void PLL_enableOscDiv(); +IDECL void PLL_disableOscDiv(); + +IDECL void PLL_setMultiplier(Uint32 val); +IDECL void PLL_setPllRatio(Uint32 divId,Uint32 val); +IDECL void PLL_setOscRatio(Uint32 val); + +IDECL Uint32 PLL_getMultiplier(); +IDECL Uint32 PLL_getPllRatio(Uint32 divnum); +IDECL Uint32 PLL_getOscRatio(); + +/******************************************************************************\ +* Step 9. inline function definitions ( #if USEDEF - IDEF keywords) +\******************************************************************************/ + +#ifdef USEDEFS +/*----------------------------------------------------------------------------*/ +IDEF void PLL_pwrdwn(){ + PLL_FSETS(PLLCSR,PLLEN,BYPASS); /* Bypass mode PLLEN = 0 */ + PLL_FSETS(PLLCSR,PLLPWRDN,YES); /* PwrDwn mode */ + +} +/*----------------------------------------------------------------------------*/ +IDEF void PLL_operational(){ + PLL_FSETS(PLLCSR,PLLPWRDN,NO); /* Operational mode */ + PLL_FSETS(PLLDIV0,D0EN,ENABLE); /* Enable D0 path */ + PLL_FSETS(PLLCSR,PLLEN,ENABLE); /* Enable PLLEN = 1 */ +} +/*----------------------------------------------------------------------------*/ +IDEF void PLL_enable(){ + PLL_FSETS(PLLCSR,PLLEN,ENABLE); /* Bypass mode PLLEN = 1 */ +} +/*----------------------------------------------------------------------------*/ +IDEF void PLL_bypass(){ + PLL_FSETS(PLLCSR,PLLEN,BYPASS); /* Bypass mode PLLEN = 0 */ +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 PLL_clkTest(){ + return(PLL_FGET(PLLCSR,STABLE)); +} +/*----------------------------------------------------------------------------*/ +IDEF void PLL_reset(){ + PLL_FSETS(PLLCSR,PLLRST,1); /* reset mode */ +} +/*----------------------------------------------------------------------------*/ +IDEF void PLL_deassert(){ + PLL_FSETS(PLLCSR,PLLRST,0); /* deassert PLL */ +} +/*----------------------------------------------------------------------------*/ +IDEF void PLL_enablePllDiv(Uint32 divId){ + (*(volatile Uint32*) _PLL_divAddr[divId]) |=(0x00008000u); +} +/*----------------------------------------------------------------------------*/ +IDEF void PLL_disablePllDiv(Uint32 divId){ + (*(volatile Uint32*) _PLL_divAddr[divId]) &=~(0x00008000u); +} +/*----------------------------------------------------------------------------*/ +IDEF void PLL_enableOscDiv(){ + PLL_FSET(OSCDIV1,OD1EN,1); +} +/*----------------------------------------------------------------------------*/ +IDEF void PLL_disableOscDiv(){ + PLL_FSET(OSCDIV1,OD1EN,0); +} +/*----------------------------------------------------------------------------*/ +IDEF void PLL_setPllRatio(Uint32 divId, Uint32 val){ + Uint32 tmp= ((*(volatile Uint32*) _PLL_divAddr[divId]) & 0xFFFFFFE0u); + (*(volatile Uint32*) _PLL_divAddr[divId]) =(val | tmp ); +} +/*----------------------------------------------------------------------------*/ +IDEF void PLL_setOscRatio(Uint32 val){ + PLL_FSET(OSCDIV1,RATIO,val); +} +/*----------------------------------------------------------------------------*/ +IDEF void PLL_setMultiplier(Uint32 val){ + PLL_FSET(PLLM,PLLM,val); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 PLL_getPllRatio(Uint32 divId){ + return (Uint32)((*(volatile Uint32*) _PLL_divAddr[divId]) & 0x0000001Fu); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 PLL_getOscRatio(){ + return(PLL_FGET(OSCDIV1,RATIO)); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 PLL_getMultiplier(){ + return(PLL_FGET(PLLM,PLLM)); +} + +/*----------------------------------------------------------------------------*/ +IDEF void PLL_init(PLL_Init *init) { + + Uint32 gie ; + gie = IRQ_globalDisable(); + + PLL_FSETS(PLLCSR,PLLEN,BYPASS); /* Bypass mode PLLEN = 0 */ + + plldelay(20); + + PLL_FSETS(PLLCSR,PLLRST,1); /* reset mode */ + + plldelay(20); + + // Set main multiplier/divisor + PLL_RSET(PLLM,init->mdiv); + PLL_RSET(PLLDIV0, PLL_PLLDIV0_RMK(0,init->d0ratio)); + PLL_RSET(OSCDIV1,PLL_OSCDIV1_RMK(0,init->od1ratio)); + + // Set DSP clock + PLL_RSET(PLLDIV1,PLL_PLLDIV1_RMK(1,init->d1ratio)); + + // Set EMIF clock + PLL_RSET(PLLDIV3,PLL_PLLDIV3_RMK(0,init->d3ratio)); + + plldelay(20); + + // Take PLL out of reset + PLL_FSETS(PLLCSR,PLLRST,0); + plldelay(1500); + + // Enable PLL + PLL_FSETS(PLLCSR,PLLEN,ENABLE); + plldelay(20); + + IRQ_globalRestore(gie); +} + + +/*----------------------------------------------------------------------------*/ +IDEF void PLL_config(PLL_Config *config) { + Uint32 gie; + volatile Uint32 *base; + register Uint32 x0,x1,x2,x3,x4,x5,x6; + + gie = IRQ_globalDisable(); + + x0 = config->pllcsr; + x1 = config->pllm; + x2 = config->plldiv0; + x3 = config->plldiv1; + x4 = config->plldiv2; + x5 = config->plldiv3; + x6 = config->oscdiv1; + + + base = (volatile Uint32 *)(_PLL_BASE_ADDR); + + base[_PLL_PLLM_OFFSET] = x1; + base[_PLL_PLLDIV0_OFFSET] = x2; + if ( base[_PLL_PLLDIV1_OFFSET] > x3 ) { + base[_PLL_PLLDIV1_OFFSET] = x3; + base[_PLL_PLLDIV2_OFFSET] = x4; + } + else { + base[_PLL_PLLDIV2_OFFSET] = x4; + base[_PLL_PLLDIV1_OFFSET] = x3; + } + + base[_PLL_PLLDIV3_OFFSET] = x5; + base[_PLL_OSCDIV1_OFFSET] = x6; + base[_PLL_PLLCSR_OFFSET] = x0; + + IRQ_globalRestore(gie); + +} + +/*----------------------------------------------------------------------------*/ +IDEF void PLL_configArgs(Uint32 pllcsr, Uint32 pllm, Uint32 plldiv0, Uint32 plldiv1, Uint32 plldiv2, Uint32 plldiv3,Uint32 oscdiv1){ + + Uint32 gie; + volatile Uint32 *base; + gie = IRQ_globalDisable(); + + base = (volatile Uint32 *)(_PLL_BASE_ADDR); + + base[_PLL_PLLM_OFFSET] = pllm; + base[_PLL_PLLDIV0_OFFSET] = plldiv0; + if ( base[_PLL_PLLDIV1_OFFSET] > plldiv1) { + base[_PLL_PLLDIV1_OFFSET] = plldiv1; + base[_PLL_PLLDIV2_OFFSET] = plldiv2; + } + else { + base[_PLL_PLLDIV2_OFFSET] = plldiv2; + base[_PLL_PLLDIV1_OFFSET] = plldiv1; + } + base[_PLL_PLLDIV3_OFFSET] = plldiv3; + base[_PLL_OSCDIV1_OFFSET] = oscdiv1; + base[_PLL_PLLCSR_OFFSET] = pllcsr; + + IRQ_globalRestore(gie); +} + + +/*----------------------------------------------------------------------------*/ +IDEF void PLL_getConfig(PLL_Config *config) { + Uint32 gie; + volatile Uint32 *base; + register Uint32 x0,x1,x2,x3,x4,x5,x6; + + gie = IRQ_globalDisable(); + + base = (volatile Uint32 *)(_PLL_BASE_ADDR); + + x0 = base[_PLL_PLLCSR_OFFSET]; + x1 = base[_PLL_PLLM_OFFSET]; + x2 = base[_PLL_PLLDIV0_OFFSET]; + x3 = base[_PLL_PLLDIV1_OFFSET]; + x4 = base[_PLL_PLLDIV2_OFFSET]; + x5 = base[_PLL_PLLDIV3_OFFSET]; + x6 = base[_PLL_OSCDIV1_OFFSET]; + + config->pllcsr = x0; + config->pllm = x1; + config->plldiv0 = x2; + config->plldiv1 = x3; + config->plldiv2 = x4; + config->plldiv3 = x5; + config->oscdiv1 = x6; + + IRQ_globalRestore(gie); + +} + + + +/*----------------------------------------------------------------------------*/ +#endif /* USEDEFS */ + +/* Local software delay function */ + +static void plldelay(Uint32 count){ + Uint32 i = count; + while(i--){ + asm(" NOP 1"); + } +} + +/******************************************************************************\ +* Step 10. #endif for PLL_SUPPORT and CSL_PLL_H Macro + Footer +\******************************************************************************/ +#endif /* PLL_SUPPORT */ +#endif /* _CSL_PLL_H_ */ +/******************************************************************************\ +* End of csl_module.h +\******************************************************************************/ diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_pllhal.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_pllhal.h new file mode 100644 index 0000000..ad734f3 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_pllhal.h @@ -0,0 +1,686 @@ +/****************************************************************************\ +* Copyright (C) 2001 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* MODULE NAME... PLL +* FILENAME...... csl_pllhal.h +* DATE CREATED.. Tue 10-30-2001 at 9:08:46a +* DATE MODIFIED. Fri 04-16-2004 Modified PID field default values(CLASS,TYPE). +*------------------------------------------------------------------------------ +* HISTORY: +*------------------------------------------------------------------------------ +* DESCRIPTION: (HAL interface file for the PLL module) +* +* REGISTERS +* +* PID - "PLL Controller Peripheral Identification Register" +* PLLCSR - "Control Status register" +* PLLM - "Multiplier Control register" (PLLM) +* PLLDIV0 - "PLL Divider 0 register" +* PLLDIV1 - "PLL Divider 1 register" +* PLLDIV2 - "PLL Divider 2 register" +* PLLDIV3 - "PLL Divider 3 register" +* OSCDIV1 - "Oscillator Divider 1 register" +* +\***************************************************************************/ + +#ifndef _CSL_PLLHAL_H_ +#define _CSL_PLLHAL_H_ + +/*****************************\ +* Include files +\*****************************/ +#include +#include + +#if (PLL_SUPPORT) +/************************************************************\ +* Misc. Declarations +\************************************************************/ + + #define _PLL_BASE_ADDR 0x01B7C000u + +/************************************************************\ +* Module level register/field access macros +\************************************************************/ + + /* ------------------- */ + /* FIELD MAKE MACROS */ + /* ------------------- */ + + #define PLL_FMK(REG,FIELD,x)\ + _PER_FMK(PLL,##REG,##FIELD,x) + + #define PLL_FMKS(REG,FIELD,SYM)\ + _PER_FMKS(PLL,##REG,##FIELD,##SYM) + + /* ---------------------------------- */ + /* RAW REGISTER/FIELD ACCESS MACROS */ + /* ---------------------------------- */ + + #define PLL_REG(REG) (*(volatile Uint32*) (_PLL_##REG##_ADDR)) + + #define PLL_ADDR(REG)\ + _PLL_##REG##_ADDR + + #define PLL_RGET(REG)\ + _PER_RGET(_PLL_##REG##_ADDR,PLL,##REG) + + #define PLL_RSET(REG,x)\ + _PER_RSET(_PLL_##REG##_ADDR,PLL,##REG,x) + + #define PLL_FGET(REG,FIELD)\ + _PLL_##REG##_FGET(##FIELD) + + #define PLL_FSET(REG,FIELD,x)\ + _PLL_##REG##_FSET(##FIELD,x) + + #define PLL_FSETS(REG,FIELD,SYM)\ + _PLL_##REG##_FSETS(##FIELD,##SYM) + + /* -------------------------------------------- */ + /* ADDRESS BASED REGISTER/FIELD ACCESS MACROS */ + /* -------------------------------------------- */ + + #define PLL_RGETA(addr,REG)\ + _PER_RGET(addr,PLL,##REG) + + #define PLL_RSETA(addr,REG,x)\ + _PER_RSET(addr,PLL,##REG,x) + + #define PLL_FGETA(addr,REG,FIELD)\ + _PER_FGET(addr,PLL,##REG,##FIELD) + + #define PLL_FSETA(addr,REG,FIELD,x)\ + _PER_FSET(addr,PLL,##REG,##FIELD,x) + + #define PLL_FSETSA(addr,REG,FIELD,SYM)\ + _PER_FSETS(addr,PLL,##REG,##FIELD,##SYM) + + + +/*******************************************************************\ +* +* ________________ +* | | +* | PID | +* |________________| +* +* PID - "Peripheral Identification register" +* +* FIELDS (msb -> lsb) +* (r) TYPE +* (r) CLASS +* (r) REV +* +\*******************************************************************/ + + #define _PLL_PID_OFFSET 0 + #define _PLL_PID_ADDR 0x01B7C000u + #define PLL_PID PLL_REG(PID) + + + #define _PLL_PID_TYPE_MASK 0x00FF0000u + #define _PLL_PID_TYPE_SHIFT 0x00000010u + #define PLL_PID_TYPE_DEFAULT 0x00000001u + #define PLL_PID_TYPE_OF(x) _VALUEOF(x) + + #define _PLL_PID_CLASS_MASK 0x0000FF00u + #define _PLL_PID_CLASS_SHIFT 0x00000008u + #define PLL_PID_CLASS_DEFAULT 0x00000008u + #define PLL_PID_CLASS_OF(x) _VALUEOF(x) + + #define _PLL_PID_REV_MASK 0x000000FFu + #define _PLL_PID_REV_SHIFT 0x00000000u + #define PLL_PID_REV_DEFAULT 0x00000001u + #define PLL_PID_REV_OF(x) _VALUEOF(x) + + /*============= Register DEFAULT macro ==============*/ + #define PLL_PID_DEFAULT (Uint32) (\ + _PER_FDEFAULT(PLL,PID,TYPE) \ + |_PER_FDEFAULT(PLL,PID,CLASS) \ + |_PER_FDEFAULT(PLL,PID,REV) \ + ) + + + /*============= Register MAKE _RMK macro ==============*/ + + /*============= Register Access macros ==============*/ + #define _PLL_PID_FGET(FIELD)\ + _PER_FGET(_PLL_PID_ADDR,PLL,PID,##FIELD) + + #define _PLL_PID_FSET(FIELD,field)\ + _PER_FSET(_PLL_PID_ADDR,PLL,PID,##FIELD,field) + + #define _PLL_PID_FSETS(FIELD,SYM)\ + _PER_FSETS(_PLL_PID_ADDR,PLL,PID,##FIELD,##SYM) + + + +/*******************************************************************\ +* +* ________________ +* | | +* | PLLCSR | +* |________________| +* +* PLLCSR - "Control Status register" +* +* FIELDS (msb -> lsb) +* (r) STABLE +* (rw) PLLRST +* (rw) PLLPWRDN +* (rw) PLLEN +* +\*******************************************************************/ + + #define _PLL_PLLCSR_OFFSET 64 + #define _PLL_PLLCSR_ADDR (_PLL_BASE_ADDR + 0x100u) + #define PLL_PLLCSR PLL_REG(PLLCSR) + + + #define _PLL_PLLCSR_STABLE_MASK 0x00000040u + #define _PLL_PLLCSR_STABLE_SHIFT 0x00000006u + #define PLL_PLLCSR_STABLE_DEFAULT 0x00000001u + #define PLL_PLLCSR_STABLE_OF(x) _VALUEOF(x) + + #define _PLL_PLLCSR_PLLRST_MASK 0x00000008u + #define _PLL_PLLCSR_PLLRST_SHIFT 0x00000003u + #define PLL_PLLCSR_PLLRST_DEFAULT 0x00000001u + #define PLL_PLLCSR_PLLRST_OF(x) _VALUEOF(x) + #define PLL_PLLCSR_PLLRST_1 0x00000001u + #define PLL_PLLCSR_PLLRST_0 0x00000000u + + #define _PLL_PLLCSR_PLLPWRDN_MASK 0x00000002u + #define _PLL_PLLCSR_PLLPWRDN_SHIFT 0x00000001u + #define PLL_PLLCSR_PLLPWRDN_DEFAULT 0x00000000u + #define PLL_PLLCSR_PLLPWRDN_OF(x) _VALUEOF(x) + #define PLL_PLLCSR_PLLPWRDN_YES 0x00000001u + #define PLL_PLLCSR_PLLPWRDN_NO 0x00000000u + + #define _PLL_PLLCSR_PLLEN_MASK 0x00000001u + #define _PLL_PLLCSR_PLLEN_SHIFT 0x00000000u + #define PLL_PLLCSR_PLLEN_DEFAULT 0x00000000u + #define PLL_PLLCSR_PLLEN_OF(x) _VALUEOF(x) + #define PLL_PLLCSR_PLLEN_ENABLE 0x00000001u + #define PLL_PLLCSR_PLLEN_BYPASS 0x00000000u + + /*============= Register DEFAULT macro ==============*/ + #define PLL_PLLCSR_DEFAULT (Uint32) (\ + _PER_FDEFAULT(PLL,PLLCSR,STABLE) \ + |_PER_FDEFAULT(PLL,PLLCSR,PLLRST) \ + |_PER_FDEFAULT(PLL,PLLCSR,PLLPWRDN) \ + |_PER_FDEFAULT(PLL,PLLCSR,PLLEN) \ + ) + + + /*============= Register MAKE _RMK macro ==============*/ + #define PLL_PLLCSR_RMK(pllrst,pllpwrdn,pllen) \ + (Uint32) (\ + _PER_FMK(PLL,PLLCSR,PLLRST,pllrst) \ + |_PER_FMK(PLL,PLLCSR,PLLPWRDN,pllpwrdn) \ + |_PER_FMK(PLL,PLLCSR,PLLEN,pllen) \ + ) + + /*============= Register Access macros ==============*/ + #define _PLL_PLLCSR_FGET(FIELD)\ + _PER_FGET(_PLL_PLLCSR_ADDR,PLL,PLLCSR,##FIELD) + + #define _PLL_PLLCSR_FSET(FIELD,field)\ + _PER_FSET(_PLL_PLLCSR_ADDR,PLL,PLLCSR,##FIELD,field) + + #define _PLL_PLLCSR_FSETS(FIELD,SYM)\ + _PER_FSETS(_PLL_PLLCSR_ADDR,PLL,PLLCSR,##FIELD,##SYM) + + + +/*******************************************************************\ +* +* ________________ +* | | +* PLLM +* |________________| +* +* PLLM - "Multiplier Control register" +* +* FIELDS (msb -> lsb) +* (rw) PLLM +* +\*******************************************************************/ + + #define _PLL_PLLM_OFFSET 68 + #define _PLL_PLLM_ADDR (_PLL_BASE_ADDR + 0x110u) + #define PLL_PLLM PLL_REG(PLLM) + + + #define _PLL_PLLM_PLLM_MASK 0x0000001Fu + #define _PLL_PLLM_PLLM_SHIFT 0x00000000u + #define PLL_PLLM_PLLM_DEFAULT 0x00000007u + #define PLL_PLLM_PLLM_OF(x) _VALUEOF(x) + + /*============= Register DEFAULT macro ==============*/ + #define PLL_PLLM_DEFAULT (Uint32) (\ + _PER_FDEFAULT(PLL,PLLM,PLLM) \ + ) + + + /*============= Register MAKE _RMK macro ==============*/ + #define PLL_PLLM_RMK(pllm) \ + (Uint32) (\ + _PER_FMK(PLL,PLLM,PLLM,pllm) \ + ) + + /*============= Register Access macros ==============*/ + #define _PLL_PLLM_FGET(FIELD)\ + _PER_FGET(_PLL_PLLM_ADDR,PLL,PLLM,##FIELD) + + #define _PLL_PLLM_FSET(FIELD,field)\ + _PER_FSET(_PLL_PLLM_ADDR,PLL,PLLM,##FIELD,field) + + #define _PLL_PLLM_FSETS(FIELD,SYM)\ + _PER_FSETS(_PLL_PLLM_ADDR,PLL,PLLM,##FIELD,##SYM) + + + +/*******************************************************************\ +* +* ________________ +* | | +* | PLLDIV0 | +* |________________| +* +* PLLDIV0 - "PLL Divider 0 register" +* +* FIELDS (msb -> lsb) +* (rw) D0EN +* (rw) RATIO +* +\*******************************************************************/ + + #define _PLL_PLLDIV0_OFFSET 69 + #define _PLL_PLLDIV0_ADDR (_PLL_BASE_ADDR + 0x114u) + #define PLL_PLLDIV0 PLL_REG(PLLDIV0) + + + #define _PLL_PLLDIV0_D0EN_MASK 0x00008000u + #define _PLL_PLLDIV0_D0EN_SHIFT 0x0000000Fu + #define PLL_PLLDIV0_D0EN_DEFAULT 0x00000001u + #define PLL_PLLDIV0_D0EN_OF(x) _VALUEOF(x) + #define PLL_PLLDIV0_D0EN_ENABLE 0x00000001u + #define PLL_PLLDIV0_D0EN_DISABLE 0x00000000u + + #define _PLL_PLLDIV0_RATIO_MASK 0x0000001Fu + #define _PLL_PLLDIV0_RATIO_SHIFT 0x00000000u + #define PLL_PLLDIV0_RATIO_DEFAULT 0x00000000u + #define PLL_PLLDIV0_RATIO_OF(x) _VALUEOF(x) + + /*============= Register DEFAULT macro ==============*/ + #define PLL_PLLDIV0_DEFAULT (Uint32) (\ + _PER_FDEFAULT(PLL,PLLDIV0,D0EN) \ + |_PER_FDEFAULT(PLL,PLLDIV0,RATIO) \ + ) + + + /*============= Register MAKE _RMK macro ==============*/ + #define PLL_PLLDIV0_RMK(d0en,ratio) \ + (Uint32) (\ + _PER_FMK(PLL,PLLDIV0,D0EN,d0en) \ + |_PER_FMK(PLL,PLLDIV0,RATIO,ratio) \ + ) + + /*============= Register Access macros ==============*/ + #define _PLL_PLLDIV0_FGET(FIELD)\ + _PER_FGET(_PLL_PLLDIV0_ADDR,PLL,PLLDIV0,##FIELD) + + #define _PLL_PLLDIV0_FSET(FIELD,field)\ + _PER_FSET(_PLL_PLLDIV0_ADDR,PLL,PLLDIV0,##FIELD,field) + + #define _PLL_PLLDIV0_FSETS(FIELD,SYM)\ + _PER_FSETS(_PLL_PLLDIV0_ADDR,PLL,PLLDIV0,##FIELD,##SYM) + + + +/*******************************************************************\ +* +* ________________ +* | | +* | PLLDIV1 | +* |________________| +* +* PLLDIV1 - "PLL Divider 1 register" +* +* FIELDS (msb -> lsb) +* (rw) D1EN +* (rw) RATIO +* +\*******************************************************************/ + + #define _PLL_PLLDIV1_OFFSET 70 + #define _PLL_PLLDIV1_ADDR (_PLL_BASE_ADDR + 0x118u) + #define PLL_PLLDIV1 PLL_REG(PLLDIV1) + + + #define _PLL_PLLDIV1_D1EN_MASK 0x00008000u + #define _PLL_PLLDIV1_D1EN_SHIFT 0x0000000Fu + #define PLL_PLLDIV1_D1EN_DEFAULT 0x00000001u + #define PLL_PLLDIV1_D1EN_OF(x) _VALUEOF(x) + #define PLL_PLLDIV1_D1EN_ENABLE 0x00000001u + #define PLL_PLLDIV1_D1EN_DISABLE 0x00000000u + + #define _PLL_PLLDIV1_RATIO_MASK 0x0000001Fu + #define _PLL_PLLDIV1_RATIO_SHIFT 0x00000000u + #define PLL_PLLDIV1_RATIO_DEFAULT 0x00000000u + #define PLL_PLLDIV1_RATIO_OF(x) _VALUEOF(x) + + /*============= Register DEFAULT macro ==============*/ + #define PLL_PLLDIV1_DEFAULT (Uint32) (\ + _PER_FDEFAULT(PLL,PLLDIV1,D1EN) \ + |_PER_FDEFAULT(PLL,PLLDIV1,RATIO) \ + ) + + + /*============= Register MAKE _RMK macro ==============*/ + #define PLL_PLLDIV1_RMK(d1en,ratio) \ + (Uint32) (\ + _PER_FMK(PLL,PLLDIV1,D1EN,d1en) \ + |_PER_FMK(PLL,PLLDIV1,RATIO,ratio) \ + ) + + /*============= Register Access macros ==============*/ + #define _PLL_PLLDIV1_FGET(FIELD)\ + _PER_FGET(_PLL_PLLDIV1_ADDR,PLL,PLLDIV1,##FIELD) + + #define _PLL_PLLDIV1_FSET(FIELD,field)\ + _PER_FSET(_PLL_PLLDIV1_ADDR,PLL,PLLDIV1,##FIELD,field) + + #define _PLL_PLLDIV1_FSETS(FIELD,SYM)\ + _PER_FSETS(_PLL_PLLDIV1_ADDR,PLL,PLLDIV1,##FIELD,##SYM) + + + +/*******************************************************************\ +* +* ________________ +* | | +* | PLLDIV2 | +* |________________| +* +* PLLDIV2 - "PLL Divider 2 register" +* +* FIELDS (msb -> lsb) +* (rw) D2EN +* (rw) RATIO +* +\*******************************************************************/ + + #define _PLL_PLLDIV2_OFFSET 71 + #define _PLL_PLLDIV2_ADDR (_PLL_BASE_ADDR + 0x11Cu) + #define PLL_PLLDIV2 PLL_REG(PLLDIV2) + + + #define _PLL_PLLDIV2_D2EN_MASK 0x00008000u + #define _PLL_PLLDIV2_D2EN_SHIFT 0x0000000Fu + #define PLL_PLLDIV2_D2EN_DEFAULT 0x00000001u + #define PLL_PLLDIV2_D2EN_OF(x) _VALUEOF(x) + #define PLL_PLLDIV2_D2EN_ENABLE 0x00000001u + #define PLL_PLLDIV2_D2EN_DISABLE 0x00000000u + + #define _PLL_PLLDIV2_RATIO_MASK 0x0000001Fu + #define _PLL_PLLDIV2_RATIO_SHIFT 0x00000000u + #define PLL_PLLDIV2_RATIO_DEFAULT 0x00000001u + #define PLL_PLLDIV2_RATIO_OF(x) _VALUEOF(x) + + /*============= Register DEFAULT macro ==============*/ + #define PLL_PLLDIV2_DEFAULT (Uint32) (\ + _PER_FDEFAULT(PLL,PLLDIV2,D2EN) \ + |_PER_FDEFAULT(PLL,PLLDIV2,RATIO) \ + ) + + + /*============= Register MAKE _RMK macro ==============*/ + #define PLL_PLLDIV2_RMK(d2en,ratio) \ + (Uint32) (\ + _PER_FMK(PLL,PLLDIV2,D2EN,d2en) \ + |_PER_FMK(PLL,PLLDIV2,RATIO,ratio) \ + ) + + /*============= Register Access macros ==============*/ + #define _PLL_PLLDIV2_FGET(FIELD)\ + _PER_FGET(_PLL_PLLDIV2_ADDR,PLL,PLLDIV2,##FIELD) + + #define _PLL_PLLDIV2_FSET(FIELD,field)\ + _PER_FSET(_PLL_PLLDIV2_ADDR,PLL,PLLDIV2,##FIELD,field) + + #define _PLL_PLLDIV2_FSETS(FIELD,SYM)\ + _PER_FSETS(_PLL_PLLDIV2_ADDR,PLL,PLLDIV2,##FIELD,##SYM) + + + +/*******************************************************************\ +* +* ________________ +* | | +* | PLLDIV3 | +* |________________| +* +* PLLDIV3 - "PLL Divider 3 register" +* +* FIELDS (msb -> lsb) +* (rw) D3EN +* (rw) RATIO +* +\*******************************************************************/ + + #define _PLL_PLLDIV3_OFFSET 72 + #define _PLL_PLLDIV3_ADDR (_PLL_BASE_ADDR + 0x120u) + #define PLL_PLLDIV3 PLL_REG(PLLDIV3) + + + #define _PLL_PLLDIV3_D3EN_MASK 0x00008000u + #define _PLL_PLLDIV3_D3EN_SHIFT 0x0000000Fu + #define PLL_PLLDIV3_D3EN_DEFAULT 0x00000001u + #define PLL_PLLDIV3_D3EN_OF(x) _VALUEOF(x) + #define PLL_PLLDIV3_D3EN_ENABLE 0x00000001u + #define PLL_PLLDIV3_D3EN_DISABLE 0x00000000u + + #define _PLL_PLLDIV3_RATIO_MASK 0x0000001Fu + #define _PLL_PLLDIV3_RATIO_SHIFT 0x00000000u + #define PLL_PLLDIV3_RATIO_DEFAULT 0x00000001u + #define PLL_PLLDIV3_RATIO_OF(x) _VALUEOF(x) + + /*============= Register DEFAULT macro ==============*/ + #define PLL_PLLDIV3_DEFAULT (Uint32) (\ + _PER_FDEFAULT(PLL,PLLDIV3,D3EN) \ + |_PER_FDEFAULT(PLL,PLLDIV3,RATIO) \ + ) + + + /*============= Register MAKE _RMK macro ==============*/ + #define PLL_PLLDIV3_RMK(d3en,ratio) \ + (Uint32) (\ + _PER_FMK(PLL,PLLDIV3,D3EN,d3en) \ + |_PER_FMK(PLL,PLLDIV3,RATIO,ratio) \ + ) + + /*============= Register Access macros ==============*/ + #define _PLL_PLLDIV3_FGET(FIELD)\ + _PER_FGET(_PLL_PLLDIV3_ADDR,PLL,PLLDIV3,##FIELD) + + #define _PLL_PLLDIV3_FSET(FIELD,field)\ + _PER_FSET(_PLL_PLLDIV3_ADDR,PLL,PLLDIV3,##FIELD,field) + + #define _PLL_PLLDIV3_FSETS(FIELD,SYM)\ + _PER_FSETS(_PLL_PLLDIV3_ADDR,PLL,PLLDIV3,##FIELD,##SYM) + + + +/*******************************************************************\ +* +* ________________ +* | | +* | OSCDIV1 | +* |________________| +* +* OSCDIV1 - "Oscillator Divider 1 register" +* +* FIELDS (msb -> lsb) +* (rw) OD1EN +* (rw) RATIO +* +\*******************************************************************/ + + #define _PLL_OSCDIV1_OFFSET 73 + #define _PLL_OSCDIV1_ADDR (_PLL_BASE_ADDR + 0x124u) + + #define PLL_OSCDIV1 PLL_REG(OSCDIV1) + + + #define _PLL_OSCDIV1_OD1EN_MASK 0x00008000u + #define _PLL_OSCDIV1_OD1EN_SHIFT 0x0000000Fu + #define PLL_OSCDIV1_OD1EN_DEFAULT 0x00000001u + #define PLL_OSCDIV1_OD1EN_OF(x) _VALUEOF(x) + #define PLL_OSCDIV1_OD1EN_ENABLE 0x00000001u + #define PLL_OSCDIV1_OD1EN_DISABLE 0x00000000u + + #define _PLL_OSCDIV1_RATIO_MASK 0x0000001Fu + #define _PLL_OSCDIV1_RATIO_SHIFT 0x00000000u + #define PLL_OSCDIV1_RATIO_DEFAULT 0x00000007u + #define PLL_OSCDIV1_RATIO_OF(x) _VALUEOF(x) + + /*============= Register DEFAULT macro ==============*/ + #define PLL_OSCDIV1_DEFAULT (Uint32) (\ + _PER_FDEFAULT(PLL,OSCDIV1,OD1EN) \ + |_PER_FDEFAULT(PLL,OSCDIV1,RATIO) \ + ) + + + /*============= Register MAKE _RMK macro ==============*/ + #define PLL_OSCDIV1_RMK(od1en,ratio) \ + (Uint32) (\ + _PER_FMK(PLL,OSCDIV1,OD1EN,od1en) \ + |_PER_FMK(PLL,OSCDIV1,RATIO,ratio) \ + ) + + /*============= Register Access macros ==============*/ + #define _PLL_OSCDIV1_FGET(FIELD)\ + _PER_FGET(_PLL_OSCDIV1_ADDR,PLL,OSCDIV1,##FIELD) + + #define _PLL_OSCDIV1_FSET(FIELD,field)\ + _PER_FSET(_PLL_OSCDIV1_ADDR,PLL,OSCDIV1,##FIELD,field) + + #define _PLL_OSCDIV1_FSETS(FIELD,SYM)\ + _PER_FSETS(_PLL_OSCDIV1_ADDR,PLL,OSCDIV1,##FIELD,##SYM) + + + +/*******************************************************************\ +* +* ________________ +* | | +* WAKEUP +* |________________| +* +* WAKEUP - "Wakeup register" Not Documented +* +* FIELDS (msb -> lsb) +* (rw) WKEN +* +\*******************************************************************/ + + #define _PLL_WAKEUP_OFFSET 76 + #define _PLL_WAKEUP_ADDR (_PLL_BASE_ADDR + 0x130u) + #define PLL_WAKEUP PLL_REG(WAKEUP) + + + #define _PLL_WAKEUP_WKEN_MASK 0xFFFFFFFFu + #define _PLL_WAKEUP_WKEN_SHIFT 0x00000000u + #define PLL_WAKEUP_WKEN_DEFAULT 0x00000000u + #define PLL_WAKEUP_WKEN_OF(x) _VALUEOF(x) + #define PLL_WAKEUP_WKEN_ENABLE 0x00000001u + #define PLL_WAKEUP_WKEN_DISABLE 0x00000000u + + /*============= Register DEFAULT macro ==============*/ + #define PLL_WAKEUP_DEFAULT (Uint32) (\ + _PER_FDEFAULT(PLL,WAKEUP,WKEN) \ + ) + + + /*============= Register MAKE _RMK macro ==============*/ + #define PLL_WAKEUP_RMK(wken) \ + (Uint32) (\ + _PER_FMK(PLL,WAKEUP,WKEN,wken) \ + ) + + /*============= Register Access macros ==============*/ + #define _PLL_WAKEUP_FGET(FIELD)\ + _PER_FGET(_PLL_WAKEUP_ADDR,PLL,WAKEUP,##FIELD) + + #define _PLL_WAKEUP_FSET(FIELD,field)\ + _PER_FSET(_PLL_WAKEUP_ADDR,PLL,WAKEUP,##FIELD,field) + + #define _PLL_WAKEUP_FSETS(FIELD,SYM)\ + _PER_FSETS(_PLL_WAKEUP_ADDR,PLL,WAKEUP,##FIELD,##SYM) + + + +/*******************************************************************\ +* +* ________________ +* | | +* CLK3SEL +* |________________| +* +* CLK3SEL - "Clkout3 Select register" Not Documented +* +* FIELDS (msb -> lsb) +* (rw) CK3SEL +* +\*******************************************************************/ + + #define _PLL_CLK3SEL_OFFSET 65 + #define _PLL_CLK3SEL_ADDR (_PLL_BASE_ADDR + 0x104u) + #define PLL_CLK3SEL PLL_REG(CLK3SEL) + + + #define _PLL_CLK3SEL_CK3SEL_MASK 0x0000000Fu + #define _PLL_CLK3SEL_CK3SEL_SHIFT 0x00000000u + #define PLL_CLK3SEL_CK3SEL_DEFAULT 0x00000000u + #define PLL_CLK3SEL_CK3SEL_OF(x) _VALUEOF(x) + #define PLL_CLK3SEL_CK3SEL_DISABLED 0x00000008u + #define PLL_CLK3SEL_CK3SEL_PTA 0x00000009u + #define PLL_CLK3SEL_CK3SEL_PTB 0x0000000Au + #define PLL_CLK3SEL_CK3SEL_PTC 0x0000000Bu + #define PLL_CLK3SEL_CK3SEL_PTD 0x0000000Cu + #define PLL_CLK3SEL_CK3SEL_PTE 0x0000000Du + #define PLL_CLK3SEL_CK3SEL_PTF 0x0000000Eu + #define PLL_CLK3SEL_CK3SEL_PTG 0x0000000Fu + + /*============= Register DEFAULT macro ==============*/ + #define PLL_CLK3SEL_DEFAULT (Uint32) (\ + _PER_FDEFAULT(PLL,CLK3SEL,CK3SEL) \ + ) + + + /*============= Register MAKE _RMK macro ==============*/ + #define PLL_CLK3SEL_RMK(ck3sel) \ + (Uint32) (\ + _PER_FMK(PLL,CLK3SEL,CK3SEL,ck3sel) \ + ) + + /*============= Register Access macros ==============*/ + #define _PLL_CLK3SEL_FGET(FIELD)\ + _PER_FGET(_PLL_CLK3SEL_ADDR,PLL,CLK3SEL,##FIELD) + + #define _PLL_CLK3SEL_FSET(FIELD,field)\ + _PER_FSET(_PLL_CLK3SEL_ADDR,PLL,CLK3SEL,##FIELD,field) + + #define _PLL_CLK3SEL_FSETS(FIELD,SYM)\ + _PER_FSETS(_PLL_CLK3SEL_ADDR,PLL,CLK3SEL,##FIELD,##SYM) + + +/*----------------------------------------------------------------------*/ +#endif /* PLL_SUPPORT */ +#endif /* _PLLHAL_H */ +/*******************************************************************\ +* End of file +\*******************************************************************/ diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_pwr.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_pwr.h new file mode 100644 index 0000000..5ac8a07 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_pwr.h @@ -0,0 +1,130 @@ +/******************************************************************************\ +* Copyright (C) 1999-2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_pwr.h +* DATE CREATED.. 11/11/1999 +* LAST MODIFIED. 10/03/2000 +\******************************************************************************/ +#ifndef _CSL_PWR_H_ +#define _CSL_PWR_H_ + +#include +#include +#include + + +#if (PWR_SUPPORT) +/******************************************************************************\ +* scope and inline control macros +\******************************************************************************/ +#ifdef __cplusplus +#define CSLAPI extern "C" far +#else +#define CSLAPI extern far +#endif + +#undef USEDEFS +#undef IDECL +#undef IDEF + +#ifdef _PWR_MOD_ + #define IDECL CSLAPI + #define USEDEFS + #define IDEF +#else + #ifdef _INLINE + #define IDECL static inline + #define USEDEFS + #define IDEF static inline + #else + #define IDECL CSLAPI + #endif +#endif + +/******************************************************************************\ +* global macro declarations +\******************************************************************************/ + + +/******************************************************************************\ +* global typedef declarations +\******************************************************************************/ +typedef enum { + PWR_NONE = 0x00, + PWR_PD1A = 0x09, + PWR_PD1B = 0x11, + PWR_PD2 = 0x1A, + PWR_PD3 = 0x1C, + PWR_IDLE = 0xFF +} PWR_Mode; + +#if (_PWR_COND1) + typedef struct { + Uint32 pdctl; + } PWR_Config; +#endif + + +/******************************************************************************\ +* global variable declarations +\******************************************************************************/ + + +/******************************************************************************\ +* global function declarations +\******************************************************************************/ + + +/******************************************************************************\ +* inline function declarations +\******************************************************************************/ +IDECL void PWR_powerDown(PWR_Mode mode); +#if (_PWR_COND1) + IDECL void PWR_config(PWR_Config *config); + IDECL void PWR_configArgs(Uint32 pdctl); + IDECL void PWR_getConfig(PWR_Config *config); +#endif + + +/******************************************************************************\ +* inline function definitions +\******************************************************************************/ +#ifdef USEDEFS +/*----------------------------------------------------------------------------*/ +IDEF void PWR_powerDown(PWR_Mode mode) { + if (mode == PWR_IDLE) { + asm(" IDLE"); + } else { + CHIP_FSET(CSR,PWRD,(Uint32)mode); + } +} +/*----------------------------------------------------------------------------*/ +#if (_PWR_COND1) + IDEF void PWR_config(PWR_Config *config) { + PWR_RSET(PDCTL,config->pdctl); + } +#endif +/*----------------------------------------------------------------------------*/ +#if (_PWR_COND1) + IDEF void PWR_configArgs(Uint32 pdctl) { + PWR_RSET(PDCTL,pdctl); + } +#endif +/*----------------------------------------------------------------------------*/ +#if (_PWR_COND1) + IDEF void PWR_getConfig(PWR_Config *config) { + volatile PWR_Config* cfg = (volatile PWR_Config*)config; + cfg->pdctl = PWR_RGET(PDCTL); + } +#endif +/*----------------------------------------------------------------------------*/ +#endif /* USEDEFS */ + + +#endif /* PWR_SUPPORT */ +#endif /* _CSL_PWR_H_ */ +/******************************************************************************\ +* End of csl_pwr.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_pwrhal.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_pwrhal.h new file mode 100644 index 0000000..3dbc7e5 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_pwrhal.h @@ -0,0 +1,174 @@ +/******************************************************************************\ +* Copyright (C) 1999-2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_pwrhal.h +* DATE CREATED.. 11/11/1999 +* LAST MODIFIED. 11/06/2000 +*------------------------------------------------------------------------------ +* REGISTERS +* +* PDCTL - power down control register +* +\******************************************************************************/ +#ifndef _CSL_PWRHAL_H_ +#define _CSL_PWRHAL_H_ + +#include +#include + +#if (PWR_SUPPORT) +/******************************************************************************\ +* MISC section +\******************************************************************************/ +#define _PWR_COND1 (CHIP_6202|CHIP_6203|CHIP_6411) + +/******************************************************************************\ +* module level register/field access macros +\******************************************************************************/ + + /* ----------------- */ + /* FIELD MAKE MACROS */ + /* ----------------- */ + + #define PWR_FMK(REG,FIELD,x)\ + _PER_FMK(PWR,##REG,##FIELD,x) + + #define PWR_FMKS(REG,FIELD,SYM)\ + _PER_FMKS(PWR,##REG,##FIELD,##SYM) + + + /* -------------------------------- */ + /* RAW REGISTER/FIELD ACCESS MACROS */ + /* -------------------------------- */ + + #define PWR_ADDR(REG)\ + _PWR_##REG##_ADDR + + #define PWR_RGET(REG)\ + _PER_RGET(_PWR_##REG##_ADDR,PWR,##REG) + + #define PWR_RSET(REG,x)\ + _PER_RSET(_PWR_##REG##_ADDR,PWR,##REG,x) + + #define PWR_FGET(REG,FIELD)\ + _PWR_##REG##_FGET(##FIELD) + + #define PWR_FSET(REG,FIELD,x)\ + _PWR_##REG##_FSET(##FIELD,##x) + + #define PWR_FSETS(REG,FIELD,SYM)\ + _PWR_##REG##_FSETS(##FIELD,##SYM) + + + /* ------------------------------------------ */ + /* ADDRESS BASED REGISTER/FIELD ACCESS MACROS */ + /* ------------------------------------------ */ + + #define PWR_RGETA(addr,REG)\ + _PER_RGET(addr,PWR,##REG) + + #define PWR_RSETA(addr,REG,x)\ + _PER_RSET(addr,PWR,##REG,x) + + #define PWR_FGETA(addr,REG,FIELD)\ + _PER_FGET(addr,PWR,##REG,##FIELD) + + #define PWR_FSETA(addr,REG,FIELD,x)\ + _PER_FSET(addr,PWR,##REG,##FIELD,x) + + #define PWR_FSETSA(addr,REG,FIELD,SYM)\ + _PER_FSETS(addr,PWR,##REG,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | P D C T L | +* |___________________| +* +* PDCTL - powerdown control register +* +* FIELDS (msb -> lsb) +* (rw) MCBSP2 +* (rw) MCBSP1 +* (rw) MCBSP0 +* (rw) EMIF +* (rw) DMA +* +\******************************************************************************/ +#if (_PWR_COND1) + #define _PWR_PDCTL_ADDR 0x019C0200u + + #define _PWR_PDCTL_MCBSP2_MASK 0x00000010u + #define _PWR_PDCTL_MCBSP2_SHIFT 0x00000004u + #define PWR_PDCTL_MCBSP2_DEFAULT 0x00000000u + #define PWR_PDCTL_MCBSP2_OF(x) _VALUEOF(x) + #define PWR_PDCTL_MCBSP2_CLKON 0x00000000u + #define PWR_PDCTL_MCBSP2_CLKOFF 0x00000001u + + #define _PWR_PDCTL_MCBSP1_MASK 0x00000008u + #define _PWR_PDCTL_MCBSP1_SHIFT 0x00000003u + #define PWR_PDCTL_MCBSP1_DEFAULT 0x00000000u + #define PWR_PDCTL_MCBSP1_OF(x) _VALUEOF(x) + #define PWR_PDCTL_MCBSP1_CLKON 0x00000000u + #define PWR_PDCTL_MCBSP1_CLKOFF 0x00000001u + + #define _PWR_PDCTL_MCBSP0_MASK 0x00000004u + #define _PWR_PDCTL_MCBSP0_SHIFT 0x00000002u + #define PWR_PDCTL_MCBSP0_DEFAULT 0x00000000u + #define PWR_PDCTL_MCBSP0_OF(x) _VALUEOF(x) + #define PWR_PDCTL_MCBSP0_CLKON 0x00000000u + #define PWR_PDCTL_MCBSP0_CLKOFF 0x00000001u + + #define _PWR_PDCTL_EMIF_MASK 0x00000002u + #define _PWR_PDCTL_EMIF_SHIFT 0x00000001u + #define PWR_PDCTL_EMIF_DEFAULT 0x00000000u + #define PWR_PDCTL_EMIF_OF(x) _VALUEOF(x) + #define PWR_PDCTL_EMIF_CLKON 0x00000000u + #define PWR_PDCTL_EMIF_CLKOFF 0x00000001u + + #define _PWR_PDCTL_DMA_MASK 0x00000001u + #define _PWR_PDCTL_DMA_SHIFT 0x00000000u + #define PWR_PDCTL_DMA_DEFAULT 0x00000000u + #define PWR_PDCTL_DMA_OF(x) _VALUEOF(x) + #define PWR_PDCTL_DMA_CLKON 0x00000000u + #define PWR_PDCTL_DMA_CLKOFF 0x00000001u + + #define PWR_PDCTL_OF(x) _VALUEOF(x) + + #define PWR_PDCTL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(PWR,PDCTL,MCBSP2) \ + |_PER_FDEFAULT(PWR,PDCTL,MCBSP1) \ + |_PER_FDEFAULT(PWR,PDCTL,MCBSP0) \ + |_PER_FDEFAULT(PWR,PDCTL,EMIF) \ + |_PER_FDEFAULT(PWR,PDCTL,DMA) \ + ) + + #define PWR_PDCTL_RMK(mcbsp2,mcbsp1,mcbsp0,emif,dma) (Uint32)( \ + _PER_FMK(PWR,PDCTL,MCBSP2,mcbsp2) \ + |_PER_FMK(PWR,PDCTL,MCBSP1,mcbsp1) \ + |_PER_FMK(PWR,PDCTL,MCBSP0,mcbsp0) \ + |_PER_FMK(PWR,PDCTL,EMIF,emif) \ + |_PER_FMK(PWR,PDCTL,DMA,dma) \ + ) + + #define _PWR_PDCTL_FGET(FIELD)\ + _PER_FGET(_PWR_PDCTL_ADDR,PWR,PDCTL,##FIELD) + + #define _PWR_PDCTL_FSET(FIELD,field)\ + _PER_FSET(_PWR_PDCTL_ADDR,PWR,PDCTL,##FIELD,field) + + #define _PWR_PDCTL_FSETS(FIELD,SYM)\ + _PER_FSETS(_PWR_PDCTL_ADDR,PWR,PDCTL,##FIELD,##SYM) +#endif + + +/*----------------------------------------------------------------------------*/ + +#endif /* PWR_SUPPORT */ +#endif /* _CSL_PWRHAL_H_ */ +/******************************************************************************\ +* End of csl_pwrhal.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_stdinc.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_stdinc.h new file mode 100644 index 0000000..6c08d8d --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_stdinc.h @@ -0,0 +1,68 @@ +/******************************************************************************\ +* Copyright (C) 1999-2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_stdinc.h +* DATE CREATED.. 03/11/1999 +* LAST MODIFIED. 10/03/2000 +* 01/06/2005 Added _TI_STD_TYPES directive to protect +* multiple definition of datatypes. +\******************************************************************************/ +#ifndef _CSL_STDINC_H_ +#define _CSL_STDINC_H_ + +#include + + +/******************************************************************************\ +* macro declarations +\******************************************************************************/ + +/* a few standard constants */ +#ifndef TRUE + #define TRUE 1 +#endif +#ifndef FALSE + #define FALSE 0 +#endif + +/* Invalid Pointer */ +/* In many instances, it is better to use INV as opposed to NULL */ +/* because 0 may actually be a valid pointer */ +#ifndef INV + #define INV ((void*)(-1)) +#endif + +#ifndef UNREFERENCED_PARAMETER + #define UNREFERENCED_PARAMETER(P) ((P)=(P)) +#endif + +#ifndef REG32 + #define REG32(addr) (*(volatile unsigned int*)(addr)) + #define REG16(addr) (*(volatile unsigned short*)(addr)) + #define REG8(addr) (*(volatile unsigned char*)(addr)) +#endif + +/******************************************************************************\ +* typedef declarations +\******************************************************************************/ + +#include /* use typedefs provided with CCS*/ + +/******************************************************************************\ +* variable declarations +\******************************************************************************/ + + + typedef long Int40; + typedef unsigned long Uint40; +/******************************************************************************\ +* function declarations +\******************************************************************************/ + + +#endif /* _CSL_STDINC_H_ */ +/******************************************************************************\ +* End of csl_stdinc.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_stdinchal.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_stdinchal.h new file mode 100644 index 0000000..c1288b1 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_stdinchal.h @@ -0,0 +1,114 @@ +/******************************************************************************\ +* Copyright (C) 1999-2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_stdinchal.h +* DATE CREATED.. 03/11/1999 +* LAST MODIFIED. 03/23/2001 +\******************************************************************************/ +#ifndef _CSL_STDINCHAL_H_ +#define _CSL_STDINCHAL_H_ + + +/******************************************************************************\ +* HAL macro definitions +\******************************************************************************/ + + #define _VALUEOF(x) ((Uint32)(x)) + + /*******************************************************/ + /* generic macros for field manipulation */ + /*******************************************************/ + + #define _PER_FSHIFT(PER,REG,FIELD) \ + _##PER##_##REG##_##FIELD##_SHIFT + + #define _PER_FMASK(PER,REG,FIELD) \ + _##PER##_##REG##_##FIELD##_MASK + + #define _PER_FSYM(PER,REG,FIELD,SYM)\ + PER##_##REG##_##FIELD##_##SYM + + #define _PER_FDEFAULT(PER,REG,FIELD) \ + ((##PER##_##REG##_##FIELD##_DEFAULT << _##PER##_##REG##_##FIELD##_SHIFT) \ + & _##PER##_##REG##_##FIELD##_MASK) + + #define _PER_FMK(PER,REG,FIELD,x) (\ + (((Uint32)(x))<<_PER_FSHIFT(##PER,##REG,##FIELD))\ + &_PER_FMASK(##PER,##REG,##FIELD)\ + ) + + #define _PER_FMKS(PER,REG,FIELD,SYM) (\ + (_PER_FSYM(##PER,##REG,##FIELD,##SYM)<<_PER_FSHIFT(##PER,##REG,##FIELD))\ + &_PER_FMASK(##PER,##REG,##FIELD)\ + ) + + #define _PER_FEXTRACT(PER,REG,FIELD,reg) (Uint32)(\ + (((Uint32)(reg)&_PER_FMASK(##PER,##REG,##FIELD))\ + >>_PER_FSHIFT(##PER,##REG,##FIELD))\ + ) + + #define _PER_FINSERT(PER,REG,FIELD,reg,field) (Uint32)(\ + (((Uint32)(reg)&~_PER_FMASK(##PER,##REG,##FIELD))|\ + (((Uint32)(field)<<_PER_FSHIFT(##PER,##REG,##FIELD))\ + &_PER_FMASK(##PER,##REG,##FIELD)))\ + ) + + /*******************************************************/ + /* macros for memmory mapped registers */ + /*******************************************************/ + + #define _PER_RAOI(addr,PER,REG,and,or,inv)\ + (*(volatile Uint32*)(addr))=(\ + ((((*(volatile Uint32*)(addr))\ + &((Uint32)(and)))\ + |((Uint32)(or)))\ + ^((Uint32)(inv)))\ + ) + + #define _PER_RGET(addr,PER,REG) \ + (*(volatile Uint32*)(addr)) + + #define _PER_RSET(addr,PER,REG,x) \ + (*(volatile Uint32*)(addr))=((Uint32)(x)) + + #define _PER_FGET(addr,PER,REG,FIELD) \ + _PER_FEXTRACT(##PER,##REG,##FIELD,_PER_RGET(addr,##PER,##REG)) + + #define _PER_FSET(addr,PER,REG,FIELD,field)\ + _PER_RSET(addr,##PER,##REG,\ + _PER_FINSERT(##PER,##REG,##FIELD,_PER_RGET(addr,##PER,##REG),field)) + + #define _PER_FSETS(addr,PER,REG,FIELD,SYM)\ + _PER_RSET(addr,##PER,##REG,_PER_FINSERT(##PER,##REG,##FIELD,_PER_RGET(addr,##PER,##REG),\ + _PER_FSYM(##PER,##REG,##FIELD,##SYM))) + + /*******************************************************/ + /* macros for CPU control registers */ + /*******************************************************/ + + #define _PER_CRGET(PER,REG) \ + REG + + #define _PER_CRSET(PER,REG,reg) \ + REG=((Uint32)(reg)) + + #define _PER_CFGET(PER,REG,FIELD) \ + _PER_FEXTRACT(##PER,##REG,##FIELD,_PER_CRGET(##PER,##REG)) + + #define _PER_CFSET(PER,REG,FIELD,field)\ + _PER_CRSET(##PER,##REG,\ + _PER_FINSERT(##PER,##REG,##FIELD,_PER_CRGET(##PER,##REG),field)) + + #define _PER_CFSETS(PER,REG,FIELD,SYM)\ + _PER_CRSET(##PER,##REG,\ + _PER_FINSERT(##PER,##REG,FIELD,_PER_CRGET(##PER,##REG),\ + _PER_FSYM(##PER,##REG,##FIELD,##SYM))) + +/*----------------------------------------------------------------------------*/ + +#endif /* _CSL_STDINCHAL_H_ */ +/******************************************************************************\ +* End of csl_stdinchal.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_tcp.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_tcp.h new file mode 100644 index 0000000..da07154 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_tcp.h @@ -0,0 +1,630 @@ +/******************************************************************************\ +* Copyright (C) 2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_tcp.h +* DATE CREATED.. 02/22/2001 +* LAST MODIFIED. 09/17/2001 +* +\******************************************************************************/ +#ifndef _CSL_TCP_H_ +#define _CSL_TCP_H_ + +#include +#include +#include +#include "csl_tcphal.h" + +#if (TCP_SUPPORT) +/****************************************\ +* TCP scope and inline control macros +\****************************************/ +#ifdef __cplusplus +#define CSLAPI extern "C" far +#else +#define CSLAPI extern far +#endif + +#undef USEDEFS +#undef IDECL +#undef IDEF + +#ifdef _TCP_MOD_ + #define IDECL extern far + #define USEDEFS + #define IDEF +#else + #ifdef _INLINE + #define IDECL static inline + #define USEDEFS + #define IDEF static inline + #else + #define IDECL extern far + #endif +#endif + +/****************************************\ +* TCP global macro declarations +\****************************************/ + +/****************************************\ +* TCP global typedef declarations +\****************************************/ +typedef Uint8 TCP_Standard; +typedef Uint8 TCP_Mode; +typedef Uint8 TCP_Map; +typedef Uint8 TCP_Rate; +typedef Uint8 TCP_UserData; +typedef Uint8 TCP_ExtrinsicData; + +typedef struct { + Uint32 ic0; + Uint32 ic1; + Uint32 ic2; + Uint32 ic3; + Uint32 ic4; + Uint32 ic5; + Uint32 ic6; + Uint32 ic7; + Uint32 ic8; + Uint32 ic9; + Uint32 ic10; + Uint32 ic11; +} TCP_ConfigIc; + +typedef struct { + TCP_Standard standard; + TCP_Mode mode; + TCP_Map map; + TCP_Rate rate; + Uint32 intFlag; + Uint32 outParmFlag; + Uint32 frameLen; + Uint32 subFrameLen; + Uint32 relLen; + Uint32 relLenLast; + Uint32 prologSize; + Uint32 numSubBlock; + Uint32 numSubBlockLast; + Uint32 maxIter; + Uint32 snr; + Uint32 numInter; + Uint32 numSysPar; + Uint32 numApriori; + Uint32 numExt; + Uint32 numHd; +} TCP_Params; + +typedef struct { + TCP_Standard standard; + TCP_Rate rate; + Uint16 frameLen; + Uint8 prologSize; + Uint8 maxIter; + Uint8 snr; + Uint8 intFlag; + Uint8 outParmFlag; +} TCP_BaseParams; + +/************ New structure for Init ***************/ +typedef struct { + TCP_UserData *restrict xabData; + TCP_Standard standard; + TCP_Rate rate; + Uint16 frameLen; + Uint8 prologSize; + Uint8 maxIter; + Uint8 snr; + Uint8 intFlag; + Uint8 outParmFlag; +} TCP_Init; + +/****************************************\ +* TCP global ants declarations +\****************************************/ +#define TCP_RATE_1_2 2 +#define TCP_RATE_1_3 3 +#define TCP_RATE_1_4 4 +#define TCP_MODE_SA 0 +#define TCP_MODE_SP 1 +#define TCP_MAP_MAP1A 0 +#define TCP_MAP_MAP1B 1 +#define TCP_MAP_MAP2 3 +#define TCP_STANDARD_3GPP 0 +#define TCP_STANDARD_IS2000 1 +#define TCP_RLEN_MAX 128 +#define TCP_FLEN_MAX 5114 +#define TCP_NUM_IC 12 +#define TCP_NUM_OP 2 + +/****************************************\ +* TCP global function declarations +\****************************************/ + +/* Set the ic6-ic9 registers (tails) based on the user data */ +/* TCP_tailConfig calls TCP_tailConfig3GPP() or TCP_tailConfigIs2000 */ +/* based on the "standard" parameter value */ +CSLAPI void TCP_tailConfig(TCP_Standard standard, + TCP_Mode mode, + TCP_Map map, + TCP_Rate rate, + TCP_UserData *restrict xabData, + TCP_ConfigIc *restrict configIc); +CSLAPI void TCP_tailConfig3GPP(TCP_Mode mode, + TCP_Map map, + TCP_UserData *restrict xabData, + TCP_ConfigIc *restrict configIc); +CSLAPI void TCP_tailConfigIs2000(TCP_Mode mode, + TCP_Map map, + TCP_Rate rate, + TCP_UserData *restrict xabData, + TCP_ConfigIc *restrict configIc); + +/* Set the Parameters passed via Param structure to ic0-ic5 registers */ +/* configIc is the returned config structure of the icx registers */ +CSLAPI void TCP_setParams(TCP_Params *restrict configParms, + TCP_ConfigIc *restrict configIc); + +/* Set all icx registers : */ +/* configPrams input parameters dedicated to ic0-ic5 registers */ +/* xabData input parameters dedicated to set ic6-ic11 registers (tails */ +/* configIc is the returned config structure of the icx registers */ +CSLAPI void TCP_genIc(TCP_Params *restrict configParms, + TCP_UserData *restrict xabData, + TCP_ConfigIc *restrict configIc); + +/* Divide the data frames into subframes and subblocks. */ +/* The values calculated in these routines are entered into the configParms */ +/* struct and are used in programming the TCP IC values and the EDMA */ +/* parameters. Either TCP_calcSubBlocks3GPP or TCP_calcSubBlocksIs2000 is */ +/* used depending on the standard. */ +CSLAPI void TCP_calcSubBlocksSA(TCP_Params *configParms); + +CSLAPI Uint32 TCP_calcSubBlocksSP(TCP_Params *configParms); + +/* Fill out the necessary TCP parameters. */ +CSLAPI Uint32 TCP_genParams(TCP_BaseParams *configBase, + TCP_Params *configParms); + + +/*** Init parameters and set registers **********/ +void TCP_init(TCP_Init *Init); +void TCP_tailInit3GPP(TCP_Mode mode, TCP_Map map,TCP_UserData *restrict xabData); +void TCP_tailInitIs2000(TCP_Mode mode,TCP_Map map,TCP_Rate rate,TCP_UserData *restrict xabData); + +/* Calculate the count values (number of 32-bit words) required for the */ +/* programming of the EDMA for all data buffers. The counts calculated */ +/* using either TCP_calcCounts3GPP or TCP_calcCountsIs2000 depending on the */ +/* standard. */ +CSLAPI void TCP_calcCountsSA(TCP_Params *configParms); + +CSLAPI void TCP_calcCountsSP(TCP_Params *configParms); + +/* Interleave the extrinsics data to give the apriori data required for the */ +/* subsequent MAP decoding. TCP_interleaveExt is performed by the CPU */ +/* following a MAP1 decoding by the TCP. This function is used in shared */ +/* processing mode only. */ +CSLAPI void TCP_interleaveExt(TCP_ExtrinsicData *restrict aprioriMap2, + const TCP_ExtrinsicData *restrict extrinsicsMap1, + const Uint16 *restrict interleaverTable, + Uint32 numExt); + +/* De-interleave the extrinsics data to give the apriori data required for */ +/* the subsequent MAP decoding. TCP_deinterleaveExt is performed by the CPU */ +/* following a MAP2 decoding by the TCP. This function is used in shared */ +/* processing mode only. */ +CSLAPI void TCP_deinterleaveExt(TCP_ExtrinsicData *restrict aprioriMap1, + const TCP_ExtrinsicData *restrict extrinsicsMap2, + const Uint16 *restrict interleaverTable, + Uint32 numExt); + +/* Calculate hard decisions following all MAP decodings in shared processing*/ +/* mode. */ +CSLAPI void TCP_calculateHd(const TCP_ExtrinsicData *restrict extrinsicsMap1, + const TCP_ExtrinsicData *restrict apriori, + const TCP_UserData *restrict channel_data, + Uint32 *restrict hardDecisions, + Uint16 numExt, + Uint8 rate); + +/* Demultiplex the input data into two "working data" buffers. The two new */ +/* data buffers are used separately for MAP 1 and MAP 2 decodings in shared */ +/* processing mode. */ +CSLAPI void TCP_demuxInput(Uint32 rate, + Uint32 frameLen, + const TCP_UserData *restrict input, + const Uint16 *restrict interleaver, + TCP_ExtrinsicData *restrict nonInterleaved, + TCP_ExtrinsicData *restrict interleaved); + +/****************************************\ +* TCP inline function declarations +\****************************************/ + +/* Master transfer functions */ +IDECL void TCP_start(); +IDECL void TCP_pause(); +IDECL void TCP_unpause(); + +IDECL Uint32 TCP_getNumIt(); +IDECL Uint32 TCP_getSysParEndian(); +IDECL Uint32 TCP_getInterEndian(); +IDECL Uint32 TCP_getAprioriEndian(); +IDECL Uint32 TCP_getExtEndian(); + +IDECL void TCP_setNativeEndian(); +IDECL void TCP_setPacked32Endian(); +IDECL void TCP_setSysParEndian(Uint32 sysParEnd); +IDECL void TCP_setInterEndian(Uint32 interEnd); +IDECL void TCP_setAprioriEndian(Uint32 aprioriEnd); +IDECL void TCP_setExtEndian(Uint32 extEnd); + +IDECL Uint32 TCP_statPause(); +IDECL Uint32 TCP_statRun(); +IDECL Uint32 TCP_statError(); +IDECL Uint32 TCP_statWaitIc(); +IDECL Uint32 TCP_statWaitInter(); +IDECL Uint32 TCP_statWaitSysPar(); +IDECL Uint32 TCP_statWaitApriori(); +IDECL Uint32 TCP_statWaitExt(); +IDECL Uint32 TCP_statWaitHardDec(); +IDECL Uint32 TCP_statWaitOutParm(); + +IDECL Uint32 TCP_errTest(); +IDECL Uint32 TCP_getFrameLenErr(); +IDECL Uint32 TCP_getProlLenErr(); +IDECL Uint32 TCP_getRateErr(); +IDECL Uint32 TCP_getSubFrameErr(); +IDECL Uint32 TCP_getModeErr(); +IDECL Uint32 TCP_getRelLenErr(); +IDECL Uint32 TCP_getLastRelLenErr(); +IDECL Uint32 TCP_getInterleaveErr(); +IDECL Uint32 TCP_getOutParmErr(); +IDECL Uint32 TCP_getAccessErr(); + + +/* Set all the TCP registers : ic0-ic11 using a configuration structure */ +IDECL void TCP_icConfig(TCP_ConfigIc *config); + +/* Set all the TCP registers : ic0-ic11 with register values */ +IDECL void TCP_icConfigArgs(Uint32 ic0, Uint32 ic1, Uint32 ic2, Uint32 ic3, + Uint32 ic4, Uint32 ic5, Uint32 ic6, Uint32 ic7, + Uint32 ic8, Uint32 ic9, Uint32 ic10, Uint32 ic11); +/* Get TCP registers : ic0-ic11 returned into a configuration structure */ +IDECL void TCP_getIcConfig(TCP_ConfigIc *config); + +/* Build the tail value */ +IDECL Uint32 TCP_makeTailArgs(Uint8 byte31_24, Uint8 byte23_16, + Uint8 byte15_8, Uint8 byte7_0); + +/* Ceiling functions */ +IDECL Uint32 TCP_ceil(Uint32 a, Uint32 b); + +IDECL Uint32 TCP_normalCeil(Uint32 a, Uint32 b); + +/****************************************\ +* TCP inline function definitions +\****************************************/ +#ifdef USEDEFS +/*----------------------------------------------------------------------------*/ +IDEF void TCP_start(){ + TCP_FSET(EXE,START,1); +} +/*----------------------------------------------------------------------------*/ +IDEF void TCP_pause(){ + TCP_FSET(EXE,PAUSE,1); +} +/*----------------------------------------------------------------------------*/ +IDEF void TCP_unpause(){ + TCP_FSET(EXE,UNPAUSE,1); +} +/*----------------------------------------------------------------------------*/ +IDEF void TCP_reset(){ + TCP_RSET(IC0,TCP_IC0_DEFAULT); + TCP_RSET(IC1,TCP_IC1_DEFAULT); + TCP_RSET(IC2,TCP_IC2_DEFAULT); + TCP_RSET(IC3,TCP_IC3_DEFAULT); + TCP_RSET(IC4,TCP_IC4_DEFAULT); + TCP_RSET(IC5,TCP_IC5_DEFAULT); + TCP_RSET(IC6,TCP_IC6_DEFAULT); + TCP_RSET(IC7,TCP_IC7_DEFAULT); + TCP_RSET(IC8,TCP_IC8_DEFAULT); + TCP_RSET(IC9,TCP_IC9_DEFAULT); + TCP_RSET(IC10,TCP_IC10_DEFAULT); + TCP_RSET(IC11,TCP_IC11_DEFAULT); + TCP_RSET(OUT,TCP_OUT_DEFAULT); + TCP_RSET(EXE,TCP_EXE_DEFAULT); + TCP_RSET(END,TCP_END_DEFAULT); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 TCP_getNumIt(){ + return TCP_FGET(OUT,NIT); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 TCP_getSysParEndian(){ + return TCP_FGET(END,SYSPAR); +} +/*----------------------------------------------------------------------------*/ +IDEF void TCP_setSysParEndian(Uint32 sysParEnd){ + TCP_FSET(END,SYSPAR,sysParEnd); +} + +/*----------------------------------------------------------------------------*/ +IDEF Uint32 TCP_getInterEndian(){ + return TCP_FGET(END,INTER); +} +/*----------------------------------------------------------------------------*/ +IDEF void TCP_setInterEndian(Uint32 interEnd){ + TCP_FSET(END,INTER,interEnd); +} + +/*----------------------------------------------------------------------------*/ +IDEF Uint32 TCP_getAprioriEndian(){ + return TCP_FGET(END,AP); +} +/*----------------------------------------------------------------------------*/ +IDEF void TCP_setAprioriEndian(Uint32 aprioriEnd ){ + TCP_FSET(END,AP,aprioriEnd); +} + +/*----------------------------------------------------------------------------*/ +IDEF Uint32 TCP_getExtEndian(){ + return TCP_FGET(END,EXT); +} +/*----------------------------------------------------------------------------*/ +IDEF void TCP_setExtEndian(Uint32 extEnd){ + TCP_FSET(END,EXT,extEnd); +} +/*----------------------------------------------------------------------------*/ +IDEF void TCP_setNativeEndian(){ + TCP_RSET(END,0xF); +} +/*----------------------------------------------------------------------------*/ +IDEF void TCP_setPacked32Endian(){ + TCP_RSET(END,0x0); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 TCP_statPause(){ + return TCP_FGET(STAT,PAUS); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 TCP_statRun(){ + return TCP_FGET(STAT,RUN); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 TCP_statError(){ + return TCP_FGET(STAT,ERR); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 TCP_statWaitIc(){ + return TCP_FGET(STAT,WIC); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 TCP_statWaitInter(){ + return TCP_FGET(STAT,WINT); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 TCP_statWaitSysPar(){ + return TCP_FGET(STAT,WSP); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 TCP_statWaitApriori(){ + return TCP_FGET(STAT,WAP); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 TCP_statWaitExt(){ + return TCP_FGET(STAT,REXT); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 TCP_statWaitHardDec(){ + return TCP_FGET(STAT,RHD); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 TCP_statWaitOutParm(){ + return TCP_FGET(STAT,ROP); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 TCP_errTest(){ + return TCP_FGET(ERR,ERR); +} + +/*----------------------------------------------------------------------------*/ +IDEF Uint32 TCP_getFrameLenErr(){ + return TCP_FGET(ERR,F); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 TCP_getProlLenErr(){ + return TCP_FGET(ERR,P); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 TCP_getRateErr(){ + return TCP_FGET(ERR,RATE); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 TCP_getSubFrameErr(){ + return TCP_FGET(ERR,SF); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 TCP_getModeErr(){ + return TCP_FGET(ERR,MODE); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 TCP_getRelLenErr(){ + return TCP_FGET(ERR,R); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 TCP_getLastRelLenErr(){ + return TCP_FGET(ERR,LR); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 TCP_getInterleaveErr(){ + return TCP_FGET(ERR,INT); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 TCP_getOutParmErr(){ + return TCP_FGET(ERR,OP); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 TCP_getAccessErr(){ + return TCP_FGET(ERR,ACC); +} +/*----------------------------------------------------------------------------*/ +IDEF void TCP_icConfig(TCP_ConfigIc *config) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *) _TCP_BASE_IC; + register int x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11; + + gie = IRQ_globalDisable(); + + x0 = config->ic0; + x1 = config->ic1; + x2 = config->ic2; + x3 = config->ic3; + x4 = config->ic4; + x5 = config->ic5; + x6 = config->ic6; + x7 = config->ic7; + x8 = config->ic8; + x9 = config->ic9; + x10 = config->ic10; + x11 = config->ic11; + + base[_TCP_IC0_OFFSET] = x0; + base[_TCP_IC1_OFFSET] = x1; + base[_TCP_IC2_OFFSET] = x2; + base[_TCP_IC3_OFFSET] = x3; + base[_TCP_IC4_OFFSET] = x4; + base[_TCP_IC5_OFFSET] = x5; + base[_TCP_IC6_OFFSET] = x6; + base[_TCP_IC7_OFFSET] = x7; + base[_TCP_IC8_OFFSET] = x8; + base[_TCP_IC9_OFFSET] = x9; + base[_TCP_IC10_OFFSET] = x10; + base[_TCP_IC11_OFFSET] = x11; + + IRQ_globalRestore(gie); +} +/*----------------------------------------------------------------------------*/ +IDEF void TCP_icConfigArgs(Uint32 ic0, Uint32 ic1, Uint32 ic2, Uint32 ic3, Uint32 ic4, + Uint32 ic5, Uint32 ic6, Uint32 ic7, Uint32 ic8, Uint32 ic9, + Uint32 ic10, Uint32 ic11) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *) _TCP_BASE_IC; + + gie = IRQ_globalDisable(); + + base[_TCP_IC0_OFFSET] = ic0; + base[_TCP_IC1_OFFSET] = ic1; + base[_TCP_IC2_OFFSET] = ic2; + base[_TCP_IC3_OFFSET] = ic3; + base[_TCP_IC4_OFFSET] = ic4; + base[_TCP_IC5_OFFSET] = ic5; + base[_TCP_IC6_OFFSET] = ic6; + base[_TCP_IC7_OFFSET] = ic7; + base[_TCP_IC8_OFFSET] = ic8; + base[_TCP_IC9_OFFSET] = ic9; + base[_TCP_IC10_OFFSET] = ic10; + base[_TCP_IC11_OFFSET] = ic11; + + IRQ_globalRestore(gie); +} +/*----------------------------------------------------------------------------*/ +IDEF void TCP_getIcConfig(TCP_ConfigIc *config) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *) _TCP_BASE_IC; + register int x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11; + + gie = IRQ_globalDisable(); + + x0 = base[_TCP_IC0_OFFSET]; + x1 = base[_TCP_IC1_OFFSET]; + x2 = base[_TCP_IC2_OFFSET]; + x3 = base[_TCP_IC3_OFFSET]; + x4 = base[_TCP_IC4_OFFSET]; + x5 = base[_TCP_IC5_OFFSET]; + x6 = base[_TCP_IC6_OFFSET]; + x7 = base[_TCP_IC7_OFFSET]; + x8 = base[_TCP_IC8_OFFSET]; + x9 = base[_TCP_IC9_OFFSET]; + x10 = base[_TCP_IC10_OFFSET]; + x11 = base[_TCP_IC11_OFFSET]; + + config->ic0 = x0; + config->ic1 = x1; + config->ic2 = x2; + config->ic3 = x3; + config->ic4 = x4; + config->ic5 = x5; + config->ic6 = x6; + config->ic7 = x7; + config->ic8 = x8; + config->ic9 = x9; + config->ic10 = x10; + config->ic11 = x11; + + IRQ_globalRestore(gie); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 TCP_makeTailArgs(Uint8 byte31_24, Uint8 byte23_16, + Uint8 byte15_8, Uint8 byte7_0) { + + Uint32 gie; + Uint32 x; + + gie = IRQ_globalDisable(); + + x = (byte31_24 << 24) | (byte23_16 << 16) | (byte15_8 << 8) | byte7_0; + + IRQ_globalRestore(gie); + + return(x); +} + +/*----------------------------------------------------------------------------*/ + +IDEF Uint32 TCP_ceil(Uint32 val, Uint32 pwr2) { + Uint32 gie; + Uint32 x; + + gie = IRQ_globalDisable(); + + /* x^pwr2 = ceil(val, 2^pwr2) */ + /* val is increased (if necessary) to be a multiple of 2^pwr2 */ + x = (((val) - (((val)>>(pwr2)) << (pwr2))) == 0) ? \ + ((val)>>(pwr2)):(((val)>>(pwr2))+1); + + IRQ_globalRestore(gie); + + return(x); +} + +/*----------------------------------------------------------------------------*/ + +IDEF Uint32 TCP_normalCeil(Uint32 val1, Uint32 val2) { + Uint32 gie; + Uint32 x; + + gie = IRQ_globalDisable(); + + /* x = ceil(val1, val2) */ + /* val is increased (if necessary) to be a multiple of val2 */ + x = ( ((val1)%(val2))!=0 )?( ((val1)/(val2)) + 1 ):((val1)/(val2)); + + IRQ_globalRestore(gie); + + return(x); +} + +/*----------------------------------------------------------------------------*/ + +#endif /* USEDEFS */ + +#endif /* (TCP_SUPPORT) */ +#endif /* _CSL_TCP_H_ */ +/******************************************************************************\ +* End of csl_tcp.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_tcphal.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_tcphal.h new file mode 100644 index 0000000..1ed4a4f --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_tcphal.h @@ -0,0 +1,1167 @@ +/******************************************************************************\ +* Copyright (C) 1999-2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_tcphal.h +* DATE CREATED.. 02/21/2001 +* LAST MODIFIED. 08/02/2004 - Adding support for C6418 +* 04/20/2001 +*------------------------------------------------------------------------------ +* REGISTERS +* +* IC0 - TCP input configuration register 0 +* IC1 - TCP input configuration register 1 +* IC2 - TCP input configuration register 2 +* IC3 - TCP input configuration register 3 +* IC4 - TCP input configuration register 4 +* IC5 - TCP input configuration register 5 +* IC6 - TCP input configuration register 6 +* IC7 - TCP input configuration register 7 +* IC8 - TCP input configuration register 8 +* IC9 - TCP input configuration register 9 +* IC10 - TCP input configuration register 10 +* IC11 - TCP input configuration register 11 +* OUT - TCP output parameters register +* EXE - TCP execution register +* END - TCP endian mode register +* ERR - TCP error register +* STAT - TCP status register +* +*------------------------------------------------------------------------------ +* MEMORY REGIONS +* +* ICMEM - TCP interrupt configuration register space +* OPMEM - TCP output parameter register space +* SPMEM - TCP systematics and parities memory +* EXMEM - TCP extrinsics memory +* APMEM - TCP apriori memory +* ILMEM - TCP interleaver memory +* HDMEM - TCP hard decisions memory +* +\******************************************************************************/ +#ifndef _CSL_TCPHAL_H_ +#define _CSL_TCPHAL_H_ + +#include +#include + +#if (TCP_SUPPORT) + +/******************************************************************************\ +* Memory section +\******************************************************************************/ + + #define _TCP_BASE_IC 0x01BA0000u + #define TCP_ICMEM_ADDR 0x58000000u + #define TCP_OPMEM_ADDR 0x58000030u + #define TCP_SPMEM_ADDR 0x58020000u + #define TCP_EXMEM_ADDR 0x58040000u + #define TCP_APMEM_ADDR 0x58060000u + #define TCP_ILMEM_ADDR 0x58080000u + #define TCP_HDMEM_ADDR 0x580A0000u + + +/******************************************************************************\ +* module level register/field access macros +\******************************************************************************/ + + /* ----------------- */ + /* FIELD MAKE MACROS */ + /* ----------------- */ + + #define TCP_FMK(REG,FIELD,x)\ + _PER_FMK(TCP,##REG,##FIELD,x) + + #define TCP_FMKS(REG,FIELD,SYM)\ + _PER_FMKS(TCP,##REG,##FIELD,##SYM) + + + /* -------------------------------- */ + /* RAW REGISTER/FIELD ACCESS MACROS */ + /* -------------------------------- */ + + #define TCP_ADDR(REG)\ + _TCP_##REG##_ADDR + + #define TCP_RGET(REG)\ + _PER_RGET(_TCP_##REG##_ADDR,TCP,##REG) + + #define TCP_RSET(REG,x)\ + _PER_RSET(_TCP_##REG##_ADDR,TCP,##REG,x) + + #define TCP_FGET(REG,FIELD)\ + _TCP_##REG##_FGET(##FIELD) + + #define TCP_FSET(REG,FIELD,x)\ + _TCP_##REG##_FSET(##FIELD,##x) + + #define TCP_FSETS(REG,FIELD,SYM)\ + _TCP_##REG##_FSETS(##FIELD,##SYM) + + + /* ------------------------------------------ */ + /* ADDRESS BASED REGISTER/FIELD ACCESS MACROS */ + /* ------------------------------------------ */ + + #define TCP_RGETA(addr,REG)\ + _PER_RGET(addr,TCP,##REG) + + #define TCP_RSETA(addr,REG,x)\ + _PER_RSET(addr,TCP,##REG,x) + + #define TCP_FGETA(addr,REG,FIELD)\ + _PER_FGET(addr,TCP,##REG,##FIELD) + + #define TCP_FSETA(addr,REG,FIELD,x)\ + _PER_FSET(addr,TCP,##REG,##FIELD,x) + + #define TCP_FSETSA(addr,REG,FIELD,SYM)\ + _PER_FSETS(addr,TCP,##REG,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | I C 0 | +* |___________________| +* +* TCP input configuration register 0 +* +* FIELDS (msb -> lsb) +* (rw) FL +* (rw) OUTF +* (rw) INTER +* (rw) RATE +* (rw) OPMOD +* +* +\******************************************************************************/ + #define _TCP_IC0_OFFSET 0 + + #define _TCP_IC0_ADDR 0x01BA0000u + // #define _TCP_IC0_ADDR 0x58000000u + + #define _TCP_IC0_FL_MASK 0xFFFF0000u + #define _TCP_IC0_FL_SHIFT 0x00000010u + #define TCP_IC0_FL_DEFAULT 0x00000000u + #define TCP_IC0_FL_OF(x) _VALUEOF(x) + + #define _TCP_IC0_OUTF_MASK 0x00002000u // error doc + #define _TCP_IC0_OUTF_SHIFT 0x0000000Du + #define TCP_IC0_OUTF_DEFAULT 0x00000000u + #define TCP_IC0_OUTF_OF(x) _VALUEOF(x) + #define TCP_IC0_OUTF_NO 0x00000000u + #define TCP_IC0_OUTF_YES 0x00000001u + + #define _TCP_IC0_INTER_MASK 0x00001000u + #define _TCP_IC0_INTER_SHIFT 0x0000000Cu + #define TCP_IC0_INTER_DEFAULT 0x00000000u + #define TCP_IC0_INTER_OF(x) _VALUEOF(x) + #define TCP_IC0_INTER_NO 0x00000000u + #define TCP_IC0_INTER_YES 0x00000001u + + #define _TCP_IC0_RATE_MASK 0x00000300u + #define _TCP_IC0_RATE_SHIFT 0x00000008u + #define TCP_IC0_RATE_DEFAULT 0x00000000u + #define TCP_IC0_RATE_OF(x) _VALUEOF(x) + #define TCP_IC0_RATE_1_2 0x00000001u + #define TCP_IC0_RATE_1_3 0x00000002u + #define TCP_IC0_RATE_1_4 0x00000003u + + #define _TCP_IC0_OPMOD_MASK 0x0000000Eu + #define _TCP_IC0_OPMOD_SHIFT 0x00000001u + #define TCP_IC0_OPMOD_DEFAULT 0x00000000u + #define TCP_IC0_OPMOD_OF(x) _VALUEOF(x) + #define TCP_IC0_OPMOD_SA 0x00000000u + #define TCP_IC0_OPMOD_MAP1A 0x00000004u + #define TCP_IC0_OPMOD_MAP1B 0x00000005u + #define TCP_IC0_OPMOD_MAP2 0x00000007u + + + #define TCP_IC0_OF(x) _VALUEOF(x) + + #define TCP_IC0_DEFAULT (Uint32)(\ + _PER_FDEFAULT(TCP,IC0,FL)\ + |_PER_FDEFAULT(TCP,IC0,OUTF)\ + |_PER_FDEFAULT(TCP,IC0,INTER)\ + |_PER_FDEFAULT(TCP,IC0,RATE)\ + |_PER_FDEFAULT(TCP,IC0,OPMOD)\ + ) + + #define TCP_IC0_RMK(fl,outf,inter,rate,opmod) (Uint32)(\ + _PER_FMK(TCP,IC0,FL,fl)\ + |_PER_FMK(TCP,IC0,OUTF,outf)\ + |_PER_FMK(TCP,IC0,INTER,inter)\ + |_PER_FMK(TCP,IC0,RATE,rate)\ + |_PER_FMK(TCP,IC0,OPMOD,opmod)\ + ) + + #define _TCP_IC0_FGET(FIELD)\ + _PER_FGET(_TCP_IC0_ADDR,TCP,IC0,##FIELD) + + #define _TCP_IC0_FSET(FIELD,field)\ + _PER_FSET(_TCP_IC0_ADDR,TCP,IC0,##FIELD,field) + + #define _TCP_IC0_FSETS(FIELD,SYM)\ + _PER_FSETS(_TCP_IC0_ADDR,TCP,IC0,FIELD,##SYM) + +/******************************************************************************\ +* _____________________ +* | | +* | I C 1 | +* |___________________| +* +* TCP input configuration register 1 +* +* FIELDS (msb -> lsb) +* (rw) LASTR +* (rw) R +* (rw) SFL +* +\******************************************************************************/ + #define _TCP_IC1_OFFSET 1 + + #define _TCP_IC1_ADDR 0x01BA0004u +// #define _TCP_IC1_ADDR 0x580000004u + + #define _TCP_IC1_LASTR_MASK 0x7F000000u + #define _TCP_IC1_LASTR_SHIFT 0x00000018u + #define TCP_IC1_LASTR_DEFAULT 0x00000000u + #define TCP_IC1_LASTR_OF(x) _VALUEOF(x) + + #define _TCP_IC1_R_MASK 0x007F0000u + #define _TCP_IC1_R_SHIFT 0x00000010u + #define TCP_IC1_R_DEFAULT 0x00000000u + #define TCP_IC1_R_OF(x) _VALUEOF(x) + + #define _TCP_IC1_SFL_MASK 0x0000FFFFu + #define _TCP_IC1_SFL_SHIFT 0x00000000u + #define TCP_IC1_SFL_DEFAULT 0x00000000u + #define TCP_IC1_SFL_OF(x) _VALUEOF(x) + + #define TCP_IC1_OF(x) _VALUEOF(x) + + #define TCP_IC1_DEFAULT (Uint32)(\ + _PER_FDEFAULT(TCP,IC1,LASTR)\ + |_PER_FDEFAULT(TCP,IC1,R)\ + |_PER_FDEFAULT(TCP,IC1,SFL)\ + ) + + #define TCP_IC1_RMK(lastr,r,sfl) (Uint32)(\ + _PER_FMK(TCP,IC1,LASTR,lastr)\ + |_PER_FMK(TCP,IC1,R,r)\ + |_PER_FMK(TCP,IC1,SFL,sfl)\ + ) + + #define _TCP_IC1_FGET(FIELD)\ + _PER_FGET(_TCP_IC1_ADDR,TCP,IC1,##FIELD) + + #define _TCP_IC1_FSET(FIELD,field)\ + _PER_FSET(_TCP_IC1_ADDR,TCP,IC1,##FIELD,field) + + #define _TCP_IC1_FSETS(FIELD,SYM)\ + _PER_FSETS(_TCP_IC1_ADDR,TCP,IC1,FIELD,##SYM) + +/******************************************************************************\ +* _____________________ +* | | +* | I C 2 | +* |___________________| +* +* TCP input configuration register 2 +* +* FIELDS (msb -> lsb) +* (rw) SNR +* (rw) MAXIT +* (rw) LASTNSB +* (rw) NSB +* (rw) PS +* +\******************************************************************************/ + #define _TCP_IC2_OFFSET 2 + + #define _TCP_IC2_ADDR 0x01BA0008u + // #define _TCP_IC2_ADDR 0x58000008u + + #define _TCP_IC2_SNR_MASK 0xFF000000u + #define _TCP_IC2_SNR_SHIFT 0x00000018u + #define TCP_IC2_SNR_DEFAULT 0x00000000u + #define TCP_IC2_SNR_OF(x) _VALUEOF(x) + #define TCP_IC2_SNR_NONE 0x00000000u + + #define _TCP_IC2_MAXIT_MASK 0x001F0000u + #define _TCP_IC2_MAXIT_SHIFT 0x00000010u + #define TCP_IC2_MAXIT_DEFAULT 0x00000000u + #define TCP_IC2_MAXIT_OF(x) _VALUEOF(x) + + #define _TCP_IC2_LASTNSB_MASK 0x0000F000u + #define _TCP_IC2_LASTNSB_SHIFT 0x0000000Cu + #define TCP_IC2_LASTNSB_DEFAULT 0x00000000u + #define TCP_IC2_LASTNSB_OF(x) _VALUEOF(x) + + #define _TCP_IC2_NSB_MASK 0x00000F00u + #define _TCP_IC2_NSB_SHIFT 0x00000008u + #define TCP_IC2_NSB_DEFAULT 0x00000000u + #define TCP_IC2_NSB_OF(x) _VALUEOF(x) + + #define _TCP_IC2_P_MASK 0x0000003Fu + #define _TCP_IC2_P_SHIFT 0x00000000u + #define TCP_IC2_P_DEFAULT 0x00000000u + #define TCP_IC2_P_OF(x) _VALUEOF(x) + + #define TCP_IC2_OF(x) _VALUEOF(x) + + #define TCP_IC2_DEFAULT (Uint32)(\ + _PER_FDEFAULT(TCP,IC2,SNR)\ + |_PER_FDEFAULT(TCP,IC2,MAXIT)\ + |_PER_FDEFAULT(TCP,IC2,LASTNSB)\ + |_PER_FDEFAULT(TCP,IC2,NSB)\ + |_PER_FDEFAULT(TCP,IC2,P)\ + ) + + #define TCP_IC2_RMK(snr,maxit,lastnsb,nsb,p) (Uint32)(\ + _PER_FMK(TCP,IC2,SNR,snr)\ + |_PER_FMK(TCP,IC2,MAXIT,maxit)\ + |_PER_FMK(TCP,IC2,LASTNSB,lastnsb)\ + |_PER_FMK(TCP,IC2,NSB,nsb)\ + |_PER_FMK(TCP,IC2,P,p)\ + ) + + #define _TCP_IC2_FGET(FIELD)\ + _PER_FGET(_TCP_IC2_ADDR,TCP,IC2,##FIELD) + + #define _TCP_IC2_FSET(FIELD,field)\ + _PER_FSET(_TCP_IC2_ADDR,TCP,IC2,##FIELD,field) + + #define _TCP_IC2_FSETS(FIELD,SYM)\ + _PER_FSETS(_TCP_IC2_ADDR,TCP,IC2,FIELD,##SYM) + +/******************************************************************************\ +* _____________________ +* | | +* | I C 3 | +* |___________________| +* +* TCP input configuration register 3 +* +* FIELDS (msb -> lsb) +* (rw) NWDSYPAR +* (rw) NWDINTER +* +\******************************************************************************/ + #define _TCP_IC3_OFFSET 3 + + #define _TCP_IC3_ADDR 0x01BA000Cu + + // #define _TCP_IC3_ADDR 0x5800000Cu + + #define _TCP_IC3_NWDSYPAR_MASK 0xFFFF0000u + #define _TCP_IC3_NWDSYPAR_SHIFT 0x00000010u + #define TCP_IC3_NWDSYPAR_DEFAULT 0x00000000u + #define TCP_IC3_NWDSYPAR_OF(x) _VALUEOF(x) + + #define _TCP_IC3_NWDINTER_MASK 0x0000FFFFu + #define _TCP_IC3_NWDINTER_SHIFT 0x00000000u + #define TCP_IC3_NWDINTER_DEFAULT 0x00000000u + #define TCP_IC3_NWDINTER_OF(x) _VALUEOF(x) + + #define TCP_IC3_OF(x) _VALUEOF(x) + + #define TCP_IC3_DEFAULT (Uint32)(\ + _PER_FDEFAULT(TCP,IC3,NWDSYPAR)\ + |_PER_FDEFAULT(TCP,IC3,NWDINTER)\ + ) + + #define TCP_IC3_RMK(nwdsypar,nwdinter) (Uint32)(\ + _PER_FMK(TCP,IC3,NWDSYPAR,nwdsypar)\ + |_PER_FMK(TCP,IC3,NWDINTER,nwdinter)\ + ) + + #define _TCP_IC3_FGET(FIELD)\ + _PER_FGET(_TCP_IC3_ADDR,TCP,IC3,##FIELD) + + #define _TCP_IC3_FSET(FIELD,field)\ + _PER_FSET(_TCP_IC3_ADDR,TCP,IC3,##FIELD,field) + + #define _TCP_IC3_FSETS(FIELD,SYM)\ + _PER_FSETS(_TCP_IC3_ADDR,TCP,IC3,FIELD,##SYM) + +/******************************************************************************\ +* _____________________ +* | | +* | I C 4 | +* |___________________| +* +* TCP input configuration register 4 +* +* FIELDS (msb -> lsb) +* (rw) NWDEXT +* (rw) NWDAP +* +\******************************************************************************/ + #define _TCP_IC4_OFFSET 4 + + #define _TCP_IC4_ADDR 0x01BA0010u + //#define _TCP_IC4_ADDR 0x58000010u + + #define _TCP_IC4_NWDEXT_MASK 0xFFFF0000u + #define _TCP_IC4_NWDEXT_SHIFT 0x00000010u + #define TCP_IC4_NWDEXT_DEFAULT 0x00000000u + #define TCP_IC4_NWDEXT_OF(x) _VALUEOF(x) + + #define _TCP_IC4_NWDAP_MASK 0x0000FFFFu + #define _TCP_IC4_NWDAP_SHIFT 0x00000000u + #define TCP_IC4_NWDAP_DEFAULT 0x00000000u + #define TCP_IC4_NWDAP_OF(x) _VALUEOF(x) + + #define TCP_IC4_OF(x) _VALUEOF(x) + + #define TCP_IC4_DEFAULT (Uint32)(\ + _PER_FDEFAULT(TCP,IC4,NWDEXT)\ + |_PER_FDEFAULT(TCP,IC4,NWDAP)\ + ) + + #define TCP_IC4_RMK(nwdext,nwdap) (Uint32)(\ + _PER_FMK(TCP,IC4,NWDEXT,nwdext)\ + |_PER_FMK(TCP,IC4,NWDAP,nwdap)\ + ) + + #define _TCP_IC4_FGET(FIELD)\ + _PER_FGET(_TCP_IC4_ADDR,TCP,IC4,##FIELD) + + #define _TCP_IC4_FSET(FIELD,field)\ + _PER_FSET(_TCP_IC4_ADDR,TCP,IC4,##FIELD,field) + + #define _TCP_IC4_FSETS(FIELD,SYM)\ + _PER_FSETS(_TCP_IC4_ADDR,TCP,IC4,FIELD,##SYM) + +/******************************************************************************\ +* _____________________ +* | | +* | I C 5 | +* |___________________| +* +* TCP input configuration register 5 +* +* FIELDS (msb -> lsb) +* (rw) NWDHD +* +\******************************************************************************/ + #define _TCP_IC5_OFFSET 5 + + #define _TCP_IC5_ADDR 0x01BA0014u + //#define _TCP_IC5_ADDR 0x58000014u + + #define _TCP_IC5_NWDHD_MASK 0x0000FFFFu + #define _TCP_IC5_NWDHD_SHIFT 0x00000000u + #define TCP_IC5_NWDHD_DEFAULT 0x00000000u + #define TCP_IC5_NWDHD_OF(x) _VALUEOF(x) + + #define TCP_IC5_OF(x) _VALUEOF(x) + + #define TCP_IC5_DEFAULT (Uint32)(\ + _PER_FDEFAULT(TCP,IC5,NWDHD)\ + ) + + #define TCP_IC5_RMK(nwdhd) (Uint32)(\ + _PER_FMK(TCP,IC5,NWDHD,nwdhd)\ + ) + + #define _TCP_IC5_FGET(FIELD)\ + _PER_FGET(_TCP_IC5_ADDR,TCP,IC5,##FIELD) + + #define _TCP_IC5_FSET(FIELD,field)\ + _PER_FSET(_TCP_IC5_ADDR,TCP,IC5,##FIELD,field) + + #define _TCP_IC5_FSETS(FIELD,SYM)\ + _PER_FSETS(_TCP_IC5_ADDR,TCP,IC5,FIELD,##SYM) + +/******************************************************************************\ +* _____________________ +* | | +* | I C 6 | +* |___________________| +* +* TCP input configuration register 6 +* +* FIELDS (msb -> lsb) +* (rw) TAIL1 +* +\******************************************************************************/ + #define _TCP_IC6_OFFSET 6 + + #define _TCP_IC6_ADDR 0x01BA0018u + // #define _TCP_IC6_ADDR 0x58000018u + + #define _TCP_IC6_TAIL1_MASK 0xFFFFFFFFu + #define _TCP_IC6_TAIL1_SHIFT 0x00000000u + #define TCP_IC6_TAIL1_DEFAULT 0x00000000u + #define TCP_IC6_TAIL1_OF(x) _VALUEOF(x) + + #define TCP_IC6_OF(x) _VALUEOF(x) + + #define TCP_IC6_DEFAULT (Uint32)(\ + _PER_FDEFAULT(TCP,IC6,TAIL1)\ + ) + + #define TCP_IC6_RMK(tail1) (Uint32)(\ + _PER_FMK(TCP,IC6,TAIL1,tail1)\ + ) + + #define _TCP_IC6_FGET(FIELD)\ + _PER_FGET(_TCP_IC6_ADDR,TCP,IC6,##FIELD) + + #define _TCP_IC6_FSET(FIELD,field)\ + _PER_FSET(_TCP_IC6_ADDR,TCP,IC6,##FIELD,field) + + #define _TCP_IC6_FSETS(FIELD,SYM)\ + _PER_FSETS(_TCP_IC6_ADDR,TCP,IC6,FIELD,##SYM) + +/******************************************************************************\ +* _____________________ +* | | +* | I C 7 | +* |___________________| +* +* TCP input configuration register 7 +* +* FIELDS (msb -> lsb) +* (rw) TAIL2 +* +\******************************************************************************/ + #define _TCP_IC7_OFFSET 7 + + #define _TCP_IC7_ADDR 0x01BA001Cu + // #define _TCP_IC7_ADDR 0x5800001Cu + + #define _TCP_IC7_TAIL2_MASK 0xFFFFFFFFu + #define _TCP_IC7_TAIL2_SHIFT 0x00000000u + #define TCP_IC7_TAIL2_DEFAULT 0x00000000u + #define TCP_IC7_TAIL2_OF(x) _VALUEOF(x) + + #define TCP_IC7_OF(x) _VALUEOF(x) + + #define TCP_IC7_DEFAULT (Uint32)(\ + _PER_FDEFAULT(TCP,IC7,TAIL2)\ + ) + + #define TCP_IC7_RMK(tail2) (Uint32)(\ + _PER_FMK(TCP,IC7,TAIL2,tail2)\ + ) + + #define _TCP_IC7_FGET(FIELD)\ + _PER_FGET(_TCP_IC7_ADDR,TCP,IC7,##FIELD) + + #define _TCP_IC7_FSET(FIELD,field)\ + _PER_FSET(_TCP_IC7_ADDR,TCP,IC7,##FIELD,field) + + #define _TCP_IC7_FSETS(FIELD,SYM)\ + _PER_FSETS(_TCP_IC7_ADDR,TCP,IC7,FIELD,##SYM) + +/******************************************************************************\ +* _____________________ +* | | +* | I C 8 | +* |___________________| +* +* TCP input configuration register 8 +* +* FIELDS (msb -> lsb) +* (rw) TAIL3 +* +\******************************************************************************/ + #define _TCP_IC8_OFFSET 8 + + #define _TCP_IC8_ADDR 0x01BA0020u + // #define _TCP_IC8_ADDR 0x58000020u + + #define _TCP_IC8_TAIL3_MASK 0xFFFFFFFFu + #define _TCP_IC8_TAIL3_SHIFT 0x00000000u + #define TCP_IC8_TAIL3_DEFAULT 0x00000000u + #define TCP_IC8_TAIL3_OF(x) _VALUEOF(x) + + #define TCP_IC8_OF(x) _VALUEOF(x) + + #define TCP_IC8_DEFAULT (Uint32)(\ + _PER_FDEFAULT(TCP,IC8,TAIL3)\ + ) + + #define TCP_IC8_RMK(tail3) (Uint32)(\ + _PER_FMK(TCP,IC8,TAIL3,tail3)\ + ) + + #define _TCP_IC8_FGET(FIELD)\ + _PER_FGET(_TCP_IC8_ADDR,TCP,IC8,##FIELD) + + #define _TCP_IC8_FSET(FIELD,field)\ + _PER_FSET(_TCP_IC8_ADDR,TCP,IC8,##FIELD,field) + + #define _TCP_IC8_FSETS(FIELD,SYM)\ + _PER_FSETS(_TCP_IC8_ADDR,TCP,IC8,FIELD,##SYM) + +/******************************************************************************\ +* _____________________ +* | | +* | I C 9 | +* |___________________| +* +* TCP input configuration register 9 +* +* FIELDS (msb -> lsb) +* (rw) TAIL4 +* +\******************************************************************************/ + #define _TCP_IC9_OFFSET 9 + + #define _TCP_IC9_ADDR 0x01BA0024u + //#define _TCP_IC9_ADDR 0x58000024u + + #define _TCP_IC9_TAIL4_MASK 0xFFFFFFFFu + #define _TCP_IC9_TAIL4_SHIFT 0x00000000u + #define TCP_IC9_TAIL4_DEFAULT 0x00000000u + #define TCP_IC9_TAIL4_OF(x) _VALUEOF(x) + + #define TCP_IC9_OF(x) _VALUEOF(x) + + #define TCP_IC9_DEFAULT (Uint32)(\ + _PER_FDEFAULT(TCP,IC9,TAIL4)\ + ) + + #define TCP_IC9_RMK(tail4) (Uint32)(\ + _PER_FMK(TCP,IC9,TAIL4,tail4)\ + ) + + #define _TCP_IC9_FGET(FIELD)\ + _PER_FGET(_TCP_IC9_ADDR,TCP,IC9,##FIELD) + + #define _TCP_IC9_FSET(FIELD,field)\ + _PER_FSET(_TCP_IC9_ADDR,TCP,IC9,##FIELD,field) + + #define _TCP_IC9_FSETS(FIELD,SYM)\ + _PER_FSETS(_TCP_IC9_ADDR,TCP,IC9,FIELD,##SYM) + +/******************************************************************************\ +* _____________________ +* | | +* | I C 1 0 | +* |___________________| +* +* TCP input configuration register 10 +* +* FIELDS (msb -> lsb) +* (rw) TAIL5 +* +\******************************************************************************/ + #define _TCP_IC10_OFFSET 10 + + #define _TCP_IC10_ADDR 0x01BA0028u + // #define _TCP_IC10_ADDR 0x58000028u + + #define _TCP_IC10_TAIL5_MASK 0xFFFFFFFFu + #define _TCP_IC10_TAIL5_SHIFT 0x00000000u + #define TCP_IC10_TAIL5_DEFAULT 0x00000000u + #define TCP_IC10_TAIL5_OF(x) _VALUEOF(x) + + #define TCP_IC10_OF(x) _VALUEOF(x) + + #define TCP_IC10_DEFAULT (Uint32)(\ + _PER_FDEFAULT(TCP,IC10,TAIL5)\ + ) + + #define TCP_IC10_RMK(tail5) (Uint32)(\ + _PER_FMK(TCP,IC10,TAIL5,tail5)\ + ) + + #define _TCP_IC10_FGET(FIELD)\ + _PER_FGET(_TCP_IC10_ADDR,TCP,IC10,##FIELD) + + #define _TCP_IC10_FSET(FIELD,field)\ + _PER_FSET(_TCP_IC10_ADDR,TCP,IC10,##FIELD,field) + + #define _TCP_IC10_FSETS(FIELD,SYM)\ + _PER_FSETS(_TCP_IC10_ADDR,TCP,IC10,FIELD,##SYM) + +/******************************************************************************\ +* _____________________ +* | | +* | I C 1 1 | +* |___________________| +* +* TCP input configuration register 11 +* +* FIELDS (msb -> lsb) +* (rw) TAIL6 +* +\******************************************************************************/ + #define _TCP_IC11_OFFSET 11 + + #define _TCP_IC11_ADDR 0x01BA002Cu + // #define _TCP_IC11_ADDR 0x5800002Cu + + #define _TCP_IC11_TAIL6_MASK 0xFFFFFFFFu + #define _TCP_IC11_TAIL6_SHIFT 0x00000000u + #define TCP_IC11_TAIL6_DEFAULT 0x00000000u + #define TCP_IC11_TAIL6_OF(x) _VALUEOF(x) + + #define TCP_IC11_OF(x) _VALUEOF(x) + + #define TCP_IC11_DEFAULT (Uint32)(\ + _PER_FDEFAULT(TCP,IC11,TAIL6)\ + ) + + #define TCP_IC11_RMK(tail6) (Uint32)(\ + _PER_FMK(TCP,IC11,TAIL6,tail6)\ + ) + + #define _TCP_IC11_FGET(FIELD)\ + _PER_FGET(_TCP_IC11_ADDR,TCP,IC11,##FIELD) + + #define _TCP_IC11_FSET(FIELD,field)\ + _PER_FSET(_TCP_IC11_ADDR,TCP,IC11,##FIELD,field) + + #define _TCP_IC11_FSETS(FIELD,SYM)\ + _PER_FSETS(_TCP_IC11_ADDR,TCP,IC11,FIELD,##SYM) + +/******************************************************************************\ +* _____________________ +* | | +* | O U T | +* |___________________| +* +* TCP output parameters register +* +* FIELDS (msb -> lsb) +* (rw) NIT +* +\******************************************************************************/ + #define _TCP_OUT_OFFSET 12 + + #define _TCP_OUT_ADDR 0x01BA0030u + + #define _TCP_OUT_NIT_MASK 0xFFFF0000u + #define _TCP_OUT_NIT_SHIFT 0x00000010u + #define TCP_OUT_NIT_DEFAULT 0x00000000u + #define TCP_OUT_NIT_OF(x) _VALUEOF(x) + + #define TCP_OUT_OF(x) _VALUEOF(x) + + #define TCP_OUT_DEFAULT (Uint32)(\ + _PER_FDEFAULT(TCP,OUT,NIT)\ + ) + + #define TCP_OUT_RMK(nit) (Uint32)(\ + _PER_FMK(TCP,OUT,NIT,nit)\ + ) + + #define _TCP_OUT_FGET(FIELD)\ + _PER_FGET(_TCP_OUT_ADDR,TCP,OUT,##FIELD) + + #define _TCP_OUT_FSET(FIELD,field)\ + _PER_FSET(_TCP_OUT_ADDR,TCP,OUT,##FIELD,field) + + #define _TCP_OUT_FSETS(FIELD,SYM)\ + _PER_FSETS(_TCP_OUT_ADDR,TCP,OUT,##FIELD,##SYM) + +/******************************************************************************\ +* _____________________ +* | | +* | E X E | +* |___________________| +* +* TCP execution register +* +* FIELDS (msb -> lsb) +* (rw) UNPAUSE +* (rw) PAUSE +* (rw) START +* +\******************************************************************************/ + #define _TCP_EXE_OFFSET 14 + + #define _TCP_EXE_ADDR 0x01BA0038u + + #define _TCP_EXE_UNPAUSE_MASK 0x00000004u //0x7F000000u + #define _TCP_EXE_UNPAUSE_SHIFT 0x00000002u //0x00000018u + #define TCP_EXE_UNPAUSE_DEFAULT 0x00000000u + #define TCP_EXE_UNPAUSE_OF(x) _VALUEOF(x) + #define TCP_EXE_UNPAUSE_UNPAUSE 0x00000001u + + #define _TCP_EXE_PAUSE_MASK 0x00000002u //0x007F0000u + #define _TCP_EXE_PAUSE_SHIFT 0x00000001u + #define TCP_EXE_PAUSE_DEFAULT 0x00000000u + #define TCP_EXE_PAUSE_OF(x) _VALUEOF(x) + #define TCP_EXE_PAUSE_PAUSE 0x00000001u + + #define _TCP_EXE_START_MASK 0x00000001u //0x0000FFFFu + #define _TCP_EXE_START_SHIFT 0x00000000u + #define TCP_EXE_START_DEFAULT 0x00000000u + #define TCP_EXE_START_OF(x) _VALUEOF(x) + #define TCP_EXE_START_START 0x00000001u + + #define TCP_EXE_OF(x) _VALUEOF(x) + + #define TCP_EXE_DEFAULT (Uint32)(\ + _PER_FDEFAULT(TCP,EXE,UNPAUSE)\ + |_PER_FDEFAULT(TCP,EXE,PAUSE)\ + |_PER_FDEFAULT(TCP,EXE,START)\ + ) + + #define TCP_EXE_RMK(unpause,pause,start) (Uint32)(\ + _PER_FMK(TCP,EXE,UNPAUSE,unpause)\ + |_PER_FMK(TCP,EXE,PAUSE,pause)\ + |_PER_FMK(TCP,EXE,START,start)\ + ) + + #define _TCP_EXE_FGET(FIELD)\ + _PER_FGET(_TCP_EXE_ADDR,TCP,EXE,##FIELD) + + #define _TCP_EXE_FSET(FIELD,field)\ + _PER_FSET(_TCP_EXE_ADDR,TCP,EXE,##FIELD,field) + + #define _TCP_EXE_FSETS(FIELD,SYM)\ + _PER_FSETS(_TCP_EXE_ADDR,TCP,EXE,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | E N D | +* |___________________| +* +* TCP endian mode register +* +* FIELDS (msb -> lsb) +* (rw) EXF +* (rw) AP +* (rw) INTER +* (rw) SYSPAR +* +\******************************************************************************/ + #define _TCP_END_OFFSET 16 + + #define _TCP_END_ADDR 0x01BA0040u + + #define _TCP_END_EXT_MASK 0x00000008u + #define _TCP_END_EXT_SHIFT 0x00000003u + #define TCP_END_EXT_DEFAULT 0x00000000u + #define TCP_END_EXT_OF(x) _VALUEOF(x) + #define TCP_END_EXT_32BIT 0x00000000u + #define TCP_END_EXT_NATIVE 0x00000001u + + #define _TCP_END_AP_MASK 0x00000004u + #define _TCP_END_AP_SHIFT 0x00000002u + #define TCP_END_AP_DEFAULT 0x00000000u + #define TCP_END_AP_OF(x) _VALUEOF(x) + #define TCP_END_AP_32BIT 0x00000000u + #define TCP_END_AP_NATIVE 0x00000001u + + #define _TCP_END_INTER_MASK 0x00000002u + #define _TCP_END_INTER_SHIFT 0x00000001u + #define TCP_END_INTER_DEFAULT 0x00000000u + #define TCP_END_INTER_OF(x) _VALUEOF(x) + #define TCP_END_INTER_32BIT 0x00000000u + #define TCP_END_INTER_NATIVE 0x00000001u + + #define _TCP_END_SYSPAR_MASK 0x00000001u + #define _TCP_END_SYSPAR_SHIFT 0x00000000u + #define TCP_END_SYSPAR_DEFAULT 0x00000000u + #define TCP_END_SYSPAR_OF(x) _VALUEOF(x) + #define TCP_END_SYSPAR_32BIT 0x00000000u + #define TCP_END_SYSPAR_NATIVE 0x00000001u + + #define TCP_END_OF(x) _VALUEOF(x) + + #define TCP_END_DEFAULT (Uint32)(\ + _PER_FDEFAULT(TCP,END,EXT)\ + |_PER_FDEFAULT(TCP,END,AP)\ + |_PER_FDEFAULT(TCP,END,INTER)\ + |_PER_FDEFAULT(TCP,END,SYSPAR)\ + ) + + #define TCP_END_RMK(ext,ap,inter,syspar) (Uint32)(\ + _PER_FMK(TCP,END,EXT,ext)\ + |_PER_FMK(TCP,END,AP,ap)\ + |_PER_FMK(TCP,END,INTER,inter)\ + |_PER_FMK(TCP,END,SYSPAR,syspar)\ + ) + + #define _TCP_END_FGET(FIELD)\ + _PER_FGET(_TCP_END_ADDR,TCP,END,##FIELD) + + #define _TCP_END_FSET(FIELD,field)\ + _PER_FSET(_TCP_END_ADDR,TCP,END,##FIELD,field) + + #define _TCP_END_FSETS(FIELD,SYM)\ + _PER_FSETS(_TCP_END_ADDR,TCP,END,##FIELD,##SYM) + +/******************************************************************************\ +* _____________________ +* | | +* | E R R | +* |___________________| +* +* TCP error register +* +* FIELDS (msb -> lsb) +* (r) ACC +* (r) OP +* (r) INT +* (r) LR +* (r) R +* (r) MODE +* (r) SF +* (r) RATE +* (r) P +* (r) F +* (r) ERR +* +\******************************************************************************/ + #define _TCP_ERR_OFFSET 20 + + #define _TCP_ERR_ADDR 0x01BA0050u + + #define _TCP_ERR_ACC_MASK 0x00000800u + #define _TCP_ERR_ACC_SHIFT 0x0000000Bu + #define TCP_ERR_ACC_DEFAULT 0x00000000u + #define TCP_ERR_ACC_OF(x) _VALUEOF(x) + #define TCP_ERR_ACC_NO 0x00000000u + #define TCP_ERR_ACC_YES 0x00000001u + + #define _TCP_ERR_OP_MASK 0x00000400u + #define _TCP_ERR_OP_SHIFT 0x0000000Au + #define TCP_ERR_OP_DEFAULT 0x00000000u + #define TCP_ERR_OP_OF(x) _VALUEOF(x) + #define TCP_ERR_OP_NO 0x00000000u + #define TCP_ERR_OP_YES 0x00000001u + + #define _TCP_ERR_INT_MASK 0x00000200u + #define _TCP_ERR_INT_SHIFT 0x00000009u + #define TCP_ERR_INT_DEFAULT 0x00000000u + #define TCP_ERR_INT_OF(x) _VALUEOF(x) + #define TCP_ERR_INT_NO 0x00000000u + #define TCP_ERR_INT_YES 0x00000001u + + #define _TCP_ERR_LR_MASK 0x00000100u + #define _TCP_ERR_LR_SHIFT 0x00000008u + #define TCP_ERR_LR_DEFAULT 0x00000000u + #define TCP_ERR_LR_OF(x) _VALUEOF(x) + #define TCP_ERR_LR_NO 0x00000000u + #define TCP_ERR_LR_YES 0x00000001u + + #define _TCP_ERR_R_MASK 0x00000080u + #define _TCP_ERR_R_SHIFT 0x00000007u + #define TCP_ERR_R_DEFAULT 0x00000000u + #define TCP_ERR_R_OF(x) _VALUEOF(x) + #define TCP_ERR_R_NO 0x00000000u + #define TCP_ERR_R_YES 0x00000001u + + #define _TCP_ERR_MODE_MASK 0x00000040u + #define _TCP_ERR_MODE_SHIFT 0x00000006u + #define TCP_ERR_MODE_DEFAULT 0x00000000u + #define TCP_ERR_MODE_OF(x) _VALUEOF(x) + #define TCP_ERR_MODE_NO 0x00000000u + #define TCP_ERR_MODE_YES 0x00000001u + + #define _TCP_ERR_SF_MASK 0x00000010u + #define _TCP_ERR_SF_SHIFT 0x00000004u + #define TCP_ERR_SF_DEFAULT 0x00000000u + #define TCP_ERR_SF_OF(x) _VALUEOF(x) + #define TCP_ERR_SF_NO 0x00000000u + #define TCP_ERR_SF_YES 0x00000001u + + #define _TCP_ERR_RATE_MASK 0x00000008u + #define _TCP_ERR_RATE_SHIFT 0x00000003u + #define TCP_ERR_RATE_DEFAULT 0x00000000u + #define TCP_ERR_RATE_OF(x) _VALUEOF(x) + #define TCP_ERR_RATE_NO 0x00000000u + #define TCP_ERR_RATE_YES 0x00000001u + + #define _TCP_ERR_P_MASK 0x00000004u + #define _TCP_ERR_P_SHIFT 0x00000002u + #define TCP_ERR_P_DEFAULT 0x00000000u + #define TCP_ERR_P_OF(x) _VALUEOF(x) + #define TCP_ERR_P_NO 0x00000000u + #define TCP_ERR_P_YES 0x00000001u + + #define _TCP_ERR_F_MASK 0x00000002u + #define _TCP_ERR_F_SHIFT 0x00000001u + #define TCP_ERR_F_DEFAULT 0x00000000u + #define TCP_ERR_F_OF(x) _VALUEOF(x) + #define TCP_ERR_F_NO 0x00000000u + #define TCP_ERR_F_YES 0x00000001u + + #define _TCP_ERR_ERR_MASK 0x00000001u + #define _TCP_ERR_ERR_SHIFT 0x00000000u + #define TCP_ERR_ERR_DEFAULT 0x00000000u + #define TCP_ERR_ERR_OF(x) _VALUEOF(x) + #define TCP_ERR_ERR_NO 0x00000000u + #define TCP_ERR_ERR_YES 0x00000001u + + #define TCP_ERR_OF(x) _VALUEOF(x) + + #define TCP_ERR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(TCP,ERR,ACC)\ + |_PER_FDEFAULT(TCP,ERR,OP)\ + |_PER_FDEFAULT(TCP,ERR,INT)\ + |_PER_FDEFAULT(TCP,ERR,LR)\ + |_PER_FDEFAULT(TCP,ERR,R)\ + |_PER_FDEFAULT(TCP,ERR,MODE)\ + |_PER_FDEFAULT(TCP,ERR,SF)\ + |_PER_FDEFAULT(TCP,ERR,RATE)\ + |_PER_FDEFAULT(TCP,ERR,P)\ + |_PER_FDEFAULT(TCP,ERR,F)\ + |_PER_FDEFAULT(TCP,ERR,ERR)\ + ) +#if (!(CHIP_6413 | CHIP_6418 | CHIP_6410)) + #define TCP_ERR_RMK(acc,op,inter,lr,r,mode, \ + sf,rate,p,f,err) (Uint32)(\ + _PER_FMK(TCP,ERR,ACC,acc)\ + |_PER_FMK(TCP,ERR,OP,op)\ + |_PER_FMK(TCP,ERR,INT,inter)\ + |_PER_FMK(TCP,ERR,LR,lr)\ + |_PER_FMK(TCP,ERR,R,r)\ + |_PER_FMK(TCP,ERR,MODE,mode)\ + |_PER_FMK(TCP,ERR,SF,sf)\ + |_PER_FMK(TCP,ERR,RATE,rate)\ + |_PER_FMK(TCP,ERR,P,p)\ + |_PER_FMK(TCP,ERR,F,f)\ + |_PER_FMK(TCP,ERR,ERR,err)\ + ) +#endif + #define _TCP_ERR_FGET(FIELD)\ + _PER_FGET(_TCP_ERR_ADDR,TCP,ERR,##FIELD) + +/******************************************************************************\ +* _____________________ +* | | +* | S T A T | +* |___________________| +* +* TCP status register +* +* FIELDS (msb -> lsb) +* (r) ROP +* (r) RHD +* (r) REXT +* (r) WAP +* (r) WSP +* (r) WINT +* (r) WIC +* (r) ERR +* (r) RUN +* (r) PAUS +* +\******************************************************************************/ + #define _TCP_STAT_OFFSET 22 + + #define _TCP_STAT_ADDR 0x01BA0058u + + #define _TCP_STAT_ROP_MASK 0x00000200u + #define _TCP_STAT_ROP_SHIFT 0x00000009u + #define TCP_STAT_ROP_DEFAULT 0x00000000u + #define TCP_STAT_ROP_OF(x) _VALUEOF(x) + #define TCP_STAT_ROP_NREADY 0x00000000u + #define TCP_STAT_ROP_READY 0x00000001u + + #define _TCP_STAT_RHD_MASK 0x00000100u + #define _TCP_STAT_RHD_SHIFT 0x00000008u + #define TCP_STAT_RHD_DEFAULT 0x00000000u + #define TCP_STAT_RHD_OF(x) _VALUEOF(x) + #define TCP_STAT_RHD_NREADY 0x00000000u + #define TCP_STAT_RHD_READY 0x00000001u + + #define _TCP_STAT_REXT_MASK 0x00000080u + #define _TCP_STAT_REXT_SHIFT 0x00000007u + #define TCP_STAT_REXT_DEFAULT 0x00000000u + #define TCP_STAT_REXT_OF(x) _VALUEOF(x) + #define TCP_STAT_REXT_NREADY 0x00000000u + #define TCP_STAT_REXT_READY 0x00000001u + + #define _TCP_STAT_WAP_MASK 0x00000040u + #define _TCP_STAT_WAP_SHIFT 0x00000006u + #define TCP_STAT_WAP_DEFAULT 0x00000000u + #define TCP_STAT_WAP_OF(x) _VALUEOF(x) + #define TCP_STAT_WAP_NREADY 0x00000000u + #define TCP_STAT_WAP_READY 0x00000001u + + #define _TCP_STAT_WSP_MASK 0x00000020u + #define _TCP_STAT_WSP_SHIFT 0x00000005u + #define TCP_STAT_WSP_DEFAULT 0x00000000u + #define TCP_STAT_WSP_OF(x) _VALUEOF(x) + #define TCP_STAT_WSP_NREADY 0x00000000u + #define TCP_STAT_WSP_READY 0x00000001u + + #define _TCP_STAT_WINT_MASK 0x00000010u + #define _TCP_STAT_WINT_SHIFT 0x00000004u + #define TCP_STAT_WINT_DEFAULT 0x00000000u + #define TCP_STAT_WINT_OF(x) _VALUEOF(x) + #define TCP_STAT_WINT_NREADY 0x00000000u + #define TCP_STAT_WINT_READY 0x00000001u + + #define _TCP_STAT_WIC_MASK 0x00000008u + #define _TCP_STAT_WIC_SHIFT 0x00000003u + #define TCP_STAT_WIC_DEFAULT 0x00000000u + #define TCP_STAT_WIC_OF(x) _VALUEOF(x) + #define TCP_STAT_WIC_NREADY 0x00000000u + #define TCP_STAT_WIC_READY 0x00000001u + + #define _TCP_STAT_ERR_MASK 0x00000004u + #define _TCP_STAT_ERR_SHIFT 0x00000002u + #define TCP_STAT_ERR_DEFAULT 0x00000000u + #define TCP_STAT_ERR_OF(x) _VALUEOF(x) + #define TCP_STAT_ERR_NO 0x00000000u + #define TCP_STAT_ERR_YES 0x00000001u + + #define _TCP_STAT_RUN_MASK 0x00000002u + #define _TCP_STAT_RUN_SHIFT 0x00000001u + #define TCP_STAT_RUN_DEFAULT 0x00000000u + #define TCP_STAT_RUN_OF(x) _VALUEOF(x) + #define TCP_STAT_RUN_NO 0x00000000u + #define TCP_STAT_RUN_YES 0x00000001u + + #define _TCP_STAT_PAUS_MASK 0x00000001u + #define _TCP_STAT_PAUS_SHIFT 0x00000000u + #define TCP_STAT_PAUS_DEFAULT 0x00000000u + #define TCP_STAT_PAUS_OF(x) _VALUEOF(x) + #define TCP_STAT_PAUS_NO 0x00000000u + #define TCP_STAT_PAUS_YES 0x00000001u + + #define TCP_STAT_OF(x) _VALUEOF(x) + + #define TCP_STAT_DEFAULT (Uint32)(\ + _PER_FDEFAULT(TCP,STAT,ROP)\ + |_PER_FDEFAULT(TCP,STAT,RHD)\ + |_PER_FDEFAULT(TCP,STAT,REX)\ + |_PER_FDEFAULT(TCP,STAT,WAP)\ + |_PER_FDEFAULT(TCP,STAT,WSP)\ + |_PER_FDEFAULT(TCP,STAT,WINT)\ + |_PER_FDEFAULT(TCP,STAT,WIC)\ + |_PER_FDEFAULT(TCP,STAT,ERR)\ + |_PER_FDEFAULT(TCP,STAT,RUN)\ + |_PER_FDEFAULT(TCP,STAT,PAUS)\ + ) + #define TCP_STAT_RMK(rop,rhd,rex,wap,wsp,wint,wic,err,run,paus) (Uint32)(\ + _PER_FMK(TCP,STAT,ROP,rop)\ + |_PER_FMK(TCP,STAT,RHD,rhd)\ + |_PER_FMK(TCP,STAT,REX,rex)\ + |_PER_FMK(TCP,STAT,WAP,wap)\ + |_PER_FMK(TCP,STAT,WSP,wsp)\ + |_PER_FMK(TCP,STAT,WINT,wint)\ + |_PER_FMK(TCP,STAT,WIC,wic)\ + |_PER_FMK(TCP,STAT,ERR,err)\ + |_PER_FMK(TCP,STAT,RUN,run)\ + |_PER_FMK(TCP,STAT,PAUS,paus)\ + ) + #define _TCP_STAT_FGET(FIELD)\ + _PER_FGET(_TCP_STAT_ADDR,TCP,STAT,##FIELD) + + + +/*----------------------------------------------------------------------------*/ + +#endif /* TCP_SUPPORT */ +#endif /* _CSL_TCPHAL_H_ */ +/******************************************************************************\ +* End of csl_tcphal.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_timer.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_timer.h new file mode 100644 index 0000000..7e66b88 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_timer.h @@ -0,0 +1,243 @@ +/******************************************************************************\ +* Copyright (C) 1999-2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_timer.h +* DATE CREATED.. 06/20/1999 +* LAST MODIFIED. 07/24/2004 Re-introduced BIOS dependency due to compatibilty issues +* 02/09/2004 Removed bios related items +* 10/03/2000 +\******************************************************************************/ +#ifndef _CSL_TIMER_H_ +#define _CSL_TIMER_H_ + +#include +#include +#include + + +#if (TIMER_SUPPORT) +/******************************************************************************\ +* scope and inline control macros +\******************************************************************************/ +#ifdef __cplusplus +#define CSLAPI extern "C" far +#else +#define CSLAPI extern far +#endif + +#undef USEDEFS +#undef IDECL +#undef IDEF + +#ifdef _TIMER_MOD_ + #define IDECL CSLAPI + #define USEDEFS + #define IDEF +#else + #ifdef _INLINE + #define IDECL static inline + #define USEDEFS + #define IDEF static inline + #else + #define IDECL CSLAPI + #endif +#endif + + +/******************************************************************************\ +* global macro declarations +\******************************************************************************/ + +/* TIMER_open() flags */ +#define TIMER_OPEN_RESET (0x00000001) + +/* device identifiers for TIMER_open() */ +#define TIMER_DEVANY (-1) +#define TIMER_DEV0 (0) +#define TIMER_DEV1 (1) +#if (TIMER_DEVICE_CNT > 2) + #define TIMER_DEV2 (2) +#endif + + +/******************************************************************************\ +* global typedef declarations +\******************************************************************************/ + +/* handle structure */ +typedef struct { + Uint32 allocated; + Uint32 eventId; + volatile Uint32 *baseAddr; +} TIMER_Obj, *TIMER_Handle; + +/* device configuration structure */ +typedef struct { + Uint32 ctl; + Uint32 prd; + Uint32 cnt; +} TIMER_Config; + + +/******************************************************************************\ +* global variable declarations +\******************************************************************************/ + +/* predefined deviced handles for legacy - should not be used */ +extern far TIMER_Handle _TIMER_hDev0; +extern far TIMER_Handle _TIMER_hDev1; +extern far TIMER_Handle _TIMER_hBios; + + +/******************************************************************************\ +* global function declarations +\******************************************************************************/ +CSLAPI TIMER_Handle TIMER_getBiosHandle(); + +CSLAPI void TIMER_reset(TIMER_Handle hTimer); +CSLAPI void TIMER_resetAll(); + +CSLAPI TIMER_Handle TIMER_open(int devNum, Uint32 flags); +CSLAPI void TIMER_close(TIMER_Handle hTimer); + + +/******************************************************************************\ +* inline function declarations +\******************************************************************************/ +IDECL Uint32 TIMER_getEventId(TIMER_Handle hTimer); + +IDECL void TIMER_start(TIMER_Handle hTimer); +IDECL void TIMER_pause(TIMER_Handle hTimer); +IDECL void TIMER_resume(TIMER_Handle hTimer); + +IDECL Uint32 TIMER_getPeriod(TIMER_Handle hTimer); +IDECL void TIMER_setPeriod(TIMER_Handle hTimer, Uint32 period); +IDECL Uint32 TIMER_getCount(TIMER_Handle hTimer); +IDECL void TIMER_setCount(TIMER_Handle hTimer, Uint32 count); + +IDECL int TIMER_getDatIn(TIMER_Handle hTimer); +IDECL void TIMER_setDatOut(TIMER_Handle hTimer, int Val); +IDECL int TIMER_getTstat(TIMER_Handle hTimer); + +IDECL void TIMER_config(TIMER_Handle hTimer, TIMER_Config *config); +IDECL void TIMER_configArgs(TIMER_Handle hTimer, Uint32 ctl, Uint32 prd, + Uint32 cnt); +IDECL void TIMER_getConfig(TIMER_Handle hTimer, TIMER_Config *config); + + +/******************************************************************************\ +* inline function definitions +\******************************************************************************/ +#ifdef USEDEFS +/*----------------------------------------------------------------------------*/ +IDEF Uint32 TIMER_getEventId(TIMER_Handle hTimer) { + return hTimer->eventId; +} +/*----------------------------------------------------------------------------*/ +IDEF void TIMER_start(TIMER_Handle hTimer) { + TIMER_FSETH(hTimer,CTL,HLD,1); + TIMER_FSETH(hTimer,CTL,GO,1); +} +/*----------------------------------------------------------------------------*/ +IDEF void TIMER_pause(TIMER_Handle hTimer) { + TIMER_FSETH(hTimer,CTL,HLD,0); +} +/*----------------------------------------------------------------------------*/ +IDEF void TIMER_resume(TIMER_Handle hTimer) { + TIMER_FSETH(hTimer,CTL,HLD,1); +} +/*----------------------------------------------------------------------------*/ +IDEF int TIMER_getDatIn(TIMER_Handle hTimer) { + return TIMER_FGETH(hTimer,CTL,DATIN); +} +/*----------------------------------------------------------------------------*/ +IDEF void TIMER_setDatOut(TIMER_Handle hTimer, int val) { + TIMER_FSETH(hTimer,CTL,DATOUT,val); +} +/*----------------------------------------------------------------------------*/ +IDEF int TIMER_getTstat(TIMER_Handle hTimer) { + return TIMER_FGETH(hTimer,CTL,TSTAT); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 TIMER_getPeriod(TIMER_Handle hTimer) { + return TIMER_RGETH(hTimer,PRD); +} +/*----------------------------------------------------------------------------*/ +IDEF void TIMER_setPeriod(TIMER_Handle hTimer, Uint32 period) { + TIMER_RSETH(hTimer,PRD,period); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 TIMER_getCount(TIMER_Handle hTimer) { + return TIMER_RGETH(hTimer,CNT); +} +/*----------------------------------------------------------------------------*/ +IDEF void TIMER_setCount(TIMER_Handle hTimer, Uint32 count) { + TIMER_RSETH(hTimer,CNT,count); +} +/*----------------------------------------------------------------------------*/ +IDEF void TIMER_config(TIMER_Handle hTimer, TIMER_Config *config) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)(hTimer->baseAddr); + register int x0,x1,x2; + + gie = IRQ_globalDisable(); + + x0 = config->ctl; + x1 = config->prd; + x2 = config->cnt; + + base[_TIMER_CTL_OFFSET] = 0x00000000; + base[_TIMER_PRD_OFFSET] = x1; + base[_TIMER_CNT_OFFSET] = x2; + base[_TIMER_CTL_OFFSET] = x0; + + IRQ_globalRestore(gie); +} +/*----------------------------------------------------------------------------*/ +IDEF void TIMER_configArgs(TIMER_Handle hTimer, Uint32 ctl, Uint32 prd, + Uint32 cnt){ + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)(hTimer->baseAddr); + + gie = IRQ_globalDisable(); + + base[_TIMER_CTL_OFFSET] = 0x00000000; + base[_TIMER_PRD_OFFSET] = prd; + base[_TIMER_CNT_OFFSET] = cnt; + base[_TIMER_CTL_OFFSET] = ctl; + + IRQ_globalRestore(gie); +} +/*----------------------------------------------------------------------------*/ +IDEF void TIMER_getConfig(TIMER_Handle hTimer, TIMER_Config *config) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)(hTimer->baseAddr); + volatile TIMER_Config* cfg = (volatile TIMER_Config*)config; + register int x0,x1,x2; + + gie = IRQ_globalDisable(); + + x0 = base[_TIMER_CTL_OFFSET]; + x1 = base[_TIMER_PRD_OFFSET]; + x2 = base[_TIMER_CNT_OFFSET]; + + cfg->ctl = x0; + cfg->prd = x1; + cfg->cnt = x2; + + IRQ_globalRestore(gie); +} +/*----------------------------------------------------------------------------*/ +#endif /* USEDEFS */ + + +#endif /* TIMER_SUPPORT */ +#endif /* _CSL_TIMER_H_ */ +/******************************************************************************\ +* End of csl_timer.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_timerhal.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_timerhal.h new file mode 100644 index 0000000..bc47c27 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_timerhal.h @@ -0,0 +1,492 @@ +/******************************************************************************\ +* Copyright (C) 2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_timerhal.h +* DATE CREATED.. 08/14/2000 +* LAST MODIFIED. 08/02/2004 - Adding support for C6418 +* 09/30/2003 Added SPND field description macros for CTL reg. +* 10/03/2000 +*------------------------------------------------------------------------------ +* REGISTERS +* +* CTL0 - timer control register 0 +* CTL1 - timer control register 1 +* CTL2 - timer control register 2 (1) +* PRD0 - timer period register 0 +* PRD1 - timer period register 1 +* PRD2 - timer period register 2 (1) +* CNT0 - timer count register 0 +* CNT1 - timer count register 1 +* CNT2 - timer count register 2 (1) +* +* (1) - only supported on C64x devices +* +\******************************************************************************/ +#ifndef _CSL_TIMERHAL_H_ +#define _CSL_TIMERHAL_H_ + +#include +#include + +#if (TIMER_SUPPORT) +/******************************************************************************\ +* MISC section +\******************************************************************************/ + +#if (CHIP_6414 | CHIP_6415 | CHIP_6416 | CHIP_DM642 | CHIP_DM641 | CHIP_DM640 | CHIP_6412 | CHIP_6411 | CHIP_6410 | CHIP_6413 | CHIP_6418) + #define TIMER_DEVICE_CNT 3 + #define _TIMER_BASE_DEV0 0x01940000u + #define _TIMER_BASE_DEV1 0x01980000u + #define _TIMER_BASE_DEV2 0x01AC0000u +#else + #define TIMER_DEVICE_CNT 2 + #define _TIMER_BASE_DEV0 0x01940000u + #define _TIMER_BASE_DEV1 0x01980000u +#endif + + +/******************************************************************************\ +* module level register/field access macros +\******************************************************************************/ + + /* ----------------- */ + /* FIELD MAKE MACROS */ + /* ----------------- */ + + #define TIMER_FMK(REG,FIELD,x)\ + _PER_FMK(TIMER,##REG,##FIELD,x) + + #define TIMER_FMKS(REG,FIELD,SYM)\ + _PER_FMKS(TIMER,##REG,##FIELD,##SYM) + + + /* -------------------------------- */ + /* RAW REGISTER/FIELD ACCESS MACROS */ + /* -------------------------------- */ + + #define TIMER_ADDR(REG)\ + _TIMER_##REG##_ADDR + + #define TIMER_RGET(REG)\ + _PER_RGET(_TIMER_##REG##_ADDR,TIMER,##REG) + + #define TIMER_RSET(REG,x)\ + _PER_RSET(_TIMER_##REG##_ADDR,TIMER,##REG,x) + + #define TIMER_FGET(REG,FIELD)\ + _TIMER_##REG##_FGET(##FIELD) + + #define TIMER_FSET(REG,FIELD,x)\ + _TIMER_##REG##_FSET(##FIELD,##x) + + #define TIMER_FSETS(REG,FIELD,SYM)\ + _TIMER_##REG##_FSETS(##FIELD,##SYM) + + + /* ------------------------------------------ */ + /* ADDRESS BASED REGISTER/FIELD ACCESS MACROS */ + /* ------------------------------------------ */ + + #define TIMER_RGETA(addr,REG)\ + _PER_RGET(addr,TIMER,##REG) + + #define TIMER_RSETA(addr,REG,x)\ + _PER_RSET(addr,TIMER,##REG,x) + + #define TIMER_FGETA(addr,REG,FIELD)\ + _PER_FGET(addr,TIMER,##REG,##FIELD) + + #define TIMER_FSETA(addr,REG,FIELD,x)\ + _PER_FSET(addr,TIMER,##REG,##FIELD,x) + + #define TIMER_FSETSA(addr,REG,FIELD,SYM)\ + _PER_FSETS(addr,TIMER,##REG,##FIELD,##SYM) + + + /* ----------------------------------------- */ + /* HANDLE BASED REGISTER/FIELD ACCESS MACROS */ + /* ----------------------------------------- */ + + #define TIMER_ADDRH(h,REG)\ + (Uint32)(&((h)->baseAddr[_TIMER_##REG##_OFFSET])) + + #define TIMER_RGETH(h,REG)\ + TIMER_RGETA(TIMER_ADDRH(h,##REG),##REG) + + + #define TIMER_RSETH(h,REG,x)\ + TIMER_RSETA(TIMER_ADDRH(h,##REG),##REG,x) + + + #define TIMER_FGETH(h,REG,FIELD)\ + TIMER_FGETA(TIMER_ADDRH(h,##REG),##REG,##FIELD) + + + #define TIMER_FSETH(h,REG,FIELD,x)\ + TIMER_FSETA(TIMER_ADDRH(h,##REG),##REG,##FIELD,x) + + + #define TIMER_FSETSH(h,REG,FIELD,SYM)\ + TIMER_FSETSA(TIMER_ADDRH(h,##REG),##REG,##FIELD,##SYM) + + + +/******************************************************************************\ +* _____________________ +* | | +* | C T L | +* |___________________| +* +* CTL0 - timer control register 0 +* CTL1 - timer control register 1 +* CTL2 - timer control register 2 (1) +* +* FIELDS (msb -> lsb) +* (rw) SPND (1) +* (r) TSTAT +* (rw) INVINP +* (rw) CLKSRC +* (rw) CP +* (rw) HLD +* (rw) GO +* (rw) PWID +* (r) DATIN +* (rw) DATOUT +* (rw) INVOUT +* (rw) FUNC +* +* (1) - only supported on C64x devices +\******************************************************************************/ + #define _TIMER_CTL_OFFSET 0 + + #define _TIMER_CTL0_ADDR 0x01940000u + #define _TIMER_CTL1_ADDR 0x01980000u + #if (TIMER_DEVICE_CNT == 3) + #define _TIMER_CTL2_ADDR 0x01AC0000u + #endif + + #if (C64_SUPPORT) + #define _TIMER_CTL_SPND_MASK 0x00008000u + #define _TIMER_CTL_SPND_SHIFT 0x0000000Fu + #define TIMER_CTL_SPND_DEFAULT 0x00000000u + #define TIMER_CTL_SPND_OF(x) _VALUEOF(x) + #define TIMER_CTL_SPND_EMUSTOP 0x00000001u + #define TIMER_CTL_SPND_EMURUN 0x00000000u + #endif + + #define _TIMER_CTL_TSTAT_MASK 0x00000800u + #define _TIMER_CTL_TSTAT_SHIFT 0x0000000Bu + #define TIMER_CTL_TSTAT_DEFAULT 0x00000000u + #define TIMER_CTL_TSTAT_OF(x) _VALUEOF(x) + #define TIMER_CTL_TSTAT_0 0x00000000u + #define TIMER_CTL_TSTAT_1 0x00000001u + + #define _TIMER_CTL_INVINP_MASK 0x00000400u + #define _TIMER_CTL_INVINP_SHIFT 0x0000000Au + #define TIMER_CTL_INVINP_DEFAULT 0x00000000u + #define TIMER_CTL_INVINP_OF(x) _VALUEOF(x) + #define TIMER_CTL_INVINP_NO 0x00000000u + #define TIMER_CTL_INVINP_YES 0x00000001u + + #define _TIMER_CTL_CLKSRC_MASK 0x00000200u + #define _TIMER_CTL_CLKSRC_SHIFT 0x00000009u + #define TIMER_CTL_CLKSRC_DEFAULT 0x00000000u + #define TIMER_CTL_CLKSRC_OF(x) _VALUEOF(x) + #define TIMER_CTL_CLKSRC_EXTERNAL 0x00000000u + #if (C64_SUPPORT) + #define TIMER_CTL_CLKSRC_CPUOVR8 0x00000001u + #else + #define TIMER_CTL_CLKSRC_CPUOVR4 0x00000001u + #endif + + #define _TIMER_CTL_CP_MASK 0x00000100u + #define _TIMER_CTL_CP_SHIFT 0x00000008u + #define TIMER_CTL_CP_DEFAULT 0x00000000u + #define TIMER_CTL_CP_OF(x) _VALUEOF(x) + #define TIMER_CTL_CP_PULSE 0x00000000u + #define TIMER_CTL_CP_CLOCK 0x00000001u + + #define _TIMER_CTL_HLD_MASK 0x00000080u + #define _TIMER_CTL_HLD_SHIFT 0x00000007u + #define TIMER_CTL_HLD_DEFAULT 0x00000000u + #define TIMER_CTL_HLD_OF(x) _VALUEOF(x) + #define TIMER_CTL_HLD_YES 0x00000000u + #define TIMER_CTL_HLD_NO 0x00000001u + + #define _TIMER_CTL_GO_MASK 0x00000040u + #define _TIMER_CTL_GO_SHIFT 0x00000006u + #define TIMER_CTL_GO_DEFAULT 0x00000000u + #define TIMER_CTL_GO_OF(x) _VALUEOF(x) + #define TIMER_CTL_GO_NO 0x00000000u + #define TIMER_CTL_GO_YES 0x00000001u + + #define _TIMER_CTL_PWID_MASK 0x00000010u + #define _TIMER_CTL_PWID_SHIFT 0x00000004u + #define TIMER_CTL_PWID_DEFAULT 0x00000000u + #define TIMER_CTL_PWID_OF(x) _VALUEOF(x) + #define TIMER_CTL_PWID_ONE 0x00000000u + #define TIMER_CTL_PWID_TWO 0x00000001u + + #define _TIMER_CTL_DATIN_MASK 0x00000008u + #define _TIMER_CTL_DATIN_SHIFT 0x00000003u + #define TIMER_CTL_DATIN_DEFAULT 0x00000000u + #define TIMER_CTL_DATIN_OF(x) _VALUEOF(x) + #define TIMER_CTL_DATIN_0 0x00000000u + #define TIMER_CTL_DATIN_1 0x00000001u + + #define _TIMER_CTL_DATOUT_MASK 0x00000004u + #define _TIMER_CTL_DATOUT_SHIFT 0x00000002u + #define TIMER_CTL_DATOUT_DEFAULT 0x00000000u + #define TIMER_CTL_DATOUT_OF(x) _VALUEOF(x) + #define TIMER_CTL_DATOUT_0 0x00000000u + #define TIMER_CTL_DATOUT_1 0x00000001u + + #define _TIMER_CTL_INVOUT_MASK 0x00000002u + #define _TIMER_CTL_INVOUT_SHIFT 0x00000001u + #define TIMER_CTL_INVOUT_DEFAULT 0x00000000u + #define TIMER_CTL_INVOUT_OF(x) _VALUEOF(x) + #define TIMER_CTL_INVOUT_NO 0x00000000u + #define TIMER_CTL_INVOUT_YES 0x00000001u + + #define _TIMER_CTL_FUNC_MASK 0x00000001u + #define _TIMER_CTL_FUNC_SHIFT 0x00000000u + #define TIMER_CTL_FUNC_DEFAULT 0x00000000u + #define TIMER_CTL_FUNC_OF(x) _VALUEOF(x) + #define TIMER_CTL_FUNC_GPIO 0x00000000u + #define TIMER_CTL_FUNC_TOUT 0x00000001u + + #define TIMER_CTL_OF(x) _VALUEOF(x) + + #if (C64_SUPPORT) + #define TIMER_CTL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(TIMER,CTL,SPND) \ + |_PER_FDEFAULT(TIMER,CTL,TSTAT) \ + |_PER_FDEFAULT(TIMER,CTL,INVINP) \ + |_PER_FDEFAULT(TIMER,CTL,CLKSRC) \ + |_PER_FDEFAULT(TIMER,CTL,CP) \ + |_PER_FDEFAULT(TIMER,CTL,HLD) \ + |_PER_FDEFAULT(TIMER,CTL,GO) \ + |_PER_FDEFAULT(TIMER,CTL,PWID) \ + |_PER_FDEFAULT(TIMER,CTL,DATIN) \ + |_PER_FDEFAULT(TIMER,CTL,DATOUT) \ + |_PER_FDEFAULT(TIMER,CTL,INVOUT) \ + |_PER_FDEFAULT(TIMER,CTL,FUNC) \ + ) + #else + #define TIMER_CTL_DEFAULT (Uint32)( \ + _PER_FDEFAULT(TIMER,CTL,TSTAT) \ + |_PER_FDEFAULT(TIMER,CTL,INVINP) \ + |_PER_FDEFAULT(TIMER,CTL,CLKSRC) \ + |_PER_FDEFAULT(TIMER,CTL,CP) \ + |_PER_FDEFAULT(TIMER,CTL,HLD) \ + |_PER_FDEFAULT(TIMER,CTL,GO) \ + |_PER_FDEFAULT(TIMER,CTL,PWID) \ + |_PER_FDEFAULT(TIMER,CTL,DATIN) \ + |_PER_FDEFAULT(TIMER,CTL,DATOUT) \ + |_PER_FDEFAULT(TIMER,CTL,INVOUT) \ + |_PER_FDEFAULT(TIMER,CTL,FUNC) \ + ) + #endif + + #if (C64_SUPPORT) + #define TIMER_CTL_RMK(spnd,invinp,clksrc,cp,hld,go,pwid,datout,invout,func) \ + (Uint32)( \ + _PER_FMK(TIMER,CTL,SPND,spnd) \ + |_PER_FMK(TIMER,CTL,INVINP,invinp) \ + |_PER_FMK(TIMER,CTL,CLKSRC,clksrc) \ + |_PER_FMK(TIMER,CTL,CP,cp) \ + |_PER_FMK(TIMER,CTL,HLD,hld) \ + |_PER_FMK(TIMER,CTL,GO,go) \ + |_PER_FMK(TIMER,CTL,PWID,pwid) \ + |_PER_FMK(TIMER,CTL,DATOUT,datout) \ + |_PER_FMK(TIMER,CTL,INVOUT,invout) \ + |_PER_FMK(TIMER,CTL,FUNC,func) \ + ) + #else + #define TIMER_CTL_RMK(invinp,clksrc,cp,hld,go,pwid,datout,invout,func) \ + (Uint32)( \ + _PER_FMK(TIMER,CTL,INVINP,invinp) \ + |_PER_FMK(TIMER,CTL,CLKSRC,clksrc) \ + |_PER_FMK(TIMER,CTL,CP,cp) \ + |_PER_FMK(TIMER,CTL,HLD,hld) \ + |_PER_FMK(TIMER,CTL,GO,go) \ + |_PER_FMK(TIMER,CTL,PWID,pwid) \ + |_PER_FMK(TIMER,CTL,DATOUT,datout) \ + |_PER_FMK(TIMER,CTL,INVOUT,invout) \ + |_PER_FMK(TIMER,CTL,FUNC,func) \ + ) + #endif + + + #define _TIMER_CTL_FGET(N,FIELD)\ + _PER_FGET(_TIMER_CTL##N##_ADDR,TIMER,CTL,##FIELD) + + #define _TIMER_CTL_FSET(N,FIELD,f)\ + _PER_FSET(_TIMER_CTL##N##_ADDR,TIMER,CTL,##FIELD,f) + + #define _TIMER_CTL_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_TIMER_CTL##N##_ADDR,TIMER,CTL,##FIELD,##SYM) + + #define _TIMER_CTL0_FGET(FIELD) _TIMER_CTL_FGET(0,##FIELD) + #define _TIMER_CTL1_FGET(FIELD) _TIMER_CTL_FGET(1,##FIELD) + #if TIMER_DEVICE_CNT == 3 + #define _TIMER_CTL2_FGET(FIELD) _TIMER_CTL_FGET(2,##FIELD) + #endif + + #define _TIMER_CTL0_FSET(FIELD,f) _TIMER_CTL_FSET(0,##FIELD,f) + #define _TIMER_CTL1_FSET(FIELD,f) _TIMER_CTL_FSET(1,##FIELD,f) + #if TIMER_DEVICE_CNT == 3 + #define _TIMER_CTL2_FSET(FIELD,f) _TIMER_CTL_FSET(2,##FIELD,f) + #endif + + #define _TIMER_CTL0_FSETS(FIELD,SYM) _TIMER_CTL_FSETS(0,##FIELD,##SYM) + #define _TIMER_CTL1_FSETS(FIELD,SYM) _TIMER_CTL_FSETS(1,##FIELD,##SYM) + #if TIMER_DEVICE_CNT == 3 + #define _TIMER_CTL2_FSETS(FIELD,SYM) _TIMER_CTL_FSETS(2,##FIELD,##SYM) + #endif + + +/******************************************************************************\ +* _____________________ +* | | +* | P R D | +* |___________________| +* +* PRD0 - timer period register 0 +* PRD1 - timer period register 1 +* PRD2 - timer period register 2 (1) +* +* (1) - only supported on C64x devices +* +* FIELDS (msb -> lsb) +* (rw) PRD +* +\******************************************************************************/ + #define _TIMER_PRD_OFFSET 1 + + #define _TIMER_PRD0_ADDR 0x01940004u + #define _TIMER_PRD1_ADDR 0x01980004u + #if TIMER_DEVICE_CNT == 3 + #define _TIMER_PRD2_ADDR 0x01AC0004u + #endif + + #define _TIMER_PRD_PRD_MASK 0xFFFFFFFFu + #define _TIMER_PRD_PRD_SHIFT 0x00000000u + #define TIMER_PRD_PRD_DEFAULT 0x00000000u + #define TIMER_PRD_PRD_OF(x) _VALUEOF(x) + + #define TIMER_PRD_OF(x) _VALUEOF(x) + + #define TIMER_PRD_DEFAULT (Uint32)( \ + _PER_FDEFAULT(TIMER,PRD,PRD) \ + ) + + #define TIMER_PRD_RMK(prd) (Uint32)( \ + _PER_FMK(TIMER,PRD,PRD,prd) \ + ) + + #define _TIMER_PRD_FGET(N,FIELD)\ + _PER_FGET(_TIMER_PRD##N##_ADDR,TIMER,PRD,##FIELD) + + #define _TIMER_PRD_FSET(N,FIELD,f)\ + _PER_FSET(_TIMER_PRD##N##_ADDR,TIMER,PRD,##FIELD,f) + + #define _TIMER_PRD_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_TIMER_PRD##N##_ADDR,TIMER,PRD,##FIELD,##SYM) + + #define _TIMER_PRD0_FGET(FIELD) _TIMER_PRD_FGET(0,##FIELD) + #define _TIMER_PRD1_FGET(FIELD) _TIMER_PRD_FGET(1,##FIELD) + #if TIMER_DEVICE_CNT == 3 + #define _TIMER_PRD2_FGET(FIELD) _TIMER_PRD_FGET(2,##FIELD) + #endif + + #define _TIMER_PRD0_FSET(FIELD,f) _TIMER_PRD_FSET(0,##FIELD,f) + #define _TIMER_PRD1_FSET(FIELD,f) _TIMER_PRD_FSET(1,##FIELD,f) + #if TIMER_DEVICE_CNT == 3 + #define _TIMER_PRD2_FSET(FIELD,f) _TIMER_PRD_FSET(2,##FIELD,f) + #endif + + #define _TIMER_PRD0_FSETS(FIELD,SYM) _TIMER_PRD_FSETS(0,##FIELD,##SYM) + #define _TIMER_PRD1_FSETS(FIELD,SYM) _TIMER_PRD_FSETS(1,##FIELD,##SYM) + #if TIMER_DEVICE_CNT == 3 + #define _TIMER_PRD2_FSETS(FIELD,SYM) _TIMER_PRD_FSETS(2,##FIELD,##SYM) + #endif + + +/******************************************************************************\ +* _____________________ +* | | +* | C N T | +* |___________________| +* +* CNT0 - timer count register 0 +* CNT1 - timer count register 1 +* CNT2 - timer count register 2 (1) +* +* (1) - only supported on C64x devices +* +* FIELDS (msb -> lsb) +* (rw) CNT +* +\******************************************************************************/ + #define _TIMER_CNT_OFFSET 2 + + #define _TIMER_CNT0_ADDR 0x01940008u + #define _TIMER_CNT1_ADDR 0x01980008u + #if TIMER_DEVICE_CNT == 3 + #define _TIMER_CNT2_ADDR 0x01AC0008u + #endif + + #define _TIMER_CNT_CNT_MASK 0xFFFFFFFFu + #define _TIMER_CNT_CNT_MASK 0xFFFFFFFFu + #define _TIMER_CNT_CNT_SHIFT 0x00000000u + #define TIMER_CNT_CNT_DEFAULT 0x00000000u + #define TIMER_CNT_CNT_OF(x) _VALUEOF(x) + + #define TIMER_CNT_OF(x) _VALUEOF(x) + + #define TIMER_CNT_DEFAULT (Uint32)( \ + _PER_FDEFAULT(TIMER,CNT,CNT) \ + ) + + #define TIMER_CNT_RMK(cnt) (Uint32)( \ + _PER_FMK(TIMER,CNT,CNT,cnt) \ + ) + + #define _TIMER_CNT_FGET(N,FIELD)\ + _PER_FGET(_TIMER_CNT##N##_ADDR,TIMER,CNT,##FIELD) + + #define _TIMER_CNT_FSET(N,FIELD,f)\ + _PER_FSET(_TIMER_CNT##N##_ADDR,TIMER,CNT,##FIELD,f) + + #define _TIMER_CNT_FSETS(N,FIELD,SYM)\ + _PER_FSETS(_TIMER_CNT##N##_ADDR,TIMER,CNT,##FIELD,##SYM) + + #define _TIMER_CNT0_FGET(FIELD) _TIMER_CNT_FGET(0,##FIELD) + #define _TIMER_CNT1_FGET(FIELD) _TIMER_CNT_FGET(1,##FIELD) + #if TIMER_DEVICE_CNT == 3 + #define _TIMER_CNT2_FGET(FIELD) _TIMER_CNT_FGET(2,##FIELD) + #endif + + #define _TIMER_CNT0_FSET(FIELD,f) _TIMER_CNT_FSET(0,##FIELD,f) + #define _TIMER_CNT1_FSET(FIELD,f) _TIMER_CNT_FSET(1,##FIELD,f) + #if TIMER_DEVICE_CNT == 3 + #define _TIMER_CNT2_FSET(FIELD,f) _TIMER_CNT_FSET(2,##FIELD,f) + #endif + + #define _TIMER_CNT0_FSETS(FIELD,SYM) _TIMER_CNT_FSETS(0,##FIELD,##SYM) + #define _TIMER_CNT1_FSETS(FIELD,SYM) _TIMER_CNT_FSETS(1,##FIELD,##SYM) + #if TIMER_DEVICE_CNT == 3 + #define _TIMER_CNT2_FSETS(FIELD,SYM) _TIMER_CNT_FSETS(2,##FIELD,##SYM) + #endif + + +/*----------------------------------------------------------------------------*/ + +#endif /* (TIMER_SUPPORT) */ +#endif /* _CSL_TIMERHAL_H_ */ +/******************************************************************************\ +* End of csl_timerhal.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_utop.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_utop.h new file mode 100644 index 0000000..d51a354 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_utop.h @@ -0,0 +1,252 @@ +/******************************************************************************\ +* Copyright (C) 2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_utop.h +* DATE CREATED.. 07/19/2000 +* LAST MODIFIED. 12/22/2000 +\******************************************************************************/ +#ifndef _CSL_UTOP_H_ +#define _CSL_UTOP_H_ + +#include +#include +#include + +#if (UTOP_SUPPORT) +/******************************************************************************\ +* scope and inline control macros +\******************************************************************************/ +#ifdef __cplusplus +#define CSLAPI extern "C" far +#else +#define CSLAPI extern far +#endif + +#undef USEDEFS +#undef IDECL +#undef IDEF + +#ifdef _UTOP_MOD_ + #define IDECL CSLAPI + #define USEDEFS + #define IDEF +#else + #ifdef _INLINE + #define IDECL static inline + #define USEDEFS + #define IDEF static inline + #else + #define IDECL CSLAPI + #endif +#endif + +/******************************************************************************\ +* global macro declarations +\******************************************************************************/ + +/* utopia interrupt numbers */ +#define UTOP_INT_XQ 0 +#define UTOP_INT_RQ 16 + +/* utopia error interrupt numbers */ +#define UTOP_ERR_RQS 0 +#define UTOP_ERR_RCF 1 +#define UTOP_ERR_RCP 2 +#define UTOP_ERR_XQS 16 +#define UTOP_ERR_XCF 17 +#define UTOP_ERR_XCP 18 + +#define UTOP_RCVQ_ADDR _UTOP_BASE_RQUEUE +#define UTOP_XMTQ_ADDR _UTOP_BASE_XQUEUE + + +/******************************************************************************\ +* global typedef declarations +\******************************************************************************/ + +/* device configuration structure */ +typedef struct { + Uint32 ucr; + Uint32 cdr; +} UTOP_Config; + +/******************************************************************************\ +* global variable declarations +\******************************************************************************/ + + +/******************************************************************************\ +* global function declarations +\******************************************************************************/ +CSLAPI void UTOP_reset(); + +/******************************************************************************\ +* inline function declarations +\******************************************************************************/ +IDECL Uint32 UTOP_getXmtAddr(); +IDECL Uint32 UTOP_getRcvAddr(); +IDECL Uint32 UTOP_getEventId(); + +/* UTOP_read/write is for CPU servicing Utopia */ +IDECL Uint32 UTOP_read(); +IDECL void UTOP_write(Uint32 val); + +IDECL void UTOP_enableXmt(); +IDECL void UTOP_enableRcv(); + +IDECL void UTOP_intDisable(Uint32 intNum); +IDECL void UTOP_intEnable(Uint32 intNum); +IDECL void UTOP_intClear(Uint32 intNum); +IDECL Uint32 UTOP_intTest(Uint32 intNum); +IDECL void UTOP_intReset(Uint32 intNum); + +IDECL void UTOP_errDisable(Uint32 errNum); +IDECL void UTOP_errEnable(Uint32 errNum); +IDECL void UTOP_errClear(Uint32 errNum); +IDECL Uint32 UTOP_errTest(Uint32 errNum); +IDECL void UTOP_errReset(Uint32 errNum); + +IDECL void UTOP_config(UTOP_Config *config); +IDECL void UTOP_configArgs(Uint32 ucr, Uint32 cdr); +IDECL void UTOP_getConfig(UTOP_Config *config); + + +/******************************************************************************\ +* inline function definitions +\******************************************************************************/ +#ifdef USEDEFS +/*----------------------------------------------------------------------------*/ +IDEF Uint32 UTOP_getXmtAddr() { + return (Uint32)(_UTOP_BASE_XQUEUE); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 UTOP_getRcvAddr() { + return (Uint32)(_UTOP_BASE_RQUEUE); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 UTOP_getEventId() { + return (IRQ_EVT_UINT); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 UTOP_read() { + return (*(volatile Uint32*)(_UTOP_BASE_RQUEUE)); +} +/*----------------------------------------------------------------------------*/ +IDEF void UTOP_write(Uint32 val) { + (*(volatile Uint32*)(_UTOP_BASE_XQUEUE)) = val; +} +/*----------------------------------------------------------------------------*/ +IDEF void UTOP_enableXmt() { + UTOP_FSETS(UCR,UXEN,ENABLE); +} +/*----------------------------------------------------------------------------*/ +IDEF void UTOP_enableRcv() { + UTOP_FSETS(UCR,UREN,ENABLE); +} +/*----------------------------------------------------------------------------*/ +IDEF void UTOP_intDisable(Uint32 intNum){ + UTOP_RSET(UIER,UTOP_RGET(UIER)&~(1<ucr; + x1 = config->cdr; + + base[_UTOP_UCR_OFFSET] = 0x00000000u; + base[_UTOP_CDR_OFFSET] = x1; + base[_UTOP_UCR_OFFSET] = x0; /* Enable interface after everything is set up */ + + IRQ_globalRestore(gie); +} +/*----------------------------------------------------------------------------*/ +IDEF void UTOP_configArgs(Uint32 ucr, Uint32 cdr) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)_UTOP_UCR_ADDR; + + gie = IRQ_globalDisable(); + + base[_UTOP_UCR_OFFSET] = 0x00000000u; + base[_UTOP_CDR_OFFSET] = cdr; + base[_UTOP_UCR_OFFSET] = ucr; /* Enable interface after everything is set up */ + + IRQ_globalRestore(gie); +} +/*----------------------------------------------------------------------------*/ +IDEF void UTOP_getConfig(UTOP_Config *config) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *)_UTOP_UCR_ADDR; + register int x0,x1; + + gie = IRQ_globalDisable(); + + /* the compiler generates more efficient code if the loads */ + /* and stores are grouped together rather than intermixed */ + + x0 = base[_UTOP_UCR_OFFSET]; + x1 = base[_UTOP_CDR_OFFSET]; + + config->ucr = x0; + config->cdr = x1; + + IRQ_globalRestore(gie); +} +/*----------------------------------------------------------------------------*/ +#endif /* USEDEFS */ + + +#endif /* UTOP_SUPPORT */ +#endif /* _CSL_UTOP_H_ */ +/******************************************************************************\ +* End of csl_utop.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_utophal.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_utophal.h new file mode 100644 index 0000000..bd69797 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_utophal.h @@ -0,0 +1,521 @@ +/******************************************************************************\ +* Copyright (C) 2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_utophal.h +* DATE CREATED.. 07/19/2000 +* LAST MODIFIED. 09/21/2001 +*------------------------------------------------------------------------------ +* REGISTERS +* +* UCR - Utopia Control Register +* UIER - Utopia Interrupt Enable Register +* UIPR - Utopia Interrupt Pending Register +* CDR - Clock Detect Register +* EIER - Error Interrupt Enable Register +* EIPR - Error Interrupt Pending Register +* +\******************************************************************************/ +#ifndef _CSL_UTOPHAL_H_ +#define _CSL_UTOPHAL_H_ + +#include +#include + +#if (UTOP_SUPPORT) +/******************************************************************************\ +* MISC section +\******************************************************************************/ + #define _UTOP_BASE_GLOBAL 0x01B40000u + #define _UTOP_BASE_RQUEUE 0x3C000000u + #define _UTOP_BASE_XQUEUE 0x3D000000u + +/******************************************************************************\ +* module level register/field access macros +\******************************************************************************/ + + /* ----------------- */ + /* FIELD MAKE MACROS */ + /* ----------------- */ + + #define UTOP_FMK(REG,FIELD,x)\ + _PER_FMK(UTOP,##REG,##FIELD,x) + + #define UTOP_FMKS(REG,FIELD,SYM)\ + _PER_FMKS(UTOP,##REG,##FIELD,##SYM) + + + /* -------------------------------- */ + /* RAW REGISTER/FIELD ACCESS MACROS */ + /* -------------------------------- */ + + #define UTOP_ADDR(REG)\ + _UTOP_##REG##_ADDR + + #define UTOP_RGET(REG)\ + _PER_RGET(_UTOP_##REG##_ADDR,UTOP,##REG) + + #define UTOP_RSET(REG,x)\ + _PER_RSET(_UTOP_##REG##_ADDR,UTOP,##REG,x) + + #define UTOP_FGET(REG,FIELD)\ + _UTOP_##REG##_FGET(##FIELD) + + #define UTOP_FSET(REG,FIELD,x)\ + _UTOP_##REG##_FSET(##FIELD,##x) + + #define UTOP_FSETS(REG,FIELD,SYM)\ + _UTOP_##REG##_FSETS(##FIELD,##SYM) + + + /* ------------------------------------------ */ + /* ADDRESS BASED REGISTER/FIELD ACCESS MACROS */ + /* ------------------------------------------ */ + + #define UTOP_RGETA(addr,REG)\ + _PER_RGET(addr,UTOP,##REG) + + #define UTOP_RSETA(addr,REG,x)\ + _PER_RSET(addr,UTOP,##REG,x) + + #define UTOP_FGETA(addr,REG,FIELD)\ + _PER_FGET(addr,UTOP,##REG,##FIELD) + + #define UTOP_FSETA(addr,REG,FIELD,x)\ + _PER_FSET(addr,UTOP,##REG,##FIELD,x) + + #define UTOP_FSETSA(addr,REG,FIELD,SYM)\ + _PER_FSETS(addr,UTOP,##REG,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | U C R | +* |___________________| +* +* UCR - Utopia Control Register +* +* Fields (msb --> lsb): +* (rw) BEND +* (rw) SLIDSLEND +* (rw) XUDC +* (rw) UXEN +* (rw) MPHY +* (rw) RUDC +* (rw) UREN + +\******************************************************************************/ + #define _UTOP_UCR_OFFSET 0 + + #define _UTOP_UCR_ADDR 0x01B40000u + + #define _UTOP_UCR_BEND_MASK 0x80000000u + #define _UTOP_UCR_BEND_SHIFT 0x0000001Fu + #define UTOP_UCR_BEND_DEFAULT 0x00000000u + #define UTOP_UCR_BEND_OF(x) _VALUEOF(x) + #define UTOP_UCR_BEND_LITTLE 0x00000000u + #define UTOP_UCR_BEND_BIG 0x00000001u + + #define _UTOP_UCR_SLID_MASK 0x1F000000u + #define _UTOP_UCR_SLID_SHIFT 0x00000018u + #define UTOP_UCR_SLID_DEFAULT 0x00000000u + #define UTOP_UCR_SLID_OF(x) _VALUEOF(x) + #define UTOP_UCR_SLID_NULL 0x0000001Fu + + #define _UTOP_UCR_XUDC_MASK 0x003C0000u + #define _UTOP_UCR_XUDC_SHIFT 0x00000012u + #define UTOP_UCR_XUDC_DEFAULT 0x00000000u + #define UTOP_UCR_XUDC_OF(x) _VALUEOF(x) + + #define _UTOP_UCR_UXEN_MASK 0x00010000u + #define _UTOP_UCR_UXEN_SHIFT 0x00000010u + #define UTOP_UCR_UXEN_DEFAULT 0x00000000u + #define UTOP_UCR_UXEN_OF(x) _VALUEOF(x) + #define UTOP_UCR_UXEN_DISABLE 0x00000000u + #define UTOP_UCR_UXEN_ENABLE 0x00000001u + + #define _UTOP_UCR_MPHY_MASK 0x00004000u + #define _UTOP_UCR_MPHY_SHIFT 0x0000000Eu + #define UTOP_UCR_MPHY_DEFAULT 0x00000000u + #define UTOP_UCR_MPHY_OF(x) _VALUEOF(x) + #define UTOP_UCR_MPHY_SINGLE 0x00000000u + #define UTOP_UCR_MPHY_MULTI 0x00000001u + + #define _UTOP_UCR_RUDC_MASK 0x0000003Cu + #define _UTOP_UCR_RUDC_SHIFT 0x00000002u + #define UTOP_UCR_RUDC_DEFAULT 0x00000000u + #define UTOP_UCR_RUDC_OF(x) _VALUEOF(x) + + #define _UTOP_UCR_UREN_MASK 0x00000001u + #define _UTOP_UCR_UREN_SHIFT 0x00000000u + #define UTOP_UCR_UREN_DEFAULT 0x00000000u + #define UTOP_UCR_UREN_OF(x) _VALUEOF(x) + #define UTOP_UCR_UREN_ENABLE 0x00000001u + #define UTOP_UCR_UREN_DISABLE 0x00000000u + + #define UTOP_UCR_OF(x) _VALUEOF(x) + + #define UTOP_UCR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(UTOP,UCR,BEND)\ + |_PER_FDEFAULT(UTOP,UCR,SLID)\ + |_PER_FDEFAULT(UTOP,UCR,XUDC)\ + |_PER_FDEFAULT(UTOP,UCR,UXEN)\ + |_PER_FDEFAULT(UTOP,UCR,MPHY)\ + |_PER_FDEFAULT(UTOP,UCR,RUDC)\ + |_PER_FDEFAULT(UTOP,UCR,UREN)\ + ) + + #define UTOP_UCR_RMK(bend,slid,xudc,uxen,\ + mphy,rudc,uren) (Uint32)(\ + _PER_FMK(UTOP,UCR,BEND,bend)\ + |_PER_FMK(UTOP,UCR,SLID,slid)\ + |_PER_FMK(UTOP,UCR,XUDC,xudc)\ + |_PER_FMK(UTOP,UCR,UXEN,uxen)\ + |_PER_FMK(UTOP,UCR,MPHY,mphy)\ + |_PER_FMK(UTOP,UCR,RUDC,rudc)\ + |_PER_FMK(UTOP,UCR,UREN,uren)\ + ) + + #define _UTOP_UCR_FGET(FIELD)\ + _PER_FGET(_UTOP_UCR_ADDR,UTOP,UCR,##FIELD) + + #define _UTOP_UCR_FSET(FIELD,field)\ + _PER_FSET(_UTOP_UCR_ADDR,UTOP,UCR,##FIELD,field) + + #define _UTOP_UCR_FSETS(FIELD,SYM)\ + _PER_FSETS(_UTOP_UCR_ADDR,UTOP,UCR,##FIELD,##SYM) + +/******************************************************************************\ +* _____________________ +* | | +* | U I E R | +* |___________________| +* +* UIER - Utopia Interrupt Enable Register +* +* Fields (msb --> lsb): +* (rw) RQIE +* (rw) XQIE +* +\******************************************************************************/ + #define _UTOP_UIER_OFFSET 3 + + #define _UTOP_UIER_ADDR 0x01B4000Cu + + #define _UTOP_UIER_RQIE_MASK 0x00010000u + #define _UTOP_UIER_RQIE_SHIFT 0x00000010u + #define UTOP_UIER_RQIE_DEFAULT 0x00000000u + #define UTOP_UIER_RQIE_OF(x) _VALUEOF(x) + + #define _UTOP_UIER_XQIE_MASK 0x00000001u + #define _UTOP_UIER_XQIE_SHIFT 0x00000000u + #define UTOP_UIER_XQIE_DEFAULT 0x00000000u + #define UTOP_UIER_XQIE_OF(x) _VALUEOF(x) + + #define UTOP_UIER_OF(x) _VALUEOF(x) + + #define UTOP_UIER_DEFAULT (Uint32)(\ + _PER_FDEFAULT(UTOP,UIER,RQIE)\ + |_PER_FDEFAULT(UTOP,UIER,XQIE)\ + ) + + #define UTOP_UIER_RMK(rqie,xqie) (Uint32)(\ + _PER_FMK(UTOP,UIER,RQIE,rqie)\ + |_PER_FMK(UTOP,UIER,XQIE,xqie)\ + ) + + #define _UTOP_UIER_FGET(FIELD)\ + _PER_FGET(_UTOP_UIER_ADDR,UTOP,UIER,##FIELD) + + #define _UTOP_UIER_FSET(FIELD,field)\ + _PER_FSET(_UTOP_UIER_ADDR,UTOP,UIER,##FIELD,field) + + #define _UTOP_UIER_FSETS(FIELD,SYM)\ + _PER_FSETS(_UTOP_UIER_ADDR,UTOP,UIER,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | U I P R | +* |___________________| +* +* UIPR - Utopia Interrupt Pending Register +* +* Fields (msb --> lsb): +* (rw) RQIP +* (rw) XQIP +* +\******************************************************************************/ + #define _UTOP_UIPR_OFFSET 4 + + #define _UTOP_UIPR_ADDR 0x01B40010u + + #define _UTOP_UIPR_RQIP_MASK 0x00010000u + #define _UTOP_UIPR_RQIP_SHIFT 0x00000010u + #define UTOP_UIPR_RQIP_DEFAULT 0x00000000u + #define UTOP_UIPR_RQIP_OF(x) _VALUEOF(x) + #define UTOP_UIPR_RQIP_CLEAR 0x00000001u + + #define _UTOP_UIPR_XQIP_MASK 0x00000001u + #define _UTOP_UIPR_XQIP_SHIFT 0x00000000u + #define UTOP_UIPR_XQIP_DEFAULT 0x00000000u + #define UTOP_UIPR_XQIP_OF(x) _VALUEOF(x) + #define UTOP_UIPR_XQIP_CLEAR 0x00000001u + + #define UTOP_UIPR_OF(x) _VALUEOF(x) + + #define UTOP_UIPR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(UTOP,UIPR,RQIP)\ + |_PER_FDEFAULT(UTOP,UIPR,XQIP)\ + ) + + #define UTOP_UIPR_RMK(rqip,xqip) (Uint32)(\ + _PER_FMK(UTOP,UIPR,RQIP,rqip)\ + |_PER_FMK(UTOP,UIPR,XQIP,xqip)\ + ) + + #define _UTOP_UIPR_FGET(FIELD)\ + _PER_FGET(_UTOP_UIPR_ADDR,UTOP,UIPR,##FIELD) + + #define _UTOP_UIPR_FSET(FIELD,field)\ + _PER_FSET(_UTOP_UIPR_ADDR,UTOP,UIPR,##FIELD,field) + + #define _UTOP_UIPR_FSETS(FIELD,SYM)\ + _PER_FSETS(_UTOP_UIPR_ADDR,UTOP,UIPR,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | C D R | +* |___________________| +* +* CDR - Clock Detect Register +* +* Fields (msb --> lsb): +* (rw) XCCNT +* (rw) RCCNT +* +\******************************************************************************/ + #define _UTOP_CDR_OFFSET 5 + + #define _UTOP_CDR_ADDR 0x01B40014u + + #define _UTOP_CDR_XCCNT_MASK 0x00FF0000u + #define _UTOP_CDR_XCCNT_SHIFT 0x00000010u + #define UTOP_CDR_XCCNT_DEFAULT 0x000000FFu + #define UTOP_CDR_XCCNT_OF(x) _VALUEOF(x) + + #define _UTOP_CDR_RCCNT_MASK 0x000000FFu + #define _UTOP_CDR_RCCNT_SHIFT 0x00000000u + #define UTOP_CDR_RCCNT_DEFAULT 0x000000FFu + #define UTOP_CDR_RCCNT_OF(x) _VALUEOF(x) + + #define UTOP_CDR_OF(x) _VALUEOF(x) + + #define UTOP_CDR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(UTOP,CDR,XCCNT)\ + |_PER_FDEFAULT(UTOP,CDR,RCCNT)\ + ) + + #define UTOP_CDR_RMK(xccnt,rccnt) (Uint32)(\ + _PER_FMK(UTOP,CDR,XCCNT,xccnt)\ + |_PER_FMK(UTOP,CDR,RCCNT,rccnt)\ + ) + + #define _UTOP_CDR_FGET(FIELD)\ + _PER_FGET(_UTOP_CDR_ADDR,UTOP,CDR,##FIELD) + + #define _UTOP_CDR_FSET(FIELD,field)\ + _PER_FSET(_UTOP_CDR_ADDR,UTOP,CDR,##FIELD,field) + + #define _UTOP_CDR_FSETS(FIELD,SYM)\ + _PER_FSETS(_UTOP_CDR_ADDR,UTOP,CDR,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | E I E R | +* |___________________| +* +* EIER - Error Interrupt Enable Register +* +* Fields (msb --> lsb): +* (rw) XCPE +* (rw) XCFE +* (rw) XQSE +* (rw) RCPE +* (rw) RCFE +* (rw) RQSE +* +\******************************************************************************/ + #define _UTOP_EIER_OFFSET 6 + + #define _UTOP_EIER_ADDR 0x01B40018u + + #define _UTOP_EIER_XCPE_MASK 0x00040000u + #define _UTOP_EIER_XCPE_SHIFT 0x00000012u + #define UTOP_EIER_XCPE_DEFAULT 0x00000000u + #define UTOP_EIER_XCPE_OF(x) _VALUEOF(x) + #define UTOP_EIER_XCPE_DISABLE 0x00000000u + #define UTOP_EIER_XCPE_ENABLE 0x00000001u + + #define _UTOP_EIER_XCFE_MASK 0x00020000u + #define _UTOP_EIER_XCFE_SHIFT 0x00000011u + #define UTOP_EIER_XCFE_DEFAULT 0x00000000u + #define UTOP_EIER_XCFE_OF(x) _VALUEOF(x) + #define UTOP_EIER_XCFE_DISABLE 0x00000000u + #define UTOP_EIER_XCFE_ENABLE 0x00000001u + + #define _UTOP_EIER_XQSE_MASK 0x00010000u + #define _UTOP_EIER_XQSE_SHIFT 0x00000010u + #define UTOP_EIER_XQSE_DEFAULT 0x00000000u + #define UTOP_EIER_XQSE_OF(x) _VALUEOF(x) + #define UTOP_EIER_XQSE_DISABLE 0x00000000u + #define UTOP_EIER_XQSE_ENABLE 0x00000001u + + #define _UTOP_EIER_RCPE_MASK 0x00000004u + #define _UTOP_EIER_RCPE_SHIFT 0x00000002u + #define UTOP_EIER_RCPE_DEFAULT 0x00000000u + #define UTOP_EIER_RCPE_OF(x) _VALUEOF(x) + #define UTOP_EIER_RCPE_DISABLE 0x00000000u + #define UTOP_EIER_RCPE_ENABLE 0x00000001u + + #define _UTOP_EIER_RCFE_MASK 0x00000002u + #define _UTOP_EIER_RCFE_SHIFT 0x00000001u + #define UTOP_EIER_RCFE_DEFAULT 0x00000000u + #define UTOP_EIER_RCFE_OF(x) _VALUEOF(x) + #define UTOP_EIER_RCFE_DISABLE 0x00000000u + #define UTOP_EIER_RCFE_ENABLE 0x00000001u + + #define _UTOP_EIER_RQSE_MASK 0x00000001u + #define _UTOP_EIER_RQSE_SHIFT 0x00000000u + #define UTOP_EIER_RQSE_DEFAULT 0x00000000u + #define UTOP_EIER_RQSE_OF(x) _VALUEOF(x) + #define UTOP_EIER_RQSE_DISABLE 0x00000000u + #define UTOP_EIER_RQSE_ENABLE 0x00000001u + + #define UTOP_EIER_OF(x) _VALUEOF(x) + + #define UTOP_EIER_DEFAULT (Uint32)(\ + _PER_FDEFAULT(UTOP,EIER,XCPE)\ + |_PER_FDEFAULT(UTOP,EIER,XCFE)\ + |_PER_FDEFAULT(UTOP,EIER,XQSE)\ + |_PER_FDEFAULT(UTOP,EIER,RCPE)\ + |_PER_FDEFAULT(UTOP,EIER,RCFE)\ + |_PER_FDEFAULT(UTOP,EIER,RQSE)\ + ) + + #define UTOP_EIER_RMK(xcpe,xcfe,xqse,rcpe,rcfe,rqse) (Uint32)(\ + _PER_FMK(UTOP,EIER,XCPE,xcpe)\ + |_PER_FMK(UTOP,EIER,XCFE,xcfe)\ + |_PER_FMK(UTOP,EIER,XQSE,xqse)\ + |_PER_FMK(UTOP,EIER,RCPE,rcpe)\ + |_PER_FMK(UTOP,EIER,RCFE,rcfe)\ + |_PER_FMK(UTOP,EIER,RQSE,rqse)\ + ) + + #define _UTOP_EIER_FGET(FIELD)\ + _PER_FGET(_UTOP_EIER_ADDR,UTOP,EIER,##FIELD) + + #define _UTOP_EIER_FSET(FIELD,field)\ + _PER_FSET(_UTOP_EIER_ADDR,UTOP,EIER,##FIELD,field) + + #define _UTOP_EIER_FSETS(FIELD,SYM)\ + _PER_FSETS(_UTOP_EIER_ADDR,UTOP,EIER,##FIELD,##SYM) + + +/******************************************************************************\ +* _____________________ +* | | +* | E I P R | +* |___________________| +* +* EIPR - Error Interrupt Enable Register +* +* Fields (msb --> lsb): +* (rw) XCPP +* (rw) XCFP +* (r) XQSP +* (rw) RCPP +* (rw) RCFP +* (r) RQSP +* +\******************************************************************************/ + #define _UTOP_EIPR_OFFSET 7 + + #define _UTOP_EIPR_ADDR 0x01B4001Cu + + #define _UTOP_EIPR_XCPP_MASK 0x00040000u + #define _UTOP_EIPR_XCPP_SHIFT 0x00000012u + #define UTOP_EIPR_XCPP_DEFAULT 0x00000000u + #define UTOP_EIPR_XCPP_OF(x) _VALUEOF(x) + #define UTOP_EIPR_XCPP_CLEAR 0x00000001u + + #define _UTOP_EIPR_XCFP_MASK 0x00020000u + #define _UTOP_EIPR_XCFP_SHIFT 0x00000011u + #define UTOP_EIPR_XCFP_DEFAULT 0x00000000u + #define UTOP_EIPR_XCFP_OF(x) _VALUEOF(x) + #define UTOP_EIPR_XCFP_CLEAR 0x00000001u + + #define _UTOP_EIPR_XQSP_MASK 0x00010000u + #define _UTOP_EIPR_XQSP_SHIFT 0x00000010u + #define UTOP_EIPR_XQSP_DEFAULT 0x00000000u + #define UTOP_EIPR_XQSP_OF(x) _VALUEOF(x) + + #define _UTOP_EIPR_RCPP_MASK 0x00000004u + #define _UTOP_EIPR_RCPP_SHIFT 0x00000002u + #define UTOP_EIPR_RCPP_DEFAULT 0x00000000u + #define UTOP_EIPR_RCPP_OF(x) _VALUEOF(x) + #define UTOP_EIPR_RCPP_CLEAR 0x00000001u + + #define _UTOP_EIPR_RCFP_MASK 0x00000002u + #define _UTOP_EIPR_RCFP_SHIFT 0x00000001u + #define UTOP_EIPR_RCFP_DEFAULT 0x00000000u + #define UTOP_EIPR_RCFP_OF(x) _VALUEOF(x) + #define UTOP_EIPR_RCFP_CLEAR 0x00000001u + + #define _UTOP_EIPR_RQSP_MASK 0x00000001u + #define _UTOP_EIPR_RQSP_SHIFT 0x00000000u + #define UTOP_EIPR_RQSP_DEFAULT 0x00000000u + #define UTOP_EIPR_RQSP_OF(x) _VALUEOF(x) + + #define UTOP_EIPR_OF(x) _VALUEOF(x) + + #define UTOP_EIPR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(UTOP,EIPR,XCPP)\ + |_PER_FDEFAULT(UTOP,EIPR,XCFP)\ + |_PER_FDEFAULT(UTOP,EIPR,XQSP)\ + |_PER_FDEFAULT(UTOP,EIPR,RCPP)\ + |_PER_FDEFAULT(UTOP,EIPR,RCFP)\ + |_PER_FDEFAULT(UTOP,EIPR,RQSP)\ + ) + + #define UTOP_EIPR_RMK(xcpp,xcfp,rcpp,rcfp) (Uint32)(\ + _PER_FMK(UTOP,EIPR,XCPP,xcpp)\ + |_PER_FMK(UTOP,EIPR,XCFP,xcfp)\ + |_PER_FMK(UTOP,EIPR,RCPP,rcpp)\ + |_PER_FMK(UTOP,EIPR,RCFP,rcfp)\ + ) + + #define _UTOP_EIPR_FGET(FIELD)\ + _PER_FGET(_UTOP_EIPR_ADDR,UTOP,EIPR,##FIELD) + + #define _UTOP_EIPR_FSET(FIELD,field)\ + _PER_FSET(_UTOP_EIPR_ADDR,UTOP,EIPR,##FIELD,field) + + #define _UTOP_EIPR_FSETS(FIELD,SYM)\ + _PER_FSETS(_UTOP_EIPR_ADDR,UTOP,EIPR,##FIELD,##SYM) + + +/*----------------------------------------------------------------------------*/ + +#endif /* UTOP_SUPPORT */ +#endif /* _CSL_UTOPHAL_H_ */ +/******************************************************************************\ +* End of csl_utophal.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_vcp.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_vcp.h new file mode 100644 index 0000000..383befc --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_vcp.h @@ -0,0 +1,405 @@ +/******************************************************************************\ +* Copyright (C) 2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_vcp.h +* DATE CREATED.. 04/09/2001 +* LAST MODIFIED. 05/30/2001 +* +\******************************************************************************/ +#ifndef _CSL_VCP_H_ +#define _CSL_VCP_H_ + +#include +#include +#include +#include "csl_vcphal.h" + +#if (VCP_SUPPORT) +/****************************************\ +* VCP scope and inline control macros +\****************************************/ +#ifdef __cplusplus +#define CSLAPI extern "C" far +#else +#define CSLAPI extern far +#endif + +#undef USEDEFS +#undef IDECL +#undef IDEF + +#ifdef _VCP_MOD_ + #define IDECL extern far + #define USEDEFS + #define IDEF +#else + #ifdef _INLINE + #define IDECL static inline + #define USEDEFS + #define IDEF static inline + #else + #define IDECL extern far + #endif +#endif + +/****************************************\ +* VCP global macro declarations +\****************************************/ + +/****************************************\ +* VCP global typedef declarations +\****************************************/ +typedef Uint32 VCP_Standard; +typedef Uint32 VCP_Mode; +typedef Uint32 VCP_Map; +typedef Uint32 VCP_Rate; +typedef Uint8 VCP_UserData; +typedef Uint8 VCP_ExtrinsicData; + +typedef struct { + Uint32 ic0; + Uint32 ic1; + Uint32 ic2; + Uint32 ic3; + Uint32 ic4; + Uint32 ic5; +} VCP_ConfigIc; + +typedef struct { + VCP_Rate rate; + Uint8 constLen; + Uint8 poly0; + Uint8 poly1; + Uint8 poly2; + Uint8 poly3; + Uint16 yamTh; + Uint16 frameLen; + Uint16 relLen; + Uint16 convDist; + Uint16 maxSm; + Uint16 minSm; + Uint8 stateNum; + Uint8 bmBuffLen; + Uint8 decBuffLen; + Uint8 traceBack; + Uint8 readFlag; + Uint8 decision; + Uint16 numBranchMetrics; + Uint16 numDecisions; + Uint16 numBmFrames; + Uint16 numDecFrames; +} VCP_Params; +typedef struct { + VCP_Rate rate; + Uint8 constLen; + Uint16 frameLen; + Uint16 yamTh; + Uint8 stateNum; + Uint8 decision; + Uint8 readFlag; +} VCP_BaseParams; + +/****************************************\ +* VCP global ants declarations +\****************************************/ +#define VCP_RATE_1_2 2 +#define VCP_RATE_1_3 3 +#define VCP_RATE_1_4 4 +#define VCP_DECISION_HARD 0 +#define VCP_DECISION_SOFT 1 +#define VCP_TRACEBACK_NONE 0 +#define VCP_TRACEBACK_TAILED 1 +#define VCP_TRACEBACK_CONVERGENT 2 +#define VCP_TRACEBACK_MIXED 3 +#define VCP_END_PACKED32 0 +#define VCP_END_NATIVE 1 +#define VCP_NUM_IC 6 +#define VCP_NUM_OP 2 + +/****************************************\ +* VCP global function declarations +\****************************************/ +/* Set all icx registers : */ +/* Establish all IC register values in the configIc struct based on the */ +/* parameters defined in configParms. */ +CSLAPI void VCP_genIc(VCP_Params *restrict configParms, + VCP_ConfigIc *restrict configIc); + +/* Fill out the necessary TCP parameters. */ +CSLAPI void VCP_genParams(VCP_BaseParams *configBase, + VCP_Params *configParms); + + +/****************************************\ +* VCP inline function declarations +\****************************************/ + +/* Master transfer functions */ +IDECL void VCP_start(); +IDECL void VCP_pause(); +IDECL void VCP_unpause(); +IDECL void VCP_stop(); +IDECL void VCP_reset(); + +IDECL Uint32 VCP_getMinSm(); +IDECL Uint32 VCP_getMaxSm(); +IDECL Uint32 VCP_getYamBit(); +IDECL Uint32 VCP_getIndexState(); + +IDECL Uint32 VCP_statPause(); +IDECL Uint32 VCP_statRun(); +IDECL Uint32 VCP_statError(); +IDECL Uint32 VCP_statWaitIc(); +IDECL Uint32 VCP_statInFifo(); +IDECL Uint32 VCP_statOutFifo(); + +IDECL Uint32 VCP_statSymProc(); +IDECL Uint32 VCP_getNumOutFifo(); +IDECL Uint32 VCP_getNumInFifo(); + +IDECL Uint32 VCP_errTest(); + +IDECL Uint32 VCP_getBmEndian(); +IDECL Uint32 VCP_getSdEndian(); + +IDECL void VCP_setNativeEndian(); +IDECL void VCP_setPacked32Endian(); +IDECL void VCP_setBmEndian(Uint32 bmEnd); +IDECL void VCP_setSdEndian(Uint32 sdEnd); + +IDECL void VCP_icConfig(VCP_ConfigIc *config); +IDECL void VCP_icConfigArgs(Uint32 ic0, Uint32 ic1, Uint32 ic2, Uint32 ic3, + Uint32 ic4, Uint32 ic5); +IDECL void VCP_getIcConfig(VCP_ConfigIc *config); + +/* Ceiling functions */ +IDECL Uint32 VCP_ceil(Uint32 a, Uint32 b); + +IDECL Uint32 VCP_normalCeil(Uint32 a, Uint32 b); + +/****************************************\ +* VCP inline function definitions +\****************************************/ +#ifdef USEDEFS +/*----------------------------------------------------------------------------*/ +IDEF void VCP_start(){ + VCP_FSET(EXE,COMMAND,1) ; +} +/*----------------------------------------------------------------------------*/ +IDEF void VCP_pause(){ + VCP_FSET(EXE,COMMAND,2); +} +/*----------------------------------------------------------------------------*/ +IDEF void VCP_unpause(){ + VCP_FSET(EXE,COMMAND,4); +} +/*----------------------------------------------------------------------------*/ +IDEF void VCP_stop(){ + VCP_FSET(EXE,COMMAND,5) ; +} +/*----------------------------------------------------------------------------*/ +IDEF void VCP_reset(){ + VCP_RSET(IC0,VCP_IC0_DEFAULT); + VCP_RSET(IC1,VCP_IC1_DEFAULT); + VCP_RSET(IC2,VCP_IC2_DEFAULT); + VCP_RSET(IC3,VCP_IC3_DEFAULT); + VCP_RSET(IC4,VCP_IC4_DEFAULT); + VCP_RSET(IC5,VCP_IC5_DEFAULT); + VCP_RSET(EXE,VCP_EXE_DEFAULT); + VCP_RSET(END,VCP_END_DEFAULT); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 VCP_getMinSm(){ + return VCP_FGET(OUT0,FMINS); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 VCP_getMaxSm(){ + return VCP_FGET(OUT0,FMAXS); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 VCP_getYamBit(){ + return VCP_FGET(OUT1,YAM); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 VCP_getIndexState(){ + return VCP_FGET(OUT1,FMAXI); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 VCP_statPause(){ + return VCP_FGET(STAT0,PAUS); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 VCP_statRun(){ + return VCP_FGET(STAT0,RUN); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 VCP_statError(){ + return VCP_FGET(STAT0,ERR); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 VCP_statWaitIc(){ + return VCP_FGET(STAT0,WIC); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 VCP_statInFifo(){ + return VCP_FGET(STAT0,IFEMP); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 VCP_statOutFifo(){ + return VCP_FGET(STAT0,OFFUL); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 VCP_statSymProc(){ + return VCP_FGET(STAT0,NSYM); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 VCP_getNumOutFifo(){ + return VCP_FGET(STAT1,NSYMOF); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 VCP_getNumInFifo(){ + return VCP_FGET(STAT1,NSYMIF); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 VCP_errTest(){ + return VCP_FGET(ERR,ERROR); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 VCP_getBmEndian(){ + return VCP_FGET(END,BM); +} +/*----------------------------------------------------------------------------*/ +IDEF Uint32 VCP_getSdEndian(){ + return VCP_FGET(END,SD); +} +/*----------------------------------------------------------------------------*/ +IDEF void VCP_setNativeEndian(){ + VCP_FSET(END,BM,VCP_END_BM_NATIVE); + VCP_FSET(END,SD,VCP_END_SD_NATIVE); +} +/*----------------------------------------------------------------------------*/ +IDEF void VCP_setPacked32Endian(){ + VCP_FSET(END,BM,VCP_END_BM_32BIT); + VCP_FSET(END,SD,VCP_END_SD_32BIT); +} +/*----------------------------------------------------------------------------*/ +IDEF void VCP_setBmEndian(Uint32 bmEnd){ + VCP_FSET(END,BM,bmEnd); +} +/*----------------------------------------------------------------------------*/ +IDEF void VCP_setSdEndian(Uint32 sdEnd){ + VCP_FSET(END,SD,sdEnd); +} +/*----------------------------------------------------------------------------*/ +IDEF void VCP_icConfig(VCP_ConfigIc *config) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *) _VCP_BASE_IC; + register int x0,x1,x2,x3,x4,x5; + + gie = IRQ_globalDisable(); + + x0 = config->ic0; + x1 = config->ic1; + x2 = config->ic2; + x3 = config->ic3; + x4 = config->ic4; + x5 = config->ic5; + + base[_VCP_IC0_OFFSET] = x0; + base[_VCP_IC1_OFFSET] = x1; + base[_VCP_IC2_OFFSET] = x2; + base[_VCP_IC3_OFFSET] = x3; + base[_VCP_IC4_OFFSET] = x4; + base[_VCP_IC5_OFFSET] = x5; + + IRQ_globalRestore(gie); +} +/*----------------------------------------------------------------------------*/ +IDEF void VCP_icConfigArgs(Uint32 ic0, Uint32 ic1, Uint32 ic2, Uint32 ic3, Uint32 ic4, + Uint32 ic5) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *) _VCP_BASE_IC; + + gie = IRQ_globalDisable(); + + base[_VCP_IC0_OFFSET] = ic0; + base[_VCP_IC1_OFFSET] = ic1; + base[_VCP_IC2_OFFSET] = ic2; + base[_VCP_IC3_OFFSET] = ic3; + base[_VCP_IC4_OFFSET] = ic4; + base[_VCP_IC5_OFFSET] = ic5; + + IRQ_globalRestore(gie); +} +/*----------------------------------------------------------------------------*/ +IDEF void VCP_getIcConfig(VCP_ConfigIc *config) { + + Uint32 gie; + volatile Uint32 *base = (volatile Uint32 *) _VCP_BASE_IC; + register int x0,x1,x2,x3,x4,x5; + + gie = IRQ_globalDisable(); + + x0 = base[_VCP_IC0_OFFSET]; + x1 = base[_VCP_IC1_OFFSET]; + x2 = base[_VCP_IC2_OFFSET]; + x3 = base[_VCP_IC3_OFFSET]; + x4 = base[_VCP_IC4_OFFSET]; + x5 = base[_VCP_IC5_OFFSET]; + + config->ic0 = x0; + config->ic1 = x1; + config->ic2 = x2; + config->ic3 = x3; + config->ic4 = x4; + config->ic5 = x5; + + IRQ_globalRestore(gie); +} + +/*----------------------------------------------------------------------------*/ + +IDEF Uint32 VCP_ceil(Uint32 val, Uint32 pwr2) { + Uint32 gie; + Uint32 x; + + gie = IRQ_globalDisable(); + + /* x^pwr2 = ceil(val, 2^pwr2) */ + /* val is increased (if necessary) to be a multiple of 2^pwr2 */ + x = (((val) - (((val)>>(pwr2)) << (pwr2))) == 0) ? \ + ((val)>>(pwr2)):(((val)>>(pwr2))+1); + + IRQ_globalRestore(gie); + + return(x); +} + +/*----------------------------------------------------------------------------*/ + +IDEF Uint32 VCP_normalCeil(Uint32 val1, Uint32 val2) { + Uint32 gie; + Uint32 x; + + gie = IRQ_globalDisable(); + + /* x = ceil(val1, val2) */ + /* val is increased (if necessary) to be a multiple of val2 */ + x = ( ((val1)%(val2))!=0 )?( ((val1)/(val2)) + 1 ):((val1)/(val2)); + + IRQ_globalRestore(gie); + + return(x); +} +/*----------------------------------------------------------------------------*/ +#endif /* USEDEFS */ + +#endif /* VCP_SUPPORT */ +#endif /* _CSL_VCP_H_ */ +/******************************************************************************\ +* End of csl_vcp.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_vcphal.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_vcphal.h new file mode 100644 index 0000000..56ae677 --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_vcphal.h @@ -0,0 +1,868 @@ +/******************************************************************************\ +* Copyright (C) 1999-2000 Texas Instruments Incorporated. +* All Rights Reserved +*------------------------------------------------------------------------------ +* FILENAME...... csl_vcphal.h +* DATE CREATED.. 02/21/2001 +* LAST MODIFIED. 08/02/2004 - Adding support for C6418 +* 04/17/2003 +*------------------------------------------------------------------------------ +* REGISTERS +* +* IC0 - VCP input configuration register 0 +* IC1 - VCP input configuration register 1 +* IC2 - VCP input configuration register 2 +* IC3 - VCP input configuration register 3 +* IC4 - VCP input configuration register 4 +* IC5 - VCP input configuration register 5 +* EXE - VCP execution register +* END - VCP endian mode register +* OUT0 - VCP output parameters register 0 +* OUT1 - VCP output parameters register 1 +* STAT0 - VCP status register 0 +* STAT1 - VCP status register 1 +* ERR - VCP error register +* +*------------------------------------------------------------------------------ +* MEMORY REGIONS +* +* ICMEM - VCP interrupt configuration register space +* OPMEM - VCP output parameter register space +* BMMEM - VCP systematics and parities memory +* HDMEM - VCP hard decisions memory +* +****************************************************************************** +*Corrections Made 04/17/2003 +*#define VCP_OPMEM_ADDR 0x50000048u VCPOUT0 VCP Output Register 0 //Correction was 0x50000024u +*#define _VCP_IC4_IMINS_MASK 0x0FFF0000u //Correction was 0x00FF0000u +*#define _VCP_IC4_IMAXS_MASK 0x00000FFFu //Correction was 0x000000FFu +*#define VCP_IC5_SDHD_SOFT 0x00000001u //Correction was 0 +*#define VCP_IC5_SDHD_HARD 0x00000000u //Correction was 1 +*#define _VCP_OUT0_ADDR 0x01B80048u //Correction was 0x01B80024u +*#define _VCP_OUT0_FMINS_MASK 0x0FFF0000u //Correction was 0x00FF0000u +*#define _VCP_OUT0_FMAXS_MASK 0x00000FFFu //Correction was 0x00000FFFu +*#define _VCP_ERR_ERROR_MASK 0x00000007u //Correction was 0x00000400u +*#define _VCP_ERR_ERROR_SHIFT 0x00000000u //Correction was 0x0000000Au +*#define _VCP_STAT0_NSYM_MASK 0xFFFF0000u +*#define _VCP_STAT0_NSYM_SHIFT 0x00000010u +*#define _VCP_OUT1_FMAXI_MASK 0x00000FFFu //Correction was 0x00000FFFu +*#define _VCP_OUT1_ADDR 0x01B8004Cu //Correction was 0x01B80028 +\*******************************************************************************/ +#ifndef _CSL_VCPHAL_H_ +#define _CSL_VCPHAL_H_ + +#include +#include + +#if (VCP_SUPPORT) +/******************************************************************************\ +* Memory section +\******************************************************************************/ + + #define _VCP_BASE_IC 0x01B80000u /*VCPIC0 VCP Input Configuration Reg 0 Config bus*/ + #define VCP_ICMEM_ADDR 0x50000000u /*VCPIC0 VCP Input Configuration Reg 0 EDMA bus*/ + #define VCP_OPMEM_ADDR 0x50000048u /*VCPOUT0 VCP Output Register 0 Correction*/ + #define VCP_BMMEM_ADDR 0x50000080u /*VCPWBM VCP Branch Metrics Write Register*/ + #define VCP_HDMEM_ADDR 0x50000088u /*VCPRDECS VCP Decisions Read Register*/ + + +/******************************************************************************\ +* module level register/field access macros +\******************************************************************************/ + + /* ----------------- */ + /* FIELD MAKE MACROS */ + /* ----------------- */ + + #define VCP_FMK(REG,FIELD,x)\ + _PER_FMK(VCP,##REG,##FIELD,x) + + #define VCP_FMKS(REG,FIELD,SYM)\ + _PER_FMKS(VCP,##REG,##FIELD,##SYM) + + + /* -------------------------------- */ + /* RAW REGISTER/FIELD ACCESS MACROS */ + /* -------------------------------- */ + + #define VCP_ADDR(REG)\ + _VCP_##REG##_ADDR + + #define VCP_RGET(REG)\ + _PER_RGET(_VCP_##REG##_ADDR,VCP,##REG) + + #define VCP_RSET(REG,x)\ + _PER_RSET(_VCP_##REG##_ADDR,VCP,##REG,x) + + #define VCP_FGET(REG,FIELD)\ + _VCP_##REG##_FGET(##FIELD) + + #define VCP_FSET(REG,FIELD,x)\ + _VCP_##REG##_FSET(##FIELD,##x) + + #define VCP_FSETS(REG,FIELD,SYM)\ + _VCP_##REG##_FSETS(##FIELD,##SYM) + + + /* ------------------------------------------ */ + /* ADDRESS BASED REGISTER/FIELD ACCESS MACROS */ + /* ------------------------------------------ */ + + #define VCP_RGETA(addr,REG)\ + _PER_RGET(addr,VCP,##REG) + + #define VCP_RSETA(addr,REG,x)\ + _PER_RSET(addr,VCP,##REG,x) + + #define VCP_FGETA(addr,REG,FIELD)\ + _PER_FGET(addr,VCP,##REG,##FIELD) + + #define VCP_FSETA(addr,REG,FIELD,x)\ + _PER_FSET(addr,VCP,##REG,##FIELD,x) + + #define VCP_FSETSA(addr,REG,FIELD,SYM)\ + _PER_FSETS(addr,VCP,##REG,##FIELD,##SYM) + + + /* ----------------------------------------- */ + /* HANDLE BASED REGISTER/FIELD ACCESS MACROS */ + /* ----------------------------------------- */ + + #define VCP_ADDRH(h,REG)\ + (Uint32)(&((h)->baseAddr[_VCP_##REG##_OFFSET])) + + #define VCP_RGETH(h,REG)\ + VCP_RGETA(VCP_ADDRH(h,##REG),##REG) + + + #define VCP_RSETH(h,REG,x)\ + VCP_RSETA(VCP_ADDRH(h,##REG),##REG,x) + + + #define VCP_FGETH(h,REG,FIELD)\ + VCP_FGETA(VCP_ADDRH(h,##REG),##REG,##FIELD) + + + #define VCP_FSETH(h,REG,FIELD,x)\ + VCP_FSETA(VCP_ADDRH(h,##REG),##REG,##FIELD,x) + + + #define VCP_FSETSH(h,REG,FIELD,SYM)\ + VCP_FSETSA(VCP_ADDRH(h,##REG),##REG,##FIELD,##SYM) + + + +/******************************************************************************\ +* _____________________ +* | | +* | I C 0 | +* |___________________| +* +* VCP input configuration register 0 +* +* FIELDS (msb -> lsb) +* (rw) POLY3 +* (rw) POLY2 +* (rw) POLY1 +* (rw) POLY0 +* +\******************************************************************************/ + #define _VCP_IC0_OFFSET 0 + + #define _VCP_IC0_ADDR 0x01B80000u + + #define _VCP_IC0_POLY3_MASK 0xFF000000u + #define _VCP_IC0_POLY3_SHIFT 0x00000018u + #define VCP_IC0_POLY3_DEFAULT 0x00000000u + #define VCP_IC0_POLY3_OF(x) _VALUEOF(x) + + #define _VCP_IC0_POLY2_MASK 0x00FF0000u + #define _VCP_IC0_POLY2_SHIFT 0x00000010u + #define VCP_IC0_POLY2_DEFAULT 0x00000000u + #define VCP_IC0_POLY2_OF(x) _VALUEOF(x) + + #define _VCP_IC0_POLY1_MASK 0x0000FF00u + #define _VCP_IC0_POLY1_SHIFT 0x00000008u + #define VCP_IC0_POLY1_DEFAULT 0x00000000u + #define VCP_IC0_POLY1_OF(x) _VALUEOF(x) + + #define _VCP_IC0_POLY0_MASK 0x000000FFu + #define _VCP_IC0_POLY0_SHIFT 0x00000000u + #define VCP_IC0_POLY0_DEFAULT 0x00000000u + #define VCP_IC0_POLY0_OF(x) _VALUEOF(x) + + #define VCP_IC0_OF(x) _VALUEOF(x) + + #define VCP_IC0_DEFAULT (Uint32)(\ + _PER_FDEFAULT(VCP,IC0,POLY3)\ + |_PER_FDEFAULT(VCP,IC0,POLY2)\ + |_PER_FDEFAULT(VCP,IC0,POLY1)\ + |_PER_FDEFAULT(VCP,IC0,POLY0)\ + ) + + #define VCP_IC0_RMK(poly3,poly2,poly1,poly0) (Uint32)(\ + _PER_FMK(VCP,IC0,POLY3,poly3)\ + |_PER_FMK(VCP,IC0,POLY2,poly2)\ + |_PER_FMK(VCP,IC0,POLY1,poly1)\ + |_PER_FMK(VCP,IC0,POLY0,poly0)\ + ) + + #define _VCP_IC0_FGET(FIELD)\ + _PER_FGET(_VCP_IC0_ADDR,VCP,IC0,##FIELD) + + #define _VCP_IC0_FSET(FIELD,field)\ + _PER_FSET(_VCP_IC0_ADDR,VCP,IC0,##FIELD,field) + + #define _VCP_IC0_FSETS(FIELD,SYM)\ + _PER_FSETS(_VCP_IC0_ADDR,VCP,IC0,FIELD,##SYM) + +/******************************************************************************\ +* _____________________ +* | | +* | I C 1 | +* |___________________| +* +* VCP input configuration register 1 +* +* FIELDS (msb -> lsb) +* (rw) YAMEN +* (rw) YAMT +* (rw) ZERO +* +\******************************************************************************/ + #define _VCP_IC1_OFFSET 1 + + #define _VCP_IC1_ADDR 0x01B80004u + + #define _VCP_IC1_YAMEN_MASK 0x10000000u + #define _VCP_IC1_YAMEN_SHIFT 0x0000001Cu + #define VCP_IC1_YAMEN_DEFAULT 0x00000000u + #define VCP_IC1_YAMEN_OF(x) _VALUEOF(x) + #define VCP_IC1_YAMEN_DISABLE 0x00000000u + #define VCP_IC1_YAMEN_ENABLE 0x00000001u + + #define _VCP_IC1_YAMT_MASK 0x0FFF0000u + #define _VCP_IC1_YAMT_SHIFT 0x00000010u + #define VCP_IC1_YAMT_DEFAULT 0x00000000u + #define VCP_IC1_YAMT_OF(x) _VALUEOF(x) + + #define _VCP_IC1_ZERO_MASK 0x0000FFFFu + #define _VCP_IC1_ZERO_SHIFT 0x00000000u + #define VCP_IC1_ZERO_DEFAULT 0x00000000u + #define VCP_IC1_ZERO_OF(x) _VALUEOF(x) + #define VCP_IC1_ZERO_ZEROS 0x00000000u + + #define VCP_IC1_OF(x) _VALUEOF(x) + + #define VCP_IC1_DEFAULT (Uint32)(\ + _PER_FDEFAULT(VCP,IC1,YAMEN)\ + |_PER_FDEFAULT(VCP,IC1,YAMT)\ + |_PER_FDEFAULT(VCP,IC1,ZERO)\ + ) + + #define VCP_IC1_RMK(yamen,yamt,zero) (Uint32)(\ + _PER_FMK(VCP,IC1,YAMEN,yamen)\ + |_PER_FMK(VCP,IC1,YAMT,yamt)\ + |_PER_FMK(VCP,IC1,ZERO,zero)\ + ) + + #define _VCP_IC1_FGET(FIELD)\ + _PER_FGET(_VCP_IC1_ADDR,VCP,IC1,##FIELD) + + #define _VCP_IC1_FSET(FIELD,field)\ + _PER_FSET(_VCP_IC1_ADDR,VCP,IC1,##FIELD,field) + + #define _VCP_IC1_FSETS(FIELD,SYM)\ + _PER_FSETS(_VCP_IC1_ADDR,VCP,IC1,FIELD,##SYM) + +/******************************************************************************\ +* _____________________ +* | | +* | I C 2 | +* |___________________| +* +* VCP input configuration register 2 +* +* FIELDS (msb -> lsb) +* (rw) R +* (rw) F +* +\******************************************************************************/ + #define _VCP_IC2_OFFSET 2 + + #define _VCP_IC2_ADDR 0x01BA0008u + + #define _VCP_IC2_R_MASK 0xFFFF0000u + #define _VCP_IC2_R_SHIFT 0x00000010u + #define VCP_IC2_R_DEFAULT 0x00000000u + #define VCP_IC2_R_OF(x) _VALUEOF(x) + + #define _VCP_IC2_FL_MASK 0x0000FFFFu + #define _VCP_IC2_FL_SHIFT 0x00000000u + #define VCP_IC2_FL_DEFAULT 0x00000000u + #define VCP_IC2_FL_OF(x) _VALUEOF(x) + + #define VCP_IC2_OF(x) _VALUEOF(x) + + #define VCP_IC2_DEFAULT (Uint32)(\ + _PER_FDEFAULT(VCP,IC2,R)\ + |_PER_FDEFAULT(VCP,IC2,FL)\ + ) + + #define VCP_IC2_RMK(r,fl) (Uint32)(\ + _PER_FMK(VCP,IC2,R,r)\ + |_PER_FMK(VCP,IC2,FL,fl)\ + ) + + #define _VCP_IC2_FGET(FIELD)\ + _PER_FGET(_VCP_IC2_ADDR,VCP,IC2,##FIELD) + + #define _VCP_IC2_FSET(FIELD,field)\ + _PER_FSET(_VCP_IC2_ADDR,VCP,IC2,##FIELD,field) + + #define _VCP_IC2_FSETS(FIELD,SYM)\ + _PER_FSETS(_VCP_IC2_ADDR,VCP,IC2,FIELD,##SYM) + +/******************************************************************************\ +* _____________________ +* | | +* | I C 3 | +* |___________________| +* +* VCP input configuration register 3 +* +* FIELDS (msb -> lsb) +* (rw) C +* +\******************************************************************************/ + #define _VCP_IC3_OFFSET 3 + + #define _VCP_IC3_ADDR 0x01BA000Cu + + #define _VCP_IC3_C_MASK 0x0000FFFFu + #define _VCP_IC3_C_SHIFT 0x00000000u + #define VCP_IC3_C_DEFAULT 0x00000000u + #define VCP_IC3_C_OF(x) _VALUEOF(x) + + #define VCP_IC3_OF(x) _VALUEOF(x) + + #define VCP_IC3_DEFAULT (Uint32)(\ + _PER_FDEFAULT(VCP,IC3,C)\ + ) + + #define VCP_IC3_RMK(c) (Uint32)(\ + _PER_FMK(VCP,IC3,C,c)\ + ) + + #define _VCP_IC3_FGET(FIELD)\ + _PER_FGET(_VCP_IC3_ADDR,VCP,IC3,##FIELD) + + #define _VCP_IC3_FSET(FIELD,field)\ + _PER_FSET(_VCP_IC3_ADDR,VCP,IC3,##FIELD,field) + + #define _VCP_IC3_FSETS(FIELD,SYM)\ + _PER_FSETS(_VCP_IC3_ADDR,VCP,IC3,FIELD,##SYM) + +/******************************************************************************\ +* _____________________ +* | | +* | I C 4 | +* |___________________| +* +* VCP input configuration register 4 +* +* FIELDS (msb -> lsb) +* (rw) IMINS +* (rw) IMAXS +* +\******************************************************************************/ + #define _VCP_IC4_OFFSET 4 + + #define _VCP_IC4_ADDR 0x01BA0010u + + #define _VCP_IC4_IMINS_MASK 0x0FFF0000u /*Correction*/ + #define _VCP_IC4_IMINS_SHIFT 0x00000010u + #define VCP_IC4_IMINS_DEFAULT 0x00000000u + #define VCP_IC4_IMINS_OF(x) _VALUEOF(x) + + #define _VCP_IC4_IMAXS_MASK 0x00000FFFu /*Correction*/ + #define _VCP_IC4_IMAXS_SHIFT 0x00000000u + #define VCP_IC4_IMAXS_DEFAULT 0x00000000u + #define VCP_IC4_IMAXS_OF(x) _VALUEOF(x) + + #define VCP_IC4_OF(x) _VALUEOF(x) + + #define VCP_IC4_DEFAULT (Uint32)(\ + _PER_FDEFAULT(VCP,IC4,IMINS)\ + |_PER_FDEFAULT(VCP,IC4,IMAXS)\ + ) + + #define VCP_IC4_RMK(imins,imaxs) (Uint32)(\ + _PER_FMK(VCP,IC4,IMINS,imins)\ + |_PER_FMK(VCP,IC4,IMAXS,imaxs)\ + ) + + #define _VCP_IC4_FGET(FIELD)\ + _PER_FGET(_VCP_IC4_ADDR,VCP,IC4,##FIELD) + + #define _VCP_IC4_FSET(FIELD,field)\ + _PER_FSET(_VCP_IC4_ADDR,VCP,IC4,##FIELD,field) + + #define _VCP_IC4_FSETS(FIELD,SYM)\ + _PER_FSETS(_VCP_IC4_ADDR,VCP,IC4,FIELD,##SYM) + +/******************************************************************************\ +* _____________________ +* | | +* | I C 5 | +* |___________________| +* +* VCP input configuration register 5 +* +* FIELDS (msb -> lsb) +* (rw) SDHD +* (rw) OUTF +* (rw) TB +* (rw) SYMR +* (rw) SYMX +* (rw) IMAXI +* +\******************************************************************************/ + #define _VCP_IC5_OFFSET 5 + + #define _VCP_IC5_ADDR 0x01BA0014u + + #define _VCP_IC5_SDHD_MASK 0x80000000u + #define _VCP_IC5_SDHD_SHIFT 0x0000001Fu + #define VCP_IC5_SDHD_DEFAULT 0x00000000u + #define VCP_IC5_SDHD_OF(x) _VALUEOF(x) + #define VCP_IC5_SDHD_SOFT 0x00000001u /*Correction was 0*/ + #define VCP_IC5_SDHD_HARD 0x00000000u /*Correction was 1*/ + + #define _VCP_IC5_OUTF_MASK 0x40000000u + #define _VCP_IC5_OUTF_SHIFT 0x0000001Eu + #define VCP_IC5_OUTF_DEFAULT 0x00000000u + #define VCP_IC5_OUTF_OF(x) _VALUEOF(x) + #define VCP_IC5_OUTF_NO 0x00000000u + #define VCP_IC5_OUTF_YES 0x00000001u + + #define _VCP_IC5_TB_MASK 0x03000000u + #define _VCP_IC5_TB_SHIFT 0x00000018u + #define VCP_IC5_TB_DEFAULT 0x00000000u + #define VCP_IC5_TB_OF(x) _VALUEOF(x) + #define VCP_IC5_TB_NO 0x00000000u + #define VCP_IC5_TB_TAIL 0x00000001u + #define VCP_IC5_TB_CONV 0x00000002u + #define VCP_IC5_TB_MIX 0x00000003u + + #define _VCP_IC5_SYMR_MASK 0x00F00000u + #define _VCP_IC5_SYMR_SHIFT 0x00000014u + #define VCP_IC5_SYMR_DEFAULT 0x00000000u + #define VCP_IC5_SYMR_OF(x) _VALUEOF(x) + + #define _VCP_IC5_SYMX_MASK 0x000F0000u + #define _VCP_IC5_SYMX_SHIFT 0x00000010u + #define VCP_IC5_SYMX_DEFAULT 0x00000000u + #define VCP_IC5_SYMX_OF(x) _VALUEOF(x) + + #define _VCP_IC5_IMAXI_MASK 0x000000FFu + #define _VCP_IC5_IMAXI_SHIFT 0x00000000u + #define VCP_IC5_IMAXI_DEFAULT 0x00000000u + #define VCP_IC5_IMAXI_OF(x) _VALUEOF(x) + + #define VCP_IC5_OF(x) _VALUEOF(x) + + #define VCP_IC5_DEFAULT (Uint32)(\ + _PER_FDEFAULT(VCP,IC5,SDHD)\ + |_PER_FDEFAULT(VCP,IC5,OUTF)\ + |_PER_FDEFAULT(VCP,IC5,TB)\ + |_PER_FDEFAULT(VCP,IC5,SYMR)\ + |_PER_FDEFAULT(VCP,IC5,SYMX)\ + |_PER_FDEFAULT(VCP,IC5,IMAXI)\ + |_PER_FDEFAULT(VCP,IC5,IMAXI)\ + ) + + #define VCP_IC5_RMK(sdhd,outf,tb,symr,symx,imaxi) (Uint32)(\ + _PER_FMK(VCP,IC5,SDHD,sdhd)\ + |_PER_FMK(VCP,IC5,OUTF,outf)\ + |_PER_FMK(VCP,IC5,TB,tb)\ + |_PER_FMK(VCP,IC5,SYMR,symr)\ + |_PER_FMK(VCP,IC5,SYMX,symx)\ + |_PER_FMK(VCP,IC5,IMAXI,imaxi)\ + ) + + #define _VCP_IC5_FGET(FIELD)\ + _PER_FGET(_VCP_IC5_ADDR,VCP,IC5,##FIELD) + + #define _VCP_IC5_FSET(FIELD,field)\ + _PER_FSET(_VCP_IC5_ADDR,VCP,IC5,##FIELD,field) + + #define _VCP_IC5_FSETS(FIELD,SYM)\ + _PER_FSETS(_VCP_IC5_ADDR,VCP,IC5,FIELD,##SYM) + +/******************************************************************************\ +* _____________________ +* | | +* | E X E | +* |___________________| +* +* VCP execution register +* +* FIELDS (msb -> lsb) +* (rw) COMMAND +* +\******************************************************************************/ + #define _VCP_EXE_OFFSET 6 + + #define _VCP_EXE_ADDR 0x01B80018u + + #define _VCP_EXE_COMMAND_MASK 0x000000FFu + #define _VCP_EXE_COMMAND_SHIFT 0x00000000u + #define VCP_EXE_COMMAND_DEFAULT 0x00000000u + #define VCP_EXE_COMMAND_OF(x) _VALUEOF(x) + #define VCP_EXE_COMMAND_START 0x00000001u + #define VCP_EXE_COMMAND_PAUSE 0x00000002u + #define VCP_EXE_COMMAND_UNPAUSE 0x00000004u + #define VCP_EXE_COMMAND_STOP 0x00000005u + + #define VCP_EXE_OF(x) _VALUEOF(x) + + #define VCP_EXE_DEFAULT (Uint32)(\ + _PER_FDEFAULT(VCP,EXE,COMMAND)\ + ) + + #define VCP_EXE_RMK(command) (Uint32)(\ + _PER_FMK(VCP,EXE,COMMAND,command)\ + ) + + #define _VCP_EXE_FGET(FIELD)\ + _PER_FGET(_VCP_EXE_ADDR,VCP,EXE,##FIELD) + + #define _VCP_EXE_FSET(FIELD,field)\ + _PER_FSET(_VCP_EXE_ADDR,VCP,EXE,##FIELD,field) + + #define _VCP_EXE_FSETS(FIELD,SYM)\ + _PER_FSETS(_VCP_EXE_ADDR,VCP,EXE,##FIELD,##SYM) + +/******************************************************************************\ +* _____________________ +* | | +* | E N D | +* |___________________| +* +* VCP endian mode register +* +* FIELDS (msb -> lsb) +* (rw) SD +* (rw) BM +* +\******************************************************************************/ + #define _VCP_END_OFFSET 8 + + #define _VCP_END_ADDR 0x01B80020u + + #define _VCP_END_SD_MASK 0x00000002u + #define _VCP_END_SD_SHIFT 0x00000001u + #define VCP_END_SD_DEFAULT 0x00000000u + #define VCP_END_SD_OF(x) _VALUEOF(x) + #define VCP_END_SD_32BIT 0x00000000u + #define VCP_END_SD_NATIVE 0x00000001u + + #define _VCP_END_BM_MASK 0x00000001u + #define _VCP_END_BM_SHIFT 0x00000000u + #define VCP_END_BM_DEFAULT 0x00000000u + #define VCP_END_BM_OF(x) _VALUEOF(x) + #define VCP_END_BM_32BIT 0x00000000u + #define VCP_END_BM_NATIVE 0x00000001u + + + + #define VCP_END_OF(x) _VALUEOF(x) + + #define VCP_END_DEFAULT (Uint32)(\ + _PER_FDEFAULT(VCP,END,SD)\ + |_PER_FDEFAULT(VCP,END,BM)\ + ) + + #define VCP_END_RMK(sd,bm) (Uint32)(\ + _PER_FMK(VCP,END,SD,sd)\ + |_PER_FMK(VCP,END,BM,bm)\ + ) + + #define _VCP_END_FGET(FIELD)\ + _PER_FGET(_VCP_END_ADDR,VCP,END,##FIELD) + + #define _VCP_END_FSET(FIELD,field)\ + _PER_FSET(_VCP_END_ADDR,VCP,END,##FIELD,field) + + #define _VCP_END_FSETS(FIELD,SYM)\ + _PER_FSETS(_VCP_END_ADDR,VCP,END,##FIELD,##SYM) + +/******************************************************************************\ +* _____________________ +* | | +* | O U T 0 | +* |___________________| +* +* VCP output parameters register 0 +* +* FIELDS (msb -> lsb) +* (r) FMINS +* (r) FMAXS +* +\******************************************************************************/ + #define _VCP_OUT0_OFFSET 9 + + #define _VCP_OUT0_ADDR 0x01B80048u /*Correction was 0x01B80024*/ + + #define _VCP_OUT0_FMINS_MASK 0x0FFF0000u /*Correction was 0x00FF0000u*/ + #define _VCP_OUT0_FMINS_SHIFT 0x00000010u + #define VCP_OUT0_FMINS_DEFAULT 0x00000000u + #define VCP_OUT0_FMINS_OF(x) _VALUEOF(x) + + #define _VCP_OUT0_FMAXS_MASK 0x00000FFFu /*Correction was 0x000000FFu*/ + #define _VCP_OUT0_FMAXS_SHIFT 0x00000000u + #define VCP_OUT0_FMAXS_DEFAULT 0x00000000u + #define VCP_OUT0_FMAXS_OF(x) _VALUEOF(x) + + #define VCP_OUT0_OF(x) _VALUEOF(x) + + #define VCP_OUT0_DEFAULT (Uint32)(\ + _PER_FDEFAULT(VCP,OUT0,FMINS)\ + |_PER_FDEFAULT(VCP,OUT0,FMAXS)\ + ) + #if (!(CHIP_6413 | CHIP_6418 | CHIP_6410)) + #define VCP_OUT0_RMK(fmins,fmaxs)(Uint32)(\ + _PER_FMK(VCP,OUT0,FMINS,fmins)\ + |_PER_FMK(VCP,OUT0,FMAXS,fmaxs)\ + ) + #endif + + #define _VCP_OUT0_FGET(FIELD)\ + _PER_FGET(_VCP_OUT0_ADDR,VCP,OUT0,##FIELD) + +/******************************************************************************\ +* _____________________ +* | | +* | O U T 1 | +* |___________________| +* +* VCP output parameters register 1 +* +* FIELDS (msb -> lsb) +* (r) YAM +* (r) FMAXI +* +\******************************************************************************/ + #define _VCP_OUT1_OFFSET 10 + + #define _VCP_OUT1_ADDR 0x01B8004Cu /*Correction was 0x01B80028*/ + + #define _VCP_OUT1_YAM_MASK 0x00010000u + #define _VCP_OUT1_YAM_SHIFT 0x00000010u + #define VCP_OUT1_YAM_DEFAULT 0x00000000u + #define VCP_OUT1_YAM_OF(x) _VALUEOF(x) + #define VCP_OUT1_YAM_NO 0x00000000u + #define VCP_OUT1_YAM_YES 0x00000001u + + #define _VCP_OUT1_FMAXI_MASK 0x00000FFFu /*Correction was 0x00000FFFu*/ + #define _VCP_OUT1_FMAXI_SHIFT 0x00000000u + #define VCP_OUT1_FMAXI_DEFAULT 0x00000000u + #define VCP_OUT1_FMAXI_OF(x) _VALUEOF(x) + + #define VCP_OUT1_OF(x) _VALUEOF(x) + + #define VCP_OUT1_DEFAULT (Uint32)(\ + _PER_FDEFAULT(VCP,OUT1,YAM)\ + |_PER_FDEFAULT(VCP,OUT1,FMAXI)\ + ) +#if (!(CHIP_6413 | CHIP_6418 | CHIP_6410)) + #define VCP_OUT1_RMK(yam,fmaxi) (Uint32)(\ + _PER_FMK(VCP,OUT1,YAM,yam)\ + |_PER_FMK(VCP,OUT1,FMAXI,fmaxi)\ + ) +#endif + #define _VCP_OUT1_FGET(FIELD)\ + _PER_FGET(_VCP_OUT1_ADDR,VCP,OUT1,##FIELD) + +/******************************************************************************\ +* _____________________ +* | | +* | S T A T 0 | +* |___________________| +* +* VCP status register 0 +* +* FIELDS (msb -> lsb) +* (r) NSYM +* (r) OFFUL +* (r) IFEMP +* (r) WIC +* (r) ERR +* (r) RUN +* (r) PAUS +* +\******************************************************************************/ + #define _VCP_STAT0_OFFSET 16 + + #define _VCP_STAT0_ADDR 0x01B80040u + + #define _VCP_STAT0_NSYM_MASK 0xFFFF0000u + #define _VCP_STAT0_NSYM_SHIFT 0x00000010u + #define VCP_STAT0_NSYM_DEFAULT 0x00000000u + #define VCP_STAT0_NSYM_OF(x) _VALUEOF(x) + + #define _VCP_STAT0_OFFUL_MASK 0x00000020u + #define _VCP_STAT0_OFFUL_SHIFT 0x00000005u + #define VCP_STAT0_OFFUL_DEFAULT 0x00000000u + #define VCP_STAT0_OFFUL_OF(x) _VALUEOF(x) + #define VCP_STAT0_OFFUL_NO 0x00000000u + #define VCP_STAT0_OFFUL_YES 0x00000001u + + #define _VCP_STAT0_IFEMP_MASK 0x00000010u + #define _VCP_STAT0_IFEMP_SHIFT 0x00000004u + #define VCP_STAT0_IFEMP_DEFAULT 0x00000000u + #define VCP_STAT0_IFEMP_OF(x) _VALUEOF(x) + #define VCP_STAT0_IFEMP_NO 0x00000000u + #define VCP_STAT0_IFEMP_YES 0x00000001u + + #define _VCP_STAT0_WIC_MASK 0x00000008u + #define _VCP_STAT0_WIC_SHIFT 0x00000003u + #define VCP_STAT0_WIC_DEFAULT 0x00000000u + #define VCP_STAT0_WIC_OF(x) _VALUEOF(x) + #define VCP_STAT0_WIC_NO 0x00000000u + #define VCP_STAT0_WIC_YES 0x00000001u + + #define _VCP_STAT0_ERR_MASK 0x00000004u + #define _VCP_STAT0_ERR_SHIFT 0x00000002u + #define VCP_STAT0_ERR_DEFAULT 0x00000000u + #define VCP_STAT0_ERR_OF(x) _VALUEOF(x) + #define VCP_STAT0_ERR_NO 0x00000000u + #define VCP_STAT0_ERR_YES 0x00000001u + + #define _VCP_STAT0_RUN_MASK 0x00000002u + #define _VCP_STAT0_RUN_SHIFT 0x00000001u + #define VCP_STAT0_RUN_DEFAULT 0x00000000u + #define VCP_STAT0_RUN_OF(x) _VALUEOF(x) + #define VCP_STAT0_RUN_NO 0x00000000u + #define VCP_STAT0_RUN_YES 0x00000001u + + #define _VCP_STAT0_PAUS_MASK 0x00000001u + #define _VCP_STAT0_PAUS_SHIFT 0x00000000u + #define VCP_STAT0_PAUS_DEFAULT 0x00000000u + #define VCP_STAT0_PAUS_OF(x) _VALUEOF(x) + #define VCP_STAT0_PAUS_NO 0x00000000u + #define VCP_STAT0_PAUS_YES 0x00000001u + + #define VCP_STAT0_OF(x) _VALUEOF(x) + + #define VCP_STAT0_DEFAULT (Uint32)(\ + _PER_FDEFAULT(VCP,STAT0,NSYM)\ + |_PER_FDEFAULT(VCP,STAT0,OFFUL)\ + |_PER_FDEFAULT(VCP,STAT0,IFEMP)\ + |_PER_FDEFAULT(VCP,STAT0,WIC)\ + |_PER_FDEFAULT(VCP,STAT0,ERR)\ + |_PER_FDEFAULT(VCP,STAT0,RUN)\ + |_PER_FDEFAULT(VCP,STAT0,PAUS)\ + ) +#if (!(CHIP_6413 | CHIP_6418 | CHIP_6410)) + #define VCP_STAT0_RMK(nsym,offul,ifemp,wic,err,run,paus) (Uint32)(\ + _PER_FMK(VCP,STAT0,NSYM,nsym)\ + |_PER_FMK(VCP,STAT0,OFFUL,offul)\ + |_PER_FMK(VCP,STAT0,IFEMP,ifemp)\ + |_PER_FMK(VCP,STAT0,WIC,wic)\ + |_PER_FMK(VCP,STAT0,ERR,err)\ + |_PER_FMK(VCP,STAT0,RUN,run)\ + |_PER_FMK(VCP,STAT0,PAUS,paus)\ + ) +#endif + #define _VCP_STAT0_FGET(FIELD)\ + _PER_FGET(_VCP_STAT0_ADDR,VCP,STAT0,##FIELD) + +/******************************************************************************\ +* _____________________ +* | | +* | S T A T 1 | +* |___________________| +* +* VCP status register 1 +* +* FIELDS (msb -> lsb) +* (r) NSYMOF +* (r) NSYMIF +* +\******************************************************************************/ + #define _VCP_STAT1_OFFSET 17 + + #define _VCP_STAT1_ADDR 0x01B80044u + + #define _VCP_STAT1_NSYMOF_MASK 0xFFFF0000u + #define _VCP_STAT1_NSYMOF_SHIFT 0x00000010u + #define VCP_STAT1_NSYMOF_DEFAULT 0x00000000u + #define VCP_STAT1_NSYMOF_OF(x) _VALUEOF(x) + + #define _VCP_STAT1_NSYMIF_MASK 0x0000FFFFu + #define _VCP_STAT1_NSYMIF_SHIFT 0x00000000u + #define VCP_STAT1_NSYMIF_DEFAULT 0x00000000u + #define VCP_STAT1_NSYMIF_OF(x) _VALUEOF(x) + + #define VCP_STAT1_OF(x) _VALUEOF(x) + + #define VCP_STAT1_DEFAULT (Uint32)(\ + _PER_FDEFAULT(VCP,STAT1,NSYMOF)\ + |_PER_FDEFAULT(VCP,STAT1,NSYMIF)\ + ) +#if (!(CHIP_6413 | CHIP_6418 | CHIP_6410)) + #define VCP_STAT1_RMK(nsymof,nsymif) (Uint32)(\ + _PER_FMK(VCP,STAT1,NSYMOF,nsymof)\ + |_PER_FMK(VCP,STAT1,NSYMIF,nsymif)\ + ) +#endif + #define _VCP_STAT1_FGET(FIELD)\ + _PER_FGET(_VCP_STAT1_ADDR,VCP,STAT1,##FIELD) + +/******************************************************************************\ +* _____________________ +* | | +* | E R R | +* |___________________| +* +* VCP error register +* +* FIELDS (msb -> lsb) +* (r) ERROR +* +\******************************************************************************/ + #define _VCP_ERR_OFFSET 20 + + #define _VCP_ERR_ADDR 0x01B80050u + + #define _VCP_ERR_ERROR_MASK 0x00000007u /*Correction was 0x00000400u*/ + #define _VCP_ERR_ERROR_SHIFT 0x00000000u /*Correction was 0x0000000Au*/ + #define VCP_ERR_ERROR_DEFAULT 0x00000000u + #define VCP_ERR_ERROR_OF(x) _VALUEOF(x) + #define VCP_ERR_ERROR_NO 0x00000000u + #define VCP_ERR_ERROR_TBNA 0x00000001u + #define VCP_ERR_ERROR_FTL 0x00000002u + #define VCP_ERR_ERROR_FCTL 0x00000003u + + #define VCP_ERR_OF(x) _VALUEOF(x) + + #define VCP_ERR_DEFAULT (Uint32)(\ + _PER_FDEFAULT(VCP,ERR,ERROR)\ + ) +#if (!(CHIP_6413 | CHIP_6418 | CHIP_6410)) + #define VCP_ERR_RMK(error) (Uint32)(\ + _PER_FMK(VCP,ERR,ERROR,error)\ + ) +#endif + #define _VCP_ERR_FGET(FIELD)\ + _PER_FGET(_VCP_ERR_ADDR,VCP,ERR,##FIELD) + +/*----------------------------------------------------------------------------*/ +#endif /* VCP_SUPPORT) */ +#endif /* _CSL_VCPHAL_H_ */ +/******************************************************************************\ +* End of csl_vcphal.h +\******************************************************************************/ + diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_version.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_version.h new file mode 100644 index 0000000..b9c668f --- /dev/null +++ b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_version.h @@ -0,0 +1,82 @@ +/********************************************************* +Adds a version string to an object file that can be +read with the "vers" CCS command-line program. + +The string is placed in a new section named "VERSION", +so that it can easily be moved in memory or discarded. + +usage: + VERSION(id, rev, tag) +where + id is a module variable name prefix + rev is a string, a module revision number + tag is a string, a revision control tag +*********************************************************/ + +#ifndef _VERSION +#define _VERSION + +/* +VERSION(id, rev, tag) + Initialize an int array named _version with a character string + in the following format: + Id: Rev: Tag: Built:

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b/examples/CSL2_DAT_DEMO/docs/readme.txt @@ -0,0 +1,27 @@ +CSL 2.0 DAT Adapter Reference Implementation Using EDMA3 Low Level Driver + ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +Following directories are part of this package:- + +CSL2_DAT_DEMO - Top level directory + - csl2_legacy_include - Legacy headers of CSL 2.0 + - dat_edma3LLD - Reference implementation of the DAT APIs using + the EDMA3 Low level driver package + - demo - Example pjt to run on DM6446 EVM, + that makes calls DAT APIs + - bios_adapter - BIOS specific implementation of critical section entry exit APIs required by EDMA3 LLD as well as + the Dat wrapper + - Interrupt registration and un-registration code + required by the application + - docs - CSL_DAT_Adapter presentation ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +Following environment variables need to be set to correctly build the pjt +EDMA3LLD_INSTALL_DIR Location of EDMA3 Low level driver package + installation + (NOTE:- Ensure EDMA3 low level driver package is + built specifically for DM6446) + ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +Issues:- +1. Due to a DM6446 Simulation bug, this example does not run on the simulator ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ diff --git a/examples/edma3_driver/evmDA830/.ccsproject b/examples/edma3_driver/evmDA830/.ccsproject new file mode 100644 index 0000000..f5e7d02 --- /dev/null +++ b/examples/edma3_driver/evmDA830/.ccsproject @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/examples/edma3_driver/evmDA830/.cdtbuild b/examples/edma3_driver/evmDA830/.cdtbuild new file mode 100644 index 0000000..17e7326 --- /dev/null +++ b/examples/edma3_driver/evmDA830/.cdtbuild @@ -0,0 +1,83 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/examples/edma3_driver/evmDA830/.cdtproject b/examples/edma3_driver/evmDA830/.cdtproject new file mode 100644 index 0000000..e6354c6 --- /dev/null +++ b/examples/edma3_driver/evmDA830/.cdtproject @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/examples/edma3_driver/evmDA830/.project b/examples/edma3_driver/evmDA830/.project new file mode 100644 index 0000000..ca6c257 --- /dev/null +++ b/examples/edma3_driver/evmDA830/.project @@ -0,0 +1,76 @@ + + + edma3_drv_bios6_da830_st_sample + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.rtsc.buildDefinitions.XDC.xdcNature + + + + dma_test.c + 1 + EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_test.c + + + dma_poll_test.c + 1 + EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_poll_test.c + + + ping_pong.cmd + 1 + EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/ping_pong.cmd + + + main.c + 1 + EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/main.c + + + dma_link_test.c + 1 + EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_link_test.c + + + dma_misc_test.c + 1 + EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_misc_test.c + + + qdma_test.c + 1 + EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/qdma_test.c + + + dma_ping_pong_test.c + 1 + EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_ping_pong_test.c + + + qdma_link_test.c + 1 + EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/qdma_link_test.c + + + common.c + 1 + EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/common.c + + + dma_chain_test.c + 1 + EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_chain_test.c + + + diff --git a/examples/edma3_driver/evmDA830/.settings/org.eclipse.cdt.core.prefs b/examples/edma3_driver/evmDA830/.settings/org.eclipse.cdt.core.prefs new file mode 100644 index 0000000..6c8013a --- /dev/null +++ b/examples/edma3_driver/evmDA830/.settings/org.eclipse.cdt.core.prefs @@ -0,0 +1,3 @@ +#Tue Sep 09 12:02:37 IST 2008 +eclipse.preferences.version=1 +indexerId=org.eclipse.cdt.core.domsourceindexer diff --git a/examples/edma3_driver/evmDA830/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/examples/edma3_driver/evmDA830/.settings/org.eclipse.cdt.managedbuilder.core.prefs new file mode 100644 index 0000000..ec1c748 --- /dev/null +++ b/examples/edma3_driver/evmDA830/.settings/org.eclipse.cdt.managedbuilder.core.prefs @@ -0,0 +1,25 @@ +#Mon Oct 06 17:02:48 IST 2008 +com.ti.ccstudio.buildDefinitions.C6000.exe.Release.1065278989/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.C6000.exe.Release.1065278989/internalBuilder/ignoreErr=true +com.ti.ccstudio.buildDefinitions.C6000.exe.Release.1186945729/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.C6000.exe.Release.1186945729/internalBuilder/ignoreErr=true +com.ti.ccstudio.buildDefinitions.C6000.exe.Release.1892307065/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.C6000.exe.Release.1892307065/internalBuilder/ignoreErr=true +com.ti.ccstudio.buildDefinitions.C6000.exe.Release.1975285728/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.C6000.exe.Release.1975285728/internalBuilder/ignoreErr=true +com.ti.ccstudio.buildDefinitions.C6000.exe.Release.610445157/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.C6000.exe.Release.610445157/internalBuilder/ignoreErr=true +com.ti.ccstudio.buildDefinitions.C6000.exe.debug.1203821570/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.C6000.exe.debug.1203821570/internalBuilder/ignoreErr=true +com.ti.ccstudio.buildDefinitions.C6000.exe.debug.1629703996/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.C6000.exe.debug.1629703996/internalBuilder/ignoreErr=true +com.ti.ccstudio.buildDefinitions.C6000.exe.debug.2083982388/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.C6000.exe.debug.2083982388/internalBuilder/ignoreErr=true +com.ti.ccstudio.buildDefinitions.C6000.exe.debug.218764001/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.C6000.exe.debug.218764001/internalBuilder/ignoreErr=true +com.ti.ccstudio.buildDefinitions.C6000.exe.debug.222735589/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.C6000.exe.debug.222735589/internalBuilder/ignoreErr=true +eclipse.preferences.version=1 +environment/project=\r\n\r\n +environment/project/com.ti.ccstudio.buildDefinitions.C6000.exe.Release.610445157=\r\n\r\n +environment/project/com.ti.ccstudio.buildDefinitions.C6000.exe.debug.1203821570=\r\n\r\n diff --git a/examples/edma3_driver/evmDA830/.settings/org.eclipse.ltk.core.refactoring.prefs b/examples/edma3_driver/evmDA830/.settings/org.eclipse.ltk.core.refactoring.prefs new file mode 100644 index 0000000..42d6ada --- /dev/null +++ b/examples/edma3_driver/evmDA830/.settings/org.eclipse.ltk.core.refactoring.prefs @@ -0,0 +1,3 @@ +#Thu Sep 25 14:53:53 IST 2008 +eclipse.preferences.version=1 +org.eclipse.ltk.core.refactoring.enable.project.refactoring.history=false diff --git a/examples/edma3_driver/evmDA830/edma3_drv_bios6_da830_st_sample.cfg b/examples/edma3_driver/evmDA830/edma3_drv_bios6_da830_st_sample.cfg new file mode 100644 index 0000000..10957cf --- /dev/null +++ b/examples/edma3_driver/evmDA830/edma3_drv_bios6_da830_st_sample.cfg @@ -0,0 +1,19 @@ +/*use modules*/ +var Task = xdc.useModule ("ti.sysbios.knl.Task"); +var BIOS = xdc.useModule ("ti.sysbios.BIOS"); +var ECM = xdc.useModule ("ti.sysbios.family.c64p.EventCombiner"); +var Startup = xdc.useModule ("xdc.runtime.Startup"); +var System = xdc.useModule ("xdc.runtime.System"); +var Log = xdc.useModule ("xdc.runtime.Log"); +var Hwi = xdc.useModule('ti.sysbios.hal.Hwi'); +var Semaphore = xdc.useModule('ti.sysbios.ipc.Semaphore'); +var Cache = xdc.useModule('ti.sysbios.hal.Cache'); + +ECM.eventGroupHwiNum[0] = 7; +ECM.eventGroupHwiNum[1] = 8; +ECM.eventGroupHwiNum[2] = 9; +ECM.eventGroupHwiNum[3] = 10; + +/* USE EDMA3 Sample App */ +xdc.loadPackage('ti.sdo.edma3.drv.sample'); + diff --git a/examples/edma3_driver/src/common.c b/examples/edma3_driver/src/common.c new file mode 100644 index 0000000..07d3a74 --- /dev/null +++ b/examples/edma3_driver/src/common.c @@ -0,0 +1,166 @@ +/******************************************************************************* +**+--------------------------------------------------------------------------+** +**| **** |** +**| **** |** +**| ******o*** |** +**| ********_///_**** |** +**| ***** /_//_/ **** |** +**| ** ** (__/ **** |** +**| ********* |** +**| **** |** +**| *** |** +**| |** +**| Copyright (c) 1998-2006 Texas Instruments Incorporated |** +**| ALL RIGHTS RESERVED |** +**| |** +**| Permission is hereby granted to licensees of Texas Instruments |** +**| Incorporated (TI) products to use this computer program for the sole |** +**| purpose of implementing a licensee product based on TI products. |** +**| No other rights to reproduce, use, or disseminate this computer |** +**| program, whether in part or in whole, are granted. |** +**| |** +**| TI makes no representation or warranties with respect to the |** +**| performance of this computer program, and specifically disclaims |** +**| any responsibility for any damages, special or consequential, |** +**| connected with the use of this program. |** +**| |** +**+--------------------------------------------------------------------------+** +*******************************************************************************/ + +/** \file common.c + + \brief Demo sample application for the EDMA3 Driver for BIOS 6. + + (C) Copyright 2006, Texas Instruments, Inc + + \version 1.0 Anuj Aggarwal - Created + + */ + +#include "sample.h" + + +/* Flag variable to check transfer completion on channel 1 */ +volatile short irqRaised1 = 0; +/* Flag variable to check transfer completion on channel 2 */ +volatile short irqRaised2 = 0; + + +/* Cache line aligned source buffer 1. */ +#ifdef EDMA3_ENABLE_DCACHE +/** + * The DATA_ALIGN pragma aligns the symbol to an alignment boundary. The + * alignment boundary is the maximum of the symbolÂ’s default alignment value + * or the value of the constant in bytes. The constant must be a power of 2. + * The syntax of the pragma in C is: + * #pragma DATA_ALIGN (symbol, constant); + */ +#pragma DATA_ALIGN(_srcBuff1, EDMA3_CACHE_LINE_SIZE_IN_BYTES); +#endif /* #ifdef EDMA3_ENABLE_DCACHE */ +signed char _srcBuff1[MAX_BUFFER_SIZE]; + + +/* Cache line aligned destination buffer 1. */ +#ifdef EDMA3_ENABLE_DCACHE +/** + * The DATA_ALIGN pragma aligns the symbol to an alignment boundary. The + * alignment boundary is the maximum of the symbolÂ’s default alignment value + * or the value of the constant in bytes. The constant must be a power of 2. + * The syntax of the pragma in C is: + * #pragma DATA_ALIGN (symbol, constant); + */ +#pragma DATA_ALIGN(_dstBuff1, EDMA3_CACHE_LINE_SIZE_IN_BYTES); +#endif /* #ifdef EDMA3_ENABLE_DCACHE */ +signed char _dstBuff1[MAX_BUFFER_SIZE]; + +signed char *srcBuff1; +signed char *dstBuff1; + + + +/* Cache line aligned source buffer 2. */ +#ifdef EDMA3_ENABLE_DCACHE +/** + * The DATA_ALIGN pragma aligns the symbol to an alignment boundary. The + * alignment boundary is the maximum of the symbolÂ’s default alignment value + * or the value of the constant in bytes. The constant must be a power of 2. + * The syntax of the pragma in C is: + * #pragma DATA_ALIGN (symbol, constant); + */ +#pragma DATA_ALIGN(_srcBuff2, EDMA3_CACHE_LINE_SIZE_IN_BYTES); +#endif /* #ifdef EDMA3_ENABLE_DCACHE */ +signed char _srcBuff2[MAX_BUFFER_SIZE]; + + +#ifdef EDMA3_ENABLE_DCACHE +/* Cache line aligned destination buffer 2. */ +/** + * The DATA_ALIGN pragma aligns the symbol to an alignment boundary. The + * alignment boundary is the maximum of the symbolÂ’s default alignment value + * or the value of the constant in bytes. The constant must be a power of 2. + * The syntax of the pragma in C is: + * #pragma DATA_ALIGN (symbol, constant); + */ +#pragma DATA_ALIGN(_dstBuff2, EDMA3_CACHE_LINE_SIZE_IN_BYTES); +#endif /* #ifdef EDMA3_ENABLE_DCACHE */ +signed char _dstBuff2[MAX_BUFFER_SIZE]; + +signed char *srcBuff2; +signed char *dstBuff2; + + +/* Callback function 1 */ +void callback1 (unsigned int tcc, EDMA3_RM_TccStatus status, + void *appData) + { + (void)tcc; + (void)appData; + + switch (status) + { + case EDMA3_RM_XFER_COMPLETE: + /* Transfer completed successfully */ + irqRaised1 = 1; + break; + case EDMA3_RM_E_CC_DMA_EVT_MISS: + /* Transfer resulted in DMA event miss error. */ + irqRaised1 = -1; + break; + case EDMA3_RM_E_CC_QDMA_EVT_MISS: + /* Transfer resulted in QDMA event miss error. */ + irqRaised1 = -2; + break; + default: + break; + } + } + + + +/* Callback function 2 */ +void callback2 (unsigned int tcc, EDMA3_RM_TccStatus status, + void *appData) + { + (void)tcc; + (void)appData; + + switch (status) + { + case EDMA3_RM_XFER_COMPLETE: + /* Transfer completed successfully */ + irqRaised2 = 1; + break; + case EDMA3_RM_E_CC_DMA_EVT_MISS: + /* Transfer resulted in DMA event miss error. */ + irqRaised2 = -1; + break; + case EDMA3_RM_E_CC_QDMA_EVT_MISS: + /* Transfer resulted in QDMA event miss error. */ + irqRaised2 = -2; + break; + default: + break; + } + } + + diff --git a/examples/edma3_driver/src/dma_chain_test.c b/examples/edma3_driver/src/dma_chain_test.c new file mode 100644 index 0000000..c6e7a5e --- /dev/null +++ b/examples/edma3_driver/src/dma_chain_test.c @@ -0,0 +1,426 @@ +#include "sample.h" + +extern signed char _srcBuff1[MAX_BUFFER_SIZE]; +extern signed char _srcBuff2[MAX_BUFFER_SIZE]; +extern signed char _dstBuff1[MAX_BUFFER_SIZE]; +extern signed char _dstBuff2[MAX_BUFFER_SIZE]; + +extern signed char *srcBuff1; +extern signed char *srcBuff2; +extern signed char *dstBuff1; +extern signed char *dstBuff2; + + +/** + * Test case demonstrating the usgae of DMA channels for transferring + * data between two memory locations. The two DMA channels are chained + * to each other. + */ +/** + * \brief EDMA3 mem-to-mem data copy test case, using two DMA channels, + * chained to each other. + * + * \param acnt [IN] Number of bytes in an array + * \param bcnt [IN] Number of arrays in a frame + * \param ccnt [IN] Number of frames in a block + * \param syncType [IN] Synchronization type (A/AB Sync) + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + */ +EDMA3_DRV_Result edma3_test_with_chaining( + unsigned int acnt, + unsigned int bcnt, + unsigned int ccnt, + EDMA3_DRV_SyncType syncType) + { + EDMA3_DRV_ChainOptions chain = {EDMA3_DRV_TCCHEN_DIS, + EDMA3_DRV_ITCCHEN_DIS, + EDMA3_DRV_TCINTEN_DIS, + EDMA3_DRV_ITCINTEN_DIS}; + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + unsigned int BRCnt = 0; + int srcbidx = 0, desbidx = 0; + int srccidx = 0, descidx = 0; + unsigned int ch1Id = 0; + unsigned int ch2Id = 0; + unsigned int tcc1 = 0; + unsigned int tcc2 = 0; + int i; + unsigned int numenabled = 0; + unsigned int count; + unsigned int Istestpassed1 = 0u; + unsigned int Istestpassed2 = 0u; + + + srcBuff1 = (signed char*) _srcBuff1; + dstBuff1 = (signed char*) _dstBuff1; + srcBuff2 = (signed char*) _srcBuff2; + dstBuff2 = (signed char*) _dstBuff2; + + + /* Initalize source and destination buffers */ + for (count = 0u; count < (acnt*bcnt*ccnt); count++) + { + srcBuff1[count] = (int)count+4; + srcBuff2[count] = (int)count+4; + /** + * No need to initialize the destination buffer as it is being invalidated. + dstBuff1[count] = initval; + dstBuff2[count] = initval; + */ + } + + +#ifdef EDMA3_ENABLE_DCACHE + /* + * Note: These functions are required if the buffer is in DDR. + * For other cases, where buffer is NOT in DDR, user + * may or may not require the below functions. + */ + /* Flush the Source Buffers */ + if (result == EDMA3_DRV_SOK) + { + result = Edma3_CacheFlush((unsigned int)srcBuff1, (acnt*bcnt*ccnt)); + } + if (result == EDMA3_DRV_SOK) + { + result = Edma3_CacheFlush((unsigned int)srcBuff2, (acnt*bcnt*ccnt)); + } + + /* Invalidate the Destination Buffers */ + if (result == EDMA3_DRV_SOK) + { + result = Edma3_CacheInvalidate((unsigned int)dstBuff1, (acnt*bcnt*ccnt)); + } + if (result == EDMA3_DRV_SOK) + { + result = Edma3_CacheInvalidate((unsigned int)dstBuff2, (acnt*bcnt*ccnt)); + } +#endif /* EDMA3_ENABLE_DCACHE */ + + + /* Set B count reload as B count. */ + BRCnt = bcnt; + + /* Setting up the SRC/DES Index */ + srcbidx = (int)acnt; + desbidx = (int)acnt; + + if (syncType == EDMA3_DRV_SYNC_A) + { + /* A Sync Transfer Mode */ + srccidx = (int)acnt; + descidx = (int)acnt; + } + else + { + /* AB Sync Transfer Mode */ + srccidx = ((int)acnt * (int)bcnt); + descidx = ((int)acnt * (int)bcnt); + } + + + /* Transfer complete chaining enable. */ + chain.tcchEn = EDMA3_DRV_TCCHEN_EN; + /* Intermediate transfer complete chaining enable. */ + chain.itcchEn = EDMA3_DRV_ITCCHEN_EN; + /* Transfer complete interrupt is enabled. */ + chain.tcintEn = EDMA3_DRV_TCINTEN_EN; + /* Intermediate transfer complete interrupt is disabled. */ + chain.itcintEn = EDMA3_DRV_ITCINTEN_DIS; + + + /* Setup for Channel 1*/ + tcc1 = EDMA3_DRV_TCC_ANY; + ch1Id = EDMA3_DRV_DMA_CHANNEL_ANY; + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_requestChannel (hEdma, &ch1Id, &tcc1, + (EDMA3_RM_EventQueue)0, + &callback1, NULL); + } + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setSrcParams (hEdma, ch1Id, + (unsigned int)(srcBuff1), + EDMA3_DRV_ADDR_MODE_INCR, + EDMA3_DRV_W8BIT); + } + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setDestParams (hEdma, ch1Id, + (unsigned int)(dstBuff1), + EDMA3_DRV_ADDR_MODE_INCR, + EDMA3_DRV_W8BIT); + } + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setSrcIndex (hEdma, ch1Id, srcbidx, srccidx); + } + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setDestIndex (hEdma, ch1Id, desbidx, descidx); + } + + if (result == EDMA3_DRV_SOK) + { + if (syncType == EDMA3_DRV_SYNC_A) + { + result = EDMA3_DRV_setTransferParams (hEdma, ch1Id, acnt, bcnt, + ccnt,BRCnt, + EDMA3_DRV_SYNC_A); + } + else + { + /* AB Sync Transfer Mode */ + result = EDMA3_DRV_setTransferParams (hEdma, ch1Id, acnt, bcnt, + ccnt, BRCnt, + EDMA3_DRV_SYNC_AB); + } + } + + + if (result == EDMA3_DRV_SOK) + { + /* Setup for Channel 2 */ + tcc2 = EDMA3_DRV_TCC_ANY; + ch2Id = EDMA3_DRV_DMA_CHANNEL_ANY; + + result = EDMA3_DRV_requestChannel (hEdma, &ch2Id, &tcc2, + (EDMA3_RM_EventQueue)0, + &callback2, NULL); + } + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setSrcParams (hEdma, ch2Id, (unsigned int)(srcBuff2), + EDMA3_DRV_ADDR_MODE_INCR, + EDMA3_DRV_W8BIT); + } + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setDestParams (hEdma, ch2Id, + (unsigned int)(dstBuff2), + EDMA3_DRV_ADDR_MODE_INCR, + EDMA3_DRV_W8BIT); + } + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setSrcIndex (hEdma, ch2Id, srcbidx, srccidx); + } + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setDestIndex (hEdma, ch2Id, desbidx, descidx); + } + + if (result == EDMA3_DRV_SOK) + { + if (syncType == EDMA3_DRV_SYNC_A) + { + result = EDMA3_DRV_setTransferParams (hEdma, ch2Id, acnt, bcnt, + ccnt, BRCnt, + EDMA3_DRV_SYNC_A); + } + else + { + /* AB Sync Transfer Mode */ + result = EDMA3_DRV_setTransferParams (hEdma, ch2Id, acnt, bcnt, + ccnt, BRCnt, + EDMA3_DRV_SYNC_AB); + } + } + + + if (result == EDMA3_DRV_SOK) + { + /** + * Enable the Transfer Completion Interrupt on the Chained Channel + * (Ch 2). + */ + result = EDMA3_DRV_setOptField (hEdma, ch2Id, + EDMA3_DRV_OPT_FIELD_TCINTEN, 1u); + } + + if (result == EDMA3_DRV_SOK) + { + /** + * Enable the Intermediate Transfer Completion Interrupt on the + * Chained Channel (Ch 2). + */ + result = EDMA3_DRV_setOptField (hEdma, ch2Id, + EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u); + } + + + if (result == EDMA3_DRV_SOK) + { + /* Now chain the two channels together. */ + result = EDMA3_DRV_chainChannel(hEdma, ch1Id, ch2Id, + (EDMA3_DRV_ChainOptions *)&chain); + } + + + /*Need to activate next param*/ + if (syncType == EDMA3_DRV_SYNC_A) + { + numenabled = bcnt * ccnt; + } + else + { + /* AB Sync Transfer Mode */ + numenabled = ccnt; + } + + + if (result == EDMA3_DRV_SOK) + { + for (i = 0; i < numenabled; i++) + { + irqRaised2 = 0; + + /* + * Now enable the transfer for Master channel as many times + * as calculated above. + */ + result = EDMA3_DRV_enableTransfer (hEdma, ch1Id, + EDMA3_DRV_TRIG_MODE_MANUAL); + if (result != EDMA3_DRV_SOK) + { + #ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF ("error from edma3_test_with_chaining\n\r\n"); + #endif /* EDMA3_DRV_DEBUG */ + break; + } + + + /** + * Transfer on the master channel (ch1Id) will finish after some + * time. + * Now, because of the enabling of intermediate chaining on channel + * 1, after the transfer gets over, a sync event will be sent + * to channel 2, which will trigger the transfer on it. + * Also, Final and Intermediate Transfer Complete + * Interrupts are enabled on channel 2, so we should wait for the + * completion ISR on channel 2 first, before proceeding + * ahead. + */ + while (irqRaised2 == 0) + { + /* Wait for the Completion ISR on channel 2. */ + Task_sleep(1u); + } + + /* Check the status of the completed transfer */ + if (irqRaised2 < 0) + { + /* Some error occured, break from the FOR loop. */ +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF ("\r\nedma3_test_with_chaining: Event Miss Occured!!!\r\n"); +#endif /* EDMA3_DRV_DEBUG */ + + /* Clear the error bits first */ + result = EDMA3_DRV_clearErrorBits (hEdma, ch1Id); + + break; + } + } + } + + + if (result == EDMA3_DRV_SOK) + { + /* Match the Source and Destination Buffers. */ + if (result == EDMA3_DRV_SOK) + { + for (i = 0; i < (acnt*bcnt*ccnt); i++) + { + if (srcBuff1[i] != dstBuff1[i]) + { + Istestpassed1 = 0; + + #ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("edma3_test_with_chaining: Data write-read " \ + "matching FAILED at i = %d " \ + "(srcBuff1 -> dstBuff1)\r\n", i); + #endif /* EDMA3_DRV_DEBUG */ + break; + } + } + if (i == (acnt*bcnt*ccnt)) + { + Istestpassed1 = 1u; + } + + + for (i = 0; i < (acnt*bcnt*ccnt); i++) + { + if (srcBuff2[i] != dstBuff2[i]) + { + Istestpassed2 = 0; + + #ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("edma3_test_with_chaining: Data write-read " \ + "matching FAILED at i = %d " \ + "(srcBuff2 -> dstBuff2)\r\n", i); + #endif /* EDMA3_DRV_DEBUG */ + break; + } + } + if (i == (acnt*bcnt*ccnt)) + { + Istestpassed2 = 1u; + } + } + + + if (result == EDMA3_DRV_SOK) + { + /* Free the previously allocated channels. */ + result = EDMA3_DRV_freeChannel (hEdma, ch1Id); + if (result != EDMA3_DRV_SOK) + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("edma3_test_with_chaining: EDMA3_DRV_freeChannel() for ch 1 FAILED, error code: %d\r\n", result); +#endif /* EDMA3_DRV_DEBUG */ + } + else + { + result = EDMA3_DRV_freeChannel (hEdma, ch2Id); + if (result != EDMA3_DRV_SOK) + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("edma3_test_with_chaining: EDMA3_DRV_freeChannel() for ch 2 FAILED, error code: %d\r\n", result); +#endif /* EDMA3_DRV_DEBUG */ + } + } + } + } + + + if((Istestpassed1 == 1u) && (Istestpassed2 == 1u)) + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("edma3_test_with_chaining PASSED\r\n"); +#endif /* EDMA3_DRV_DEBUG */ + } + else + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("edma3_test_with_chaining FAILED\r\n"); +#endif /* EDMA3_DRV_DEBUG */ + result = ((EDMA3_DRV_SOK == result) ? + EDMA3_DATA_MISMATCH_ERROR : result); + } + + + return result; + } + diff --git a/examples/edma3_driver/src/dma_link_test.c b/examples/edma3_driver/src/dma_link_test.c new file mode 100644 index 0000000..40ba15e --- /dev/null +++ b/examples/edma3_driver/src/dma_link_test.c @@ -0,0 +1,587 @@ +#include "sample.h" + +extern signed char _srcBuff1[MAX_BUFFER_SIZE]; +extern signed char _srcBuff2[MAX_BUFFER_SIZE]; +extern signed char _dstBuff1[MAX_BUFFER_SIZE]; +extern signed char _dstBuff2[MAX_BUFFER_SIZE]; + +extern signed char *srcBuff1; +extern signed char *srcBuff2; +extern signed char *dstBuff1; +extern signed char *dstBuff2; + + +/** + * \brief EDMA3 mem-to-mem data copy test case, using two DMA + * channels, linked to each other. + * + * \param acnt [IN] Number of bytes in an array + * \param bcnt [IN] Number of arrays in a frame + * \param ccnt [IN] Number of frames in a block + * \param syncType [IN] Synchronization type (A/AB Sync) + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + */ +EDMA3_DRV_Result edma3_test_with_link( + unsigned int acnt, + unsigned int bcnt, + unsigned int ccnt, + EDMA3_DRV_SyncType syncType) + { + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + EDMA3_DRV_PaRAMRegs paramSet = {0,0,0,0,0,0,0,0,0,0,0,0}; + unsigned int ch1Id = 0; + unsigned int ch2Id = 0; + unsigned int tcc1 = 0; + unsigned int tcc2 = 0; + int i; + unsigned int count; + unsigned int Istestpassed1 = 0u; + unsigned int Istestpassed2 = 0u; + unsigned int numenabled = 0; + unsigned int BRCnt = 0; + int srcbidx = 0, desbidx = 0; + int srccidx = 0, descidx = 0; + + + srcBuff1 = (signed char*) _srcBuff1; + dstBuff1 = (signed char*) _dstBuff1; + srcBuff2 = (signed char*) _srcBuff2; + dstBuff2 = (signed char*) _dstBuff2; + + + /* Initalize source and destination buffers */ + for (count = 0u; count < (acnt*bcnt*ccnt); count++) + { + srcBuff1[count] = (int)count+1; + srcBuff2[count] = (int)count+1; + /** + * No need to initialize the destination buffer as it is being invalidated. + dstBuff1[count] = initval; + dstBuff2[count] = initval; + */ + } + + +#ifdef EDMA3_ENABLE_DCACHE + /* + * Note: These functions are required if the buffer is in DDR. + * For other cases, where buffer is NOT in DDR, user + * may or may not require the below functions. + */ + /* Flush the Source Buffers */ + if (result == EDMA3_DRV_SOK) + { + result = Edma3_CacheFlush((unsigned int)srcBuff1, (acnt*bcnt*ccnt)); + } + if (result == EDMA3_DRV_SOK) + { + result = Edma3_CacheFlush((unsigned int)srcBuff2, (acnt*bcnt*ccnt)); + } + + /* Invalidate the Destination Buffers */ + if (result == EDMA3_DRV_SOK) + { + result = Edma3_CacheInvalidate((unsigned int)dstBuff1, (acnt*bcnt*ccnt)); + } + if (result == EDMA3_DRV_SOK) + { + result = Edma3_CacheInvalidate((unsigned int)dstBuff2, (acnt*bcnt*ccnt)); + } +#endif /* EDMA3_ENABLE_DCACHE */ + + + irqRaised1 = 0; + irqRaised2 = 0; + + /* Set B count reload as B count. */ + BRCnt = bcnt; + + /* Setting up the SRC/DES Index */ + srcbidx = (int)acnt; + desbidx = (int)acnt; + if (syncType == EDMA3_DRV_SYNC_A) + { + /* A Sync Transfer Mode */ + srccidx = (int)acnt; + descidx = (int)acnt; + } + else + { + /* AB Sync Transfer Mode */ + srccidx = ((int)acnt * (int)bcnt); + descidx = ((int)acnt * (int)bcnt); + } + + + /* Setup for Channel 1*/ + tcc1 = EDMA3_DRV_TCC_ANY; + ch1Id = EDMA3_DRV_DMA_CHANNEL_ANY; + + /* Request any DMA channel and any TCC */ + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_requestChannel (hEdma, &ch1Id, &tcc1, + (EDMA3_RM_EventQueue)0, + &callback1, NULL); + } + + if (result == EDMA3_DRV_SOK) + { + /* Fill the PaRAM Set with transfer specific information */ + paramSet.srcAddr = (unsigned int)(srcBuff1); + paramSet.destAddr = (unsigned int)(dstBuff1); + + /** + * Be Careful !!! + * Valid values for SRCBIDX/DSTBIDX are between –32768 and 32767 + * Valid values for SRCCIDX/DSTCIDX are between –32768 and 32767 + */ + paramSet.srcBIdx = srcbidx; + paramSet.destBIdx = desbidx; + paramSet.srcCIdx = srccidx; + paramSet.destCIdx = descidx; + + /** + * Be Careful !!! + * Valid values for ACNT/BCNT/CCNT are between 0 and 65535. + * ACNT/BCNT/CCNT must be greater than or equal to 1. + * Maximum number of bytes in an array (ACNT) is 65535 bytes + * Maximum number of arrays in a frame (BCNT) is 65535 + * Maximum number of frames in a block (CCNT) is 65535 + */ + paramSet.aCnt = acnt; + paramSet.bCnt = bcnt; + paramSet.cCnt = ccnt; + + /* For AB-synchronized transfers, BCNTRLD is not used. */ + paramSet.bCntReload = BRCnt; + + paramSet.linkAddr = 0xFFFFu; + + /* Src & Dest are in INCR modes */ + paramSet.opt &= 0xFFFFFFFCu; + /* Program the TCC */ + paramSet.opt |= ((tcc1 << OPT_TCC_SHIFT) & OPT_TCC_MASK); + + /* Enable Intermediate & Final transfer completion interrupt */ + paramSet.opt |= (1 << OPT_ITCINTEN_SHIFT); + paramSet.opt |= (1 << OPT_TCINTEN_SHIFT); + + if (syncType == EDMA3_DRV_SYNC_A) + { + paramSet.opt &= 0xFFFFFFFBu; + } + else + { + /* AB Sync Transfer Mode */ + paramSet.opt |= (1 << OPT_SYNCDIM_SHIFT); + } + + /* Now, write the PaRAM Set. */ + result = EDMA3_DRV_setPaRAM (hEdma, ch1Id, ¶mSet); + } + + + /* + * There is another way to program the PaRAM Set using specific APIs + * for different PaRAM set entries. It gives user more control and easier + * to use interface. User can use any of the methods. + * Below is the alternative way to program the PaRAM Set. + */ + + /* + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setSrcParams (hEdma, ch1Id, (unsigned int)(srcBuff1), + EDMA3_DRV_ADDR_MODE_INCR, + EDMA3_DRV_W8BIT); + } + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setDestParams (hEdma, ch1Id, + (unsigned int)(dstBuff1), + EDMA3_DRV_ADDR_MODE_INCR, + EDMA3_DRV_W8BIT); + } + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setSrcIndex (hEdma, ch1Id, srcbidx, srccidx); + } + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setDestIndex (hEdma, ch1Id, desbidx, descidx); + } + + if (result == EDMA3_DRV_SOK) + { + if (syncType == EDMA3_DRV_SYNC_A) + { + result = EDMA3_DRV_setTransferParams (hEdma, ch1Id, acnt, bcnt, + ccnt, BRCnt, + EDMA3_DRV_SYNC_A); + } + else + { + result = EDMA3_DRV_setTransferParams (hEdma, ch1Id, acnt, bcnt, + ccnt, BRCnt, + EDMA3_DRV_SYNC_AB); + } + } + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setOptField (hEdma, ch1Id, + EDMA3_DRV_OPT_FIELD_TCINTEN, 1u); + } + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setOptField (hEdma, ch1Id, + EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u); + } + + */ + + + /* Request any LINK channel and any TCC */ + if (result == EDMA3_DRV_SOK) + { + /* Setup for Channel 2 */ + ch2Id = EDMA3_DRV_LINK_CHANNEL; + tcc2 = EDMA3_DRV_TCC_ANY; + + result = EDMA3_DRV_requestChannel (hEdma, &ch2Id, &tcc2, + (EDMA3_RM_EventQueue)0, + &callback1, NULL); + } + + if (result == EDMA3_DRV_SOK) + { + /* + * Fill the PaRAM Set for the LINK channel + * with transfer specific information. + */ + paramSet.srcAddr = (unsigned int)(srcBuff2); + paramSet.destAddr = (unsigned int)(dstBuff2); + + /** + * Be Careful !!! + * Valid values for SRCBIDX/DSTBIDX are between –32768 and 32767 + * Valid values for SRCCIDX/DSTCIDX are between –32768 and 32767 + */ + paramSet.srcBIdx = srcbidx; + paramSet.destBIdx = desbidx; + paramSet.srcCIdx = srccidx; + paramSet.destCIdx = descidx; + + /** + * Be Careful !!! + * Valid values for ACNT/BCNT/CCNT are between 0 and 65535. + * ACNT/BCNT/CCNT must be greater than or equal to 1. + * Maximum number of bytes in an array (ACNT) is 65535 bytes + * Maximum number of arrays in a frame (BCNT) is 65535 + * Maximum number of frames in a block (CCNT) is 65535 + */ + paramSet.aCnt = acnt; + paramSet.bCnt = bcnt; + paramSet.cCnt = ccnt; + + /* For AB-synchronized transfers, BCNTRLD is not used. */ + paramSet.bCntReload = BRCnt; + + paramSet.linkAddr = 0xFFFFu; + + /* Reset opt field first */ + paramSet.opt = 0x0u; + /* Src & Dest are in INCR modes */ + paramSet.opt &= 0xFFFFFFFCu; + + /* Enable Intermediate & Final transfer completion interrupt */ + paramSet.opt |= (1 << OPT_ITCINTEN_SHIFT); + paramSet.opt |= (1 << OPT_TCINTEN_SHIFT); + + if (syncType == EDMA3_DRV_SYNC_A) + { + paramSet.opt &= 0xFFFFFFFBu; + } + else + { + /* AB Sync Transfer Mode */ + paramSet.opt |= (1 << OPT_SYNCDIM_SHIFT); + } + + /* Now, write the PaRAM Set. */ + result = EDMA3_DRV_setPaRAM(hEdma, ch2Id, ¶mSet); + } + + + /* + * There is another way to program the PaRAM Set using specific APIs + * for different PaRAM set entries. It gives user more control and easier + * to use interface. User can use any of the methods. + * Below is the alternative way to program the PaRAM Set. + */ + + /* + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setSrcParams (hEdma, ch2Id, (unsigned int)(srcBuff2), + EDMA3_DRV_ADDR_MODE_INCR, + EDMA3_DRV_W8BIT); + } + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setDestParams (hEdma, ch2Id, + (unsigned int)(dstBuff2), + EDMA3_DRV_ADDR_MODE_INCR, + EDMA3_DRV_W8BIT); + } + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setSrcIndex (hEdma, ch2Id, srcbidx, srccidx); + } + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setDestIndex (hEdma, ch2Id, desbidx, descidx); + } + + if (result == EDMA3_DRV_SOK) + { + if (syncType == EDMA3_DRV_SYNC_A) + { + result = EDMA3_DRV_setTransferParams (hEdma, ch2Id, acnt, bcnt, + ccnt, + BRCnt,EDMA3_DRV_SYNC_A); + } + else + { + result = EDMA3_DRV_setTransferParams (hEdma, ch2Id, acnt, bcnt, + ccnt, + BRCnt,EDMA3_DRV_SYNC_AB); + } + } + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setOptField (hEdma, ch2Id, + EDMA3_DRV_OPT_FIELD_TCINTEN, 1u); + } + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setOptField (hEdma, ch2Id, + EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u); + } + + */ + + + /* Link both the channels. */ + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_linkChannel (hEdma, ch1Id, ch2Id); + } + + + /* + * Since the transfer is going to happen in Manual mode of EDMA3 + * operation, we have to 'Enable the Transfer' multiple times. + * Number of times depends upon the Mode (A/AB Sync) + * and the different counts. + */ + if (result == EDMA3_DRV_SOK) + { + /*Need to activate next param*/ + if (syncType == EDMA3_DRV_SYNC_A) + { + numenabled = bcnt * ccnt; + } + else + { + /* AB Sync Transfer Mode */ + numenabled = ccnt; + } + + for (i = 0; i < numenabled; i++) + { + irqRaised1 = 0; + + /* + * Now enable the transfer for Master channel as many times + * as calculated above. + */ + result = EDMA3_DRV_enableTransfer (hEdma, ch1Id, + EDMA3_DRV_TRIG_MODE_MANUAL); + if (result != EDMA3_DRV_SOK) + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF ("error from edma3_test_with_link\n\r\n"); +#endif /* EDMA3_DRV_DEBUG */ + break; + } + + while (irqRaised1 == 0) + { + /* Wait for the Completion ISR on Master Channel. */ + Task_sleep(1u); + } + + /* Check the status of the completed transfer */ + if (irqRaised1 < 0) + { + /* Some error occured, break from the FOR loop. */ +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF ("\r\nedma3_test_with_link: Event Miss Occured!!!\r\n"); +#endif /* EDMA3_DRV_DEBUG */ + + /* Clear the error bits first */ + result = EDMA3_DRV_clearErrorBits (hEdma, ch1Id); + + break; + } + } + } + + + /** + * Now the transfer on Master channel is finished. + * Trigger next (LINK) param. + */ + if (EDMA3_DRV_SOK == result) + { + for (i = 0; i < numenabled; i++) + { + irqRaised1 = 0; + + /* + * Enable the transfer for LINK channel as many times + * as calculated above. + */ + result = EDMA3_DRV_enableTransfer (hEdma, ch1Id, + EDMA3_DRV_TRIG_MODE_MANUAL); + if (result != EDMA3_DRV_SOK) + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF ("error from edma3_test_with_link\n\r\n"); +#endif /* EDMA3_DRV_DEBUG */ + break; + } + + while (irqRaised1 == 0) + { + /* Wait for the Completion ISR on the Link Channel. */ + Task_sleep(1u); + } + + /* Check the status of the completed transfer */ + if (irqRaised1 < 0) + { + /* Some error occured, break from the FOR loop. */ +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF ("\r\nedma3_test_with_link: Event Miss Occured!!!\r\n"); +#endif /* EDMA3_DRV_DEBUG */ + + /* Clear the error bits first */ + result = EDMA3_DRV_clearErrorBits (hEdma, ch2Id); + + break; + } + } + } + + + + /* Match the Source and Destination Buffers. */ + if (EDMA3_DRV_SOK == result) + { + for (i = 0; i < (acnt*bcnt*ccnt); i++) + { + if (srcBuff1[i] != dstBuff1[i]) + { + Istestpassed1 = 0u; +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("edma3_test_with_link: Data write-read " \ + "matching FAILED at i = %d " \ + "(srcBuff1 -> dstBuff1)\r\n", i); +#endif /* EDMA3_DRV_DEBUG */ + break; + } + } + if (i == (acnt*bcnt*ccnt)) + { + Istestpassed1 = 1u; + } + + + for (i = 0; i < (acnt*bcnt*ccnt); i++) + { + if (srcBuff2[i] != dstBuff2[i]) + { + Istestpassed2 = 0; +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("edma3_test_with_link: Data write-read " \ + "matching FAILED at i = %d " \ + "(srcBuff2 -> dstBuff2)\r\n", i); +#endif /* EDMA3_DRV_DEBUG */ + break; + } + } + if (i == (acnt*bcnt*ccnt)) + { + Istestpassed2 = 1u; + } + + + /* Free the previously allocated channels. */ + result = EDMA3_DRV_freeChannel (hEdma, ch1Id); + if (result != EDMA3_DRV_SOK) + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("edma3_test_with_link: EDMA3_DRV_freeChannel() " \ + "for ch1 FAILED, error code: %d\r\n", result); +#endif /* EDMA3_DRV_DEBUG */ + } + else + { + result = EDMA3_DRV_freeChannel (hEdma, ch2Id); + if (result != EDMA3_DRV_SOK) + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("edma3_test_with_link: " \ + "EDMA3_DRV_freeChannel() for ch 2 FAILED, " \ + "error code: %d\r\n", result); +#endif /* EDMA3_DRV_DEBUG */ + } + } + } + + + if((Istestpassed1 == 1u) && (Istestpassed2 == 1u)) + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("edma3_test_with_link PASSED\r\n"); +#endif /* EDMA3_DRV_DEBUG */ + } + else + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("edma3_test_with_link FAILED\r\n"); +#endif /* EDMA3_DRV_DEBUG */ + result = ((EDMA3_DRV_SOK == result) ? + EDMA3_DATA_MISMATCH_ERROR : result); + } + + + return result; +} + + diff --git a/examples/edma3_driver/src/dma_misc_test.c b/examples/edma3_driver/src/dma_misc_test.c new file mode 100644 index 0000000..4c3159f --- /dev/null +++ b/examples/edma3_driver/src/dma_misc_test.c @@ -0,0 +1,231 @@ +#include "sample.h" + +/** + * \brief EDMA3 misc test cases. + * This test case will read/write to some CC registers. + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + */ +EDMA3_DRV_Result edma3_misc_test() + { + EDMA3_DRV_Result drvResult = EDMA3_DRV_SOK; + unsigned int ccRegOffset = 0u; + unsigned int ccRegVal = 0u; + unsigned int newRegVal = 0u; + unsigned int origRegVal = 0u; + + + /** + *1. Try fetching some CC registers value. + * It should PASS. + */ + /* PID Register */ + ccRegOffset = 0x0u; + ccRegVal = 0; + drvResult = EDMA3_DRV_getCCRegister(hEdma, ccRegOffset, &ccRegVal); + + if (drvResult != EDMA3_DRV_SOK) + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF ("Fetching CC Register (offset 0X%x) Failed, test FAILED\r\n", ccRegOffset); +#endif + } + else + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF ("Fetching CC Register (offset 0X%x) Passed, test PASSED\r\n", ccRegOffset); +#endif + +#ifdef EDMA3_DEBUG_PRINT + EDMA3_DEBUG_PRINTF ("Fetched CC Register at Offset 0X%x, Value = 0X%x\r\n", ccRegOffset, ccRegVal); +#endif /* EDMA3_DEBUG_PRINT */ + } + + + if (drvResult == EDMA3_DRV_SOK) + { + /* Fetch DRAE1 Register */ + ccRegOffset = 0x0348u; + ccRegVal = 0; + drvResult = EDMA3_DRV_getCCRegister(hEdma, ccRegOffset, &ccRegVal); + + if (drvResult != EDMA3_DRV_SOK) + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF ("Fetching CC Register (offset 0X%x) Failed, test FAILED\r\n", ccRegOffset); +#endif + } + else + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF ("Fetching CC Register (offset 0X%x) Passed, test PASSED\r\n", ccRegOffset); +#endif + +#ifdef EDMA3_DEBUG_PRINT + EDMA3_DEBUG_PRINTF ("Fetched CC Register at Offset 0X%x, Value = 0X%x\r\n", ccRegOffset, ccRegVal); +#endif /* EDMA3_DEBUG_PRINT */ + } + } + + + if (drvResult == EDMA3_DRV_SOK) + { + /* Fetch QWMTHRA Register */ + ccRegOffset = 0x0620u; + ccRegVal = 0; + drvResult = EDMA3_DRV_getCCRegister(hEdma, ccRegOffset, &ccRegVal); + + if (drvResult != EDMA3_DRV_SOK) + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF ("Fetching CC Register (offset 0X%x) Failed, test FAILED\r\n", ccRegOffset); +#endif + return drvResult; + } + else + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF ("Fetching CC Register (offset 0X%x) Passed, test PASSED\r\n", ccRegOffset); +#endif + +#ifdef EDMA3_DEBUG_PRINT + EDMA3_DEBUG_PRINTF ("Fetched CC Register at Offset 0X%x, Value = 0X%x\r\n", ccRegOffset, ccRegVal); +#endif /* EDMA3_DEBUG_PRINT */ + } + } + + + + /** + * 2. Try fetching some CC registers value, whose offset is not 4-bytes + * aligned. It should FAIL. + */ + if (drvResult == EDMA3_DRV_SOK) + { + ccRegOffset = 0x1002u; + ccRegVal = 0x0u; + drvResult = EDMA3_DRV_getCCRegister(hEdma, ccRegOffset, &ccRegVal); + + if (drvResult == EDMA3_DRV_E_INVALID_PARAM) + { +#ifdef EDMA3_DEBUG_PRINT + EDMA3_DEBUG_PRINTF ("Fetching Invalid CC Register (offset 0X%x) Failed, test PASSED\r\n", ccRegOffset); +#endif /* EDMA3_DEBUG_PRINT */ + drvResult = EDMA3_DRV_SOK; + } + else + { +#ifdef EDMA3_DEBUG_PRINT + EDMA3_DEBUG_PRINTF ("Fetching Invalid CC Register (offset 0X%x) Passed, test FAILED\r\n", ccRegOffset); +#endif /* EDMA3_DEBUG_PRINT */ + } + } + + + + /** + * 3. Read CC Register QWMTHRA. Store the current value. Write a different + * value on it. Read it back. Write the original value again. Read it back to + * cross-check. It should PASS. + */ + if (drvResult == EDMA3_DRV_SOK) + { + ccRegOffset = 0x0620u; + origRegVal = 0x0u; + drvResult = EDMA3_DRV_getCCRegister(hEdma, ccRegOffset, &origRegVal); + + if (drvResult != EDMA3_DRV_SOK) + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF ("Fetching CC Register (offset 0X%x) Failed, test FAILED\r\n", ccRegOffset); +#endif + } + else + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF ("Fetching CC Register (offset 0X%x) Passed, test PASSED\r\n", ccRegOffset); +#endif + +#ifdef EDMA3_DEBUG_PRINT + EDMA3_DEBUG_PRINTF ("Fetched CC Register at Offset 0X%x, Value = 0X%x\r\n", ccRegOffset, origRegVal); +#endif /* EDMA3_DEBUG_PRINT */ + + /* Find the new value to be written, it depends on the no of event queues */ + switch (origRegVal) + { + /* Write a new value on the same register */ + case 0x10: + /* 1 TC */ + newRegVal = 0x0Fu; + break; + + case 0x1010: + /* 2 TC */ + newRegVal = 0x0F0Fu; + break; + + case 0x101010: + /* 3 TC */ + newRegVal = 0x0F0F0Fu; + break; + + case 0x10101010: + /* 4 TC */ + newRegVal = 0x0F0F0F0Fu; + break; + + default: + newRegVal = origRegVal; + break; + } + + drvResult = EDMA3_DRV_setCCRegister (hEdma, ccRegOffset, newRegVal); + if (drvResult == EDMA3_DRV_SOK) + { + /* If write is successful, read it back to check */ + ccRegVal = 0x0u; + + drvResult = EDMA3_DRV_getCCRegister (hEdma, ccRegOffset, &ccRegVal); + if (drvResult == EDMA3_DRV_SOK) + { + /* Check with the value which we have written */ + if (newRegVal == ccRegVal) + { +#ifdef EDMA3_DEBUG_PRINT + EDMA3_DEBUG_PRINTF ("Value written successfully \r\n"); +#endif /* EDMA3_DEBUG_PRINT */ + } + else + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF ("QWMTHRA write FAILED \r\n"); +#endif + drvResult = EDMA3_DRV_E_INVALID_PARAM; + } + } + + /* Restore the original value */ + if (drvResult == EDMA3_DRV_SOK) + { + drvResult = EDMA3_DRV_setCCRegister (hEdma, ccRegOffset, origRegVal); + if (drvResult != EDMA3_DRV_SOK) + { +#ifdef EDMA3_DEBUG_PRINT + EDMA3_DEBUG_PRINTF ("QWMTHRA Restore FAILED\r\n"); +#endif /* EDMA3_DEBUG_PRINT */ + } + else + { +#ifdef EDMA3_DEBUG_PRINT + EDMA3_DEBUG_PRINTF ("QWMTHRA Restore Successful\r\n"); +#endif /* EDMA3_DEBUG_PRINT */ + } + } + } + } + } + + + return drvResult; + } + diff --git a/examples/edma3_driver/src/dma_ping_pong_test.c b/examples/edma3_driver/src/dma_ping_pong_test.c new file mode 100644 index 0000000..e94a69b --- /dev/null +++ b/examples/edma3_driver/src/dma_ping_pong_test.c @@ -0,0 +1,623 @@ +#include "sample.h" + +/** Test Case Description **/ +/** + * There are two big buffers of size (PING_PONG_NUM_COLUMNS * PING_PONG_NUM_ROWS). + * Both are present in DDR and are known as pingpongSrcBuf and pingpongDestBuf. + * There are two small buffers of size (PING_PONG_L1D_BUFFER_SIZE). They are known as + * ping buffer and pong buffer. + * The pingpongSrcBuf is divided into chunks, each having size of + * PING_PONG_L1D_BUFFER_SIZE. Data is being transferred from pingpongSrcBuf + * to either ping or pong buffers, using EDMA3. Logic behind using two ping pong + * buffers is that one can be processed by DSP while the other is used by EDMA3 + * for data movement. So ping and pong are alternately used by EDMA3 and DSP. + * Also, to simulate the real world scenario, as a part of DSP processing, + * I am copying data from ping/pong buffers to pingpongDestBuf. + * In the end, I compare pingpongSrcBuf and pingpongDestBuf to check whether + * the algorithm has worked fine. + */ +/** + * Number of columns in the bigger source buffer. + */ +#define PING_PONG_NUM_COLUMNS (720u) + +/** + * Number of columns in the bigger source buffer. + */ +#define PING_PONG_NUM_ROWS (480u) + +/* ACNT is equal to number of columns. */ +#define PING_PONG_ACNT PING_PONG_NUM_COLUMNS +/* BCNT is equal to number of rows which will be transferred in one shot. */ +#define PING_PONG_BCNT (8u) +/* CCNT is equal to 1. */ +#define PING_PONG_CCNT (1u) + +/* Number of times DMA will be triggered. */ +#define PING_PONG_NUM_TRIGGERS (PING_PONG_NUM_ROWS/PING_PONG_BCNT) + +/* Size of bigger buffers in DDR. */ +#define PING_PONG_DDR_BUFFER_SIZE (PING_PONG_NUM_COLUMNS*PING_PONG_NUM_ROWS) +/* Size of smaller buffers in IRAM. */ +#define PING_PONG_L1D_BUFFER_SIZE (PING_PONG_ACNT*PING_PONG_BCNT) + + +/* Ping pong source buffer */ +#ifdef EDMA3_ENABLE_DCACHE +/* Cache line aligned big source buffer. */ +/** + * The DATA_ALIGN pragma aligns the symbol to an alignment boundary. The + * alignment boundary is the maximum of the symbolÂ’s default alignment value + * or the value of the constant in bytes. The constant must be a power of 2. + * The syntax of the pragma in C is: + * #pragma DATA_ALIGN (symbol, constant); + */ +#pragma DATA_ALIGN(_pingpongSrcBuf, EDMA3_CACHE_LINE_SIZE_IN_BYTES); +#endif /* #ifdef EDMA3_ENABLE_DCACHE */ +static signed char _pingpongSrcBuf[PING_PONG_DDR_BUFFER_SIZE]; + + +/** + * Ping pong destination buffer. + * It will be used to copy data from L1D ping/pong buffers to check the + * validity. + */ +#ifdef EDMA3_ENABLE_DCACHE +/* Cache line aligned big destination buffer. */ +/** + * The DATA_ALIGN pragma aligns the symbol to an alignment boundary. The + * alignment boundary is the maximum of the symbolÂ’s default alignment value + * or the value of the constant in bytes. The constant must be a power of 2. + * The syntax of the pragma in C is: + * #pragma DATA_ALIGN (symbol, constant); + */ +#pragma DATA_ALIGN(_pingpongDestBuf, EDMA3_CACHE_LINE_SIZE_IN_BYTES); +#endif /* #ifdef EDMA3_ENABLE_DCACHE */ +static signed char _pingpongDestBuf[PING_PONG_DDR_BUFFER_SIZE]; + + +/* These destination buffers are in IRAM. */ +#ifdef EDMA3_ENABLE_DCACHE +/* Cache line aligned destination buffer 1 i.e. Ping buffer. */ +/** + * The DATA_ALIGN pragma aligns the symbol to an alignment boundary. The + * alignment boundary is the maximum of the symbolÂ’s default alignment value + * or the value of the constant in bytes. The constant must be a power of 2. + * The syntax of the pragma in C is: + * #pragma DATA_ALIGN (symbol, constant); + */ +#pragma DATA_ALIGN(_dstL1DBuff1, EDMA3_CACHE_LINE_SIZE_IN_BYTES); +#endif /* #ifdef EDMA3_ENABLE_DCACHE */ +#pragma DATA_SECTION(_dstL1DBuff1, "my_sect"); +static signed char _dstL1DBuff1[PING_PONG_L1D_BUFFER_SIZE]; + +#ifdef EDMA3_ENABLE_DCACHE +/* Cache line aligned destination buffer 2 i.e. Pong buffer. */ +/** + * The DATA_ALIGN pragma aligns the symbol to an alignment boundary. The + * alignment boundary is the maximum of the symbolÂ’s default alignment value + * or the value of the constant in bytes. The constant must be a power of 2. + * The syntax of the pragma in C is: + * #pragma DATA_ALIGN (symbol, constant); + */ +#pragma DATA_ALIGN(_dstL1DBuff2, EDMA3_CACHE_LINE_SIZE_IN_BYTES); +#endif /* #ifdef EDMA3_ENABLE_DCACHE */ +#pragma DATA_SECTION(_dstL1DBuff2, "my_sect"); +static signed char _dstL1DBuff2[PING_PONG_L1D_BUFFER_SIZE]; + +/* Pointers for all those buffers */ +static signed char *pingpongSrcBuf; +static signed char *pingpongDestBuf; +static signed char *pingpongSrcBufCopy; +static signed char *pingpongDestBufCopy; + +static signed char *dstL1DBuff1; +static signed char *dstL1DBuff2; + +/** Local MemCpy function */ +extern void edma3MemCpy(void *dst, const void *src, unsigned int len); + +static EDMA3_DRV_Result process_ping_pong_buffer(unsigned short buff_id) +{ + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + + /** + * Copy the L1D ping-pong buffers from L1D to DDR using CPU. + * This is kind of dummy processing routine. + */ + if (buff_id == 1u) + { + /* Copy pong buffer */ + + /* Invalidate first if cache is enabled, otherwise CPU will take from cache. */ + /** + * Since the ping/pong buffers are in IRAM, there is no need of invalidating + * them. If they are in DDR, invalidate them. + */ +#ifdef EDMA3_ENABLE_DCACHE + /* + if (result == EDMA3_DRV_SOK) + { + result = Edma3_CacheInvalidate((unsigned int)dstL1DBuff2, + PING_PONG_L1D_BUFFER_SIZE); + } + */ +#endif /* EDMA3_ENABLE_DCACHE */ + + if (result == EDMA3_DRV_SOK) + { + edma3MemCpy((void *)(pingpongDestBufCopy), + (const void *)(dstL1DBuff2), + PING_PONG_L1D_BUFFER_SIZE); + } + } + else + { + /* Copy ping buffer */ + + /* Invalidate first if cache is enabled, otherwise CPU will take from cache. */ +#ifdef EDMA3_ENABLE_DCACHE + /* + if (result == EDMA3_DRV_SOK) + { + result = Edma3_CacheInvalidate((unsigned int)dstL1DBuff1, + PING_PONG_L1D_BUFFER_SIZE); + } + */ +#endif /* EDMA3_ENABLE_DCACHE */ + + if (result == EDMA3_DRV_SOK) + { + edma3MemCpy((void *)(pingpongDestBufCopy), + (const void *)(dstL1DBuff1), + PING_PONG_L1D_BUFFER_SIZE); + } + } + + /* Adjust the pointer. */ + pingpongDestBufCopy += PING_PONG_L1D_BUFFER_SIZE; + + return result; +} + + +/** + * \brief EDMA3 ping-pong based data copy test case, using a DMA and + * a link channel. + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + */ +EDMA3_DRV_Result edma3_test_ping_pong_mode() + { + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + EDMA3_DRV_PaRAMRegs paramSet = {0,0,0,0,0,0,0,0,0,0,0,0}; + /* One master channel */ + unsigned int chId = 0; + /* Two link channels */ + unsigned int lChId1 = 0; + unsigned int lChId2 = 0; + unsigned int tcc = 0; + int i; + unsigned int count; + unsigned int Istestpassed = 0u; + unsigned int BRCnt = 0; + int srcbidx = 0, desbidx = 0; + int srccidx = 0, descidx = 0; + /* PaRAM Set handle */ + unsigned int phyaddress = 0; + EDMA3_DRV_ParamentryRegs *param_handle = NULL; + /* Number of triggers for EDMA3. */ + unsigned int numenabled = PING_PONG_NUM_TRIGGERS; + + pingpongSrcBuf = (signed char*)_pingpongSrcBuf; + pingpongDestBuf = (signed char*)_pingpongDestBuf; + pingpongSrcBufCopy = pingpongSrcBuf; + pingpongDestBufCopy = pingpongDestBuf; + dstL1DBuff1 = (signed char*)_dstL1DBuff1; + dstL1DBuff2 = (signed char*)_dstL1DBuff2; + + + /* Initalize source buffer for PING_PONG_DDR_BUFFER_SIZE bytes of data */ + for (count = 0u; count < PING_PONG_DDR_BUFFER_SIZE; count++) + { + pingpongSrcBuf[count] = (count % 0xFF); + } + + +#ifdef EDMA3_ENABLE_DCACHE + /* + * Note: These functions are required if the buffer is in DDR. + * For other cases, where buffer is NOT in DDR, user + * may or may not require the below functions. + */ + /* Flush the Source Buffer */ + if (result == EDMA3_DRV_SOK) + { + result = Edma3_CacheFlush((unsigned int)pingpongSrcBuf, PING_PONG_DDR_BUFFER_SIZE); + } + + /* Invalidate the Destination Buffers */ + if (result == EDMA3_DRV_SOK) + { + result = Edma3_CacheInvalidate((unsigned int)pingpongDestBuf, PING_PONG_DDR_BUFFER_SIZE); + } + + /** + * Since the ping/pong buffers are in IRAM, there is no need of invalidating + * them. If they are in DDR, invalidate them. + */ + + /* + if (result == EDMA3_DRV_SOK) + { + result = Edma3_CacheInvalidate((unsigned int)dstL1DBuff1, PING_PONG_L1D_BUFFER_SIZE); + } + if (result == EDMA3_DRV_SOK) + { + result = Edma3_CacheInvalidate((unsigned int)dstL1DBuff2, PING_PONG_L1D_BUFFER_SIZE); + } + */ +#endif /* EDMA3_ENABLE_DCACHE */ + + + /* Set B count reload as B count. */ + BRCnt = PING_PONG_BCNT; + + /* Setting up the SRC/DES Index */ + srcbidx = (int)PING_PONG_ACNT; + desbidx = (int)PING_PONG_ACNT; + + /* AB Sync Transfer Mode */ + srccidx = ((int)PING_PONG_ACNT * (int)PING_PONG_BCNT); + descidx = ((int)PING_PONG_ACNT * (int)PING_PONG_BCNT); + + /* Setup for DMA Channel 1*/ + tcc = EDMA3_DRV_TCC_ANY; + chId = EDMA3_DRV_DMA_CHANNEL_ANY; + + /* Request any DMA channel and any TCC */ + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_requestChannel (hEdma, &chId, &tcc, + (EDMA3_RM_EventQueue)0, + &callback1, NULL); + } + + /* If successful, allocate the two link channels. */ + if (result == EDMA3_DRV_SOK) + { + lChId1 = EDMA3_DRV_LINK_CHANNEL; + lChId2 = EDMA3_DRV_LINK_CHANNEL; + + result = ( + (EDMA3_DRV_requestChannel (hEdma, &lChId1, NULL, + (EDMA3_RM_EventQueue)0, + &callback1, NULL)) + || + (EDMA3_DRV_requestChannel (hEdma, &lChId2, NULL, + (EDMA3_RM_EventQueue)0, + &callback1, NULL)) + ); + } + + + /** + * Fill the PaRAM Sets associated with all these channels with transfer + * specific information. + */ + if (result == EDMA3_DRV_SOK) + { + paramSet.srcBIdx = srcbidx; + paramSet.destBIdx = desbidx; + paramSet.srcCIdx = srccidx; + paramSet.destCIdx = descidx; + + paramSet.aCnt = PING_PONG_ACNT; + paramSet.bCnt = PING_PONG_BCNT; + paramSet.cCnt = PING_PONG_CCNT; + + /* For AB-synchronized transfers, BCNTRLD is not used. */ + paramSet.bCntReload = BRCnt; + + /* Src & Dest are in INCR modes */ + paramSet.opt &= 0xFFFFFFFCu; + /* Program the TCC */ + paramSet.opt |= ((tcc << OPT_TCC_SHIFT) & OPT_TCC_MASK); + + /* Enable Intermediate & Final transfer completion interrupt */ + paramSet.opt |= (1 << OPT_ITCINTEN_SHIFT); + paramSet.opt |= (1 << OPT_TCINTEN_SHIFT); + + /* AB Sync Transfer Mode */ + paramSet.opt |= (1 << OPT_SYNCDIM_SHIFT); + + + /* Program the source and dest addresses for master DMA channel */ + paramSet.srcAddr = (unsigned int)(pingpongSrcBuf); + paramSet.destAddr = (unsigned int)(dstL1DBuff1); + + + /* Write to the master DMA channel first. */ + result = EDMA3_DRV_setPaRAM(hEdma, chId, ¶mSet); + } + + + /* If write is successful, write the same thing to first link channel. */ + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setPaRAM(hEdma, lChId1, ¶mSet); + } + + + /** + * Now modify the dest addresses and write the param set to the + * second link channel. + */ + if (result == EDMA3_DRV_SOK) + { + paramSet.destAddr = (unsigned int)(dstL1DBuff2); + + result = EDMA3_DRV_setPaRAM(hEdma, lChId2, ¶mSet); + } + + + + /** + * Do the linking now. + * Master DMA channel is linked to IInd Link channel. + * IInd Link channel is linked to Ist Link channel. + * Ist Link channel is again linked to IInd Link channel. + */ + if (result == EDMA3_DRV_SOK) + { + result = ( + (EDMA3_DRV_linkChannel (hEdma, chId, lChId2)) + || + (EDMA3_DRV_linkChannel (hEdma, lChId2, lChId1)) + || + (EDMA3_DRV_linkChannel (hEdma, lChId1, lChId2)) + ); + } + + /** + * Save the handle to the master dma channel param set. + * It will be used later to modify the source address quickly. + */ + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_getPaRAMPhyAddr(hEdma, chId, &phyaddress); + } + + /* + - Algorithm used in the ping pong copy: + 1. Application starts EDMA of first image stripe into ping buffer in L1D. + 2. Application waits for ping EDMA to finish. + 3. Application starts EDMA of next image stripe into pong buffer in L1D. + 4. Application starts processing ping buffer. + 5. Application waits for pong EDMA to finish. + 6. Application starts EDMA of next image stripe into ping buffer in L1D. + 7. Application starts processing pong buffer. + 8. Repeat from step 3, until image exhausted. + - EDMA re-programming should be minimized to reduce overhead (PaRAM + accesses via slow config bus), i.e. use 2 reload PaRAM entries, and + only change src address fields. + */ + + if (result == EDMA3_DRV_SOK) + { + /* Param address successfully fetched. */ + param_handle = (EDMA3_DRV_ParamentryRegs *)phyaddress; + + /* Step 1 */ + result = EDMA3_DRV_enableTransfer (hEdma, chId, + EDMA3_DRV_TRIG_MODE_MANUAL); + /** + * Every time a transfer is triggered, numenabled is decremented. + */ + numenabled--; + + /** + * Every time a transfer is triggered, pingpongSrcBufCopy is + * incremented to point it to correct source address. + */ + pingpongSrcBufCopy += PING_PONG_L1D_BUFFER_SIZE; + } + + + if (result == EDMA3_DRV_SOK) + { + /* Need to activate next param till numenabled is exhausted. */ + for (i = 0; numenabled; i++) + { + /* Step 2 */ + /* Wait for the Completion ISR. */ + while (irqRaised1 == 0u) + { + Task_sleep (1u); + } + + irqRaised1 = 0; + + /* + * Now modify the source buffer in the param set + * loaded to the master dma channel and trigger + * the transfer again.. + */ + param_handle->SRC = (unsigned int)pingpongSrcBufCopy; + + /* Step 3 */ + result = EDMA3_DRV_enableTransfer (hEdma, chId, + EDMA3_DRV_TRIG_MODE_MANUAL); + + /** + * Every time a transfer is triggered, numenabled is decremented. + */ + numenabled--; + + /** + * Every time a transfer is triggered, pingpongSrcBufCopy is + * incremented to point it to correct source address. + */ + pingpongSrcBufCopy += PING_PONG_L1D_BUFFER_SIZE; + + if (result != EDMA3_DRV_SOK) + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF ("edma3_test_ping_pong_mode: EDMA3_DRV_enableTransfer " \ + "Failed, error code: %d\r\n", result); +#endif /* EDMA3_DRV_DEBUG */ + break; + } + + /** + * Step 4, copy the ping buffer to the dest buffer in + * DDR (using CPU), as a part of processing. + */ + result = process_ping_pong_buffer(0u); + if (result != EDMA3_DRV_SOK) + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF ("edma3_test_ping_pong_mode: process_ping_pong_buffer " \ + "Failed, error code: %d\r\n", result); +#endif /* EDMA3_DRV_DEBUG */ + break; + } + + + /* Step 5 */ + /* Wait for the Completion ISR. */ + while (irqRaised1 == 0u) + { + Task_sleep (1u); + } + + /* Check the status of the completed transfer */ + if (irqRaised1 < 0) + { + /* Some error occured, break from the FOR loop. */ +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF ("\r\nedma3_test: Event Miss Occured!!!\r\n"); +#endif /* EDMA3_DRV_DEBUG */ + + /* Clear the error bits first */ + result = EDMA3_DRV_clearErrorBits (hEdma, chId); + break; + } + + + /** + * Last row will be transferred by the Pong buffer. + * So this step should be jumped over. + * Check for that... + */ + if (numenabled) + { + irqRaised1 = 0; + + /* Step 6 */ + /* + * Now modify the source buffer in the param set + * again and trigger the transfer... + */ + param_handle->SRC = (unsigned int)pingpongSrcBufCopy; + + result = EDMA3_DRV_enableTransfer (hEdma, chId, + EDMA3_DRV_TRIG_MODE_MANUAL); + /** + * Every time a transfer is triggered, numenabled is decremented. + */ + numenabled--; + + /** + * Every time a transfer is triggered, pingpongSrcBufCopy is + * incremented to point it to correct source address. + */ + pingpongSrcBufCopy += PING_PONG_L1D_BUFFER_SIZE; + + if (result != EDMA3_DRV_SOK) + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF ("edma3_test_ping_pong_mode: EDMA3_DRV_enableTransfer " \ + "Failed, error code: %d\r\n", result); +#endif /* EDMA3_DRV_DEBUG */ + break; + } + } + + /** + * Step 7, copy the pong buffer to the dest buffer in + * DDR (using CPU), as a part of processing. + */ + result = process_ping_pong_buffer(1u); + if (result != EDMA3_DRV_SOK) + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF ("edma3_test_ping_pong_mode: process_ping_pong_buffer " \ + "Failed, error code: %d\r\n", result); +#endif /* EDMA3_DRV_DEBUG */ + break; + } + } + } + + + + if (EDMA3_DRV_SOK == result) + { + /* Match the Source and Destination Buffers. */ + for (i = 0; i < PING_PONG_DDR_BUFFER_SIZE; i++) + { + if (pingpongSrcBuf[i] != pingpongDestBuf[i]) + { + Istestpassed = 0u; +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("edma3_test_ping_pong_mode: Data write-read matching" \ + "FAILED at i = %d\r\n", i); +#endif /* EDMA3_DRV_DEBUG */ + break; + } + } + if (i == PING_PONG_DDR_BUFFER_SIZE) + { + Istestpassed = 1u; + } + + + + /* Free the previously allocated channels. */ + result = ( + (EDMA3_DRV_freeChannel (hEdma, chId)) + || + (EDMA3_DRV_freeChannel (hEdma, lChId1)) + || + (EDMA3_DRV_freeChannel (hEdma, lChId2)) + ); + + if (result != EDMA3_DRV_SOK) + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("edma3_test_ping_pong_mode: EDMA3_DRV_freeChannel() FAILED, " \ + "error code: %d\r\n", result); +#endif /* EDMA3_DRV_DEBUG */ + } + } + + + if(Istestpassed == 1u) + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("edma3_test_ping_pong_mode PASSED\r\n"); +#endif /* EDMA3_DRV_DEBUG */ + } + else + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("edma3_test_ping_pong_mode FAILED\r\n"); +#endif /* EDMA3_DRV_DEBUG */ + result = ((EDMA3_DRV_SOK == result) ? + EDMA3_DATA_MISMATCH_ERROR : result); + } + + + return result; + } diff --git a/examples/edma3_driver/src/dma_poll_test.c b/examples/edma3_driver/src/dma_poll_test.c new file mode 100644 index 0000000..a8deded --- /dev/null +++ b/examples/edma3_driver/src/dma_poll_test.c @@ -0,0 +1,268 @@ +#include "sample.h" + +extern signed char _srcBuff1[MAX_BUFFER_SIZE]; +extern signed char _dstBuff1[MAX_BUFFER_SIZE]; + +extern signed char *srcBuff1; +extern signed char *dstBuff1; + +/** + * Test case demonstrating the poll mode scenario. + * A user has requested a data transfer without giving any + * callback function. After programming and enabling the channel, + * he uses different APIs (meant to be used in poll mode) + * to check the status of ongoing transfer. + * Interrupt will NOT occur in this case. + */ +/** + * \brief EDMA3 mem-to-mem data copy test case, using a DMA channel. + * This test case doesnot rely on the callback mechanism. + * Instead, it Polls the IPR register to check the transfer + * completion status. + * + * \param acnt [IN] Number of bytes in an array + * \param bcnt [IN] Number of arrays in a frame + * \param ccnt [IN] Number of frames in a block + * \param syncType [IN] Synchronization type (A/AB Sync) + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + */ +EDMA3_DRV_Result edma3_test_poll_mode( + unsigned int acnt, + unsigned int bcnt, + unsigned int ccnt, + EDMA3_DRV_SyncType syncType) + { + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + unsigned int chId = 0; + unsigned int tcc = 0; + int i; + unsigned int count; + unsigned int Istestpassed = 0u; + unsigned int numenabled = 0; + unsigned int BRCnt = 0; + int srcbidx = 0, desbidx = 0; + int srccidx = 0, descidx = 0; + + + srcBuff1 = (signed char*)_srcBuff1; + dstBuff1 = (signed char*)_dstBuff1; + + + /* Initalize source and destination buffers */ + for (count = 0u; count < (acnt*bcnt*ccnt); count++) + { + srcBuff1[count] = (int)count+5; + /** + * No need to initialize the destination buffer as it is being invalidated. + dstBuff1[count] = initval; + */ + } + + +#ifdef EDMA3_ENABLE_DCACHE + /* + * Note: These functions are required if the buffer is in DDR. + * For other cases, where buffer is NOT in DDR, user + * may or may not require the below functions. + */ + /* Flush the Source Buffer */ + if (result == EDMA3_DRV_SOK) + { + result = Edma3_CacheFlush((unsigned int)srcBuff1, (acnt*bcnt*ccnt)); + } + + /* Invalidate the Destination Buffer */ + if (result == EDMA3_DRV_SOK) + { + result = Edma3_CacheInvalidate((unsigned int)dstBuff1, (acnt*bcnt*ccnt)); + } +#endif /* EDMA3_ENABLE_DCACHE */ + + + /* Set B count reload as B count. */ + BRCnt = bcnt; + + /* Setting up the SRC/DES Index */ + srcbidx = (int)acnt; + desbidx = (int)acnt; + + if (syncType == EDMA3_DRV_SYNC_A) + { + /* A Sync Transfer Mode */ + srccidx = (int)acnt; + descidx = (int)acnt; + } + else + { + /* AB Sync Transfer Mode */ + srccidx = ((int)acnt * (int)bcnt); + descidx = ((int)acnt * (int)bcnt); + } + + + /* Setup for Channel 1*/ + tcc = EDMA3_DRV_TCC_ANY; + chId = EDMA3_DRV_DMA_CHANNEL_ANY; + + + /* Request any DMA channel and any TCC */ + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_requestChannel (hEdma, &chId, &tcc, + (EDMA3_RM_EventQueue)0, + NULL, NULL); + } + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setSrcParams (hEdma, chId, (unsigned int)(srcBuff1), + EDMA3_DRV_ADDR_MODE_INCR, + EDMA3_DRV_W8BIT); + } + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setDestParams (hEdma, chId, (unsigned int)(dstBuff1), + EDMA3_DRV_ADDR_MODE_INCR, + EDMA3_DRV_W8BIT); + } + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setSrcIndex (hEdma, chId, srcbidx, srccidx); + } + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setDestIndex (hEdma, chId, desbidx, descidx); + } + + if (result == EDMA3_DRV_SOK) + { + if (syncType == EDMA3_DRV_SYNC_A) + { + result = EDMA3_DRV_setTransferParams (hEdma, chId, acnt, bcnt, ccnt, + BRCnt, EDMA3_DRV_SYNC_A); + } + else + { + result = EDMA3_DRV_setTransferParams (hEdma, chId, acnt, bcnt, ccnt, + BRCnt, EDMA3_DRV_SYNC_AB); + } + } + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setOptField (hEdma, chId, + EDMA3_DRV_OPT_FIELD_TCINTEN, 1u); + } + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setOptField (hEdma, chId, + EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u); + } + + /* + * Since the transfer is going to happen in Manual mode of EDMA3 + * operation, we have to 'Enable the Transfer' multiple times. + * Number of times depends upon the Mode (A/AB Sync) + * and the different counts. + */ + if (result == EDMA3_DRV_SOK) + { + /*Need to activate next param*/ + if (syncType == EDMA3_DRV_SYNC_A) + { + numenabled = bcnt * ccnt; + } + else + { + /* AB Sync Transfer Mode */ + numenabled = ccnt; + } + + + for (i = 0; i < numenabled; i++) + { + /* + * Now enable the transfer as many times as calculated above. + */ + result = EDMA3_DRV_enableTransfer (hEdma, chId, + EDMA3_DRV_TRIG_MODE_MANUAL); + if (result != EDMA3_DRV_SOK) + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF ("edma3_test_poll_mode: EDMA3_DRV_enableTransfer " \ + "Failed, error code: %d\r\n", result); +#endif /* EDMA3_DRV_DEBUG */ + break; + } + + + /* Wait for the Completion Bit to be SET in the IPR/IPRH register. */ + result = EDMA3_DRV_waitAndClearTcc (hEdma, tcc); + if (result != EDMA3_DRV_SOK) + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF ("edma3_test_poll_mode: EDMA3_DRV_waitAndClearTcc " \ + "Failed, error code: %d\r\n", result); +#endif /* EDMA3_DRV_DEBUG */ + break; + } + } + } + + + /* Match the Source and Destination Buffers. */ + if (EDMA3_DRV_SOK == result) + { + for (i = 0; i < (acnt*bcnt*ccnt); i++) + { + if (srcBuff1[i] != dstBuff1[i]) + { + Istestpassed = 0u; +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("edma3_test_poll_mode: Data write-read matching" \ + "FAILED at i = %d\r\n", i); +#endif /* EDMA3_DRV_DEBUG */ + break; + } + } + if (i == (acnt*bcnt*ccnt)) + { + Istestpassed = 1u; + } + + + /* Free the previously allocated channel. */ + result = EDMA3_DRV_freeChannel (hEdma, chId); + if (result != EDMA3_DRV_SOK) + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("edma3_test_poll_mode: EDMA3_DRV_freeChannel() FAILED, " \ + "error code: %d\r\n", result); +#endif /* EDMA3_DRV_DEBUG */ + } + } + + + if(Istestpassed == 1u) + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("edma3_test_poll_mode PASSED\r\n"); +#endif /* EDMA3_DRV_DEBUG */ + } + else + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("edma3_test_poll_mode FAILED\r\n"); +#endif /* EDMA3_DRV_DEBUG */ + result = ((EDMA3_DRV_SOK == result) ? + EDMA3_DATA_MISMATCH_ERROR : result); + } + + + return result; +} diff --git a/examples/edma3_driver/src/dma_test.c b/examples/edma3_driver/src/dma_test.c new file mode 100644 index 0000000..d6a59f2 --- /dev/null +++ b/examples/edma3_driver/src/dma_test.c @@ -0,0 +1,324 @@ +#include "sample.h" + +extern signed char _srcBuff1[MAX_BUFFER_SIZE]; +extern signed char _dstBuff1[MAX_BUFFER_SIZE]; + +extern signed char *srcBuff1; +extern signed char *dstBuff1; + + +/** + * \brief EDMA3 mem-to-mem data copy test case, using a DMA channel. + * + * + * \param acnt [IN] Number of bytes in an array + * \param bcnt [IN] Number of arrays in a frame + * \param ccnt [IN] Number of frames in a block + * \param syncType [IN] Synchronization type (A/AB Sync) + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + */ +EDMA3_DRV_Result edma3_test( + unsigned int acnt, + unsigned int bcnt, + unsigned int ccnt, + EDMA3_DRV_SyncType syncType) + { + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + EDMA3_DRV_PaRAMRegs paramSet = {0,0,0,0,0,0,0,0,0,0,0,0}; + unsigned int chId = 0; + unsigned int tcc = 0; + int i; + unsigned int count; + unsigned int Istestpassed = 0u; + unsigned int numenabled = 0; + unsigned int BRCnt = 0; + int srcbidx = 0, desbidx = 0; + int srccidx = 0, descidx = 0; + + + srcBuff1 = (signed char*)_srcBuff1; + dstBuff1 = (signed char*)_dstBuff1; + + + /* Initalize source and destination buffers */ + for (count = 0u; count < (acnt*bcnt*ccnt); count++) + { + srcBuff1[count] = (int)count; + /** + * No need to initialize the destination buffer as it is being invalidated. + dstBuff1[count] = initval; + */ + } + + +#ifdef EDMA3_ENABLE_DCACHE + /* + * Note: These functions are required if the buffer is in DDR. + * For other cases, where buffer is NOT in DDR, user + * may or may not require the below functions. + */ + /* Flush the Source Buffer */ + if (result == EDMA3_DRV_SOK) + { + result = Edma3_CacheFlush((unsigned int)srcBuff1, (acnt*bcnt*ccnt)); + } + + /* Invalidate the Destination Buffer */ + if (result == EDMA3_DRV_SOK) + { + result = Edma3_CacheInvalidate((unsigned int)dstBuff1, (acnt*bcnt*ccnt)); + } +#endif /* EDMA3_ENABLE_DCACHE */ + + + /* Set B count reload as B count. */ + BRCnt = bcnt; + + /* Setting up the SRC/DES Index */ + srcbidx = (int)acnt; + desbidx = (int)acnt; + if (syncType == EDMA3_DRV_SYNC_A) + { + /* A Sync Transfer Mode */ + srccidx = (int)acnt; + descidx = (int)acnt; + } + else + { + /* AB Sync Transfer Mode */ + srccidx = ((int)acnt * (int)bcnt); + descidx = ((int)acnt * (int)bcnt); + } + + + /* Setup for Channel 1*/ + tcc = EDMA3_DRV_TCC_ANY; + chId = EDMA3_DRV_DMA_CHANNEL_ANY; + + /* Request any DMA channel and any TCC */ + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_requestChannel (hEdma, &chId, &tcc, + (EDMA3_RM_EventQueue)0, + &callback1, NULL); + } + + if (result == EDMA3_DRV_SOK) + { + /* Fill the PaRAM Set with transfer specific information */ + paramSet.srcAddr = (unsigned int)(srcBuff1); + paramSet.destAddr = (unsigned int)(dstBuff1); + + /** + * Be Careful !!! + * Valid values for SRCBIDX/DSTBIDX are between –32768 and 32767 + * Valid values for SRCCIDX/DSTCIDX are between –32768 and 32767 + */ + paramSet.srcBIdx = srcbidx; + paramSet.destBIdx = desbidx; + paramSet.srcCIdx = srccidx; + paramSet.destCIdx = descidx; + + /** + * Be Careful !!! + * Valid values for ACNT/BCNT/CCNT are between 0 and 65535. + * ACNT/BCNT/CCNT must be greater than or equal to 1. + * Maximum number of bytes in an array (ACNT) is 65535 bytes + * Maximum number of arrays in a frame (BCNT) is 65535 + * Maximum number of frames in a block (CCNT) is 65535 + */ + paramSet.aCnt = acnt; + paramSet.bCnt = bcnt; + paramSet.cCnt = ccnt; + + /* For AB-synchronized transfers, BCNTRLD is not used. */ + paramSet.bCntReload = BRCnt; + + paramSet.linkAddr = 0xFFFFu; + + /* Src & Dest are in INCR modes */ + paramSet.opt &= 0xFFFFFFFCu; + /* Program the TCC */ + paramSet.opt |= ((tcc << OPT_TCC_SHIFT) & OPT_TCC_MASK); + + /* Enable Intermediate & Final transfer completion interrupt */ + paramSet.opt |= (1 << OPT_ITCINTEN_SHIFT); + paramSet.opt |= (1 << OPT_TCINTEN_SHIFT); + + if (syncType == EDMA3_DRV_SYNC_A) + { + paramSet.opt &= 0xFFFFFFFBu; + } + else + { + /* AB Sync Transfer Mode */ + paramSet.opt |= (1 << OPT_SYNCDIM_SHIFT); + } + + /* Now, write the PaRAM Set. */ + result = EDMA3_DRV_setPaRAM(hEdma, chId, ¶mSet); + } + + + /* + * There is another way to program the PaRAM Set using specific APIs + * for different PaRAM set entries. It gives user more control and easier + * to use interface. User can use any of the methods. + * Below is the alternative way to program the PaRAM Set. + */ + + /* + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setSrcParams (hEdma, chId, (unsigned int)(srcBuff1), + EDMA3_DRV_ADDR_MODE_INCR, + EDMA3_DRV_W8BIT); + } + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setDestParams (hEdma, chId, (unsigned int)(dstBuff1), + EDMA3_DRV_ADDR_MODE_INCR, + EDMA3_DRV_W8BIT); + } + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setSrcIndex (hEdma, chId, srcbidx, srccidx); + } + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setDestIndex (hEdma, chId, desbidx, descidx); + } + + if (result == EDMA3_DRV_SOK) + { + if (syncType == EDMA3_DRV_SYNC_A) + { + result = EDMA3_DRV_setTransferParams (hEdma, chId, acnt, bcnt, ccnt, + BRCnt, EDMA3_DRV_SYNC_A); + } + else + { + result = EDMA3_DRV_setTransferParams (hEdma, chId, acnt, bcnt, ccnt, + BRCnt, EDMA3_DRV_SYNC_AB); + } + } + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setOptField (hEdma, chId, + EDMA3_DRV_OPT_FIELD_TCINTEN, 1u); + } + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setOptField (hEdma, chId, + EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u); + } + + */ + + + /* + * Since the transfer is going to happen in Manual mode of EDMA3 + * operation, we have to 'Enable the Transfer' multiple times. + * Number of times depends upon the Mode (A/AB Sync) + * and the different counts. + */ + if (result == EDMA3_DRV_SOK) + { + /*Need to activate next param*/ + if (syncType == EDMA3_DRV_SYNC_A) + { + numenabled = bcnt * ccnt; + } + else + { + /* AB Sync Transfer Mode */ + numenabled = ccnt; + } + + for (i = 0; i < numenabled; i++) + { + irqRaised1 = 0; + + /* + * Now enable the transfer as many times as calculated above. + */ + result = EDMA3_DRV_enableTransfer (hEdma, chId, + EDMA3_DRV_TRIG_MODE_MANUAL); + if (result != EDMA3_DRV_SOK) + { + printf ("edma3_test: EDMA3_DRV_enableTransfer " \ + "Failed, error code: %d\r\n", result); + break; + } + + /* Wait for the Completion ISR. */ + while (irqRaised1 == 0u) + { + Task_sleep (1u); + } + + /* Check the status of the completed transfer */ + if (irqRaised1 < 0) + { + /* Some error occured, break from the FOR loop. */ + printf ("\r\nedma3_test: Event Miss Occured!!!\r\n"); + + /* Clear the error bits first */ + result = EDMA3_DRV_clearErrorBits (hEdma, chId); + break; + } + } + } + + + /* Match the Source and Destination Buffers. */ + if (EDMA3_DRV_SOK == result) + { + for (i = 0; i < (acnt*bcnt*ccnt); i++) + { + if (srcBuff1[i] != dstBuff1[i]) + { + Istestpassed = 0u; + printf("edma3_test: Data write-read matching" \ + "FAILED at i = %d\r\n", i); + break; + } + } + if (i == (acnt*bcnt*ccnt)) + { + Istestpassed = 1u; + } + + + /* Free the previously allocated channel. */ + result = EDMA3_DRV_freeChannel (hEdma, chId); + if (result != EDMA3_DRV_SOK) + { + printf("edma3_test: EDMA3_DRV_freeChannel() FAILED, " \ + "error code: %d\r\n", result); + } + } + + + if(Istestpassed == 1u) + { + printf("edma3_test PASSED\r\n"); + } + else + { + printf("edma3_test FAILED\r\n"); + result = ((EDMA3_DRV_SOK == result) ? + EDMA3_DATA_MISMATCH_ERROR : result); + } + + + return result; +} + + diff --git a/examples/edma3_driver/src/main.c b/examples/edma3_driver/src/main.c new file mode 100644 index 0000000..3ba42df --- /dev/null +++ b/examples/edma3_driver/src/main.c @@ -0,0 +1,305 @@ +/******************************************************************************* +**+--------------------------------------------------------------------------+** +**| **** |** +**| **** |** +**| ******o*** |** +**| ********_///_**** |** +**| ***** /_//_/ **** |** +**| ** ** (__/ **** |** +**| ********* |** +**| **** |** +**| *** |** +**| |** +**| Copyright (c) 1998-2006 Texas Instruments Incorporated |** +**| ALL RIGHTS RESERVED |** +**| |** +**| Permission is hereby granted to licensees of Texas Instruments |** +**| Incorporated (TI) products to use this computer program for the sole |** +**| purpose of implementing a licensee product based on TI products. |** +**| No other rights to reproduce, use, or disseminate this computer |** +**| program, whether in part or in whole, are granted. |** +**| |** +**| TI makes no representation or warranties with respect to the |** +**| performance of this computer program, and specifically disclaims |** +**| any responsibility for any damages, special or consequential, |** +**| connected with the use of this program. |** +**| |** +**+--------------------------------------------------------------------------+** +*******************************************************************************/ + +/** \file main.c + * + * \brief This file contains the test / demo code to demonstrate the + * EDMA driver implemented for DSP/BIOS + * + * (C) Copyright 2006, Texas Instruments, Inc + * + * \author Anuj Aggarwal + * + * \version 1.0 Anuj Aggarwal - Created + */ + +#include +#include +#include +#include + +#include "sample.h" + +EDMA3_DRV_Result edma3MemToMemCpytest (); + +/* + * Local References + */ +static void tskHeartBit(void); +void echo(void); + +void main() +{ + Task_create((Task_FuncPtr)echo, NULL, NULL); + + BIOS_start(); +} + + +static void printWelcomeBanner(void) + { + /* Welcome Message */ + printf("***************************************************************\n\r"); + printf("* *\n\r"); + printf("* **** *\n\r"); + printf("* **** *\n\r"); + printf("* ******o*** *\n\r"); + printf("* ********_///_**** *\n\r"); + printf("* ***** /_//_/ **** *\n\r"); + printf("* ** ** (__/ **** *\n\r"); + printf("* ********* *\n\r"); + printf("* **** *\n\r"); + printf("* *** *\n\r"); + printf("* *\n\r"); + printf("* TI EDMA3 LOW LEVEL DRIVER *\n\r"); + printf("* *\n\r"); + printf("* *\n\r"); + printf("* For issues on TI EDMA3 LLD, contact TII PSP Team *\n\r"); + printf("* *\n\r"); + printf("* *\n\r"); + printf("* *\n\r"); + printf("***************************************************************\n\r"); + printf("\r\n\r\n"); + } + + + +void echo() + { + EDMA3_DRV_Result edmaResult = EDMA3_DRV_SOK; + + /* Print the Welcome Message */ + printWelcomeBanner(); + + /* Initialize EDMA3 first */ + edmaResult = edma3init(); + if (edmaResult != EDMA3_DRV_SOK) + { + printf("echo: edma3init() FAILED, error code: %d\r\n", + edmaResult); + } + else + { + printf("echo: edma3init() PASSED\r\n"); + } + + if (edmaResult == EDMA3_DRV_SOK) + { + /* Edma Test for memory to memory copy */ + printf("\r\nEDMA3: Starting EDMA3 Test memory to memory copy\r\n"); + + edmaResult = edma3MemToMemCpytest(); + + if (EDMA3_DRV_SOK != edmaResult) + { + /* Report EDMA Error */ + printf("\r\nEDMA3: edma3MemToMemCpytest() failed\r\n"); + } + else + { + printf("\r\nEDMA3: edma3MemToMemCpytest() passed\r\n"); + } + + printf("\r\nEDMA3 : End EDMA3 Test memory to memory copy\r\n\n"); + } + + /* De-init EDMA3 now. */ + edmaResult = edma3deinit(); + if (edmaResult != EDMA3_DRV_SOK) + { + printf("echo: edma3deinit() FAILED, error code: %d\r\n", + edmaResult); + } + else + { + printf("echo: edma3deinit() PASSED\r\n"); + } + + /* Start the Heart Beat Print */ + tskHeartBit(); + + return; + } + + + + +/** + * \brief Main sample test case which will call other EDMA3 test cases. + * If one wants to call Edma3 test cases, include this main + * test case only. + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + */ +EDMA3_DRV_Result edma3MemToMemCpytest () +{ + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + + if (hEdma == NULL) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + + /* Edma test without linking, async, incr mode */ + if (result == EDMA3_DRV_SOK) + { + result = edma3_test(512u, 32u, 8u, EDMA3_DRV_SYNC_A); + + if (result == EDMA3_DRV_SOK) + { + printf ("edma3_test (without linking) Passed\r\n"); + } + else + { + printf ("edma3_test (without linking) Failed\r\n"); + } + } + + /* Edma test with linking, async, incr mode */ + if (result == EDMA3_DRV_SOK) + { + result = edma3_test_with_link(512u, 32u, 8u, EDMA3_DRV_SYNC_A); + + if (result == EDMA3_DRV_SOK) + { + printf ("edma3_test_with_link Passed\r\n"); + } + else + { + printf ("edma3_test_with_link Failed\r\n"); + } + } + + /* Qdma test, async, incr mode */ + if (result == EDMA3_DRV_SOK) + { + result = qdma_test(512u, 32u, 8u, EDMA3_DRV_SYNC_A); + + if (result == EDMA3_DRV_SOK) + { + printf ("qdma_test Passed\r\n"); + } + else + { + printf ("qdma_test Failed\r\n"); + } + } + + /* Qdma test with linking, async, incr mode */ + if (result == EDMA3_DRV_SOK) + { + result = qdma_test_with_link (512u, 32u, 8u, EDMA3_DRV_SYNC_A); + + if (result == EDMA3_DRV_SOK) + { + printf ("qdma_test_with_link Passed\r\n"); + } + else + { + printf ("qdma_test_with_link Failed\r\n"); + } + } + + /* DMA channels with chaining test. */ + if (result == EDMA3_DRV_SOK) + { + result = edma3_test_with_chaining(512u, 32u, 8u, EDMA3_DRV_SYNC_A); + + if (result == EDMA3_DRV_SOK) + { + printf ("edma3_test_with_chaining Passed\r\n"); + } + else + { + printf ("edma3_test_with_chaining Failed\r\n"); + } + } + + /* DMA channels using Polling mode test. */ + if (result == EDMA3_DRV_SOK) + { + result = edma3_test_poll_mode(512u, 32u, 8u, EDMA3_DRV_SYNC_A); + + if (result == EDMA3_DRV_SOK) + { + printf ("edma3_test_poll_mode Passed\r\n"); + } + else + { + printf ("edma3_test_poll_mode Failed\r\n"); + } + } + + /* DMA channels in using ping-pong buffers test. */ + if (result == EDMA3_DRV_SOK) + { + result = edma3_test_ping_pong_mode(); + + if (result == EDMA3_DRV_SOK) + { + printf ("edma3_test_ping_pong_mode Passed\r\n"); + } + else + { + printf ("edma3_test_ping_pong_mode Failed\r\n"); + } + } + + /* Misc tests. */ + if (result == EDMA3_DRV_SOK) + { + result = edma3_misc_test(); + + if (result == EDMA3_DRV_SOK) + { + printf ("edma3_misc_test Passed\r\n"); + } + else + { + printf ("edma3_misc_test Failed\r\n"); + } + } + + return result; +} + + + +void tskHeartBit() + { + static unsigned int counter = 0u; + + while (counter < 0x1000000u) + { + Task_sleep (1000u); + printf("\r\n\r\n!!! EDMA3 LLD HrtBt %x", counter); + counter++; + } + } + diff --git a/examples/edma3_driver/src/ping_pong.cmd b/examples/edma3_driver/src/ping_pong.cmd new file mode 100644 index 0000000..c027350 --- /dev/null +++ b/examples/edma3_driver/src/ping_pong.cmd @@ -0,0 +1,4 @@ +SECTIONS +{ + my_sect :> IRAM +} \ No newline at end of file diff --git a/examples/edma3_driver/src/qdma_link_test.c b/examples/edma3_driver/src/qdma_link_test.c new file mode 100644 index 0000000..ac0fbe9 --- /dev/null +++ b/examples/edma3_driver/src/qdma_link_test.c @@ -0,0 +1,664 @@ +#include "sample.h" + +extern signed char _srcBuff1[MAX_BUFFER_SIZE]; +extern signed char _srcBuff2[MAX_BUFFER_SIZE]; +extern signed char _dstBuff1[MAX_BUFFER_SIZE]; +extern signed char _dstBuff2[MAX_BUFFER_SIZE]; + +extern signed char *srcBuff1; +extern signed char *srcBuff2; +extern signed char *dstBuff1; +extern signed char *dstBuff2; + + +/** + * Test case demonstrating the usgae of QDMA channel for transferring + * data between two memory locations. QDMA channel is linked to a LINK + * channel. + */ +/** + * \brief EDMA3 mem-to-mem data copy test case, using a QDMA channel, + * linked to another LINK channel. + * + * \param acnt [IN] Number of bytes in an array + * \param bcnt [IN] Number of arrays in a frame + * \param ccnt [IN] Number of frames in a block + * \param syncType [IN] Synchronization type (A/AB Sync) + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + */ +EDMA3_DRV_Result qdma_test_with_link( + unsigned int acnt, + unsigned int bcnt, + unsigned int ccnt, + EDMA3_DRV_SyncType syncType) + { + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + unsigned int i; + unsigned int count; + unsigned int Istestpassed1 = 0u; + unsigned int Istestpassed2 = 0u; + unsigned int qCh1Id=0; + unsigned int qTcc1 = 0; + unsigned int qCh2Id=0; + unsigned int qTcc2 = 0; + unsigned int BRCnt = 0; + int srcbidx = 0, desbidx = 0; + int srccidx = 0, descidx = 0; + unsigned int numenabled = 0; + static signed char* tmpSrcBuff1 = NULL; + static signed char* tmpDstBuff1 = NULL; + static signed char* tmpSrcBuff2 = NULL; + static signed char* tmpDstBuff2 = NULL; + unsigned int abCNT = 0; + unsigned int bcntReloadLinkField = 0x0u; + + + srcBuff1 = (signed char*) _srcBuff1; + dstBuff1 = (signed char*) _dstBuff1; + srcBuff2 = (signed char*) _srcBuff2; + dstBuff2 = (signed char*) _dstBuff2; + + + /* Store the original pointers for future usage. */ + tmpSrcBuff1 = srcBuff1; + tmpDstBuff1 = dstBuff1; + tmpSrcBuff2 = srcBuff2; + tmpDstBuff2 = dstBuff2; + + + /* Initalize source and destination buffers */ + for (count= 0u; count < (acnt*bcnt*ccnt); count++) + { + srcBuff1[count] = (int)count+3; + srcBuff2[count] = (int)count+3; + /** + * No need to initialize the destination buffer as it is being invalidated. + dstBuff1[count] = initval; + dstBuff2[count] = initval; + */ + } + + +#ifdef EDMA3_ENABLE_DCACHE + /* + * Note: These functions are required if the buffer is in DDR. + * For other cases, where buffer is NOT in DDR, user + * may or may not require the below functions. + */ + /* Flush the Source Buffers */ + if (result == EDMA3_DRV_SOK) + { + result = Edma3_CacheFlush((unsigned int)srcBuff1, (acnt*bcnt*ccnt)); + } + if (result == EDMA3_DRV_SOK) + { + result = Edma3_CacheFlush((unsigned int)srcBuff2, (acnt*bcnt*ccnt)); + } + + /* Invalidate the Destination Buffers */ + if (result == EDMA3_DRV_SOK) + { + result = Edma3_CacheInvalidate((unsigned int)dstBuff1, (acnt*bcnt*ccnt)); + } + if (result == EDMA3_DRV_SOK) + { + result = Edma3_CacheInvalidate((unsigned int)dstBuff2, (acnt*bcnt*ccnt)); + } +#endif /* EDMA3_ENABLE_DCACHE */ + + + /* Set B count reload as B count. */ + BRCnt = bcnt; + + /* Setting up the SRC/DES Index */ + srcbidx = (int)acnt; + desbidx = (int)acnt; + + if (syncType == EDMA3_DRV_SYNC_A) + { + /* A Sync Transfer Mode */ + srccidx = (int)acnt; + descidx = (int)acnt; + } + else + { + /* AB Sync Transfer Mode */ + srccidx = ((int)acnt * (int)bcnt); + descidx = ((int)acnt * (int)bcnt); + } + + + /* Setup for any QDMA Channel */ + qCh1Id = EDMA3_DRV_QDMA_CHANNEL_ANY; + qTcc1 = EDMA3_DRV_TCC_ANY; + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_requestChannel (hEdma, &qCh1Id, &qTcc1, + (EDMA3_RM_EventQueue)0, + &callback1, NULL); + } + + if (result == EDMA3_DRV_SOK) + { + /* Setup for Channel 2 (Link Channel) */ + qCh2Id = EDMA3_DRV_LINK_CHANNEL; + qTcc2 = EDMA3_DRV_TCC_ANY; + + result = EDMA3_DRV_requestChannel (hEdma, &qCh2Id, &qTcc2, + (EDMA3_RM_EventQueue)0, + &callback1, NULL); + } + + /* Configure the Link Channel first */ + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setSrcParams (hEdma, qCh2Id, + (unsigned int)(srcBuff2), + EDMA3_DRV_ADDR_MODE_INCR, + EDMA3_DRV_W8BIT); + } + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setDestParams (hEdma, qCh2Id, + (unsigned int)(dstBuff2), + EDMA3_DRV_ADDR_MODE_INCR, + EDMA3_DRV_W8BIT); + } + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setSrcIndex (hEdma, qCh2Id, srcbidx, srccidx); + } + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setDestIndex (hEdma, qCh2Id, desbidx, descidx); + } + + if (result == EDMA3_DRV_SOK) + { + if (syncType == EDMA3_DRV_SYNC_A) + { + result = EDMA3_DRV_setTransferParams (hEdma, qCh2Id, acnt, bcnt, + ccnt, BRCnt, + EDMA3_DRV_SYNC_A); + } + else + { + /* AB Sync Transfer Mode */ + result = EDMA3_DRV_setTransferParams (hEdma, qCh2Id, acnt, bcnt, + ccnt, BRCnt, + EDMA3_DRV_SYNC_AB); + } + } + + if (result == EDMA3_DRV_SOK) + { + /* Enable the Transfer Completion Interrupt on Link Channel */ + result = EDMA3_DRV_setOptField (hEdma, qCh2Id, + EDMA3_DRV_OPT_FIELD_TCINTEN, 1u); + } + + if (result == EDMA3_DRV_SOK) + { + /** + * Enable the Intermediate Transfer Completion Interrupt on Link + * Channel. + */ + result = EDMA3_DRV_setOptField (hEdma, qCh2Id, + EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u); + } + + if (result == EDMA3_DRV_SOK) + { + /* Link both the channels. */ + result = EDMA3_DRV_linkChannel (hEdma, qCh1Id, qCh2Id); + } + + if (result == EDMA3_DRV_SOK) + { + /** + * Now configure the QDMA channel. Here lies the trick. Since QDMA + * channel is linked to another DMA channel, as soon as transfer on + * QDMA channel is finished, static field being NOT SET, the associated + * PaRAM Set will be reloaded with the Linked PaRAM Set. Now, as the + * reload occurs, the QDMA channel will be triggered due to the write + * on a specific Trigger Word. We want the trigger to happen immediately + * after the write, so the trigger word should be chosen in such a way + * that it should trigger after the COMPLETE PaRAM Set will get copied + * onto the QDMA Channel PaRAM Set. In that case, only ONE option is + * there to choose the CCNT as the trigger word. All other trigger + * words will cause the trigger happen in-between the PaRAM Set is + * loading. So Set the trigger word as CCNT. + */ + result = EDMA3_DRV_setQdmaTrigWord (hEdma, qCh1Id, + EDMA3_RM_QDMA_TRIG_CCNT); + } + + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setSrcIndex (hEdma, qCh1Id, srcbidx, srccidx); + } + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setDestIndex (hEdma, qCh1Id, desbidx, descidx); + } + + abCNT = acnt | ((bcnt & 0xFFFFu) << 16u); + + /* Write ACNT and BCNT */ + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setPaRAMEntry(hEdma, qCh1Id, + EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT, + abCNT); + } + + /* Set the SYNC Mode (A/AB Sync) */ + if (syncType == EDMA3_DRV_SYNC_A) + { + result = EDMA3_DRV_setOptField (hEdma, qCh1Id, + EDMA3_DRV_OPT_FIELD_SYNCDIM, 0u); + } + else + { + result = EDMA3_DRV_setOptField (hEdma, qCh1Id, + EDMA3_DRV_OPT_FIELD_SYNCDIM, 1u); + } + + if (result == EDMA3_DRV_SOK) + { + /* Enable Transfer Completion Interrupt */ + result = EDMA3_DRV_setOptField (hEdma, qCh1Id, + EDMA3_DRV_OPT_FIELD_TCINTEN, 1u); + } + + if (result == EDMA3_DRV_SOK) + { + /* Enable Intermediate Transfer Completion Interrupt */ + result = EDMA3_DRV_setOptField (hEdma, qCh1Id, + EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u); + } + + if (result == EDMA3_DRV_SOK) + { + /* Set Source Transfer Mode as Increment Mode. */ + result = EDMA3_DRV_setOptField (hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_SAM, + EDMA3_DRV_ADDR_MODE_INCR); + } + + if (result == EDMA3_DRV_SOK) + { + /* Set Destination Transfer Mode as Increment Mode. */ + result = EDMA3_DRV_setOptField (hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_DAM, + EDMA3_DRV_ADDR_MODE_INCR); + } + + if (result == EDMA3_DRV_SOK) + { + /* Get Link Address. */ + result = EDMA3_DRV_getPaRAMField(hEdma, qCh1Id, + EDMA3_DRV_PARAM_FIELD_LINKADDR, + &bcntReloadLinkField); + } + + bcntReloadLinkField = (bcntReloadLinkField | (BRCnt << 16)); + + if (result == EDMA3_DRV_SOK) + { + /* Set B Count Reload & Link Address. */ + result = EDMA3_DRV_setPaRAMEntry(hEdma, qCh1Id, + EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD, + bcntReloadLinkField); + } + + + /*Need to activate next param*/ + if (syncType == EDMA3_DRV_SYNC_A) + { + numenabled = bcnt * ccnt; + } + else + { + /* AB Sync Transfer Mode */ + numenabled = ccnt; + } + + + if (numenabled == 1u) + { + /** + * If only one Sync event is required, make the PaRAM Set associated + * with the LINK channel as Static. + */ + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setOptField (hEdma, qCh2Id, + EDMA3_DRV_OPT_FIELD_STATIC, 1u); + } + + /** + * Be Careful!!! + * PaRAM Set associated with the Master Channel should NOT be + * set as Static, otherwise the reload will not occur. + */ + } + + + + /* + * Since the transfer is going to happen in QDMA mode of EDMA3 + * operation, we have to "Trigger" the transfer multiple times. + * Number of times depends upon the Mode (A/AB Sync) + * and the different counts. + */ + if (result == EDMA3_DRV_SOK) + { + for (i = 0u; i < numenabled; i++) + { + irqRaised1 = 0u; + + /* Write to the Source Address */ + result = EDMA3_DRV_setSrcParams (hEdma, qCh1Id, + (unsigned int)(srcBuff1), + EDMA3_DRV_ADDR_MODE_INCR, + EDMA3_DRV_W8BIT); + if (result != EDMA3_DRV_SOK) + { + printf ("error from qdma_test_with_link\r\n\r\n"); + return result; + } + + + /* Write to the Destination Address */ + result = EDMA3_DRV_setDestParams(hEdma, qCh1Id, + (unsigned int)(dstBuff1), + EDMA3_DRV_ADDR_MODE_INCR, + EDMA3_DRV_W8BIT); + if (result != EDMA3_DRV_SOK) + { + printf ("error from qdma_test_with_link\r\n\r\n"); + return result; + } + + + /* Now write to the Trigger Word i.e. CCNT. */ + result = EDMA3_DRV_setPaRAMEntry(hEdma, qCh1Id, EDMA3_DRV_PARAM_ENTRY_CCNT, ccnt); + if (result != EDMA3_DRV_SOK) + { + printf ("error from qdma_test_with_link\r\n\r\n"); + return result; + } + + + /* After this, transfer will start. */ + while (irqRaised1 == 0) + { + /* Wait for the Completion ISR for the Master QDMA Channel. */ + Task_sleep(1u); + } + + + /* Check the status of the completed transfer */ + if (irqRaised1 < 0) + { + /* Some error occured, break from the FOR loop. */ + printf ("\r\nqdma_test_with_link: Event Miss Occured!!!\r\n"); + + /* Clear the error bits first */ + result = EDMA3_DRV_clearErrorBits (hEdma, qCh1Id); + + break; + } + + + /** + * Now, update the source and destination addresses for next + * "Trigger". + */ + srcBuff1 += srccidx; + dstBuff1 += descidx; + + + /** + * Read the current C Count from the PaRAM Set and write it back. + * In this way, we would write the correct CCNT every time and + * trigger the transfer also. Since CC will decrement the CCNT + * after every (ACNT * BCNT) bytes of data transfer, we can use + * that decremented value to trigger the next transfer. + * Another option is to take count of CCNT manually (in your code) + * and write that value. + * First option seems less error prone. + */ + result = EDMA3_DRV_getPaRAMField(hEdma, qCh1Id, EDMA3_DRV_PARAM_FIELD_CCNT, &ccnt); + if (result != EDMA3_DRV_SOK) + { + printf ("error from qdma_test_with_link\r\n\r\n"); + return result; + } + } + } + + + /** + * Transfer on the QDMA channel has finished and Link + * PaRAM Set is loaded on the QDMA channel PaRAM Set. + * Now for the transfers on the LINK channel, + * if only one "TRIGGER" is required, + * that has already been provided by the PaRAM Set + * upload. + * For other triggers, we will take care. + */ + if (result == EDMA3_DRV_SOK) + { + /** + * One trigger has been provided already, so first wait for + * that transfer to complete. + */ + while (irqRaised1 == 0) + { + /* Wait for the Completion ISR for the Master QDMA Channel. */ + Task_sleep(1u); + } + + /* Check the status of the completed transfer */ + if (irqRaised1 < 0) + { + /* Some error occured, clear the error bits. */ + printf ("\r\nqdma_test_with_link: Event Miss Occured!!!\r\n"); + + /* Clear the error bits first */ + result = EDMA3_DRV_clearErrorBits (hEdma, qCh1Id); + } + + + if (numenabled == 1u) + { + /** + * Only 1 trigger was required which has been provided + * already. No need to do anything. + */ + } + else + { + /** + * One trigger has been provided already, so take that into account. + */ + numenabled -= 1u; + + for (i = 0u; i < numenabled; i++) + { + irqRaised1 = 0u; + + if (i == (numenabled - 1u)) + { + /** + * Before providing the last trigger, + * make the PaRAM Set static. + */ + result = EDMA3_DRV_setOptField (hEdma, qCh1Id, + EDMA3_DRV_OPT_FIELD_STATIC, 1u); + } + + /** + * Now, update the source and destination addresses for next + * "Trigger". + */ + srcBuff2 += srccidx; + dstBuff2 += descidx; + + + /** + * Read the current C Count from the PaRAM Set and write it back. + * In this way, we would write the correct CCNT every time and + * trigger the transfer also. + */ + result = EDMA3_DRV_getPaRAMField(hEdma, qCh1Id, EDMA3_DRV_PARAM_FIELD_CCNT, &ccnt); + if (result != EDMA3_DRV_SOK) + { + printf ("error from qdma_test_with_link\r\n\r\n"); + return result; + } + + + /* Write to the Source Address */ + result = EDMA3_DRV_setSrcParams (hEdma, qCh1Id, + (unsigned int)(srcBuff2), + EDMA3_DRV_ADDR_MODE_INCR, + EDMA3_DRV_W8BIT); + if (result != EDMA3_DRV_SOK) + { + printf ("error from qdma_test_with_link\r\n\r\n"); + return result; + } + + + /* Write to the Destination Address */ + result = EDMA3_DRV_setDestParams(hEdma, qCh1Id, + (unsigned int)(dstBuff2), + EDMA3_DRV_ADDR_MODE_INCR, + EDMA3_DRV_W8BIT); + if (result != EDMA3_DRV_SOK) + { + printf ("error from qdma_test_with_link\r\n\r\n"); + return result; + } + + + /* Now write to the Trigger Word i.e. CCNT. */ + result = EDMA3_DRV_setPaRAMEntry(hEdma, qCh1Id, EDMA3_DRV_PARAM_ENTRY_CCNT, ccnt); + if (result != EDMA3_DRV_SOK) + { + printf ("error from qdma_test_with_link\r\n\r\n"); + return result; + } + + + /* After this, transfer will start. */ + while (irqRaised1 == 0) + { + /* Wait for the Completion ISR for the Link Channel. */ + Task_sleep(1u); + } + + + /* Check the status of the completed transfer */ + if (irqRaised1 < 0) + { + /* Some error occured, break from the FOR loop. */ + printf ("\r\nqdma_test_with_link: Event Miss Occured!!!\r\n"); + + /* Clear the error bits first */ + result = EDMA3_DRV_clearErrorBits (hEdma, qCh1Id); + + break; + } + } + } + } + + + /* Restore the src and dest buffers */ + srcBuff1 = tmpSrcBuff1; + dstBuff1 = tmpDstBuff1; + srcBuff2 = tmpSrcBuff2; + dstBuff2 = tmpDstBuff2; + + + /* Match the Source and Destination Buffers. */ + if (EDMA3_DRV_SOK == result) + { + for (i = 0; i < (acnt*bcnt*ccnt); i++) + { + if (srcBuff1[i] != dstBuff1[i]) + { + Istestpassed1 = 0; + printf("qdma_test_with_link: Data write-read " \ + "matching FAILED at i = %d " \ + "(srcBuff1 -> dstBuff1)\r\r\n", i); + break; + } + } + if (i == (acnt*bcnt*ccnt)) + { + Istestpassed1 = 1u; + } + + + for (i = 0; i < (acnt*bcnt*ccnt); i++) + { + if (srcBuff2[i] != dstBuff2[i]) + { + Istestpassed2 = 0; + printf("qdma_test_with_link: Data write-read " \ + "matching FAILED at i = %d " \ + "(srcBuff2 -> dstBuff2)\r\n", i); + break; + } + } + if (i == (acnt*bcnt*ccnt)) + { + Istestpassed2 = 1u; + } + } + + + if (EDMA3_DRV_SOK == result) + { + /* Free the previously allocated channels. */ + result = EDMA3_DRV_freeChannel (hEdma, qCh1Id); + if (result != EDMA3_DRV_SOK) + { + printf("qdma_test_with_link: EDMA3_DRV_freeChannel() for qCh1Id FAILED, error code: %d\r\n", result); + } + else + { + result = EDMA3_DRV_freeChannel (hEdma, qCh2Id); + if (result != EDMA3_DRV_SOK) + { + printf("qdma_test_with_link: EDMA3_DRV_freeChannel() for qCh2Id FAILED, error code: %d\r\n", result); + } + } + } + + + if((Istestpassed1 == 1u) && (Istestpassed2 == 1u)) + { + printf("qdma_test_with_link PASSED\r\n"); + } + else + { + printf("qdma_test_with_link FAILED\r\n"); + result = ((EDMA3_DRV_SOK == result) ? + EDMA3_DATA_MISMATCH_ERROR : result); + } + + + return result; + } + diff --git a/examples/edma3_driver/src/qdma_test.c b/examples/edma3_driver/src/qdma_test.c new file mode 100644 index 0000000..b294f12 --- /dev/null +++ b/examples/edma3_driver/src/qdma_test.c @@ -0,0 +1,296 @@ +#include "sample.h" + +extern signed char _srcBuff1[MAX_BUFFER_SIZE]; +extern signed char _dstBuff1[MAX_BUFFER_SIZE]; + +extern signed char *srcBuff1; +extern signed char *dstBuff1; + + +/** + * \brief EDMA3 mem-to-mem data copy test case, using a QDMA channel. + * + * + * \param acnt [IN] Number of bytes in an array + * \param bcnt [IN] Number of arrays in a frame + * \param ccnt [IN] Number of frames in a block + * \param syncType [IN] Synchronization type (A/AB Sync) + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + */ +EDMA3_DRV_Result qdma_test( + unsigned int acnt, + unsigned int bcnt, + unsigned int ccnt, + EDMA3_DRV_SyncType syncType) + { + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + unsigned int i; + unsigned int count; + unsigned int Istestpassed = 0u; + unsigned int numenabled = 0; + unsigned int qCh1Id=0; + unsigned int qTcc1 = 0; + unsigned int BRCnt = 0; + int srcbidx = 0, desbidx = 0; + int srccidx = 0, descidx = 0; + static signed char* tmpSrcBuff1 = NULL; + static signed char* tmpDstBuff1 = NULL; + + srcBuff1 = (signed char*) _srcBuff1; + dstBuff1 = (signed char*) _dstBuff1; + + tmpSrcBuff1 = srcBuff1; + tmpDstBuff1 = dstBuff1; + + /* Initalize source and destination buffers */ + for (count = 0u; count < (acnt*bcnt*ccnt); count++) + { + srcBuff1[count] = (int)count+2; + /** + * No need to initialize the destination buffer as it is being invalidated. + dstBuff1[count] = initval; + */ + } + +#ifdef EDMA3_ENABLE_DCACHE + /* + * Note: These functions are required if the buffer is in DDR. + * For other cases, where buffer is NOT in DDR, user + * may or may not require the below functions. + */ + /* Flush the Source Buffer */ + if (result == EDMA3_DRV_SOK) + { + result = Edma3_CacheFlush((unsigned int)srcBuff1, (acnt*bcnt*ccnt)); + } + + /* Invalidate the Destination Buffer */ + if (result == EDMA3_DRV_SOK) + { + result = Edma3_CacheInvalidate((unsigned int)dstBuff1, (acnt*bcnt*ccnt)); + } +#endif /* EDMA3_ENABLE_DCACHE */ + + + irqRaised1 = 0; + + /* Set B count reload as B count. */ + BRCnt = bcnt; + /* Setting up the SRC/DES Index */ + srcbidx = (int)acnt; + desbidx = (int)acnt; + + if (syncType == EDMA3_DRV_SYNC_A) + { + srccidx = (int)acnt; + descidx = (int)acnt; + } + else + { + /* AB Sync Transfer Mode */ + srccidx = ((int)acnt * (int)bcnt); + descidx = ((int)acnt * (int)bcnt); + } + + + /* Setup for any QDMA Channel */ + qCh1Id = EDMA3_DRV_QDMA_CHANNEL_ANY; + qTcc1 = EDMA3_DRV_TCC_ANY; + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_requestChannel (hEdma, &qCh1Id, &qTcc1, + (EDMA3_RM_EventQueue)0, &callback1, + NULL); + } + + if (result == EDMA3_DRV_SOK) + { + /* Set QDMA Trigger Word as Destination Address */ + result = EDMA3_DRV_setQdmaTrigWord (hEdma, qCh1Id, + EDMA3_RM_QDMA_TRIG_DST); + } + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setSrcIndex (hEdma, qCh1Id, srcbidx, srccidx); + } + + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setDestIndex (hEdma, qCh1Id, desbidx, descidx); + } + + if (result == EDMA3_DRV_SOK) + { + if (syncType == EDMA3_DRV_SYNC_A) + { + result = EDMA3_DRV_setTransferParams (hEdma, qCh1Id, acnt, bcnt, + ccnt, BRCnt, EDMA3_DRV_SYNC_A); + } + else + { + /* AB Sync Transfer Mode */ + result = EDMA3_DRV_setTransferParams (hEdma, qCh1Id, acnt, bcnt, + ccnt, BRCnt, EDMA3_DRV_SYNC_AB); + } + } + + if (result == EDMA3_DRV_SOK) + { + /* Enable Transfer Completion Interrupt */ + result = EDMA3_DRV_setOptField (hEdma, qCh1Id, + EDMA3_DRV_OPT_FIELD_TCINTEN, 1u); + } + + if (result == EDMA3_DRV_SOK) + { + /* Enable Intermediate Transfer Completion Interrupt */ + result = EDMA3_DRV_setOptField (hEdma, qCh1Id, + EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u); + } + + if (result == EDMA3_DRV_SOK) + { + /* Set Source Transfer Mode as Increment Mode. */ + result = EDMA3_DRV_setOptField (hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_SAM, + EDMA3_DRV_ADDR_MODE_INCR); + } + + if (result == EDMA3_DRV_SOK) + { + /* Set Destination Transfer Mode as Increment Mode. */ + result = EDMA3_DRV_setOptField (hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_DAM, + EDMA3_DRV_ADDR_MODE_INCR); + } + + + /* + * Since the transfer is going to happen in QDMA mode of EDMA3 + * operation, we have to "Trigger" the transfer multiple times. + * Number of times depends upon the Mode (A/AB Sync) + * and the different counts. + */ + if (result == EDMA3_DRV_SOK) + { + /*Need to activate next param*/ + if (syncType == EDMA3_DRV_SYNC_A) + { + numenabled = bcnt * ccnt; + } + else + { + /* AB Sync Transfer Mode */ + numenabled = ccnt; + } + + for (i = 0u; i < numenabled; i++) + { + irqRaised1 = 0u; + + if (i == (numenabled-1u)) + { + /** + * Since OPT.STATIC field should be SET for isolated QDMA + * transfers or for the final transfer in a linked list of QDMA + * transfers, do the needful for the last request. + */ + result = EDMA3_DRV_setOptField (hEdma, qCh1Id, + EDMA3_DRV_OPT_FIELD_STATIC, 1u); + } + + /* Write to the Source Address */ + result = EDMA3_DRV_setSrcParams (hEdma, qCh1Id, + (unsigned int)(srcBuff1), + EDMA3_DRV_ADDR_MODE_INCR, + EDMA3_DRV_W8BIT); + /* + * Now trigger the QDMA channel by writing to the Trigger + * Word which is set as Destination Address. + */ + if (result == EDMA3_DRV_SOK) + { + result = EDMA3_DRV_setPaRAMEntry (hEdma, qCh1Id, + EDMA3_DRV_PARAM_ENTRY_DST, + (unsigned int)(dstBuff1)); + if (result != EDMA3_DRV_SOK) + { + printf ("error from qdma_test\n\r\n"); + break; + } + } + + /* Wait for the Completion ISR. */ + while (irqRaised1 == 0) + { + /* Wait for the Completion ISR. */ + Task_sleep (1u); + } + + /* Check the status of the completed transfer */ + if (irqRaised1 < 0) + { + /* Some error occured, break from the FOR loop. */ + printf ("\r\nqdma_test: Event Miss Occured!!!\r\n"); + + /* Clear the error bits first */ + result = EDMA3_DRV_clearErrorBits (hEdma, qCh1Id); + + break; + } + + /** + * Now, update the source and destination addresses for next + * "Trigger". + */ + srcBuff1 += srccidx; + dstBuff1 += descidx; + } + } + + if (result == EDMA3_DRV_SOK) + { + /* Restore the src and dest buffers */ + srcBuff1 = tmpSrcBuff1; + dstBuff1 = tmpDstBuff1; + + /* Match the Source and Destination Buffers. */ + for (i = 0u; i < (acnt*bcnt*ccnt); i++) + { + if (srcBuff1[i] != dstBuff1[i]) + { + Istestpassed = 0u; + printf("qdma_test: Data write-read matching FAILED" \ + " at i = %d\r\n", i); + break; + } + } + if (i == (acnt*bcnt*ccnt)) + { + Istestpassed = 1u; + } + + /* Free the previously allocated channel. */ + result = EDMA3_DRV_freeChannel (hEdma, qCh1Id); + if (result != EDMA3_DRV_SOK) + { + printf("qdma_test: EDMA3_DRV_freeChannel() FAILED, error code: %d\r\n", result); + } + } + + if(Istestpassed == 1u) + { + printf("qdma_test PASSED\r\n"); + } + else + { + printf("qdma_test FAILED\r\n"); + result = ((EDMA3_DRV_SOK == result) ? + EDMA3_DATA_MISMATCH_ERROR : result); + } + + return result; + } + + diff --git a/examples/edma3_driver/src/sample.h b/examples/edma3_driver/src/sample.h new file mode 100644 index 0000000..0da3f90 --- /dev/null +++ b/examples/edma3_driver/src/sample.h @@ -0,0 +1,255 @@ +/******************************************************************************* +**+--------------------------------------------------------------------------+** +**| **** |** +**| **** |** +**| ******o*** |** +**| ********_///_**** |** +**| ***** /_//_/ **** |** +**| ** ** (__/ **** |** +**| ********* |** +**| **** |** +**| *** |** +**| |** +**| Copyright (c) 1998-2006 Texas Instruments Incorporated |** +**| ALL RIGHTS RESERVED |** +**| |** +**| Permission is hereby granted to licensees of Texas Instruments |** +**| Incorporated (TI) products to use this computer program for the sole |** +**| purpose of implementing a licensee product based on TI products. |** +**| No other rights to reproduce, use, or disseminate this computer |** +**| program, whether in part or in whole, are granted. |** +**| |** +**| TI makes no representation or warranties with respect to the |** +**| performance of this computer program, and specifically disclaims |** +**| any responsibility for any damages, special or consequential, |** +**| connected with the use of this program. |** +**| |** +**+--------------------------------------------------------------------------+** +*******************************************************************************/ + +/** \file bios6_edma3_drv_sample.h + + \brief Header file for the Demo application for the EDMA3 Driver. + + (C) Copyright 2006, Texas Instruments, Inc + + \version 1.0 Anuj Aggarwal - Created + + */ + +#ifndef _SAMPLE_H_ +#define _SAMPLE_H_ + +#include +#include +#include + +/* Include EDMA3 Driver */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/* To include linking or chaining test case. */ +#define QDMA_TEST_WITH_LINKING (1u) +/* #undef QDMA_TEST_WITH_LINKING */ + +#define EDMA3_TEST_WITH_CHAINING (1u) +/* #undef EDMA3_TEST_WITH_CHAINING */ + +/* To include Poll mode tests */ +#define EDMA3_POLL_MODE_TEST (1u) +/* #undef EDMA3_POLL_MODE_TEST */ + +/* To include ping-pong buffer tests */ +#define EDMA3_PING_PONG_TEST (1u) +/* #undef EDMA3_PING_PONG_TEST */ + + +/** + * Buffers (src and dest) are needed for mem-2-mem data transfers. + * This define is for the MAXIMUM size and hence the maximum data + * which could be transferred using the sample test cases below. + */ +#define MAX_BUFFER_SIZE (512u*32u*8u) + +/** + * Cache line size on the underlying SoC. It needs to be modified + * for different cache line sizes, if the Cache is Enabled. + */ +#define EDMA3_CACHE_LINE_SIZE_IN_BYTES (128u) + +/* To enable/disable the cache .*/ +#define EDMA3_ENABLE_DCACHE (1u) + +/* OPT Field specific defines */ +#define OPT_SYNCDIM_SHIFT (0x00000002u) +#define OPT_TCC_MASK (0x0003F000u) +#define OPT_TCC_SHIFT (0x0000000Cu) +#define OPT_ITCINTEN_SHIFT (0x00000015u) +#define OPT_TCINTEN_SHIFT (0x00000014u) + + +/* Error returned in case of data mismatch */ +#define EDMA3_DATA_MISMATCH_ERROR (-1) + + + +/** + * EDMA3 Driver Handle, which is used to call all the Driver APIs. + * It gets initialized during EDMA3 Initialization. + */ +extern EDMA3_DRV_Handle hEdma; + + +extern void callback1 (unsigned int tcc, EDMA3_RM_TccStatus status, + void *appData); + +extern void callback2 (unsigned int tcc, EDMA3_RM_TccStatus status, + void *appData); + +/* Flag variable to check transfer completion on channel 1 */ +extern volatile short irqRaised1; +/* Flag variable to check transfer completion on channel 2 */ +extern volatile short irqRaised2; + + +/** + * \brief EDMA3 mem-to-mem data copy test case, using a DMA channel. + * + * + * \param acnt [IN] Number of bytes in an array + * \param bcnt [IN] Number of arrays in a frame + * \param ccnt [IN] Number of frames in a block + * \param syncType [IN] Synchronization type (A/AB Sync) + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + */ +EDMA3_DRV_Result edma3_test( + unsigned int acnt, + unsigned int bcnt, + unsigned int ccnt, + EDMA3_DRV_SyncType syncType); + + + +/** + * \brief EDMA3 mem-to-mem data copy test case, using two DMA + * channels, linked to each other. + * + * \param acnt [IN] Number of bytes in an array + * \param bcnt [IN] Number of arrays in a frame + * \param ccnt [IN] Number of frames in a block + * \param syncType [IN] Synchronization type (A/AB Sync) + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + */ +EDMA3_DRV_Result edma3_test_with_link( + unsigned int acnt, + unsigned int bcnt, + unsigned int ccnt, + EDMA3_DRV_SyncType syncType); + + + +/** + * \brief EDMA3 mem-to-mem data copy test case, using a QDMA channel. + * + * + * \param acnt [IN] Number of bytes in an array + * \param bcnt [IN] Number of arrays in a frame + * \param ccnt [IN] Number of frames in a block + * \param syncType [IN] Synchronization type (A/AB Sync) + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + */ +EDMA3_DRV_Result qdma_test( + unsigned int acnt, + unsigned int bcnt, + unsigned int ccnt, + EDMA3_DRV_SyncType syncType); + + + +/** + * \brief EDMA3 misc test cases. + * This test case will read/write to some CC registers. + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + */ +EDMA3_DRV_Result edma3_misc_test(); + + +/** + * \brief EDMA3 mem-to-mem data copy test case, using a QDMA channel, + * linked to another LINK channel. + * + * \param acnt [IN] Number of bytes in an array + * \param bcnt [IN] Number of arrays in a frame + * \param ccnt [IN] Number of frames in a block + * \param syncType [IN] Synchronization type (A/AB Sync) + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + */ +EDMA3_DRV_Result qdma_test_with_link( + unsigned int acnt, + unsigned int bcnt, + unsigned int ccnt, + EDMA3_DRV_SyncType syncType); + + +/** + * \brief EDMA3 mem-to-mem data copy test case, using two DMA channels, + * chained to each other. + * + * \param acnt [IN] Number of bytes in an array + * \param bcnt [IN] Number of arrays in a frame + * \param ccnt [IN] Number of frames in a block + * \param syncType [IN] Synchronization type (A/AB Sync) + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + */ +EDMA3_DRV_Result edma3_test_with_chaining( + unsigned int acnt, + unsigned int bcnt, + unsigned int ccnt, + EDMA3_DRV_SyncType syncType); + + +/** + * \brief EDMA3 mem-to-mem data copy test case, using a DMA channel. + * This test case doesnot rely on the callback mechanism. + * Instead, it Polls the IPR register to check the transfer + * completion status. + * + * \param acnt [IN] Number of bytes in an array + * \param bcnt [IN] Number of arrays in a frame + * \param ccnt [IN] Number of frames in a block + * \param syncType [IN] Synchronization type (A/AB Sync) + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + */ +EDMA3_DRV_Result edma3_test_poll_mode( + unsigned int acnt, + unsigned int bcnt, + unsigned int ccnt, + EDMA3_DRV_SyncType syncType); + + +/** + * \brief EDMA3 ping-pong based data copy test case, using a DMA and + * a link channel. + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + */ +EDMA3_DRV_Result edma3_test_ping_pong_mode(); + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif /* _SAMPLE_H_ */ + diff --git a/package.bld b/package.bld new file mode 100644 index 0000000..cde803f --- /dev/null +++ b/package.bld @@ -0,0 +1,42 @@ +/* + * ======== package.bld ======== + */ + +/* + * Create a new repository in this bundle named "packages". + * By convention most bundles contain a "packages" repository + * to hold the "high value" content. Other supporting content + * such as examples are often put into separate repositories. + */ +var rep = Pkg.addRepository('packages'); + +/* + * Define the contents of the new repository. Initially the + * repository is empty -- here we name the packages that are + * to be released in this repository. + * + * The packages are named using a special syntax: + * ':' + * + * Each named package is found along the package path. The + * release name is a tar file produced by "xdc release" on + * the named package, and is located in the package itself. + */ +rep.addPackages( + [ + 'ti.sdo.edma3.rm:ti_sdo_edma3_rm.tar', + 'ti.sdo.edma3.rm.sample:ti_sdo_edma3_rm_sample.tar', + 'ti.sdo.edma3.drv:ti_sdo_edma3_drv.tar', + 'ti.sdo.edma3.drv.sample:ti_sdo_edma3_drv_sample.tar', + ] +); + + +Pkg.otherFiles = [ + 'docs', + 'examples', + /* 'config.bld', */ + 'package.bld', + 'release_notes_edma3_lld_02_00_00.html', +]; + diff --git a/package.xdc b/package.xdc new file mode 100644 index 0000000..fd6b200 --- /dev/null +++ b/package.xdc @@ -0,0 +1,17 @@ +/* + * List the packages to be included in the bundle. The 'requires' + * statements must come before the 'package' statement. + */ +requires ti.sdo.edma3.rm; +requires ti.sdo.edma3.rm.sample; + +requires ti.sdo.edma3.drv; +requires ti.sdo.edma3.drv.sample; + + +/*! + * ======== edma3_lld_02_00_00_03 ======== + */ +package edma3_lld_02_00_00_03 [02, 00, 00] { +} + diff --git a/packages/config.bld b/packages/config.bld new file mode 100644 index 0000000..beb6693 --- /dev/null +++ b/packages/config.bld @@ -0,0 +1,44 @@ +/* + * ======== config.bld ======== + * Sample Build configuration script + */ + +/* load the required modules for the configuration */ +var C674 = xdc.useModule('ti.targets.C674'); + +/* compiler paths for the CCS4.0 */ +var rootDirPre = "C:/Program Files/"; +var rootDirPost = "Code Generation Tools 6.1.5"; + + +/**********************************c674******************************/ + +/* configure the options for the c674 targets */ + +/* c674 compiler directory path */ +C674.rootDir = rootDirPre + "C6000" + rootDirPost;; + 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\li2520\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin2520\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext50 DescContinue 7;}{ +\s50\ql \li2880\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin2880\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext51 DescContinue 8;}{ +\s51\ql \li3240\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin3240\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext51 DescContinue 9;}{\s52\ql \li0\ri0\sb30\sa30\widctlpar +\tqr\tldot\tx8640\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 \sbasedon0 \snext63 LatexTOC 0;}{\s53\ql \li360\ri0\sb27\sa27\widctlpar +\tqr\tldot\tx8640\wrapdefault\faauto\adjustright\rin0\lin360\itap0 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+08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003200340039000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 4}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 +\par Module Documentation\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 PAGEREF _Toc211937250 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003200350030000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 5}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 +\par }\pard\plain \ltrpar\s83\ql \li200\ri0\widctlpar\tqr\tldot\tx8630\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3 Driver Interface Definition\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 PAGEREF _Toc211937251 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003200350031000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 5}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 +\par EDMA3 Driver Usage Guidelines\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 PAGEREF _Toc211937252 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003200350032000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 9}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 +\par EDMA3 Driver Error Codes\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 PAGEREF _Toc211937253 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003200350033000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 9}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 +\par EDMA3 Driver Channel Setup\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 PAGEREF _Toc211937254 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003200350034000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 17}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 +\par EDMA3 Driver Typical EDMA Transfer Setup\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 PAGEREF _Toc211937255 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003200350035000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 27}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 +\par EDMA3 Driver Optional Setup for EDMA\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 PAGEREF _Toc211937256 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003200350036000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 41}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 +\par Internal Interface Definition for EDMA3 Driver\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 PAGEREF _Toc211937257 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 +{\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003200350037000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 53}}}\sectd +\pgnlcrm\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 +\par Boundary Values\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 PAGEREF _Toc211937258 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003200350038000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 61}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 +\par Object Maintenance\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 PAGEREF _Toc211937259 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003200350039000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 62}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 +\par }\pard\plain \ltrpar\s82\ql \li0\ri0\widctlpar\tqr\tldot\tx8630\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Data Structure Documentation\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 PAGEREF _Toc211937260 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003200360030000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 64}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 +\par }\pard\plain \ltrpar\s83\ql \li200\ri0\widctlpar\tqr\tldot\tx8630\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_ChainOptions\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 PAGEREF _Toc211937261 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003200360031000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 64}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 +\par EDMA3_DRV_ChBoundResources\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 PAGEREF _Toc211937262 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003200360032000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 65}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 +\par EDMA3_DRV_EvtQuePriority\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 PAGEREF _Toc211937263 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003200360033000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 67}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 +\par EDMA3_DRV_GblConfigParams\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 PAGEREF _Toc211937264 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003200360034000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 68}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 +\par EDMA3_DRV_InitConfig\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 PAGEREF _Toc211937265 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003200360035000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 72}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 +\par EDMA3_DRV_Instance\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 PAGEREF _Toc211937266 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003200360036000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 74}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 +\par EDMA3_DRV_InstanceInitConfig\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 PAGEREF _Toc211937267 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003200360037000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 76}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 +\par EDMA3_DRV_MiscParam\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 PAGEREF _Toc211937268 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003200360038000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 79}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 +\par EDMA3_DRV_Object\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 PAGEREF _Toc211937269 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003200360039000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 80}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 +\par EDMA3_DRV_ParamentryRegs\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 PAGEREF _Toc211937270 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003200370030000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 82}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 +\par EDMA3_DRV_PaRAMRegs\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 PAGEREF _Toc211937271 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003200370031000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 84}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 +\par }\pard\plain \ltrpar\s82\ql \li0\ri0\widctlpar\tqr\tldot\tx8630\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 File Documentation\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 PAGEREF _Toc211937272 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003200370032000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 86}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 +\par }\pard\plain \ltrpar\s83\ql \li200\ri0\widctlpar\tqr\tldot\tx8630\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 edma3.h\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 PAGEREF _Toc211937273 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 +{\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003200370033000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 86}}}\sectd +\pgnlcrm\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 +\par edma3_drv.h\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 PAGEREF _Toc211937274 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003200370034000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 89}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 +\par edma3_drv_adv.c\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 PAGEREF _Toc211937275 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003200370035000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 96}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 +\par edma3_drv_basic.c\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 PAGEREF _Toc211937276 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003200370036000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 100}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 +\par edma3_drv_init.c\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 PAGEREF _Toc211937277 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003200370037000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 104}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 +\par }\pard\plain \ltrpar\s82\ql \li0\ri0\widctlpar\tqr\tldot\tx8630\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Index\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 PAGEREF _Toc211937278 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 +{\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003200370038000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 107}}}\sectd +\pgnlcrm\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 }}\pard\plain \ltrpar +\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 \sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid6424133 +\par \sect }\sectd \ltrsect\pgnrestart\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 \sect }\sectd \ltrsect\sbknone\linex0\sectdefaultcl\sftnbj {\footerr \ltrpar \pard\plain \ltrpar\s20\qr \li0\ri0\widctlpar\tqc\tx4320\tqr\tx8640\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \chpgn +\par }}\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 \sect +}\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s1\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs36\alang1025 \ltrch\fcs0 +\b\f1\fs36\lang1033\langfe1033\kerning36\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Module Index +\par }\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 +{\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\tc { +\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 {\*\bkmkstart _Toc211937247}Module Index{\*\bkmkend _Toc211937247}}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Modules +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Here is a list of all modules:}{\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s53\ql \li360\ri0\sb27\sa27\widctlpar\tqr\tldot\tx8640\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 EDMA3 Driver Interface Definition\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 PAGEREF AAAAAAAABI \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 5}}} +\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s54\ql \li720\ri0\sb24\sa24\widctlpar\tqr\tldot\tx8640\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 EDMA3 Driver Usage Guidelines\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 PAGEREF AAAAAAAABP \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 9}}} +\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3 Driver Error Codes\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 PAGEREF AAAAAAAABQ \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 9}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3 Driver Channel Setup\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 PAGEREF AAAAAAAACJ \\ +*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 17}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3 Driver Typical EDMA Transfer Setup\tab }{\field{\*\fldinst { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 PAGEREF AAAAAAAAFO \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 27}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3 Driver Optional Setup for EDMA\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 PAGEREF AAAAAAAAHW \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 41}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s53\ql \li360\ri0\sb27\sa27\widctlpar\tqr\tldot\tx8640\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 Internal Interface Definition for EDMA3 Driver\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 PAGEREF AAAAAAAAJN \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 53}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s54\ql \li720\ri0\sb24\sa24\widctlpar\tqr\tldot\tx8640\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 Boundary Values\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 PAGEREF AAAAAAAALU \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 61}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Object Maintenance\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 PAGEREF AAAAAAAAMB \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 62}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s53\ql \li360\ri0\sb27\sa27\widctlpar\tqr\tldot\tx8640\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 \sect +}\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s1\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs36\alang1025 \ltrch\fcs0 +\b\f1\fs36\lang1033\langfe1033\kerning36\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Data Structure Index +\par }\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 +{\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\tc { +\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 {\*\bkmkstart _Toc211937248}Data Structure Index{\*\bkmkend _Toc211937248}}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Data Structures +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Here are the data structures with brief descriptions:}{\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s53\ql \li360\ri0\sb27\sa27\widctlpar\tqr\tldot\tx8640\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ChainOptions (Structure to be used to configure interrupt generation and chaining options )}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +PAGEREF AAAAAAAAMH \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 64}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ChBoundResources (EDMA3 Channel-Bound resources )}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 PAGEREF AAAAAAAAMI \\ +*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 65}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_EvtQuePriority (Event queue priorities setup )}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 PAGEREF AAAAAAAAMJ \\ +*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 67}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_GblConfigParams (Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information )}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \tab }{\field{\*\fldinst { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 PAGEREF AAAAAAAAMK \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 68}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 + +\par }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_InitConfig (Used to Initialize the EDMA3 Driver Instance )}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +PAGEREF AAAAAAAAML \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 72}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_Instance (EDMA3 Driver Instance Configuration Structure )}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +PAGEREF AAAAAAAAMM \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 74}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_InstanceInitConfig (Init-time Region Specific Configuration structure for EDMA3 Driver, to provide region specific Information )}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \tab } +{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 PAGEREF AAAAAAAAMN \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 76}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 +\par }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_MiscParam (Used to specify the miscellaneous options during EDMA3 Driver Initialization )}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 PAGEREF AAAAAAAAMO \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 79}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_Object (EDMA3 Driver Object (HW Specific) Maintenance structure )}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +PAGEREF AAAAAAAAMP \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 80}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ParamentryRegs (EDMA3 PaRAM Set )}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 PAGEREF AAAAAAAAMQ \\*MERGEFORMAT} +}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 82}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PaRAMRegs (EDMA3 Parameter RAM Set in User Configurable format )}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +PAGEREF AAAAAAAAMR \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 84}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 \sect +}\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s1\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs36\alang1025 \ltrch\fcs0 +\b\f1\fs36\lang1033\langfe1033\kerning36\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 File Index +\par }\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 +{\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\tc { +\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 {\*\bkmkstart _Toc211937249}File Index{\*\bkmkend _Toc211937249}}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 File List +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Here is a list of all documented files with brief descriptions:}{\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s53\ql \li360\ri0\sb27\sa27\widctlpar\tqr\tldot\tx8640\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid6424133 edma3.h (EDMA3 Driver Internal header file )}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 PAGEREF AAAAAAAAAA \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 +\af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 86}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 edma3_drv.h (EDMA3 Controller )}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 PAGEREF AAAAAAAAAB \\*MERGEFORMAT}}{\fldrslt { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 89}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 +edma3_drv_adv.c (EDMA3 Driver Advanced Interface Implementation This file contains advanced-level EDMA3 Driver APIs which are required to: a) Link and chain two channels. b) Set/get the whole PaRAM Set in one shot +. c) Set/get each individual field of the PaRAM Set. d) Poll mode APIs. e) IOCTL interface. These APIs are provided to have complete control on the EDMA3 hardware and normally advanced users are expected to use them for their specific use-cases )}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 PAGEREF AAAAAAAAAC \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 96}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 +edma3_drv_basic.c (EDMA3 Driver Basic Interface Implementation This file contains beginner-level EDMA3 Driver APIs which are required to: a) Request/free a DMA, QDMA and Link channel. b) Program various fields in the PaRA +M Set like source/destination parameters, transfer parameters etc. c) Enable/disable a transfer. These APIs are provided to program a DMA/QDMA channel for simple use-cases and don't expose all the features of EDMA3 hardware. Users who want to go beyond th +is and have complete control on the EDMA3 hardware are advised to refer edma3_drv_adv.c source file )}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 PAGEREF AAAAAAAAAM \\*MERGEFORMAT} +}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 100}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 edma3_drv_init.c (EDMA3 Driver Initialization Interface Implementation This file contains EDMA3 Driver APIs use +d to: a) Create/delete EDMA3 Driver Object b) Open/close EDMA3 Driver Instance. These APIs are required to initialize EDMA3 properly )}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +PAGEREF AAAAAAAAAX \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 104}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 \sect +}\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s1\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs36\alang1025 \ltrch\fcs0 +\b\f1\fs36\lang1033\langfe1033\kerning36\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Module Documentation}{\pard\plain \ltrpar +\s1\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs36\alang1025 \ltrch\fcs0 \b\v\f1\fs36\lang1033\langfe1033\kerning36\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 {\*\bkmkstart _Toc211937250}Module Documentation{\*\bkmkend _Toc211937250}}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3 Driver Interface Definition +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 \tcl2{\*\bkmkstart _Toc211937251}EDMA3 Driver Interface Definition{\*\bkmkend _Toc211937251}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3 Driver Interface Definition}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAABI}{\*\bkmkend AAAAAAAABI}Modules +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 +EDMA3 Driver Usage Guidelines}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3 Driver Error Codes}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Usage of EDMA3 Driver. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3 Driver Channel Setup}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3 Driver Typical EDMA Transfer Setup}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3 Driver Optional Setup for EDMA}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Data Structures +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_GblConfigParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_InstanceInitConfig}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Init-time Region Specific Configuration structure for EDMA3 Driver, to provide region specific Information. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_InitConfig}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Used to Initialize the EDMA3 Driver Instance. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_MiscParam}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Used to specify the miscellaneous options during EDMA3 Driver Initialization. +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Defines +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define } +{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_CH_NO_PARAM_MAP}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \~ EDMA3_RM_CH_NO_PARAM_MAP +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_CH_NO_TCC_MAP}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ EDMA3_RM_CH_NO_TCC_MAP +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Functions +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_create}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (unsigned int phyCtrllerInstId, const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_GblConfigParams}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 *gblCfgParams, const void *miscParam) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Create EDMA3 Driver Object. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_delete}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (unsigned int phyCtrllerInstId, const void *param) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Delete EDMA3 Driver Object. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Handle }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_open}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (unsigned int phyCtrllerInstId, const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_InitConfig}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 *initCfg, EDMA3_DRV_Result *errorCode) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Open EDMA3 Driver Instance. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_close}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, const void *param) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Close the EDMA3 Driver Instance. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 Top-level Encapsulation of all documentation for EDMA3 Driver +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Define Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 EDMA3_DRV_CH_NO_PARAM_MAP\:Edma3DrvMain}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 Edma3DrvMain\:EDMA3_DRV_CH_NO_PARAM_MAP}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_CH_NO_PARAM_MAP\~ EDMA3_RM_CH_NO_PARAM_MAP +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAABJ}{\*\bkmkend AAAAAAAABJ} +This define is used to specify that a DMA channel is NOT tied to any PaRAM Set and hence any available PaRAM Set could be used for that DMA channel. It could be used in dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH], in global configuration structure + EDMA3_RM_GblConfigParams. +\par This value should mandatorily be used to mark DMA channels with no initial mapping to specific PaRAM Sets. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_requestChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_CH_NO_TCC_MAP\:Edma3DrvMain}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvMain\:EDMA3_DRV_CH_NO_TCC_MAP}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_CH_NO_TCC_MAP\~ EDMA3_RM_CH_NO_TCC_MAP +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAABK}{\*\bkmkend AAAAAAAABK}This define is used to specify that the DMA/QDMA channel is not tied to any TCC and hence any available TCC could be used for that DMA/QDMA channel. It co +uld be used in dmaChannelTccMap [EDMA3_MAX_DMA_CH], in global configuration structure EDMA3_RM_GblConfigParams. +\par This value should mandatorily be used to mark DMA channels with no initial mapping to specific TCCs. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_requestChannel(). +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Function Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 EDMA3_DRV_close\:Edma3DrvMain}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 Edma3DrvMain\:EDMA3_DRV_close}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result EDMA3_DRV_close (EDMA3_DRV_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , const void * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 param}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAABL}{\*\bkmkend AAAAAAAABL}Close the EDMA3 Driver Instance. +\par This API is used to close a previously opened EDMA3 Driver Instance. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Handle to the previously opened EDMA3 Driver Instance. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 param}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] For possible future use +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_SOK or EDMA3_DRV Error code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 This function disables the global interrupts (by calling API edma3OsProtectEntry with protection level EDMA3_OS_PROTECT_INTERRUPT) while modifying the global data structures, to make it re-entrant. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 References EDMA3_DRV_Instance::drvInstInitConfig, EDMA3_DRV_CLOSED, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_ +E_OBJ_NOT_OPENED, EDMA3_DRV_E_RM_CLOSE_FAIL, EDMA3_DRV_OPENED, edma3MemSet(), EDMA3_DRV_Object::numOpens, EDMA3_DRV_Instance::pDrvObjectHandle, EDMA3_DRV_Instance::resMgrInstance, EDMA3_DRV_Instance::shadowRegs, and EDMA3_DRV_Object::state. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_create\:Edma3DrvMain}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvMain\:EDMA3_DRV_create}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result EDMA3_DRV_create (unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 phyCtrllerInstId}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , const EDMA3_DRV_GblConfigParams * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 +gblCfgParams}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , const void * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 miscParam}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAABM}{\*\bkmkend AAAAAAAABM}Create EDMA3 Driver Object. +\par This API is used to create the EDMA3 Driver Object. It should be called only ONCE for each EDMA3 hardware instance. +\par Init-time Configuration structure for EDMA3 hardware is provided to pass the SoC specific information. This configuration information could be provi +ded by the user at init-time. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3__cfg.c, in case it is available. +\par This API clears the error specific registers (EMCR/EMCRh, QEMCR, CCERRC +LR) and sets the TCs priorities and Event Queues' watermark levels, if the 'miscParam' argument is NULL. User can avoid these registers' programming (in some specific use cases) by SETTING the 'isSlave' field of 'EDMA3_RM_MiscParam' configuration structur +e and passing this structure as the third argument (miscParam). +\par After successful completion of this API, Driver Object's state changes to EDMA3_DRV_CREATED from EDMA3_DRV_DELETED. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid6424133 phyCtrllerInstId}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] EDMA3 Controller Instance Id (Hardware instance id, starting from 0). +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 gblCfgParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] SoC specific configuration structure for the EDMA3 Hardware. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 miscParam}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Misc configuration options provided in the structure 'EDMA3_DRV_MiscParam'. For default options, user can pass NULL in this argument. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_SOK or EDMA3_DRV Error code +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Used to reset the Internal EDMA3 Driver Data Structures for the first time. +\par We are NOT checking 'gblCfgParams' for NULL. Whatever user has passed is given to RM. If user passed NULL, config info from config file will be taken else user specific info will be passed to the RM. Similarly, 'miscParam' is not being checked and passed +as it is to the Resource Manager layer. +\par Copy the global config info from the RM object to the driver object for future use. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 References EDMA3_DRV_CREATED, EDMA3_DRV_DELETED, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_E_OBJ_NOT_DELETED, EDMA3_DRV_TRIG_MODE_NONE, e +dma3MemCpy(), edma3MemSet(), EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_Object::numOpens, EDMA3_DRV_GblConfigParams::numRegions, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Object::phyCtrllerInstId, resMgrObj, EDMA3_DRV_Object::state, EDMA3_DRV_ChBoundR +esources::tcc, and EDMA3_DRV_ChBoundResources::trigMode. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_delete\:Edma3DrvMain}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvMain\:EDMA3_DRV_delete}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result EDMA3_DRV_delete (unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 phyCtrllerInstId}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , const void * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 param}{\rtlch\fcs1 +\af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAABN}{\*\bkmkend AAAAAAAABN}Delete EDMA3 Driver Object. +\par Use this API to delete the EDMA3 Driver Object. It should be called only ONCE for each EDMA3 hardware instance. It should be called ONLY after closing all the EDMA3 Driver Instances. +\par This API is used to delete the EDMA3 Driver Object. It should be called once for each EDMA3 hardware instance, ONLY after closing all the previously opened EDMA3 Driver Instances. +\par After successful completion of this API, Driver Object's state changes to EDMA3_DRV_DELETED. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid6424133 phyCtrllerInstId}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] EDMA3 Phy Controller Instance Id (Hardware instance id, starting from 0). +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 param}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] For possible future use. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_SOK or EDMA3_DRV Error code +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 If number of Driver Instances is 0, then state should be EDMA3_DRV_CLOSED OR EDMA3_DRV_CREATED. +\par If number of Driver Instances is NOT 0, then this function SHOULD NOT be called by anybody. +\par State is correct. Delete the RM Object. +\par Change state to EDMA3_DRV_DELETED +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 References EDMA3_DRV_CLOSED, EDMA3_DRV_CREATED, EDMA3_DRV_DELETED, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_E_INVALID_STATE, EDMA3_DRV_E_OBJ_NOT_CLOSED, edma3MemSet(), and EDMA3_DRV_Object::state. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_open\:Edma3DrvMain}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvMain\:EDMA3_DRV_open}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Handle EDMA3_DRV_open (unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 phyCtrllerInstId}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , const EDMA3_DRV_InitConfig * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 initCfg}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , EDMA3_DRV_Result * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 errorCode}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAABO}{\*\bkmkend AAAAAAAABO}Open EDMA3 Driver Instance. +\par This API is used to open an EDMA3 Driver Instance. It could be called multiple times, for each possible EDMA3 shadow region. Maximum EDMA3_MAX_REGIONS instances are allo +wed for each EDMA3 hardware instance. Multiple instances on the same shadow region are NOT allowed. +\par Also, only ONE Master Driver Instance is permitted. This master instance (and hence the region to which it belongs) will only receive the EDMA3 interrupts, if enabled. +\par User could pass the instance specific configuration structure (initCfg.drvInstInitConfig) as a part of the 'initCfg' structure, during init-time. In case user doesn't provide it, this information could be taken from the SoC specific configurati +on file edma3__cfg.c, in case it is available. +\par By default, this EDMA3 Driver instance will clear the PaRAM Sets while allocating them. To change the default behavior, user should use the IOCTL interface appropriately. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid6424133 phyCtrllerInstId}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] EDMA3 Controller Instance Id (Hardware instance id, starting from 0). +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 initCfg}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Used to Initialize the EDMA3 Driver Instance (Master or Slave). +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 errorCode}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [OUT] Error code while opening DRV instance. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Handle : If successfully opened, the API will return the associated driver's instance handle. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 This function disables the global interrupts (by calling API edma3OsProtectEntry with protection level EDMA3_OS_PROTECT_INTERRUPT) while modifying the global data structures, to make it re-entrant. +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +This API is used to open an EDMA3 Driver Instance. It could be called multiple times, for each possible EDMA3 shadow region. Maximum EDMA3_MAX_REGIONS instances are allowed for each EDMA3 hardware instance. Multiple instances on the same sha +dow region are NOT allowed. +\par Also, only ONE Master Driver Instance is permitted. This master instance (and hence the region to which it belongs) will only receive the EDMA3 interrupts, if enabled. +\par User could pass the instance specific configuration structur +e (initCfg.drvInstInitConfig) as a part of the 'initCfg' structure, during init-time. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3__cfg.c, in case it is available. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid6424133 phyCtrllerInstId}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] EDMA3 Controller Instance Id (Hardware instance id, starting from 0). +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 initCfg}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Used to Initialize the EDMA3 Driver Instance (Master or Slave). +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 errorCode}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [OUT] Error code while opening DRV instance. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Handle : If successfully opened, the API will return the associated driver's instance handle. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 This function disables the global interrupts (by calling API edma3OsProtectEntry with protection level EDMA3_OS_PROTECT_INTERRUPT) while modifying the global data structures, to make it re-entrant. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +References EDMA3_DRV_Instance::drvInstInitConfig, EDMA3_DRV_InitConfig::drvInstInitConfig, EDMA3_DRV_Instance::drvSemHandle, EDMA3_DRV_InitConfig::drvSemHandle, EDMA3_DRV_CLOSED, EDMA3_DRV_CREATED, EDMA3_DRV_E_INST_ALREADY_EXIS +TS, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_E_INVALID_STATE, EDMA3_DRV_OPENED, edma3MemCpy(), edma3OpenResMgr(), EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_InitConfig::gblerrCb, EDMA3_DRV_Instance::gblerrCbParams, EDMA3_DRV_InitConfig::gblerrData, EDMA3_DRV_G +b +lConfigParams::globalRegs, EDMA3_DRV_InitConfig::isMaster, EDMA3_DRV_Instance::isMaster, EDMA3_DRV_Object::numOpens, EDMA3_DRV_GblConfigParams::numRegions, EDMA3_DRV_Instance::pDrvObjectHandle, EDMA3_DRV_Instance::regionId, EDMA3_DRV_InitConfig::regionId, + EDMA3_DRV_Instance::shadowRegs, and EDMA3_DRV_Object::state. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3 Driver Usage Guidelines +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc { +\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 \tcl2{\*\bkmkstart _Toc211937252}EDMA3 Driver Usage Guidelines{\*\bkmkend _Toc211937252}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 +\ltrch\fcs0 \fs24\insrsid6424133 EDMA3 Driver Usage Guidelines}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAABP}{\*\bkmkend AAAAAAAABP}Guidelines for typical usage of EDMA3 Driver. +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 +\ltrch\fcs0 \fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3 Driver Error Codes +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc { +\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 \tcl2{\*\bkmkstart _Toc211937253}EDMA3 Driver Error Codes{\*\bkmkend _Toc211937253}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn +\pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 EDMA3 Driver Error Codes}}} +\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAABQ}{\*\bkmkend AAAAAAAABQ}Usage of EDMA3 Driver. +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Defines +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define } +{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_E_BASE}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \~ (-128) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_E_OBJ_NOT_DELETED}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_E_BASE) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_E_OBJ_NOT_CLOSED}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_E_BASE-1) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_E_OBJ_NOT_OPENED}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_E_BASE-2) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_E_RM_CLOSE_FAIL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_E_BASE-3) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_E_BASE-4) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_E_BASE-5) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_E_PARAM_SET_UNAVAIL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_E_BASE-6) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_E_TCC_UNAVAIL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_E_BASE-7) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_E_TCC_REGISTER_FAIL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_E_BASE-8) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_E_CH_PARAM_BIND_FAIL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_E_BASE-9) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_E_ADDRESS_NOT_ALIGNED}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_E_BASE-10) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_E_INVALID_PARAM}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_E_BASE-11) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_E_INVALID_STATE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_E_BASE-12) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_E_INST_ALREADY_EXISTS}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_E_BASE-13) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_E_BASE-14) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_E_SEMAPHORE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_E_BASE-15) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_E_INST_NOT_OPENED}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_E_BASE-16) +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Usage of EDMA3 Driver. +\par +\par }\pard\plain \ltrpar\s72\ql \fi-360\li360\ri0\widctlpar\wrapdefault\faauto\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 1.\tab +Create EDMA3 Driver Object (one for each EDMA3 hardware instance) +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result result = EDMA3_DRV_SOK; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 unsigned int edma3HwInstanceId = 0; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_GblConfigParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 *gblCfgParams = NULL; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. This could be NULL also. In that case, static configuration will be taken. +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 result = EDMA3_DRV_create (edma3HwInstanceId, gblCfgParams, NULL); +\par }\pard\plain \ltrpar\s72\ql \fi-360\li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s72\ql \fi-360\li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 1.\tab Open EDMA3 driver Instance +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Steps + +\par {\pntext\pard\plain\ltrpar \s64 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s64\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin1080\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 +EDMA3_DRV_InitConfig}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 initCfg; +\par {\pntext\pard\plain\ltrpar \s64 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s64\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Handle hEdma = NULL; +\par {\pntext\pard\plain\ltrpar \s64 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s64\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_OS_SemAttrs semAttrs = \{EDMA3_OS_SEMTYPE_FIFO, NULL\}; +\par {\pntext\pard\plain\ltrpar \s64 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s64\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Result edmaResult; -To get the error code while opening driver instance +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s72\ql \fi-360\li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s72\ql \fi-360\li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 1.\tab initCfg.regionId = One of the possible regions available for eg, (EDMA3_RM_RegionId)0 or (EDMA3_RM_RegionId)1 etc, for different masters. +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s72\ql \fi-360\li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 1.\tab initCfg.isMaster = TRUE/FALSE (Whether this EDMA3 DRV instance is Master or not. The EDMA3 Shadow Region tied to the Master DRV Instance will ONLY receive the EDMA3 interrupts (error or completion), if enabled). +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s72\ql \fi-360\li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 1.\tab initCfg.drvSemHandle = EDMA3 DRV Instance specific semaphore handle. It should be provided by the user for proper sharing of resources. +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +edma3Result = edma3OsSemCreate(1, &semAttrs, &initCfg.drvSemHandle); +\par }\pard\plain \ltrpar\s72\ql \fi-360\li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s72\ql \fi-360\li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 1.\tab +initCfg.drvInstInitConfig = Init-time Region Specific Configuration Structure. It can be provided by the user at run-time. If not provided by the user, this info would be taken from the platform specific config file, if it exists. +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s72\ql \fi-360\li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 1.\tab initCfg.drvInstInitConfig->ownDmaChannels[] = The bitmap(s) which indicate the DMA channels owned by this instance of the EDMA3 Driver +\par E.g. A '1' at bit position 24 indicates that this instance of the EDMA3 Driver owns DMA Channel Id 24 +\par Later when a request is made based on a particular Channel Id, the EDMA3 Driver will check first if it owns that channel. If it doesnot own it, EDMA3 Driver returns error. +\par 2.\tab initCfg.drvInstInitConfig->ownQdmaChannels[] = The bitmap(s) which indicate the QDMA channels owned by this instance of the EDMA3 Driver +\par 3.\tab initCfg.drvInstInitConfig->ownPaRAMSets[] = The bitmap(s) which indicate the PaRAM Sets owned by this instance of the EDMA3 Driver +\par 4.\tab initCfg.drvInstInitConfig->ownTccs[] = The bitmap(s) which indicate the TCCs owned by this instance of the EDMA3 Driver +\par +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s72\ql \fi-360\li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 1.\tab initCfg.drvInstInitConfig->resvdDmaChannels[] = The bitmap(s) which indicate the DMA channels reserved by this instance of the EDMA3 Driver +\par E.g. A '1' at bit position 24 indicates that this instance of the EDMA3 Driver reserves Channel Id 24 +\par These channels are reserved and may be mapped to HW events, these are not given to 'EDMA3_DRV_DMA_CHANNEL_ANY' requests. +\par 2.\tab initCfg.drvInstInitConfig->resvdQdmaChannels[] = The bitmap(s) which indicate the QDMA channels reserved by this instance of the EDMA3 Driver +\par E.g. A '1' at bit position 1 indicates that this instance of the EDMA3 Driver reserves QDMA Channel Id 1 +\par These channels are reserved for some specific purpose, these are not given to 'EDMA3_DRV_QDMA_CHANNEL_ANY' request +\par 3.\tab initCfg.drvInstInitConfig->resvdPaRAMSets[] = PaRAM Sets which are reserved by this Region; +\par 4.\tab initCfg.drvInstInitConfig->resvdTccs[] = TCCs which are reserved by this Region; +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s72\ql \fi-360\li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 1.\tab initCfg.gblerrCb = Instance wide callback function to catch non-channel specific errors; +\par 2.\tab initCfg.gblerrData = Application data to be passed back to the callback function; +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s72\ql \fi-360\li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 1.\tab hEdma = EDMA3_DRV_open(edma3HwInstanceId, &initCfg, &edmaResult); +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s72\ql \fi-360\li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 1.\tab EDMA3 driver APIs +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_RM_ResDesc resObj; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Result result; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 unsigned int ch1Id = 0; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 unsigned int ch2Id = 0; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 unsigned int tcc1 = 0; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 unsigned int tcc2 = 0; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 unsigned int qCh1Id = 0; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 unsigned int qTcc1 = 0; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 unsigned int qCh2Id = 0; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 unsigned int qTcc2 = 0; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 unsigned int paRAMId; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 int srcbidx = 0; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 int desbidx = 0; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 int srccidx = 0; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 int descidx = 0; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 unsigned int acnt = 0; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 unsigned int bcnt = 0; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 unsigned int ccnt = 0; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 unsigned int bcntreload = 0; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_SyncType synctype; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_RM_TccCallback tccCb; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 void *cbData; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Use Case 1: Memory to memory transfer on any available +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 DMA Channel +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s64 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s64\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin1080\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +tcc1 = EDMA3_DRV_TCC_ANY; +\par {\pntext\pard\plain\ltrpar \s64 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s64\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 ch1Id = EDMA3_DRV_DMA_CHANNEL_ANY; +\par {\pntext\pard\plain\ltrpar \s64 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s64\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 result = EDMA3_DRV_requestChannel (hEdma, &ch1Id, &tcc1, (EDMA3_RM_EventQueue)0, &callback1, NULL); +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s72\ql \fi-360\li360\ri0\widctlpar\wrapdefault\faauto\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +result = EDMA3_DRV_setSrcParams (hEdma, ch1Id, (unsigned int)(srcBuff1), EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_W8BIT); +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +result = EDMA3_DRV_setDestParams (hEdma, ch1Id, (unsigned int)(dstBuff1), EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_W8BIT); +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Set EDMA transfer parameters (aCnt, bCnt, cCnt, bCntReload, SyncType) acnt = 256; bcnt = 1; ccnt = 1, bcntreload = 0; synctype = EDMA3_DRV_SYNC_A; +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 result = EDMA3_DRV_setTransferParams (hEdma, ch1Id, acnt, bcnt, ccnt, bcntreload, synctype); +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Set srcbidx and srccidx to the appropriate values +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 srcbidx = acnt; srccidx = acnt; +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 result = EDMA3_DRV_setSrcIndex (hEdma, ch1Id, srcbidx, srccidx); +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Set desbidx and descidx to the appropriate values +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 desbidx = acnt; descidx = acnt; +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 result = EDMA3_DRV_setDestIndex (hEdma, ch1Id, desbidx, descidx); +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Enable the final completion interrupt. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 result = EDMA3_DRV_setOptField (hEdma, ch1Id, EDMA3_DRV_OPT_FIELD_TCINTEN, 1); +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Enable the transfer +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 result = EDMA3_DRV_enableTransfer (hEdma, ch1Id, EDMA3_DRV_TRIG_MODE_MANUAL); +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Use Case 2: Linked memory to memory transfer on any available +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 DMA Channel +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Perform steps as for Use Case 1 for the Master logical channel ch1Id for configuration. DONOT enable the transfer for ch1Id. +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Configure link channel, ch2Id. +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 tcc2 = EDMA3_DRV_TCC_ANY; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 ch2Id = EDMA3_DRV_LINK_CHANNEL; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 result = EDMA3_DRV_requestChannel (hEdma, &ch2Id, &tcc2, (EDMA3_RM_EventQueue)0, &callback2, NULL); +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +result = EDMA3_DRV_setSrcParams (hEdma, ch2Id, (unsigned int)(srcBuff2), EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_W8BIT); +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +result = EDMA3_DRV_setDestParams (hEdma, ch2Id,( unsigned int)(dstBuff2), EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_W8BIT); +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +result = EDMA3_DRV_setSrcIndex (hEdma, ch2Id, srcbidx, srccidx); +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 result = EDMA3_DRV_setDestIndex (hEdma, ch2Id, desbidx, descidx); +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +result = EDMA3_DRV_setTransferParams (hEdma, ch2Id, acnt, bcnt, ccnt, bcntreload, synctype); +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Link both the channels +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 result = EDMA3_DRV_linkChannel (hEdma, ch1Id, ch2Id); +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Enable the final completion interrupts on both the channels +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 result = EDMA3_DRV_setOptField (hEdma, ch1Id, EDMA3_DRV_OPT_FIELD_TCINTEN, 1); +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 result = EDMA3_DRV_setOptField (hEdma, ch2Id, EDMA3_DRV_OPT_FIELD_TCINTEN, 1); +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Enable the transfer on channel 1. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 result = EDMA3_DRV_enableTransfer (hEdma, ch1Id, EDMA3_DRV_TRIG_MODE_MANUAL); +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Wait for +the completion interrupt on Ch1 and then enable the transfer again for the LINK channel, to provide the required sync event. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 result = EDMA3_DRV_enableTransfer (hEdma, ch1Id, EDMA3_DRV_TRIG_MODE_MANUAL); +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Note: Enabling of transfers on channel 1 (for master and link channel) is required as many number of times as the sync events are required. For ASync mode, number of sync events=(bcnt * ccnt) and for ABSync mode, number of sync events = ccnt. +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Use Case 3: Memory to memory transfer on any available +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 QDMA Channel +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +qTcc1 = EDMA3_DRV_TCC_ANY; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 qCh1Id = EDMA3_DRV_QDMA_CHANNEL_ANY; +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +result = EDMA3_DRV_requestChannel (hEdma, &qCh1Id, &qTcc1, (EDMA3_RM_EventQueue)0, &callback1, NULL); +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Set the QDMA trigger word. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 result = EDMA3_DRV_setQdmaTrigWord (hEdma, qCh1Id, EDMA3_RM_QDMA_TRIG_DST); +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Note: DONOT write the destination address (trigger word) before completing the configuration as it will trigger the transfer. Also, DONOT use }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setDestParams()}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 to set the destination address as it also sets other parameters. Use }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setPaRAMEntry()}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 to set the destination address +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +result = EDMA3_DRV_setSrcParams (hEdma, qCh1Id, (unsigned int)(srcBuff1), EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_W8BIT); +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Set QDMA transfer parameters (aCnt, bCnt, cCnt, bCntReload, SyncType) acnt = 256; bcnt = 1; ccnt = 1, bcntreload = 0; synctype = EDMA3_DRV_SYNC_A; +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 result = EDMA3_DRV_setTransferParams (hEdma, qCh1Id, acnt, bcnt, ccnt, bcntreload, synctype); +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +srcbidx = acnt; srccidx = acnt; desbidx = acnt; descidx = acnt; +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 result = EDMA3_DRV_setSrcIndex (hEdma, qCh1Id, srcbidx, srccidx); +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 result = EDMA3_DRV_setDestIndex (hEdma, qCh1Id, desbidx, descidx); +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Enable the final completion interrupt. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 result = EDMA3_DRV_setOptField (hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_TCINTEN, 1); +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Set the Destination Addressing Mode as Increment +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 result = EDMA3_DRV_setOptField (hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_DAM, EDMA3_DRV_ADDR_MODE_INCR); +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Trigger the QDMA channel by writing the destination address +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 result = EDMA3_DRV_setPaRAMEntry (hEdma, qCh1Id, EDMA3_DRV_PARAM_ENTRY_DST, (unsigned int)(dstBuff1)); +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Use Case 4: Linked memory to memory transfer on any available +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 QDMA Channel +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Setup for any QDMA Channel +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 qTcc1 = EDMA3_DRV_TCC_ANY; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 qCh1Id = EDMA3_DRV_QDMA_CHANNEL_ANY; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 result = EDMA3_DRV_requestChannel (hEdma, &qCh1Id, &qTcc1, (EDMA3_RM_EventQueue)0, &callback1, NULL); +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Setup for Channel 2 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 qCh2Id = EDMA3_DRV_LINK_CHANNEL; +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 qTcc2 = EDMA3_DRV_TCC_ANY; +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 result = EDMA3_DRV_requestChannel (hEdma, &qCh2Id, &qTcc2, (EDMA3_RM_EventQueue)0, &callback2, NULL); +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +result = EDMA3_DRV_setSrcParams (hEdma, qCh2Id, (unsigned int)(srcBuff2), EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_W8BIT); +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 result = EDMA3_DRV_setDestParams(hEdma, qCh2Id, (unsigned int)(dstBuff2), EDMA3_DRV_ADDR_MODE_INCR, EDMA3_D +RV_W8BIT); +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +acnt = 256; bcnt = 1; ccnt = 1, bcntreload = 0; synctype = EDMA3_DRV_SYNC_A; +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 result = EDMA3_DRV_setTransferParams (hEdma, qCh2Id, acnt, bcnt, ccnt, BRCnt, EDMA3_DRV_SYNC_A); +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +srcbidx = acnt; srccidx = acnt; desbidx = acnt; descidx = acnt; +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 result = EDMA3_DRV_setSrcIndex (hEdma, qCh2Id, srcbidx, srccidx); +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 result = EDMA3_DRV_setDestIndex (hEdma, qCh2Id, desbidx, descidx); +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +result = EDMA3_DRV_setOptField (hEdma, qCh2Id, EDMA3_DRV_OPT_FIELD_TCINTEN, 1); +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Make the PaRAM Set associated with qCh2Id as Static +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 result = EDMA3_DRV_setOptField (hEdma, qCh2Id, EDMA3_DRV_OPT_FIELD_STATIC, 1u); +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Link both the channels +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 result = EDMA3_DRV_linkChannel (hEdma,qCh1Id,qCh2Id); +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Set the QDMA trigger word. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 result = EDMA3_DRV_setQdmaTrigWord (hEdma, qCh1Id, EDMA3_DRV_QDMA_TRIG_DST); +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Note: DONOT write the destination address (trigger word) before completing the configuration as it'll trigger the transfer. Also, DONOT use EDMA3_DRV_setDestParams () function to set the destination address as it also sets other parameters. Use }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setPaRAMEntry()}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 to set the dest address. +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +result = EDMA3_DRV_setSrcParams (hEdma, qCh1Id, (unsigned int)(srcBuff1), EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_W8BIT); +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Set QDMA transfer parameters (aCnt, bCnt, cCnt, bCntReload, SyncType) acnt = 256; bcnt = 1; ccnt = 1, bcntreload = 0; synctype = EDMA3_DRV_SYNC_A; +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 result = EDMA3_DRV_setTransferParams (hEdma, qCh1Id, acnt, bcnt, ccnt, bcntreload, synctype); +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +srcbidx = acnt; srccidx = acnt; desbidx = acnt; descidx = acnt; +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 result = EDMA3_DRV_setSrcIndex (hEdma, qCh1Id, srcbidx, srccidx); +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 result = EDMA3_DRV_setDestIndex (hEdma, qCh1Id, desbidx, descidx); +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +result = EDMA3_DRV_setOptField (hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_TCINTEN, 1); +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Set the Destination Addressing Mode as Increment +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 result = EDMA3_DRV_setOptField (hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_DAM, EDMA3_DRV_ADDR_MODE_INCR); +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Trigger the QDMA channel by writing the destination address +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 result = EDMA3_DRV_setPaRAMEntry (hEdma, qCh1Id, EDMA3_DRV_PARAM_ENTRY_DST, (unsigned int)(dstBuff1)); +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 Error Codes returned by the EDMA3 Driver +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Define Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 EDMA3_DRV_E_ADDRESS_NOT_ALIGNED\:Edma3DrvErrorCode}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 Edma3DrvErrorCode\:EDMA3_DRV_E_ADDRESS_NOT_ALIGNED}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 #define EDMA3_DRV_E_ADDRESS_NOT_ALIGNED\~ (EDMA3_DRV_E_BASE-10) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAABR}{\*\bkmkend AAAAAAAABR}The address of the memory location passed as argument is not properly aligned. It should be 32 bytes aligned. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_setDestParams(), and EDMA3_DRV_setSrcParams(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_E_BASE\:Edma3DrvErrorCode}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvErrorCode\:EDMA3_DRV_E_BASE}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_E_BASE\~ (-128) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAABS}{\*\bkmkend AAAAAAAABS}EDMA3 Driver Error Codes Base define +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_E_CH_PARAM_BIND_FAIL\:Edma3DrvErrorCode}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvErrorCode\:EDMA3_DRV_E_CH_PARAM_BIND_FAIL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_E_CH_PARAM_BIND_FAIL\~ (EDMA3_DRV_E_BASE-9) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAABT}{\*\bkmkend AAAAAAAABT}The binding of Channel and PaRAM Set failed +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_requestChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL\:Edma3DrvErrorCode}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvErrorCode\:EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL\~ (EDMA3_DRV_E_BASE-4) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAABU}{\*\bkmkend AAAAAAAABU}The requested DMA Channel not available +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_requestChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED\:Edma3DrvErrorCode}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvErrorCode\:EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED\~ (EDMA3_DRV_E_BASE-14) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAABV}{\*\bkmkend AAAAAAAABV}FIFO width not supported by the requested TC +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_setDestParams(), and EDMA3_DRV_setSrcParams(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_E_INST_ALREADY_EXISTS\:Edma3DrvErrorCode}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvErrorCode\:EDMA3_DRV_E_INST_ALREADY_EXISTS}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_E_INST_ALREADY_EXISTS\~ (EDMA3_DRV_E_BASE-13) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAABW}{\*\bkmkend AAAAAAAABW}EDMA3 Driver instance already exists for the specified region +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_open(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_E_INST_NOT_OPENED\:Edma3DrvErrorCode}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvErrorCode\:EDMA3_DRV_E_INST_NOT_OPENED}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_E_INST_NOT_OPENED\~ (EDMA3_DRV_E_BASE-16) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAABX}{\*\bkmkend AAAAAAAABX}EDMA3 Driver Instance does not exist, it is not opened yet +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_getInstHandle(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_E_INVALID_PARAM\:Edma3DrvErrorCode}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvErrorCode\:EDMA3_DRV_E_INVALID_PARAM}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_E_INVALID_PARAM\~ (EDMA3_DRV_E_BASE-11) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAABY}{\*\bkmkend AAAAAAAABY}Invalid Parameter passed to API +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_checkAndClearTcc(), EDMA3_DRV_clearErrorBits(), EDMA3_DRV_close(), EDMA3_DRV_create(), EDMA3_DRV_delete(), EDMA3_DRV_disableTransfer(), EDMA3_DRV_enableTransfer(), EDMA3_DRV_freeChanne +l(), EDMA3_DRV_getCCRegister(), EDMA3_DRV_getInstHandle(), EDMA3_DRV_getMapChToEvtQ(), EDMA3_DRV_getOptField(), EDMA3_DRV_getPaRAM(), EDMA3_DRV_getPaRAMEntry(), EDMA3_DRV_getPaRAMField(), EDMA3_DRV_getPaRAMPhyAddr(), EDMA3_DRV_Ioctl(), EDMA3_DRV_linkChann +e +l(), EDMA3_DRV_mapChToEvtQ(), EDMA3_DRV_open(), EDMA3_DRV_requestChannel(), EDMA3_DRV_setCCRegister(), EDMA3_DRV_setDestIndex(), EDMA3_DRV_setDestParams(), EDMA3_DRV_setEvtQPriority(), EDMA3_DRV_setOptField(), EDMA3_DRV_setPaRAM(), EDMA3_DRV_setPaRAMEntry +( +), EDMA3_DRV_setPaRAMField(), EDMA3_DRV_setQdmaTrigWord(), EDMA3_DRV_setSrcIndex(), EDMA3_DRV_setSrcParams(), EDMA3_DRV_setTransferParams(), EDMA3_DRV_unchainChannel(), EDMA3_DRV_unlinkChannel(), EDMA3_DRV_waitAndClearTcc(), edma3OpenResMgr(), and edma3Re +moveMapping(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_E_INVALID_STATE\:Edma3DrvErrorCode}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvErrorCode\:EDMA3_DRV_E_INVALID_STATE}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_E_INVALID_STATE\~ (EDMA3_DRV_E_BASE-12) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAABZ}{\*\bkmkend AAAAAAAABZ}Invalid State of EDMA3 HW Obj +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_delete(), and EDMA3_DRV_open(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_E_OBJ_NOT_CLOSED\:Edma3DrvErrorCode}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvErrorCode\:EDMA3_DRV_E_OBJ_NOT_CLOSED}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_E_OBJ_NOT_CLOSED\~ (EDMA3_DRV_E_BASE-1) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAACA}{\*\bkmkend AAAAAAAACA}EDMA3 Driver Object Not Closed yet. So it cannot be deleted. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_delete(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_E_OBJ_NOT_DELETED\:Edma3DrvErrorCode}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvErrorCode\:EDMA3_DRV_E_OBJ_NOT_DELETED}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_E_OBJ_NOT_DELETED\~ (EDMA3_DRV_E_BASE) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAACB}{\*\bkmkend AAAAAAAACB}EDMA3 Driver Object Not Deleted yet. So it cannot be created. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_create(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_E_OBJ_NOT_OPENED\:Edma3DrvErrorCode}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvErrorCode\:EDMA3_DRV_E_OBJ_NOT_OPENED}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_E_OBJ_NOT_OPENED\~ (EDMA3_DRV_E_BASE-2) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAACC}{\*\bkmkend AAAAAAAACC}EDMA3 Driver Object Not Opened yet So it cannot be closed. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_close(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_E_PARAM_SET_UNAVAIL\:Edma3DrvErrorCode}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvErrorCode\:EDMA3_DRV_E_PARAM_SET_UNAVAIL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_E_PARAM_SET_UNAVAIL\~ (EDMA3_DRV_E_BASE-6) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAACD}{\*\bkmkend AAAAAAAACD}The requested PaRAM Set not available +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL\:Edma3DrvErrorCode}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvErrorCode\:EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL\~ (EDMA3_DRV_E_BASE-5) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAACE}{\*\bkmkend AAAAAAAACE}The requested QDMA Channel not available +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_requestChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_E_RM_CLOSE_FAIL\:Edma3DrvErrorCode}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvErrorCode\:EDMA3_DRV_E_RM_CLOSE_FAIL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_E_RM_CLOSE_FAIL\~ (EDMA3_DRV_E_BASE-3) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAACF}{\*\bkmkend AAAAAAAACF}While closing EDMA3 Driver, Resource Manager Close Failed. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_close(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_E_SEMAPHORE\:Edma3DrvErrorCode}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvErrorCode\:EDMA3_DRV_E_SEMAPHORE}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_E_SEMAPHORE\~ (EDMA3_DRV_E_BASE-15) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAACG}{\*\bkmkend AAAAAAAACG}Semaphore related error +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_E_TCC_REGISTER_FAIL\:Edma3DrvErrorCode}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvErrorCode\:EDMA3_DRV_E_TCC_REGISTER_FAIL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_E_TCC_REGISTER_FAIL\~ (EDMA3_DRV_E_BASE-8) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAACH}{\*\bkmkend AAAAAAAACH}The registration of TCC failed +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_requestChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_E_TCC_UNAVAIL\:Edma3DrvErrorCode}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvErrorCode\:EDMA3_DRV_E_TCC_UNAVAIL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_E_TCC_UNAVAIL\~ (EDMA3_DRV_E_BASE-7) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAACI}{\*\bkmkend AAAAAAAACI}The requested TCC not available +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_requestChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3 Driver Channel Setup +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 \tcl2{\*\bkmkstart _Toc211937254}EDMA3 Driver Channel Setup{\*\bkmkend _Toc211937254}}}}\sectd +\linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3 Driver Channel Setup}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAACJ} +{\*\bkmkend AAAAAAAACJ}Defines +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define } +{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_DMA_CHANNEL_ANY}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \~ 1002u +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_QDMA_CHANNEL_ANY}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ 1003u +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TCC_ANY}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 \~ 1004u +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_LINK_CHANNEL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ 1005u +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_QDMA_CHANNEL_0}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 QDMA Channel defines They should be used while requesting a specific QDMA channel. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define } +{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_QDMA_CHANNEL_1}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_QDMA_CHANNEL_0+1u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_QDMA_CHANNEL_2}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_QDMA_CHANNEL_0+2u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_QDMA_CHANNEL_3}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_QDMA_CHANNEL_0+3u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_QDMA_CHANNEL_4}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_QDMA_CHANNEL_0+4u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_QDMA_CHANNEL_5}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_QDMA_CHANNEL_0+5u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_QDMA_CHANNEL_6}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_QDMA_CHANNEL_0+6u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_QDMA_CHANNEL_7}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_QDMA_CHANNEL_0+7u) +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Enumerations +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_0}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 + = 0, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_1}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_2}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_3}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_4}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_5}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_6}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_7}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_8}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_9}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 +EDMA3_DRV_HW_CHANNEL_EVENT_10}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_11}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_12}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_13}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_14}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_15}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 +\ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_16}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_17}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_18}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_19}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_20}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_21}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_22}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_23}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_24}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_25}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_26}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 +EDMA3_DRV_HW_CHANNEL_EVENT_27}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_28}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_29}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_30}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_31}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_32}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 +\ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_33}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_34}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_35}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_36}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_37}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_38}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_39}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_40}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_41}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_42}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_43}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 +EDMA3_DRV_HW_CHANNEL_EVENT_44}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_45}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_46}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_47}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_48}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_49}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 +\ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_50}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_51}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_52}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_53}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_54}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_55}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_56}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_57}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_58}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_59}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_60}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 +EDMA3_DRV_HW_CHANNEL_EVENT_61}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_62}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_63}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 DMA + Channels assigned to different Hardware Events. They should be used while requesting a specific DMA channel. One possible usage is to maintain a SoC specific file, which will contain the mapping of these hardware events to the respective peripherals for +better understanding and lesser probability of errors. Also, if any event associated with a particular peripheral gets changed, only that SoC specific file needs to be changed. +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Functions +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_requestChannel}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, un +signed int *pLCh, unsigned int *pTcc, EDMA3_RM_EventQueue evtQueue, EDMA3_RM_TccCallback tccCb, void *cbData) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Request a DMA/QDMA/Link channel. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_freeChannel}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int channelId) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Free the specified channel (DMA/QDMA/Link) and its associated resources (PaRAM Set, TCC etc) and removes various mappings. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_clearErrorBits}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int channelId) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Clears Event Register and Error Register for a specific DMA channel and brings back EDMA3 to its initial state. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_linkChannel}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh1, unsigned int lCh2) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Link two logical channels. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_unlinkChannel}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 +\i\insrsid6424133 Unlink the channel from the earlier linked logical channel. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Channel related Interface of the EDMA3 Driver +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Define Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 +\ltrch\fcs0 \fs24\insrsid6424133 EDMA3_DRV_DMA_CHANNEL_ANY\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_DMA_CHANNEL_ANY}}}\sectd \linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 #define EDMA3_DRV_DMA_CHANNEL_ANY\~ 1002u +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAACK}{\*\bkmkend AAAAAAAACK}Used to specify any available DMA Channel while requesting one. Used in the API }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_requestChannel()}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +. DMA channel from the pool of (owned && non_reserved && available_right_now) DMA channels will be chosen and returned. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_requestChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_LINK_CHANNEL\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_LINK_CHANNEL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 #define EDMA3_DRV_LINK_CHANNEL\~ 1005u +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAACL}{\*\bkmkend AAAAAAAACL}Used to specify any available PaRAM Set while requesting one. Used in the API }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_requestChannel()}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +, for Link channels. PaRAM Set from the pool of (owned && non_reserved && available_right_now) PaRAM Sets will be chosen and returned. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_requestChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_QDMA_CHANNEL_0\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_QDMA_CHANNEL_0}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 #define EDMA3_DRV_QDMA_CHANNEL_0\~ (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAACM}{\*\bkmkend AAAAAAAACM}QDMA Channel defines They should be used while requesting a specific QDMA channel. +\par QDMA Channel 0 +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_setPaRAMField(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_QDMA_CHANNEL_1\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_QDMA_CHANNEL_1}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 #define EDMA3_DRV_QDMA_CHANNEL_1\~ (EDMA3_DRV_QDMA_CHANNEL_0+1u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAACN}{\*\bkmkend AAAAAAAACN}QDMA Channel 1 +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_QDMA_CHANNEL_2\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_QDMA_CHANNEL_2}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 #define EDMA3_DRV_QDMA_CHANNEL_2\~ (EDMA3_DRV_QDMA_CHANNEL_0+2u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAACO}{\*\bkmkend AAAAAAAACO}QDMA Channel 2 +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_QDMA_CHANNEL_3\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_QDMA_CHANNEL_3}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 #define EDMA3_DRV_QDMA_CHANNEL_3\~ (EDMA3_DRV_QDMA_CHANNEL_0+3u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAACP}{\*\bkmkend AAAAAAAACP}QDMA Channel 3 +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_QDMA_CHANNEL_4\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_QDMA_CHANNEL_4}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 #define EDMA3_DRV_QDMA_CHANNEL_4\~ (EDMA3_DRV_QDMA_CHANNEL_0+4u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAACQ}{\*\bkmkend AAAAAAAACQ}QDMA Channel 4 +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_QDMA_CHANNEL_5\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_QDMA_CHANNEL_5}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 #define EDMA3_DRV_QDMA_CHANNEL_5\~ (EDMA3_DRV_QDMA_CHANNEL_0+5u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAACR}{\*\bkmkend AAAAAAAACR}QDMA Channel 5 +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_QDMA_CHANNEL_6\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_QDMA_CHANNEL_6}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 #define EDMA3_DRV_QDMA_CHANNEL_6\~ (EDMA3_DRV_QDMA_CHANNEL_0+6u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAACS}{\*\bkmkend AAAAAAAACS}QDMA Channel 6 +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_QDMA_CHANNEL_7\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_QDMA_CHANNEL_7}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 #define EDMA3_DRV_QDMA_CHANNEL_7\~ (EDMA3_DRV_QDMA_CHANNEL_0+7u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAACT}{\*\bkmkend AAAAAAAACT}QDMA Channel 7 +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_setPaRAMField(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_QDMA_CHANNEL_ANY\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_QDMA_CHANNEL_ANY}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 #define EDMA3_DRV_QDMA_CHANNEL_ANY\~ 1003u +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAACU}{\*\bkmkend AAAAAAAACU}Used to specify any available QDMA Channel while requesting one. Used in the API }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_requestChannel()}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +. QDMA channel from the pool of (owned && non_reserved && available_right_now) QDMA channels will be chosen and returned. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_requestChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_TCC_ANY\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_TCC_ANY}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_TCC_ANY\~ 1004u +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAACV}{\*\bkmkend AAAAAAAACV}Used to specify any available TCC while requesting one. Used in the API }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_requestChannel()}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +, for both DMA and QDMA channels. TCC from the pool of (owned && non_reserved && available_right_now) TCCs will be chosen and returned. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_requestChannel(). +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 +\b\f1\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Enumeration Type Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 +\ltrch\fcs0 \fs24\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 +\rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 enum EDMA3_DRV_HW_CHANNEL_EVENT +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAACW}{\*\bkmkend AAAAAAAACW}DMA Channels assigned to different Hardware Events. They should be used while requesting a specific DMA channel. One possible u +sage is to maintain a SoC specific file, which will contain the mapping of these hardware events to the respective peripherals for better understanding and lesser probability of errors. Also, if any event associated with a particular peripheral gets chang +ed, only that SoC specific file needs to be changed. +\par for eg, the sample SoC specific file "soc.h" can have these defines: +\par define EDMA3_DRV_HW_CHANNEL_MCBSP_TX EDMA3_DRV_HW_CHANNEL_EVENT_2 define EDMA3_DRV_HW_CHANNEL_MCBSP_RX EDMA3_DRV_HW_CHANNEL_EVENT_3 +\par These defines will be used by the MCBSP driver. The same event EDMA3_DRV_HW_CHANNEL_EVENT_2/3 could be mapped to some other peripheral also. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 Enumerator: }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_HW_CHANNEL_EVENT_0\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 +\v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_0}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 +EDMA3_DRV_HW_CHANNEL_EVENT_0}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAACX}{\*\bkmkend AAAAAAAACX} Channel assigned to EDMA3 Event 0 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_1\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_1}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_1}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAACY}{\*\bkmkend AAAAAAAACY} Channel assigned to EDMA3 Event 1 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_2\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_2}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_2}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAACZ}{\*\bkmkend AAAAAAAACZ} Channel assigned to EDMA3 Event 2 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_3\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_3}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_3}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAADA}{\*\bkmkend AAAAAAAADA} Channel assigned to EDMA3 Event 3 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_4\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_4}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_4}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAADB}{\*\bkmkend AAAAAAAADB} Channel assigned to EDMA3 Event 4 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_5\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_5}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_5}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAADC}{\*\bkmkend AAAAAAAADC} Channel assigned to EDMA3 Event 5 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_6\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_6}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_6}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAADD}{\*\bkmkend AAAAAAAADD} Channel assigned to EDMA3 Event 6 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_7\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_7}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_7}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAADE}{\*\bkmkend AAAAAAAADE} Channel assigned to EDMA3 Event 7 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_8\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_8}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_8}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAADF}{\*\bkmkend AAAAAAAADF} Channel assigned to EDMA3 Event 8 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_9\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_9}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_9}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAADG}{\*\bkmkend AAAAAAAADG} Channel assigned to EDMA3 Event 9 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_10\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_10}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_10}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAADH}{\*\bkmkend AAAAAAAADH} Channel assigned to EDMA3 Event 10 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_11\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_11}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_11}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAADI}{\*\bkmkend AAAAAAAADI} Channel assigned to EDMA3 Event 11 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_12\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_12}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_12}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAADJ}{\*\bkmkend AAAAAAAADJ} Channel assigned to EDMA3 Event 12 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_13\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_13}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_13}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAADK}{\*\bkmkend AAAAAAAADK} Channel assigned to EDMA3 Event 13 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_14\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_14}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_14}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAADL}{\*\bkmkend AAAAAAAADL} Channel assigned to EDMA3 Event 14 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_15\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_15}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_15}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAADM}{\*\bkmkend AAAAAAAADM} Channel assigned to EDMA3 Event 15 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_16\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_16}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_16}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAADN}{\*\bkmkend AAAAAAAADN} Channel assigned to EDMA3 Event 16 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_17\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_17}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_17}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAADO}{\*\bkmkend AAAAAAAADO} Channel assigned to EDMA3 Event 17 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_18\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_18}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_18}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAADP}{\*\bkmkend AAAAAAAADP} Channel assigned to EDMA3 Event 18 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_19\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_19}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_19}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAADQ}{\*\bkmkend AAAAAAAADQ} Channel assigned to EDMA3 Event 19 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_20\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_20}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_20}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAADR}{\*\bkmkend AAAAAAAADR} Channel assigned to EDMA3 Event 20 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_21\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_21}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_21}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAADS}{\*\bkmkend AAAAAAAADS} Channel assigned to EDMA3 Event 21 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_22\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_22}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_22}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAADT}{\*\bkmkend AAAAAAAADT} Channel assigned to EDMA3 Event 22 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_23\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_23}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_23}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAADU}{\*\bkmkend AAAAAAAADU} Channel assigned to EDMA3 Event 23 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_24\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_24}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_24}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAADV}{\*\bkmkend AAAAAAAADV} Channel assigned to EDMA3 Event 24 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_25\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_25}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_25}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAADW}{\*\bkmkend AAAAAAAADW} Channel assigned to EDMA3 Event 25 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_26\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_26}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_26}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAADX}{\*\bkmkend AAAAAAAADX} Channel assigned to EDMA3 Event 26 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_27\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_27}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_27}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAADY}{\*\bkmkend AAAAAAAADY} Channel assigned to EDMA3 Event 27 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_28\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_28}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_28}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAADZ}{\*\bkmkend AAAAAAAADZ} Channel assigned to EDMA3 Event 28 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_29\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_29}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_29}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAEA}{\*\bkmkend AAAAAAAAEA} Channel assigned to EDMA3 Event 29 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_30\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_30}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_30}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAEB}{\*\bkmkend AAAAAAAAEB} Channel assigned to EDMA3 Event 30 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_31\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_31}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_31}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAEC}{\*\bkmkend AAAAAAAAEC} Channel assigned to EDMA3 Event 31 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_32\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_32}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_32}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAED}{\*\bkmkend AAAAAAAAED} Channel assigned to EDMA3 Event 32 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_33\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_33}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_33}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAEE}{\*\bkmkend AAAAAAAAEE} Channel assigned to EDMA3 Event 33 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_34\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_34}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_34}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAEF}{\*\bkmkend AAAAAAAAEF} Channel assigned to EDMA3 Event 34 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_35\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_35}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_35}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAEG}{\*\bkmkend AAAAAAAAEG} Channel assigned to EDMA3 Event 35 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_36\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_36}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_36}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAEH}{\*\bkmkend AAAAAAAAEH} Channel assigned to EDMA3 Event 36 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_37\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_37}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_37}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAEI}{\*\bkmkend AAAAAAAAEI} Channel assigned to EDMA3 Event 37 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_38\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_38}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_38}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAEJ}{\*\bkmkend AAAAAAAAEJ} Channel assigned to EDMA3 Event 38 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_39\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_39}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_39}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAEK}{\*\bkmkend AAAAAAAAEK} Channel assigned to EDMA3 Event 39 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_40\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_40}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_40}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAEL}{\*\bkmkend AAAAAAAAEL} Channel assigned to EDMA3 Event 40 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_41\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_41}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_41}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAEM}{\*\bkmkend AAAAAAAAEM} Channel assigned to EDMA3 Event 41 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_42\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_42}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_42}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAEN}{\*\bkmkend AAAAAAAAEN} Channel assigned to EDMA3 Event 42 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_43\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_43}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_43}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAEO}{\*\bkmkend AAAAAAAAEO} Channel assigned to EDMA3 Event 43 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_44\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_44}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_44}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAEP}{\*\bkmkend AAAAAAAAEP} Channel assigned to EDMA3 Event 44 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_45\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_45}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_45}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAEQ}{\*\bkmkend AAAAAAAAEQ} Channel assigned to EDMA3 Event 45 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_46\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_46}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_46}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAER}{\*\bkmkend AAAAAAAAER} Channel assigned to EDMA3 Event 46 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_47\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_47}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_47}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAES}{\*\bkmkend AAAAAAAAES} Channel assigned to EDMA3 Event 47 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_48\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_48}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_48}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAET}{\*\bkmkend AAAAAAAAET} Channel assigned to EDMA3 Event 48 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_49\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_49}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_49}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAEU}{\*\bkmkend AAAAAAAAEU} Channel assigned to EDMA3 Event 49 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_50\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_50}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_50}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAEV}{\*\bkmkend AAAAAAAAEV} Channel assigned to EDMA3 Event 50 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_51\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_51}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_51}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAEW}{\*\bkmkend AAAAAAAAEW} Channel assigned to EDMA3 Event 51 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_52\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_52}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_52}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAEX}{\*\bkmkend AAAAAAAAEX} Channel assigned to EDMA3 Event 52 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_53\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_53}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_53}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAEY}{\*\bkmkend AAAAAAAAEY} Channel assigned to EDMA3 Event 53 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_54\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_54}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_54}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAEZ}{\*\bkmkend AAAAAAAAEZ} Channel assigned to EDMA3 Event 54 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_55\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_55}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_55}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAFA}{\*\bkmkend AAAAAAAAFA} Channel assigned to EDMA3 Event 55 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_56\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_56}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_56}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAFB}{\*\bkmkend AAAAAAAAFB} Channel assigned to EDMA3 Event 56 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_57\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_57}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_57}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAFC}{\*\bkmkend AAAAAAAAFC} Channel assigned to EDMA3 Event 57 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_58\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_58}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_58}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAFD}{\*\bkmkend AAAAAAAAFD} Channel assigned to EDMA3 Event 58 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_59\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_59}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_59}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAFE}{\*\bkmkend AAAAAAAAFE} Channel assigned to EDMA3 Event 59 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_60\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_60}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_60}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAFF}{\*\bkmkend AAAAAAAAFF} Channel assigned to EDMA3 Event 60 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_61\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_61}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_61}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAFG}{\*\bkmkend AAAAAAAAFG} Channel assigned to EDMA3 Event 61 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_62\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_62}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_62}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAFH}{\*\bkmkend AAAAAAAAFH} Channel assigned to EDMA3 Event 62 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_63\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_HW_CHANNEL_EVENT_63}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_63}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAFI}{\*\bkmkend AAAAAAAAFI} Channel assigned to EDMA3 Event 63 +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 +\b\f1\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Function Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 +\ltrch\fcs0 \fs24\insrsid6424133 EDMA3_DRV_clearErrorBits\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_clearErrorBits}}}\sectd \linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Result EDMA3_DRV_clearErrorBits (EDMA3_DRV_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 +\ltrch\fcs0 \i\insrsid6424133 channelId}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAFJ}{\*\bkmkend AAAAAAAAFJ}Clears Event Register and Error Register for a specific DMA channel and brings back EDMA3 to its initial state. +\par This API clears the Event register, Event Miss register Event Enable register for a specific DMA channel. It also clears the CC Error register. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 hEdma +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Handle to the EDMA Driver Instance. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 channelId}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] DMA Channel needs to be cleaned. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_SOK or EDMA3_DRV Error code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +This function is re-entrant for unique channelId values. It is non- re-entrant for same channelId value. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +References EDMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numEvtQueue, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Instance::shadowRegs. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_freeChannel\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_freeChannel}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Result EDMA3_DRV_freeChannel (EDMA3_DRV_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\insrsid6424133 channelId}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAFK}{\*\bkmkend AAAAAAAAFK}Free the specified channel (DMA/QDMA/Link) and its associated resources (PaRAM Set, TCC etc) and removes various mappings. +\par This API internally uses EDMA3_RM_freeResource () to free the desired resources. +\par For Link channels, this API only frees the associated PaRAM Set. +\par For DMA/QDMA channels, it doe +s the following operations: a) Disable any ongoing transfer on the channel, b) Unregister the TCC Callback function and disable the interrupts, c) Remove the channel to Event Queue mapping, d) For DMA channels, clear the DCHMAP register, if available e) F +or QDMA channels, clear the QCHMAP register, f) Frees the DMA/QDMA channel in the end. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 hEdma +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Handle to the EDMA Driver Instance. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 channelId}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Logical Channel number to be freed. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_SOK or EDMA3_DRV Error code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 This f +unction disables the global interrupts while modifying the global CC registers and while modifying global data structures, to prevent simultaneous access to the global pool of resources. It internally calls EDMA3_RM_freeResource () for resource de-allocat +ion. It is re-entrant. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +References EDMA3_DRV_CHANNEL_TYPE_DMA, EDMA3_DRV_CHANNEL_TYPE_LINK, EDMA3_DRV_CHANNEL_TYPE_NONE, EDMA3_DRV_CHANNEL_TYPE_QDMA, EDMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LINK_CH_MAX_VAL, EDMA3_DRV_LINK_CH_MIN_VAL, +EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, edma3RemoveMapping(), EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_GblConfigParams::numTccs, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_D +RV_Instance::pDrvObjectHandle, EDMA3_DRV_Object::phyCtrllerInstId, EDMA3_DRV_Instance::resMgrInstance, and EDMA3_DRV_ChBoundResources::tcc. +\par Referenced by EDMA3_DRV_requestChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_linkChannel\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_linkChannel}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Result EDMA3_DRV_linkChannel (EDMA3_DRV_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\insrsid6424133 lCh1}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 lCh2}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAFL}{\*\bkmkend AAAAAAAAFL}Link two logical channels. +\par This API is used to link two previously allocated logical (DMA/QDMA/Link) channels. +\par It sets the Link field of the PaRAM set associated with first logical channel (lCh1) to point it to the PaRAM set associated with second logical channel (lCh2). +\par It also sets the TCC field of PaRAM set associated with second logical channel to the same as that of the first logical channel. +\par After linking the channels, user should not update any PaRAM Set of the channel. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 hEdma +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Handle to the EDMA Driver Instance. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 lCh1}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Logical Channel to which particular channel will be linked. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 lCh2}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Logical Channel which needs to be linked to the first channel. After the transfer based on the PaRAM set of lCh1 is over, the PaRAM set of +lCh2 will be copied to the PaRAM set of lCh1 and transfer will resume. For DMA channels, another sync event is required to initiate the transfer on the Link channel. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_SOK or EDMA3_DRV Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +This function is re-entrant for unique lCh1 & lCh2 values. It is non-re-entrant for same lCh1 & lCh2 values. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_OPT_TCC_CLR_MASK, EDMA3_DRV_OPT_TCC_GET_MASK, EDMA3_DRV_OPT_TCC_SET_MASK, EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD, + EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_requestChannel\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_requestChannel}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Result EDMA3_DRV_requestChannel (EDMA3_DRV_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\insrsid6424133 pLCh}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 pTcc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , EDMA3_RM_EventQueue }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\insrsid6424133 evtQueue}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , EDMA3_RM_TccCallback }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 tccCb}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , void * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\insrsid6424133 cbData}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAFM}{\*\bkmkend AAAAAAAAFM}Request a DMA/QDMA/Link channel. +\par Each channel (DMA/QDMA/Link) must be requested before initiating a DMA transfer on that channel. +\par This API is used to allocate a logical channel (DMA/QDMA/Link) along with the associated resources. For DMA and QDMA channels, TCC and PaRAM Set are also allocated along with the requested channel. For Link channel, ONLY a PaRAM Set is allocated. +\par User can request a specific logical channel by passing the channel id in 'pLCh'. Note that the channel + id is the same as the actual resource id in case of DMA channels. To allocate specific QDMA channels, user SHOULD use the defines EDMA3_DRV_QDMA_CHANNEL_X mentioned above. +\par User can also request ANY available logical channel also by specifying the below me +ntioned values in '*pLCh': a) EDMA3_DRV_DMA_CHANNEL_ANY: For DMA channels b) EDMA3_DRV_QDMA_CHANNEL_ANY: For QDMA channels, and c) EDMA3_DRV_LINK_CHANNEL: For Link channels. Normally user should use this value to request link channels (PaRAM Sets used for + linking purpose only), unless he wants to use some specific link channels (PaRAM Sets) which is also allowed. +\par This API internally uses EDMA3_RM_allocResource () to allocate the desired resources (DMA/QDMA channel, PaRAM Set and TCC). +\par This API also registers a specific callback function against the allocated TCC. +\par For DMA/QDMA channels, after allocating all the EDMA3 resources, this API sets the TCC field of the OPT PaRAM Word with the allocated TCC. It also sets the event queue for the channel allocated. The event queue needs to be specified by the user. +\par For DMA channel, it also sets the DCHMAP register, if required. +\par For QDMA channel, it sets the QCHMAP register and CCNT as trigger word and enables the QDMA channel by writing to the QEESR register. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 hEdma +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Handle to the previously opened Driver Instance. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 pLCh}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN/OUT] Requested logical channel id. Examples: +\par {\pntext\pard\plain\ltrpar \s64 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s64\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin1080\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_HW_CHANNEL_EVENT_0 +\par {\pntext\pard\plain\ltrpar \s64 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s64\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 To request a DMA Master Channel mapped to EDMA Event 0. +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 + +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_DMA_CHANNEL_ANY +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 For requesting any DMA Master channel with no event mapping. +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_QDMA_CHANNEL_ANY +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 For requesting any QDMA Master channel +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_QDMA_CHANNEL_0 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 For requesting the QDMA Channel 0. +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_LINK_CHANNEL +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 For requesting a DMA Slave Channel, +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 to be linked to some other Master +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 channel. +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +In case user passes a specific channel Id, pLCh value is left unchanged. In case user requests ANY available resource, the allocated channel id is returned in pLCh. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +To request a PaRAM Set for the purpose of linking to another channel, call the function with +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +*pLCh = EDMA3_DRV_LINK_CHANNEL; +\par This function will update *pLCh with the allocated Link channel handle. This handle could be DIFFERENT from the actual PaRAM Set allocated by the Resource Manager internally. So user SHOULD NOT assume the handle as the PaRAM Set Id. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 pTcc} +{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN/OUT] The channel number on which the completion/error interrupt is generated. Not used if user requested for a Link channel. Examples: +\par {\pntext\pard\plain\ltrpar \s64 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s64\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin1080\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_HW_CHANNEL_EVENT_0 +\par {\pntext\pard\plain\ltrpar \s64 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s64\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 To request TCC associated with +\par {\pntext\pard\plain\ltrpar \s64 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s64\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 DMA Master Channel mapped to EDMA +\par {\pntext\pard\plain\ltrpar \s64 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s64\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 event 0. +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 + +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_TCC_ANY +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 For requesting any TCC with no +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +channel mapping. In case user passes a specific TCC value, pTcc value is left unchanged. In case user requests ANY available TCC, the allocated one is returned in pTcc +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 +evtQueue}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Event Queue Number to which the channel will be mapped (valid only for the Master Channel (DMA/QDMA) request) +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 tccCb}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] TCC callback - caters to channel- specific events like "Event Miss Error" or "Transfer Complete" +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 cbData}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Data which will be passed directly to the tccCb callback function +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_SOK or EDMA3_DRV Error code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +This function internally uses EDMA3 Resource Manager, which acquires a RM Instance specific semaphore to prevent simultaneous access to the global pool of resources. It also disables the global interrupts while modifying the +global CC registers. It is re-entrant, but SHOULD NOT be called from the user callback function (ISR context). +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Fill the resource id, whose associated TCC needs to be registered. For QDMA channels, pass the actual QDMA channel no instead of (*pLCh). +\par Map the allocated PaRAM Set to the logical DMa/QDMA channel. +\par First check whether the mapping feature is supported on the underlying platform. In case it is not supported, dont call this API, because this API returns error in case the feature is not there. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Refer +ences EDMA3_DRV_GblConfigParams::dmaChannelPaRAMMap, EDMA3_DRV_GblConfigParams::dmaChannelTccMap, EDMA3_DRV_GblConfigParams::dmaChPaRAMMapExists, EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CHANNEL_TYPE_DMA, EDMA3_DRV_CHANNEL_TYPE_QDMA, +E +DMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_DMA_CHANNEL_ANY, EDMA3_DRV_DMAQNUM_CLR_MASK, EDMA3_DRV_DMAQNUM_SET_MASK, EDMA3_DRV_E_CH_PARAM_BIND_FAIL, EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL, EDMA3_DRV_E_TCC_REGIS +T +ER_FAIL, EDMA3_DRV_E_TCC_UNAVAIL, EDMA3_DRV_freeChannel(), EDMA3_DRV_LINK_CH_MAX_VAL, EDMA3_DRV_LINK_CH_MIN_VAL, EDMA3_DRV_LINK_CHANNEL, EDMA3_DRV_OPT_TCC_CLR_MASK, EDMA3_DRV_OPT_TCC_SET_MASK, EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD, EDMA3_DRV_QDMA_CH_MAX_VAL, + +EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_QDMA_CHANNEL_ANY, EDMA3_DRV_QDMAQNUM_CLR_MASK, EDMA3_DRV_QDMAQNUM_SET_MASK, EDMA3_DRV_TCC_ANY, EDMA3_DRV_TRIG_MODE_NONE, EDMA3_DRV_TRIG_MODE_QDMA, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, +E +DMA3_DRV_GblConfigParams::numDmaChannels, EDMA3_DRV_GblConfigParams::numEvtQueue, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, EDMA3_DRV_Object::phyCtrllerInstId, EDMA3_DRV_Instance::resMgrInstance, EDMA3_DRV_Instance::shadow +Regs, EDMA3_DRV_ChBoundResources::tcc, and EDMA3_DRV_ChBoundResources::trigMode. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_unlinkChannel\:Edma3DrvChannelSetup}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvChannelSetup\:EDMA3_DRV_unlinkChannel}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Result EDMA3_DRV_unlinkChannel (EDMA3_DRV_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\insrsid6424133 lCh}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAFN}{\*\bkmkend AAAAAAAAFN}Unlink the channel from the earlier linked logical channel. +\par This function breaks the link between the specified channel and the earlier linked logical channel by clearing the Link Address field. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 hEdma +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Handle to the EDMA Driver Instance. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 lCh}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Channel for which linking has to be removed +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_SOK or EDMA3_DRV Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_ +DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3 Driver Typical EDMA Transfer Setup +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 \tcl2{\*\bkmkstart _Toc211937255}EDMA3 Driver Typical EDMA Transfer Setup{\*\bkmkend _Toc211937255}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3 Driver Typical EDMA Transfer Setup}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAFO}{\*\bkmkend AAAAAAAAFO}Data Structures +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ChainOptions}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Structure to be used to configure interrupt generation and chaining options. +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Enumerations +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OptField}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_FIELD_SAM}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 0, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_FIELD_DAM}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 1, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_FIELD_SYNCDIM}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 + = 2, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_FIELD_STATIC}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 3, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_FIELD_FWID}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 = 4, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_FIELD_TCCMODE}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 5, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_FIELD_TCC}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 = 6, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_FIELD_TCINTEN}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 7, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_FIELD_ITCINTEN}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 8, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_FIELD_TCCHEN}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 9, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 +EDMA3_DRV_OPT_FIELD_ITCCHEN}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 10 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 OPT Field Offset. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_AddrMode}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ADDR_MODE_INCR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 0, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ADDR_MODE_FIFO}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 1 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 EDMA Addressing modes. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_SyncType}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_SYNC_A}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 0, }{\rtlch\fcs1 +\ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_SYNC_AB}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 1 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 EDMA Transfer Synchronization type. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_StaticMode}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_STATIC_DIS}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 0, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_STATIC_EN}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 1 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 True/False: PaRAM set is Static or not. A Static PaRAM set is updated or linked after TR is submitted. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_FifoWidth}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_W8BIT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 0, }{\rtlch\fcs1 +\ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_W16BIT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 1, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_W32BIT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 2, }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_W64BIT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 3, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_W128BIT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 4, }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_W256BIT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 5 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 EDMA3 FIFO width. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TccMode}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TCCMODE_NORMAL}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 0, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TCCMODE_EARLY}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 1 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Transfer complete code mode. Indicates the point at which a transfer is considered completed for chaining and interrupt generation. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TcintEn}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TCINTEN_DIS}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 0, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TCINTEN_EN}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 1 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Transfer complete interrupt enable. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ItcintEn}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ITCINTEN_DIS}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 0, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ITCINTEN_EN}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 1 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Intermediate Transfer complete interrupt enable. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TcchEn}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TCCHEN_DIS}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 0, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TCCHEN_EN}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 1 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Transfer complete chaining enable. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ItcchEn}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ITCCHEN_DIS}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 0, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ITCCHEN_EN}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 1 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Intermediate Transfer complete chaining enable. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TrigMode}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TRIG_MODE_MANUAL}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 0, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TRIG_MODE_QDMA}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 1, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TRIG_MODE_EVENT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 + = 2, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TRIG_MODE_NONE}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 3 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 EDMA Trigger Mode Selection. +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Functions +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setOptField}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OptField}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 optField, unsigned int newOptFieldVal) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Set a particular OPT field in the PaRAM set associated with the logical channel 'lCh'. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_getOptField}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OptField}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 optField, unsigned int *optFieldVal) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Get a particular OPT field in the PaRAM set associated with the logical channel 'lCh'. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setSrcParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int srcAddr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 EDMA3_DRV_AddrMode}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 addrMode, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_FifoWidth}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 fifoWidth) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 DMA source parameters setup. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setDestParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int destAddr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 EDMA3_DRV_AddrMode}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 addrMode, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_FifoWidth}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 fifoWidth) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 DMA Destination parameters setup. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setSrcIndex}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, int srcBIdx, int srcCIdx) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 DMA source index setup. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setDestIndex}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, int destBIdx, int destCIdx) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 DMA destination index setup. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setTransferParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 + (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int aCnt, unsigned int bCnt, unsigned int cCnt, unsigned int bCntReload, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_SyncType}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 syncType) + +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 DMA transfer parameters setup. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_chainChannel}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh1, unsigned int lCh2, const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 EDMA3_DRV_ChainOptions}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 *chainOptions) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Chain the two specified channels. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA +3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_unchainChannel}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Unchain the two channels. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_enableTransfer}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TrigMode} +{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 trigMode) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Start EDMA transfer on the specified channel. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_disableTransfer}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TrigMode +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 trigMode) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 +\i\insrsid6424133 Disable DMA transfer on the specified channel. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +The typical EDMA transfer related Interface of the EDMA3 Driver +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Enumeration Type Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 +\ltrch\fcs0 \fs24\insrsid6424133 EDMA3_DRV_AddrMode\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_AddrMode}}}\sectd \linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 enum EDMA3_DRV_AddrMode +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAFP}{\*\bkmkend AAAAAAAAFP}EDMA Addressing modes. +\par The EDMA3 TC supports two addressing modes +\par }\pard\plain \ltrpar\s73\ql \fi-360\li720\ri0\widctlpar\wrapdefault\faauto\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 1.\tab +Increment transfer +\par 2.\tab FIFO transfer +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +The SAM (Source Addressing Mode) and the DAM (Destination Addressing Mode) can be independently set to either of the two via the OPT register. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 Enumerator: }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 ED +MA3_DRV_ADDR_MODE_INCR\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 +\v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_ADDR_MODE_INCR}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 +EDMA3_DRV_ADDR_MODE_INCR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAFQ}{\*\bkmkend AAAAAAAAFQ} Increment (INCR) mode. Source addressing within an array increments. Source is not a FIFO. +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_ADDR_MODE_FIFO\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_ADDR_MODE_FIFO}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_ADDR_MODE_FIFO}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAFR}{\*\bkmkend AAAAAAAAFR} FIFO mode. Source addressing within an array wraps around upon reaching FIFO width. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_FifoWidth\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_FifoWidth}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 enum EDMA3_DRV_FifoWidth +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAFS}{\*\bkmkend AAAAAAAAFS}EDMA3 FIFO width. +\par The user can set the width of the FIFO using this enum. This is done via the OPT register. This is valid only if the EDMA3_DRV_ADDR_MODE_FIFO value is used for the enum EDMA3_DRV_AddrMode. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 Enumerator: }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_W8BIT\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 +\v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_W8BIT}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 +EDMA3_DRV_W8BIT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAFT}{\*\bkmkend AAAAAAAAFT} FIFO width is 8-bit. +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_W16BIT\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 +\v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_W16BIT}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 +EDMA3_DRV_W16BIT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAFU}{\*\bkmkend AAAAAAAAFU} FIFO width is 16-bit. +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_W32BIT\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 +\v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_W32BIT}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 EDMA3_ +DRV_W32BIT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAFV}{\*\bkmkend AAAAAAAAFV} FIFO width is 32-bit. +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_W64BIT\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 +\v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_W64BIT}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 +EDMA3_DRV_W64BIT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAFW}{\*\bkmkend AAAAAAAAFW} FIFO width is 64-bit. +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_W128BIT\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 +\v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_W128BIT}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 +EDMA3_DRV_W128BIT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAFX}{\*\bkmkend AAAAAAAAFX} FIFO width is 128-bit. +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_W256BIT\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 +\v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_W256BIT}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 +EDMA3_DRV_W256BIT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAFY}{\*\bkmkend AAAAAAAAFY} FIFO width is 256-bit. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_ItcchEn\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_ItcchEn}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 enum EDMA3_DRV_ItcchEn +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAFZ}{\*\bkmkend AAAAAAAAFZ}Intermediate Transfer complete chaining enable. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 +\par Enumerator: }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_ITCCHEN_DIS\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 +\v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_ITCCHEN_DIS}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 +EDMA3_DRV_ITCCHEN_DIS}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAGA}{\*\bkmkend AAAAAAAAGA} Intermediate Transfer complete chaining is disabled +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_ITCCHEN_EN\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 +\v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_ITCCHEN_EN}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 +EDMA3_DRV_ITCCHEN_EN}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAGB}{\*\bkmkend AAAAAAAAGB} + Intermediate transfer complete chaining is enabled. When enabled, the chained event register (CER/CERH) bit is set on every intermediate chained transfer comple +tion (upon completion of every intermediate TR in the PaRAM set, except the final TR in the PaRAM set). The bit (position) set in CER or CERH is the TCC value specified. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_ItcintEn\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_ItcintEn}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 enum EDMA3_DRV_ItcintEn +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAGC}{\*\bkmkend AAAAAAAAGC}Intermediate Transfer complete interrupt enable. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 +\par Enumerator: }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_ITCINTEN_DIS\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 +\v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_ITCINTEN_DIS}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 +EDMA3_DRV_ITCINTEN_DIS}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAGD}{\*\bkmkend AAAAAAAAGD} Intermediate Transfer complete interrupt is disabled +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_ITCINTEN_EN\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_ITCINTEN_EN}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_ITCINTEN_EN}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAGE}{\*\bkmkend AAAAAAAAGE} Intermediate transfer comple +te interrupt is enabled. When enabled, the interrupt pending register (IPR/IPRH) bit is set on every intermediate transfer completion (upon completion of every intermediate TR in the PaRAM set, except the final TR in the PaRAM set). The bit (position) set + in IPR or IPRH is the TCC value specified. In order to generate a completion interrupt to the CPU, the corresponding IER [TCC] / IERH [TCC] bit must be set to 1. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_OptField\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_OptField}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 enum EDMA3_DRV_OptField +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAGF}{\*\bkmkend AAAAAAAAGF}OPT Field Offset. +\par Use this enum to set or get any of the Fields within an OPT of a Parameter RAM set. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 Enumerator: }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_OPT_FIELD_SAM\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 +\v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_OPT_FIELD_SAM}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 +EDMA3_DRV_OPT_FIELD_SAM}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAGG}{\*\bkmkend AAAAAAAAGG} Source addressing mode (INCR / FIFO) (Bit 0) +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_OPT_FIELD_DAM\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_OPT_FIELD_DAM}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_OPT_FIELD_DAM}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAGH}{\*\bkmkend AAAAAAAAGH} Destination addressing mode (INCR / FIFO) (Bit 1) +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_OPT_FIELD_SYNCDIM\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_OPT_FIELD_SYNCDIM}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_OPT_FIELD_SYNCDIM}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAGI}{\*\bkmkend AAAAAAAAGI} Transfer synchronization dimension (A-synchronized / AB-synchronized) (Bit 2) +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_OPT_FIELD_STATIC\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_OPT_FIELD_STATIC}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_OPT_FIELD_STATIC}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAGJ}{\*\bkmkend AAAAAAAAGJ} The STATIC field PaRAM set is static/non-static? (Bit 3) +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_OPT_FIELD_FWID\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_OPT_FIELD_FWID}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_OPT_FIELD_FWID}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAGK}{\*\bkmkend AAAAAAAAGK} FIFO Width. Applies if either SAM or DAM is set to FIFO mode. (Bitfield 8-10) +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_OPT_FIELD_TCCMODE\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_OPT_FIELD_TCCMODE}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_OPT_FIELD_TCCMODE}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAGL}{\*\bkmkend AAAAAAAAGL} Transfer complete code mode. Indicates the point at which a transfer is con +sidered completed for chaining and interrupt generation. (Bit 11) +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_OPT_FIELD_TCC\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_OPT_FIELD_TCC}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_OPT_FIELD_TCC}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAGM}{\*\bkmkend AAAAAAAAGM} Transfer Complete Code (TCC). Th +is 6-bit code is used to set the relevant bit in chaining enable register (CER[TCC]/CERH[TCC]) for chaining or in interrupt pending register (IPR[TCC]/IPRH[TCC]) for interrupts. (Bitfield 12-17) +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_OPT_FIELD_TCINTEN\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_OPT_FIELD_TCINTEN}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_OPT_FIELD_TCINTEN}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAGN}{\*\bkmkend AAAAAAAAGN} Transfer complete interrupt enable/disable. (Bit 20) +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_OPT_FIELD_ITCINTEN\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_OPT_FIELD_ITCINTEN}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_OPT_FIELD_ITCINTEN}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAGO}{\*\bkmkend AAAAAAAAGO} Intermediate transfer complete interrupt enable/disable. (Bit 21) +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_OPT_FIELD_TCCHEN\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_OPT_FIELD_TCCHEN}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_OPT_FIELD_TCCHEN}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAGP}{\*\bkmkend AAAAAAAAGP} Transfer complete chaining enable/disable (Bit 22) +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_OPT_FIELD_ITCCHEN\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_OPT_FIELD_ITCCHEN}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_OPT_FIELD_ITCCHEN}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAGQ}{\*\bkmkend AAAAAAAAGQ} Intermediate transfer completion chaining enable/disable (Bit 23) +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_StaticMode\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_StaticMode}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 enum EDMA3_DRV_StaticMode +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAGR}{\*\bkmkend AAAAAAAAGR}True/False: PaRAM set is Static or not. A Static PaRAM set is updated or linked after TR is submitted. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 +\par Enumerator: }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_STATIC_DIS\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 +\v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_STATIC_DIS}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 +EDMA3_DRV_STATIC_DIS}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAGS}{\*\bkmkend AAAAAAAAGS} + PaRAM set is not Static. PaRAM set is updated or linked after TR is submitted. A value of 0 should be used for DMA channels and for nonfinal transfers in a linked list of QDMA transfers +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_STATIC_EN\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 +\v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_STATIC_EN}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 +EDMA3_DRV_STATIC_EN}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAGT}{\*\bkmkend AAAAAAAAGT} + PaRAM set is Static. PaRAM set is not updated or linked after TR is submitted. A value of 1 should be used for isolated QDMA transfers or for the final transfer in a linked list of QDMA transfers. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_SyncType\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_SyncType}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 enum EDMA3_DRV_SyncType +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAGU}{\*\bkmkend AAAAAAAAGU}EDMA Transfer Synchronization type. +\par Two types of Synchronization of transfers are possible +\par }\pard\plain \ltrpar\s73\ql \fi-360\li720\ri0\widctlpar\wrapdefault\faauto\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 1.\tab +A Synchronized +\par 2.\tab AB Syncronized +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +A Sync +\par }\pard\plain \ltrpar\s73\ql \fi-360\li720\ri0\widctlpar\wrapdefault\faauto\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 1.\tab +Each Array is submitted as one TR +\par 2.\tab (BCNT*CCNT) number of sync events are needed to completely service a PaRAM set. (Where BCNT = Num of Arrays in a Frame; CCNT = Num of Frames in a Block) +\par 3.\tab (S/D)CIDX = (Addr of First array in next frame) minus (Addr of Last array in present frame) (Where CIDX is the Inter-Frame index) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 + +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 AB Sync + +\par }\pard\plain \ltrpar\s74\ql \fi-360\li1080\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin1080\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 1.\tab Each Frame is submitted as one TR +\par 2.\tab Only CCNT number of sync events are needed to completely service a PaRAM set +\par 3.\tab (S/D)CIDX = (Addr of First array in next frame) minus (Addr of First array of present frame) +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +ABC sync transfers can be achieved logically by chaining multiple AB sync transfers +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 Enumerator: }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_SYNC_A\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 +\v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_SYNC_A}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 +EDMA3_DRV_SYNC_A}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAGV}{\*\bkmkend AAAAAAAAGV} A-synchronized. Each event triggers the transfer of a single array of ACNT bytes +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_SYNC_AB\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 +\v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_SYNC_AB}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 +EDMA3_DRV_SYNC_AB}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAGW}{\*\bkmkend AAAAAAAAGW} AB-synchronized. Each event triggers the transfer of BCNT arrays of ACNT bytes +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_TcchEn\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_TcchEn}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 enum EDMA3_DRV_TcchEn +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAGX}{\*\bkmkend AAAAAAAAGX}Transfer complete chaining enable. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 +\par Enumerator: }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_TCCHEN_DIS\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 +\v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_TCCHEN_DIS}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 +EDMA3_DRV_TCCHEN_DIS}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAGY}{\*\bkmkend AAAAAAAAGY} Transfer complete chaining is disabled +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_TCCHEN_EN\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 +\v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_TCCHEN_EN}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 +EDMA3_DRV_TCCHEN_EN}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAGZ}{\*\bkmkend AAAAAAAAGZ} Transfer complete chaining is enabled. When enabled, the chained event register (CER/CERH) bit is set on final chained transfe +r completion (upon completion of the final / last TR in the PaRAM set). The bit (position) set in CER or CERH is the TCC value specified. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_TccMode\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_TccMode}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 enum EDMA3_DRV_TccMode +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAHA}{\*\bkmkend AAAAAAAAHA}Transfer complete code mode. Indicates the point at which a transfer is considered completed for chaining and interrupt generation. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 +\par Enumerator: }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_TCCMODE_NORMAL\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 +\v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_TCCMODE_NORMAL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 +EDMA3_DRV_TCCMODE_NORMAL}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAHB}{\*\bkmkend AAAAAAAAHB} A transfer is considered completed after transfer of data +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_TCCMODE_EARLY\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_TCCMODE_EARLY}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_TCCMODE_EARLY}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAHC}{\*\bkmkend AAAAAAAAHC} + A transfer is considered completed after the EDMA3CC submits a TR to the EDMA3TC. TC may still be transferring data when interrupt/chain is triggered. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_TcintEn\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_TcintEn}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 enum EDMA3_DRV_TcintEn +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAHD}{\*\bkmkend AAAAAAAAHD}Transfer complete interrupt enable. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 +\par Enumerator: }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_TCINTEN_DIS\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 +\v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_TCINTEN_DIS}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 +EDMA3_DRV_TCINTEN_DIS}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAHE}{\*\bkmkend AAAAAAAAHE} Transfer complete interrupt is disabled +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_TCINTEN_EN\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 +\v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_TCINTEN_EN}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 +EDMA3_DRV_TCINTEN_EN}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAHF}{\*\bkmkend AAAAAAAAHF} Transfer complete interrupt is enabled. When +enabled, the interrupt pending register (IPR/IPRH) bit is set on transfer completion (upon completion of the final TR in the PaRAM set). The bit (position) set in IPR or IPRH is the TCC value specified. In order to generate a completion interrupt to the C +PU, the corresponding IER [TCC] / IERH [TCC] bit must be set to 1. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_TrigMode\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_TrigMode}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 enum EDMA3_DRV_TrigMode +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAHG}{\*\bkmkend AAAAAAAAHG}EDMA Trigger Mode Selection. +\par Use this enum to select the EDMA trigger mode while enabling the EDMA transfer +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 Enumerator: }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_TRIG_MODE_MANUAL\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 +\v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_TRIG_MODE_MANUAL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_TRIG_MODE_MANUAL}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAHH}{\*\bkmkend AAAAAAAAHH} + Set the Trigger mode to Manual . The CPU manually triggers a transfer by writing a 1 to the corresponding bit in the event set register (ESR/ESRH). +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_TRIG_MODE_QDMA\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_TRIG_MODE_QDMA}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_TRIG_MODE_QDMA}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAHI}{\*\bkmkend AAAAAAAAHI} + Set the Trigger mode to QDMA. A QDMA transfer is triggered when a CPU (or other EDMA3 programmer) writes to the trigger word of the QDMA channel parameter set (autotriggered) or when the EDMA3CC perfo +rms a link update on a PaRAM set that has been mapped to a QDMA channel (link triggered). +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_TRIG_MODE_EVENT\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_TRIG_MODE_EVENT}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_TRIG_MODE_EVENT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAHJ}{\*\bkmkend AAAAAAAAHJ} Se +t the Trigger mode to Event. Allows for a peripheral, system, or externally-generated event to trigger a transfer request. +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_TRIG_MODE_NONE\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 +\ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_TRIG_MODE_NONE}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 +\b\i\insrsid6424133 EDMA3_DRV_TRIG_MODE_NONE}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAHK}{\*\bkmkend AAAAAAAAHK} Used to specify the trigger mode NONE +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 +\b\f1\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Function Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 +\ltrch\fcs0 \fs24\insrsid6424133 EDMA3_DRV_chainChannel\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 +\rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_chainChannel}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Result EDMA3_DRV_chainChannel (EDMA3_DRV_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int } +{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 lCh1}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 lCh2}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +, const EDMA3_DRV_ChainOptions * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 chainOptions}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAHL}{\*\bkmkend AAAAAAAAHL}Chain the two specified channels. +\par This API is used to chain two previously allocated logical (DMA/QDMA) channels. +\par Chaining + is different from Linking. The EDMA3 link feature reloads the current channel parameter set with the linked parameter set. The EDMA3 chaining feature does not modify or update any channel parameter set; it provides a synchronization event to the chained +channel. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 hEdma +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Handle to the EDMA Driver Instance. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 lCh1}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Channel to which particular channel will be chained. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 lCh2}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Channel which needs to be chained to the first channel. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 chainOptions}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Options such as intermediate interrupts are required or not, intermediate/final chaining is enabled or not etc. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_SOK or EDMA3_DRV Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +This function is re-entrant for unique lCh1 & lCh2 values. It is non-re-entrant for same lCh1 & lCh2 values. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +References EDMA3_DRV_ +E_INVALID_PARAM, EDMA3_DRV_ITCCHEN_EN, EDMA3_DRV_ITCINTEN_EN, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_OPT_ITCCHEN_CLR_MASK, EDMA3_DRV_OPT_ITCCHEN_SET_MASK, EDMA3_DRV_OPT_ITCINTEN_CLR_MASK, EDMA3_DRV_OPT_ITCINTEN_SET_MASK, EDMA3_DRV_OPT_TCC_CLR_MASK, EDMA3_DRV +_ +OPT_TCC_SET_MASK, EDMA3_DRV_OPT_TCCHEN_CLR_MASK, EDMA3_DRV_OPT_TCCHEN_SET_MASK, EDMA3_DRV_OPT_TCINTEN_CLR_MASK, EDMA3_DRV_OPT_TCINTEN_SET_MASK, EDMA3_DRV_TCCHEN_EN, EDMA3_DRV_TCINTEN_EN, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalReg +s +, EDMA3_DRV_ChainOptions::itcchEn, EDMA3_DRV_ChainOptions::itcintEn, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, EDMA3_DRV_Object::phyCtrllerInstId, EDMA3_DRV_ChainOptions::tcchEn, ED +MA3_DRV_ChainOptions::tcintEn, and EDMA3_DRV_ChBoundResources::trigMode. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_disableTransfer\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_disableTransfer}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 +\af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Result EDMA3_DRV_disableTransfer (EDMA3_DRV_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\insrsid6424133 lCh}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , EDMA3_DRV_TrigMode }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 trigMode}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAHM}{\*\bkmkend AAAAAAAAHM}Disable DMA transfer on the specified channel. +\par There are multiple ways by which an EDMA3 transfer could be triggered. The triggering mode option allows choosing from the available triggering modes: Event, Manual or QDMA. +\par To disable a channel which was previously triggered in manual mode, this API clears the Secondary Event Register and Event Miss Register, if set, for the specific DMA channel. +\par To disable a channel which was previously triggered in QDMA mode, this API clears the QDMA Even Enable Register, for the specific QDMA channel. +\par To disable a channel which was previously triggered in event mode, this API clears the Event Enable Register, Event Register, Secondary Event Register and Event Miss Register, if set, for the specific DMA channel. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 hEdma +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Handle to the EDMA Driver Instance +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 lCh}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Channel on which transfer has to be stopped +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 trigMode}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Mode of triggering start of transfer +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_SOK or EDMA3_DRV Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +References EDMA3_DRV_GblConfigParams::dmaChannelHwEvtMap, EDMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_E_INVALID_PARAM, EDMA3_D +RV_LOG_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_TRIG_MODE_EVENT, EDMA3_DRV_TRIG_MODE_MANUAL, EDMA3_DRV_TRIG_MODE_QDMA, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_Instance::pDrvObject +Handle, and EDMA3_DRV_Instance::shadowRegs. +\par Referenced by edma3RemoveMapping(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_enableTransfer\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_enableTransfer}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 +\af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Result EDMA3_DRV_enableTransfer (EDMA3_DRV_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\insrsid6424133 lCh}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , EDMA3_DRV_TrigMode }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 trigMode}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAHN}{\*\bkmkend AAAAAAAAHN}Start EDMA transfer on the specified channel. +\par There are multiple ways to trigger an EDMA3 transfer. The triggering mode option allows choosing from the available triggering modes: Event, Manual or QDMA. +\par In event triggered, a peripheral or an externally generated event triggers the transfer. This API clears the Event and Event Miss Register and then enables the DMA channel by writing to the EESR. +\par In manual triggered mode, CPU manually triggers a transfer by writing a 1 in the Event Set Register (ESR/ESRH). This API writes to the ESR/ESRH to start the transfer. +\par In QDMA triggered mode, a QDMA transfer is triggered when a CPU (or other EDMA3 programmer) writes to the trigger word of the +QDMA channel PaRAM set (auto-triggered) or when the EDMA3CC performs a link update on a PaRAM set that has been mapped to a QDMA channel (link triggered). This API enables the QDMA channel by writing to the QEESR register. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 hEdma +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Handle to the EDMA Driver Instance +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 lCh}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Channel on which transfer has to be started +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 trigMode}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Mode of triggering start of transfer (Manual, QDMA or Event) +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_SOK or EDMA3_DRV Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +References EDMA3_DRV_GblConfigParams::dmaChannelHwEvtMap, EDMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_TRIG_MODE +_EVENT, EDMA3_DRV_TRIG_MODE_MANUAL, EDMA3_DRV_TRIG_MODE_QDMA, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_Instance::pDrvObjectHandle, EDMA3_DRV_Object::phyCtrllerInstId, EDMA3_DRV_Instance::shadowRegs, and EDMA3_DRV_Ch +BoundResources::trigMode. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_getOptField\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_getOptField}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Result EDMA3_DRV_getOptField (EDMA3_DRV_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\insrsid6424133 lCh}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , EDMA3_DRV_OptField }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 optField}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\insrsid6424133 optFieldVal}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAHO}{\*\bkmkend AAAAAAAAHO}Get a particular OPT field in the PaRAM set associated with the logical channel 'lCh'. +\par This API can be used to read various optional parameters for an EDMA3 transfer. Like enable/disable completion interrupts, enable/disable chaining, setting the transfer mode (A/AB Sync), setting the FIFO width etc. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 hEdma +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Handle to the EDMA Driver Instance. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 lCh}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Logical Channel, bound to which PaRAM set OPT field is required. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 optField}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] The particular field of OPT Word that is needed +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 optFieldVal}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN/OUT] Value of the OPT field +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_SOK or EDMA3_DRV Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +This function is re-entrant. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_ +OPT_DAM_GET_MASK, EDMA3_DRV_OPT_FIELD_DAM, EDMA3_DRV_OPT_FIELD_FWID, EDMA3_DRV_OPT_FIELD_ITCCHEN, EDMA3_DRV_OPT_FIELD_ITCINTEN, EDMA3_DRV_OPT_FIELD_SAM, EDMA3_DRV_OPT_FIELD_STATIC, EDMA3_DRV_OPT_FIELD_SYNCDIM, EDMA3_DRV_OPT_FIELD_TCC, EDMA3_DRV_OPT_FIELD_ +T +CCHEN, EDMA3_DRV_OPT_FIELD_TCCMODE, EDMA3_DRV_OPT_FIELD_TCINTEN, EDMA3_DRV_OPT_FWID_GET_MASK, EDMA3_DRV_OPT_ITCCHEN_GET_MASK, EDMA3_DRV_OPT_ITCINTEN_GET_MASK, EDMA3_DRV_OPT_SAM_GET_MASK, EDMA3_DRV_OPT_STATIC_GET_MASK, EDMA3_DRV_OPT_SYNCDIM_GET_MASK, EDMA3 +_ +DRV_OPT_TCC_GET_MASK, EDMA3_DRV_OPT_TCCHEN_GET_MASK, EDMA3_DRV_OPT_TCCMODE_GET_MASK, EDMA3_DRV_OPT_TCINTEN_GET_MASK, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources +::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_setDestIndex\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_setDestIndex}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 +\af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Result EDMA3_DRV_setDestIndex (EDMA3_DRV_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\insrsid6424133 lCh}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 destBIdx}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 destCIdx}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAHP}{\*\bkmkend AAAAAAAAHP}DMA destination index setup. +\par It is used to program the destination B index and destination C index. +\par DSTBIDX is a 16-bit signed value (2s complement) used for destination addres +s modification between each array in the 2nd dimension. Valid values for DSTBIDX are between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current +frame. It applies to both A-synchronized and AB-synchronized transfers. +\par DSTCIDX is a 16-bit signed value (2s complement) used for destination address modification in the 3rd dimension. Valid values are between -32768 and 32767. It provides a byte address of +fset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array TR in the next frame. It applies to both A-synchronized and AB-synchronized transfers. Note that when DSTCIDX is applied, the current +array in an A-synchronized transfer is the last array in the frame, while the current array in a AB-synchronized transfer is the first array in the frame +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 hEdma +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Handle to the EDMA Driver Instance +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 lCh}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Logical Channel for which dest indices are to be configured +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 destBIdx}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Destination B index +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 destCIdx}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Destination C index +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_SOK or EDMA3_DRV Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +References EDM +A3_DRV_DSTBIDX_MAX_VAL, EDMA3_DRV_DSTBIDX_MIN_VAL, EDMA3_DRV_DSTCIDX_MAX_VAL, EDMA3_DRV_DSTCIDX_MIN_VAL, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX, EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX, EDMA3_DRV_Object::gblCfgP +arams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_setDestParams\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_setDestParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 +\af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Result EDMA3_DRV_setDestParams (EDMA3_DRV_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\insrsid6424133 lCh}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 destAddr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , EDMA3_DRV_AddrMode }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\insrsid6424133 addrMode}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , EDMA3_DRV_FifoWidth }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 fifoWidth}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAHQ}{\*\bkmkend AAAAAAAAHQ}DMA Destination parameters setup. +\par It is used to program the destination address, destination side addressing mode (INCR or FIFO) and the FIFO width in case the addressing mode is FIFO. +\par In FIFO Addressing mode, memory location must be 32 bytes aligned. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 hEdma +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Handle to the EDMA Driver Instance +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 lCh}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Logical Channel for which the destination parameters are to be configured +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 destAddr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Destination address +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 addrMode}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Address mode [FIFO or Increment] +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 fifoWidth}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Width of FIFO (Valid only if addrMode is FIFO) +\par }\pard\plain \ltrpar\s74\ql \fi-360\li1080\ri0\widctlpar\wrapdefault\faauto\rin0\lin1080\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 1.\tab +0 - 8 bit +\par 2.\tab 1 - 16 bit +\par 3.\tab 2 - 32 bit +\par 4.\tab 3 - 64 bit +\par 5.\tab 4 - 128 bit +\par 6.\tab 5 - 256 bit +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_SOK or EDMA3_DRV Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +In FIFO Addressing mode, memory location must be 32 bytes aligned +\par Memory is not 32 bytes aligned +\par If request is for FIFO mode, check whether the FIFO size is supported by the Transfer Controller which will be used for this transfer or not. +\par mappedEvtQ contains the event queue and hence the TC which will process this transfer request. Check whether this TC supports the FIFO size or not. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +References EDMA3_DRV_ADDR_MODE_FIFO, EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_DMAQNUM_CLR_MASK, E +DMA3_DRV_E_ADDRESS_NOT_ALIGNED, EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_OPT_DAM_CLR_MASK, EDMA3_DRV_OPT_DAM_SET_MASK, EDMA3_DRV_OPT_FWID_CLR_MASK, EDMA3_DRV_OPT_FWID_SET_MASK, EDMA3_DRV_PARAM_EN +T +RY_DST, EDMA3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_QDMAQNUM_CLR_MASK, EDMA3_DRV_W256BIT, EDMA3_DRV_W8BIT, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoun +dResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, EDMA3_DRV_Object::phyCtrllerInstId, and EDMA3_DRV_GblConfigParams::tcDefaultBurstSize. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_setOptField\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_setOptField}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Result EDMA3_DRV_setOptField (EDMA3_DRV_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\insrsid6424133 lCh}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , EDMA3_DRV_OptField }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 optField}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\insrsid6424133 newOptFieldVal}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAHR}{\*\bkmkend AAAAAAAAHR}Set a particular OPT field in the PaRAM set associated with the logical channel 'lCh'. +\par This API can be used to set various optional parameters for an EDMA3 transfer. Like enable/disable completion interrupts, enable/disable chaining, setting the transfer mode (A/AB Sync), setting the FIFO width etc. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 hEdma +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Handle to the EDMA Driver Instance. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 lCh}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Logical Channel, bound to which PaRAM set OPT field needs to be set. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 optField}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] The particular field of OPT Word that needs setting +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 newOptFieldVal}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] The new OPT field value +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_SOK or EDMA3_DRV Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_OPT_DAM_CLR_MASK, EDMA3_DRV_OPT_DAM_SET_MASK, EDMA3_DRV_OPT_FIELD_DAM, EDMA3_DRV_OP +T_FIELD_FWID, EDMA3_DRV_OPT_FIELD_ITCCHEN, EDMA3_DRV_OPT_FIELD_ITCINTEN, EDMA3_DRV_OPT_FIELD_SAM, EDMA3_DRV_OPT_FIELD_STATIC, EDMA3_DRV_OPT_FIELD_SYNCDIM, EDMA3_DRV_OPT_FIELD_TCC, EDMA3_DRV_OPT_FIELD_TCCHEN, EDMA3_DRV_OPT_FIELD_TCCMODE, EDMA3_DRV_OPT_FIEL +D +_TCINTEN, EDMA3_DRV_OPT_FWID_CLR_MASK, EDMA3_DRV_OPT_FWID_SET_MASK, EDMA3_DRV_OPT_ITCCHEN_CLR_MASK, EDMA3_DRV_OPT_ITCCHEN_SET_MASK, EDMA3_DRV_OPT_ITCINTEN_CLR_MASK, EDMA3_DRV_OPT_ITCINTEN_SET_MASK, EDMA3_DRV_OPT_SAM_CLR_MASK, EDMA3_DRV_OPT_SAM_SET_MASK, E +D +MA3_DRV_OPT_STATIC_CLR_MASK, EDMA3_DRV_OPT_STATIC_SET_MASK, EDMA3_DRV_OPT_SYNCDIM_CLR_MASK, EDMA3_DRV_OPT_SYNCDIM_SET_MASK, EDMA3_DRV_OPT_TCC_CLR_MASK, EDMA3_DRV_OPT_TCC_SET_MASK, EDMA3_DRV_OPT_TCCHEN_CLR_MASK, EDMA3_DRV_OPT_TCCHEN_SET_MASK, EDMA3_DRV_OPT +_ +TCCMODE_CLR_MASK, EDMA3_DRV_OPT_TCCMODE_SET_MASK, EDMA3_DRV_OPT_TCINTEN_CLR_MASK, EDMA3_DRV_OPT_TCINTEN_SET_MASK, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::p +aRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_setSrcIndex\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_setSrcIndex}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Result EDMA3_DRV_setSrcIndex (EDMA3_DRV_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\insrsid6424133 lCh}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 srcBIdx}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 srcCIdx}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAHS}{\*\bkmkend AAAAAAAAHS}DMA source index setup. +\par It is used to program the source B index and source C index. +\par SRCBIDX is a 16-bit signed value (2s complement) used for source address modification between each +array in the 2nd dimension. Valid values for SRCBIDX are between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-synchronized and AB-synchronized tr +ansfers. +\par SRCCIDX is a 16-bit signed value (2s complement) used for source address modification in the 3rd dimension. Valid values for SRCCIDX are between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to + by SRC address) to the beginning of the first source array in the next frame. It applies to both A-synchronized and AB-synchronized transfers. Note that when SRCCIDX is applied, the current array in an A-synchronized transfer is the last array in the fra +me, while the current array in an AB-synchronized transfer is the first array in the frame. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 hEdma +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Handle to the EDMA Driver Instance +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 lCh}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Logical Channel for which source indices are to be configured +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 srcBIdx}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Source B index +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 srcCIdx}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Source C index +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_SOK or EDMA3_DRV Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX, EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX, EDMA3_DRV_SRCBIDX_MAX_VAL, EDMA3_DRV_SRCBIDX_MIN_VAL, EDMA3_DRV_SRCCIDX_MAX_VAL, EDMA3_DRV_SRCCIDX_MIN_VAL, EDMA3_DRV_O +bject::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_setSrcParams\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_setSrcParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 +\af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Result EDMA3_DRV_setSrcParams (EDMA3_DRV_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\insrsid6424133 lCh}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 srcAddr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , EDMA3_DRV_AddrMode }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\insrsid6424133 addrMode}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , EDMA3_DRV_FifoWidth }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 fifoWidth}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAHT}{\*\bkmkend AAAAAAAAHT}DMA source parameters setup. +\par It is used to program the source address, source side addressing mode (INCR or FIFO) and the FIFO width in case the addressing mode is FIFO. +\par In FIFO Addressing mode, memory location must be 32 bytes aligned. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 hEdma +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Handle to the EDMA Driver Instance +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 lCh}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Logical Channel for which the source parameters are to be configured +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 srcAddr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Source address +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 addrMode}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Address mode [FIFO or Increment] +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 fifoWidth}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Width of FIFO (Valid only if addrMode is FIFO) +\par }\pard\plain \ltrpar\s74\ql \fi-360\li1080\ri0\widctlpar\wrapdefault\faauto\rin0\lin1080\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 1.\tab +0 - 8 bit +\par 2.\tab 1 - 16 bit +\par 3.\tab 2 - 32 bit +\par 4.\tab 3 - 64 bit +\par 5.\tab 4 - 128 bit +\par 6.\tab 5 - 256 bit +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_SOK or EDMA3_DRV Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +In FIFO Addressing mode, memory location must be 32 bytes aligned +\par Memory is not 32 bytes aligned +\par If request is for FIFO mode, check whether the FIFO size is supported by the Transfer Controller which will be used for this transfer or not. +\par mappedEvtQ contains the event queue and hence the TC which will process this transfer request. Check whether this TC supports the FIFO size or not. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +References EDMA3_DRV_ADDR_MODE_FIFO, EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_DMAQNUM_CLR_MASK, EDMA3_DRV_E_ADDRESS_NOT_ALIGNED, EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_OPT_ +F +WID_CLR_MASK, EDMA3_DRV_OPT_FWID_SET_MASK, EDMA3_DRV_OPT_SAM_CLR_MASK, EDMA3_DRV_OPT_SAM_SET_MASK, EDMA3_DRV_PARAM_ENTRY_SRC, EDMA3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_QDMAQNUM_CLR_MASK, EDMA3_DRV_W256BIT, EDMA3_DRV_W8BIT, EDMA3_DRV_ +O +bject::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, EDMA3_DRV_Object::phyCtrllerInstId, and EDMA3_DRV_GblConfigParams::tcDefaultBur +stSize. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_setTransferParams\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_setTransferParams}}}\sectd \linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Result EDMA3_DRV_setTransferParams (EDMA3_DRV_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 +\ltrch\fcs0 \i\insrsid6424133 lCh}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 aCnt}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\insrsid6424133 bCnt}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 cCnt}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\insrsid6424133 bCntReload}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , EDMA3_DRV_SyncType }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 syncType}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAHU}{\*\bkmkend AAAAAAAAHU}DMA transfer parameters setup. +\par It is used to specify the various counts (ACNT, BCNT and CCNT), B count reload and the synchronization type +\par ACNT represent +s the number of bytes within the 1st dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K - 1 bytes). ACNT must be greater than or equal to 1 + for a TR to be submitted to EDMA3 Transfer Controller. An ACNT equal to 0 is considered either a null or dummy transfer. A dummy or null transfer generates a completion code depending on the settings of the completion bit fields in OPT. +\par BCNT is a 16-bit un +signed value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT are between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K - 1 arrays). A BCNT equal to 0 is considered either a nu +ll or dummy transfer. A dummy or null transfer generates a completion code depending on the settings of the completion bit fields in OPT. +\par CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT are between 1 and + 65535. Therefore, the maximum number of frames in a block is 65535 (64K - 1 frames). A CCNT equal to 0 is considered either a null or dummy transfer. A dummy or null transfer generates a completion code depending on the settings of the completion bit fie +lds in OPT. A CCNT value of 0 is considered either a null or dummy transfer. +\par BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-synchronized transfers. In t +his case, the EDMA3CC decrements the BCNT value by 1 on each TR submission. When BCNT (conceptually) reaches 0, the EDMA3CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the EDMA3CC submits the B +CNT in the TR and the EDMA3TC decrements BCNT appropriately. For AB-synchronized transfers, BCNTRLD is not used. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 hEdma +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Handle to the EDMA Driver Instance +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 lCh}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Logical Channel for which transfer parameters are to be configured +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 aCnt}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Count for 1st Dimension. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 bCnt}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Count for 2nd Dimension. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 cCnt}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Count for 3rd Dimension. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 bCntReload}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Reload value for bCnt. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 syncType}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Transfer synchronization dimension 0: A-synchronized. Each event triggers the transfer of a single arr +ay of ACNT bytes. 1: AB-synchronized. Each event triggers the transfer of BCNT arrays of ACNT bytes. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_SOK or EDMA3_DRV Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenc +es EDMA3_DRV_ACNT_MAX_VAL, EDMA3_DRV_BCNT_MAX_VAL, EDMA3_DRV_BCNTRELD_MAX_VAL, EDMA3_DRV_CCNT_MAX_VAL, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_OPT_SYNCDIM_CLR_MASK, EDMA3_DRV_OPT_SYNCDIM_SET_MASK, EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT, ED +M +A3_DRV_PARAM_ENTRY_CCNT, EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD, EDMA3_DRV_SYNC_A, EDMA3_DRV_SYNC_AB, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DR +V_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_unchainChannel\:Edma3DrvTransferSetupType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupType\:EDMA3_DRV_unchainChannel}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 +\af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Result EDMA3_DRV_unchainChannel (EDMA3_DRV_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\insrsid6424133 lCh}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAHV}{\*\bkmkend AAAAAAAAHV}Unchain the two channels. +\par +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 hEdma +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Handle to the EDMA Driver Instance. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 lCh}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Channel whose chaining with the other channel has to be removed. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_SOK or EDMA3_DRV Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_OPT_ITCCHEN_CLR_MASK, EDMA3_DRV_OPT_TCCHEN_CLR_MASK, EDMA3_DRV_Object::gblCfgParams, EDM +A3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3 Driver Optional Setup for EDMA +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 \tcl2{\*\bkmkstart _Toc211937256}EDMA3 Driver Optional Setup for EDMA{\*\bkmkend _Toc211937256}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3 Driver Optional Setup for EDMA}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAHW}{\*\bkmkend AAAAAAAAHW}Data Structures +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ParamentryRegs}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 EDMA3 PaRAM Set. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PaRAMRegs}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 EDMA3 Parameter RAM Set in User Configurable format. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_EvtQuePriority}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Event queue priorities setup. +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Enumerations +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PaRAMEntry}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PARAM_ENTRY_OPT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 0, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PARAM_ENTRY_SRC}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 1, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 = 2, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PARAM_ENTRY_DST}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 3, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 = 4, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 5, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 +EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 6, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PARAM_ENTRY_CCNT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 7 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 PaRAM Set Entry type. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PaRAMField}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PARAM_FIELD_OPT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 0, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PARAM_FIELD_SRCADDR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 1, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PARAM_FIELD_ACNT}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 = 2, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PARAM_FIELD_BCNT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 3, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PARAM_FIELD_DESTADDR}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 = 4, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PARAM_FIELD_SRCBIDX}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 5, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 +EDMA3_DRV_PARAM_FIELD_DESTBIDX}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 6, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PARAM_FIELD_LINKADDR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 7, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 EDMA3_DRV_PARAM_FIELD_BCNTRELOAD}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 8, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PARAM_FIELD_SRCCIDX}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 9, }{\rtlch\fcs1 +\ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PARAM_FIELD_DESTCIDX}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 10, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PARAM_FIELD_CCNT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 11 +\} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 PaRAM Set Field type. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_IoctlCmd}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_IOCTL_MIN_IOCTL}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 0, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_IOCTL_MAX_IOCTL}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 EDMA3 Driver IOCTL commands. +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Functions +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setQdmaTrigWord}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_RM_QdmaTrigWord trigWord) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Assign a Trigger Word to the specified QDMA channel. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setPaRAM}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PaRAMRegs +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 *newPaRAM) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Copy the user specified PaRAM Set onto the PaRAM Set associated with the logical channel (DMA/QDMA/Link). +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_getPaRAM}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PaRAMRegs}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 *currPaRAM) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Retrieve existing PaRAM set associated with specified logical channel (DMA/QDMA/Link). +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setPaRAMEntry}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PaRAMEntry +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 paRAMEntry, unsigned int newPaRAMEntryVal) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Set a particular PaRAM set entry of the specified PaRAM set. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_getPaRAMEntry}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PaRAMEntry +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 paRAMEntry, unsigned int *paRAMEntryVal) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Get a particular PaRAM set entry of the specified PaRAM set. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setPaRAMField}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PaRAMField +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 paRAMField, unsigned int newPaRAMFieldVal) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Set a particular PaRAM set field of the specified PaRAM set. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_getPaRAMField}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PaRAMField +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 paRAMField, unsigned int *currPaRAMFieldVal) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Get a particular PaRAM set field of the specified PaRAM set. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setEvtQPriority}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_EvtQuePriority}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 *evtQPriObj) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Sets EDMA TC priority. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_mapChToEvtQ}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int channelId, EDMA3_RM_EventQueue eventQ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Associate Channel to Event Queue. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_getMapChToEvtQ}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int channelId, unsigned int *mappedEvtQ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Get the Event Queue mapped to the specified DMA/QDMA channel. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setCCRegister}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int regOffset, unsigned int newRegValue) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Set the Channel Controller (CC) Register value. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_getCCRegister}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int regOffset, unsigned int *regValue) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Get the Channel Controller (CC) Register value. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_waitAndClearTcc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int tccNo) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Wait for a transfer completion interrupt to occur and clear it. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_checkAndClearTcc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int tccNo, unsigned short *tccStatus) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Returns the status of a previously initiated transfer. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_getPaRAMPhyAddr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int *paramPhyAddr) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Get the PaRAM Set Physical Address associated with a logical channel. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_Ioctl}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_IoctlCmd}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 cmd, void *cmdArg, void *param) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 EDMA3 Driver IOCTL. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Handle }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_getInstHandle}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (unsigned int phyCtrllerInstId, EDMA3_RM_RegionId regionId, EDMA3_DRV_Result *errorCode) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Return the previously opened EDMA3 Driver Instance handle. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 Transfer. +\par The Optional EDMA transfer related Interface of the EDMA3 Driver +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Enumeration Type Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 EDMA3_DRV_IoctlCmd\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 Edma3DrvTransferSetupOpt\:EDMA3_DRV_IoctlCmd}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +enum EDMA3_DRV_IoctlCmd +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAHX}{\*\bkmkend AAAAAAAAHX}EDMA3 Driver IOCTL commands. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 +\par Enumerator: }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn +\pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\: +EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAHY} +{\*\bkmkend AAAAAAAAHY} PaRAM Sets will be cleared OR will not be cleared during allocation, depending upon this option. +\par For e.g., To clear the PaRAM Sets during allocation, cmdArg = (void *)1; +\par To NOT clear the PaRAM Sets during allocation, cmdArg = (void *)0; +\par For all other values, it will return error. +\par By default, PaRAM Sets will be cleared during allocation. Note: Since this enum can change the behavior how the resources are ini +tialized during their allocation, user is adviced to not use this command while allocating the resources. User should first change the behavior of resources' initialization and then should use start allocating resources. +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn +\pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\: +EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAHZ} +{\*\bkmkend AAAAAAAAHZ} To check whether PaRAM Sets will be cleared or not during allocation. If the value read is + '1', it means that PaRAM Sets are getting cleared during allocation. If the value read is '0', it means that PaRAM Sets are NOT getting cleared during allocation. +\par For e.g., unsigned short isParamClearingDone; cmdArg = +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_PaRAMEntry\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\:EDMA3_DRV_PaRAMEntry}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +enum EDMA3_DRV_PaRAMEntry +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAIA}{\*\bkmkend AAAAAAAAIA}PaRAM Set Entry type. +\par Use this enum to set or get any of the 8 DWords(unsigned int) within a Parameter RAM set +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 Enumerator: }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_PARAM_ENTRY_OPT\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\:EDMA3_DRV_PARAM_ENTRY_OPT}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 EDMA3_DRV_PARAM_ENTRY_OPT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAIB}{\*\bkmkend AAAAAAAAIB} The OPT field (Offset Address 0x0 Bytes) +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_PARAM_ENTRY_SRC\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\:EDMA3_DRV_PARAM_ENTRY_SRC}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 EDMA3_DRV_PARAM_ENTRY_SRC}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAIC}{\*\bkmkend AAAAAAAAIC} The SRC field (Offset Address 0x4 Bytes) +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0 +\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\:EDMA3_DRV_PARAM_ENTRY_ +ACNT_BCNT}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAID}{\*\bkmkend AAAAAAAAID} + The (ACNT+BCNT) field (Offset Address 0x8 Bytes) +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_PARAM_ENTRY_DST\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\:EDMA3_DRV_PARAM_ENTRY_DST}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 EDMA3_DRV_PARAM_ENTRY_DST}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAIE}{\*\bkmkend AAAAAAAAIE} The DST field (Offset Address 0xC Bytes) +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0 +\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\: +EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAIF} +{\*\bkmkend AAAAAAAAIF} The (SRCBIDX+DSTBIDX) field (Offset Address 0x10 Bytes) +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0 +\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\: +EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAIG} +{\*\bkmkend AAAAAAAAIG} The (LINK+BCNTRLD) field (Offset Address 0x14 Bytes) +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0 +\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\: +EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAIH} +{\*\bkmkend AAAAAAAAIH} The (SRCCIDX+DSTCIDX) field (Offset Address 0x18 Bytes) +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_PARAM_ENTRY_CCNT\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\:EDMA3_DRV_PARAM_ENTRY_CCNT}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 EDMA3_DRV_PARAM_ENTRY_CCNT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAII}{\*\bkmkend AAAAAAAAII} + The (CCNT+RSVD) field (Offset Address 0x1C Bytes) +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_PaRAMField\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\:EDMA3_DRV_PaRAMField}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +enum EDMA3_DRV_PaRAMField +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAIJ}{\*\bkmkend AAAAAAAAIJ}PaRAM Set Field type. +\par Use this enum to set or get any of the PaRAM set fields +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 Enumerator: }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_PARAM_FIELD_OPT\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\:EDMA3_DRV_PARAM_FIELD_OPT}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 EDMA3_DRV_PARAM_FIELD_OPT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAIK}{\*\bkmkend AAAAAAAAIK} OPT field of PaRAM Set +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_PARAM_FIELD_SRCADDR\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0 +\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\:EDMA3_DRV_PARAM_FIELD_SRCADDR +}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 EDMA3_DRV_PARAM_FIELD_SRCADDR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAIL}{\*\bkmkend AAAAAAAAIL} + Starting byte address of Source For FIFO mode, srcAddr must be a 256-bit aligned address. +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_PARAM_FIELD_ACNT\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\:EDMA3_DRV_PARAM_FIELD_ACNT}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 EDMA3_DRV_PARAM_FIELD_ACNT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAIM}{\*\bkmkend AAAAAAAAIM} Number of bytes in each Array (ACNT). +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_PARAM_FIELD_BCNT\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\:EDMA3_DRV_PARAM_FIELD_BCNT}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 EDMA3_DRV_PARAM_FIELD_BCNT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAIN}{\*\bkmkend AAAAAAAAIN} Number of Arrays in each Frame (BCNT). +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_PARAM_FIELD_DESTADDR\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0 +\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\: +EDMA3_DRV_PARAM_FIELD_DESTADDR}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 EDMA3_DRV_PARAM_FIELD_DESTADDR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAIO}{\*\bkmkend AAAAAAAAIO} + Starting byte address of destination For FIFO mode, destAddr must be a 256-bit aligned address. +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_PARAM_FIELD_SRCBIDX\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0 +\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\:EDMA3_DRV_PARAM_FIELD_SRCBIDX +}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 EDMA3_DRV_PARAM_FIELD_SRCBIDX}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAIP}{\*\bkmkend AAAAAAAAIP} Inde +x between consec. arrays of a Source Frame (SRCBIDX) If SAM is set to 1 (via channelOptions) then srcInterArrIndex should be an even multiple of 32 bytes. +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_PARAM_FIELD_DESTBIDX\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0 +\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\:EDMA3_DRV +_PARAM_FIELD_DESTBIDX}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 EDMA3_DRV_PARAM_FIELD_DESTBIDX}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAIQ}{\*\bkmkend AAAAAAAAIQ} + Index between consec. arrays of a Destination Frame (DSTBIDX) If DAM is set to 1 (via channelOptions) then destInterArrIndex should be an even multiple of 32 bytes. +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_PARAM_FIELD_LINKADDR\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0 +\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\: +EDMA3_DRV_PARAM_FIELD_LINKADDR}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 EDMA3_DRV_PARAM_FIELD_LINKADDR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAIR}{\*\bkmkend AAAAAAAAIR} + Address for linking (AutoReloading of a PaRAM Set) This must point to a valid aligned 32-byte PaRAM set A value of 0xFFFF means no linking Linking is especially useful for use with ping-pong buffers and circular buffers. +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_PARAM_FIELD_BCNTRELOAD\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0 +\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\: +EDMA3_DRV_PARAM_FIELD_BCNTRELOAD}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 EDMA3_DRV_PARAM_FIELD_BCNTRELOAD}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAIS}{\*\bkmkend AAAAAAAAIS} + Reload value of the numArrInFrame (BCNT) Relevant only for A-sync transfers. +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_PARAM_FIELD_SRCCIDX\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0 +\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\:EDMA3_DRV_PARAM_FIELD_SRCCIDX +}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 EDMA3_DRV_PARAM_FIELD_SRCCIDX}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAIT}{\*\bkmkend AAAAAAAAIT} + Index between consecutive frames of a Source Block (SRCCIDX). +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_PARAM_FIELD_DESTCIDX\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0 +\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\: +EDMA3_DRV_PARAM_FIELD_DESTCIDX}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 EDMA3_DRV_PARAM_FIELD_DESTCIDX}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAIU}{\*\bkmkend AAAAAAAAIU} + Index between consecutive frames of a Dest Block (DSTCIDX). +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_PARAM_FIELD_CCNT\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\:EDMA3_DRV_PARAM_FIELD_CCNT}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 EDMA3_DRV_PARAM_FIELD_CCNT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAIV}{\*\bkmkend AAAAAAAAIV} Number of Frames in a block (CCNT). +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Function Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 EDMA3_DRV_checkAndClearTcc\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 Edma3DrvTransferSetupOpt\:EDMA3_DRV_checkAndClearTcc}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_DRV_Result EDMA3_DRV_checkAndClearTcc (EDMA3_DRV_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 +tccNo}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned short * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 tccStatus}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAIW}{\*\bkmkend AAAAAAAAIW}Returns the status of a previously initiated transfer. +\par This is a non-blocking function that returns the status of a previously initiated transfer, based on the IPR/IPRH bit. This bit corresponds to the tccNo specified by the user. It clears the corresponding bit, if SET, while returning also. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Handle to the EDMA Driver Instance +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 tccNo}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] TCC, specific to which the function checks the status of the IPR/IPRH bit. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 tccStatus}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN/OUT] Status of the transfer is returned here. Returns "TRUE" if the transfer has completed (IPR/IPRH bit SET), "F +ALSE" if the transfer has not completed successfully (IPR/IPRH bit NOT SET). +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_SOK or EDMA3_DRV Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 This function is re-entrant for different tccNo. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_Object::gblCfgParams, EDMA3_ +DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numTccs, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Instance::regionId. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_getCCRegister\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\:EDMA3_DRV_getCCRegister}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3 +_DRV_Result EDMA3_DRV_getCCRegister (EDMA3_DRV_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 regOffset}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 , unsigned int * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 regValue}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAIX}{\*\bkmkend AAAAAAAAIX}Get the Channel Controller (CC) Register value. +\par +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Handle to the EDMA Driver Instance +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 regOffset}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] CC Register offset whose value is needed +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 regValue}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN/OUT] CC Register Value +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_SOK or EDMA3_DRV Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 This function is re-entrant. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, and EDMA3_DRV_Instance::pDrvObjectHandle. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_getInstHandle\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\:EDMA3_DRV_getInstHandle}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Handle EDMA3_DRV_getInstHandle (unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 phyCtrllerInstId}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , EDMA3_RM_RegionId }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 regionId}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , EDMA3_DRV_Result * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 errorCode}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAIY}{\*\bkmkend AAAAAAAAIY}Return the previously opened EDMA3 Driver Instance handle. +\par This API is used to return the previously opened EDMA3 Driver's Instance Handle (region specific), which could be used to call ot +her EDMA3 Driver APIs. Since EDMA3 Driver does not allow multiple instances, for a single shadow region, this API is provided. This API is meant for users who DO NOT want to / could not open a new Driver Instance and hence re-use the existing Driver Insta +nce to allocate EDMA3 resources and use various other EDMA3 Driver APIs. +\par In case the Driver Instance is not yet opened, NULL is returned as the function return value whereas EDMA3_DRV_E_INST_NOT_OPENED is returned in the errorCode. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid6424133 phyCtrllerInstId}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] EDMA3 Controller Instance Id (Hardware instance id, starting from 0). +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 regionId}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Shadow Region id for which the previously opened driver's instance handle is required. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 errorCode}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [OUT] Error code while returning Driver Instance Handle. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Handle : If successful, this API will return the driver's instance handle. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 1) This API returns the previously opened EDMA3 Driver's Instance handle. The instance, if exists, could have been opened by some other user (most pro +bably) or may be by the same user calling this API. If it was opened by some other user, then that user can very well close this instance anytime, without even knowing that the same instance handle is being used by other users as well. In that case, the h +andle becomes INVALID and user has to open a valid driver instance for his/her use. +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 2) This function is re-entrant. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 References EDMA3_DRV_E_INST_NOT_OPENED, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::numRegions, and EDMA3_DRV_Instance::pDrvObjectHandle. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_getMapChToEvtQ\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\:EDMA3_DRV_getMapChToEvtQ}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result EDMA3_DRV_getMapChToEvtQ (EDMA3_DRV_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 channelId}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 mappedEvtQ}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAIZ}{\*\bkmkend AAAAAAAAIZ}Get the Event Queue mapped to the specified DMA/QDMA channel. +\par +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Handle to the EDMA Driver Instance +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 channelId}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Logical Channel whose associated Event Queue is needed +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 mappedEvtQ}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN/OUT] The Event Queue which is mapped to the DMA/QDMA channel +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_SOK or EDMA3_DRV Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 This function is re-entrant. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 References EDMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_DMAQNUM_CLR_MASK, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDM +A3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_QDMAQNUM_CLR_MASK, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, and EDMA3_DRV_Instance::pDrvObjectHandle. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_getPaRAM\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\:EDMA3_DRV_getPaRAM}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result EDMA3_DRV_getPaRAM (EDMA3_DRV_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 lCh}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 , EDMA3_DRV_PaRAMRegs * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 currPaRAM}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAJA}{\*\bkmkend AAAAAAAAJA}Retrieve existing PaRAM set associated with specified logical channel (DMA/QDMA/Link). +\par +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Handle to the EDMA Instance object +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 lCh}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Logical Channel whose PaRAM set is requested +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 currPaRAM}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN/OUT] User gets the existing PaRAM here +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_SOK or EDMA3_DRV Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 This function is re-entrant. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, edma3MemCpy(), EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObj +ectHandle, and EDMA3_DRV_Object::phyCtrllerInstId. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_getPaRAMEntry\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\:EDMA3_DRV_getPaRAMEntry}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result EDMA3_DRV_getPaRAMEntry (EDMA3_DRV_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 lCh}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 , EDMA3_DRV_PaRAMEntry }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 paRAMEntry}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 paRAMEntryVal}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAJB}{\*\bkmkend AAAAAAAAJB}Get a particular PaRAM set entry of the specified PaRAM set. +\par +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Handle to the EDMA Driver Instance +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 lCh}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Logical Channel bound to the Parameter RAM set whose specified field value is needed +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 paRAMEntry}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Specify the PaRAM set entry which needs to be obtained +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 paRAMEntryVal}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN/OUT] The value of the field is returned here +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_SOK or EDMA3_DRV Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 This function is re-entrant. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_PARAM_ENTRY_CCNT, EDMA3_DRV_PARAM_ENTRY_OPT, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBound +Resources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_getPaRAMField\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\:EDMA3_DRV_getPaRAMField}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result EDMA3_DRV_getPaRAMField (EDMA3_DRV_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 lCh}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 , EDMA3_DRV_PaRAMField }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 paRAMField}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 currPaRAMFieldVal}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAJC}{\*\bkmkend AAAAAAAAJC}Get a particular PaRAM set field of the specified PaRAM set. +\par +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Handle to the EDMA Driver Instance +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 lCh}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Logical Channel bound to the PaRAM set whose specified field value is needed +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 paRAMField}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Specify the PaRAM set field which needs to be obtained +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 currPaRAMFieldVal}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN/OUT] The value of the field is returned here +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_SOK or EDMA3_DRV Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 This function is re-entrant. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT, EDMA3_DRV_PARAM_ENTRY_CCNT, EDMA3_DRV_PARAM_ENTRY_DST, EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD, EDMA3_DRV_PARAM_EN +TRY_OPT, EDMA3_DRV_PARAM_ENTRY_SRC, EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX, EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX, EDMA3_DRV_PARAM_FIELD_ACNT, EDMA3_DRV_PARAM_FIELD_BCNT, EDMA3_DRV_PARAM_FIELD_BCNTRELOAD, EDMA3_DRV_PARAM_FIELD_CCNT, EDMA3_DRV_PARAM_FIELD_DESTADD +R +, EDMA3_DRV_PARAM_FIELD_DESTBIDX, EDMA3_DRV_PARAM_FIELD_DESTCIDX, EDMA3_DRV_PARAM_FIELD_LINKADDR, EDMA3_DRV_PARAM_FIELD_OPT, EDMA3_DRV_PARAM_FIELD_SRCADDR, EDMA3_DRV_PARAM_FIELD_SRCBIDX, EDMA3_DRV_PARAM_FIELD_SRCCIDX, EDMA3_DRV_Object::gblCfgParams, EDMA3 +_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_getPaRAMPhyAddr\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\:EDMA3_DRV_getPaRAMPhyAddr}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result EDMA3_DRV_getPaRAMPhyAddr (EDMA3_DRV_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 lCh}{\rtlch\fcs1 +\af1 \ltrch\fcs0 \insrsid6424133 , unsigned int * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 paramPhyAddr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAJD}{\*\bkmkend AAAAAAAAJD}Get the PaRAM Set Physical Address associated with a logical channel. +\par This function returns the PaRAM Set Phy Address (unsigned 32 bits). The returned address could be used by the advanced users to program the PaRAM Set directly without using any APIs. +\par Least significant 16 bits of this address could be used to program the LINK field in the PaRAM Set. Users which program the LINK field directly SHOULD use this API to get the associated PaRAM Set address with the LINK channel. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Handle to the EDMA Driver Instance +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 lCh}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Logical Channel for which the PaRAM set physical address is required +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 paramPhyAddr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN/OUT] PaRAM Set physical address is returned here. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_SOK or EDMA3_DRV Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 This function is re-entrant. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3 +_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Ioctl\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\:EDMA3_DRV_Ioctl}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result EDMA3_DRV_Ioctl (EDMA3_DRV_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , EDMA3_DRV_IoctlCmd }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 cmd}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 , void * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 cmdArg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , void * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 param}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAJE}{\*\bkmkend AAAAAAAAJE}EDMA3 Driver IOCTL. +\par This function provides IOCTL functionality for EDMA3 Driver. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Handle to the EDMA Driver Instance +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 cmd}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] IOCTL command to be performed +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 cmdArg}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN/OUT] IOCTL command argument (if any) +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 param}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN/OUT] Device/Cmd specific argument +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_SOK or EDMA3_DRV Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 For 'EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION', this function is re-entrant. For 'EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION', this function is re-entrant for different EDMA3 Driver Instances (handles). +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 This function provides IOCTL functionality for EDMA3 Driver. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Handle to the EDMA Driver Instance +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 cmd}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] IOCTL command to be performed +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 cmdArg}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN/OUT] IOCTL command argument (if any) +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 param}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN/OUT] Device/Cmd specific argument +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_SOK or EDMA3_DRV Error Code +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION, EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION, and EDMA3_DRV_Instance::resMgrInstance. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_mapChToEvtQ\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\:EDMA3_DRV_mapChToEvtQ}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result EDMA3_DRV_mapChToEvtQ (EDMA3_DRV_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 channelId}{\rtlch\fcs1 +\af1 \ltrch\fcs0 \insrsid6424133 , EDMA3_RM_EventQueue }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 eventQ}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAJF}{\*\bkmkend AAAAAAAAJF}Associate Channel to Event Queue. +\par +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Handle to the EDMA Driver Instance +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 channelId}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Logical Channel to which the Event Queue is to be mapped +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 eventQ}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] The Event Queue which is to be mapped to the DMA channel +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_SOK or EDMA3_DRV Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 There should not be any data transfer going on while setting the mapping. Results could be unpredictable. +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 This function disables the global interrupts while modifying the global CC Registers, to make it re-entrant. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 References EDMA3_DRV_DMA_CH_MAX_VAL, EDM +A3_DRV_DMAQNUM_CLR_MASK, EDMA3_DRV_DMAQNUM_SET_MASK, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_QDMAQNUM_CLR_MASK, EDMA3_DRV_QDMAQNUM_SET_MASK, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::glob +alRegs, EDMA3_DRV_GblConfigParams::numEvtQueue, and EDMA3_DRV_Instance::pDrvObjectHandle. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_setCCRegister\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\:EDMA3_DRV_setCCRegister}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result EDMA3_DRV_setCCRegister (EDMA3_DRV_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 regOffset}{\rtlch\fcs1 +\af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 newRegValue}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAJG}{\*\bkmkend AAAAAAAAJG}Set the Channel Controller (CC) Register value. +\par +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Handle to the EDMA Driver Instance +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 regOffset}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] CC Register offset whose value needs to be set +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 newRegValue}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] New CC Register Value +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_SOK or EDMA3_DRV Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 This function is non re-entrant for users using the same EDMA handle i.e. working on the same shadow region. Before modifying a register, it tries to acquire a sema +phore (Driver instance specific), to protect simultaneous modification of the same register by two different users. After the successful change, it releases the semaphore. For users working on different shadow regions, thus different EDMA handles, this fu +nction is re-entrant. +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Take the instance specific semaphore, to prevent simultaneous access to the shared resources. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 References EDMA3_DRV_Instance::drvSemHandle, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, and EDMA3_DRV_Instance::pDrvObjectHandle. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_setEvtQPriority\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\:EDMA3_DRV_setEvtQPriority}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result EDMA3_DRV_setEvtQPriority (EDMA3_DRV_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , const EDMA3_DRV_EvtQuePriority * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 +evtQPriObj}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAJH}{\*\bkmkend AAAAAAAAJH}Sets EDMA TC priority. +\par User can program the priority of the Event Queues at a system-wide level. This means that the user can set the priority of an IO initiated by either of the TCs (Transfer Ctrllers) relative to I +O initiated by the other bus masters on the device (ARM, DSP, USB, etc) +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Handle to the EDMA Driver Instance +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 evtQPriObj}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Priority of the Event Queues +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_SOK or EDMA3_DRV Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 This function disables the global interrupts while modifying the global CC Registers, to make it re-entrant. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_QPRIORITY_MAX_VAL, EDMA3_DRV_EvtQuePriority::evtQPri, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_Gb +lConfigParams::globalRegs, and EDMA3_DRV_Instance::pDrvObjectHandle. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_setPaRAM\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\:EDMA3_DRV_setPaRAM}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result EDMA3_DRV_setPaRAM (EDMA3_DRV_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 lCh}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 , const EDMA3_DRV_PaRAMRegs * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 newPaRAM}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAJI}{\*\bkmkend AAAAAAAAJI}Copy the user specified PaRAM Set onto the PaRAM Set associated with the logical channel (DMA/QDMA/Link). +\par This API takes a PaRAM Set as input and copies it onto the actual PaRAM Set associated with the logical channel. OPT field of the PaRAM Set is written first and the CCNT field is written last. +\par Caution: It should be used carefully when programming the QDMA channels whose trigger words are not CCNT field. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Handle to the EDMA Instance object +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 lCh}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Logical Channel for which new PaRAM set is specified +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 newPaRAM}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Parameter RAM set to be copied onto existing PaRAM +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_SOK or EDMA3_DRV Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, edma3MemCpy(), EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAM +Id, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_setPaRAMEntry\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\:EDMA3_DRV_setPaRAMEntry}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result EDMA3_DRV_setPaRAMEntry (EDMA3_DRV_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 lCh}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 , EDMA3_DRV_PaRAMEntry }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 paRAMEntry}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 newPaRAMEntryVal}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAJJ}{\*\bkmkend AAAAAAAAJJ}Set a particular PaRAM set entry of the specified PaRAM set. +\par +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Handle to the EDMA Driver Instance +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 lCh}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Logical Channel bound to the Parameter RAM set whose specified field needs to be set +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 paRAMEntry}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Specify the PaRAM set entry which needs to be set +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 newPaRAMEntryVal}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] The new field setting +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_SOK or EDMA3_DRV Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 +This API should be used while setting the PaRAM set entry for QDMA channels. If EDMA3_DRV_setPaRAMField () used, it will trigger the QDMA channel before complete PaRAM set entry is written. For DMA channels, no such constraint is there. +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_PARAM_ENTRY_CCNT, EDMA3_DRV_PARAM_ENTRY_OPT, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::glo +balRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_setPaRAMField\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\:EDMA3_DRV_setPaRAMField}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result EDMA3_DRV_setPaRAMField (EDMA3_DRV_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 lCh}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 , EDMA3_DRV_PaRAMField }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 paRAMField}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 newPaRAMFieldVal}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAJK}{\*\bkmkend AAAAAAAAJK}Set a particular PaRAM set field of the specified PaRAM set. +\par +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Handle to the EDMA Driver Instance +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 lCh}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Logical Channel bound to the PaRAM set whose specified field needs to be set +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 paRAMField}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Specify the PaRAM set field which needs to be set +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 newPaRAMFieldVal}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] The new field setting +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_SOK or EDMA3_DRV Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 This API CANNOT be used while setting the PaRAM set field for QDMA channels. It can trigger the QDMA channel before complete PaRAM set ENTRY (4-bytes field) is written (for eg, as soon one sets the ACNT + field for QDMA channel, transfer is started, before one modifies the BCNT field). For DMA channels, no such constraint is there. +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 References EDMA3_DRV_E_INVALID_P +ARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT, EDMA3_DRV_PARAM_ENTRY_CCNT, EDMA3_DRV_PARAM_ENTRY_DST, EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD, EDMA3_DRV_PARAM_ENTRY_OPT, EDMA3_DRV_PARAM_ENTRY_SRC, EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX, EDMA3_DRV +_ +PARAM_ENTRY_SRC_DST_CIDX, EDMA3_DRV_PARAM_FIELD_ACNT, EDMA3_DRV_PARAM_FIELD_BCNT, EDMA3_DRV_PARAM_FIELD_BCNTRELOAD, EDMA3_DRV_PARAM_FIELD_CCNT, EDMA3_DRV_PARAM_FIELD_DESTADDR, EDMA3_DRV_PARAM_FIELD_DESTBIDX, EDMA3_DRV_PARAM_FIELD_DESTCIDX, EDMA3_DRV_PARAM +_ +FIELD_LINKADDR, EDMA3_DRV_PARAM_FIELD_OPT, EDMA3_DRV_PARAM_FIELD_SRCADDR, EDMA3_DRV_PARAM_FIELD_SRCBIDX, EDMA3_DRV_PARAM_FIELD_SRCCIDX, EDMA3_DRV_QDMA_CHANNEL_0, EDMA3_DRV_QDMA_CHANNEL_7, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRe +gs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_setQdmaTrigWord\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\:EDMA3_DRV_setQdmaTrigWord}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result EDMA3_DRV_setQdmaTrigWord (EDMA3_DRV_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 lCh}{\rtlch\fcs1 +\af1 \ltrch\fcs0 \insrsid6424133 , EDMA3_RM_QdmaTrigWord }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 trigWord}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAJL}{\*\bkmkend AAAAAAAAJL}Assign a Trigger Word to the specified QDMA channel. +\par This API sets the Trigger word for the specific QDMA channel in the QCHMAP Register. Default QDMA trigger word is CCNT. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Handle to the EDMA Instance object +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 lCh}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] QDMA Channel which needs to be assigned the Trigger Word +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 trigWord}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] The Trigger Word for the QDMA channel. +Trigger Word is the word in the PaRAM Register Set which, when written to by CPU, will start the QDMA transfer automatically. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_SOK or EDMA3_DRV Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_QCH_TRWORD_CLR_MASK, EDMA3_DRV_QCH_TRWORD_SET_MASK, EDMA3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, and EDM +A3_DRV_Instance::pDrvObjectHandle. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_waitAndClearTcc\:Edma3DrvTransferSetupOpt}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvTransferSetupOpt\:EDMA3_DRV_waitAndClearTcc}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result EDMA3_DRV_waitAndClearTcc (EDMA3_DRV_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 tccNo}{\rtlch\fcs1 +\af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAJM}{\*\bkmkend AAAAAAAAJM}Wait for a transfer completion interrupt to occur and clear it. +\par This is a blocking function that returns when the IPR/IPRH bit corresponding to the tccNo specified, is SET. It clears the corresponding bit while returning also. +\par This function waits for the specific bit indefinitely in a tight loop, with out any delay in between. USE IT CAUTIOUSLY. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] Handle to the EDMA Driver Instance +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 tccNo}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [IN] TCC, specific to which the function waits on a IPR/IPRH bit. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_SOK or EDMA3_DRV Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 This function is re-entrant for different tccNo. +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Bit found SET, transfer is completed, clear the pending interrupt and return. +\par Bit found SET, transfer is completed, clear the pending interrupt and return. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 References EDMA3_D +RV_E_INVALID_PARAM, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numTccs, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Instance::regionId. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Internal Interface Definition for EDMA3 Driver +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 \tcl2{\*\bkmkstart _Toc211937257}Internal Interface Definition for EDMA3 Driver{\*\bkmkend _Toc211937257} +}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Internal Interface Definition for EDMA3 Driver}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAJN}{\*\bkmkend AAAAAAAAJN}Modules +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 +Boundary Values}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 Object Maintenance}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Data Structures +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ChBoundResources}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 EDMA3 Channel-Bound resources. +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Defines +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define } +{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_SAM_CLR_MASK}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \~ (~EDMA3_CCRL_OPT_SAM_MASK) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_SAM_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (mode)\~ (((EDMA3_CCRL_OPT_SAM_MASK >> EDMA3_CCRL_OPT_SAM_SHIFT) & (mode)) << EDMA3_CCRL_OPT_SAM_SHIFT) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_DAM_CLR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (~EDMA3_CCRL_OPT_DAM_MASK) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_DAM_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (mode)\~ (((EDMA3_CCRL_OPT_DAM_MASK >> EDMA3_CCRL_OPT_DAM_SHIFT) & (mode)) << EDMA3_CCRL_OPT_DAM_SHIFT) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_SYNCDIM_CLR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (~EDMA3_CCRL_OPT_SYNCDIM_MASK) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_SYNCDIM_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (synctype)\~ (((EDMA3_CCRL_OPT_SYNCDIM_MASK >> EDMA3_CCRL_OPT_SYNCDIM_SHIFT) & (synctype)) << EDMA3_CCRL_OPT_SYNCDIM_SHIFT) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_STATIC_CLR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (~EDMA3_CCRL_OPT_STATIC_MASK) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_STATIC_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (en)\~ (((EDMA3_CCRL_OPT_STATIC_MASK >> EDMA3_CCRL_OPT_STATIC_SHIFT) & (en)) << EDMA3_CCRL_OPT_STATIC_SHIFT) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_FWID_CLR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (~EDMA3_CCRL_OPT_FWID_MASK) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_FWID_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (width)\~ (((EDMA3_CCRL_OPT_FWID_MASK >> EDMA3_CCRL_OPT_FWID_SHIFT) & (width)) << EDMA3_CCRL_OPT_FWID_SHIFT) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_TCCMODE_CLR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (~EDMA3_CCRL_OPT_TCCMODE_MASK) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_TCCMODE_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (early)\~ (((EDMA3_CCRL_OPT_TCCMODE_MASK >> EDMA3_CCRL_OPT_TCCMODE_SHIFT) & (early)) << EDMA3_CCRL_OPT_TCCMODE_SHIFT) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_TCC_CLR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (~EDMA3_CCRL_OPT_TCC_MASK) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_TCC_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (tcc)\~ (((EDMA3_CCRL_OPT_TCC_MASK >> EDMA3_CCRL_OPT_TCC_SHIFT) & (tcc)) << EDMA3_CCRL_OPT_TCC_SHIFT) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_TCINTEN_CLR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (~EDMA3_CCRL_OPT_TCINTEN_MASK) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_TCINTEN_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (tcinten)\~ (((EDMA3_CCRL_OPT_TCINTEN_MASK >> EDMA3_CCRL_OPT_TCINTEN_SHIFT) & (tcinten)) << EDMA3_CCRL_OPT_TCINTEN_SHIFT) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_ITCINTEN_CLR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (~EDMA3_CCRL_OPT_ITCINTEN_MASK) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_ITCINTEN_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (itcinten)\~ (((EDMA3_CCRL_OPT_ITCINTEN_MASK >> EDMA3_CCRL_OPT_ITCINTEN_SHIFT) & (itcinten)) << EDMA3_CCRL_OPT_ITCINTEN_SHIFT) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_TCCHEN_CLR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (~EDMA3_CCRL_OPT_TCCHEN_MASK) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_TCCHEN_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (tcchen)\~ (((EDMA3_CCRL_OPT_TCCHEN_MASK >> EDMA3_CCRL_OPT_TCCHEN_SHIFT) & (tcchen)) << EDMA3_CCRL_OPT_TCCHEN_SHIFT) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_ITCCHEN_CLR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (~EDMA3_CCRL_OPT_ITCCHEN_MASK) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_ITCCHEN_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (itcchen)\~ (((EDMA3_CCRL_OPT_ITCCHEN_MASK >> EDMA3_CCRL_OPT_ITCCHEN_SHIFT) & (itcchen)) << EDMA3_CCRL_OPT_ITCCHEN_SHIFT) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_SAM_GET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (mode)\~ ((mode)&1u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_DAM_GET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (mode)\~ (((mode)&(1u<<1u))>>1u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_SYNCDIM_GET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (synctype)\~ (((synctype)&(1u<<2u))>>2u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_STATIC_GET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (en)\~ (((en)&(1u<<3u))>>3u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_FWID_GET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (width)\~ (((width)&(0x7u<<8u))>>8u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_TCCMODE_GET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (early)\~ (((early)&(1u<<11u))>>11u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_TCC_GET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (tcc)\~ (((tcc)&(0x3fu<<12u))>>12u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_TCINTEN_GET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (tcinten)\~ (((tcinten)&(1u<<20u))>>20u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_ITCINTEN_GET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (itcinten)\~ (((itcinten)&(1u<<21u))>>21u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_TCCHEN_GET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (tcchen)\~ (((tcchen)&(1u<<22u))>>22u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_ITCCHEN_GET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (itcchen)\~ (((itcchen)&(1u<<23u))>>23u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_DMAQNUM_CLR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (chNum)\~ (~(0x7u<<(((chNum)%8u)*4u))) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_DMAQNUM_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (chNum, queNum)\~ ((0x7u & (queNum)) << (((chNum)%8u)*4u)) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_QDMAQNUM_CLR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (chNum)\~ (~(0x7u<<((chNum)*4u))) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_QDMAQNUM_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (chNum, queNum)\~ ((0x7u & (queNum)) << ((chNum)*4u)) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_QCH_TRWORD_CLR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (~EDMA3_CCRL_QCHMAP_TRWORD_MASK) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_QCH_TRWORD_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (paRAMId)\~ (((EDMA3_CCRL_QCHMAP_TRWORD_MASK >> EDMA3_CCRL_QCHMAP_TRWORD_SHIFT) & (paRAMId)) << EDMA3_CCRL_QCHMAP_TRWORD_SHIFT) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ACNT_MAX_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (0xFFFFu) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_BCNT_MAX_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (0xFFFFu) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_CCNT_MAX_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (0xFFFFu) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_BCNTRELD_MAX_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (0xFFFFu) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_SRCBIDX_MAX_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (0x7FFF) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_SRCBIDX_MIN_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (-32768) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_SRCCIDX_MAX_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (0x7FFF) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_SRCCIDX_MIN_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (-32768) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_DSTBIDX_MAX_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (0x7FFF) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_DSTBIDX_MIN_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (-32768) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_DSTCIDX_MAX_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (0x7FFF) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_DSTCIDX_MIN_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (-32768) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_QPRIORITY_MAX_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (7u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_QPRIORITY_MIN_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (0u) +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Enumerations +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ChannelType}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_CHANNEL_TYPE_NONE}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_CHANNEL_TYPE_DMA}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 1, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_CHANNEL_TYPE_QDMA}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 = 2, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_CHANNEL_TYPE_LINK}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 3 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 EDMA3 Channel Type. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 Include EDMA3 Driver header file +\par Documentation of the Internal Interface of EDMA3 Driver +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Define Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 EDMA3_DRV_ACNT_MAX_VAL\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 Edma3DrvInt\:EDMA3_DRV_ACNT_MAX_VAL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_ACNT_MAX_VAL\~ (0xFFFFu) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAJO}{\*\bkmkend AAAAAAAAJO}Max value of ACnt +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_setTransferParams(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_BCNT_MAX_VAL\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_BCNT_MAX_VAL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_BCNT_MAX_VAL\~ (0xFFFFu) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAJP}{\*\bkmkend AAAAAAAAJP}Max value of BCnt +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_setTransferParams(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_BCNTRELD_MAX_VAL\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_BCNTRELD_MAX_VAL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_BCNTRELD_MAX_VAL\~ (0xFFFFu) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAJQ}{\*\bkmkend AAAAAAAAJQ}Max value of BCntReld +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_setTransferParams(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_CCNT_MAX_VAL\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_CCNT_MAX_VAL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_CCNT_MAX_VAL\~ (0xFFFFu) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAJR}{\*\bkmkend AAAAAAAAJR}Max value of CCnt +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_setTransferParams(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_DMAQNUM_CLR_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_DMAQNUM_CLR_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_DMAQNUM_CLR_MASK(chNum)\~ (~(0x7u<<(((chNum)%8u)*4u))) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAJS}{\*\bkmkend AAAAAAAAJS}DMAQNUM bits Clear +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_getMapChToEvtQ(), EDMA3_DRV_mapChToEvtQ(), EDMA3_DRV_requestChannel(), EDMA3_DRV_setDestParams(), EDMA3_DRV_setSrcParams(), and edma3RemoveMapping(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_DMAQNUM_SET_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_DMAQNUM_SET_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_DMAQNUM_SET_MASK(chNum, queNum)\~ ((0x7u & (queNum)) << (((chNum)%8u)*4u)) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAJT}{\*\bkmkend AAAAAAAAJT}DMAQNUM bits Set +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_mapChToEvtQ(), and EDMA3_DRV_requestChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_DSTBIDX_MAX_VAL\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_DSTBIDX_MAX_VAL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_DSTBIDX_MAX_VAL\~ (0x7FFF) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAJU}{\*\bkmkend AAAAAAAAJU}Max value of DestBIdx +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_setDestIndex(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_DSTBIDX_MIN_VAL\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_DSTBIDX_MIN_VAL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_DSTBIDX_MIN_VAL\~ (-32768) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAJV}{\*\bkmkend AAAAAAAAJV}Min value of DestBIdx +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_setDestIndex(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_DSTCIDX_MAX_VAL\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_DSTCIDX_MAX_VAL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_DSTCIDX_MAX_VAL\~ (0x7FFF) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAJW}{\*\bkmkend AAAAAAAAJW}Max value of DestCIdx +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_setDestIndex(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_DSTCIDX_MIN_VAL\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_DSTCIDX_MIN_VAL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_DSTCIDX_MIN_VAL\~ (-32768) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAJX}{\*\bkmkend AAAAAAAAJX}Min value of DestCIdx +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_setDestIndex(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_OPT_DAM_CLR_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_OPT_DAM_CLR_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_OPT_DAM_CLR_MASK\~ (~EDMA3_CCRL_OPT_DAM_MASK) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAJY}{\*\bkmkend AAAAAAAAJY}OPT-DAM bit Clear +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_setDestParams(), and EDMA3_DRV_setOptField(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_OPT_DAM_GET_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_OPT_DAM_GET_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_OPT_DAM_GET_MASK(mode)\~ (((mode)&(1u<<1u))>>1u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAJZ}{\*\bkmkend AAAAAAAAJZ}OPT-DAM bit Get +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_getOptField(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_OPT_DAM_SET_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_OPT_DAM_SET_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_OPT_DAM_SET_MASK(mode)\~ (((EDMA3_CCRL_OPT_DAM_MASK >> EDMA3_CCRL_OPT_DAM_SHIFT) & (mode)) << EDMA3_CCRL_OPT_DAM_SHIFT) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAKA}{\*\bkmkend AAAAAAAAKA}OPT-DAM bit Set +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_setDestParams(), and EDMA3_DRV_setOptField(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_OPT_FWID_CLR_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_OPT_FWID_CLR_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_OPT_FWID_CLR_MASK\~ (~EDMA3_CCRL_OPT_FWID_MASK) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAKB}{\*\bkmkend AAAAAAAAKB}OPT-FWID bitfield Clear +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_setDestParams(), EDMA3_DRV_setOptField(), and EDMA3_DRV_setSrcParams(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_OPT_FWID_GET_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_OPT_FWID_GET_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_OPT_FWID_GET_MASK(width)\~ (((width)&(0x7u<<8u))>>8u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAKC}{\*\bkmkend AAAAAAAAKC}OPT-FWID bitfield Get +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_getOptField(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_OPT_FWID_SET_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_OPT_FWID_SET_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_OPT_FWID_SET_MASK(width)\~ (((EDMA3_CCRL_OPT_FWID_MASK >> EDMA3_CCRL_OPT_FWID_SHIFT) & (width)) << EDMA3_CCRL_OPT_FWID_SHIFT) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAKD}{\*\bkmkend AAAAAAAAKD}OPT-FWID bitfield Set +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_setDestParams(), EDMA3_DRV_setOptField(), and EDMA3_DRV_setSrcParams(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_OPT_ITCCHEN_CLR_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_OPT_ITCCHEN_CLR_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_OPT_ITCCHEN_CLR_MASK\~ (~EDMA3_CCRL_OPT_ITCCHEN_MASK) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAKE}{\*\bkmkend AAAAAAAAKE}OPT-ITCCHEN bit Clear +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_setOptField(), and EDMA3_DRV_unchainChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_OPT_ITCCHEN_GET_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_OPT_ITCCHEN_GET_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_OPT_ITCCHEN_GET_MASK(itcchen)\~ (((itcchen)&(1u<<23u))>>23u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAKF}{\*\bkmkend AAAAAAAAKF}OPT-ITCCHEN bit Get +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_getOptField(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_OPT_ITCCHEN_SET_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_OPT_ITCCHEN_SET_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_OPT_ITCCHEN_SET_MASK(itcchen)\~ (((EDMA3_CCRL_OPT_ITCCHEN_MASK >> EDMA3_CCRL_OPT_ITCCHEN_SHIFT) & (itcchen)) << EDMA3_CCRL_OPT_ITCCHEN_SHIFT) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAKG}{\*\bkmkend AAAAAAAAKG}OPT-ITCCHEN bit Set +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_chainChannel(), and EDMA3_DRV_setOptField(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_OPT_ITCINTEN_CLR_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_OPT_ITCINTEN_CLR_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_OPT_ITCINTEN_CLR_MASK\~ (~EDMA3_CCRL_OPT_ITCINTEN_MASK) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAKH}{\*\bkmkend AAAAAAAAKH}OPT-ITCINTEN bit Clear +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_chainChannel(), and EDMA3_DRV_setOptField(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_OPT_ITCINTEN_GET_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_OPT_ITCINTEN_GET_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_OPT_ITCINTEN_GET_MASK(itcinten)\~ (((itcinten)&(1u<<21u))>>21u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAKI}{\*\bkmkend AAAAAAAAKI}OPT-ITCINTEN bit Get +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_getOptField(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_OPT_ITCINTEN_SET_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_OPT_ITCINTEN_SET_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_OPT_ITCINTEN_SET_MASK(itcinten)\~ (((EDMA3_CCRL_OPT_ITCINTEN_MASK >> EDMA3_CCRL_OPT_ITCINTEN_SHIFT) & (itcinten)) << EDMA3_CCRL_OPT_ITCINTEN_SHIFT) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAKJ}{\*\bkmkend AAAAAAAAKJ}OPT-ITCINTEN bit Set +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_chainChannel(), and EDMA3_DRV_setOptField(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_OPT_SAM_CLR_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_OPT_SAM_CLR_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_OPT_SAM_CLR_MASK\~ (~EDMA3_CCRL_OPT_SAM_MASK) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAKK}{\*\bkmkend AAAAAAAAKK}Parameter RAM Set field OPT bit-field defines OPT-SAM bit Clear +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_setOptField(), and EDMA3_DRV_setSrcParams(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_OPT_SAM_GET_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_OPT_SAM_GET_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_OPT_SAM_GET_MASK(mode)\~ ((mode)&1u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAKL}{\*\bkmkend AAAAAAAAKL}OPT-SAM bit Get +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_getOptField(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_OPT_SAM_SET_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_OPT_SAM_SET_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_OPT_SAM_SET_MASK(mode)\~ (((EDMA3_CCRL_OPT_SAM_MASK >> EDMA3_CCRL_OPT_SAM_SHIFT) & (mode)) << EDMA3_CCRL_OPT_SAM_SHIFT) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAKM}{\*\bkmkend AAAAAAAAKM}OPT-SAM bit Set +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_setOptField(), and EDMA3_DRV_setSrcParams(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_OPT_STATIC_CLR_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_OPT_STATIC_CLR_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_OPT_STATIC_CLR_MASK\~ (~EDMA3_CCRL_OPT_STATIC_MASK) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAKN}{\*\bkmkend AAAAAAAAKN}OPT-STATIC bit Clear +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_setOptField(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_OPT_STATIC_GET_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_OPT_STATIC_GET_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_OPT_STATIC_GET_MASK(en)\~ (((en)&(1u<<3u))>>3u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAKO}{\*\bkmkend AAAAAAAAKO}OPT-STATIC bit Get +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_getOptField(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_OPT_STATIC_SET_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_OPT_STATIC_SET_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_OPT_STATIC_SET_MASK(en)\~ (((EDMA3_CCRL_OPT_STATIC_MASK >> EDMA3_CCRL_OPT_STATIC_SHIFT) & (en)) << EDMA3_CCRL_OPT_STATIC_SHIFT) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAKP}{\*\bkmkend AAAAAAAAKP}OPT-STATIC bit Set +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_setOptField(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_OPT_SYNCDIM_CLR_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_OPT_SYNCDIM_CLR_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_OPT_SYNCDIM_CLR_MASK\~ (~EDMA3_CCRL_OPT_SYNCDIM_MASK) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAKQ}{\*\bkmkend AAAAAAAAKQ}OPT-SYNCDIM bit Clear +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_setOptField(), and EDMA3_DRV_setTransferParams(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_OPT_SYNCDIM_GET_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_OPT_SYNCDIM_GET_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 #defi +ne EDMA3_DRV_OPT_SYNCDIM_GET_MASK(synctype)\~ (((synctype)&(1u<<2u))>>2u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAKR}{\*\bkmkend AAAAAAAAKR}OPT-SYNCDIM bit Get +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_getOptField(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_OPT_SYNCDIM_SET_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_OPT_SYNCDIM_SET_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 #defi +ne EDMA3_DRV_OPT_SYNCDIM_SET_MASK(synctype)\~ (((EDMA3_CCRL_OPT_SYNCDIM_MASK >> EDMA3_CCRL_OPT_SYNCDIM_SHIFT) & (synctype)) << EDMA3_CCRL_OPT_SYNCDIM_SHIFT) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAKS}{\*\bkmkend AAAAAAAAKS}OPT-SYNCDIM bit Set +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_setOptField(), and EDMA3_DRV_setTransferParams(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_OPT_TCC_CLR_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_OPT_TCC_CLR_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_OPT_TCC_CLR_MASK\~ (~EDMA3_CCRL_OPT_TCC_MASK) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAKT}{\*\bkmkend AAAAAAAAKT}OPT-TCC bitfield Clear +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_linkChannel(), EDMA3_DRV_requestChannel(), and EDMA3_DRV_setOptField(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_OPT_TCC_GET_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_OPT_TCC_GET_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_OPT_TCC_GET_MASK(tcc)\~ (((tcc)&(0x3fu<<12u))>>12u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAKU}{\*\bkmkend AAAAAAAAKU}OPT-TCC bitfield Get +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_getOptField(), and EDMA3_DRV_linkChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_OPT_TCC_SET_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_OPT_TCC_SET_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_OPT_TCC_SET_MASK(tcc)\~ (((EDMA3_CCRL_OPT_TCC_MASK >> EDMA3_CCRL_OPT_TCC_SHIFT) & (tcc)) << EDMA3_CCRL_OPT_TCC_SHIFT) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAKV}{\*\bkmkend AAAAAAAAKV}OPT-TCC bitfield Set +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_linkChannel(), EDMA3_DRV_requestChannel(), and EDMA3_DRV_setOptField(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_OPT_TCCHEN_CLR_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_OPT_TCCHEN_CLR_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_OPT_TCCHEN_CLR_MASK\~ (~EDMA3_CCRL_OPT_TCCHEN_MASK) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAKW}{\*\bkmkend AAAAAAAAKW}OPT-TCCHEN bit Clear +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_setOptField(), and EDMA3_DRV_unchainChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_OPT_TCCHEN_GET_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_OPT_TCCHEN_GET_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_OPT_TCCHEN_GET_MASK(tcchen)\~ (((tcchen)&(1u<<22u))>>22u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAKX}{\*\bkmkend AAAAAAAAKX}OPT-TCCHEN bit Get +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_getOptField(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_OPT_TCCHEN_SET_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_OPT_TCCHEN_SET_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_OPT_TCCHEN_SET_MASK(tcchen)\~ (((EDMA3_CCRL_OPT_TCCHEN_MASK >> EDMA3_CCRL_OPT_TCCHEN_SHIFT) & (tcchen)) << EDMA3_CCRL_OPT_TCCHEN_SHIFT) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAKY}{\*\bkmkend AAAAAAAAKY}OPT-TCCHEN bit Set +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_chainChannel(), and EDMA3_DRV_setOptField(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_OPT_TCCMODE_CLR_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_OPT_TCCMODE_CLR_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_OPT_TCCMODE_CLR_MASK\~ (~EDMA3_CCRL_OPT_TCCMODE_MASK) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAKZ}{\*\bkmkend AAAAAAAAKZ}OPT-TCCMODE bit Clear +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_setOptField(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_OPT_TCCMODE_GET_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_OPT_TCCMODE_GET_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 #d +efine EDMA3_DRV_OPT_TCCMODE_GET_MASK(early)\~ (((early)&(1u<<11u))>>11u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAALA}{\*\bkmkend AAAAAAAALA}OPT-TCCMODE bit Get +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_getOptField(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_OPT_TCCMODE_SET_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_OPT_TCCMODE_SET_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 #defin +e EDMA3_DRV_OPT_TCCMODE_SET_MASK(early)\~ (((EDMA3_CCRL_OPT_TCCMODE_MASK >> EDMA3_CCRL_OPT_TCCMODE_SHIFT) & (early)) << EDMA3_CCRL_OPT_TCCMODE_SHIFT) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAALB}{\*\bkmkend AAAAAAAALB}OPT-TCCMODE bit Set +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_setOptField(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_OPT_TCINTEN_CLR_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_OPT_TCINTEN_CLR_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_OPT_TCINTEN_CLR_MASK\~ (~EDMA3_CCRL_OPT_TCINTEN_MASK) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAALC}{\*\bkmkend AAAAAAAALC}OPT-TCINTEN bit Clear +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_chainChannel(), and EDMA3_DRV_setOptField(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_OPT_TCINTEN_GET_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_OPT_TCINTEN_GET_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_OPT_TCINTEN_GET_MASK(tcinten)\~ (((tcinten)&(1u<<20u))>>20u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAALD}{\*\bkmkend AAAAAAAALD}OPT-TCINTEN bit Get +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_getOptField(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_OPT_TCINTEN_SET_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_OPT_TCINTEN_SET_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_OPT_TCINTEN_SET_MASK(tcinten)\~ (((EDMA3_CCRL_OPT_TCINTEN_MASK >> EDMA3_CCRL_OPT_TCINTEN_SHIFT) & (tcinten)) << EDMA3_CCRL_OPT_TCINTEN_SHIFT) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAALE}{\*\bkmkend AAAAAAAALE}OPT-TCINTEN bit Set +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_chainChannel(), and EDMA3_DRV_setOptField(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_QCH_TRWORD_CLR_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_QCH_TRWORD_CLR_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_QCH_TRWORD_CLR_MASK\~ (~EDMA3_CCRL_QCHMAP_TRWORD_MASK) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAALF}{\*\bkmkend AAAAAAAALF}QCHMAP-TrigWord bitfield Clear +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_setQdmaTrigWord(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_QCH_TRWORD_SET_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_QCH_TRWORD_SET_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_QCH_TRWORD_SET_MASK(paRAMId)\~ (((EDMA3_CCRL_QCHMAP_TRWORD_MASK >> EDMA3_CCRL_QCHMAP_TRWORD_SHIFT) & (paRAMId)) << EDMA3_CCRL_QCHMAP_TRWORD_SHIFT) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAALG}{\*\bkmkend AAAAAAAALG}QCHMAP-TrigWord bitfield Set +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_setQdmaTrigWord(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_QDMAQNUM_CLR_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_QDMAQNUM_CLR_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_QDMAQNUM_CLR_MASK(chNum)\~ (~(0x7u<<((chNum)*4u))) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAALH}{\*\bkmkend AAAAAAAALH}QDMAQNUM bits Clear +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_getMapChToEvtQ(), EDMA3_DRV_mapChToEvtQ(), EDMA3_DRV_requestChannel(), EDMA3_DRV_setDestParams(), EDMA3_DRV_setSrcParams(), and edma3RemoveMapping(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_QDMAQNUM_SET_MASK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_QDMAQNUM_SET_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_QDMAQNUM_SET_MASK(chNum, queNum)\~ ((0x7u & (queNum)) << ((chNum)*4u)) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAALI}{\*\bkmkend AAAAAAAALI}QDMAQNUM bits Set +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_mapChToEvtQ(), and EDMA3_DRV_requestChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_QPRIORITY_MAX_VAL\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_QPRIORITY_MAX_VAL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_QPRIORITY_MAX_VAL\~ (7u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAALJ}{\*\bkmkend AAAAAAAALJ}Max value of Queue Priority +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_setEvtQPriority(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_QPRIORITY_MIN_VAL\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_QPRIORITY_MIN_VAL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_QPRIORITY_MIN_VAL\~ (0u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAALK}{\*\bkmkend AAAAAAAALK}Min value of Queue Priority +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_SRCBIDX_MAX_VAL\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_SRCBIDX_MAX_VAL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_SRCBIDX_MAX_VAL\~ (0x7FFF) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAALL}{\*\bkmkend AAAAAAAALL}Max value of SrcBIdx +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_setSrcIndex(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_SRCBIDX_MIN_VAL\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_SRCBIDX_MIN_VAL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_SRCBIDX_MIN_VAL\~ (-32768) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAALM}{\*\bkmkend AAAAAAAALM}Min value of SrcBIdx +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_setSrcIndex(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_SRCCIDX_MAX_VAL\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_SRCCIDX_MAX_VAL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_SRCCIDX_MAX_VAL\~ (0x7FFF) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAALN}{\*\bkmkend AAAAAAAALN}Max value of SrcCIdx +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_setSrcIndex(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_SRCCIDX_MIN_VAL\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_SRCCIDX_MIN_VAL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_SRCCIDX_MIN_VAL\~ (-32768) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAALO}{\*\bkmkend AAAAAAAALO}Min value of SrcCIdx +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_setSrcIndex(). +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Enumeration Type Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 EDMA3_DRV_ChannelType\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 Edma3DrvInt\:EDMA3_DRV_ChannelType}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +enum EDMA3_DRV_ChannelType +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAALP}{\*\bkmkend AAAAAAAALP}EDMA3 Channel Type. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 +\par Enumerator: }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_CHANNEL_TYPE_NONE\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_CHANNEL_TYPE_NONE}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 EDMA3_DRV_CHANNEL_TYPE_NONE}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAALQ}{\*\bkmkend AAAAAAAALQ} Invalid Channel +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_CHANNEL_TYPE_DMA\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_CHANNEL_TYPE_DMA}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 EDMA3_DRV_CHANNEL_TYPE_DMA}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAALR}{\*\bkmkend AAAAAAAALR} DMA Channel +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_CHANNEL_TYPE_QDMA\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_CHANNEL_TYPE_QDMA}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 EDMA3_DRV_CHANNEL_TYPE_QDMA}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAALS}{\*\bkmkend AAAAAAAALS} QDMA Channel +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_CHANNEL_TYPE_LINK\:Edma3DrvInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvInt\:EDMA3_DRV_CHANNEL_TYPE_LINK}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 EDMA3_DRV_CHANNEL_TYPE_LINK}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAALT}{\*\bkmkend AAAAAAAALT} LINK Channel +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Boundary Values +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 \tcl2{\*\bkmkstart _Toc211937258}Boundary Values{\*\bkmkend _Toc211937258}}}}\sectd +\linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Boundary Values}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAALU} +{\*\bkmkend AAAAAAAALU}Defines +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define } +{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_DMA_CH_MAX_VAL}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \~ (EDMA3_MAX_DMA_CH - 1u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_LINK_CH_MIN_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_DMA_CH_MAX_VAL + 1u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_LINK_CH_MAX_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_LINK_CH_MIN_VAL + EDMA3_MAX_PARAM_SETS - 1u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_QDMA_CH_MIN_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_LINK_CH_MAX_VAL + 1u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_QDMA_CH_MAX_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_QDMA_CH_MIN_VAL + EDMA3_MAX_QDMA_CH - 1u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_LOG_CH_MAX_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_QDMA_CH_MAX_VAL) +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 Boundary Values for Logical Channel Ranges +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Define Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 EDMA3_DRV_DMA_CH_MAX_VAL\:Edma3DrvIntBoundVals}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 Edma3DrvIntBoundVals\:EDMA3_DRV_DMA_CH_MAX_VAL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 #define EDMA3_DRV_DMA_CH_MAX_VAL\~ (EDMA3_MAX_DMA_CH - 1u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAALV}{\*\bkmkend AAAAAAAALV}Max of DMA Channels +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_clearErrorBits(), EDMA3_DRV_disableT +ransfer(), EDMA3_DRV_enableTransfer(), EDMA3_DRV_freeChannel(), EDMA3_DRV_getMapChToEvtQ(), EDMA3_DRV_mapChToEvtQ(), EDMA3_DRV_requestChannel(), EDMA3_DRV_setDestParams(), EDMA3_DRV_setSrcParams(), and edma3RemoveMapping(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_LINK_CH_MAX_VAL\:Edma3DrvIntBoundVals}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvIntBoundVals\:EDMA3_DRV_LINK_CH_MAX_VAL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_LINK_CH_MAX_VAL\~ (EDMA3_DRV_LINK_CH_MIN_VAL + EDMA3_MAX_PARAM_SETS - 1u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAALW}{\*\bkmkend AAAAAAAALW}Max of Link Channels +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_freeChannel(), and EDMA3_DRV_requestChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_LINK_CH_MIN_VAL\:Edma3DrvIntBoundVals}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvIntBoundVals\:EDMA3_DRV_LINK_CH_MIN_VAL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_LINK_CH_MIN_VAL\~ (EDMA3_DRV_DMA_CH_MAX_VAL + 1u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAALX}{\*\bkmkend AAAAAAAALX}Min of Link Channels +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_freeChannel(), and EDMA3_DRV_requestChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_LOG_CH_MAX_VAL\:Edma3DrvIntBoundVals}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvIntBoundVals\:EDMA3_DRV_LOG_CH_MAX_VAL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_LOG_CH_MAX_VAL\~ (EDMA3_DRV_QDMA_CH_MAX_VAL) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAALY}{\*\bkmkend AAAAAAAALY}Max of Logical Channels +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_disableTransfer(), EDMA3_DRV_enableTransfer(), EDMA3_DRV_freeChannel(), EDMA3_DRV_getMapChToEvtQ(), EDMA3_DRV_getOptField(), EDMA3_DRV_getPaRAM(), EDMA3_DRV_getPaRAMEntry(), EDMA3_DRV_getPaRAMField +(), EDMA3_DRV_getPaRAMPhyAddr(), EDMA3_DRV_linkChannel(), EDMA3_DRV_setDestIndex(), EDMA3_DRV_setDestParams(), EDMA3_DRV_setOptField(), EDMA3_DRV_setPaRAM(), EDMA3_DRV_setPaRAMEntry(), EDMA3_DRV_setPaRAMField(), EDMA3_DRV_setSrcIndex(), EDMA3_DRV_setSrcPa +rams(), EDMA3_DRV_setTransferParams(), EDMA3_DRV_unchainChannel(), EDMA3_DRV_unlinkChannel(), and edma3RemoveMapping(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_QDMA_CH_MAX_VAL\:Edma3DrvIntBoundVals}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvIntBoundVals\:EDMA3_DRV_QDMA_CH_MAX_VAL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_QDMA_CH_MAX_VAL\~ (EDMA3_DRV_QDMA_CH_MIN_VAL + EDMA3_MAX_QDMA_CH - 1u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAALZ}{\*\bkmkend AAAAAAAALZ}Max of QDMA Channels +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_disableTransfer(), EDMA3_DRV_enableTransfer(), EDMA3_DRV_freeChannel(), EDMA3_DRV_getMapChToEvtQ(), EDMA3_DRV_mapChToEvtQ(), EDMA3_DR +V_requestChannel(), EDMA3_DRV_setDestParams(), EDMA3_DRV_setQdmaTrigWord(), and EDMA3_DRV_setSrcParams(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_QDMA_CH_MIN_VAL\:Edma3DrvIntBoundVals}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Edma3DrvIntBoundVals\:EDMA3_DRV_QDMA_CH_MIN_VAL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +#define EDMA3_DRV_QDMA_CH_MIN_VAL\~ (EDMA3_DRV_LINK_CH_MAX_VAL + 1u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAMA}{\*\bkmkend AAAAAAAAMA}Min of QDMA Channels +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_disableTransfer(), EDMA3_DRV_enableTransfer(), EDMA3_DRV_freeChannel(), EDMA3_DRV_getMapChToEvtQ(), EDMA3_DRV_mapChToEvtQ(), EDMA3_DRV_requestChannel(), EDMA3_DRV_set +DestParams(), EDMA3_DRV_setQdmaTrigWord(), EDMA3_DRV_setSrcParams(), and edma3RemoveMapping(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Object Maintenance +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 \tcl2{\*\bkmkstart _Toc211937259}Object Maintenance{\*\bkmkend _Toc211937259}}}}\sectd +\linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Object Maintenance}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAMB} +{\*\bkmkend AAAAAAAAMB}Data Structures +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_Object}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 EDMA3 Driver Object (HW Specific) Maintenance structure. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_Instance}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 EDMA3 Driver Instance Configuration Structure. +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Enumerations +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ObjState}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_DELETED}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 0, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_CREATED}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 1, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPENED}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 2, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_CLOSED}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 3 \} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 Maintenance of the EDMA3 Driver Object +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Enumeration Type Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 EDMA3_DRV_ObjState\:Edma3DrvIntObjMaint}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 Edma3DrvIntObjMaint\:EDMA3_DRV_ObjState}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +enum EDMA3_DRV_ObjState +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAMC}{\*\bkmkend AAAAAAAAMC}To maintain the state of the EDMA3 Driver object +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 Enumerator: }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_DELETED\:Edma3DrvIntObjMaint}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvIntObjMaint\:EDMA3_DRV_DELETED}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 EDMA3_DRV_DELETED}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAMD}{\*\bkmkend AAAAAAAAMD} Object deleted +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_CREATED\:Edma3DrvIntObjMaint}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvIntObjMaint\:EDMA3_DRV_CREATED}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 EDMA3_DRV_CREATED}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAME}{\*\bkmkend AAAAAAAAME} Obect Created +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_OPENED\:Edma3DrvIntObjMaint}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvIntObjMaint\:EDMA3_DRV_OPENED}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 EDMA3_DRV_OPENED}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAMF}{\*\bkmkend AAAAAAAAMF} Object Opened +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_CLOSED\:Edma3DrvIntObjMaint}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Edma3DrvIntObjMaint\:EDMA3_DRV_CLOSED}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid6424133 EDMA3_DRV_CLOSED}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAMG}{\*\bkmkend AAAAAAAAMG} Object Closed +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 +\ltrch\fcs0 \fs24\insrsid6424133 \sect }\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s1\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 +\rtlch\fcs1 \ab\af1\afs36\alang1025 \ltrch\fcs0 \b\f1\fs36\lang1033\langfe1033\kerning36\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Data Structure Documentation}{\pard\plain \ltrpar +\s1\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs36\alang1025 \ltrch\fcs0 +\b\v\f1\fs36\lang1033\langfe1033\kerning36\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart _Toc211937260}Data Structure Documentation{\*\bkmkend _Toc211937260}}}}\sectd \linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_ChainOptions Struct Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc { +\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 \tcl2{\*\bkmkstart _Toc211937261}EDMA3_DRV_ChainOptions{\*\bkmkend _Toc211937261}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn +\pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 EDMA3_DRV_ChainOptions}}} +\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAMH}{\*\bkmkend AAAAAAAAMH}Structure to be used to configure interrupt generation and chaining options. +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid6424133 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Data Fields +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 +EDMA3_DRV_TcchEn}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 tcchEn}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ItcchEn}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 itcchEn}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TcintEn}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 tcintEn}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ItcintEn}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 itcintEn}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Structure to be used to configure interrupt generation and chaining options. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Field Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 +\ltrch\fcs0 \fs24\insrsid6424133 tcchEn\:EDMA3_DRV_ChainOptions}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 EDMA3_DRV_ChainOptions\:tcchEn}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 EDMA3_DRV_TcchEn EDMA3_DRV_ChainOptions::tcchEn +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAMS}{\*\bkmkend AAAAAAAAMS}Transfer complete chaining enable +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_chainChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 itcchEn\:EDMA3_DRV_ChainOptions}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_ChainOptions\:itcchEn}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_ItcchEn EDMA3_DRV_ChainOptions::itcchEn +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAMT}{\*\bkmkend AAAAAAAAMT}Intermediate Transfer complete chaining enable +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_chainChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 tcintEn\:EDMA3_DRV_ChainOptions}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_ChainOptions\:tcintEn}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_TcintEn EDMA3_DRV_ChainOptions::tcintEn +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAMU}{\*\bkmkend AAAAAAAAMU}Transfer complete interrupt enable +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_chainChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 itcintEn\:EDMA3_DRV_ChainOptions}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_ChainOptions\:itcintEn}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_ItcintEn EDMA3_DRV_ChainOptions::itcintEn +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAMV}{\*\bkmkend AAAAAAAAMV}Intermediate Transfer complete interrupt enable +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_chainChannel(). +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\fs22\insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +The documentation for this struct was generated from the following file: +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 +edma3_drv.h}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 \sect +}\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_ChBoundResources Struct Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 \tcl2 +{\*\bkmkstart _Toc211937262}EDMA3_DRV_ChBoundResources{\*\bkmkend _Toc211937262}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 +\ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 EDMA3_DRV_ChBoundResources}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAMI}{\*\bkmkend AAAAAAAAMI}EDMA3 Channel-Bound resources. +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid6424133 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Data Fields +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 int }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 paRAMId}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 tcc}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TrigMode}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 trigMode}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3 Channel-Bound resources. +\par Used to maintain information of the EDMA3 resources (specifically Parameter RAM set and TCC) and the mode of triggering transfer (Manual, HW event driven etc) bound to the particular channel within }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 +EDMA3_DRV_requestChannel()}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 . +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Field Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 +\ltrch\fcs0 \fs24\insrsid6424133 paRAMId\:EDMA3_DRV_ChBoundResources}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 EDMA3_DRV_ChBoundResources\:paRAMId}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 int EDMA3_DRV_ChBoundResources::paRAMId +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAMW}{\*\bkmkend AAAAAAAAMW}PaRAM Set number associated with the particular channel +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_create(), EDMA3 +_DRV_freeChannel(), EDMA3_DRV_getOptField(), EDMA3_DRV_getPaRAM(), EDMA3_DRV_getPaRAMEntry(), EDMA3_DRV_getPaRAMField(), EDMA3_DRV_getPaRAMPhyAddr(), EDMA3_DRV_linkChannel(), EDMA3_DRV_requestChannel(), EDMA3_DRV_setDestIndex(), EDMA3_DRV_setDestParams(), + EDMA3_DRV_setOptField(), EDMA3_DRV_setPaRAM(), EDMA3_DRV_setPaRAMEntry(), EDMA3_DRV_setPaRAMField(), EDMA3_DRV_setSrcIndex(), EDMA3_DRV_setSrcParams(), EDMA3_DRV_setTransferParams(), EDMA3_DRV_unchainChannel(), and EDMA3_DRV_unlinkChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 tcc\:EDMA3_DRV_ChBoundResources}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_ChBoundResources\:tcc}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +unsigned int EDMA3_DRV_ChBoundResources::tcc +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAMX}{\*\bkmkend AAAAAAAAMX}TCC associated with the particular channel +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_create(), EDMA3_DRV_freeChannel(), and EDMA3_DRV_requestChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 trigMode\:EDMA3_DRV_ChBoundResources}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_ChBoundResources\:trigMode}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_TrigMode EDMA3_DRV_ChBoundResources::trigMode +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAMY}{\*\bkmkend AAAAAAAAMY}Mode of triggering transfer +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_create(), EDMA3_DRV_enableTransfer(), EDMA3_DRV_requestChannel(), and edma3RemoveMapping(). +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\fs22\insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +The documentation for this struct was generated from the following file: +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 +edma3.h}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 \sect +}\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_EvtQuePriority Struct Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 \tcl2 +{\*\bkmkstart _Toc211937263}EDMA3_DRV_EvtQuePriority{\*\bkmkend _Toc211937263}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 +\v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 EDMA3_DRV_EvtQuePriority}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAMJ} +{\*\bkmkend AAAAAAAAMJ}Event queue priorities setup. +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid6424133 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Data Fields +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 evtQPri}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [EDMA3_MAX_EVT_QUE]{\*\bkmkstart AAAAAAAAMZ}{\*\bkmkend AAAAAAAAMZ} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 +\i\insrsid6424133 Event Queue Priorities. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Event queue priorities setup. +\par It allows to change the priority of the individual queues and the priority of the transfer request (TR) associated with the events queued in the queue. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\fs22\insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +The documentation for this struct was generated from the following file: +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 +edma3_drv.h}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 +\par \sect }\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_GblConfigParams Struct Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 \tcl2 +{\*\bkmkstart _Toc211937264}EDMA3_DRV_GblConfigParams{\*\bkmkend _Toc211937264}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 +\v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 EDMA3_DRV_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAMK} +{\*\bkmkend AAAAAAAAMK}Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid6424133 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Data Fields +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 numDmaChannels}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 numQdmaChannels}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 numTccs}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 numPaRAMSets}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 numEvtQueue}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 numTcs}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 numRegions}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 unsigned short }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 dmaChPaRAMMapExists}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Channel mapping existence. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +unsigned short }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 memProtectionExists}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 void * }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 globalRegs}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 void * }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 tcRegs}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 [EDMA3_MAX_TC] +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 xferCompleteInt}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 ccError}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 tcError}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 [EDMA3_MAX_TC] +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 evtQPri}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 [EDMA3_MAX_EVT_QUE] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 EDMA3 TC priority setting. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 evtQueueWaterMarkLvl}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [EDMA3_MAX_EVT_QUE] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Event Queues Watermark Levels. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 tcDefaultBurstSize}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [EDMA3_MAX_TC] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Default Burst Size (DBS) of TCs. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 dmaChannelPaRAMMap}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [EDMA3_MAX_DMA_CH] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Mapping from DMA channels to PaRAM Sets. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 dmaChannelTccMap}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [EDMA3_MAX_DMA_CH] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Mapping from DMA channels to TCCs. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 dmaChannelHwEvtMap}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [EDMA3_MAX_DMA_CHAN_DWRDS] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 +\i\insrsid6424133 Mapping from DMA channels to Hardware Events. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. +\par This configuration structure is used to specify the EDMA3 Driver global settings, specific to the SoC. For e.g. number of DMA/QDMA channels, number of PaRAM sets, TCCs, event queues, transfer controllers, base addresses of CC gl +obal registers and TC registers, interrupt number for EDMA3 transfer completion, CC error, event queues' priority, watermark threshold level etc. This configuration information is SoC specific and could be provided by the user at run-time while creating t +he EDMA3 Driver Object, using API EDMA3_DRV_create. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3__cfg.c, in case it is available. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Field Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 +\ltrch\fcs0 \fs24\insrsid6424133 numDmaChannels\:EDMA3_DRV_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 EDMA3_DRV_GblConfigParams\:numDmaChannels}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 +\af1 \ltrch\fcs0 \insrsid6424133 unsigned int EDMA3_DRV_GblConfigParams::numDmaChannels +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAANA}{\*\bkmkend AAAAAAAANA}Number of DMA Channels supported by the underlying EDMA3 Controller. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_requestChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 numQdmaChannels\:EDMA3_DRV_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_GblConfigParams\:numQdmaChannels}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 unsigned int EDMA3_DRV_GblConfigParams::numQdmaChannels +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAANB}{\*\bkmkend AAAAAAAANB}Number of QDMA Channels supported by the underlying EDMA3 Controller +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 numTccs\:EDMA3_DRV_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_GblConfigParams\:numTccs}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +unsigned int EDMA3_DRV_GblConfigParams::numTccs +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAANC}{\*\bkmkend AAAAAAAANC}Number of Interrupt Channels supported by the underlying EDMA3 Controller +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_checkAndClearTcc(), EDMA3_DRV_freeChannel(), and EDMA3_DRV_waitAndClearTcc(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 numPaRAMSets\:EDMA3_DRV_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_GblConfigParams\:numPaRAMSets}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +unsigned int EDMA3_DRV_GblConfigParams::numPaRAMSets +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAND}{\*\bkmkend AAAAAAAAND}Number of PaRAM Sets supported by the underlying EDMA3 Controller +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_freeChannel(), EDMA3_DRV_getOptField(), EDMA3_DRV_getPaRAM(), EDMA3_DRV_getPaRAMEntry(), EDMA3_DRV_getPaRAMField(), EDMA3_DRV_getPaRAMPhyAddr(), EDMA3_DRV_linkChannel(), E +DMA3_DRV_setDestIndex(), EDMA3_DRV_setDestParams(), EDMA3_DRV_setOptField(), EDMA3_DRV_setPaRAM(), EDMA3_DRV_setPaRAMEntry(), EDMA3_DRV_setPaRAMField(), EDMA3_DRV_setSrcIndex(), EDMA3_DRV_setSrcParams(), EDMA3_DRV_setTransferParams(), EDMA3_DRV_unchainCha +nnel(), and EDMA3_DRV_unlinkChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 numEvtQueue\:EDMA3_DRV_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_GblConfigParams\:numEvtQueue}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +unsigned int EDMA3_DRV_GblConfigParams::numEvtQueue +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAANE}{\*\bkmkend AAAAAAAANE}Number of Event Queues in the underlying EDMA3 Controller +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_clearErrorBits(), EDMA3_DRV_mapChToEvtQ(), and EDMA3_DRV_requestChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 numTcs\:EDMA3_DRV_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_GblConfigParams\:numTcs}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +unsigned int EDMA3_DRV_GblConfigParams::numTcs +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAANF}{\*\bkmkend AAAAAAAANF}Number of Transfer Controllers (TCs) in the underlying EDMA3 Controller +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 numRegions\:EDMA3_DRV_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_GblConfigParams\:numRegions}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +unsigned int EDMA3_DRV_GblConfigParams::numRegions +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAANG}{\*\bkmkend AAAAAAAANG}Number of Regions in the underlying EDMA3 Controller +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_create(), EDMA3_DRV_getInstHandle(), and EDMA3_DRV_open(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 dmaChPaRAMMapExists\:EDMA3_DRV_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_GblConfigParams\:dmaChPaRAMMapExists}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 unsigned short EDMA3_DRV_GblConfigParams::dmaChPaRAMMapExists +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAANH}{\*\bkmkend AAAAAAAANH}Channel mapping existence. +\par A value of 0 (No channel mapping) implies that there is fixed association between a DMA channel and a PaRAM Set or, in other words, DMA channel n can ONLY use PaRAM Set n (No availability of DCHMAP registers) for transfers to happen. +\par A value of 1 implies the presence of DCHMAP registers for the DMA channels and hence the flexibility of associating any DMA channel to any PaRAM Set. In other words, ANY PaRAM Set can be used for ANY DMA channel (like QDMA Channels). +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_requestChannel(), and edma3RemoveMapping(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 memProtectionExists\:EDMA3_DRV_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_GblConfigParams\:memProtectionExists}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 unsigned short EDMA3_DRV_GblConfigParams::memProtectionExists +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAANI}{\*\bkmkend AAAAAAAANI}Existence of memory protection feature +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 globalRegs\:EDMA3_DRV_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_GblConfigParams\:globalRegs}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +void* EDMA3_DRV_GblConfigParams::globalRegs +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAANJ}{\*\bkmkend AAAAAAAANJ}Base address of EDMA3 CC memory mapped registers. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_checkAndClearTcc(), EDMA3_DRV_clearErrorBits(), EDMA3_DRV_disableTransfer(), EDMA3_DRV_enableTransfer(), EDMA3_DRV_getCCRegister(), EDMA3_DRV_getMapChToEvtQ(), EDMA3_DRV_getOptField(), EDMA3_DRV_getPaRAM() +, + EDMA3_DRV_getPaRAMEntry(), EDMA3_DRV_getPaRAMField(), EDMA3_DRV_getPaRAMPhyAddr(), EDMA3_DRV_linkChannel(), EDMA3_DRV_mapChToEvtQ(), EDMA3_DRV_open(), EDMA3_DRV_requestChannel(), EDMA3_DRV_setCCRegister(), EDMA3_DRV_setDestIndex(), EDMA3_DRV_setDestParam +s +(), EDMA3_DRV_setEvtQPriority(), EDMA3_DRV_setOptField(), EDMA3_DRV_setPaRAM(), EDMA3_DRV_setPaRAMEntry(), EDMA3_DRV_setPaRAMField(), EDMA3_DRV_setQdmaTrigWord(), EDMA3_DRV_setSrcIndex(), EDMA3_DRV_setSrcParams(), EDMA3_DRV_setTransferParams(), EDMA3_DRV_ +unchainChannel(), EDMA3_DRV_unlinkChannel(), EDMA3_DRV_waitAndClearTcc(), and edma3RemoveMapping(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 tcRegs\:EDMA3_DRV_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_GblConfigParams\:tcRegs}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +void* EDMA3_DRV_GblConfigParams::tcRegs[EDMA3_MAX_TC] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAANK}{\*\bkmkend AAAAAAAANK}Base address of EDMA3 TCs memory mapped registers. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 xferCompleteInt\:EDMA3_DRV_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_GblConfigParams\:xferCompleteInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 unsigned int EDMA3_DRV_GblConfigParams::xferCompleteInt +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAANL}{\*\bkmkend AAAAAAAANL}EDMA3 transfer completion interrupt line (could be different for ARM and DSP) +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 ccError\:EDMA3_DRV_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_GblConfigParams\:ccError}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +unsigned int EDMA3_DRV_GblConfigParams::ccError +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAANM}{\*\bkmkend AAAAAAAANM}EDMA3 CC error interrupt line (could be different for ARM and DSP) +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 tcError\:EDMA3_DRV_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_GblConfigParams\:tcError}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +unsigned int EDMA3_DRV_GblConfigParams::tcError[EDMA3_MAX_TC] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAANN}{\*\bkmkend AAAAAAAANN}EDMA3 TCs error interrupt line (could be different for ARM and DSP) +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 evtQPri\:EDMA3_DRV_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_GblConfigParams\:evtQPri}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +unsigned int EDMA3_DRV_GblConfigParams::evtQPri[EDMA3_MAX_EVT_QUE] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAANO}{\*\bkmkend AAAAAAAANO}EDMA3 TC priority setting. +\par User can program the priority of the Event Queu +es at a system-wide level. This means that the user can set the priority of an IO initiated by either of the TCs (Transfer Controllers) relative to IO initiated by the other bus masters on the device (ARM, DSP, USB, etc) +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 evtQueueWaterMarkLvl\:EDMA3_DRV_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_GblConfigParams\:evtQueueWaterMarkLvl}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 unsigned int EDMA3_DRV_GblConfigParams::evtQueueWaterMarkLvl[EDMA3_MAX_EVT_QUE] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAANP}{\*\bkmkend AAAAAAAANP}Event Queues Watermark Levels. +\par To Configure the Threshold level of number of events + that can be queued up in the Event queues. EDMA3CC error register (CCERR) will indicate whether or not at any instant of time the number of events queued up in any of the event queues exceeds or equals the threshold/watermark value that is set in the que +ue watermark threshold register (QWMTHRA). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 tcDefaultBurstSize\:EDMA3_DRV_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_GblConfigParams\:tcDefaultBurstSize}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 unsigned int EDMA3_DRV_GblConfigParams::tcDefaultBurstSize[EDMA3_MAX_TC] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAANQ}{\*\bkmkend AAAAAAAANQ}Default Burst Size (DBS) of TCs. +\par An optimally-sized command is defined by the transfer controller default burst size (DBS). Different TCs can have different DBS values. It is defined in Bytes. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_setDestParams(), and EDMA3_DRV_setSrcParams(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 dmaChannelPaRAMMap\:EDMA3_DRV_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_GblConfigParams\:dmaChannelPaRAMMap}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 unsigned int EDMA3_DRV_GblConfigParams::dmaChannelPaRAMMap[EDMA3_MAX_DMA_CH] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAANR}{\*\bkmkend AAAAAAAANR}Mapping from DMA channels to PaRAM Sets. +\par If channel mapping exis +ts (DCHMAP registers are present), this array stores the respective PaRAM Set for each DMA channel. User can initialize each array member with a specific PaRAM Set or with EDMA3_DRV_CH_NO_PARAM_MAP. If channel mapping doesn't exist, it is of no use as the + EDMA3 RM automatically uses the right PaRAM Set for that DMA channel. Useful only if mapping exists, otherwise of no use. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_requestChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 dmaChannelTccMap\:EDMA3_DRV_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_GblConfigParams\:dmaChannelTccMap}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 unsigned int EDMA3_DRV_GblConfigParams::dmaChannelTccMap[EDMA3_MAX_DMA_CH] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAANS}{\*\bkmkend AAAAAAAANS}Mapping from DMA channels to TCCs. +\par This array stores the respective TCC (interrupt channel) for each DMA channel. User can initialize each array member w +ith a specific TCC or with EDMA3_DRV_CH_NO_TCC_MAP. This specific TCC code will be returned when the transfer is completed on the mapped DMA channel. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_requestChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 dmaChannelHwEvtMap\:EDMA3_DRV_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_GblConfigParams\:dmaChannelHwEvtMap}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 unsigned int EDMA3_DRV_GblConfigParams::dmaChannelHwEvtMap[EDMA3_MAX_DMA_CHAN_DWRDS] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAANT}{\*\bkmkend AAAAAAAANT}Mapping from DMA channels to Hardware Events. +\par Each bit in this array corresponds to one DMA channel and tells whether this DMA channel is tied to any peripheral. That is whether any peripheral can send the synch event on this DMA channel or not. 1 means the channel is tied to some peripheral; 0 means + it is not. DMA channels which are tied to some peripheral are RESERVED for that peripheral only. They are not allocated when user asks for 'ANY' DMA channel. All channels need not be mapped, some can be free also. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_disableTransfer(), and EDMA3_DRV_enableTransfer(). +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\fs22\insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +The documentation for this struct was generated from the following file: +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 +edma3_drv.h}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 \sect +}\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_InitConfig Struct Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 \tcl2 +{\*\bkmkstart _Toc211937265}EDMA3_DRV_InitConfig{\*\bkmkend _Toc211937265}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 +\v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 EDMA3_DRV_InitConfig}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAML} +{\*\bkmkend AAAAAAAAML}Used to Initialize the EDMA3 Driver Instance. +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid6424133 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Data Fields +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_RM_RegionId }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 regionId}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 unsigned short }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 isMaster}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_InstanceInitConfig}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 * }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid6424133 drvInstInitConfig}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 void * }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 drvSemHandle}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_RM_GblErrCallback }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 gblerrCb}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 void * }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 gblerrData}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Used to Initialize the EDMA3 Driver Instance. +\par This configuration structure is used to initialize the EDMA3 DRV Instance. This configuration information is passed while opening the DRV instance. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Field Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 +\ltrch\fcs0 \fs24\insrsid6424133 regionId\:EDMA3_DRV_InitConfig}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 EDMA3_DRV_InitConfig\:regionId}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 EDMA3_RM_RegionId EDMA3_DRV_InitConfig::regionId +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAANU}{\*\bkmkend AAAAAAAANU}Region Identification +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_open(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 isMaster\:EDMA3_DRV_InitConfig}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_InitConfig\:isMaster}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 u +nsigned short EDMA3_DRV_InitConfig::isMaster +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAANV}{\*\bkmkend AAAAAAAANV}It tells whether the EDMA3 DRV instance is Master or not. Only the shadow region associated with this master instance will receive the EDMA3 interrupts (if enabled). +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_open(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 drvInstInitConfig\:EDMA3_DRV_InitConfig}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_InitConfig\:drvInstInitConfig}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_InstanceInitConfig* EDMA3_DRV_InitConfig::drvInstInitConfig +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAANW}{\*\bkmkend AAAAAAAANW}EDMA3 resources related shadow region specific information. Which al +l EDMA3 resources are owned and reserved by this particular instance are told in this configuration structure. User can also pass this structure as NULL. In that case, default static configuration would be taken from the platform specific configuration fi +les (part of the Resource Manager), if available. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_open(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 drvSemHandle\:EDMA3_DRV_InitConfig}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_InitConfig\:drvSemHandle}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +void* EDMA3_DRV_InitConfig::drvSemHandle +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAANX}{\*\bkmkend AAAAAAAANX}EDMA3 Driver Instance specific semaphore handle. Used to share resources (DMA/QDMA channels, PaRAM Sets, TCCs etc) among different users. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_open(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 gblerrCb\:EDMA3_DRV_InitConfig}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_InitConfig\:gblerrCb}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_RM_GblErrCallback EDMA3_DRV_InitConfig::gblerrCb +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAANY}{\*\bkmkend AAAAAAAANY}Instance wide global callback function to catch non-channel specific errors from the Channel controller. for eg, TCC error, queue threshold exceed error etc. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_open(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 gblerrData\:EDMA3_DRV_InitConfig}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_InitConfig\:gblerrData}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +void* EDMA3_DRV_InitConfig::gblerrData +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAANZ}{\*\bkmkend AAAAAAAANZ}Application data to be passed back to the global error callback function +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_open(). +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\fs22\insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +The documentation for this struct was generated from the following file: +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 +edma3_drv.h}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 \sect +}\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Instance Struct Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 \tcl2 +{\*\bkmkstart _Toc211937266}EDMA3_DRV_Instance{\*\bkmkend _Toc211937266}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 +\v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 EDMA3_DRV_Instance}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAMM} +{\*\bkmkend AAAAAAAAMM}EDMA3 Driver Instance Configuration Structure. +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid6424133 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Data Fields +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_RM_RegionId }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 regionId}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 unsigned short }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 isMaster}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_InstanceInitConfig}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid6424133 drvInstInitConfig}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 void * }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 drvSemHandle}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_RM_GblErrCallbackParams }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 gblerrCbParams}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_CCRL_ShadowRegs * }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 shadowRegs}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_Object}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 * }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 pDrvObjectHandle}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_RM_Handle }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 resMgrInstance}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3 Driver Instance Configuration Structure. +\par Used to maintain information of the EDMA3 Driver Instances. One such storage exists for each instance of the EDMA3 Driver. There could be as many Driver Instances as there are s +hadow regions. Multiple EDMA3 Driver instances on the same shadow region are NOT allowed. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Field Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 +\ltrch\fcs0 \fs24\insrsid6424133 regionId\:EDMA3_DRV_Instance}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 EDMA3_DRV_Instance\:regionId}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 EDMA3_RM_RegionId EDMA3_DRV_Instance::regionId +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAOA}{\*\bkmkend AAAAAAAAOA}Region Identification +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_checkAndClearTcc(), EDMA3_DRV_open(), and EDMA3_DRV_waitAndClearTcc(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 isMaster\:EDMA3_DRV_Instance}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Instance\:isMaster}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +unsigned short EDMA3_DRV_Instance::isMaster +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAOB}{\*\bkmkend AAAAAAAAOB}Whether EDMA3 driver instance is Master or not. Only the master instance shadow region will receive the EDMA3 interrupts, if enabled. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_open(), and edma3OpenResMgr(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 drvInstInitConfig\:EDMA3_DRV_Instance}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Instance\:drvInstInitConfig}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_InstanceInitConfig EDMA3_DRV_Instance::drvInstInitConfig +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAOC}{\*\bkmkend AAAAAAAAOC}EDMA3 Driver Instance (Shadow Region) specific init configuration. If NULL, static values will be taken +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_close(), and EDMA3_DRV_open(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 drvSemHandle\:EDMA3_DRV_Instance}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Instance\:drvSemHandle}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +void* EDMA3_DRV_Instance::drvSemHandle +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAOD}{\*\bkmkend AAAAAAAAOD}EDMA3 Driver Instance specific semaphore handle +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_open(), EDMA3_DRV_setCCRegister(), and edma3OpenResMgr(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 gblerrCbParams\:EDMA3_DRV_Instance}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Instance\:gblerrCbParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_RM_GblErrCallbackParams EDMA3_DRV_Instance::gblerrCbParams +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAOE}{\*\bkmkend AAAAAAAAOE}Instance wide Global Error callback parameters +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_open(), and edma3OpenResMgr(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 shadowRegs\:EDMA3_DRV_Instance}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Instance\:shadowRegs}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_CCRL_ShadowRegs* EDMA3_DRV_Instance::shadowRegs +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAOF}{\*\bkmkend AAAAAAAAOF}Pointer to appropriate Shadow Register region of CC Registers +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_clearErrorBits(), EDMA3_DRV_close(), EDMA3_DRV_disableTransfer(), EDMA3_DRV_enableTransfer(), EDMA3_DRV_open(), and EDMA3_DRV_requestChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 pDrvObjectHandle\:EDMA3_DRV_Instance}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Instance\:pDrvObjectHandle}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Object* EDMA3_DRV_Instance::pDrvObjectHandle +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAOG}{\*\bkmkend AAAAAAAAOG}Pointer to the EDMA3 Driver Object, for HW specific / Global Information. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_checkAndClearTcc(), EDMA3_DRV_clearErrorBits(), EDMA3_DRV_close(), EDMA3_DRV_disableTrans +fer(), EDMA3_DRV_enableTransfer(), EDMA3_DRV_freeChannel(), EDMA3_DRV_getCCRegister(), EDMA3_DRV_getInstHandle(), EDMA3_DRV_getMapChToEvtQ(), EDMA3_DRV_getOptField(), EDMA3_DRV_getPaRAM(), EDMA3_DRV_getPaRAMEntry(), EDMA3_DRV_getPaRAMField(), EDMA3_DRV_ge +t +PaRAMPhyAddr(), EDMA3_DRV_linkChannel(), EDMA3_DRV_mapChToEvtQ(), EDMA3_DRV_open(), EDMA3_DRV_requestChannel(), EDMA3_DRV_setCCRegister(), EDMA3_DRV_setDestIndex(), EDMA3_DRV_setDestParams(), EDMA3_DRV_setEvtQPriority(), EDMA3_DRV_setOptField(), EDMA3_DRV +_ +setPaRAM(), EDMA3_DRV_setPaRAMEntry(), EDMA3_DRV_setPaRAMField(), EDMA3_DRV_setQdmaTrigWord(), EDMA3_DRV_setSrcIndex(), EDMA3_DRV_setSrcParams(), EDMA3_DRV_setTransferParams(), EDMA3_DRV_unchainChannel(), EDMA3_DRV_unlinkChannel(), EDMA3_DRV_waitAndClearT +cc(), edma3OpenResMgr(), and edma3RemoveMapping(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 resMgrInstance\:EDMA3_DRV_Instance}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Instance\:resMgrInstance}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_RM_Handle EDMA3_DRV_Instance::resMgrInstance +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAOH}{\*\bkmkend AAAAAAAAOH}Pointer to the Resource Manager Instance opened by the EDMA3 Driver +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_close(), EDMA3_DRV_freeChannel(), EDMA3_DRV_Ioctl(), EDMA3_DRV_requestChannel(), edma3OpenResMgr(), and edma3RemoveMapping(). +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\fs22\insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +The documentation for this struct was generated from the following file: +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 +edma3.h}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 \sect +}\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_InstanceInitConfig Struct Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 \tcl2 +{\*\bkmkstart _Toc211937267}EDMA3_DRV_InstanceInitConfig{\*\bkmkend _Toc211937267}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 +\ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 EDMA3_DRV_InstanceInitConfig}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAMN}{\*\bkmkend AAAAAAAAMN}Init-time Region Specific Configuration structure for EDMA3 Driver, to provide region specific Information. +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid6424133 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Data Fields +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 ownPaRAMSets}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [EDMA3_MAX_PARAM_DWRDS] +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 ownDmaChannels}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 [EDMA3_MAX_DMA_CHAN_DWRDS] +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 ownQdmaChannels}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 [EDMA3_MAX_QDMA_CHAN_DWRDS] +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 ownTccs}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 [EDMA3_MAX_TCC_DWRDS] +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 resvdPaRAMSets}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 [EDMA3_MAX_PARAM_DWRDS] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Reserved PaRAM Sets. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 resvdDmaChannels}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [EDMA3_MAX_DMA_CHAN_DWRDS] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Reserved DMA channels. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 resvdQdmaChannels}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [EDMA3_MAX_QDMA_CHAN_DWRDS] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Reserved QDMA channels. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 resvdTccs}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [EDMA3_MAX_TCC_DWRDS] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 +\i\insrsid6424133 Reserved TCCs. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Init-time Region Specific Configuration structure for EDMA3 Driver, to provide region specific Information. +\par This configuration structure is used to specify which EDMA3 resources are owned and reserved by the EDMA3 Driver instance. This configuration structure is shadow region specific and will be provided by the user at run-time while calling EDMA3_DRV_open (). + +\par Owned resources: **************** +\par EDMA3 Driver Instances are tied to different shadow regions and hence different masters. Regions could be: +\par a) ARM, b) DSP, c) IMCOP (Imaging Co-processor) etc. +\par User can assign each EDMA3 resource to a shadow region using this structure. In this way, user specifies which resources are owned by the specific EDMA3 DRV + Instance. This assignment should also ensure that the same resource is not assigned to more than one shadow regions (unless desired in that way). Any assignment not following the above mentioned approach may have catastrophic consequences. +\par Reserved resources: ******************* +\par During EDMA3 DRV initialization, user can reserve some of the EDMA3 resources for future use, by specifying which resources to reserve in the configuration data structure. These (critical) resources are reserved in advance so that +they should not be allocated to someone else and thus could be used in future for some specific purpose. +\par User can request different EDMA3 resources using two methods: a) By passing the resource type and the actual resource id, b) By passing the resource type and ANY as resource id +\par For e.g. to request DMA channel 31, user will pass 31 as the resource id. But to request ANY available DMA channel (mainly used for memory-to-memory data transfer operations), user will pass EDMA3_DRV_DMA_CHANNEL_ANY as the resource id. +\par During initialization, user may have reserved some of the DMA channels for some specific purpose (mainly for peripherals using EDMA). These reserved DMA channels then will not be returned when user requests ANY as the resource id. +\par Same logic applies for QDMA channels and TCCs. +\par For PaRAM Set, there is one difference. If the DMA channels are one-to-one tied to their respective PaRAM Sets (i.e. user cannot 'choose' the PaRAM Set for a particular DMA channel), EDMA3 Driver automatically reserves all those PaRAM Sets which are tied +t +o the DMA channels. Then those PaRAM Sets would not be returned when user requests for ANY PaRAM Set (specifically for linking purpose). This is done in order to avoid allocating the PaRAM Set, tied to a particular DMA channel, for linking purpose. If thi +s constraint is not there, that DMA channel thus could not be used at all, because of the unavailability of the desired PaRAM Set. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Field Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 +\ltrch\fcs0 \fs24\insrsid6424133 ownPaRAMSets\:EDMA3_DRV_InstanceInitConfig}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 EDMA3_DRV_InstanceInitConfig\:ownPaRAMSets}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 +\af1 \ltrch\fcs0 \insrsid6424133 unsigned int EDMA3_DRV_InstanceInitConfig::ownPaRAMSets[EDMA3_MAX_PARAM_DWRDS] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAOI}{\*\bkmkend AAAAAAAAOI}PaRAM Sets owned by the EDMA3 Driver Instance. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 ownDmaChannels\:EDMA3_DRV_InstanceInitConfig}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_InstanceInitConfig\:ownDmaChannels}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 unsigned int EDMA3_DRV_InstanceInitConfig::ownDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAOJ}{\*\bkmkend AAAAAAAAOJ}DMA Channels owned by the EDMA3 Driver Instance. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 ownQdmaChannels\:EDMA3_DRV_InstanceInitConfig}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_InstanceInitConfig\:ownQdmaChannels}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 unsigned int EDMA3_DRV_InstanceInitConfig::ownQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAOK}{\*\bkmkend AAAAAAAAOK}QDMA Channels owned by the EDMA3 Driver Instance. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 ownTccs\:EDMA3_DRV_InstanceInitConfig}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_InstanceInitConfig\:ownTccs}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +unsigned int EDMA3_DRV_InstanceInitConfig::ownTccs[EDMA3_MAX_TCC_DWRDS] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAOL}{\*\bkmkend AAAAAAAAOL}TCCs owned by the EDMA3 Driver Instance. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 resvdPaRAMSets\:EDMA3_DRV_InstanceInitConfig}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_InstanceInitConfig\:resvdPaRAMSets}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 unsigned int EDMA3_DRV_InstanceInitConfig::resvdPaRAMSets[EDMA3_MAX_PARAM_DWRDS] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAOM}{\*\bkmkend AAAAAAAAOM}Reserved PaRAM Sets. +\par PaRAM Sets reserved during initialization for future use. These will not be given when user requests for ANY available PaRAM Set for linking using 'EDMA3_DRV_LINK_CHANNEL' as channel id. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 resvdDmaChannels\:EDMA3_DRV_InstanceInitConfig}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_InstanceInitConfig\:resvdDmaChannels}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 unsigned int EDMA3_DRV_InstanceInitConfig::resvdDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAON}{\*\bkmkend AAAAAAAAON}Reserved DMA channels. +\par DMA channels reserved during initialization for future use. These will not be given when user requests for ANY available DMA channel using 'EDMA3_DRV_DMA_CHANNEL_ANY' as channel id. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 resvdQdmaChannels\:EDMA3_DRV_InstanceInitConfig}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_InstanceInitConfig\:resvdQdmaChannels}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 unsigned int EDMA3_DRV_InstanceInitConfig::resvdQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAOO}{\*\bkmkend AAAAAAAAOO}Reserved QDMA channels. +\par QDMA channels reserved during initialization for future use. These will not be given when user requests for ANY available QDMA channel using 'EDMA3_DRV_QDMA_CHANNEL_ANY' as channel id. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 resvdTccs\:EDMA3_DRV_InstanceInitConfig}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_InstanceInitConfig\:resvdTccs}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +unsigned int EDMA3_DRV_InstanceInitConfig::resvdTccs[EDMA3_MAX_TCC_DWRDS] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAOP}{\*\bkmkend AAAAAAAAOP}Reserved TCCs. +\par TCCs reserved during initialization for future use. These will not be given when user requests for ANY available TCC using 'EDMA3_DRV_TCC_ANY' as resource id. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\fs22\insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +The documentation for this struct was generated from the following file: +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 e +dma3_drv.h}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 \sect +}\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_MiscParam Struct Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 \tcl2 +{\*\bkmkstart _Toc211937268}EDMA3_DRV_MiscParam{\*\bkmkend _Toc211937268}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 +\v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 EDMA3_DRV_MiscParam}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAMO} +{\*\bkmkend AAAAAAAAMO}Used to specify the miscellaneous options during EDMA3 Driver Initialization. +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid6424133 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Data Fields +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +unsigned short }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 isSlave}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 unsigned short }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 param}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Used to specify the miscellaneous options during EDMA3 Driver Initialization. +\par This configuration structure is used to specify some misc options while creating the Driver object. New options may also be added into this structure in future. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Field Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 +\ltrch\fcs0 \fs24\insrsid6424133 isSlave\:EDMA3_DRV_MiscParam}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 EDMA3_DRV_MiscParam\:isSlave}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 unsigned short EDMA3_DRV_MiscParam::isSlave +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAOQ}{\*\bkmkend AAAAAAAAOQ} +In a multi-master system (for e.g. ARM + DSP), this option is used to distinguish between Master and Slave. Only the Master is allowed to program the global EDMA3 registers (like Queue priority, Queue water- mark level, error registers etc). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 param\:EDMA3_DRV_MiscParam}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_MiscParam\:param}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +unsigned short EDMA3_DRV_MiscParam::param +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAOR}{\*\bkmkend AAAAAAAAOR}For future use +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\fs22\insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +The documentation for this struct was generated from the following file: +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 +edma3_drv.h}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 \sect +}\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Object Struct Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 \tcl2 +{\*\bkmkstart _Toc211937269}EDMA3_DRV_Object{\*\bkmkend _Toc211937269}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 +\v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 EDMA3_DRV_Object}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAMP} +{\*\bkmkend AAAAAAAAMP}EDMA3 Driver Object (HW Specific) Maintenance structure. +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid6424133 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Data Fields +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 phyCtrllerInstId}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ObjState}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 state}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 numOpens}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_GblConfigParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid6424133 gblCfgParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 +\i\insrsid6424133 Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3 Driver Object (HW Specific) Maintenance structure. +\par Used to maintain information of the EDMA3 HW configuration thoughout the lifetime of the EDMA3 Driver Object, one for each EDMA3 hardware instance. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Field Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 +\ltrch\fcs0 \fs24\insrsid6424133 phyCtrllerInstId\:EDMA3_DRV_Object}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 EDMA3_DRV_Object\:phyCtrllerInstId}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 unsigned int EDMA3_DRV_Object::phyCtrllerInstId +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAOS}{\*\bkmkend AAAAAAAAOS}Physical Instance ID of EDMA3 Controller +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_create(), EDMA3_DRV_enableTransfer(), EDMA3_DRV_freeChannel(), EDMA3_DRV_getOptField(), EDMA3_DRV_getPaRAM(), EDMA3_DRV_getPaRAMEntry(), EDMA3_DRV_getPaRAM +Field(), EDMA3_DRV_getPaRAMPhyAddr(), EDMA3_DRV_linkChannel(), EDMA3_DRV_requestChannel(), EDMA3_DRV_setDestIndex(), EDMA3_DRV_setDestParams(), EDMA3_DRV_setOptField(), EDMA3_DRV_setPaRAM(), EDMA3_DRV_setPaRAMEntry(), EDMA3_DRV_setPaRAMField(), EDMA3_DRV_ +setSrcIndex(), EDMA3_DRV_setSrcParams(), EDMA3_DRV_setTransferParams(), EDMA3_DRV_unchainChannel(), EDMA3_DRV_unlinkChannel(), and edma3RemoveMapping(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 state\:EDMA3_DRV_Object}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Object\:state}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_ObjState EDMA3_DRV_Object::state +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAOT}{\*\bkmkend AAAAAAAAOT}State information of the EDMA3 Driver object +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_close(), EDMA3_DRV_create(), EDMA3_DRV_delete(), and EDMA3_DRV_open(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 numOpens\:EDMA3_DRV_Object}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Object\:numOpens}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +unsigned int EDMA3_DRV_Object::numOpens +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAOU}{\*\bkmkend AAAAAAAAOU}Number of EDMA3 Driver instances +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_close(), EDMA3_DRV_create(), and EDMA3_DRV_open(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 gblCfgParams\:EDMA3_DRV_Object}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Object\:gblCfgParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_GblConfigParams EDMA3_DRV_Object::gblCfgParams +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAOV}{\*\bkmkend AAAAAAAAOV}Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. +\par This configuration info can be provided by the user at run-time, while calling }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_create()}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +. If not provided at run-time, this info will be taken from the config file edma3Cfg.c. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_checkAndClearTcc(), EDMA3_DRV_clearErrorBits(), EDMA3_DRV_create(), EDMA3_DRV_disableTransfer(), EDMA3_DRV_enableTran +sfer(), EDMA3_DRV_freeChannel(), EDMA3_DRV_getCCRegister(), EDMA3_DRV_getInstHandle(), EDMA3_DRV_getMapChToEvtQ(), EDMA3_DRV_getOptField(), EDMA3_DRV_getPaRAM(), EDMA3_DRV_getPaRAMEntry(), EDMA3_DRV_getPaRAMField(), EDMA3_DRV_getPaRAMPhyAddr(), EDMA3_DRV_ +l +inkChannel(), EDMA3_DRV_mapChToEvtQ(), EDMA3_DRV_open(), EDMA3_DRV_requestChannel(), EDMA3_DRV_setCCRegister(), EDMA3_DRV_setDestIndex(), EDMA3_DRV_setDestParams(), EDMA3_DRV_setEvtQPriority(), EDMA3_DRV_setOptField(), EDMA3_DRV_setPaRAM(), EDMA3_DRV_setP +a +RAMEntry(), EDMA3_DRV_setPaRAMField(), EDMA3_DRV_setQdmaTrigWord(), EDMA3_DRV_setSrcIndex(), EDMA3_DRV_setSrcParams(), EDMA3_DRV_setTransferParams(), EDMA3_DRV_unchainChannel(), EDMA3_DRV_unlinkChannel(), EDMA3_DRV_waitAndClearTcc(), and edma3RemoveMappin +g(). +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\fs22\insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +The documentation for this struct was generated from the following file: +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 +edma3.h}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 \sect +}\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_ParamentryRegs Struct Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 \tcl2 +{\*\bkmkstart _Toc211937270}EDMA3_DRV_ParamentryRegs{\*\bkmkend _Toc211937270}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 +\v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 EDMA3_DRV_ParamentryRegs}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAMQ} +{\*\bkmkend AAAAAAAAMQ}EDMA3 PaRAM Set. +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid6424133 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Data Fields +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +volatile unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 OPT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 volatile unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 SRC}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 {\*\bkmkstart AAAAAAAAOW}{\*\bkmkend AAAAAAAAOW} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Starting byte address of Source For FIFO mode, srcAddr must be a 256-bit aligned address. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +volatile unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 A_B_CNT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 volatile unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 DST}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 {\*\bkmkstart AAAAAAAAOX}{\*\bkmkend AAAAAAAAOX} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Starting byte address of destination For FIFO mode, destAddr must be a 256-bit aligned address. i.e. 5 LSBs should be 0. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +volatile unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 SRC_DST_BIDX}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 volatile unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 LINK_BCNTRLD}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Address for linking (AutoReloading of a PaRAM Set) (16 bits) and Reload value of the numArrInFrame (BCNT) (16 bits). +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +volatile unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 SRC_DST_CIDX}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAOY}{\*\bkmkend AAAAAAAAOY} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Index between consecutive frames of a Source Block (SRCCIDX) (16 bits) and Index between consecutive frames of a Dest Block (DSTCIDX) (16 bits). +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +volatile unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 CCNT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAOZ}{\*\bkmkend AAAAAAAAOZ} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 +\i\insrsid6424133 Number of Frames in a block (CCNT) (16 bits). +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3 PaRAM Set. +\par This is a mapping of the EDMA3 PaRAM set provided to the user for ease of modification of the individual PaRAM words. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Field Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 +\ltrch\fcs0 \fs24\insrsid6424133 OPT\:EDMA3_DRV_ParamentryRegs}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 EDMA3_DRV_ParamentryRegs\:OPT}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 volatile unsigned int EDMA3_DRV_ParamentryRegs::OPT +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAPA}{\*\bkmkend AAAAAAAAPA}OPT field of PaRAM Set +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 A_B_CNT\:EDMA3_DRV_ParamentryRegs}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_ParamentryRegs\:A_B_CNT}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +volatile unsigned int EDMA3_DRV_ParamentryRegs::A_B_CNT +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAPB}{\*\bkmkend AAAAAAAAPB}Number of bytes in each Array (ACNT) (16 bits) and Number of Arrays in each Frame (BCNT) (16 bits). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 SRC_DST_BIDX\:EDMA3_DRV_ParamentryRegs}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_ParamentryRegs\:SRC_DST_BIDX}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +volatile unsigned int EDMA3_DRV_ParamentryRegs::SRC_DST_BIDX +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAPC}{\*\bkmkend AAAAAAAAPC}Index between consec. arrays of a Source Frame (SRCBIDX) (16 bits) and Index between consec. arrays of a Destination Frame (DSTBIDX) (16 bits). +\par If SAM is set to 1 (via channelOptions) then srcInterArrIndex should be an even multiple of 32 bytes. +\par If DAM is set to 1 (via channelOptions) then destInterArrIndex should be an even multiple of 32 bytes +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 LINK_BCNTRLD\:EDMA3_DRV_ParamentryRegs}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_ParamentryRegs\:LINK_BCNTRLD}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +volatile unsigned int EDMA3_DRV_ParamentryRegs::LINK_BCNTRLD +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAPD}{\*\bkmkend AAAAAAAAPD}Address for linking (AutoReloading of a PaRAM Set) (16 bits) and Reload value of the numArrInFrame (BCNT) (16 bits). +\par Link field must point to a valid aligned 32-byte PaRAM set A value of 0xFFFF means no linking. +\par B count reload field is relevant only for A-sync transfers. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\fs22\insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 The documenta +tion for this struct was generated from the following file: +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 +edma3_drv.h}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 \sect +}\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_PaRAMRegs Struct Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 \tcl2 +{\*\bkmkstart _Toc211937271}EDMA3_DRV_PaRAMRegs{\*\bkmkend _Toc211937271}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 +\v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 EDMA3_DRV_PaRAMRegs}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAMR} +{\*\bkmkend AAAAAAAAMR}EDMA3 Parameter RAM Set in User Configurable format. +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid6424133 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Data Fields +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +volatile unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 opt}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 volatile unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 srcAddr}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAPE}{\*\bkmkend AAAAAAAAPE} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Starting byte address of Source For FIFO mode, srcAddr must be a 256-bit aligned address. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +volatile unsigned short }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 aCnt}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAPF}{\*\bkmkend AAAAAAAAPF} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Number of bytes in each Array (ACNT). +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +volatile unsigned short }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 bCnt}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAPG}{\*\bkmkend AAAAAAAAPG} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Number of Arrays in each Frame (BCNT). +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +volatile unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 destAddr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAPH}{\*\bkmkend AAAAAAAAPH} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Starting byte address of destination For FIFO mode, destAddr must be a 256-bit aligned address. i.e. 5 LSBs should be 0. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +volatile short }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 srcBIdx}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAPI}{\*\bkmkend AAAAAAAAPI} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Index between consec. arrays of a Source Frame (SRCBIDX) If SAM is set to 1 (via channelOptions) then srcInterArrIndex should be an even multiple of 32 bytes. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +volatile short }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 destBIdx}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAPJ}{\*\bkmkend AAAAAAAAPJ} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Index between consec. arrays of a Destination Frame (DSTBIDX) If DAM is set to 1 (via channelOptions) then destInterArrIndex should be an even multiple of 32 bytes. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +volatile unsigned short }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 linkAddr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAPK}{\*\bkmkend AAAAAAAAPK} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Addre +ss for linking (AutoReloading of a PaRAM Set) This must point to a valid aligned 32-byte PaRAM set A value of 0xFFFF means no linking Linking is especially useful for use with ping-pong buffers and circular buffers. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +volatile unsigned short }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 bCntReload}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAPL}{\*\bkmkend AAAAAAAAPL} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Reload value of the numArrInFrame (BCNT) Relevant only for A-sync transfers. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +volatile short }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 srcCIdx}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAPM}{\*\bkmkend AAAAAAAAPM} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Index between consecutive frames of a Source Block (SRCCIDX). +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +volatile short }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 destCIdx}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAPN}{\*\bkmkend AAAAAAAAPN} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Index between consecutive frames of a Dest Block (DSTCIDX). +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +volatile unsigned short }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 cCnt}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAPO}{\*\bkmkend AAAAAAAAPO} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 +\i\insrsid6424133 Number of Frames in a block (CCNT). +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3 Parameter RAM Set in User Configurable format. +\par This is a mapping of the EDMA3 PaRAM set provided to the user for ease of modification of the individual fields +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Field Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 +\ltrch\fcs0 \fs24\insrsid6424133 opt\:EDMA3_DRV_PaRAMRegs}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 EDMA3_DRV_PaRAMRegs\:opt}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 volatile unsigned int EDMA3_DRV_PaRAMRegs::opt +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAPP}{\*\bkmkend AAAAAAAAPP}OPT field of PaRAM Set +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\fs22\insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +The documentation for this struct was generated from the following file: +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 +edma3_drv.h}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 \sect +}\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s1\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs36\alang1025 \ltrch\fcs0 +\b\f1\fs36\lang1033\langfe1033\kerning36\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 File Documentation}{\pard\plain \ltrpar +\s1\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs36\alang1025 \ltrch\fcs0 \b\v\f1\fs36\lang1033\langfe1033\kerning36\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 {\*\bkmkstart _Toc211937272}File Documentation{\*\bkmkend _Toc211937272}}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 edma3.h File Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 \tcl2 +{\*\bkmkstart _Toc211937273}edma3.h{\*\bkmkend _Toc211937273}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 +\v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 edma3.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAAA} +{\*\bkmkend AAAAAAAAAA}EDMA3 Driver Internal header file. +\par }\pard\plain \ltrpar\s18\ql \li0\ri0\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid6424133 +#include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid6424133 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Data Structures +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_Object}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 EDMA3 Driver Object (HW Specific) Maintenance structure. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_Instance}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 EDMA3 Driver Instance Configuration Structure. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ChBoundResources}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 EDMA3 Channel-Bound resources. +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Defines +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define } +{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_SAM_CLR_MASK}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \~ (~EDMA3_CCRL_OPT_SAM_MASK) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_SAM_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (mode)\~ (((EDMA3_CCRL_OPT_SAM_MASK >> EDMA3_CCRL_OPT_SAM_SHIFT) & (mode)) << EDMA3_CCRL_OPT_SAM_SHIFT) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_DAM_CLR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (~EDMA3_CCRL_OPT_DAM_MASK) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_DAM_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (mode)\~ (((EDMA3_CCRL_OPT_DAM_MASK >> EDMA3_CCRL_OPT_DAM_SHIFT) & (mode)) << EDMA3_CCRL_OPT_DAM_SHIFT) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_SYNCDIM_CLR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (~EDMA3_CCRL_OPT_SYNCDIM_MASK) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_SYNCDIM_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (synctype)\~ (((EDMA3_CCRL_OPT_SYNCDIM_MASK >> EDMA3_CCRL_OPT_SYNCDIM_SHIFT) & (synctype)) << EDMA3_CCRL_OPT_SYNCDIM_SHIFT) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_STATIC_CLR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (~EDMA3_CCRL_OPT_STATIC_MASK) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_STATIC_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (en)\~ (((EDMA3_CCRL_OPT_STATIC_MASK >> EDMA3_CCRL_OPT_STATIC_SHIFT) & (en)) << EDMA3_CCRL_OPT_STATIC_SHIFT) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_FWID_CLR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (~EDMA3_CCRL_OPT_FWID_MASK) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_FWID_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (width)\~ (((EDMA3_CCRL_OPT_FWID_MASK >> EDMA3_CCRL_OPT_FWID_SHIFT) & (width)) << EDMA3_CCRL_OPT_FWID_SHIFT) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_TCCMODE_CLR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (~EDMA3_CCRL_OPT_TCCMODE_MASK) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_TCCMODE_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (early)\~ (((EDMA3_CCRL_OPT_TCCMODE_MASK >> EDMA3_CCRL_OPT_TCCMODE_SHIFT) & (early)) << EDMA3_CCRL_OPT_TCCMODE_SHIFT) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_TCC_CLR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (~EDMA3_CCRL_OPT_TCC_MASK) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_TCC_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (tcc)\~ (((EDMA3_CCRL_OPT_TCC_MASK >> EDMA3_CCRL_OPT_TCC_SHIFT) & (tcc)) << EDMA3_CCRL_OPT_TCC_SHIFT) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_TCINTEN_CLR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (~EDMA3_CCRL_OPT_TCINTEN_MASK) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_TCINTEN_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (tcinten)\~ (((EDMA3_CCRL_OPT_TCINTEN_MASK >> EDMA3_CCRL_OPT_TCINTEN_SHIFT) & (tcinten)) << EDMA3_CCRL_OPT_TCINTEN_SHIFT) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_ITCINTEN_CLR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (~EDMA3_CCRL_OPT_ITCINTEN_MASK) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_ITCINTEN_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (itcinten)\~ (((EDMA3_CCRL_OPT_ITCINTEN_MASK >> EDMA3_CCRL_OPT_ITCINTEN_SHIFT) & (itcinten)) << EDMA3_CCRL_OPT_ITCINTEN_SHIFT) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_TCCHEN_CLR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (~EDMA3_CCRL_OPT_TCCHEN_MASK) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_TCCHEN_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (tcchen)\~ (((EDMA3_CCRL_OPT_TCCHEN_MASK >> EDMA3_CCRL_OPT_TCCHEN_SHIFT) & (tcchen)) << EDMA3_CCRL_OPT_TCCHEN_SHIFT) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_ITCCHEN_CLR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (~EDMA3_CCRL_OPT_ITCCHEN_MASK) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_ITCCHEN_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (itcchen)\~ (((EDMA3_CCRL_OPT_ITCCHEN_MASK >> EDMA3_CCRL_OPT_ITCCHEN_SHIFT) & (itcchen)) << EDMA3_CCRL_OPT_ITCCHEN_SHIFT) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_SAM_GET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (mode)\~ ((mode)&1u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_DAM_GET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (mode)\~ (((mode)&(1u<<1u))>>1u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_SYNCDIM_GET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (synctype)\~ (((synctype)&(1u<<2u))>>2u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_STATIC_GET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (en)\~ (((en)&(1u<<3u))>>3u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_FWID_GET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (width)\~ (((width)&(0x7u<<8u))>>8u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_TCCMODE_GET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (early)\~ (((early)&(1u<<11u))>>11u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_TCC_GET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (tcc)\~ (((tcc)&(0x3fu<<12u))>>12u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_TCINTEN_GET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (tcinten)\~ (((tcinten)&(1u<<20u))>>20u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_ITCINTEN_GET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (itcinten)\~ (((itcinten)&(1u<<21u))>>21u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_TCCHEN_GET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (tcchen)\~ (((tcchen)&(1u<<22u))>>22u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_ITCCHEN_GET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (itcchen)\~ (((itcchen)&(1u<<23u))>>23u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_DMAQNUM_CLR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (chNum)\~ (~(0x7u<<(((chNum)%8u)*4u))) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_DMAQNUM_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (chNum, queNum)\~ ((0x7u & (queNum)) << (((chNum)%8u)*4u)) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_QDMAQNUM_CLR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (chNum)\~ (~(0x7u<<((chNum)*4u))) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_QDMAQNUM_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (chNum, queNum)\~ ((0x7u & (queNum)) << ((chNum)*4u)) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_QCH_TRWORD_CLR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (~EDMA3_CCRL_QCHMAP_TRWORD_MASK) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_QCH_TRWORD_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (paRAMId)\~ (((EDMA3_CCRL_QCHMAP_TRWORD_MASK >> EDMA3_CCRL_QCHMAP_TRWORD_SHIFT) & (paRAMId)) << EDMA3_CCRL_QCHMAP_TRWORD_SHIFT) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ACNT_MAX_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (0xFFFFu) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_BCNT_MAX_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (0xFFFFu) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_CCNT_MAX_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (0xFFFFu) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_BCNTRELD_MAX_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (0xFFFFu) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_SRCBIDX_MAX_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (0x7FFF) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_SRCBIDX_MIN_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (-32768) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_SRCCIDX_MAX_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (0x7FFF) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_SRCCIDX_MIN_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (-32768) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_DSTBIDX_MAX_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (0x7FFF) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_DSTBIDX_MIN_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (-32768) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_DSTCIDX_MAX_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (0x7FFF) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_DSTCIDX_MIN_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (-32768) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_QPRIORITY_MAX_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (7u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_QPRIORITY_MIN_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (0u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_DMA_CH_MAX_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_MAX_DMA_CH - 1u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_LINK_CH_MIN_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_DMA_CH_MAX_VAL + 1u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_LINK_CH_MAX_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_LINK_CH_MIN_VAL + EDMA3_MAX_PARAM_SETS - 1u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_QDMA_CH_MIN_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_LINK_CH_MAX_VAL + 1u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_QDMA_CH_MAX_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_QDMA_CH_MIN_VAL + EDMA3_MAX_QDMA_CH - 1u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_LOG_CH_MAX_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_QDMA_CH_MAX_VAL) +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Enumerations +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ObjState}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_DELETED}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 0, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_CREATED}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 1, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPENED}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 2, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_CLOSED}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 3 \} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 enum }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ChannelType}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_CHANNEL_TYPE_NONE}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_CHANNEL_TYPE_DMA}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 = 1, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_CHANNEL_TYPE_QDMA}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 2, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_CHANNEL_TYPE_LINK}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 3 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 +\i\insrsid6424133 EDMA3 Channel Type. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3 Driver Internal header file. +\par This file contains implementation specific details used by the EDMA3 Driver internally. +\par (C) Copyright 2006, Texas Instruments, Inc +\par }\pard\plain \ltrpar\s5\qj \li0\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Version: +\par }\pard\plain \ltrpar\s43\ql \li360\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +0.1.0 Joseph Fernandez - Created 0.2.0 Anuj Aggarwal - Modified it for EDMA3 package +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Added multiple instances capability 0.2.1 Anuj Aggarwal - Modified it for more run time configuration. +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Made EDMA3 package OS independent. 0.2.2 Anuj Aggarwal - Critical section handling code modification. Uses semaphore and interrupts disabling mechanism for resource sharing. 0.3.0 Anuj Aggarwal - Renamed EDMA3_DVR to EDMA3_DRV +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 IPR bit clearing in RM ISR issue fixed. +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Sample application made generic 0.3.1 Anuj Aggarwal - Added DMA/QDMA Channel to TCC mapping, to fix QDMA missed event issue. 0.3.2 Anuj Aggarwal - Added support for POLL mode +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Added a new API to modify the CC Register. 1.0.0 Anuj Aggarwal - Fixed resource allocation related bugs. 1.0.0.1 Anuj Aggarwal - Fixed spurious missed event generation related bug. 1.0.0.2 Anuj Aggarwal - Made the EDMA3 package RTSC compliant. 1.0.0.3 An +uj Aggarwal - Changed the directory structure as per RTSC standard. 1.01.00.01 Anuj Aggarwal - a) Added new APIs to allocate logical channels b) Created EDMA3 config files for different platforms c) Misc changes 1.02.00.01 Anuj Aggarwal - a) Added DM6467 +support b) Fixed some MRs 1.03.00.01 Anuj Aggarwal - a) Added non-RTSC PJT files b) IOCTL Interface added. c) Fixed some MRs. 1.04 Anuj Aggarwal - a) Header files modified to have extern "C" declarations. b) Implemented ECNs DPSP00009815 & DPSP00010035. + +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 +\par \sect }\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 edma3_drv.h File Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 \tcl2 +{\*\bkmkstart _Toc211937274}edma3_drv.h{\*\bkmkend _Toc211937274}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 +\v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 edma3_drv.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAAB} +{\*\bkmkend AAAAAAAAAB}EDMA3 Controller. +\par }\pard\plain \ltrpar\s18\ql \li0\ri0\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid6424133 +#include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Data Structures +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_GblConfigParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_InstanceInitConfig}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Init-time Region Specific Configuration structure for EDMA3 Driver, to provide region specific Information. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_InitConfig}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Used to Initialize the EDMA3 Driver Instance. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_MiscParam}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Used to specify the miscellaneous options during EDMA3 Driver Initialization. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ChainOptions}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Structure to be used to configure interrupt generation and chaining options. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ParamentryRegs}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 EDMA3 PaRAM Set. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PaRAMRegs}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 EDMA3 Parameter RAM Set in User Configurable format. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_EvtQuePriority}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Event queue priorities setup. +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Defines +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define } +{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_E_BASE}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \~ (-128) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_E_OBJ_NOT_DELETED}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_E_BASE) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_E_OBJ_NOT_CLOSED}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_E_BASE-1) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_E_OBJ_NOT_OPENED}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_E_BASE-2) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_E_RM_CLOSE_FAIL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_E_BASE-3) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_E_BASE-4) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_E_BASE-5) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_E_PARAM_SET_UNAVAIL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_E_BASE-6) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_E_TCC_UNAVAIL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_E_BASE-7) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_E_TCC_REGISTER_FAIL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_E_BASE-8) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_E_CH_PARAM_BIND_FAIL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_E_BASE-9) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_E_ADDRESS_NOT_ALIGNED}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_E_BASE-10) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_E_INVALID_PARAM}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_E_BASE-11) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_E_INVALID_STATE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_E_BASE-12) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_E_INST_ALREADY_EXISTS}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_E_BASE-13) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_E_BASE-14) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_E_SEMAPHORE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_E_BASE-15) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_E_INST_NOT_OPENED}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_E_BASE-16) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_CH_NO_PARAM_MAP}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ EDMA3_RM_CH_NO_PARAM_MAP +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_CH_NO_TCC_MAP}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ EDMA3_RM_CH_NO_TCC_MAP +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_DMA_CHANNEL_ANY}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ 1002u +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_QDMA_CHANNEL_ANY}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ 1003u +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TCC_ANY}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 \~ 1004u +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_LINK_CHANNEL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ 1005u +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_QDMA_CHANNEL_0}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 QDMA Channel defines They should be used while requesting a specific QDMA channel. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define } +{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_QDMA_CHANNEL_1}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_QDMA_CHANNEL_0+1u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_QDMA_CHANNEL_2}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_QDMA_CHANNEL_0+2u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_QDMA_CHANNEL_3}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_QDMA_CHANNEL_0+3u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_QDMA_CHANNEL_4}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_QDMA_CHANNEL_0+4u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_QDMA_CHANNEL_5}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_QDMA_CHANNEL_0+5u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_QDMA_CHANNEL_6}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_QDMA_CHANNEL_0+6u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_QDMA_CHANNEL_7}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 \~ (EDMA3_DRV_QDMA_CHANNEL_0+7u) +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Enumerations +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_0}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 + = 0, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_1}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_2}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_3}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_4}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_5}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_6}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_7}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_8}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_9}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 +EDMA3_DRV_HW_CHANNEL_EVENT_10}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_11}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_12}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_13}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_14}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_15}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 +\ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_16}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_17}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_18}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_19}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_20}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_21}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_22}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_23}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_24}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_25}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_26}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 +EDMA3_DRV_HW_CHANNEL_EVENT_27}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_28}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_29}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_30}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_31}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_32}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 +\ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_33}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_34}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_35}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_36}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_37}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_38}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_39}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_40}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_41}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_42}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_43}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 +EDMA3_DRV_HW_CHANNEL_EVENT_44}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_45}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_46}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_47}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_48}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_49}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 +\ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_50}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_51}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_52}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_53}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_54}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_55}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_56}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_57}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_58}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_59}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_60}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHA +NNEL_EVENT_61}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_62}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 +EDMA3_DRV_HW_CHANNEL_EVENT_63}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 DMA Channels assigned to different Hardware Events. They should be used while requesting a specific DMA channel. One possible usage is to maintain a SoC specific file, which will + contain the mapping of these hardware events to the respective peripherals for better understanding and lesser probability of errors. Also, if any event associated with a particular peripheral gets changed, only that SoC specific file needs to be changed +. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OptField}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_FIELD_SAM}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 0, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_FIELD_DAM}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 1, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_FIELD_SYNCDIM}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 + = 2, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_FIELD_STATIC}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 3, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_FIELD_FWID}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 = 4, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_FIELD_TCCMODE}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 5, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_FIELD_TCC}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 = 6, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_FIELD_TCINTEN}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 7, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_FIELD_ITCINTEN}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 8, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OPT_FIELD_TCCHEN}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 9, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 +EDMA3_DRV_OPT_FIELD_ITCCHEN}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 10 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 OPT Field Offset. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_AddrMode}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ADDR_MODE_INCR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 0, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ADDR_MODE_FIFO}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 1 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 EDMA Addressing modes. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_SyncType}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_SYNC_A}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 0, }{\rtlch\fcs1 +\ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_SYNC_AB}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 1 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 EDMA Transfer Synchronization type. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_StaticMode}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_STATIC_DIS}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 0, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_STATIC_EN}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 1 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 True/False: PaRAM set is Static or not. A Static PaRAM set is updated or linked after TR is submitted. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_FifoWidth}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_W8BIT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 0, }{\rtlch\fcs1 +\ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_W16BIT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 1, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_W32BIT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 2, }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_W64BIT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 3, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_W128BIT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 4, }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_W256BIT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 5 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 EDMA3 FIFO width. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TccMode}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TCCMODE_NORMAL}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 0, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TCCMODE_EARLY}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 1 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Transfer complete code mode. Indicates the point at which a transfer is considered completed for chaining and interrupt generation. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TcintEn}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TCINTEN_DIS}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 0, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TCINTEN_EN}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 1 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Transfer complete interrupt enable. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ItcintEn}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ITCINTEN_DIS}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 0, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ITCINTEN_EN}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 1 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Intermediate Transfer complete interrupt enable. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TcchEn}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TCCHEN_DIS}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 0, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TCCHEN_EN}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 1 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Transfer complete chaining enable. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ItcchEn}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ITCCHEN_DIS}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 0, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ITCCHEN_EN}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 1 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Intermediate Transfer complete chaining enable. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TrigMode}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TRIG_MODE_MANUAL}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 0, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TRIG_MODE_QDMA}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 1, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TRIG_MODE_EVENT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 + = 2, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TRIG_MODE_NONE}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 3 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 EDMA Trigger Mode Selection. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PaRAMEntry}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PARAM_ENTRY_OPT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 0, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PARAM_ENTRY_SRC}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 1, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 = 2, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PARAM_ENTRY_DST}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 3, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 = 4, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 5, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 +EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 6, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PARAM_ENTRY_CCNT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 7 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 PaRAM Set Entry type. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PaRAMField}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PARAM_FIELD_OPT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 0, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PARAM_FIELD_SRCADDR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 1, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PARAM_FIELD_ACNT}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 = 2, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PARAM_FIELD_BCNT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 3, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PARAM_FIELD_DESTADDR}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 = 4, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PARAM_FIELD_SRCBIDX}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 5, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 +EDMA3_DRV_PARAM_FIELD_DESTBIDX}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 6, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PARAM_FIELD_LINKADDR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 7, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 EDMA3_DRV_PARAM_FIELD_BCNTRELOAD}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 8, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PARAM_FIELD_SRCCIDX}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 9, }{\rtlch\fcs1 +\ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PARAM_FIELD_DESTCIDX}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 10, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PARAM_FIELD_CCNT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 11 +\} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 PaRAM Set Field type. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_IoctlCmd}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_IOCTL_MIN_IOCTL}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 = 0, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_IOCTL_MAX_IOCTL}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 EDMA3 Driver IOCTL commands. +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Functions +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_create}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (unsigned int phyCtrllerInstId, const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_GblConfigParams}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 *gblCfgParams, const void *miscParam) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Create EDMA3 Driver Object. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_delete}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (unsigned int phyCtrllerInstId, const void *param) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Delete EDMA3 Driver Object. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Handle }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_open}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (unsigned int phyCtrllerInstId, const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_InitConfig}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 *initCfg, EDMA3_DRV_Result *errorCode) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Open EDMA3 Driver Instance. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_close}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, const void *param) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Close the EDMA3 Driver Instance. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_requestChannel}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 + (EDMA3_DRV_Handle hEdma, unsigned int *pLCh, unsigned int *pTcc, EDMA3_RM_EventQueue evtQueue, EDMA3_RM_TccCallback tccCb, void *cbData) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Request a DMA/QDMA/Link channel. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_freeChannel}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int channelId) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Free the specified channel (DMA/QDMA/Link) and its associated resources (PaRAM Set, TCC etc) and removes various mappings. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_clearErrorBits}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int channelId) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Clears Event Register and Error Register for a specific DMA channel and brings back EDMA3 to its initial state. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_linkChannel}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh1, unsigned int lCh2) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Link two logical channels. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_unlinkChannel}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Unlink the channel from the earlier linked logical channel. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setOptField}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OptField}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 optField, unsigned int newOptFieldVal) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Set a particular OPT field in the PaRAM set associated with the logical channel 'lCh'. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_getOptField}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OptField}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 optField, unsigned int *optFieldVal) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Get a particular OPT field in the PaRAM set associated with the logical channel 'lCh'. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setSrcParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int srcAddr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 EDMA3_DRV_AddrMode}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 addrMode, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_FifoWidth}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 fifoWidth) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 DMA source parameters setup. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setDestParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int destAddr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 EDMA3_DRV_AddrMode}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 addrMode, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_FifoWidth}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 fifoWidth) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 DMA Destination parameters setup. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setSrcIndex}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, int srcBIdx, int srcCIdx) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 DMA source index setup. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setDestIndex}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, int destBIdx, int destCIdx) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 DMA destination index setup. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setTransferParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 + (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int aCnt, unsigned int bCnt, unsigned int cCnt, unsigned int bCntReload, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_SyncType}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 syncType) + +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 DMA transfer parameters setup. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_chainChannel}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh1, unsigned int lCh2, const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 EDMA3_DRV_ChainOptions}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 *chainOptions) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Chain the two specified channels. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_unchainChannel}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Unchain the two channels. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 E +DMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_enableTransfer}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TrigMode}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 trigMode) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Start EDMA transfer on the specified channel. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_disableTransfer}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TrigMode +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 trigMode) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Disable DMA transfer on the specified channel. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setQdmaTrigWord}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_RM_QdmaTrigWord trigWord) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Assign a Trigger Word to the specified QDMA channel. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setPaRAM}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PaRAMRegs +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 *newPaRAM) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Copy the user specified PaRAM Set onto the PaRAM Set associated with the logical channel (DMA/QDMA/Link). +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_getPaRAM}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PaRAMRegs}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 *currPaRAM) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Retrieve existing PaRAM set associated with specified logical channel (DMA/QDMA/Link). +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setPaRAMEntry}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PaRAMEntry +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 paRAMEntry, unsigned int newPaRAMEntryVal) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Set a particular PaRAM set entry of the specified PaRAM set. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_getPaRAMEntry}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PaRAMEntry +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 paRAMEntry, unsigned int *paRAMEntryVal) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Get a particular PaRAM set entry of the specified PaRAM set. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setPaRAMField}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PaRAMField +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 paRAMField, unsigned int newPaRAMFieldVal) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Set a particular PaRAM set field of the specified PaRAM set. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_getPaRAMField}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PaRAMField +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 paRAMField, unsigned int *currPaRAMFieldVal) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Get a particular PaRAM set field of the specified PaRAM set. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setEvtQPriority}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_EvtQuePriority}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 *evtQPriObj) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Sets EDMA TC priority. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_mapChToEvtQ}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int channelId, EDMA3_RM_EventQueue eventQ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Associate Channel to Event Queue. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA +3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_getMapChToEvtQ}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int channelId, unsigned int *mappedEvtQ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Get the Event Queue mapped to the specified DMA/QDMA channel. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setCCRegister}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int regOffset, unsigned int newRegValue) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Set the Channel Controller (CC) Register value. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_getCCRegister}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int regOffset, unsigned int *regValue) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Get the Channel Controller (CC) Register value. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_waitAndClearTcc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int tccNo) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Wait for a transfer completion interrupt to occur and clear it. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_checkAndClearTcc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int tccNo, unsigned short *tccStatus) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Returns the status of a previously initiated transfer. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_getPaRAMPhyAddr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int *paramPhyAddr) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Get the PaRAM Set Physical Address associated with a logical channel. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_Ioctl}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_IoctlCmd}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 cmd, void *cmdArg, void *param) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 EDMA3 Driver IOCTL. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Handle }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_getInstHandle}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (unsigned int phyCtrllerInstId, EDMA3_RM_RegionId regionId, EDMA3_DRV_Result *errorCode) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 +\i\insrsid6424133 Return the previously opened EDMA3 Driver Instance handle. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3 Controller. +\par This file contains Application Interface for the EDMA3 Driver. EDMA3 Driver uses the EDMA3 Resource Manager internally for resource allocation, interrupt handling and EDMA3 registers programming. +\par (C) Copyright 2006, Texas Instruments, Inc +\par }\pard\plain \ltrpar\s5\qj \li0\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Version: +\par }\pard\plain \ltrpar\s43\ql \li360\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +0.0.1 Purushotam Kumar - Created 0.1.0 Joseph Fernandez - Made generic +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Added documentation +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Moved SoC specific defines to SoC specific header. 0.2.0 Anuj Aggarwal - Modified it for EDMA3 package +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Added multiple instances capability 0.2.1 Anuj Aggarwal - Modified it for more run time configuration. +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Made EDMA3 package OS independent. 0.2.2 Anuj Aggarwal - Critical section handling code modification. Uses semaphore and interrupts disabling mechanism for resource sharing. 0.3.0 Anuj Aggarwal - Renamed EDMA3_DVR to EDMA3_DRV +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 IPR bit clearing in RM ISR issue fixed. +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +Sample application made generic 0.3.1 Anuj Aggarwal - Added DMA/QDMA Channel to TCC mapping, to fix QDMA missed event issue. 0.3.2 Anuj Aggarwal - Added support for POLL mode +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Added a new API to modify the CC Register. 1.0.0 Anuj Aggarwal - Fixed + resource allocation related bugs. 1.0.0.1 Anuj Aggarwal - Fixed spurious missed event generation related bug. 1.0.0.2 Anuj Aggarwal - Made the EDMA3 package RTSC compliant. 1.0.0.3 Anuj Aggarwal - Changed the directory structure as per RTSC standard. 1.0 +1 +.00.01 Anuj Aggarwal - a) Added new APIs to allocate logical channels b) Created EDMA3 config files for different platforms c) Misc changes 1.02.00.01 Anuj Aggarwal - a) Added DM6467 support b) Fixed some MRs 1.03.00.01 Anuj Aggarwal - a) Added non-RTSC P +JT files b) IOCTL Interface added. c) Fixed some MRs. 1.04 Anuj Aggarwal - a) Header files modified to have extern "C" declarations. b) Implemented ECNs DPSP00009815 & DPSP00010035. +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 +\par \sect }\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 edma3_drv_adv.c File Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 \tcl2 +{\*\bkmkstart _Toc211937275}edma3_drv_adv.c{\*\bkmkend _Toc211937275}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 +\v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 edma3_drv_adv.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAAC} +{\*\bkmkend AAAAAAAAAC}EDMA3 Driver Advanced Interface Implementation This file contains advanced-level EDMA3 Driver APIs which are required to: a) Link and chain two channels. b) Set/get the whole PaRAM Set in one shot. c) Set/get each individu +al field of the PaRAM Set. d) Poll mode APIs. e) IOCTL interface. These APIs are provided to have complete control on the EDMA3 hardware and normally advanced users are expected to use them for their specific use-cases. +\par }\pard\plain \ltrpar\s18\ql \li0\ri0\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid6424133 +#include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid6424133 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Functions +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 void }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 edma3MemSet}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (void *dst, unsigned char data, unsigned int len) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 void }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 edma3MemCpy}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 (void *dst, const void *src, unsigned int len) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_linkChannel}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh1, unsigned int lCh2) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Link two logical channels. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_unlinkChannel}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Unlink the channel from the earlier linked logical channel. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_chainChannel}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh1, unsigned int lCh2, const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 EDMA3_DRV_ChainOptions}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 *chainOptions) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Chain the two specified channels. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_unchainChannel}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Unchain the two channels. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DR +V_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setQdmaTrigWord}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_RM_QdmaTrigWord trigWord) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Assign a Trigger Word to the specified QDMA channel. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setPaRAM}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PaRAMRegs +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 *newPaRAM) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Copy the user specified PaRAM Set onto the PaRAM Set associated with the logical channel (DMA/QDMA/Link). +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_getPaRAM}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PaRAMRegs}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 *currPaRAM) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Retrieve existing PaRAM set associated with specified logical channel (DMA/QDMA/Link). +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setPaRAMEntry}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PaRAMEntry +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 paRAMEntry, unsigned int newPaRAMEntryVal) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Set a particular PaRAM set entry of the specified PaRAM set. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_getPaRAMEntry}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PaRAMEntry +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 paRAMEntry, unsigned int *paRAMEntryVal) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Get a particular PaRAM set entry of the specified PaRAM set. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_ +DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setPaRAMField}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PaRAMField}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 paRAMField, unsigned int newPaRAMFieldVal) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Set a particular PaRAM set field of the specified PaRAM set. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_getPaRAMField}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_PaRAMField +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 paRAMField, unsigned int *currPaRAMFieldVal) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Get a particular PaRAM set field of the specified PaRAM set. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setEvtQPriority}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_EvtQuePriority}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 *evtQPriObj) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Sets EDMA TC priority. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_mapChToEvtQ}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int channelId, EDMA3_RM_EventQueue eventQ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Associate Channel to Event Queue. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_getMapChToEvtQ}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int channelId, unsigned int *mappedEvtQ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Get the Event Queue mapped to the specified DMA/QDMA channel. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setCCRegister}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int regOffset, unsigned int newRegValue) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Set the Channel Controller (CC) Register value. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_getCCRegister}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int regOffset, unsigned int *regValue) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Get the Channel Controller (CC) Register value. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_waitAndClearTcc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int tccNo) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Wait for a transfer completion interrupt to occur and clear it. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_checkAndClearTcc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int tccNo, unsigned short *tccStatus) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Returns the status of a previously initiated transfer. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_getPaRAMPhyAddr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int *paramPhyAddr) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Get the PaRAM Set Physical Address associated with a logical channel. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_Ioctl}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_IoctlCmd}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 cmd, void *cmdArg, void *param) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 EDMA3 Driver IOCTL. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Handle }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_getInstHandle}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (unsigned int phyCtrllerInstId, EDMA3_RM_RegionId regionId, EDMA3_DRV_Result *errorCode) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Return the previously opened EDMA3 Driver Instance handle. +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Variables +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +const unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_MAX_RM_INSTANCES}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_RM_Obj }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 resMgrObj}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 [EDMA3_MAX_EDMA3_INSTANCES] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 EDMA3 Resource Manager Objects, tied to each EDMA3 HW Controller. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_RM_InstanceInitConfig * }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 ptrInitCfgArray}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Region Specific Configuration structure for EDMA3 controller, to provide region specific Information. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_RM_Instance * }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 ptrRMIArray}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_Object}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 drvObj}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [EDMA3_MAX_EDMA3_INSTANCES] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 EDMA3 Driver Objects, tied to each EDMA3 HW Controller. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 +EDMA3_DRV_Instance}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 drvInstance}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ChBoundResources}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid6424133 edma3DrvChBoundRes}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_LOGICAL_CH] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Resources bound to a Channel. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 EDMA3 Driver Advanced + Interface Implementation This file contains advanced-level EDMA3 Driver APIs which are required to: a) Link and chain two channels. b) Set/get the whole PaRAM Set in one shot. c) Set/get each individual field of the PaRAM Set. d) Poll mode APIs. e) IOCTL + interface. These APIs are provided to have complete control on the EDMA3 hardware and normally advanced users are expected to use them for their specific use-cases. +\par +\par }\pard\plain \ltrpar\s5\qj \li0\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Author: +\par }\pard\plain \ltrpar\s43\ql \li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 : PSP Team, TII +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Function Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 edma3MemCpy\:edma3_drv_adv.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 edma3_drv_adv.c\:edma3MemCpy}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +void edma3MemCpy (void * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 dst}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , const void * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 src}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +, unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 len}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAAD}{\*\bkmkend AAAAAAAAAD}Local MemCpy function +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_create(), EDMA3_DRV_getPaRAM(), EDMA3_DRV_open(), EDMA3_DRV_setPaRAM(), and edma3OpenResMgr(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 edma3MemSet\:edma3_drv_adv.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 edma3_drv_adv.c\:edma3MemSet}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 void edma3MemSet (void * }{ +\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 dst}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned char }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 data}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 +\ai\af1 \ltrch\fcs0 \i\insrsid6424133 len}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAAE}{\*\bkmkend AAAAAAAAAE}Local MemSet function +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_close(), EDMA3_DRV_create(), and EDMA3_DRV_delete(). +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Variable Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 drvInstance\:edma3_drv_adv.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 edma3_drv_adv.c\:drvInstance}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Instance drvInstance[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAAF}{\*\bkmkend AAAAAAAAAF}Handles of EDMA3 Driver Instances. +\par Used to maintain information of the EDMA3 Driver Instances for each region, for each HW controller. There could be as many Driver Instances as there are shadow regions. Multiple EDMA3 Driver instances on the same shadow region are NOT allowed. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 drvObj\:edma3_drv_adv.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 edma3_drv_adv.c\:drvObj}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Object drvObj[EDMA3_MAX_EDMA3_INSTANCES] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAAG}{\*\bkmkend AAAAAAAAAG}EDMA3 Driver Objects, tied to each EDMA3 HW Controller. +\par Typically one object will cater to one EDMA3 HW controller and will have all regions' (ARM, DSP etc) specific config information. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_MAX_RM_INSTANCES\:edma3_drv_adv.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 edma3_drv_adv.c\:EDMA3_MAX_RM_INSTANCES}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +const unsigned int EDMA3_MAX_RM_INSTANCES +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAAH}{\*\bkmkend AAAAAAAAAH}Maximum Resource Manager Instances supported by the EDMA3 Package. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by edma3OpenResMgr(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 edma3DrvChBoundRes\:edma3_drv_adv.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 edma3_drv_adv.c\:edma3DrvChBoundRes}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_ChBoundResources edma3DrvChBoundRes[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_LOGICAL_CH] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAAI}{\*\bkmkend AAAAAAAAAI}Resources bound to a Channel. +\par When a request for a channel is made, the resources PaRAM Set and TCC get bound to that channel. This information is needed internally by the driver when a request is made to free the channel +(Since it is the responsibility of the driver to free up the channel-associated resources from the Resource Manager layer). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ptrInitCfgArray\:edma3_drv_adv.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 edma3_drv_adv.c\:ptrInitCfgArray}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_RM_InstanceInitConfig* ptrInitCfgArray +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAAJ}{\*\bkmkend AAAAAAAAAJ}Region Specific Configuration structure for EDMA3 controller, to provide region specific Information. +\par This configuration info can also be provided by the user at run-time, while calling EDMA3_RM_open (). If not provided at run-time, this info will be taken from the config file "edma3__cfg.c", for the specified platform. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by edma3OpenResMgr(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ptrRMIArray\:edma3_drv_adv.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 edma3_drv_adv.c\:ptrRMIArray}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_RM_Instance* ptrRMIArray +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAAK}{\*\bkmkend AAAAAAAAAK}Handles of EDMA3 Resource Manager Instances. +\par Used to maintain information of the EDMA3 RM Instances for each HW controller. There could be a maximum of EDMA3_MAX_RM_INSTANCES instances per EDMA3 HW. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by edma3OpenResMgr(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 resMgrObj\:edma3_drv_adv.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 edma3_drv_adv.c\:resMgrObj}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_RM_Obj resMgrObj[EDMA3_MAX_EDMA3_INSTANCES] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAAL}{\*\bkmkend AAAAAAAAAL}EDMA3 Resource Manager Objects, tied to each EDMA3 HW Controller. +\par Typically one RM object will cater to one EDMA3 HW controller and will have all the global config information. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 Referenced by EDMA3_DRV_create(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 +\ltrch\fcs0 \fs24\insrsid6424133 \sect }\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 +\rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 edma3_drv_basic.c File Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc { +\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 \tcl2{\*\bkmkstart _Toc211937276}edma3_drv_basic.c{\*\bkmkend _Toc211937276}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn +\pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 edma3_drv_basic.c}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAAM}{\*\bkmkend AAAAAAAAAM} +EDMA3 Driver Basic Interface Implementation This file contains beginner-level EDMA3 Driver APIs which are required to: a) Request/free a DMA, QDMA and Link channel. b) Program various fields in the PaRAM Set like source/destination parameters, transfer + parameters etc. c) Enable/disable a transfer. These APIs are provided to program a DMA/QDMA channel for simple use-cases and don't expose all the features of EDMA3 hardware. Users who want to go beyond this and have complete control on the EDMA3 hardware + are advised to refer }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 edma3_drv_adv.c}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 source file. +\par }\pard\plain \ltrpar\s18\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af2 +\ltrch\fcs0 \f2\insrsid6424133 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid6424133 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid6424133 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Functions +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 void }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 edma3MemSet}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (void *dst, unsigned char data, unsigned int len) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 void }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 edma3MemCpy}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 (void *dst, const void *src, unsigned int len) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 static EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 edma3RemoveMapping}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int channelId) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_requestChannel}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int *pLCh, unsigned int *pTcc, EDMA3_RM_EventQueue evtQueue, EDMA3_RM_TccCallback tccCb, void *cbData) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Request a DMA/QDMA/Link channel. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_freeChannel}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int channelId) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Free the specified channel (DMA/QDMA/Link) and its associated resources (PaRAM Set, TCC etc) and removes various mappings. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_clearErrorBits}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int channelId) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Clears Event Register and Error Register for a specific DMA channel and brings back EDMA3 to its initial state. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_ +DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setOptField}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OptField}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 optField, unsigned int newOptFieldVal) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Set a particular OPT field in the PaRAM set associated with the logical channel 'lCh'. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_getOptField}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_OptField}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 optField, unsigned int *optFieldVal) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Get a particular OPT field in the PaRAM set associated with the logical channel 'lCh'. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setSrcParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int srcAddr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 EDMA3_DRV_AddrMode}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 addrMode, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_FifoWidth}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 fifoWidth) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 DMA source parameters setup. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setDestParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int destAddr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 EDMA3_DRV_AddrMode}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 addrMode, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_FifoWidth}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 fifoWidth) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 DMA Destination parameters setup. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setSrcIndex}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, int srcBIdx, int srcCIdx) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 DMA source index setup. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setDestIndex}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, int destBIdx, int destCIdx) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 DMA destination index setup. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_setTransferParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int aCnt, unsigned int bCnt, unsign +ed int cCnt, unsigned int bCntReload, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_SyncType}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 syncType) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 DMA transfer parameters setup. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_enableTransfer}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TrigMode} +{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 trigMode) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Start EDMA transfer on the specified channel. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_disableTransfer}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, unsigned int lCh, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_TrigMode +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 trigMode) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Disable DMA transfer on the specified channel. +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Variables +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +const unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_MAX_RM_INSTANCES}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_RM_Obj }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 resMgrObj}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 [EDMA3_MAX_EDMA3_INSTANCES] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 EDMA3 Resource Manager Objects, tied to each EDMA3 HW Controller. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_RM_InstanceInitConfig * }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 ptrInitCfgArray}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Region Specific Configuration structure for EDMA3 controller, to provide region specific Information. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_RM_Instance * }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 ptrRMIArray}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_Object}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 drvObj}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [EDMA3_MAX_EDMA3_INSTANCES] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 EDMA3 Driver Objects, tied to each EDMA3 HW Controller. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 +EDMA3_DRV_Instance}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 drvInstance}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ChBoundResources}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid6424133 edma3DrvChBoundRes}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_LOGICAL_CH] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Resources bound to a Channel. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 EDMA3 Driver Basic Interface Implementation This file contains beginner-level EDMA3 Driver APIs which are required to: a) Request/free a DMA, QDMA and Link channel. b) Pr +ogram various fields in the PaRAM Set like source/destination parameters, transfer parameters etc. c) Enable/disable a transfer. These APIs are provided to program a DMA/QDMA channel for simple use-cases and don't expose all the features of EDMA3 hardware +. Users who want to go beyond this and have complete control on the EDMA3 hardware are advised to refer }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 edma3_drv_adv.c}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 source file. +\par +\par }\pard\plain \ltrpar\s5\qj \li0\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Author: +\par }\pard\plain \ltrpar\s43\ql \li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 : PSP Team, TII +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Function Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 edma3MemCpy\:edma3_drv_basic.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 edma3_drv_basic.c\:edma3MemCpy}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +void edma3MemCpy (void * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 dst}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , const void * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 src}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +, unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 len}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAAN}{\*\bkmkend AAAAAAAAAN}Local MemCpy function +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 edma3MemSet\:edma3_drv_basic.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 edma3_drv_basic.c\:edma3MemSet}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 void edma3MemSet (void * } +{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 dst}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned char }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 data}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 +\ai\af1 \ltrch\fcs0 \i\insrsid6424133 len}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAAO}{\*\bkmkend AAAAAAAAAO}Local MemSet function +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 edma3RemoveMapping\:edma3_drv_basic.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 edma3_drv_basic.c\:edma3RemoveMapping}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +static EDMA3_DRV_Result edma3RemoveMapping (EDMA3_DRV_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 hEdma}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 channelId}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 )}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid6424133 [static]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAAP}{\*\bkmkend AAAAAAAAAP}Remove various mappings and do cleanup for DMA/QDMA channels +\par Disable any ongoing transfer on the channel, if transfer was enabled earlier. +\par If DMA channel to PaRAM Set mapping exists, remove it too. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 References EDMA3_DRV_GblConfigParams::dmaChPaRAMMapExists, +EDMA3_DRV_disableTransfer(), EDMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_DMAQNUM_CLR_MASK, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_QDMAQNUM_CLR_MASK, EDMA3_DRV_TRIG_MODE_NONE, EDMA3_DRV_Object::gblCfgParams, EDMA3 +_DRV_GblConfigParams::globalRegs, EDMA3_DRV_Instance::pDrvObjectHandle, EDMA3_DRV_Object::phyCtrllerInstId, EDMA3_DRV_Instance::resMgrInstance, and EDMA3_DRV_ChBoundResources::trigMode. +\par Referenced by EDMA3_DRV_freeChannel(). +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Variable Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 drvInstance\:edma3_drv_basic.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 edma3_drv_basic.c\:drvInstance}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Instance drvInstance[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAAQ}{\*\bkmkend AAAAAAAAAQ}Handles of EDMA3 Driver Instances. +\par Used to maintain information of the EDMA3 Driver Instances for each region, for each HW controller. There could be as many Driver Instances as there are shadow regions. Multiple EDMA3 Driver instances on the same shadow region are NOT allowed. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 drvObj\:edma3_drv_basic.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 edma3_drv_basic.c\:drvObj}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV +_Object drvObj[EDMA3_MAX_EDMA3_INSTANCES] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAAR}{\*\bkmkend AAAAAAAAAR}EDMA3 Driver Objects, tied to each EDMA3 HW Controller. +\par Typically one object will cater to one EDMA3 HW controller and will have all regions' (ARM, DSP etc) specific config information. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_MAX_RM_INSTANCES\:edma3_drv_basic.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 edma3_drv_basic.c\:EDMA3_MAX_RM_INSTANCES}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +const unsigned int EDMA3_MAX_RM_INSTANCES +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAAS}{\*\bkmkend AAAAAAAAAS}Define NDEBUG to ignore assert(). NDEBUG should be defined before including assert.h header file. Maximum +Resource Manager Instances supported by the EDMA3 Package. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 edma3DrvChBoundRes\:edma3_drv_basic.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 edma3_drv_basic.c\:edma3DrvChBoundRes}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_ChBoundResources edma3DrvChBoundRes[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_LOGICAL_CH] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAAT}{\*\bkmkend AAAAAAAAAT}Resources bound to a Channel. +\par When a request for a channel is made, the resources PaRAM Set and TCC get bound to that channel. This information is needed internally by the driver when a request is made to free the channel (Since it is the respon +sibility of the driver to free up the channel-associated resources from the Resource Manager layer). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ptrInitCfgArray\:edma3_drv_basic.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 edma3_drv_basic.c\:ptrInitCfgArray}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_RM_InstanceInitConfig* ptrInitCfgArray +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAAU}{\*\bkmkend AAAAAAAAAU}Region Specific Configuration structure for EDMA3 controller, to provide region specific Information. +\par This configuration info can also be provided by the user at run-time, while calling EDMA3_RM_open (). If not provided at run-time, this info will be taken from the config file "edma3__cfg.c", for the specified platform. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ptrRMIArray\:edma3_drv_basic.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 edma3_drv_basic.c\:ptrRMIArray}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_RM_Instance* ptrRMIArray +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAAV}{\*\bkmkend AAAAAAAAAV}Handles of EDMA3 Resource Manager Instances. +\par Used to maintain information of the EDMA3 RM Instances for each HW controller. There could be a maximum of EDMA3_MAX_RM_INSTANCES instances per EDMA3 HW. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 resMgrObj\:edma3_drv_basic.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 edma3_drv_basic.c\:resMgrObj}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_RM_Obj resMgrObj[EDMA3_MAX_EDMA3_INSTANCES] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAAW}{\*\bkmkend AAAAAAAAAW}EDMA3 Resource Manager Objects, tied to each EDMA3 HW Controller. +\par Typically one RM object will cater to one EDMA3 HW controller and will have all the global config information. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 +\ltrch\fcs0 \fs24\insrsid6424133 \sect }\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 +\rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 edma3_drv_init.c File Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc { +\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 \tcl2{\*\bkmkstart _Toc211937277}edma3_drv_init.c{\*\bkmkend _Toc211937277}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn +\pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 edma3_drv_init.c}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 {\*\bkmkstart AAAAAAAAAX}{\*\bkmkend AAAAAAAAAX} +EDMA3 Driver Initialization Interface Implementation This file contains EDMA3 Driver APIs used to: a) Create/delete EDMA3 Driver Object b) Open/close EDMA3 Driver Instance. These APIs are required to initialize EDMA3 properly. +\par }\pard\plain \ltrpar\s18\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af2 +\ltrch\fcs0 \f2\insrsid6424133 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid6424133 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid6424133 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Functions +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 void }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 edma3MemSet}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (void *dst, unsigned char data, unsigned int len) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 void }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 edma3MemCpy}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 (void *dst, const void *src, unsigned int len) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 static EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 edma3OpenResMgr}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (unsigned int instId, unsigned int regionId, unsigned short flag) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_create}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid6424133 (unsigned int phyCtrllerInstId, const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_GblConfigParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 *gblCfgParams, const void *miscParam) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Create EDMA3 Driver Object. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_delete}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (unsigned int phyCtrllerInstId, const void *param) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Delete EDMA3 Driver Object. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Handle }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_open}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (unsigned int phyCtrllerInstId, const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_InitConfig}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid6424133 *initCfg, EDMA3_DRV_Result *errorCode) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Open EDMA3 Driver Instance. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Result }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_close}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 (EDMA3_DRV_Handle hEdma, const void *param) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Close the EDMA3 Driver Instance. +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Variables +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +const unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_MAX_RM_INSTANCES}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 EDMA3_RM_Obj }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 resMgrObj}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid6424133 [EDMA3_MAX_EDMA3_INSTANCES] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 EDMA3 Resource Manager Objects, tied to each EDMA3 HW Controller. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_RM_InstanceInitConfig * }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 ptrInitCfgArray}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 Region Specific Configuration structure for EDMA3 controller, to provide region specific Information. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3_RM_Instance * }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 ptrRMIArray}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_Object}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid6424133 drvObj}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [EDMA3_MAX_EDMA3_INSTANCES] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid6424133 EDMA3 Driver Objects, tied to each EDMA3 HW Controller. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 +EDMA3_DRV_Instance}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 drvInstance}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid6424133 EDMA3_DRV_ChBoundResources}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid6424133 edma3DrvChBoundRes}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_LOGICAL_CH] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 +\i\insrsid6424133 Resources bound to a Channel. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +EDMA3 Driver Initialization Interface Implementation This file contains EDMA3 Driver APIs used to: a) Create/delete EDMA3 Driver Object b) Open/close EDMA3 Driver Instance. These APIs are required to initialize EDMA3 properly. +\par +\par }\pard\plain \ltrpar\s5\qj \li0\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Author: +\par }\pard\plain \ltrpar\s43\ql \li360\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +: PSP Team, TII +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Function Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 +\ltrch\fcs0 \fs24\insrsid6424133 edma3MemCpy\:edma3_drv_init.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 edma3_drv_init.c\:edma3MemCpy}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 void edma3MemCpy (void * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 dst}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , const void * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 src}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 len}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAAY}{\*\bkmkend AAAAAAAAAY}Local MemCpy function +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 edma3MemSet\:edma3_drv_init.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 edma3_drv_init.c\:edma3MemSet}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +void edma3MemSet (void * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 dst}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned char }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 data}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +, unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 len}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAAAZ}{\*\bkmkend AAAAAAAAAZ}Local MemSet function +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 edma3OpenResMgr\:edma3_drv_init.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 edma3_drv_init.c\:edma3OpenResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +static EDMA3_DRV_Result edma3OpenResMgr (unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 instId}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 regionId}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 , unsigned short }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid6424133 flag}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 )}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid6424133 [static]}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAABA}{\*\bkmkend AAAAAAAABA}Local function to prepare the init config structure for open of Resource Manager +\par User has passed the instance initialization specific info, which we have saved previously too, so use it. +\par User has NOT passed the instance initialization specific info. Pass NULL to the Resource Manager. +\par Save the RM Instance specific information in the driver. Earlier this was easier, now a bit tricky. Search for the RM instance number based on the handle just returned, to fetch the correct config info from the userInitConfig[]. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +References EDMA3_DRV_Instance::drvSemHandle, EDMA3_DRV_ +E_INVALID_PARAM, EDMA3_MAX_RM_INSTANCES, edma3MemCpy(), EDMA3_DRV_Instance::gblerrCbParams, EDMA3_DRV_Instance::isMaster, EDMA3_DRV_Instance::pDrvObjectHandle, ptrInitCfgArray, ptrRMIArray, and EDMA3_DRV_Instance::resMgrInstance. +\par Referenced by EDMA3_DRV_open(). +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 +\b\f1\insrsid6424133 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 Variable Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 +\ltrch\fcs0 \fs24\insrsid6424133 drvInstance\:edma3_drv_init.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid6424133 edma3_drv_init.c\:drvInstance}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid6424133 EDMA3_DRV_Instance drvInstance[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAABB}{\*\bkmkend AAAAAAAABB}Handles of EDMA3 Driver Instances. +\par Used to maintain information of the EDMA3 Driver Instances for each region, for each HW controller. There could be as many Driver Instances as there are shadow regions. Multiple EDMA3 Driver instances on the same shadow region are NOT allowed. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 drvObj\:edma3_drv_init.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 edma3_drv_init.c\:drvObj}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_DRV_Object drvObj[EDMA3_MAX_EDMA3_INSTANCES] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAABC}{\*\bkmkend AAAAAAAABC}EDMA3 Driver Objects, tied to each EDMA3 HW Controller. +\par Typically one object will cater to one EDMA3 HW controller and will have all regions' (ARM, DSP etc) specific config information. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 EDMA3_MAX_RM_INSTANCES\:edma3_drv_init.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 edma3_drv_init.c\:EDMA3_MAX_RM_INSTANCES}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +const unsigned int EDMA3_MAX_RM_INSTANCES +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAABD}{\*\bkmkend AAAAAAAABD}Define NDEBUG to ignore assert(). NDEBUG should be defined before including assert.h header file. Maximum Resource Manager Instances supported by the EDMA3 Package. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 edma3DrvChBoundRes\:edma3_drv_init.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 edma3_drv_init.c\:edma3DrvChBoundRes}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 EDMA3_ +DRV_ChBoundResources edma3DrvChBoundRes[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_LOGICAL_CH] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAABE}{\*\bkmkend AAAAAAAABE}Resources bound to a Channel. +\par When a request for a channel is made, the resources PaRAM Set and TCC get bound to that channel. This information is + needed internally by the driver when a request is made to free the channel (Since it is the responsibility of the driver to free up the channel-associated resources from the Resource Manager layer). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 ptrInitCfgArray\:edma3_drv_init.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 edma3_drv_init.c\:ptrInitCfgArray}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_RM_InstanceInitConfig* ptrInitCfgArray +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAABF}{\*\bkmkend AAAAAAAABF}Region Specific Configuration structure for EDMA3 controller, to provide region specific Information. +\par This configuration info can also be provided by the user at run-time, while calling EDMA3_RM_open (). If not provided at run-time, this info will be taken from the config file "edma3__cfg.c", for the specified platform. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 ptrRMIArray\:edma3_drv_init.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 edma3_drv_init.c\:ptrRMIArray}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_RM_Instance* ptrRMIArray +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAABG}{\*\bkmkend AAAAAAAABG}Handles of EDMA3 Resource Manager Instances. +\par Used to maintain information of the EDMA3 RM Instances for each HW controller. There could be a maximum of EDMA3_MAX_RM_INSTANCES instances per EDMA3 HW. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid6424133 resMgrObj\:edma3_drv_init.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 edma3_drv_init.c\:resMgrObj}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 +EDMA3_RM_Obj resMgrObj[EDMA3_MAX_EDMA3_INSTANCES] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid6424133 +{\*\bkmkstart AAAAAAAABH}{\*\bkmkend AAAAAAAABH}EDMA3 Resource Manager Objects, tied to each EDMA3 HW Controller. +\par Typically one RM object will cater to one EDMA3 HW controller and will have all the global config information. +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 \sect +}\sectd \ltrsect\linex0\sectdefaultcl\sectrsid6424133\sftnbj \pard\plain \ltrpar\s1\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs36\alang1025 \ltrch\fcs0 +\b\f1\fs36\lang1033\langfe1033\kerning36\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid6424133 Index +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 {\*\bkmkstart _Toc211937278} +Index{\*\bkmkend _Toc211937278}}}}\sectd \linex0\sectdefaultcl\sectrsid6424133\sftnbj {\field{\*\fldinst {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid6424133 INDEX \\c2 \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 +\par }{\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\lang1024\langfe1024\noproof\insrsid6424133 \sect }\sectd \ltrsect\sbknone\linex0\cols2\sectdefaultcl\sectrsid6424133\sftnbj \pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar +\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid6424133 A_B_CNT + +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_ParamentryRegs, 82 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Boundary Values, 61 +\par ccError +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_GblConfigParams, 70 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 dmaChannelHwEvtMap +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_GblConfigParams, 71 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 dmaChannelPaRAMMap +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_GblConfigParams, 71 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 dmaChannelTccMap +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_GblConfigParams, 71 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 dmaChPaRAMMapExists +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_GblConfigParams, 69 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 drvInstance +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 edma3_drv_adv.c, 98 +\par edma3_drv_basic.c, 102 +\par edma3_drv_init.c, 105 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 drvInstInitConfig +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_InitConfig, 72 +\par EDMA3_DRV_Instance, 74 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 drvObj +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 edma3_drv_adv.c, 98 +\par edma3_drv_basic.c, 102 +\par edma3_drv_init.c, 105 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 drvSemHandle +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_InitConfig, 72 +\par EDMA3_DRV_Instance, 74 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3 Driver Channel Setup, 17 +\par EDMA3 Driver Error Codes, 9 +\par EDMA3 Driver Interface Definition, 5 +\par EDMA3 Driver Optional Setup for EDMA, 41 +\par EDMA3 Driver Typical EDMA Transfer Setup, 27 +\par EDMA3 Driver Usage Guidelines, 9 +\par edma3.h, 86 +\par edma3_drv.h, 89 +\par EDMA3_DRV_ACNT_MAX_VAL +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 55 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_ADDR_MODE_FIFO +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_ADDR_MODE_INCR +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_AddrMode +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 edma3_drv_adv.c, 96 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 drvInstance, 98 +\par drvObj, 98 +\par EDMA3_MAX_RM_INSTANCES, 98 +\par edma3DrvChBoundRes, 98 +\par edma3MemCpy, 98 +\par edma3MemSet, 98 +\par ptrInitCfgArray, 99 +\par ptrRMIArray, 99 +\par resMgrObj, 99 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 edma3_drv_basic.c, 100 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 drvInstance, 102 +\par drvObj, 102 +\par EDMA3_MAX_RM_INSTANCES, 102 +\par edma3DrvChBoundRes, 102 +\par edma3MemCpy, 102 +\par edma3MemSet, 102 +\par edma3RemoveMapping, 102 +\par ptrInitCfgArray, 103 +\par ptrRMIArray, 103 +\par resMgrObj, 103 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_BCNT_MAX_VAL +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 55 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_BCNTRELD_MAX_VAL +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 55 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_CCNT_MAX_VAL +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 55 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_CH_NO_PARAM_MAP +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvMain, 6 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_CH_NO_TCC_MAP +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvMain, 6 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_chainChannel +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 33 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_ChainOptions, 64 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 itcchEn, 64 +\par itcintEn, 64 +\par tcchEn, 64 +\par tcintEn, 64 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_CHANNEL_TYPE_DMA +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 61 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_CHANNEL_TYPE_LINK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 61 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_CHANNEL_TYPE_NONE +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 61 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_CHANNEL_TYPE_QDMA +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 61 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_ChannelType +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 61 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_ChBoundResources, 65 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 paRAMId, 65 +\par tcc, 65 +\par trigMode, 65 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_checkAndClearTcc +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 45 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_clearErrorBits +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 23 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_close +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvMain, 6 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_CLOSED +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvIntObjMaint, 63 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_create +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvMain, 7 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_CREATED +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvIntObjMaint, 63 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_delete +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvMain, 7 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_DELETED +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvIntObjMaint, 63 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_disableTransfer +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 34 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_DMA_CH_MAX_VAL +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvIntBoundVals, 61 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_DMA_CHANNEL_ANY +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 19 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_DMAQNUM_CLR_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 55 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_DMAQNUM_SET_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 55 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_DSTBIDX_MAX_VAL +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 55 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_DSTBIDX_MIN_VAL +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 56 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_DSTCIDX_MAX_VAL +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 56 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_DSTCIDX_MIN_VAL +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 56 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_E_ADDRESS_NOT_ALIGNED +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvErrorCode, 15 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_E_BASE +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvErrorCode, 16 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_E_CH_PARAM_BIND_FAIL +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvErrorCode, 16 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvErrorCode, 16 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvErrorCode, 16 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_E_INST_ALREADY_EXISTS +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvErrorCode, 16 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_E_INST_NOT_OPENED +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvErrorCode, 16 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_E_INVALID_PARAM +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvErrorCode, 16 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_E_INVALID_STATE +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvErrorCode, 16 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_E_OBJ_NOT_CLOSED +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvErrorCode, 17 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_E_OBJ_NOT_DELETED +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvErrorCode, 17 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_E_OBJ_NOT_OPENED +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvErrorCode, 17 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_E_PARAM_SET_UNAVAIL +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvErrorCode, 17 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvErrorCode, 17 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_E_RM_CLOSE_FAIL +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvErrorCode, 17 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_E_SEMAPHORE +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvErrorCode, 17 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_E_TCC_REGISTER_FAIL +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvErrorCode, 17 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_E_TCC_UNAVAIL +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvErrorCode, 17 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_enableTransfer +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 34 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_EvtQuePriority, 67 +\par EDMA3_DRV_FifoWidth +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_freeChannel +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 23 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_GblConfigParams, 68 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 ccError, 70 +\par dmaChannelHwEvtMap, 71 +\par dmaChannelPaRAMMap, 71 +\par dmaChannelTccMap, 71 +\par dmaChPaRAMMapExists, 69 +\par evtQPri, 70 +\par evtQueueWaterMarkLvl, 70 +\par globalRegs, 70 +\par memProtectionExists, 70 +\par numDmaChannels, 69 +\par numEvtQueue, 69 +\par numPaRAMSets, 69 +\par numQdmaChannels, 69 +\par numRegions, 69 +\par numTccs, 69 +\par numTcs, 69 +\par tcDefaultBurstSize, 71 +\par tcError, 70 +\par tcRegs, 70 +\par xferCompleteInt, 70 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_getCCRegister +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 45 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_getInstHandle +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 45 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_getMapChToEvtQ +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 46 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_getOptField +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 35 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_getPaRAM +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 46 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_getPaRAMEntry +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 47 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_getPaRAMField +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 47 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_getPaRAMPhyAddr +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 48 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 20 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_0 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 21 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_1 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 21 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_10 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 21 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_11 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 21 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_12 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 21 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_13 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 21 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_14 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 21 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_15 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 21 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_16 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 21 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_17 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 21 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_18 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 21 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_19 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 21 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_2 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 21 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_20 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 21 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_21 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 21 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_22 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 21 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_23 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 21 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_24 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 21 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_25 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 21 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_26 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 21 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_27 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 21 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_28 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 21 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_29 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 21 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_3 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 21 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_30 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 21 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_31 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_32 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_33 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_34 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_35 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_36 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_37 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_38 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_39 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_4 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 21 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_40 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_41 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_42 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_43 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_44 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_45 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_46 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_47 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_48 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_49 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_5 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 21 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_50 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_51 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_52 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_53 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_54 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_55 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_56 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_57 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_58 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_59 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_6 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 21 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_60 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_61 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_62 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_63 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_7 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 21 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_8 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 21 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_HW_CHANNEL_EVENT_9 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 21 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 edma3_drv_init.c, 104 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 drvInstance, 105 +\par drvObj, 105 +\par EDMA3_MAX_RM_INSTANCES, 105 +\par edma3DrvChBoundRes, 106 +\par edma3MemCpy, 105 +\par edma3MemSet, 105 +\par edma3OpenResMgr, 105 +\par ptrInitCfgArray, 106 +\par ptrRMIArray, 106 +\par resMgrObj, 106 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_InitConfig, 72 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 drvInstInitConfig, 72 +\par drvSemHandle, 72 +\par gblerrCb, 73 +\par gblerrData, 73 +\par isMaster, 72 +\par regionId, 72 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_Instance, 74 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 drvInstInitConfig, 74 +\par drvSemHandle, 74 +\par gblerrCbParams, 75 +\par isMaster, 74 +\par pDrvObjectHandle, 75 +\par regionId, 74 +\par resMgrInstance, 75 +\par shadowRegs, 75 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_InstanceInitConfig, 76 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 ownDmaChannels, 77 +\par ownPaRAMSets, 77 +\par ownQdmaChannels, 77 +\par ownTccs, 77 +\par resvdDmaChannels, 77 +\par resvdPaRAMSets, 77 +\par resvdQdmaChannels, 78 +\par resvdTccs, 78 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_Ioctl +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 48 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 43 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 43 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_IoctlCmd +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 43 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_ItcchEn +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_ITCCHEN_DIS +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_ITCCHEN_EN +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_ItcintEn +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_ITCINTEN_DIS +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_ITCINTEN_EN +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_LINK_CH_MAX_VAL +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvIntBoundVals, 61 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_LINK_CH_MIN_VAL +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvIntBoundVals, 62 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_LINK_CHANNEL +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 19 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_linkChannel +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 24 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_LOG_CH_MAX_VAL +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvIntBoundVals, 62 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_mapChToEvtQ +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 49 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_MiscParam, 79 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 isSlave, 79 +\par param, 79 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_Object, 80 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 gblCfgParams, 81 +\par numOpens, 80 +\par phyCtrllerInstId, 80 +\par state, 80 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_ObjState +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvIntObjMaint, 63 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_open +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvMain, 8 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPENED +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvIntObjMaint, 63 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_DAM_CLR_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 56 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_DAM_GET_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 56 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_DAM_SET_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 56 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_FIELD_DAM +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_FIELD_FWID +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_FIELD_ITCCHEN +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 31 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_FIELD_ITCINTEN +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 31 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_FIELD_SAM +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_FIELD_STATIC +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_FIELD_SYNCDIM +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_FIELD_TCC +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 31 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_FIELD_TCCHEN +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 31 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_FIELD_TCCMODE +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 31 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_FIELD_TCINTEN +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 31 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_FWID_CLR_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 56 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_FWID_GET_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 56 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_FWID_SET_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 56 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_ITCCHEN_CLR_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 56 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_ITCCHEN_GET_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 57 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_ITCCHEN_SET_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 57 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_ITCINTEN_CLR_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 57 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_ITCINTEN_GET_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 57 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_ITCINTEN_SET_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 57 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_SAM_CLR_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 57 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_SAM_GET_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 57 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_SAM_SET_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 57 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_STATIC_CLR_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 57 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_STATIC_GET_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 58 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_STATIC_SET_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 58 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_SYNCDIM_CLR_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 58 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_SYNCDIM_GET_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 58 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_SYNCDIM_SET_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 58 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_TCC_CLR_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 58 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_TCC_GET_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 58 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_TCC_SET_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 58 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_TCCHEN_CLR_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 58 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_TCCHEN_GET_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 59 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_TCCHEN_SET_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 59 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_TCCMODE_CLR_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 59 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_TCCMODE_GET_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 59 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_TCCMODE_SET_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 59 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_TCINTEN_CLR_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 59 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_TCINTEN_GET_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 59 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OPT_TCINTEN_SET_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 59 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_OptField +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 44 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_PARAM_ENTRY_CCNT +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 44 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_PARAM_ENTRY_DST +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 44 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 44 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_PARAM_ENTRY_OPT +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 43 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_PARAM_ENTRY_SRC +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 43 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 44 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 44 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_PARAM_FIELD_ACNT +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 44 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_PARAM_FIELD_BCNT +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 44 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_PARAM_FIELD_BCNTRELOAD +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 44 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_PARAM_FIELD_CCNT +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 44 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_PARAM_FIELD_DESTADDR +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 44 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_PARAM_FIELD_DESTBIDX +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 44 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_PARAM_FIELD_DESTCIDX +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 44 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_PARAM_FIELD_LINKADDR +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 44 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_PARAM_FIELD_OPT +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 44 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_PARAM_FIELD_SRCADDR +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 44 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_PARAM_FIELD_SRCBIDX +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 44 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_PARAM_FIELD_SRCCIDX +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 44 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_PaRAMEntry +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 43 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_ParamentryRegs, 82 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 A_B_CNT, 82 +\par LINK_BCNTRLD, 83 +\par OPT, 82 +\par SRC_DST_BIDX, 82 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_PaRAMField +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 44 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_PaRAMRegs, 84 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 opt, 85 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_QCH_TRWORD_CLR_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 59 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_QCH_TRWORD_SET_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt, 60 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_QDMA_CH_MAX_VAL +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 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+\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 36 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_setEvtQPriority +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 50 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_setOptField +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 37 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_setPaRAM +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 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+\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_TCC_ANY +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 20 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_TcchEn +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 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+\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_TCCHEN_EN +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 32 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_TccMode +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 32 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_TCCMODE_EARLY +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 32 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_TCCMODE_NORMAL +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 32 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_TcintEn +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 32 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_TCINTEN_DIS +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 32 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_TCINTEN_EN +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 32 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_TRIG_MODE_EVENT +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 33 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_TRIG_MODE_MANUAL +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 33 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_TRIG_MODE_NONE +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 33 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_TRIG_MODE_QDMA +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 33 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_TrigMode +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 32 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_unchainChannel +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 40 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_unlinkChannel +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup, 27 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_W128BIT +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_W16BIT +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_W256BIT +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_W32BIT +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_W64BIT +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_W8BIT +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_waitAndClearTcc +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt, 52 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_MAX_RM_INSTANCES +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 edma3_drv_adv.c, 98 +\par edma3_drv_basic.c, 102 +\par edma3_drv_init.c, 105 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvChannelSetup +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_clearErrorBits, 23 +\par EDMA3_DRV_DMA_CHANNEL_ANY, 19 +\par EDMA3_DRV_freeChannel, 23 +\par EDMA3_DRV_HW_CHANNEL_EVENT, 20 +\par EDMA3_DRV_HW_CHANNEL_EVENT_0, 21 +\par EDMA3_DRV_HW_CHANNEL_EVENT_1, 21 +\par EDMA3_DRV_HW_CHANNEL_EVENT_10, 21 +\par EDMA3_DRV_HW_CHANNEL_EVENT_11, 21 +\par EDMA3_DRV_HW_CHANNEL_EVENT_12, 21 +\par EDMA3_DRV_HW_CHANNEL_EVENT_13, 21 +\par EDMA3_DRV_HW_CHANNEL_EVENT_14, 21 +\par EDMA3_DRV_HW_CHANNEL_EVENT_15, 21 +\par EDMA3_DRV_HW_CHANNEL_EVENT_16, 21 +\par EDMA3_DRV_HW_CHANNEL_EVENT_17, 21 +\par EDMA3_DRV_HW_CHANNEL_EVENT_18, 21 +\par EDMA3_DRV_HW_CHANNEL_EVENT_19, 21 +\par EDMA3_DRV_HW_CHANNEL_EVENT_2, 21 +\par EDMA3_DRV_HW_CHANNEL_EVENT_20, 21 +\par EDMA3_DRV_HW_CHANNEL_EVENT_21, 21 +\par EDMA3_DRV_HW_CHANNEL_EVENT_22, 21 +\par EDMA3_DRV_HW_CHANNEL_EVENT_23, 21 +\par EDMA3_DRV_HW_CHANNEL_EVENT_24, 21 +\par EDMA3_DRV_HW_CHANNEL_EVENT_25, 21 +\par EDMA3_DRV_HW_CHANNEL_EVENT_26, 21 +\par EDMA3_DRV_HW_CHANNEL_EVENT_27, 21 +\par EDMA3_DRV_HW_CHANNEL_EVENT_28, 21 +\par EDMA3_DRV_HW_CHANNEL_EVENT_29, 21 +\par EDMA3_DRV_HW_CHANNEL_EVENT_3, 21 +\par EDMA3_DRV_HW_CHANNEL_EVENT_30, 21 +\par EDMA3_DRV_HW_CHANNEL_EVENT_31, 22 +\par EDMA3_DRV_HW_CHANNEL_EVENT_32, 22 +\par EDMA3_DRV_HW_CHANNEL_EVENT_33, 22 +\par EDMA3_DRV_HW_CHANNEL_EVENT_34, 22 +\par EDMA3_DRV_HW_CHANNEL_EVENT_35, 22 +\par EDMA3_DRV_HW_CHANNEL_EVENT_36, 22 +\par EDMA3_DRV_HW_CHANNEL_EVENT_37, 22 +\par EDMA3_DRV_HW_CHANNEL_EVENT_38, 22 +\par EDMA3_DRV_HW_CHANNEL_EVENT_39, 22 +\par EDMA3_DRV_HW_CHANNEL_EVENT_4, 21 +\par EDMA3_DRV_HW_CHANNEL_EVENT_40, 22 +\par EDMA3_DRV_HW_CHANNEL_EVENT_41, 22 +\par EDMA3_DRV_HW_CHANNEL_EVENT_42, 22 +\par EDMA3_DRV_HW_CHANNEL_EVENT_43, 22 +\par EDMA3_DRV_HW_CHANNEL_EVENT_44, 22 +\par EDMA3_DRV_HW_CHANNEL_EVENT_45, 22 +\par EDMA3_DRV_HW_CHANNEL_EVENT_46, 22 +\par EDMA3_DRV_HW_CHANNEL_EVENT_47, 22 +\par EDMA3_DRV_HW_CHANNEL_EVENT_48, 22 +\par EDMA3_DRV_HW_CHANNEL_EVENT_49, 22 +\par EDMA3_DRV_HW_CHANNEL_EVENT_5, 21 +\par EDMA3_DRV_HW_CHANNEL_EVENT_50, 22 +\par EDMA3_DRV_HW_CHANNEL_EVENT_51, 22 +\par EDMA3_DRV_HW_CHANNEL_EVENT_52, 22 +\par EDMA3_DRV_HW_CHANNEL_EVENT_53, 22 +\par EDMA3_DRV_HW_CHANNEL_EVENT_54, 22 +\par EDMA3_DRV_HW_CHANNEL_EVENT_55, 22 +\par EDMA3_DRV_HW_CHANNEL_EVENT_56, 22 +\par EDMA3_DRV_HW_CHANNEL_EVENT_57, 22 +\par EDMA3_DRV_HW_CHANNEL_EVENT_58, 22 +\par EDMA3_DRV_HW_CHANNEL_EVENT_59, 22 +\par EDMA3_DRV_HW_CHANNEL_EVENT_6, 21 +\par EDMA3_DRV_HW_CHANNEL_EVENT_60, 22 +\par EDMA3_DRV_HW_CHANNEL_EVENT_61, 22 +\par EDMA3_DRV_HW_CHANNEL_EVENT_62, 22 +\par EDMA3_DRV_HW_CHANNEL_EVENT_63, 22 +\par EDMA3_DRV_HW_CHANNEL_EVENT_7, 21 +\par EDMA3_DRV_HW_CHANNEL_EVENT_8, 21 +\par EDMA3_DRV_HW_CHANNEL_EVENT_9, 21 +\par EDMA3_DRV_LINK_CHANNEL, 19 +\par EDMA3_DRV_linkChannel, 24 +\par EDMA3_DRV_QDMA_CHANNEL_0, 19 +\par EDMA3_DRV_QDMA_CHANNEL_1, 20 +\par EDMA3_DRV_QDMA_CHANNEL_2, 20 +\par EDMA3_DRV_QDMA_CHANNEL_3, 20 +\par EDMA3_DRV_QDMA_CHANNEL_4, 20 +\par EDMA3_DRV_QDMA_CHANNEL_5, 20 +\par EDMA3_DRV_QDMA_CHANNEL_6, 20 +\par EDMA3_DRV_QDMA_CHANNEL_7, 20 +\par EDMA3_DRV_QDMA_CHANNEL_ANY, 20 +\par EDMA3_DRV_requestChannel, 24 +\par EDMA3_DRV_TCC_ANY, 20 +\par EDMA3_DRV_unlinkChannel, 27 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 edma3DrvChBoundRes +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 edma3_drv_adv.c, 98 +\par edma3_drv_basic.c, 102 +\par edma3_drv_init.c, 106 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvErrorCode +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_E_ADDRESS_NOT_ALIGNED, 15 +\par EDMA3_DRV_E_BASE, 16 +\par EDMA3_DRV_E_CH_PARAM_BIND_FAIL, 16 +\par EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL, 16 +\par EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED, 16 +\par EDMA3_DRV_E_INST_ALREADY_EXISTS, 16 +\par EDMA3_DRV_E_INST_NOT_OPENED, 16 +\par EDMA3_DRV_E_INVALID_PARAM, 16 +\par EDMA3_DRV_E_INVALID_STATE, 16 +\par EDMA3_DRV_E_OBJ_NOT_CLOSED, 17 +\par EDMA3_DRV_E_OBJ_NOT_DELETED, 17 +\par EDMA3_DRV_E_OBJ_NOT_OPENED, 17 +\par EDMA3_DRV_E_PARAM_SET_UNAVAIL, 17 +\par EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL, 17 +\par EDMA3_DRV_E_RM_CLOSE_FAIL, 17 +\par EDMA3_DRV_E_SEMAPHORE, 17 +\par EDMA3_DRV_E_TCC_REGISTER_FAIL, 17 +\par EDMA3_DRV_E_TCC_UNAVAIL, 17 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvInt +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_ACNT_MAX_VAL, 55 +\par EDMA3_DRV_BCNT_MAX_VAL, 55 +\par EDMA3_DRV_BCNTRELD_MAX_VAL, 55 +\par EDMA3_DRV_CCNT_MAX_VAL, 55 +\par EDMA3_DRV_CHANNEL_TYPE_DMA, 61 +\par EDMA3_DRV_CHANNEL_TYPE_LINK, 61 +\par EDMA3_DRV_CHANNEL_TYPE_NONE, 61 +\par EDMA3_DRV_CHANNEL_TYPE_QDMA, 61 +\par EDMA3_DRV_ChannelType, 61 +\par EDMA3_DRV_DMAQNUM_CLR_MASK, 55 +\par EDMA3_DRV_DMAQNUM_SET_MASK, 55 +\par EDMA3_DRV_DSTBIDX_MAX_VAL, 55 +\par EDMA3_DRV_DSTBIDX_MIN_VAL, 56 +\par EDMA3_DRV_DSTCIDX_MAX_VAL, 56 +\par EDMA3_DRV_DSTCIDX_MIN_VAL, 56 +\par EDMA3_DRV_OPT_DAM_CLR_MASK, 56 +\par EDMA3_DRV_OPT_DAM_GET_MASK, 56 +\par EDMA3_DRV_OPT_DAM_SET_MASK, 56 +\par EDMA3_DRV_OPT_FWID_CLR_MASK, 56 +\par EDMA3_DRV_OPT_FWID_GET_MASK, 56 +\par EDMA3_DRV_OPT_FWID_SET_MASK, 56 +\par EDMA3_DRV_OPT_ITCCHEN_CLR_MASK, 56 +\par EDMA3_DRV_OPT_ITCCHEN_GET_MASK, 57 +\par EDMA3_DRV_OPT_ITCCHEN_SET_MASK, 57 +\par EDMA3_DRV_OPT_ITCINTEN_CLR_MASK, 57 +\par EDMA3_DRV_OPT_ITCINTEN_GET_MASK, 57 +\par EDMA3_DRV_OPT_ITCINTEN_SET_MASK, 57 +\par EDMA3_DRV_OPT_SAM_CLR_MASK, 57 +\par EDMA3_DRV_OPT_SAM_GET_MASK, 57 +\par EDMA3_DRV_OPT_SAM_SET_MASK, 57 +\par EDMA3_DRV_OPT_STATIC_CLR_MASK, 57 +\par EDMA3_DRV_OPT_STATIC_GET_MASK, 58 +\par EDMA3_DRV_OPT_STATIC_SET_MASK, 58 +\par EDMA3_DRV_OPT_SYNCDIM_CLR_MASK, 58 +\par EDMA3_DRV_OPT_SYNCDIM_GET_MASK, 58 +\par EDMA3_DRV_OPT_SYNCDIM_SET_MASK, 58 +\par EDMA3_DRV_OPT_TCC_CLR_MASK, 58 +\par EDMA3_DRV_OPT_TCC_GET_MASK, 58 +\par EDMA3_DRV_OPT_TCC_SET_MASK, 58 +\par EDMA3_DRV_OPT_TCCHEN_CLR_MASK, 58 +\par EDMA3_DRV_OPT_TCCHEN_GET_MASK, 59 +\par EDMA3_DRV_OPT_TCCHEN_SET_MASK, 59 +\par EDMA3_DRV_OPT_TCCMODE_CLR_MASK, 59 +\par EDMA3_DRV_OPT_TCCMODE_GET_MASK, 59 +\par EDMA3_DRV_OPT_TCCMODE_SET_MASK, 59 +\par EDMA3_DRV_OPT_TCINTEN_CLR_MASK, 59 +\par EDMA3_DRV_OPT_TCINTEN_GET_MASK, 59 +\par EDMA3_DRV_OPT_TCINTEN_SET_MASK, 59 +\par EDMA3_DRV_QCH_TRWORD_CLR_MASK, 59 +\par EDMA3_DRV_QCH_TRWORD_SET_MASK, 60 +\par EDMA3_DRV_QDMAQNUM_CLR_MASK, 60 +\par EDMA3_DRV_QDMAQNUM_SET_MASK, 60 +\par EDMA3_DRV_QPRIORITY_MAX_VAL, 60 +\par EDMA3_DRV_QPRIORITY_MIN_VAL, 60 +\par EDMA3_DRV_SRCBIDX_MAX_VAL, 60 +\par EDMA3_DRV_SRCBIDX_MIN_VAL, 60 +\par EDMA3_DRV_SRCCIDX_MAX_VAL, 60 +\par EDMA3_DRV_SRCCIDX_MIN_VAL, 60 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvIntBoundVals +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_DMA_CH_MAX_VAL, 61 +\par EDMA3_DRV_LINK_CH_MAX_VAL, 61 +\par EDMA3_DRV_LINK_CH_MIN_VAL, 62 +\par EDMA3_DRV_LOG_CH_MAX_VAL, 62 +\par EDMA3_DRV_QDMA_CH_MAX_VAL, 62 +\par EDMA3_DRV_QDMA_CH_MIN_VAL, 62 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvIntObjMaint +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_CLOSED, 63 +\par EDMA3_DRV_CREATED, 63 +\par EDMA3_DRV_DELETED, 63 +\par EDMA3_DRV_ObjState, 63 +\par EDMA3_DRV_OPENED, 63 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvMain +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_CH_NO_PARAM_MAP, 6 +\par EDMA3_DRV_CH_NO_TCC_MAP, 6 +\par EDMA3_DRV_close, 6 +\par EDMA3_DRV_create, 7 +\par EDMA3_DRV_delete, 7 +\par EDMA3_DRV_open, 8 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupOpt +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_checkAndClearTcc, 45 +\par EDMA3_DRV_getCCRegister, 45 +\par EDMA3_DRV_getInstHandle, 45 +\par EDMA3_DRV_getMapChToEvtQ, 46 +\par EDMA3_DRV_getPaRAM, 46 +\par EDMA3_DRV_getPaRAMEntry, 47 +\par EDMA3_DRV_getPaRAMField, 47 +\par EDMA3_DRV_getPaRAMPhyAddr, 48 +\par EDMA3_DRV_Ioctl, 48 +\par EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION, 43 +\par EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION, 43 +\par EDMA3_DRV_IoctlCmd, 43 +\par EDMA3_DRV_mapChToEvtQ, 49 +\par EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT, 44 +\par EDMA3_DRV_PARAM_ENTRY_CCNT, 44 +\par EDMA3_DRV_PARAM_ENTRY_DST, 44 +\par EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD, 44 +\par EDMA3_DRV_PARAM_ENTRY_OPT, 43 +\par EDMA3_DRV_PARAM_ENTRY_SRC, 43 +\par EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX, 44 +\par EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX, 44 +\par EDMA3_DRV_PARAM_FIELD_ACNT, 44 +\par EDMA3_DRV_PARAM_FIELD_BCNT, 44 +\par EDMA3_DRV_PARAM_FIELD_BCNTRELOAD, 44 +\par EDMA3_DRV_PARAM_FIELD_CCNT, 44 +\par EDMA3_DRV_PARAM_FIELD_DESTADDR, 44 +\par EDMA3_DRV_PARAM_FIELD_DESTBIDX, 44 +\par EDMA3_DRV_PARAM_FIELD_DESTCIDX, 44 +\par EDMA3_DRV_PARAM_FIELD_LINKADDR, 44 +\par EDMA3_DRV_PARAM_FIELD_OPT, 44 +\par EDMA3_DRV_PARAM_FIELD_SRCADDR, 44 +\par EDMA3_DRV_PARAM_FIELD_SRCBIDX, 44 +\par EDMA3_DRV_PARAM_FIELD_SRCCIDX, 44 +\par EDMA3_DRV_PaRAMEntry, 43 +\par EDMA3_DRV_PaRAMField, 44 +\par EDMA3_DRV_setCCRegister, 49 +\par EDMA3_DRV_setEvtQPriority, 50 +\par EDMA3_DRV_setPaRAM, 50 +\par EDMA3_DRV_setPaRAMEntry, 51 +\par EDMA3_DRV_setPaRAMField, 51 +\par EDMA3_DRV_setQdmaTrigWord, 52 +\par EDMA3_DRV_waitAndClearTcc, 52 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Edma3DrvTransferSetupType +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_ADDR_MODE_FIFO, 29 +\par EDMA3_DRV_ADDR_MODE_INCR, 29 +\par EDMA3_DRV_AddrMode, 29 +\par EDMA3_DRV_chainChannel, 33 +\par EDMA3_DRV_disableTransfer, 34 +\par EDMA3_DRV_enableTransfer, 34 +\par EDMA3_DRV_FifoWidth, 29 +\par EDMA3_DRV_getOptField, 35 +\par EDMA3_DRV_ItcchEn, 30 +\par EDMA3_DRV_ITCCHEN_DIS, 30 +\par EDMA3_DRV_ITCCHEN_EN, 30 +\par EDMA3_DRV_ItcintEn, 30 +\par EDMA3_DRV_ITCINTEN_DIS, 30 +\par EDMA3_DRV_ITCINTEN_EN, 30 +\par EDMA3_DRV_OPT_FIELD_DAM, 30 +\par EDMA3_DRV_OPT_FIELD_FWID, 30 +\par EDMA3_DRV_OPT_FIELD_ITCCHEN, 31 +\par EDMA3_DRV_OPT_FIELD_ITCINTEN, 31 +\par EDMA3_DRV_OPT_FIELD_SAM, 30 +\par EDMA3_DRV_OPT_FIELD_STATIC, 30 +\par EDMA3_DRV_OPT_FIELD_SYNCDIM, 30 +\par EDMA3_DRV_OPT_FIELD_TCC, 31 +\par EDMA3_DRV_OPT_FIELD_TCCHEN, 31 +\par EDMA3_DRV_OPT_FIELD_TCCMODE, 31 +\par EDMA3_DRV_OPT_FIELD_TCINTEN, 31 +\par EDMA3_DRV_OptField, 30 +\par EDMA3_DRV_setDestIndex, 35 +\par EDMA3_DRV_setDestParams, 36 +\par EDMA3_DRV_setOptField, 37 +\par EDMA3_DRV_setSrcIndex, 38 +\par EDMA3_DRV_setSrcParams, 38 +\par EDMA3_DRV_setTransferParams, 39 +\par EDMA3_DRV_STATIC_DIS, 31 +\par EDMA3_DRV_STATIC_EN, 31 +\par EDMA3_DRV_StaticMode, 31 +\par EDMA3_DRV_SYNC_A, 32 +\par EDMA3_DRV_SYNC_AB, 32 +\par EDMA3_DRV_SyncType, 31 +\par EDMA3_DRV_TcchEn, 32 +\par EDMA3_DRV_TCCHEN_DIS, 32 +\par EDMA3_DRV_TCCHEN_EN, 32 +\par EDMA3_DRV_TccMode, 32 +\par EDMA3_DRV_TCCMODE_EARLY, 32 +\par EDMA3_DRV_TCCMODE_NORMAL, 32 +\par EDMA3_DRV_TcintEn, 32 +\par EDMA3_DRV_TCINTEN_DIS, 32 +\par EDMA3_DRV_TCINTEN_EN, 32 +\par EDMA3_DRV_TRIG_MODE_EVENT, 33 +\par EDMA3_DRV_TRIG_MODE_MANUAL, 33 +\par EDMA3_DRV_TRIG_MODE_NONE, 33 +\par EDMA3_DRV_TRIG_MODE_QDMA, 33 +\par EDMA3_DRV_TrigMode, 32 +\par EDMA3_DRV_unchainChannel, 40 +\par EDMA3_DRV_W128BIT, 30 +\par EDMA3_DRV_W16BIT, 29 +\par EDMA3_DRV_W256BIT, 30 +\par EDMA3_DRV_W32BIT, 30 +\par EDMA3_DRV_W64BIT, 30 +\par EDMA3_DRV_W8BIT, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 edma3MemCpy +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 edma3_drv_adv.c, 98 +\par edma3_drv_basic.c, 102 +\par edma3_drv_init.c, 105 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 edma3MemSet +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 edma3_drv_adv.c, 98 +\par edma3_drv_basic.c, 102 +\par edma3_drv_init.c, 105 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 edma3OpenResMgr +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 edma3_drv_init.c, 105 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 edma3RemoveMapping +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 edma3_drv_basic.c, 102 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 evtQPri +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_GblConfigParams, 70 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 evtQueueWaterMarkLvl +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_GblConfigParams, 70 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 gblCfgParams +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_Object, 81 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 gblerrCb +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_InitConfig, 73 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 gblerrCbParams +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_Instance, 75 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 gblerrData +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_InitConfig, 73 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 globalRegs +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_GblConfigParams, 70 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Internal Interface Definition for EDMA3 Driver, 53 +\par isMaster +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_InitConfig, 72 +\par EDMA3_DRV_Instance, 74 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 isSlave +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_MiscParam, 79 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 itcchEn +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_ChainOptions, 64 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 itcintEn +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_ChainOptions, 64 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 LINK_BCNTRLD +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_ParamentryRegs, 83 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 memProtectionExists +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_GblConfigParams, 70 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 numDmaChannels +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_GblConfigParams, 69 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 numEvtQueue +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_GblConfigParams, 69 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 numOpens +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_Object, 80 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 numPaRAMSets +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_GblConfigParams, 69 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 numQdmaChannels +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_GblConfigParams, 69 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 numRegions +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_GblConfigParams, 69 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 numTccs +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_GblConfigParams, 69 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 numTcs +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_GblConfigParams, 69 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 Object Maintenance, 62 +\par opt +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_PaRAMRegs, 85 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 OPT +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_ParamentryRegs, 82 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 ownDmaChannels +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_InstanceInitConfig, 77 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 ownPaRAMSets +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_InstanceInitConfig, 77 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 ownQdmaChannels +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_InstanceInitConfig, 77 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 ownTccs +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_InstanceInitConfig, 77 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 param +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_MiscParam, 79 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 paRAMId +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_ChBoundResources, 65 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 pDrvObjectHandle +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_Instance, 75 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 phyCtrllerInstId +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_Object, 80 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 ptrInitCfgArray +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 edma3_drv_adv.c, 99 +\par edma3_drv_basic.c, 103 +\par edma3_drv_init.c, 106 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 ptrRMIArray +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 edma3_drv_adv.c, 99 +\par edma3_drv_basic.c, 103 +\par edma3_drv_init.c, 106 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 regionId +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_InitConfig, 72 +\par EDMA3_DRV_Instance, 74 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 resMgrInstance +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_Instance, 75 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 resMgrObj +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 edma3_drv_adv.c, 99 +\par edma3_drv_basic.c, 103 +\par edma3_drv_init.c, 106 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 resvdDmaChannels +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_InstanceInitConfig, 77 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 resvdPaRAMSets +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_InstanceInitConfig, 77 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 resvdQdmaChannels +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_InstanceInitConfig, 78 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 resvdTccs +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_InstanceInitConfig, 78 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 shadowRegs +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_Instance, 75 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 SRC_DST_BIDX +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_ParamentryRegs, 82 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 state +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid6424133 EDMA3_DRV_Object, 80 +\par }\pard\plain \ltrpar\s84\ql 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Driver: Data Structures + + + + +

+
+

Data Structures

Here are the data structures with brief descriptions: + + + + + + + + + + + +
EDMA3_DRV_ChainOptionsStructure to be used to configure interrupt generation and chaining options
EDMA3_DRV_ChBoundResourcesEDMA3 Channel-Bound resources
EDMA3_DRV_EvtQuePriorityEvent queue priorities setup
EDMA3_DRV_GblConfigParamsInit-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information
EDMA3_DRV_InitConfigUsed to Initialize the EDMA3 Driver Instance
EDMA3_DRV_InstanceEDMA3 Driver Instance Configuration Structure
EDMA3_DRV_InstanceInitConfigInit-time Region Specific Configuration structure for EDMA3 Driver, to provide region specific Information
EDMA3_DRV_MiscParamUsed to specify the miscellaneous options during EDMA3 Driver Initialization
EDMA3_DRV_ObjectEDMA3 Driver Object (HW Specific) Maintenance structure
EDMA3_DRV_ParamentryRegsEDMA3 PaRAM Set
EDMA3_DRV_PaRAMRegsEDMA3 Parameter RAM Set in User Configurable format
+
+
Generated on Thu Oct 16 16:17:56 2008 for EDMA3 Driver by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/drv/docs/html/classes.html b/packages/ti/sdo/edma3/drv/docs/html/classes.html new file mode 100644 index 0000000..f60345e --- /dev/null +++ b/packages/ti/sdo/edma3/drv/docs/html/classes.html @@ -0,0 +1,35 @@ + + +EDMA3 Driver: Alphabetical List + + + + + +
+

Data Structure Index

E

+ +
  E  
+		EDMA3_DRV_EvtQuePriority   EDMA3_DRV_Instance   EDMA3_DRV_Object   
EDMA3_DRV_ChainOptions   EDMA3_DRV_GblConfigParams   EDMA3_DRV_InstanceInitConfig   EDMA3_DRV_ParamentryRegs   
EDMA3_DRV_ChBoundResources   EDMA3_DRV_InitConfig   EDMA3_DRV_MiscParam   EDMA3_DRV_PaRAMRegs   

E

+

+
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Generated on Thu Oct 16 16:17:55 2008 for EDMA3 Driver by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/drv/docs/html/edma3_8h.html b/packages/ti/sdo/edma3/drv/docs/html/edma3_8h.html new file mode 100644 index 0000000..dbd720d --- /dev/null +++ b/packages/ti/sdo/edma3/drv/docs/html/edma3_8h.html @@ -0,0 +1,194 @@ + + +EDMA3 Driver: edma3.h File Reference + + + + + +
+

edma3.h File Reference

EDMA3 Driver Internal header file. More... +

+#include <ti/sdo/edma3/drv/edma3_drv.h>
+#include <ti/sdo/edma3/rm/src/edma3_rl_cc.h>
+ +

+Go to the source code of this file. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Data Structures

struct  EDMA3_DRV_Object
 EDMA3 Driver Object (HW Specific) Maintenance structure. More...
struct  EDMA3_DRV_Instance
 EDMA3 Driver Instance Configuration Structure. More...
struct  EDMA3_DRV_ChBoundResources
 EDMA3 Channel-Bound resources. More...

Defines

#define EDMA3_DRV_OPT_SAM_CLR_MASK   (~EDMA3_CCRL_OPT_SAM_MASK)
#define EDMA3_DRV_OPT_SAM_SET_MASK(mode)   (((EDMA3_CCRL_OPT_SAM_MASK >> EDMA3_CCRL_OPT_SAM_SHIFT) & (mode)) << EDMA3_CCRL_OPT_SAM_SHIFT)
#define EDMA3_DRV_OPT_DAM_CLR_MASK   (~EDMA3_CCRL_OPT_DAM_MASK)
#define EDMA3_DRV_OPT_DAM_SET_MASK(mode)   (((EDMA3_CCRL_OPT_DAM_MASK >> EDMA3_CCRL_OPT_DAM_SHIFT) & (mode)) << EDMA3_CCRL_OPT_DAM_SHIFT)
#define EDMA3_DRV_OPT_SYNCDIM_CLR_MASK   (~EDMA3_CCRL_OPT_SYNCDIM_MASK)
#define EDMA3_DRV_OPT_SYNCDIM_SET_MASK(synctype)   (((EDMA3_CCRL_OPT_SYNCDIM_MASK >> EDMA3_CCRL_OPT_SYNCDIM_SHIFT) & (synctype)) << EDMA3_CCRL_OPT_SYNCDIM_SHIFT)
#define EDMA3_DRV_OPT_STATIC_CLR_MASK   (~EDMA3_CCRL_OPT_STATIC_MASK)
#define EDMA3_DRV_OPT_STATIC_SET_MASK(en)   (((EDMA3_CCRL_OPT_STATIC_MASK >> EDMA3_CCRL_OPT_STATIC_SHIFT) & (en)) << EDMA3_CCRL_OPT_STATIC_SHIFT)
#define EDMA3_DRV_OPT_FWID_CLR_MASK   (~EDMA3_CCRL_OPT_FWID_MASK)
#define EDMA3_DRV_OPT_FWID_SET_MASK(width)   (((EDMA3_CCRL_OPT_FWID_MASK >> EDMA3_CCRL_OPT_FWID_SHIFT) & (width)) << EDMA3_CCRL_OPT_FWID_SHIFT)
#define EDMA3_DRV_OPT_TCCMODE_CLR_MASK   (~EDMA3_CCRL_OPT_TCCMODE_MASK)
#define EDMA3_DRV_OPT_TCCMODE_SET_MASK(early)   (((EDMA3_CCRL_OPT_TCCMODE_MASK >> EDMA3_CCRL_OPT_TCCMODE_SHIFT) & (early)) << EDMA3_CCRL_OPT_TCCMODE_SHIFT)
#define EDMA3_DRV_OPT_TCC_CLR_MASK   (~EDMA3_CCRL_OPT_TCC_MASK)
#define EDMA3_DRV_OPT_TCC_SET_MASK(tcc)   (((EDMA3_CCRL_OPT_TCC_MASK >> EDMA3_CCRL_OPT_TCC_SHIFT) & (tcc)) << EDMA3_CCRL_OPT_TCC_SHIFT)
#define EDMA3_DRV_OPT_TCINTEN_CLR_MASK   (~EDMA3_CCRL_OPT_TCINTEN_MASK)
#define EDMA3_DRV_OPT_TCINTEN_SET_MASK(tcinten)   (((EDMA3_CCRL_OPT_TCINTEN_MASK >> EDMA3_CCRL_OPT_TCINTEN_SHIFT) & (tcinten)) << EDMA3_CCRL_OPT_TCINTEN_SHIFT)
#define EDMA3_DRV_OPT_ITCINTEN_CLR_MASK   (~EDMA3_CCRL_OPT_ITCINTEN_MASK)
#define EDMA3_DRV_OPT_ITCINTEN_SET_MASK(itcinten)   (((EDMA3_CCRL_OPT_ITCINTEN_MASK >> EDMA3_CCRL_OPT_ITCINTEN_SHIFT) & (itcinten)) << EDMA3_CCRL_OPT_ITCINTEN_SHIFT)
#define EDMA3_DRV_OPT_TCCHEN_CLR_MASK   (~EDMA3_CCRL_OPT_TCCHEN_MASK)
#define EDMA3_DRV_OPT_TCCHEN_SET_MASK(tcchen)   (((EDMA3_CCRL_OPT_TCCHEN_MASK >> EDMA3_CCRL_OPT_TCCHEN_SHIFT) & (tcchen)) << EDMA3_CCRL_OPT_TCCHEN_SHIFT)
#define EDMA3_DRV_OPT_ITCCHEN_CLR_MASK   (~EDMA3_CCRL_OPT_ITCCHEN_MASK)
#define EDMA3_DRV_OPT_ITCCHEN_SET_MASK(itcchen)   (((EDMA3_CCRL_OPT_ITCCHEN_MASK >> EDMA3_CCRL_OPT_ITCCHEN_SHIFT) & (itcchen)) << EDMA3_CCRL_OPT_ITCCHEN_SHIFT)
#define EDMA3_DRV_OPT_SAM_GET_MASK(mode)   ((mode)&1u)
#define EDMA3_DRV_OPT_DAM_GET_MASK(mode)   (((mode)&(1u<<1u))>>1u)
#define EDMA3_DRV_OPT_SYNCDIM_GET_MASK(synctype)   (((synctype)&(1u<<2u))>>2u)
#define EDMA3_DRV_OPT_STATIC_GET_MASK(en)   (((en)&(1u<<3u))>>3u)
#define EDMA3_DRV_OPT_FWID_GET_MASK(width)   (((width)&(0x7u<<8u))>>8u)
#define EDMA3_DRV_OPT_TCCMODE_GET_MASK(early)   (((early)&(1u<<11u))>>11u)
#define EDMA3_DRV_OPT_TCC_GET_MASK(tcc)   (((tcc)&(0x3fu<<12u))>>12u)
#define EDMA3_DRV_OPT_TCINTEN_GET_MASK(tcinten)   (((tcinten)&(1u<<20u))>>20u)
#define EDMA3_DRV_OPT_ITCINTEN_GET_MASK(itcinten)   (((itcinten)&(1u<<21u))>>21u)
#define EDMA3_DRV_OPT_TCCHEN_GET_MASK(tcchen)   (((tcchen)&(1u<<22u))>>22u)
#define EDMA3_DRV_OPT_ITCCHEN_GET_MASK(itcchen)   (((itcchen)&(1u<<23u))>>23u)
#define EDMA3_DRV_DMAQNUM_CLR_MASK(chNum)   (~(0x7u<<(((chNum)%8u)*4u)))
#define EDMA3_DRV_DMAQNUM_SET_MASK(chNum, queNum)   ((0x7u & (queNum)) << (((chNum)%8u)*4u))
#define EDMA3_DRV_QDMAQNUM_CLR_MASK(chNum)   (~(0x7u<<((chNum)*4u)))
#define EDMA3_DRV_QDMAQNUM_SET_MASK(chNum, queNum)   ((0x7u & (queNum)) << ((chNum)*4u))
#define EDMA3_DRV_QCH_TRWORD_CLR_MASK   (~EDMA3_CCRL_QCHMAP_TRWORD_MASK)
#define EDMA3_DRV_QCH_TRWORD_SET_MASK(paRAMId)   (((EDMA3_CCRL_QCHMAP_TRWORD_MASK >> EDMA3_CCRL_QCHMAP_TRWORD_SHIFT) & (paRAMId)) << EDMA3_CCRL_QCHMAP_TRWORD_SHIFT)
#define EDMA3_DRV_ACNT_MAX_VAL   (0xFFFFu)
#define EDMA3_DRV_BCNT_MAX_VAL   (0xFFFFu)
#define EDMA3_DRV_CCNT_MAX_VAL   (0xFFFFu)
#define EDMA3_DRV_BCNTRELD_MAX_VAL   (0xFFFFu)
#define EDMA3_DRV_SRCBIDX_MAX_VAL   (0x7FFF)
#define EDMA3_DRV_SRCBIDX_MIN_VAL   (-32768)
#define EDMA3_DRV_SRCCIDX_MAX_VAL   (0x7FFF)
#define EDMA3_DRV_SRCCIDX_MIN_VAL   (-32768)
#define EDMA3_DRV_DSTBIDX_MAX_VAL   (0x7FFF)
#define EDMA3_DRV_DSTBIDX_MIN_VAL   (-32768)
#define EDMA3_DRV_DSTCIDX_MAX_VAL   (0x7FFF)
#define EDMA3_DRV_DSTCIDX_MIN_VAL   (-32768)
#define EDMA3_DRV_QPRIORITY_MAX_VAL   (7u)
#define EDMA3_DRV_QPRIORITY_MIN_VAL   (0u)
#define EDMA3_DRV_DMA_CH_MAX_VAL   (EDMA3_MAX_DMA_CH - 1u)
#define EDMA3_DRV_LINK_CH_MIN_VAL   (EDMA3_DRV_DMA_CH_MAX_VAL + 1u)
#define EDMA3_DRV_LINK_CH_MAX_VAL   (EDMA3_DRV_LINK_CH_MIN_VAL + EDMA3_MAX_PARAM_SETS - 1u)
#define EDMA3_DRV_QDMA_CH_MIN_VAL   (EDMA3_DRV_LINK_CH_MAX_VAL + 1u)
#define EDMA3_DRV_QDMA_CH_MAX_VAL   (EDMA3_DRV_QDMA_CH_MIN_VAL + EDMA3_MAX_QDMA_CH - 1u)
#define EDMA3_DRV_LOG_CH_MAX_VAL   (EDMA3_DRV_QDMA_CH_MAX_VAL)

Enumerations

enum  EDMA3_DRV_ObjState {
+  EDMA3_DRV_DELETED = 0, +
+  EDMA3_DRV_CREATED = 1, +
+  EDMA3_DRV_OPENED = 2, +
+  EDMA3_DRV_CLOSED = 3 +
+ }
enum  EDMA3_DRV_ChannelType {
+  EDMA3_DRV_CHANNEL_TYPE_NONE, +
+  EDMA3_DRV_CHANNEL_TYPE_DMA = 1, +
+  EDMA3_DRV_CHANNEL_TYPE_QDMA = 2, +
+  EDMA3_DRV_CHANNEL_TYPE_LINK = 3 +
+ }
 EDMA3 Channel Type. More...
+

Detailed Description

+EDMA3 Driver Internal header file. +

+This file contains implementation specific details used by the EDMA3 Driver internally.

+(C) Copyright 2006, Texas Instruments, Inc

+

Version:
0.1.0 Joseph Fernandez - Created 0.2.0 Anuj Aggarwal - Modified it for EDMA3 package
    +
  • Added multiple instances capability 0.2.1 Anuj Aggarwal - Modified it for more run time configuration.
  • Made EDMA3 package OS independent. 0.2.2 Anuj Aggarwal - Critical section handling code modification. Uses semaphore and interrupts disabling mechanism for resource sharing. 0.3.0 Anuj Aggarwal - Renamed EDMA3_DVR to EDMA3_DRV
  • IPR bit clearing in RM ISR issue fixed.
  • Sample application made generic 0.3.1 Anuj Aggarwal - Added DMA/QDMA Channel to TCC mapping, to fix QDMA missed event issue. 0.3.2 Anuj Aggarwal - Added support for POLL mode
  • Added a new API to modify the CC Register. 1.0.0 Anuj Aggarwal - Fixed resource allocation related bugs. 1.0.0.1 Anuj Aggarwal - Fixed spurious missed event generation related bug. 1.0.0.2 Anuj Aggarwal - Made the EDMA3 package RTSC compliant. 1.0.0.3 Anuj Aggarwal - Changed the directory structure as per RTSC standard. 1.01.00.01 Anuj Aggarwal - a) Added new APIs to allocate logical channels b) Created EDMA3 config files for different platforms c) Misc changes 1.02.00.01 Anuj Aggarwal - a) Added DM6467 support b) Fixed some MRs 1.03.00.01 Anuj Aggarwal - a) Added non-RTSC PJT files b) IOCTL Interface added. c) Fixed some MRs. 1.04 Anuj Aggarwal - a) Header files modified to have extern "C" declarations. b) Implemented ECNs DPSP00009815 & DPSP00010035.
+
+
+
Generated on Thu Oct 16 16:17:55 2008 for EDMA3 Driver by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/drv/docs/html/edma3__drv_8h-source.html b/packages/ti/sdo/edma3/drv/docs/html/edma3__drv_8h-source.html new file mode 100644 index 0000000..6fe7190 --- /dev/null +++ b/packages/ti/sdo/edma3/drv/docs/html/edma3__drv_8h-source.html @@ -0,0 +1,799 @@ + + +EDMA3 Driver: edma3_drv.h Source File + + + + + +
Generated on Thu Oct 16 16:17:55 2008 for EDMA3 Driver by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/drv/docs/html/edma3__drv_8h.html b/packages/ti/sdo/edma3/drv/docs/html/edma3__drv_8h.html new file mode 100644 index 0000000..b369f3b --- /dev/null +++ b/packages/ti/sdo/edma3/drv/docs/html/edma3__drv_8h.html @@ -0,0 +1,554 @@ + + +EDMA3 Driver: edma3_drv.h File Reference + + + + + +
+

edma3_drv.h File Reference

EDMA3 Controller. More... +

+#include <ti/sdo/edma3/rm/edma3_rm.h>
+ +

+Go to the source code of this file. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Data Structures

struct  EDMA3_DRV_GblConfigParams
 Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. More...
struct  EDMA3_DRV_InstanceInitConfig
 Init-time Region Specific Configuration structure for EDMA3 Driver, to provide region specific Information. More...
struct  EDMA3_DRV_InitConfig
 Used to Initialize the EDMA3 Driver Instance. More...
struct  EDMA3_DRV_MiscParam
 Used to specify the miscellaneous options during EDMA3 Driver Initialization. More...
struct  EDMA3_DRV_ChainOptions
 Structure to be used to configure interrupt generation and chaining options. More...
struct  EDMA3_DRV_ParamentryRegs
 EDMA3 PaRAM Set. More...
struct  EDMA3_DRV_PaRAMRegs
 EDMA3 Parameter RAM Set in User Configurable format. More...
struct  EDMA3_DRV_EvtQuePriority
 Event queue priorities setup. More...

Defines

#define EDMA3_DRV_E_BASE   (-128)
#define EDMA3_DRV_E_OBJ_NOT_DELETED   (EDMA3_DRV_E_BASE)
#define EDMA3_DRV_E_OBJ_NOT_CLOSED   (EDMA3_DRV_E_BASE-1)
#define EDMA3_DRV_E_OBJ_NOT_OPENED   (EDMA3_DRV_E_BASE-2)
#define EDMA3_DRV_E_RM_CLOSE_FAIL   (EDMA3_DRV_E_BASE-3)
#define EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL   (EDMA3_DRV_E_BASE-4)
#define EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL   (EDMA3_DRV_E_BASE-5)
#define EDMA3_DRV_E_PARAM_SET_UNAVAIL   (EDMA3_DRV_E_BASE-6)
#define EDMA3_DRV_E_TCC_UNAVAIL   (EDMA3_DRV_E_BASE-7)
#define EDMA3_DRV_E_TCC_REGISTER_FAIL   (EDMA3_DRV_E_BASE-8)
#define EDMA3_DRV_E_CH_PARAM_BIND_FAIL   (EDMA3_DRV_E_BASE-9)
#define EDMA3_DRV_E_ADDRESS_NOT_ALIGNED   (EDMA3_DRV_E_BASE-10)
#define EDMA3_DRV_E_INVALID_PARAM   (EDMA3_DRV_E_BASE-11)
#define EDMA3_DRV_E_INVALID_STATE   (EDMA3_DRV_E_BASE-12)
#define EDMA3_DRV_E_INST_ALREADY_EXISTS   (EDMA3_DRV_E_BASE-13)
#define EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED   (EDMA3_DRV_E_BASE-14)
#define EDMA3_DRV_E_SEMAPHORE   (EDMA3_DRV_E_BASE-15)
#define EDMA3_DRV_E_INST_NOT_OPENED   (EDMA3_DRV_E_BASE-16)
#define EDMA3_DRV_CH_NO_PARAM_MAP   EDMA3_RM_CH_NO_PARAM_MAP
#define EDMA3_DRV_CH_NO_TCC_MAP   EDMA3_RM_CH_NO_TCC_MAP
#define EDMA3_DRV_DMA_CHANNEL_ANY   1002u
#define EDMA3_DRV_QDMA_CHANNEL_ANY   1003u
#define EDMA3_DRV_TCC_ANY   1004u
#define EDMA3_DRV_LINK_CHANNEL   1005u
#define EDMA3_DRV_QDMA_CHANNEL_0   (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS)
 QDMA Channel defines They should be used while requesting a specific QDMA channel.
#define EDMA3_DRV_QDMA_CHANNEL_1   (EDMA3_DRV_QDMA_CHANNEL_0+1u)
#define EDMA3_DRV_QDMA_CHANNEL_2   (EDMA3_DRV_QDMA_CHANNEL_0+2u)
#define EDMA3_DRV_QDMA_CHANNEL_3   (EDMA3_DRV_QDMA_CHANNEL_0+3u)
#define EDMA3_DRV_QDMA_CHANNEL_4   (EDMA3_DRV_QDMA_CHANNEL_0+4u)
#define EDMA3_DRV_QDMA_CHANNEL_5   (EDMA3_DRV_QDMA_CHANNEL_0+5u)
#define EDMA3_DRV_QDMA_CHANNEL_6   (EDMA3_DRV_QDMA_CHANNEL_0+6u)
#define EDMA3_DRV_QDMA_CHANNEL_7   (EDMA3_DRV_QDMA_CHANNEL_0+7u)

Enumerations

enum  EDMA3_DRV_HW_CHANNEL_EVENT {
+  EDMA3_DRV_HW_CHANNEL_EVENT_0 = 0, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_1, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_2, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_3, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_4, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_5, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_6, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_7, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_8, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_9, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_10, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_11, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_12, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_13, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_14, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_15, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_16, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_17, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_18, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_19, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_20, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_21, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_22, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_23, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_24, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_25, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_26, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_27, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_28, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_29, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_30, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_31, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_32, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_33, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_34, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_35, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_36, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_37, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_38, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_39, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_40, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_41, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_42, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_43, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_44, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_45, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_46, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_47, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_48, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_49, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_50, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_51, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_52, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_53, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_54, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_55, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_56, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_57, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_58, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_59, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_60, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_61, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_62, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_63 +
+ }
 DMA Channels assigned to different Hardware Events. They should be used while requesting a specific DMA channel. One possible usage is to maintain a SoC specific file, which will contain the mapping of these hardware events to the respective peripherals for better understanding and lesser probability of errors. Also, if any event associated with a particular peripheral gets changed, only that SoC specific file needs to be changed. More...
enum  EDMA3_DRV_OptField {
+  EDMA3_DRV_OPT_FIELD_SAM = 0, +
+  EDMA3_DRV_OPT_FIELD_DAM = 1, +
+  EDMA3_DRV_OPT_FIELD_SYNCDIM = 2, +
+  EDMA3_DRV_OPT_FIELD_STATIC = 3, +
+  EDMA3_DRV_OPT_FIELD_FWID = 4, +
+  EDMA3_DRV_OPT_FIELD_TCCMODE = 5, +
+  EDMA3_DRV_OPT_FIELD_TCC = 6, +
+  EDMA3_DRV_OPT_FIELD_TCINTEN = 7, +
+  EDMA3_DRV_OPT_FIELD_ITCINTEN = 8, +
+  EDMA3_DRV_OPT_FIELD_TCCHEN = 9, +
+  EDMA3_DRV_OPT_FIELD_ITCCHEN = 10 +
+ }
 OPT Field Offset. More...
enum  EDMA3_DRV_AddrMode {
+  EDMA3_DRV_ADDR_MODE_INCR = 0, +
+  EDMA3_DRV_ADDR_MODE_FIFO = 1 +
+ }
 EDMA Addressing modes. More...
enum  EDMA3_DRV_SyncType {
+  EDMA3_DRV_SYNC_A = 0, +
+  EDMA3_DRV_SYNC_AB = 1 +
+ }
 EDMA Transfer Synchronization type. More...
enum  EDMA3_DRV_StaticMode {
+  EDMA3_DRV_STATIC_DIS = 0, +
+  EDMA3_DRV_STATIC_EN = 1 +
+ }
 True/False: PaRAM set is Static or not. A Static PaRAM set is updated or linked after TR is submitted. More...
enum  EDMA3_DRV_FifoWidth {
+  EDMA3_DRV_W8BIT = 0, +
+  EDMA3_DRV_W16BIT = 1, +
+  EDMA3_DRV_W32BIT = 2, +
+  EDMA3_DRV_W64BIT = 3, +
+  EDMA3_DRV_W128BIT = 4, +
+  EDMA3_DRV_W256BIT = 5 +
+ }
 EDMA3 FIFO width. More...
enum  EDMA3_DRV_TccMode {
+  EDMA3_DRV_TCCMODE_NORMAL = 0, +
+  EDMA3_DRV_TCCMODE_EARLY = 1 +
+ }
 Transfer complete code mode. Indicates the point at which a transfer is considered completed for chaining and interrupt generation. More...
enum  EDMA3_DRV_TcintEn {
+  EDMA3_DRV_TCINTEN_DIS = 0, +
+  EDMA3_DRV_TCINTEN_EN = 1 +
+ }
 Transfer complete interrupt enable. More...
enum  EDMA3_DRV_ItcintEn {
+  EDMA3_DRV_ITCINTEN_DIS = 0, +
+  EDMA3_DRV_ITCINTEN_EN = 1 +
+ }
 Intermediate Transfer complete interrupt enable. More...
enum  EDMA3_DRV_TcchEn {
+  EDMA3_DRV_TCCHEN_DIS = 0, +
+  EDMA3_DRV_TCCHEN_EN = 1 +
+ }
 Transfer complete chaining enable. More...
enum  EDMA3_DRV_ItcchEn {
+  EDMA3_DRV_ITCCHEN_DIS = 0, +
+  EDMA3_DRV_ITCCHEN_EN = 1 +
+ }
 Intermediate Transfer complete chaining enable. More...
enum  EDMA3_DRV_TrigMode {
+  EDMA3_DRV_TRIG_MODE_MANUAL = 0, +
+  EDMA3_DRV_TRIG_MODE_QDMA = 1, +
+  EDMA3_DRV_TRIG_MODE_EVENT = 2, +
+  EDMA3_DRV_TRIG_MODE_NONE = 3 +
+ }
 EDMA Trigger Mode Selection. More...
enum  EDMA3_DRV_PaRAMEntry {
+  EDMA3_DRV_PARAM_ENTRY_OPT = 0, +
+  EDMA3_DRV_PARAM_ENTRY_SRC = 1, +
+  EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT = 2, +
+  EDMA3_DRV_PARAM_ENTRY_DST = 3, +
+  EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX = 4, +
+  EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD = 5, +
+  EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX = 6, +
+  EDMA3_DRV_PARAM_ENTRY_CCNT = 7 +
+ }
 PaRAM Set Entry type. More...
enum  EDMA3_DRV_PaRAMField {
+  EDMA3_DRV_PARAM_FIELD_OPT = 0, +
+  EDMA3_DRV_PARAM_FIELD_SRCADDR = 1, +
+  EDMA3_DRV_PARAM_FIELD_ACNT = 2, +
+  EDMA3_DRV_PARAM_FIELD_BCNT = 3, +
+  EDMA3_DRV_PARAM_FIELD_DESTADDR = 4, +
+  EDMA3_DRV_PARAM_FIELD_SRCBIDX = 5, +
+  EDMA3_DRV_PARAM_FIELD_DESTBIDX = 6, +
+  EDMA3_DRV_PARAM_FIELD_LINKADDR = 7, +
+  EDMA3_DRV_PARAM_FIELD_BCNTRELOAD = 8, +
+  EDMA3_DRV_PARAM_FIELD_SRCCIDX = 9, +
+  EDMA3_DRV_PARAM_FIELD_DESTCIDX = 10, +
+  EDMA3_DRV_PARAM_FIELD_CCNT = 11 +
+ }
 PaRAM Set Field type. More...
enum  EDMA3_DRV_IoctlCmd {
+  EDMA3_DRV_IOCTL_MIN_IOCTL = 0, +
+  EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION, +
+  EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION, +
+  EDMA3_DRV_IOCTL_MAX_IOCTL +
+ }
 EDMA3 Driver IOCTL commands. More...

Functions

EDMA3_DRV_Result EDMA3_DRV_create (unsigned int phyCtrllerInstId, const EDMA3_DRV_GblConfigParams *gblCfgParams, const void *miscParam)
 Create EDMA3 Driver Object.
EDMA3_DRV_Result EDMA3_DRV_delete (unsigned int phyCtrllerInstId, const void *param)
 Delete EDMA3 Driver Object.
EDMA3_DRV_Handle EDMA3_DRV_open (unsigned int phyCtrllerInstId, const EDMA3_DRV_InitConfig *initCfg, EDMA3_DRV_Result *errorCode)
 Open EDMA3 Driver Instance.
EDMA3_DRV_Result EDMA3_DRV_close (EDMA3_DRV_Handle hEdma, const void *param)
 Close the EDMA3 Driver Instance.
EDMA3_DRV_Result EDMA3_DRV_requestChannel (EDMA3_DRV_Handle hEdma, unsigned int *pLCh, unsigned int *pTcc, EDMA3_RM_EventQueue evtQueue, EDMA3_RM_TccCallback tccCb, void *cbData)
 Request a DMA/QDMA/Link channel.
EDMA3_DRV_Result EDMA3_DRV_freeChannel (EDMA3_DRV_Handle hEdma, unsigned int channelId)
 Free the specified channel (DMA/QDMA/Link) and its associated resources (PaRAM Set, TCC etc) and removes various mappings.
EDMA3_DRV_Result EDMA3_DRV_clearErrorBits (EDMA3_DRV_Handle hEdma, unsigned int channelId)
 Clears Event Register and Error Register for a specific DMA channel and brings back EDMA3 to its initial state.
EDMA3_DRV_Result EDMA3_DRV_linkChannel (EDMA3_DRV_Handle hEdma, unsigned int lCh1, unsigned int lCh2)
 Link two logical channels.
EDMA3_DRV_Result EDMA3_DRV_unlinkChannel (EDMA3_DRV_Handle hEdma, unsigned int lCh)
 Unlink the channel from the earlier linked logical channel.
EDMA3_DRV_Result EDMA3_DRV_setOptField (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_OptField optField, unsigned int newOptFieldVal)
 Set a particular OPT field in the PaRAM set associated with the logical channel 'lCh'.
EDMA3_DRV_Result EDMA3_DRV_getOptField (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_OptField optField, unsigned int *optFieldVal)
 Get a particular OPT field in the PaRAM set associated with the logical channel 'lCh'.
EDMA3_DRV_Result EDMA3_DRV_setSrcParams (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int srcAddr, EDMA3_DRV_AddrMode addrMode, EDMA3_DRV_FifoWidth fifoWidth)
 DMA source parameters setup.
EDMA3_DRV_Result EDMA3_DRV_setDestParams (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int destAddr, EDMA3_DRV_AddrMode addrMode, EDMA3_DRV_FifoWidth fifoWidth)
 DMA Destination parameters setup.
EDMA3_DRV_Result EDMA3_DRV_setSrcIndex (EDMA3_DRV_Handle hEdma, unsigned int lCh, int srcBIdx, int srcCIdx)
 DMA source index setup.
EDMA3_DRV_Result EDMA3_DRV_setDestIndex (EDMA3_DRV_Handle hEdma, unsigned int lCh, int destBIdx, int destCIdx)
 DMA destination index setup.
EDMA3_DRV_Result EDMA3_DRV_setTransferParams (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int aCnt, unsigned int bCnt, unsigned int cCnt, unsigned int bCntReload, EDMA3_DRV_SyncType syncType)
 DMA transfer parameters setup.
EDMA3_DRV_Result EDMA3_DRV_chainChannel (EDMA3_DRV_Handle hEdma, unsigned int lCh1, unsigned int lCh2, const EDMA3_DRV_ChainOptions *chainOptions)
 Chain the two specified channels.
EDMA3_DRV_Result EDMA3_DRV_unchainChannel (EDMA3_DRV_Handle hEdma, unsigned int lCh)
 Unchain the two channels.
EDMA3_DRV_Result EDMA3_DRV_enableTransfer (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_TrigMode trigMode)
 Start EDMA transfer on the specified channel.
EDMA3_DRV_Result EDMA3_DRV_disableTransfer (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_TrigMode trigMode)
 Disable DMA transfer on the specified channel.
EDMA3_DRV_Result EDMA3_DRV_setQdmaTrigWord (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_RM_QdmaTrigWord trigWord)
 Assign a Trigger Word to the specified QDMA channel.
EDMA3_DRV_Result EDMA3_DRV_setPaRAM (EDMA3_DRV_Handle hEdma, unsigned int lCh, const EDMA3_DRV_PaRAMRegs *newPaRAM)
 Copy the user specified PaRAM Set onto the PaRAM Set associated with the logical channel (DMA/QDMA/Link).
EDMA3_DRV_Result EDMA3_DRV_getPaRAM (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMRegs *currPaRAM)
 Retrieve existing PaRAM set associated with specified logical channel (DMA/QDMA/Link).
EDMA3_DRV_Result EDMA3_DRV_setPaRAMEntry (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMEntry paRAMEntry, unsigned int newPaRAMEntryVal)
 Set a particular PaRAM set entry of the specified PaRAM set.
EDMA3_DRV_Result EDMA3_DRV_getPaRAMEntry (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMEntry paRAMEntry, unsigned int *paRAMEntryVal)
 Get a particular PaRAM set entry of the specified PaRAM set.
EDMA3_DRV_Result EDMA3_DRV_setPaRAMField (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMField paRAMField, unsigned int newPaRAMFieldVal)
 Set a particular PaRAM set field of the specified PaRAM set.
EDMA3_DRV_Result EDMA3_DRV_getPaRAMField (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMField paRAMField, unsigned int *currPaRAMFieldVal)
 Get a particular PaRAM set field of the specified PaRAM set.
EDMA3_DRV_Result EDMA3_DRV_setEvtQPriority (EDMA3_DRV_Handle hEdma, const EDMA3_DRV_EvtQuePriority *evtQPriObj)
 Sets EDMA TC priority.
EDMA3_DRV_Result EDMA3_DRV_mapChToEvtQ (EDMA3_DRV_Handle hEdma, unsigned int channelId, EDMA3_RM_EventQueue eventQ)
 Associate Channel to Event Queue.
EDMA3_DRV_Result EDMA3_DRV_getMapChToEvtQ (EDMA3_DRV_Handle hEdma, unsigned int channelId, unsigned int *mappedEvtQ)
 Get the Event Queue mapped to the specified DMA/QDMA channel.
EDMA3_DRV_Result EDMA3_DRV_setCCRegister (EDMA3_DRV_Handle hEdma, unsigned int regOffset, unsigned int newRegValue)
 Set the Channel Controller (CC) Register value.
EDMA3_DRV_Result EDMA3_DRV_getCCRegister (EDMA3_DRV_Handle hEdma, unsigned int regOffset, unsigned int *regValue)
 Get the Channel Controller (CC) Register value.
EDMA3_DRV_Result EDMA3_DRV_waitAndClearTcc (EDMA3_DRV_Handle hEdma, unsigned int tccNo)
 Wait for a transfer completion interrupt to occur and clear it.
EDMA3_DRV_Result EDMA3_DRV_checkAndClearTcc (EDMA3_DRV_Handle hEdma, unsigned int tccNo, unsigned short *tccStatus)
 Returns the status of a previously initiated transfer.
EDMA3_DRV_Result EDMA3_DRV_getPaRAMPhyAddr (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int *paramPhyAddr)
 Get the PaRAM Set Physical Address associated with a logical channel.
EDMA3_DRV_Result EDMA3_DRV_Ioctl (EDMA3_DRV_Handle hEdma, EDMA3_DRV_IoctlCmd cmd, void *cmdArg, void *param)
 EDMA3 Driver IOCTL.
EDMA3_DRV_Handle EDMA3_DRV_getInstHandle (unsigned int phyCtrllerInstId, EDMA3_RM_RegionId regionId, EDMA3_DRV_Result *errorCode)
 Return the previously opened EDMA3 Driver Instance handle.
+

Detailed Description

+EDMA3 Controller. +

+This file contains Application Interface for the EDMA3 Driver. EDMA3 Driver uses the EDMA3 Resource Manager internally for resource allocation, interrupt handling and EDMA3 registers programming.

+(C) Copyright 2006, Texas Instruments, Inc

+

Version:
0.0.1 Purushotam Kumar - Created 0.1.0 Joseph Fernandez - Made generic
    +
  • Added documentation
  • Moved SoC specific defines to SoC specific header. 0.2.0 Anuj Aggarwal - Modified it for EDMA3 package
  • Added multiple instances capability 0.2.1 Anuj Aggarwal - Modified it for more run time configuration.
  • Made EDMA3 package OS independent. 0.2.2 Anuj Aggarwal - Critical section handling code modification. Uses semaphore and interrupts disabling mechanism for resource sharing. 0.3.0 Anuj Aggarwal - Renamed EDMA3_DVR to EDMA3_DRV
  • IPR bit clearing in RM ISR issue fixed.
  • Sample application made generic 0.3.1 Anuj Aggarwal - Added DMA/QDMA Channel to TCC mapping, to fix QDMA missed event issue. 0.3.2 Anuj Aggarwal - Added support for POLL mode
  • Added a new API to modify the CC Register. 1.0.0 Anuj Aggarwal - Fixed resource allocation related bugs. 1.0.0.1 Anuj Aggarwal - Fixed spurious missed event generation related bug. 1.0.0.2 Anuj Aggarwal - Made the EDMA3 package RTSC compliant. 1.0.0.3 Anuj Aggarwal - Changed the directory structure as per RTSC standard. 1.01.00.01 Anuj Aggarwal - a) Added new APIs to allocate logical channels b) Created EDMA3 config files for different platforms c) Misc changes 1.02.00.01 Anuj Aggarwal - a) Added DM6467 support b) Fixed some MRs 1.03.00.01 Anuj Aggarwal - a) Added non-RTSC PJT files b) IOCTL Interface added. c) Fixed some MRs. 1.04 Anuj Aggarwal - a) Header files modified to have extern "C" declarations. b) Implemented ECNs DPSP00009815 & DPSP00010035.
+
+
+
Generated on Thu Oct 16 16:17:55 2008 for EDMA3 Driver by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/drv/docs/html/edma3__drv__adv_8c.html b/packages/ti/sdo/edma3/drv/docs/html/edma3__drv__adv_8c.html new file mode 100644 index 0000000..3750b0f --- /dev/null +++ b/packages/ti/sdo/edma3/drv/docs/html/edma3__drv__adv_8c.html @@ -0,0 +1,321 @@ + + +EDMA3 Driver: edma3_drv_adv.c File Reference + + + + + +
+

edma3_drv_adv.c File Reference

EDMA3 Driver Advanced Interface Implementation This file contains advanced-level EDMA3 Driver APIs which are required to: a) Link and chain two channels. b) Set/get the whole PaRAM Set in one shot. c) Set/get each individual field of the PaRAM Set. d) Poll mode APIs. e) IOCTL interface. These APIs are provided to have complete control on the EDMA3 hardware and normally advanced users are expected to use them for their specific use-cases. More... +

+#include <ti/sdo/edma3/drv/src/edma3.h>
+#include <ti/sdo/edma3/rm/src/edma3ResMgr.h>
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Functions

void edma3MemSet (void *dst, unsigned char data, unsigned int len)
void edma3MemCpy (void *dst, const void *src, unsigned int len)
EDMA3_DRV_Result EDMA3_DRV_linkChannel (EDMA3_DRV_Handle hEdma, unsigned int lCh1, unsigned int lCh2)
 Link two logical channels.
EDMA3_DRV_Result EDMA3_DRV_unlinkChannel (EDMA3_DRV_Handle hEdma, unsigned int lCh)
 Unlink the channel from the earlier linked logical channel.
EDMA3_DRV_Result EDMA3_DRV_chainChannel (EDMA3_DRV_Handle hEdma, unsigned int lCh1, unsigned int lCh2, const EDMA3_DRV_ChainOptions *chainOptions)
 Chain the two specified channels.
EDMA3_DRV_Result EDMA3_DRV_unchainChannel (EDMA3_DRV_Handle hEdma, unsigned int lCh)
 Unchain the two channels.
EDMA3_DRV_Result EDMA3_DRV_setQdmaTrigWord (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_RM_QdmaTrigWord trigWord)
 Assign a Trigger Word to the specified QDMA channel.
EDMA3_DRV_Result EDMA3_DRV_setPaRAM (EDMA3_DRV_Handle hEdma, unsigned int lCh, const EDMA3_DRV_PaRAMRegs *newPaRAM)
 Copy the user specified PaRAM Set onto the PaRAM Set associated with the logical channel (DMA/QDMA/Link).
EDMA3_DRV_Result EDMA3_DRV_getPaRAM (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMRegs *currPaRAM)
 Retrieve existing PaRAM set associated with specified logical channel (DMA/QDMA/Link).
EDMA3_DRV_Result EDMA3_DRV_setPaRAMEntry (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMEntry paRAMEntry, unsigned int newPaRAMEntryVal)
 Set a particular PaRAM set entry of the specified PaRAM set.
EDMA3_DRV_Result EDMA3_DRV_getPaRAMEntry (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMEntry paRAMEntry, unsigned int *paRAMEntryVal)
 Get a particular PaRAM set entry of the specified PaRAM set.
EDMA3_DRV_Result EDMA3_DRV_setPaRAMField (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMField paRAMField, unsigned int newPaRAMFieldVal)
 Set a particular PaRAM set field of the specified PaRAM set.
EDMA3_DRV_Result EDMA3_DRV_getPaRAMField (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMField paRAMField, unsigned int *currPaRAMFieldVal)
 Get a particular PaRAM set field of the specified PaRAM set.
EDMA3_DRV_Result EDMA3_DRV_setEvtQPriority (EDMA3_DRV_Handle hEdma, const EDMA3_DRV_EvtQuePriority *evtQPriObj)
 Sets EDMA TC priority.
EDMA3_DRV_Result EDMA3_DRV_mapChToEvtQ (EDMA3_DRV_Handle hEdma, unsigned int channelId, EDMA3_RM_EventQueue eventQ)
 Associate Channel to Event Queue.
EDMA3_DRV_Result EDMA3_DRV_getMapChToEvtQ (EDMA3_DRV_Handle hEdma, unsigned int channelId, unsigned int *mappedEvtQ)
 Get the Event Queue mapped to the specified DMA/QDMA channel.
EDMA3_DRV_Result EDMA3_DRV_setCCRegister (EDMA3_DRV_Handle hEdma, unsigned int regOffset, unsigned int newRegValue)
 Set the Channel Controller (CC) Register value.
EDMA3_DRV_Result EDMA3_DRV_getCCRegister (EDMA3_DRV_Handle hEdma, unsigned int regOffset, unsigned int *regValue)
 Get the Channel Controller (CC) Register value.
EDMA3_DRV_Result EDMA3_DRV_waitAndClearTcc (EDMA3_DRV_Handle hEdma, unsigned int tccNo)
 Wait for a transfer completion interrupt to occur and clear it.
EDMA3_DRV_Result EDMA3_DRV_checkAndClearTcc (EDMA3_DRV_Handle hEdma, unsigned int tccNo, unsigned short *tccStatus)
 Returns the status of a previously initiated transfer.
EDMA3_DRV_Result EDMA3_DRV_getPaRAMPhyAddr (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int *paramPhyAddr)
 Get the PaRAM Set Physical Address associated with a logical channel.
EDMA3_DRV_Result EDMA3_DRV_Ioctl (EDMA3_DRV_Handle hEdma, EDMA3_DRV_IoctlCmd cmd, void *cmdArg, void *param)
 EDMA3 Driver IOCTL.
EDMA3_DRV_Handle EDMA3_DRV_getInstHandle (unsigned int phyCtrllerInstId, EDMA3_RM_RegionId regionId, EDMA3_DRV_Result *errorCode)
 Return the previously opened EDMA3 Driver Instance handle.

Variables

const unsigned int EDMA3_MAX_RM_INSTANCES
EDMA3_RM_Obj resMgrObj [EDMA3_MAX_EDMA3_INSTANCES]
 EDMA3 Resource Manager Objects, tied to each EDMA3 HW Controller.
EDMA3_RM_InstanceInitConfig * ptrInitCfgArray
 Region Specific Configuration structure for EDMA3 controller, to provide region specific Information.
EDMA3_RM_Instance * ptrRMIArray
EDMA3_DRV_Object drvObj [EDMA3_MAX_EDMA3_INSTANCES]
 EDMA3 Driver Objects, tied to each EDMA3 HW Controller.
EDMA3_DRV_Instance drvInstance [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS]
EDMA3_DRV_ChBoundResources edma3DrvChBoundRes [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_LOGICAL_CH]
 Resources bound to a Channel.
+

Detailed Description

+EDMA3 Driver Advanced Interface Implementation This file contains advanced-level EDMA3 Driver APIs which are required to: a) Link and chain two channels. b) Set/get the whole PaRAM Set in one shot. c) Set/get each individual field of the PaRAM Set. d) Poll mode APIs. e) IOCTL interface. These APIs are provided to have complete control on the EDMA3 hardware and normally advanced users are expected to use them for their specific use-cases. +

+

Author:
: PSP Team, TII
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void edma3MemCpy (void *  dst,
const void *  src,
unsigned int  len 
)
+
+
+ +

+Local MemCpy function +

Referenced by EDMA3_DRV_create(), EDMA3_DRV_getPaRAM(), EDMA3_DRV_open(), EDMA3_DRV_setPaRAM(), and edma3OpenResMgr().

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void edma3MemSet (void *  dst,
unsigned char  data,
unsigned int  len 
)
+
+
+ +

+Local MemSet function +

Referenced by EDMA3_DRV_close(), EDMA3_DRV_create(), and EDMA3_DRV_delete().

+ +
+

+

Variable Documentation

+ +
+
+ + + + +
EDMA3_DRV_Instance drvInstance[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS]
+
+
+ +

+Handles of EDMA3 Driver Instances.

+Used to maintain information of the EDMA3 Driver Instances for each region, for each HW controller. There could be as many Driver Instances as there are shadow regions. Multiple EDMA3 Driver instances on the same shadow region are NOT allowed. +

+

+ +

+
+ + + + +
EDMA3_DRV_Object drvObj[EDMA3_MAX_EDMA3_INSTANCES]
+
+
+ +

+EDMA3 Driver Objects, tied to each EDMA3 HW Controller. +

+Typically one object will cater to one EDMA3 HW controller and will have all regions' (ARM, DSP etc) specific config information. +

+

+ +

+
+ + + + +
const unsigned int EDMA3_MAX_RM_INSTANCES
+
+
+ +

+Maximum Resource Manager Instances supported by the EDMA3 Package. +

Referenced by edma3OpenResMgr().

+ +
+

+ +

+
+ + + + +
EDMA3_DRV_ChBoundResources edma3DrvChBoundRes[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_LOGICAL_CH]
+
+
+ +

+Resources bound to a Channel. +

+When a request for a channel is made, the resources PaRAM Set and TCC get bound to that channel. This information is needed internally by the driver when a request is made to free the channel (Since it is the responsibility of the driver to free up the channel-associated resources from the Resource Manager layer). +

+

+ +

+
+ + + + +
EDMA3_RM_InstanceInitConfig* ptrInitCfgArray
+
+
+ +

+Region Specific Configuration structure for EDMA3 controller, to provide region specific Information. +

+This configuration info can also be provided by the user at run-time, while calling EDMA3_RM_open (). If not provided at run-time, this info will be taken from the config file "edma3_<PLATFORM_NAME>_cfg.c", for the specified platform. +

Referenced by edma3OpenResMgr().

+ +
+

+ +

+
+ + + + +
EDMA3_RM_Instance* ptrRMIArray
+
+
+ +

+Handles of EDMA3 Resource Manager Instances.

+Used to maintain information of the EDMA3 RM Instances for each HW controller. There could be a maximum of EDMA3_MAX_RM_INSTANCES instances per EDMA3 HW. +

Referenced by edma3OpenResMgr().

+ +
+

+ +

+
+ + + + +
EDMA3_RM_Obj resMgrObj[EDMA3_MAX_EDMA3_INSTANCES]
+
+
+ +

+EDMA3 Resource Manager Objects, tied to each EDMA3 HW Controller. +

+Typically one RM object will cater to one EDMA3 HW controller and will have all the global config information. +

Referenced by EDMA3_DRV_create().

+ +
+

+

+
Generated on Thu Oct 16 16:17:55 2008 for EDMA3 Driver by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/drv/docs/html/edma3__drv__basic_8c.html b/packages/ti/sdo/edma3/drv/docs/html/edma3__drv__basic_8c.html new file mode 100644 index 0000000..a73394e --- /dev/null +++ b/packages/ti/sdo/edma3/drv/docs/html/edma3__drv__basic_8c.html @@ -0,0 +1,321 @@ + + +EDMA3 Driver: edma3_drv_basic.c File Reference + + + + + +
+

edma3_drv_basic.c File Reference

EDMA3 Driver Basic Interface Implementation This file contains beginner-level EDMA3 Driver APIs which are required to: a) Request/free a DMA, QDMA and Link channel. b) Program various fields in the PaRAM Set like source/destination parameters, transfer parameters etc. c) Enable/disable a transfer. These APIs are provided to program a DMA/QDMA channel for simple use-cases and don't expose all the features of EDMA3 hardware. Users who want to go beyond this and have complete control on the EDMA3 hardware are advised to refer edma3_drv_adv.c source file. More... +

+#include <ti/sdo/edma3/drv/src/edma3.h>
+#include <ti/sdo/edma3/rm/src/edma3ResMgr.h>
+#include <assert.h>
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Functions

void edma3MemSet (void *dst, unsigned char data, unsigned int len)
void edma3MemCpy (void *dst, const void *src, unsigned int len)
static EDMA3_DRV_Result edma3RemoveMapping (EDMA3_DRV_Handle hEdma, unsigned int channelId)
EDMA3_DRV_Result EDMA3_DRV_requestChannel (EDMA3_DRV_Handle hEdma, unsigned int *pLCh, unsigned int *pTcc, EDMA3_RM_EventQueue evtQueue, EDMA3_RM_TccCallback tccCb, void *cbData)
 Request a DMA/QDMA/Link channel.
EDMA3_DRV_Result EDMA3_DRV_freeChannel (EDMA3_DRV_Handle hEdma, unsigned int channelId)
 Free the specified channel (DMA/QDMA/Link) and its associated resources (PaRAM Set, TCC etc) and removes various mappings.
EDMA3_DRV_Result EDMA3_DRV_clearErrorBits (EDMA3_DRV_Handle hEdma, unsigned int channelId)
 Clears Event Register and Error Register for a specific DMA channel and brings back EDMA3 to its initial state.
EDMA3_DRV_Result EDMA3_DRV_setOptField (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_OptField optField, unsigned int newOptFieldVal)
 Set a particular OPT field in the PaRAM set associated with the logical channel 'lCh'.
EDMA3_DRV_Result EDMA3_DRV_getOptField (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_OptField optField, unsigned int *optFieldVal)
 Get a particular OPT field in the PaRAM set associated with the logical channel 'lCh'.
EDMA3_DRV_Result EDMA3_DRV_setSrcParams (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int srcAddr, EDMA3_DRV_AddrMode addrMode, EDMA3_DRV_FifoWidth fifoWidth)
 DMA source parameters setup.
EDMA3_DRV_Result EDMA3_DRV_setDestParams (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int destAddr, EDMA3_DRV_AddrMode addrMode, EDMA3_DRV_FifoWidth fifoWidth)
 DMA Destination parameters setup.
EDMA3_DRV_Result EDMA3_DRV_setSrcIndex (EDMA3_DRV_Handle hEdma, unsigned int lCh, int srcBIdx, int srcCIdx)
 DMA source index setup.
EDMA3_DRV_Result EDMA3_DRV_setDestIndex (EDMA3_DRV_Handle hEdma, unsigned int lCh, int destBIdx, int destCIdx)
 DMA destination index setup.
EDMA3_DRV_Result EDMA3_DRV_setTransferParams (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int aCnt, unsigned int bCnt, unsigned int cCnt, unsigned int bCntReload, EDMA3_DRV_SyncType syncType)
 DMA transfer parameters setup.
EDMA3_DRV_Result EDMA3_DRV_enableTransfer (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_TrigMode trigMode)
 Start EDMA transfer on the specified channel.
EDMA3_DRV_Result EDMA3_DRV_disableTransfer (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_TrigMode trigMode)
 Disable DMA transfer on the specified channel.

Variables

const unsigned int EDMA3_MAX_RM_INSTANCES
EDMA3_RM_Obj resMgrObj [EDMA3_MAX_EDMA3_INSTANCES]
 EDMA3 Resource Manager Objects, tied to each EDMA3 HW Controller.
EDMA3_RM_InstanceInitConfig * ptrInitCfgArray
 Region Specific Configuration structure for EDMA3 controller, to provide region specific Information.
EDMA3_RM_Instance * ptrRMIArray
EDMA3_DRV_Object drvObj [EDMA3_MAX_EDMA3_INSTANCES]
 EDMA3 Driver Objects, tied to each EDMA3 HW Controller.
EDMA3_DRV_Instance drvInstance [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS]
EDMA3_DRV_ChBoundResources edma3DrvChBoundRes [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_LOGICAL_CH]
 Resources bound to a Channel.
+

Detailed Description

+EDMA3 Driver Basic Interface Implementation This file contains beginner-level EDMA3 Driver APIs which are required to: a) Request/free a DMA, QDMA and Link channel. b) Program various fields in the PaRAM Set like source/destination parameters, transfer parameters etc. c) Enable/disable a transfer. These APIs are provided to program a DMA/QDMA channel for simple use-cases and don't expose all the features of EDMA3 hardware. Users who want to go beyond this and have complete control on the EDMA3 hardware are advised to refer edma3_drv_adv.c source file. +

+

Author:
: PSP Team, TII
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void edma3MemCpy (void *  dst,
const void *  src,
unsigned int  len 
)
+
+
+ +

+Local MemCpy function +

+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void edma3MemSet (void *  dst,
unsigned char  data,
unsigned int  len 
)
+
+
+ +

+Local MemSet function +

+

+ +

+
+ + + + + + + + + + + + + + + + + + +
static EDMA3_DRV_Result edma3RemoveMapping (EDMA3_DRV_Handle  hEdma,
unsigned int  channelId 
) [static]
+
+
+ +

+Remove various mappings and do cleanup for DMA/QDMA channels +

+Disable any ongoing transfer on the channel, if transfer was enabled earlier.

+If DMA channel to PaRAM Set mapping exists, remove it too. +

References EDMA3_DRV_GblConfigParams::dmaChPaRAMMapExists, EDMA3_DRV_disableTransfer(), EDMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_DMAQNUM_CLR_MASK, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_QDMAQNUM_CLR_MASK, EDMA3_DRV_TRIG_MODE_NONE, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_Instance::pDrvObjectHandle, EDMA3_DRV_Object::phyCtrllerInstId, EDMA3_DRV_Instance::resMgrInstance, and EDMA3_DRV_ChBoundResources::trigMode.

+ +

Referenced by EDMA3_DRV_freeChannel().

+ +
+

+

Variable Documentation

+ +
+
+ + + + +
EDMA3_DRV_Instance drvInstance[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS]
+
+
+ +

+Handles of EDMA3 Driver Instances.

+Used to maintain information of the EDMA3 Driver Instances for each region, for each HW controller. There could be as many Driver Instances as there are shadow regions. Multiple EDMA3 Driver instances on the same shadow region are NOT allowed. +

+

+ +

+
+ + + + +
EDMA3_DRV_Object drvObj[EDMA3_MAX_EDMA3_INSTANCES]
+
+
+ +

+EDMA3 Driver Objects, tied to each EDMA3 HW Controller. +

+Typically one object will cater to one EDMA3 HW controller and will have all regions' (ARM, DSP etc) specific config information. +

+

+ +

+
+ + + + +
const unsigned int EDMA3_MAX_RM_INSTANCES
+
+
+ +

+Define NDEBUG to ignore assert(). NDEBUG should be defined before including assert.h header file. Maximum Resource Manager Instances supported by the EDMA3 Package. +

+

+ +

+
+ + + + +
EDMA3_DRV_ChBoundResources edma3DrvChBoundRes[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_LOGICAL_CH]
+
+
+ +

+Resources bound to a Channel. +

+When a request for a channel is made, the resources PaRAM Set and TCC get bound to that channel. This information is needed internally by the driver when a request is made to free the channel (Since it is the responsibility of the driver to free up the channel-associated resources from the Resource Manager layer). +

+

+ +

+
+ + + + +
EDMA3_RM_InstanceInitConfig* ptrInitCfgArray
+
+
+ +

+Region Specific Configuration structure for EDMA3 controller, to provide region specific Information. +

+This configuration info can also be provided by the user at run-time, while calling EDMA3_RM_open (). If not provided at run-time, this info will be taken from the config file "edma3_<PLATFORM_NAME>_cfg.c", for the specified platform. +

+

+ +

+
+ + + + +
EDMA3_RM_Instance* ptrRMIArray
+
+
+ +

+Handles of EDMA3 Resource Manager Instances.

+Used to maintain information of the EDMA3 RM Instances for each HW controller. There could be a maximum of EDMA3_MAX_RM_INSTANCES instances per EDMA3 HW. +

+

+ +

+
+ + + + +
EDMA3_RM_Obj resMgrObj[EDMA3_MAX_EDMA3_INSTANCES]
+
+
+ +

+EDMA3 Resource Manager Objects, tied to each EDMA3 HW Controller. +

+Typically one RM object will cater to one EDMA3 HW controller and will have all the global config information. +

+

+

+
Generated on Thu Oct 16 16:17:55 2008 for EDMA3 Driver by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/drv/docs/html/edma3__drv__init_8c.html b/packages/ti/sdo/edma3/drv/docs/html/edma3__drv__init_8c.html new file mode 100644 index 0000000..3b7f0dd --- /dev/null +++ b/packages/ti/sdo/edma3/drv/docs/html/edma3__drv__init_8c.html @@ -0,0 +1,304 @@ + + +EDMA3 Driver: edma3_drv_init.c File Reference + + + + + +
+

edma3_drv_init.c File Reference

EDMA3 Driver Initialization Interface Implementation This file contains EDMA3 Driver APIs used to: a) Create/delete EDMA3 Driver Object b) Open/close EDMA3 Driver Instance. These APIs are required to initialize EDMA3 properly. More... +

+#include <ti/sdo/edma3/drv/src/edma3.h>
+#include <ti/sdo/edma3/rm/src/edma3ResMgr.h>
+#include <assert.h>
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Functions

void edma3MemSet (void *dst, unsigned char data, unsigned int len)
void edma3MemCpy (void *dst, const void *src, unsigned int len)
static EDMA3_DRV_Result edma3OpenResMgr (unsigned int instId, unsigned int regionId, unsigned short flag)
EDMA3_DRV_Result EDMA3_DRV_create (unsigned int phyCtrllerInstId, const EDMA3_DRV_GblConfigParams *gblCfgParams, const void *miscParam)
 Create EDMA3 Driver Object.
EDMA3_DRV_Result EDMA3_DRV_delete (unsigned int phyCtrllerInstId, const void *param)
 Delete EDMA3 Driver Object.
EDMA3_DRV_Handle EDMA3_DRV_open (unsigned int phyCtrllerInstId, const EDMA3_DRV_InitConfig *initCfg, EDMA3_DRV_Result *errorCode)
 Open EDMA3 Driver Instance.
EDMA3_DRV_Result EDMA3_DRV_close (EDMA3_DRV_Handle hEdma, const void *param)
 Close the EDMA3 Driver Instance.

Variables

const unsigned int EDMA3_MAX_RM_INSTANCES
EDMA3_RM_Obj resMgrObj [EDMA3_MAX_EDMA3_INSTANCES]
 EDMA3 Resource Manager Objects, tied to each EDMA3 HW Controller.
EDMA3_RM_InstanceInitConfig * ptrInitCfgArray
 Region Specific Configuration structure for EDMA3 controller, to provide region specific Information.
EDMA3_RM_Instance * ptrRMIArray
EDMA3_DRV_Object drvObj [EDMA3_MAX_EDMA3_INSTANCES]
 EDMA3 Driver Objects, tied to each EDMA3 HW Controller.
EDMA3_DRV_Instance drvInstance [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS]
EDMA3_DRV_ChBoundResources edma3DrvChBoundRes [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_LOGICAL_CH]
 Resources bound to a Channel.
+

Detailed Description

+EDMA3 Driver Initialization Interface Implementation This file contains EDMA3 Driver APIs used to: a) Create/delete EDMA3 Driver Object b) Open/close EDMA3 Driver Instance. These APIs are required to initialize EDMA3 properly. +

+

Author:
: PSP Team, TII
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void edma3MemCpy (void *  dst,
const void *  src,
unsigned int  len 
)
+
+
+ +

+Local MemCpy function +

+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void edma3MemSet (void *  dst,
unsigned char  data,
unsigned int  len 
)
+
+
+ +

+Local MemSet function +

+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
static EDMA3_DRV_Result edma3OpenResMgr (unsigned int  instId,
unsigned int  regionId,
unsigned short  flag 
) [static]
+
+
+ +

+Local function to prepare the init config structure for open of Resource Manager +

+User has passed the instance initialization specific info, which we have saved previously too, so use it.

+User has NOT passed the instance initialization specific info. Pass NULL to the Resource Manager.

+Save the RM Instance specific information in the driver. Earlier this was easier, now a bit tricky. Search for the RM instance number based on the handle just returned, to fetch the correct config info from the userInitConfig[]. +

References EDMA3_DRV_Instance::drvSemHandle, EDMA3_DRV_E_INVALID_PARAM, EDMA3_MAX_RM_INSTANCES, edma3MemCpy(), EDMA3_DRV_Instance::gblerrCbParams, EDMA3_DRV_Instance::isMaster, EDMA3_DRV_Instance::pDrvObjectHandle, ptrInitCfgArray, ptrRMIArray, and EDMA3_DRV_Instance::resMgrInstance.

+ +

Referenced by EDMA3_DRV_open().

+ +
+

+

Variable Documentation

+ +
+
+ + + + +
EDMA3_DRV_Instance drvInstance[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS]
+
+
+ +

+Handles of EDMA3 Driver Instances.

+Used to maintain information of the EDMA3 Driver Instances for each region, for each HW controller. There could be as many Driver Instances as there are shadow regions. Multiple EDMA3 Driver instances on the same shadow region are NOT allowed. +

+

+ +

+
+ + + + +
EDMA3_DRV_Object drvObj[EDMA3_MAX_EDMA3_INSTANCES]
+
+
+ +

+EDMA3 Driver Objects, tied to each EDMA3 HW Controller. +

+Typically one object will cater to one EDMA3 HW controller and will have all regions' (ARM, DSP etc) specific config information. +

+

+ +

+
+ + + + +
const unsigned int EDMA3_MAX_RM_INSTANCES
+
+
+ +

+Define NDEBUG to ignore assert(). NDEBUG should be defined before including assert.h header file. Maximum Resource Manager Instances supported by the EDMA3 Package. +

+

+ +

+
+ + + + +
EDMA3_DRV_ChBoundResources edma3DrvChBoundRes[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_LOGICAL_CH]
+
+
+ +

+Resources bound to a Channel. +

+When a request for a channel is made, the resources PaRAM Set and TCC get bound to that channel. This information is needed internally by the driver when a request is made to free the channel (Since it is the responsibility of the driver to free up the channel-associated resources from the Resource Manager layer). +

+

+ +

+
+ + + + +
EDMA3_RM_InstanceInitConfig* ptrInitCfgArray
+
+
+ +

+Region Specific Configuration structure for EDMA3 controller, to provide region specific Information. +

+This configuration info can also be provided by the user at run-time, while calling EDMA3_RM_open (). If not provided at run-time, this info will be taken from the config file "edma3_<PLATFORM_NAME>_cfg.c", for the specified platform. +

+

+ +

+
+ + + + +
EDMA3_RM_Instance* ptrRMIArray
+
+
+ +

+Handles of EDMA3 Resource Manager Instances.

+Used to maintain information of the EDMA3 RM Instances for each HW controller. There could be a maximum of EDMA3_MAX_RM_INSTANCES instances per EDMA3 HW. +

+

+ +

+
+ + + + +
EDMA3_RM_Obj resMgrObj[EDMA3_MAX_EDMA3_INSTANCES]
+
+
+ +

+EDMA3 Resource Manager Objects, tied to each EDMA3 HW Controller. +

+Typically one RM object will cater to one EDMA3 HW controller and will have all the global config information. +

+

+

+
Generated on Thu Oct 16 16:17:55 2008 for EDMA3 Driver by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/drv/docs/html/files.html b/packages/ti/sdo/edma3/drv/docs/html/files.html new file mode 100644 index 0000000..7598759 --- /dev/null +++ b/packages/ti/sdo/edma3/drv/docs/html/files.html @@ -0,0 +1,37 @@ + + +EDMA3 Driver: File Index + + + + + +
+

File List

Here is a list of all documented files with brief descriptions: + + + + + +
edma3.h [code]EDMA3 Driver Internal header file
edma3_drv.h [code]EDMA3 Controller
edma3_drv_adv.cEDMA3 Driver Advanced Interface Implementation This file contains advanced-level EDMA3 Driver APIs which are required to: a) Link and chain two channels. b) Set/get the whole PaRAM Set in one shot. c) Set/get each individual field of the PaRAM Set. d) Poll mode APIs. e) IOCTL interface. These APIs are provided to have complete control on the EDMA3 hardware and normally advanced users are expected to use them for their specific use-cases
edma3_drv_basic.cEDMA3 Driver Basic Interface Implementation This file contains beginner-level EDMA3 Driver APIs which are required to: a) Request/free a DMA, QDMA and Link channel. b) Program various fields in the PaRAM Set like source/destination parameters, transfer parameters etc. c) Enable/disable a transfer. These APIs are provided to program a DMA/QDMA channel for simple use-cases and don't expose all the features of EDMA3 hardware. Users who want to go beyond this and have complete control on the EDMA3 hardware are advised to refer edma3_drv_adv.c source file
edma3_drv_init.cEDMA3 Driver Initialization Interface Implementation This file contains EDMA3 Driver APIs used to: a) Create/delete EDMA3 Driver Object b) Open/close EDMA3 Driver Instance. These APIs are required to initialize EDMA3 properly
+
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+Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: +

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+Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: +

+

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+ + diff --git a/packages/ti/sdo/edma3/drv/docs/html/globals_0x70.html b/packages/ti/sdo/edma3/drv/docs/html/globals_0x70.html new file mode 100644 index 0000000..738c012 --- /dev/null +++ b/packages/ti/sdo/edma3/drv/docs/html/globals_0x70.html @@ -0,0 +1,60 @@ + + +EDMA3 Driver: Data Fields + + + + + +
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+Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: +

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Generated on Thu Oct 16 16:17:56 2008 for EDMA3 Driver by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/drv/docs/html/group__edma3drvchannelsetup.html b/packages/ti/sdo/edma3/drv/docs/html/group__edma3drvchannelsetup.html new file mode 100644 index 0000000..02a144f --- /dev/null +++ b/packages/ti/sdo/edma3/drv/docs/html/group__edma3drvchannelsetup.html @@ -0,0 +1,849 @@ + + +EDMA3 Driver: EDMA3 Driver Channel Setup + + + + + +
+

EDMA3 Driver Channel Setup
+ +[EDMA3 Driver Interface Definition] +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Defines

#define EDMA3_DRV_DMA_CHANNEL_ANY   1002u
#define EDMA3_DRV_QDMA_CHANNEL_ANY   1003u
#define EDMA3_DRV_TCC_ANY   1004u
#define EDMA3_DRV_LINK_CHANNEL   1005u
#define EDMA3_DRV_QDMA_CHANNEL_0   (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS)
 QDMA Channel defines They should be used while requesting a specific QDMA channel.
#define EDMA3_DRV_QDMA_CHANNEL_1   (EDMA3_DRV_QDMA_CHANNEL_0+1u)
#define EDMA3_DRV_QDMA_CHANNEL_2   (EDMA3_DRV_QDMA_CHANNEL_0+2u)
#define EDMA3_DRV_QDMA_CHANNEL_3   (EDMA3_DRV_QDMA_CHANNEL_0+3u)
#define EDMA3_DRV_QDMA_CHANNEL_4   (EDMA3_DRV_QDMA_CHANNEL_0+4u)
#define EDMA3_DRV_QDMA_CHANNEL_5   (EDMA3_DRV_QDMA_CHANNEL_0+5u)
#define EDMA3_DRV_QDMA_CHANNEL_6   (EDMA3_DRV_QDMA_CHANNEL_0+6u)
#define EDMA3_DRV_QDMA_CHANNEL_7   (EDMA3_DRV_QDMA_CHANNEL_0+7u)

Enumerations

enum  EDMA3_DRV_HW_CHANNEL_EVENT {
+  EDMA3_DRV_HW_CHANNEL_EVENT_0 = 0, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_1, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_2, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_3, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_4, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_5, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_6, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_7, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_8, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_9, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_10, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_11, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_12, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_13, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_14, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_15, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_16, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_17, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_18, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_19, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_20, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_21, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_22, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_23, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_24, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_25, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_26, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_27, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_28, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_29, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_30, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_31, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_32, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_33, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_34, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_35, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_36, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_37, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_38, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_39, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_40, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_41, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_42, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_43, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_44, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_45, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_46, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_47, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_48, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_49, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_50, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_51, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_52, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_53, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_54, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_55, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_56, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_57, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_58, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_59, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_60, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_61, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_62, +
+  EDMA3_DRV_HW_CHANNEL_EVENT_63 +
+ }
 DMA Channels assigned to different Hardware Events. They should be used while requesting a specific DMA channel. One possible usage is to maintain a SoC specific file, which will contain the mapping of these hardware events to the respective peripherals for better understanding and lesser probability of errors. Also, if any event associated with a particular peripheral gets changed, only that SoC specific file needs to be changed. More...

Functions

EDMA3_DRV_Result EDMA3_DRV_requestChannel (EDMA3_DRV_Handle hEdma, unsigned int *pLCh, unsigned int *pTcc, EDMA3_RM_EventQueue evtQueue, EDMA3_RM_TccCallback tccCb, void *cbData)
 Request a DMA/QDMA/Link channel.
EDMA3_DRV_Result EDMA3_DRV_freeChannel (EDMA3_DRV_Handle hEdma, unsigned int channelId)
 Free the specified channel (DMA/QDMA/Link) and its associated resources (PaRAM Set, TCC etc) and removes various mappings.
EDMA3_DRV_Result EDMA3_DRV_clearErrorBits (EDMA3_DRV_Handle hEdma, unsigned int channelId)
 Clears Event Register and Error Register for a specific DMA channel and brings back EDMA3 to its initial state.
EDMA3_DRV_Result EDMA3_DRV_linkChannel (EDMA3_DRV_Handle hEdma, unsigned int lCh1, unsigned int lCh2)
 Link two logical channels.
EDMA3_DRV_Result EDMA3_DRV_unlinkChannel (EDMA3_DRV_Handle hEdma, unsigned int lCh)
 Unlink the channel from the earlier linked logical channel.
+

Detailed Description

+Channel related Interface of the EDMA3 Driver

Define Documentation

+ +
+
+ + + + +
#define EDMA3_DRV_DMA_CHANNEL_ANY   1002u
+
+
+ +

+Used to specify any available DMA Channel while requesting one. Used in the API EDMA3_DRV_requestChannel(). DMA channel from the pool of (owned && non_reserved && available_right_now) DMA channels will be chosen and returned. +

Referenced by EDMA3_DRV_requestChannel().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_LINK_CHANNEL   1005u
+
+
+ +

+Used to specify any available PaRAM Set while requesting one. Used in the API EDMA3_DRV_requestChannel(), for Link channels. PaRAM Set from the pool of (owned && non_reserved && available_right_now) PaRAM Sets will be chosen and returned. +

Referenced by EDMA3_DRV_requestChannel().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_QDMA_CHANNEL_0   (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS)
+
+
+ +

+QDMA Channel defines They should be used while requesting a specific QDMA channel. +

+QDMA Channel 0 +

Referenced by EDMA3_DRV_setPaRAMField().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_QDMA_CHANNEL_1   (EDMA3_DRV_QDMA_CHANNEL_0+1u)
+
+
+ +

+QDMA Channel 1 +

+

+ +

+
+ + + + +
#define EDMA3_DRV_QDMA_CHANNEL_2   (EDMA3_DRV_QDMA_CHANNEL_0+2u)
+
+
+ +

+QDMA Channel 2 +

+

+ +

+
+ + + + +
#define EDMA3_DRV_QDMA_CHANNEL_3   (EDMA3_DRV_QDMA_CHANNEL_0+3u)
+
+
+ +

+QDMA Channel 3 +

+

+ +

+
+ + + + +
#define EDMA3_DRV_QDMA_CHANNEL_4   (EDMA3_DRV_QDMA_CHANNEL_0+4u)
+
+
+ +

+QDMA Channel 4 +

+

+ +

+
+ + + + +
#define EDMA3_DRV_QDMA_CHANNEL_5   (EDMA3_DRV_QDMA_CHANNEL_0+5u)
+
+
+ +

+QDMA Channel 5 +

+

+ +

+
+ + + + +
#define EDMA3_DRV_QDMA_CHANNEL_6   (EDMA3_DRV_QDMA_CHANNEL_0+6u)
+
+
+ +

+QDMA Channel 6 +

+

+ +

+
+ + + + +
#define EDMA3_DRV_QDMA_CHANNEL_7   (EDMA3_DRV_QDMA_CHANNEL_0+7u)
+
+
+ +

+QDMA Channel 7 +

Referenced by EDMA3_DRV_setPaRAMField().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_QDMA_CHANNEL_ANY   1003u
+
+
+ +

+Used to specify any available QDMA Channel while requesting one. Used in the API EDMA3_DRV_requestChannel(). QDMA channel from the pool of (owned && non_reserved && available_right_now) QDMA channels will be chosen and returned. +

Referenced by EDMA3_DRV_requestChannel().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_TCC_ANY   1004u
+
+
+ +

+Used to specify any available TCC while requesting one. Used in the API EDMA3_DRV_requestChannel(), for both DMA and QDMA channels. TCC from the pool of (owned && non_reserved && available_right_now) TCCs will be chosen and returned. +

Referenced by EDMA3_DRV_requestChannel().

+ +
+

+

Enumeration Type Documentation

+ +
+
+ + + + +
enum EDMA3_DRV_HW_CHANNEL_EVENT
+
+
+ +

+DMA Channels assigned to different Hardware Events. They should be used while requesting a specific DMA channel. One possible usage is to maintain a SoC specific file, which will contain the mapping of these hardware events to the respective peripherals for better understanding and lesser probability of errors. Also, if any event associated with a particular peripheral gets changed, only that SoC specific file needs to be changed. +

+for eg, the sample SoC specific file "soc.h" can have these defines:

+define EDMA3_DRV_HW_CHANNEL_MCBSP_TX EDMA3_DRV_HW_CHANNEL_EVENT_2 define EDMA3_DRV_HW_CHANNEL_MCBSP_RX EDMA3_DRV_HW_CHANNEL_EVENT_3

+These defines will be used by the MCBSP driver. The same event EDMA3_DRV_HW_CHANNEL_EVENT_2/3 could be mapped to some other peripheral also.

Enumerator:
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_DRV_HW_CHANNEL_EVENT_0  +Channel assigned to EDMA3 Event 0
EDMA3_DRV_HW_CHANNEL_EVENT_1  +Channel assigned to EDMA3 Event 1
EDMA3_DRV_HW_CHANNEL_EVENT_2  +Channel assigned to EDMA3 Event 2
EDMA3_DRV_HW_CHANNEL_EVENT_3  +Channel assigned to EDMA3 Event 3
EDMA3_DRV_HW_CHANNEL_EVENT_4  +Channel assigned to EDMA3 Event 4
EDMA3_DRV_HW_CHANNEL_EVENT_5  +Channel assigned to EDMA3 Event 5
EDMA3_DRV_HW_CHANNEL_EVENT_6  +Channel assigned to EDMA3 Event 6
EDMA3_DRV_HW_CHANNEL_EVENT_7  +Channel assigned to EDMA3 Event 7
EDMA3_DRV_HW_CHANNEL_EVENT_8  +Channel assigned to EDMA3 Event 8
EDMA3_DRV_HW_CHANNEL_EVENT_9  +Channel assigned to EDMA3 Event 9
EDMA3_DRV_HW_CHANNEL_EVENT_10  +Channel assigned to EDMA3 Event 10
EDMA3_DRV_HW_CHANNEL_EVENT_11  +Channel assigned to EDMA3 Event 11
EDMA3_DRV_HW_CHANNEL_EVENT_12  +Channel assigned to EDMA3 Event 12
EDMA3_DRV_HW_CHANNEL_EVENT_13  +Channel assigned to EDMA3 Event 13
EDMA3_DRV_HW_CHANNEL_EVENT_14  +Channel assigned to EDMA3 Event 14
EDMA3_DRV_HW_CHANNEL_EVENT_15  +Channel assigned to EDMA3 Event 15
EDMA3_DRV_HW_CHANNEL_EVENT_16  +Channel assigned to EDMA3 Event 16
EDMA3_DRV_HW_CHANNEL_EVENT_17  +Channel assigned to EDMA3 Event 17
EDMA3_DRV_HW_CHANNEL_EVENT_18  +Channel assigned to EDMA3 Event 18
EDMA3_DRV_HW_CHANNEL_EVENT_19  +Channel assigned to EDMA3 Event 19
EDMA3_DRV_HW_CHANNEL_EVENT_20  +Channel assigned to EDMA3 Event 20
EDMA3_DRV_HW_CHANNEL_EVENT_21  +Channel assigned to EDMA3 Event 21
EDMA3_DRV_HW_CHANNEL_EVENT_22  +Channel assigned to EDMA3 Event 22
EDMA3_DRV_HW_CHANNEL_EVENT_23  +Channel assigned to EDMA3 Event 23
EDMA3_DRV_HW_CHANNEL_EVENT_24  +Channel assigned to EDMA3 Event 24
EDMA3_DRV_HW_CHANNEL_EVENT_25  +Channel assigned to EDMA3 Event 25
EDMA3_DRV_HW_CHANNEL_EVENT_26  +Channel assigned to EDMA3 Event 26
EDMA3_DRV_HW_CHANNEL_EVENT_27  +Channel assigned to EDMA3 Event 27
EDMA3_DRV_HW_CHANNEL_EVENT_28  +Channel assigned to EDMA3 Event 28
EDMA3_DRV_HW_CHANNEL_EVENT_29  +Channel assigned to EDMA3 Event 29
EDMA3_DRV_HW_CHANNEL_EVENT_30  +Channel assigned to EDMA3 Event 30
EDMA3_DRV_HW_CHANNEL_EVENT_31  +Channel assigned to EDMA3 Event 31
EDMA3_DRV_HW_CHANNEL_EVENT_32  +Channel assigned to EDMA3 Event 32
EDMA3_DRV_HW_CHANNEL_EVENT_33  +Channel assigned to EDMA3 Event 33
EDMA3_DRV_HW_CHANNEL_EVENT_34  +Channel assigned to EDMA3 Event 34
EDMA3_DRV_HW_CHANNEL_EVENT_35  +Channel assigned to EDMA3 Event 35
EDMA3_DRV_HW_CHANNEL_EVENT_36  +Channel assigned to EDMA3 Event 36
EDMA3_DRV_HW_CHANNEL_EVENT_37  +Channel assigned to EDMA3 Event 37
EDMA3_DRV_HW_CHANNEL_EVENT_38  +Channel assigned to EDMA3 Event 38
EDMA3_DRV_HW_CHANNEL_EVENT_39  +Channel assigned to EDMA3 Event 39
EDMA3_DRV_HW_CHANNEL_EVENT_40  +Channel assigned to EDMA3 Event 40
EDMA3_DRV_HW_CHANNEL_EVENT_41  +Channel assigned to EDMA3 Event 41
EDMA3_DRV_HW_CHANNEL_EVENT_42  +Channel assigned to EDMA3 Event 42
EDMA3_DRV_HW_CHANNEL_EVENT_43  +Channel assigned to EDMA3 Event 43
EDMA3_DRV_HW_CHANNEL_EVENT_44  +Channel assigned to EDMA3 Event 44
EDMA3_DRV_HW_CHANNEL_EVENT_45  +Channel assigned to EDMA3 Event 45
EDMA3_DRV_HW_CHANNEL_EVENT_46  +Channel assigned to EDMA3 Event 46
EDMA3_DRV_HW_CHANNEL_EVENT_47  +Channel assigned to EDMA3 Event 47
EDMA3_DRV_HW_CHANNEL_EVENT_48  +Channel assigned to EDMA3 Event 48
EDMA3_DRV_HW_CHANNEL_EVENT_49  +Channel assigned to EDMA3 Event 49
EDMA3_DRV_HW_CHANNEL_EVENT_50  +Channel assigned to EDMA3 Event 50
EDMA3_DRV_HW_CHANNEL_EVENT_51  +Channel assigned to EDMA3 Event 51
EDMA3_DRV_HW_CHANNEL_EVENT_52  +Channel assigned to EDMA3 Event 52
EDMA3_DRV_HW_CHANNEL_EVENT_53  +Channel assigned to EDMA3 Event 53
EDMA3_DRV_HW_CHANNEL_EVENT_54  +Channel assigned to EDMA3 Event 54
EDMA3_DRV_HW_CHANNEL_EVENT_55  +Channel assigned to EDMA3 Event 55
EDMA3_DRV_HW_CHANNEL_EVENT_56  +Channel assigned to EDMA3 Event 56
EDMA3_DRV_HW_CHANNEL_EVENT_57  +Channel assigned to EDMA3 Event 57
EDMA3_DRV_HW_CHANNEL_EVENT_58  +Channel assigned to EDMA3 Event 58
EDMA3_DRV_HW_CHANNEL_EVENT_59  +Channel assigned to EDMA3 Event 59
EDMA3_DRV_HW_CHANNEL_EVENT_60  +Channel assigned to EDMA3 Event 60
EDMA3_DRV_HW_CHANNEL_EVENT_61  +Channel assigned to EDMA3 Event 61
EDMA3_DRV_HW_CHANNEL_EVENT_62  +Channel assigned to EDMA3 Event 62
EDMA3_DRV_HW_CHANNEL_EVENT_63  +Channel assigned to EDMA3 Event 63
+
+ +
+

+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Result EDMA3_DRV_clearErrorBits (EDMA3_DRV_Handle  hEdma,
unsigned int  channelId 
)
+
+
+ +

+Clears Event Register and Error Register for a specific DMA channel and brings back EDMA3 to its initial state. +

+This API clears the Event register, Event Miss register Event Enable register for a specific DMA channel. It also clears the CC Error register.

+

Parameters:
+ + + +
hEdma [IN] Handle to the EDMA Driver Instance.
channelId [IN] DMA Channel needs to be cleaned.
+
+
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error code
+
Note:
This function is re-entrant for unique channelId values. It is non- re-entrant for same channelId value.
+ +

References EDMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numEvtQueue, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Instance::shadowRegs.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Result EDMA3_DRV_freeChannel (EDMA3_DRV_Handle  hEdma,
unsigned int  channelId 
)
+
+
+ +

+Free the specified channel (DMA/QDMA/Link) and its associated resources (PaRAM Set, TCC etc) and removes various mappings. +

+This API internally uses EDMA3_RM_freeResource () to free the desired resources.

+For Link channels, this API only frees the associated PaRAM Set.

+For DMA/QDMA channels, it does the following operations: a) Disable any ongoing transfer on the channel, b) Unregister the TCC Callback function and disable the interrupts, c) Remove the channel to Event Queue mapping, d) For DMA channels, clear the DCHMAP register, if available e) For QDMA channels, clear the QCHMAP register, f) Frees the DMA/QDMA channel in the end.

+

Parameters:
+ + + +
hEdma [IN] Handle to the EDMA Driver Instance.
channelId [IN] Logical Channel number to be freed.
+
+
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error code
+
Note:
This function disables the global interrupts while modifying the global CC registers and while modifying global data structures, to prevent simultaneous access to the global pool of resources. It internally calls EDMA3_RM_freeResource () for resource de-allocation. It is re-entrant.
+ +

References EDMA3_DRV_CHANNEL_TYPE_DMA, EDMA3_DRV_CHANNEL_TYPE_LINK, EDMA3_DRV_CHANNEL_TYPE_NONE, EDMA3_DRV_CHANNEL_TYPE_QDMA, EDMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LINK_CH_MAX_VAL, EDMA3_DRV_LINK_CH_MIN_VAL, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, edma3RemoveMapping(), EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_GblConfigParams::numTccs, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, EDMA3_DRV_Object::phyCtrllerInstId, EDMA3_DRV_Instance::resMgrInstance, and EDMA3_DRV_ChBoundResources::tcc.

+ +

Referenced by EDMA3_DRV_requestChannel().

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Result EDMA3_DRV_linkChannel (EDMA3_DRV_Handle  hEdma,
unsigned int  lCh1,
unsigned int  lCh2 
)
+
+
+ +

+Link two logical channels. +

+This API is used to link two previously allocated logical (DMA/QDMA/Link) channels.

+It sets the Link field of the PaRAM set associated with first logical channel (lCh1) to point it to the PaRAM set associated with second logical channel (lCh2).

+It also sets the TCC field of PaRAM set associated with second logical channel to the same as that of the first logical channel.

+After linking the channels, user should not update any PaRAM Set of the channel.

+

Parameters:
+ + + + +
hEdma [IN] Handle to the EDMA Driver Instance.
lCh1 [IN] Logical Channel to which particular channel will be linked.
lCh2 [IN] Logical Channel which needs to be linked to the first channel. After the transfer based on the PaRAM set of lCh1 is over, the PaRAM set of lCh2 will be copied to the PaRAM set of lCh1 and transfer will resume. For DMA channels, another sync event is required to initiate the transfer on the Link channel.
+
+
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
+
Note:
This function is re-entrant for unique lCh1 & lCh2 values. It is non-re-entrant for same lCh1 & lCh2 values.
+ +

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_OPT_TCC_CLR_MASK, EDMA3_DRV_OPT_TCC_GET_MASK, EDMA3_DRV_OPT_TCC_SET_MASK, EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Result EDMA3_DRV_requestChannel (EDMA3_DRV_Handle  hEdma,
unsigned int *  pLCh,
unsigned int *  pTcc,
EDMA3_RM_EventQueue  evtQueue,
EDMA3_RM_TccCallback  tccCb,
void *  cbData 
)
+
+
+ +

+Request a DMA/QDMA/Link channel. +

+Each channel (DMA/QDMA/Link) must be requested before initiating a DMA transfer on that channel.

+This API is used to allocate a logical channel (DMA/QDMA/Link) along with the associated resources. For DMA and QDMA channels, TCC and PaRAM Set are also allocated along with the requested channel. For Link channel, ONLY a PaRAM Set is allocated.

+User can request a specific logical channel by passing the channel id in 'pLCh'. Note that the channel id is the same as the actual resource id in case of DMA channels. To allocate specific QDMA channels, user SHOULD use the defines EDMA3_DRV_QDMA_CHANNEL_X mentioned above.

+User can also request ANY available logical channel also by specifying the below mentioned values in '*pLCh': a) EDMA3_DRV_DMA_CHANNEL_ANY: For DMA channels b) EDMA3_DRV_QDMA_CHANNEL_ANY: For QDMA channels, and c) EDMA3_DRV_LINK_CHANNEL: For Link channels. Normally user should use this value to request link channels (PaRAM Sets used for linking purpose only), unless he wants to use some specific link channels (PaRAM Sets) which is also allowed.

+This API internally uses EDMA3_RM_allocResource () to allocate the desired resources (DMA/QDMA channel, PaRAM Set and TCC).

+This API also registers a specific callback function against the allocated TCC.

+For DMA/QDMA channels, after allocating all the EDMA3 resources, this API sets the TCC field of the OPT PaRAM Word with the allocated TCC. It also sets the event queue for the channel allocated. The event queue needs to be specified by the user.

+For DMA channel, it also sets the DCHMAP register, if required.

+For QDMA channel, it sets the QCHMAP register and CCNT as trigger word and enables the QDMA channel by writing to the QEESR register.

+

Parameters:
+ + + +
hEdma [IN] Handle to the previously opened Driver Instance.
pLCh [IN/OUT] Requested logical channel id. Examples:
    +
  • EDMA3_DRV_HW_CHANNEL_EVENT_0
  • To request a DMA Master Channel mapped to EDMA Event 0.
+
+
+
    +
  • EDMA3_DRV_DMA_CHANNEL_ANY
  • For requesting any DMA Master channel with no event mapping.
+

+

    +
  • EDMA3_DRV_QDMA_CHANNEL_ANY
  • For requesting any QDMA Master channel
+

+

    +
  • EDMA3_DRV_QDMA_CHANNEL_0
  • For requesting the QDMA Channel 0.
+

+

    +
  • EDMA3_DRV_LINK_CHANNEL
  • For requesting a DMA Slave Channel,
  • to be linked to some other Master
  • channel.
+

+In case user passes a specific channel Id, pLCh value is left unchanged. In case user requests ANY available resource, the allocated channel id is returned in pLCh.

+

Note:
To request a PaRAM Set for the purpose of linking to another channel, call the function with
+*pLCh = EDMA3_DRV_LINK_CHANNEL;

+This function will update *pLCh with the allocated Link channel handle. This handle could be DIFFERENT from the actual PaRAM Set allocated by the Resource Manager internally. So user SHOULD NOT assume the handle as the PaRAM Set Id.

+

Parameters:
+ + +
pTcc [IN/OUT] The channel number on which the completion/error interrupt is generated. Not used if user requested for a Link channel. Examples:
    +
  • EDMA3_DRV_HW_CHANNEL_EVENT_0
  • To request TCC associated with
  • DMA Master Channel mapped to EDMA
  • event 0.
+
+
+
    +
  • EDMA3_DRV_TCC_ANY
  • For requesting any TCC with no
  • channel mapping. In case user passes a specific TCC value, pTcc value is left unchanged. In case user requests ANY available TCC, the allocated one is returned in pTcc
+

+

Parameters:
+ + + + +
evtQueue [IN] Event Queue Number to which the channel will be mapped (valid only for the Master Channel (DMA/QDMA) request)
tccCb [IN] TCC callback - caters to channel- specific events like "Event Miss Error" or "Transfer Complete"
cbData [IN] Data which will be passed directly to the tccCb callback function
+
+
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error code
+
Note:
This function internally uses EDMA3 Resource Manager, which acquires a RM Instance specific semaphore to prevent simultaneous access to the global pool of resources. It also disables the global interrupts while modifying the global CC registers. It is re-entrant, but SHOULD NOT be called from the user callback function (ISR context).
+ +

+Fill the resource id, whose associated TCC needs to be registered. For QDMA channels, pass the actual QDMA channel no instead of (*pLCh).

+Map the allocated PaRAM Set to the logical DMa/QDMA channel.

+First check whether the mapping feature is supported on the underlying platform. In case it is not supported, dont call this API, because this API returns error in case the feature is not there. +

References EDMA3_DRV_GblConfigParams::dmaChannelPaRAMMap, EDMA3_DRV_GblConfigParams::dmaChannelTccMap, EDMA3_DRV_GblConfigParams::dmaChPaRAMMapExists, EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CHANNEL_TYPE_DMA, EDMA3_DRV_CHANNEL_TYPE_QDMA, EDMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_DMA_CHANNEL_ANY, EDMA3_DRV_DMAQNUM_CLR_MASK, EDMA3_DRV_DMAQNUM_SET_MASK, EDMA3_DRV_E_CH_PARAM_BIND_FAIL, EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL, EDMA3_DRV_E_TCC_REGISTER_FAIL, EDMA3_DRV_E_TCC_UNAVAIL, EDMA3_DRV_freeChannel(), EDMA3_DRV_LINK_CH_MAX_VAL, EDMA3_DRV_LINK_CH_MIN_VAL, EDMA3_DRV_LINK_CHANNEL, EDMA3_DRV_OPT_TCC_CLR_MASK, EDMA3_DRV_OPT_TCC_SET_MASK, EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD, EDMA3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_QDMA_CHANNEL_ANY, EDMA3_DRV_QDMAQNUM_CLR_MASK, EDMA3_DRV_QDMAQNUM_SET_MASK, EDMA3_DRV_TCC_ANY, EDMA3_DRV_TRIG_MODE_NONE, EDMA3_DRV_TRIG_MODE_QDMA, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numDmaChannels, EDMA3_DRV_GblConfigParams::numEvtQueue, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, EDMA3_DRV_Object::phyCtrllerInstId, EDMA3_DRV_Instance::resMgrInstance, EDMA3_DRV_Instance::shadowRegs, EDMA3_DRV_ChBoundResources::tcc, and EDMA3_DRV_ChBoundResources::trigMode.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Result EDMA3_DRV_unlinkChannel (EDMA3_DRV_Handle  hEdma,
unsigned int  lCh 
)
+
+
+ +

+Unlink the channel from the earlier linked logical channel. +

+This function breaks the link between the specified channel and the earlier linked logical channel by clearing the Link Address field.

+

Parameters:
+ + + +
hEdma [IN] Handle to the EDMA Driver Instance.
lCh [IN] Channel for which linking has to be removed
+
+
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
+
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.
+ +

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

+ +
+

+

+
Generated on Thu Oct 16 16:17:55 2008 for EDMA3 Driver by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/drv/docs/html/group__edma3drverrorcode.html b/packages/ti/sdo/edma3/drv/docs/html/group__edma3drverrorcode.html new file mode 100644 index 0000000..bd8c83e --- /dev/null +++ b/packages/ti/sdo/edma3/drv/docs/html/group__edma3drverrorcode.html @@ -0,0 +1,556 @@ + + +EDMA3 Driver: EDMA3 Driver Error Codes + + + + + +
+

EDMA3 Driver Error Codes
+ +[EDMA3 Driver Interface Definition] +

Usage of EDMA3 Driver. +More... + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Defines

#define EDMA3_DRV_E_BASE   (-128)
#define EDMA3_DRV_E_OBJ_NOT_DELETED   (EDMA3_DRV_E_BASE)
#define EDMA3_DRV_E_OBJ_NOT_CLOSED   (EDMA3_DRV_E_BASE-1)
#define EDMA3_DRV_E_OBJ_NOT_OPENED   (EDMA3_DRV_E_BASE-2)
#define EDMA3_DRV_E_RM_CLOSE_FAIL   (EDMA3_DRV_E_BASE-3)
#define EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL   (EDMA3_DRV_E_BASE-4)
#define EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL   (EDMA3_DRV_E_BASE-5)
#define EDMA3_DRV_E_PARAM_SET_UNAVAIL   (EDMA3_DRV_E_BASE-6)
#define EDMA3_DRV_E_TCC_UNAVAIL   (EDMA3_DRV_E_BASE-7)
#define EDMA3_DRV_E_TCC_REGISTER_FAIL   (EDMA3_DRV_E_BASE-8)
#define EDMA3_DRV_E_CH_PARAM_BIND_FAIL   (EDMA3_DRV_E_BASE-9)
#define EDMA3_DRV_E_ADDRESS_NOT_ALIGNED   (EDMA3_DRV_E_BASE-10)
#define EDMA3_DRV_E_INVALID_PARAM   (EDMA3_DRV_E_BASE-11)
#define EDMA3_DRV_E_INVALID_STATE   (EDMA3_DRV_E_BASE-12)
#define EDMA3_DRV_E_INST_ALREADY_EXISTS   (EDMA3_DRV_E_BASE-13)
#define EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED   (EDMA3_DRV_E_BASE-14)
#define EDMA3_DRV_E_SEMAPHORE   (EDMA3_DRV_E_BASE-15)
#define EDMA3_DRV_E_INST_NOT_OPENED   (EDMA3_DRV_E_BASE-16)
+

Detailed Description

+Usage of EDMA3 Driver. +

+

    +
  1. Create EDMA3 Driver Object (one for each EDMA3 hardware instance)
      +
    • EDMA3_DRV_Result result = EDMA3_DRV_SOK;
    • unsigned int edma3HwInstanceId = 0;
    • EDMA3_DRV_GblConfigParams *gblCfgParams = NULL;
    • Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. This could be NULL also. In that case, static configuration will be taken.
    • result = EDMA3_DRV_create (edma3HwInstanceId, gblCfgParams, NULL);
    +
+

+

    +
  1. Open EDMA3 driver Instance
      +
    • Steps
        +
      • EDMA3_DRV_InitConfig initCfg;
      • EDMA3_DRV_Handle hEdma = NULL;
      • EDMA3_OS_SemAttrs semAttrs = {EDMA3_OS_SEMTYPE_FIFO, NULL};
      • EDMA3_DRV_Result edmaResult; -To get the error code while opening driver instance
      +
    +
+

+

    +
  1. initCfg.regionId = One of the possible regions available for eg, (EDMA3_RM_RegionId)0 or (EDMA3_RM_RegionId)1 etc, for different masters.
+

+

    +
  1. initCfg.isMaster = TRUE/FALSE (Whether this EDMA3 DRV instance is Master or not. The EDMA3 Shadow Region tied to the Master DRV Instance will ONLY receive the EDMA3 interrupts (error or completion), if enabled).
+

+

    +
  1. initCfg.drvSemHandle = EDMA3 DRV Instance specific semaphore handle. It should be provided by the user for proper sharing of resources.
      +
    • edma3Result = edma3OsSemCreate(1, &semAttrs, &initCfg.drvSemHandle);
    +
+

+

    +
  1. initCfg.drvInstInitConfig = Init-time Region Specific Configuration Structure. It can be provided by the user at run-time. If not provided by the user, this info would be taken from the platform specific config file, if it exists.
+

+

    +
  1. initCfg.drvInstInitConfig->ownDmaChannels[] = The bitmap(s) which indicate the DMA channels owned by this instance of the EDMA3 Driver
    + E.g. A '1' at bit position 24 indicates that this instance of the EDMA3 Driver owns DMA Channel Id 24
    + Later when a request is made based on a particular Channel Id, the EDMA3 Driver will check first if it owns that channel. If it doesnot own it, EDMA3 Driver returns error.
  2. initCfg.drvInstInitConfig->ownQdmaChannels[] = The bitmap(s) which indicate the QDMA channels owned by this instance of the EDMA3 Driver
    +
  3. initCfg.drvInstInitConfig->ownPaRAMSets[] = The bitmap(s) which indicate the PaRAM Sets owned by this instance of the EDMA3 Driver
    +
  4. initCfg.drvInstInitConfig->ownTccs[] = The bitmap(s) which indicate the TCCs owned by this instance of the EDMA3 Driver
    +
+

+

    +
  1. initCfg.drvInstInitConfig->resvdDmaChannels[] = The bitmap(s) which indicate the DMA channels reserved by this instance of the EDMA3 Driver
    + E.g. A '1' at bit position 24 indicates that this instance of the EDMA3 Driver reserves Channel Id 24
    + These channels are reserved and may be mapped to HW events, these are not given to 'EDMA3_DRV_DMA_CHANNEL_ANY' requests.
    +
  2. initCfg.drvInstInitConfig->resvdQdmaChannels[] = The bitmap(s) which indicate the QDMA channels reserved by this instance of the EDMA3 Driver
    + E.g. A '1' at bit position 1 indicates that this instance of the EDMA3 Driver reserves QDMA Channel Id 1
    + These channels are reserved for some specific purpose, these are not given to 'EDMA3_DRV_QDMA_CHANNEL_ANY' request
    +
  3. initCfg.drvInstInitConfig->resvdPaRAMSets[] = PaRAM Sets which are reserved by this Region;
  4. initCfg.drvInstInitConfig->resvdTccs[] = TCCs which are reserved by this Region;
+

+

    +
  1. initCfg.gblerrCb = Instance wide callback function to catch non-channel specific errors;
  2. initCfg.gblerrData = Application data to be passed back to the callback function;
+

+

    +
  1. hEdma = EDMA3_DRV_open(edma3HwInstanceId, &initCfg, &edmaResult);
+

+

    +
  1. EDMA3 driver APIs
      +
    • EDMA3_RM_ResDesc resObj;
    • EDMA3_DRV_Result result;
    • unsigned int ch1Id = 0;
    • unsigned int ch2Id = 0;
    • unsigned int tcc1 = 0;
    • unsigned int tcc2 = 0;
    • unsigned int qCh1Id = 0;
    • unsigned int qTcc1 = 0;
    • unsigned int qCh2Id = 0;
    • unsigned int qTcc2 = 0;
    • unsigned int paRAMId;
    • int srcbidx = 0;
    • int desbidx = 0;
    • int srccidx = 0;
    • int descidx = 0;
    • unsigned int acnt = 0;
    • unsigned int bcnt = 0;
    • unsigned int ccnt = 0;
    • unsigned int bcntreload = 0;
    • EDMA3_DRV_SyncType synctype;
    • EDMA3_RM_TccCallback tccCb;
    • void *cbData;
    • Use Case 1: Memory to memory transfer on any available
    • DMA Channel
      +
      +
        +
      • tcc1 = EDMA3_DRV_TCC_ANY;
      • ch1Id = EDMA3_DRV_DMA_CHANNEL_ANY;
      • result = EDMA3_DRV_requestChannel (hEdma, &ch1Id, &tcc1, (EDMA3_RM_EventQueue)0, &callback1, NULL);
      +
    +
+

+

    +
  • result = EDMA3_DRV_setSrcParams (hEdma, ch1Id, (unsigned int)(srcBuff1), EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_W8BIT);
  • result = EDMA3_DRV_setDestParams (hEdma, ch1Id, (unsigned int)(dstBuff1), EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_W8BIT);
+

+

    +
  • Set EDMA transfer parameters (aCnt, bCnt, cCnt, bCntReload, SyncType) acnt = 256; bcnt = 1; ccnt = 1, bcntreload = 0; synctype = EDMA3_DRV_SYNC_A;
  • result = EDMA3_DRV_setTransferParams (hEdma, ch1Id, acnt, bcnt, ccnt, bcntreload, synctype);
+

+

    +
  • Set srcbidx and srccidx to the appropriate values
  • srcbidx = acnt; srccidx = acnt;
  • result = EDMA3_DRV_setSrcIndex (hEdma, ch1Id, srcbidx, srccidx);
+

+

    +
  • Set desbidx and descidx to the appropriate values
  • desbidx = acnt; descidx = acnt;
  • result = EDMA3_DRV_setDestIndex (hEdma, ch1Id, desbidx, descidx);
+

+

    +
  • Enable the final completion interrupt.
  • result = EDMA3_DRV_setOptField (hEdma, ch1Id, EDMA3_DRV_OPT_FIELD_TCINTEN, 1);
+

+

    +
  • Enable the transfer
  • result = EDMA3_DRV_enableTransfer (hEdma, ch1Id, EDMA3_DRV_TRIG_MODE_MANUAL);
+

+

    +
  • Use Case 2: Linked memory to memory transfer on any available
  • DMA Channel
    +
    +
      +
    • Perform steps as for Use Case 1 for the Master logical channel ch1Id for configuration. DONOT enable the transfer for ch1Id.
    • Configure link channel, ch2Id.
    • tcc2 = EDMA3_DRV_TCC_ANY;
    • ch2Id = EDMA3_DRV_LINK_CHANNEL;
    • result = EDMA3_DRV_requestChannel (hEdma, &ch2Id, &tcc2, (EDMA3_RM_EventQueue)0, &callback2, NULL);
    +
+

+

    +
  • result = EDMA3_DRV_setSrcParams (hEdma, ch2Id, (unsigned int)(srcBuff2), EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_W8BIT);
  • result = EDMA3_DRV_setDestParams (hEdma, ch2Id,( unsigned int)(dstBuff2), EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_W8BIT);
+

+

    +
  • result = EDMA3_DRV_setSrcIndex (hEdma, ch2Id, srcbidx, srccidx);
  • result = EDMA3_DRV_setDestIndex (hEdma, ch2Id, desbidx, descidx);
+

+

    +
  • result = EDMA3_DRV_setTransferParams (hEdma, ch2Id, acnt, bcnt, ccnt, bcntreload, synctype);
+

+

    +
  • Link both the channels
  • result = EDMA3_DRV_linkChannel (hEdma, ch1Id, ch2Id);
+

+

    +
  • Enable the final completion interrupts on both the channels
  • result = EDMA3_DRV_setOptField (hEdma, ch1Id, EDMA3_DRV_OPT_FIELD_TCINTEN, 1);
  • result = EDMA3_DRV_setOptField (hEdma, ch2Id, EDMA3_DRV_OPT_FIELD_TCINTEN, 1);
+

+

    +
  • Enable the transfer on channel 1.
  • result = EDMA3_DRV_enableTransfer (hEdma, ch1Id, EDMA3_DRV_TRIG_MODE_MANUAL);
  • Wait for the completion interrupt on Ch1 and then enable the transfer again for the LINK channel, to provide the required sync event.
  • result = EDMA3_DRV_enableTransfer (hEdma, ch1Id, EDMA3_DRV_TRIG_MODE_MANUAL);
+

+

    +
  • Note: Enabling of transfers on channel 1 (for master and link channel) is required as many number of times as the sync events are required. For ASync mode, number of sync events=(bcnt * ccnt) and for ABSync mode, number of sync events = ccnt.
+

+

    +
  • Use Case 3: Memory to memory transfer on any available
  • QDMA Channel
    +
    +
      +
    • qTcc1 = EDMA3_DRV_TCC_ANY;
    • qCh1Id = EDMA3_DRV_QDMA_CHANNEL_ANY;
    +
+

+

    +
  • result = EDMA3_DRV_requestChannel (hEdma, &qCh1Id, &qTcc1, (EDMA3_RM_EventQueue)0, &callback1, NULL);
+

+

    +
  • Set the QDMA trigger word.
  • result = EDMA3_DRV_setQdmaTrigWord (hEdma, qCh1Id, EDMA3_RM_QDMA_TRIG_DST);
  • Note: DONOT write the destination address (trigger word) before completing the configuration as it will trigger the transfer. Also, DONOT use EDMA3_DRV_setDestParams() to set the destination address as it also sets other parameters. Use EDMA3_DRV_setPaRAMEntry() to set the destination address
+

+

    +
  • result = EDMA3_DRV_setSrcParams (hEdma, qCh1Id, (unsigned int)(srcBuff1), EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_W8BIT);
+

+

    +
  • Set QDMA transfer parameters (aCnt, bCnt, cCnt, bCntReload, SyncType) acnt = 256; bcnt = 1; ccnt = 1, bcntreload = 0; synctype = EDMA3_DRV_SYNC_A;
  • result = EDMA3_DRV_setTransferParams (hEdma, qCh1Id, acnt, bcnt, ccnt, bcntreload, synctype);
+

+

    +
  • srcbidx = acnt; srccidx = acnt; desbidx = acnt; descidx = acnt;
  • result = EDMA3_DRV_setSrcIndex (hEdma, qCh1Id, srcbidx, srccidx);
  • result = EDMA3_DRV_setDestIndex (hEdma, qCh1Id, desbidx, descidx);
+

+

    +
  • Enable the final completion interrupt.
  • result = EDMA3_DRV_setOptField (hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_TCINTEN, 1);
+

+

    +
  • Set the Destination Addressing Mode as Increment
  • result = EDMA3_DRV_setOptField (hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_DAM, EDMA3_DRV_ADDR_MODE_INCR);
+

+

    +
  • Trigger the QDMA channel by writing the destination address
  • result = EDMA3_DRV_setPaRAMEntry (hEdma, qCh1Id, EDMA3_DRV_PARAM_ENTRY_DST, (unsigned int)(dstBuff1));
+

+

    +
  • Use Case 4: Linked memory to memory transfer on any available
  • QDMA Channel
    +
    +
      +
    • Setup for any QDMA Channel
    • qTcc1 = EDMA3_DRV_TCC_ANY;
    • qCh1Id = EDMA3_DRV_QDMA_CHANNEL_ANY;
    • result = EDMA3_DRV_requestChannel (hEdma, &qCh1Id, &qTcc1, (EDMA3_RM_EventQueue)0, &callback1, NULL);
    +
+

+

    +
  • Setup for Channel 2
  • qCh2Id = EDMA3_DRV_LINK_CHANNEL;
  • qTcc2 = EDMA3_DRV_TCC_ANY;
  • result = EDMA3_DRV_requestChannel (hEdma, &qCh2Id, &qTcc2, (EDMA3_RM_EventQueue)0, &callback2, NULL);
+

+

    +
  • result = EDMA3_DRV_setSrcParams (hEdma, qCh2Id, (unsigned int)(srcBuff2), EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_W8BIT);
  • result = EDMA3_DRV_setDestParams(hEdma, qCh2Id, (unsigned int)(dstBuff2), EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_W8BIT);
+

+

    +
  • acnt = 256; bcnt = 1; ccnt = 1, bcntreload = 0; synctype = EDMA3_DRV_SYNC_A;
  • result = EDMA3_DRV_setTransferParams (hEdma, qCh2Id, acnt, bcnt, ccnt, BRCnt, EDMA3_DRV_SYNC_A);
+

+

    +
  • srcbidx = acnt; srccidx = acnt; desbidx = acnt; descidx = acnt;
  • result = EDMA3_DRV_setSrcIndex (hEdma, qCh2Id, srcbidx, srccidx);
  • result = EDMA3_DRV_setDestIndex (hEdma, qCh2Id, desbidx, descidx);
+

+

    +
  • result = EDMA3_DRV_setOptField (hEdma, qCh2Id, EDMA3_DRV_OPT_FIELD_TCINTEN, 1);
+

+

    +
  • Make the PaRAM Set associated with qCh2Id as Static
  • result = EDMA3_DRV_setOptField (hEdma, qCh2Id, EDMA3_DRV_OPT_FIELD_STATIC, 1u);
+

+

    +
  • Link both the channels
  • result = EDMA3_DRV_linkChannel (hEdma,qCh1Id,qCh2Id);
+

+

    +
  • Set the QDMA trigger word.
  • result = EDMA3_DRV_setQdmaTrigWord (hEdma, qCh1Id, EDMA3_DRV_QDMA_TRIG_DST);
  • Note: DONOT write the destination address (trigger word) before completing the configuration as it'll trigger the transfer. Also, DONOT use EDMA3_DRV_setDestParams () function to set the destination address as it also sets other parameters. Use EDMA3_DRV_setPaRAMEntry() to set the dest address.
+

+

    +
  • result = EDMA3_DRV_setSrcParams (hEdma, qCh1Id, (unsigned int)(srcBuff1), EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_W8BIT);
+

+

    +
  • Set QDMA transfer parameters (aCnt, bCnt, cCnt, bCntReload, SyncType) acnt = 256; bcnt = 1; ccnt = 1, bcntreload = 0; synctype = EDMA3_DRV_SYNC_A;
  • result = EDMA3_DRV_setTransferParams (hEdma, qCh1Id, acnt, bcnt, ccnt, bcntreload, synctype);
+

+

    +
  • srcbidx = acnt; srccidx = acnt; desbidx = acnt; descidx = acnt;
  • result = EDMA3_DRV_setSrcIndex (hEdma, qCh1Id, srcbidx, srccidx);
  • result = EDMA3_DRV_setDestIndex (hEdma, qCh1Id, desbidx, descidx);
+

+

    +
  • result = EDMA3_DRV_setOptField (hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_TCINTEN, 1);
+

+

    +
  • Set the Destination Addressing Mode as Increment
  • result = EDMA3_DRV_setOptField (hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_DAM, EDMA3_DRV_ADDR_MODE_INCR);
+

+

    +
  • Trigger the QDMA channel by writing the destination address
  • result = EDMA3_DRV_setPaRAMEntry (hEdma, qCh1Id, EDMA3_DRV_PARAM_ENTRY_DST, (unsigned int)(dstBuff1));
+

+Error Codes returned by the EDMA3 Driver

Define Documentation

+ +
+
+ + + + +
#define EDMA3_DRV_E_ADDRESS_NOT_ALIGNED   (EDMA3_DRV_E_BASE-10)
+
+
+ +

+The address of the memory location passed as argument is not properly aligned. It should be 32 bytes aligned. +

Referenced by EDMA3_DRV_setDestParams(), and EDMA3_DRV_setSrcParams().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_E_BASE   (-128)
+
+
+ +

+EDMA3 Driver Error Codes Base define +

+

+ +

+
+ + + + +
#define EDMA3_DRV_E_CH_PARAM_BIND_FAIL   (EDMA3_DRV_E_BASE-9)
+
+
+ +

+The binding of Channel and PaRAM Set failed +

Referenced by EDMA3_DRV_requestChannel().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL   (EDMA3_DRV_E_BASE-4)
+
+
+ +

+The requested DMA Channel not available +

Referenced by EDMA3_DRV_requestChannel().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED   (EDMA3_DRV_E_BASE-14)
+
+
+ +

+FIFO width not supported by the requested TC +

Referenced by EDMA3_DRV_setDestParams(), and EDMA3_DRV_setSrcParams().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_E_INST_ALREADY_EXISTS   (EDMA3_DRV_E_BASE-13)
+
+
+ +

+EDMA3 Driver instance already exists for the specified region +

Referenced by EDMA3_DRV_open().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_E_INST_NOT_OPENED   (EDMA3_DRV_E_BASE-16)
+
+
+ +

+EDMA3 Driver Instance does not exist, it is not opened yet +

Referenced by EDMA3_DRV_getInstHandle().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_E_INVALID_PARAM   (EDMA3_DRV_E_BASE-11)
+
+
+ +

+Invalid Parameter passed to API +

Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_checkAndClearTcc(), EDMA3_DRV_clearErrorBits(), EDMA3_DRV_close(), EDMA3_DRV_create(), EDMA3_DRV_delete(), EDMA3_DRV_disableTransfer(), EDMA3_DRV_enableTransfer(), EDMA3_DRV_freeChannel(), EDMA3_DRV_getCCRegister(), EDMA3_DRV_getInstHandle(), EDMA3_DRV_getMapChToEvtQ(), EDMA3_DRV_getOptField(), EDMA3_DRV_getPaRAM(), EDMA3_DRV_getPaRAMEntry(), EDMA3_DRV_getPaRAMField(), EDMA3_DRV_getPaRAMPhyAddr(), EDMA3_DRV_Ioctl(), EDMA3_DRV_linkChannel(), EDMA3_DRV_mapChToEvtQ(), EDMA3_DRV_open(), EDMA3_DRV_requestChannel(), EDMA3_DRV_setCCRegister(), EDMA3_DRV_setDestIndex(), EDMA3_DRV_setDestParams(), EDMA3_DRV_setEvtQPriority(), EDMA3_DRV_setOptField(), EDMA3_DRV_setPaRAM(), EDMA3_DRV_setPaRAMEntry(), EDMA3_DRV_setPaRAMField(), EDMA3_DRV_setQdmaTrigWord(), EDMA3_DRV_setSrcIndex(), EDMA3_DRV_setSrcParams(), EDMA3_DRV_setTransferParams(), EDMA3_DRV_unchainChannel(), EDMA3_DRV_unlinkChannel(), EDMA3_DRV_waitAndClearTcc(), edma3OpenResMgr(), and edma3RemoveMapping().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_E_INVALID_STATE   (EDMA3_DRV_E_BASE-12)
+
+
+ +

+Invalid State of EDMA3 HW Obj +

Referenced by EDMA3_DRV_delete(), and EDMA3_DRV_open().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_E_OBJ_NOT_CLOSED   (EDMA3_DRV_E_BASE-1)
+
+
+ +

+EDMA3 Driver Object Not Closed yet. So it cannot be deleted. +

Referenced by EDMA3_DRV_delete().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_E_OBJ_NOT_DELETED   (EDMA3_DRV_E_BASE)
+
+
+ +

+EDMA3 Driver Object Not Deleted yet. So it cannot be created. +

Referenced by EDMA3_DRV_create().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_E_OBJ_NOT_OPENED   (EDMA3_DRV_E_BASE-2)
+
+
+ +

+EDMA3 Driver Object Not Opened yet So it cannot be closed. +

Referenced by EDMA3_DRV_close().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_E_PARAM_SET_UNAVAIL   (EDMA3_DRV_E_BASE-6)
+
+
+ +

+The requested PaRAM Set not available +

+

+ +

+
+ + + + +
#define EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL   (EDMA3_DRV_E_BASE-5)
+
+
+ +

+The requested QDMA Channel not available +

Referenced by EDMA3_DRV_requestChannel().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_E_RM_CLOSE_FAIL   (EDMA3_DRV_E_BASE-3)
+
+
+ +

+While closing EDMA3 Driver, Resource Manager Close Failed. +

Referenced by EDMA3_DRV_close().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_E_SEMAPHORE   (EDMA3_DRV_E_BASE-15)
+
+
+ +

+Semaphore related error +

+

+ +

+
+ + + + +
#define EDMA3_DRV_E_TCC_REGISTER_FAIL   (EDMA3_DRV_E_BASE-8)
+
+
+ +

+The registration of TCC failed +

Referenced by EDMA3_DRV_requestChannel().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_E_TCC_UNAVAIL   (EDMA3_DRV_E_BASE-7)
+
+
+ +

+The requested TCC not available +

Referenced by EDMA3_DRV_requestChannel().

+ +
+

+

+
Generated on Thu Oct 16 16:17:55 2008 for EDMA3 Driver by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/drv/docs/html/group__edma3drvint.html b/packages/ti/sdo/edma3/drv/docs/html/group__edma3drvint.html new file mode 100644 index 0000000..db2fd58 --- /dev/null +++ b/packages/ti/sdo/edma3/drv/docs/html/group__edma3drvint.html @@ -0,0 +1,1229 @@ + + +EDMA3 Driver: Internal Interface Definition for EDMA3 Driver + + + + + +
+

Internal Interface Definition for EDMA3 Driver

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Modules

 Boundary Values
 Object Maintenance

Data Structures

struct  EDMA3_DRV_ChBoundResources
 EDMA3 Channel-Bound resources. More...

Defines

#define EDMA3_DRV_OPT_SAM_CLR_MASK   (~EDMA3_CCRL_OPT_SAM_MASK)
#define EDMA3_DRV_OPT_SAM_SET_MASK(mode)   (((EDMA3_CCRL_OPT_SAM_MASK >> EDMA3_CCRL_OPT_SAM_SHIFT) & (mode)) << EDMA3_CCRL_OPT_SAM_SHIFT)
#define EDMA3_DRV_OPT_DAM_CLR_MASK   (~EDMA3_CCRL_OPT_DAM_MASK)
#define EDMA3_DRV_OPT_DAM_SET_MASK(mode)   (((EDMA3_CCRL_OPT_DAM_MASK >> EDMA3_CCRL_OPT_DAM_SHIFT) & (mode)) << EDMA3_CCRL_OPT_DAM_SHIFT)
#define EDMA3_DRV_OPT_SYNCDIM_CLR_MASK   (~EDMA3_CCRL_OPT_SYNCDIM_MASK)
#define EDMA3_DRV_OPT_SYNCDIM_SET_MASK(synctype)   (((EDMA3_CCRL_OPT_SYNCDIM_MASK >> EDMA3_CCRL_OPT_SYNCDIM_SHIFT) & (synctype)) << EDMA3_CCRL_OPT_SYNCDIM_SHIFT)
#define EDMA3_DRV_OPT_STATIC_CLR_MASK   (~EDMA3_CCRL_OPT_STATIC_MASK)
#define EDMA3_DRV_OPT_STATIC_SET_MASK(en)   (((EDMA3_CCRL_OPT_STATIC_MASK >> EDMA3_CCRL_OPT_STATIC_SHIFT) & (en)) << EDMA3_CCRL_OPT_STATIC_SHIFT)
#define EDMA3_DRV_OPT_FWID_CLR_MASK   (~EDMA3_CCRL_OPT_FWID_MASK)
#define EDMA3_DRV_OPT_FWID_SET_MASK(width)   (((EDMA3_CCRL_OPT_FWID_MASK >> EDMA3_CCRL_OPT_FWID_SHIFT) & (width)) << EDMA3_CCRL_OPT_FWID_SHIFT)
#define EDMA3_DRV_OPT_TCCMODE_CLR_MASK   (~EDMA3_CCRL_OPT_TCCMODE_MASK)
#define EDMA3_DRV_OPT_TCCMODE_SET_MASK(early)   (((EDMA3_CCRL_OPT_TCCMODE_MASK >> EDMA3_CCRL_OPT_TCCMODE_SHIFT) & (early)) << EDMA3_CCRL_OPT_TCCMODE_SHIFT)
#define EDMA3_DRV_OPT_TCC_CLR_MASK   (~EDMA3_CCRL_OPT_TCC_MASK)
#define EDMA3_DRV_OPT_TCC_SET_MASK(tcc)   (((EDMA3_CCRL_OPT_TCC_MASK >> EDMA3_CCRL_OPT_TCC_SHIFT) & (tcc)) << EDMA3_CCRL_OPT_TCC_SHIFT)
#define EDMA3_DRV_OPT_TCINTEN_CLR_MASK   (~EDMA3_CCRL_OPT_TCINTEN_MASK)
#define EDMA3_DRV_OPT_TCINTEN_SET_MASK(tcinten)   (((EDMA3_CCRL_OPT_TCINTEN_MASK >> EDMA3_CCRL_OPT_TCINTEN_SHIFT) & (tcinten)) << EDMA3_CCRL_OPT_TCINTEN_SHIFT)
#define EDMA3_DRV_OPT_ITCINTEN_CLR_MASK   (~EDMA3_CCRL_OPT_ITCINTEN_MASK)
#define EDMA3_DRV_OPT_ITCINTEN_SET_MASK(itcinten)   (((EDMA3_CCRL_OPT_ITCINTEN_MASK >> EDMA3_CCRL_OPT_ITCINTEN_SHIFT) & (itcinten)) << EDMA3_CCRL_OPT_ITCINTEN_SHIFT)
#define EDMA3_DRV_OPT_TCCHEN_CLR_MASK   (~EDMA3_CCRL_OPT_TCCHEN_MASK)
#define EDMA3_DRV_OPT_TCCHEN_SET_MASK(tcchen)   (((EDMA3_CCRL_OPT_TCCHEN_MASK >> EDMA3_CCRL_OPT_TCCHEN_SHIFT) & (tcchen)) << EDMA3_CCRL_OPT_TCCHEN_SHIFT)
#define EDMA3_DRV_OPT_ITCCHEN_CLR_MASK   (~EDMA3_CCRL_OPT_ITCCHEN_MASK)
#define EDMA3_DRV_OPT_ITCCHEN_SET_MASK(itcchen)   (((EDMA3_CCRL_OPT_ITCCHEN_MASK >> EDMA3_CCRL_OPT_ITCCHEN_SHIFT) & (itcchen)) << EDMA3_CCRL_OPT_ITCCHEN_SHIFT)
#define EDMA3_DRV_OPT_SAM_GET_MASK(mode)   ((mode)&1u)
#define EDMA3_DRV_OPT_DAM_GET_MASK(mode)   (((mode)&(1u<<1u))>>1u)
#define EDMA3_DRV_OPT_SYNCDIM_GET_MASK(synctype)   (((synctype)&(1u<<2u))>>2u)
#define EDMA3_DRV_OPT_STATIC_GET_MASK(en)   (((en)&(1u<<3u))>>3u)
#define EDMA3_DRV_OPT_FWID_GET_MASK(width)   (((width)&(0x7u<<8u))>>8u)
#define EDMA3_DRV_OPT_TCCMODE_GET_MASK(early)   (((early)&(1u<<11u))>>11u)
#define EDMA3_DRV_OPT_TCC_GET_MASK(tcc)   (((tcc)&(0x3fu<<12u))>>12u)
#define EDMA3_DRV_OPT_TCINTEN_GET_MASK(tcinten)   (((tcinten)&(1u<<20u))>>20u)
#define EDMA3_DRV_OPT_ITCINTEN_GET_MASK(itcinten)   (((itcinten)&(1u<<21u))>>21u)
#define EDMA3_DRV_OPT_TCCHEN_GET_MASK(tcchen)   (((tcchen)&(1u<<22u))>>22u)
#define EDMA3_DRV_OPT_ITCCHEN_GET_MASK(itcchen)   (((itcchen)&(1u<<23u))>>23u)
#define EDMA3_DRV_DMAQNUM_CLR_MASK(chNum)   (~(0x7u<<(((chNum)%8u)*4u)))
#define EDMA3_DRV_DMAQNUM_SET_MASK(chNum, queNum)   ((0x7u & (queNum)) << (((chNum)%8u)*4u))
#define EDMA3_DRV_QDMAQNUM_CLR_MASK(chNum)   (~(0x7u<<((chNum)*4u)))
#define EDMA3_DRV_QDMAQNUM_SET_MASK(chNum, queNum)   ((0x7u & (queNum)) << ((chNum)*4u))
#define EDMA3_DRV_QCH_TRWORD_CLR_MASK   (~EDMA3_CCRL_QCHMAP_TRWORD_MASK)
#define EDMA3_DRV_QCH_TRWORD_SET_MASK(paRAMId)   (((EDMA3_CCRL_QCHMAP_TRWORD_MASK >> EDMA3_CCRL_QCHMAP_TRWORD_SHIFT) & (paRAMId)) << EDMA3_CCRL_QCHMAP_TRWORD_SHIFT)
#define EDMA3_DRV_ACNT_MAX_VAL   (0xFFFFu)
#define EDMA3_DRV_BCNT_MAX_VAL   (0xFFFFu)
#define EDMA3_DRV_CCNT_MAX_VAL   (0xFFFFu)
#define EDMA3_DRV_BCNTRELD_MAX_VAL   (0xFFFFu)
#define EDMA3_DRV_SRCBIDX_MAX_VAL   (0x7FFF)
#define EDMA3_DRV_SRCBIDX_MIN_VAL   (-32768)
#define EDMA3_DRV_SRCCIDX_MAX_VAL   (0x7FFF)
#define EDMA3_DRV_SRCCIDX_MIN_VAL   (-32768)
#define EDMA3_DRV_DSTBIDX_MAX_VAL   (0x7FFF)
#define EDMA3_DRV_DSTBIDX_MIN_VAL   (-32768)
#define EDMA3_DRV_DSTCIDX_MAX_VAL   (0x7FFF)
#define EDMA3_DRV_DSTCIDX_MIN_VAL   (-32768)
#define EDMA3_DRV_QPRIORITY_MAX_VAL   (7u)
#define EDMA3_DRV_QPRIORITY_MIN_VAL   (0u)

Enumerations

enum  EDMA3_DRV_ChannelType {
+  EDMA3_DRV_CHANNEL_TYPE_NONE, +
+  EDMA3_DRV_CHANNEL_TYPE_DMA = 1, +
+  EDMA3_DRV_CHANNEL_TYPE_QDMA = 2, +
+  EDMA3_DRV_CHANNEL_TYPE_LINK = 3 +
+ }
 EDMA3 Channel Type. More...
+

Detailed Description

+Include EDMA3 Driver header file

+Documentation of the Internal Interface of EDMA3 Driver

Define Documentation

+ +
+
+ + + + +
#define EDMA3_DRV_ACNT_MAX_VAL   (0xFFFFu)
+
+
+ +

+Max value of ACnt +

Referenced by EDMA3_DRV_setTransferParams().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_BCNT_MAX_VAL   (0xFFFFu)
+
+
+ +

+Max value of BCnt +

Referenced by EDMA3_DRV_setTransferParams().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_BCNTRELD_MAX_VAL   (0xFFFFu)
+
+
+ +

+Max value of BCntReld +

Referenced by EDMA3_DRV_setTransferParams().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_CCNT_MAX_VAL   (0xFFFFu)
+
+
+ +

+Max value of CCnt +

Referenced by EDMA3_DRV_setTransferParams().

+ +
+

+ +

+
+ + + + + + + + + +
#define EDMA3_DRV_DMAQNUM_CLR_MASK (chNum   )    (~(0x7u<<(((chNum)%8u)*4u)))
+
+
+ +

+DMAQNUM bits Clear +

Referenced by EDMA3_DRV_getMapChToEvtQ(), EDMA3_DRV_mapChToEvtQ(), EDMA3_DRV_requestChannel(), EDMA3_DRV_setDestParams(), EDMA3_DRV_setSrcParams(), and edma3RemoveMapping().

+ +
+

+ +

+
+ + + + + + + + + + + + +
#define EDMA3_DRV_DMAQNUM_SET_MASK (chNum,
queNum   )    ((0x7u & (queNum)) << (((chNum)%8u)*4u))
+
+
+ +

+DMAQNUM bits Set +

Referenced by EDMA3_DRV_mapChToEvtQ(), and EDMA3_DRV_requestChannel().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_DSTBIDX_MAX_VAL   (0x7FFF)
+
+
+ +

+Max value of DestBIdx +

Referenced by EDMA3_DRV_setDestIndex().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_DSTBIDX_MIN_VAL   (-32768)
+
+
+ +

+Min value of DestBIdx +

Referenced by EDMA3_DRV_setDestIndex().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_DSTCIDX_MAX_VAL   (0x7FFF)
+
+
+ +

+Max value of DestCIdx +

Referenced by EDMA3_DRV_setDestIndex().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_DSTCIDX_MIN_VAL   (-32768)
+
+
+ +

+Min value of DestCIdx +

Referenced by EDMA3_DRV_setDestIndex().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_OPT_DAM_CLR_MASK   (~EDMA3_CCRL_OPT_DAM_MASK)
+
+
+ +

+OPT-DAM bit Clear +

Referenced by EDMA3_DRV_setDestParams(), and EDMA3_DRV_setOptField().

+ +
+

+ +

+
+ + + + + + + + + +
#define EDMA3_DRV_OPT_DAM_GET_MASK (mode   )    (((mode)&(1u<<1u))>>1u)
+
+
+ +

+OPT-DAM bit Get +

Referenced by EDMA3_DRV_getOptField().

+ +
+

+ +

+
+ + + + + + + + + +
#define EDMA3_DRV_OPT_DAM_SET_MASK (mode   )    (((EDMA3_CCRL_OPT_DAM_MASK >> EDMA3_CCRL_OPT_DAM_SHIFT) & (mode)) << EDMA3_CCRL_OPT_DAM_SHIFT)
+
+
+ +

+OPT-DAM bit Set +

Referenced by EDMA3_DRV_setDestParams(), and EDMA3_DRV_setOptField().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_OPT_FWID_CLR_MASK   (~EDMA3_CCRL_OPT_FWID_MASK)
+
+
+ +

+OPT-FWID bitfield Clear +

Referenced by EDMA3_DRV_setDestParams(), EDMA3_DRV_setOptField(), and EDMA3_DRV_setSrcParams().

+ +
+

+ +

+
+ + + + + + + + + +
#define EDMA3_DRV_OPT_FWID_GET_MASK (width   )    (((width)&(0x7u<<8u))>>8u)
+
+
+ +

+OPT-FWID bitfield Get +

Referenced by EDMA3_DRV_getOptField().

+ +
+

+ +

+
+ + + + + + + + + +
#define EDMA3_DRV_OPT_FWID_SET_MASK (width   )    (((EDMA3_CCRL_OPT_FWID_MASK >> EDMA3_CCRL_OPT_FWID_SHIFT) & (width)) << EDMA3_CCRL_OPT_FWID_SHIFT)
+
+
+ +

+OPT-FWID bitfield Set +

Referenced by EDMA3_DRV_setDestParams(), EDMA3_DRV_setOptField(), and EDMA3_DRV_setSrcParams().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_OPT_ITCCHEN_CLR_MASK   (~EDMA3_CCRL_OPT_ITCCHEN_MASK)
+
+
+ +

+OPT-ITCCHEN bit Clear +

Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_setOptField(), and EDMA3_DRV_unchainChannel().

+ +
+

+ +

+
+ + + + + + + + + +
#define EDMA3_DRV_OPT_ITCCHEN_GET_MASK (itcchen   )    (((itcchen)&(1u<<23u))>>23u)
+
+
+ +

+OPT-ITCCHEN bit Get +

Referenced by EDMA3_DRV_getOptField().

+ +
+

+ +

+
+ + + + + + + + + +
#define EDMA3_DRV_OPT_ITCCHEN_SET_MASK (itcchen   )    (((EDMA3_CCRL_OPT_ITCCHEN_MASK >> EDMA3_CCRL_OPT_ITCCHEN_SHIFT) & (itcchen)) << EDMA3_CCRL_OPT_ITCCHEN_SHIFT)
+
+
+ +

+OPT-ITCCHEN bit Set +

Referenced by EDMA3_DRV_chainChannel(), and EDMA3_DRV_setOptField().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_OPT_ITCINTEN_CLR_MASK   (~EDMA3_CCRL_OPT_ITCINTEN_MASK)
+
+
+ +

+OPT-ITCINTEN bit Clear +

Referenced by EDMA3_DRV_chainChannel(), and EDMA3_DRV_setOptField().

+ +
+

+ +

+
+ + + + + + + + + +
#define EDMA3_DRV_OPT_ITCINTEN_GET_MASK (itcinten   )    (((itcinten)&(1u<<21u))>>21u)
+
+
+ +

+OPT-ITCINTEN bit Get +

Referenced by EDMA3_DRV_getOptField().

+ +
+

+ +

+
+ + + + + + + + + +
#define EDMA3_DRV_OPT_ITCINTEN_SET_MASK (itcinten   )    (((EDMA3_CCRL_OPT_ITCINTEN_MASK >> EDMA3_CCRL_OPT_ITCINTEN_SHIFT) & (itcinten)) << EDMA3_CCRL_OPT_ITCINTEN_SHIFT)
+
+
+ +

+OPT-ITCINTEN bit Set +

Referenced by EDMA3_DRV_chainChannel(), and EDMA3_DRV_setOptField().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_OPT_SAM_CLR_MASK   (~EDMA3_CCRL_OPT_SAM_MASK)
+
+
+ +

+Parameter RAM Set field OPT bit-field defines OPT-SAM bit Clear +

Referenced by EDMA3_DRV_setOptField(), and EDMA3_DRV_setSrcParams().

+ +
+

+ +

+
+ + + + + + + + + +
#define EDMA3_DRV_OPT_SAM_GET_MASK (mode   )    ((mode)&1u)
+
+
+ +

+OPT-SAM bit Get +

Referenced by EDMA3_DRV_getOptField().

+ +
+

+ +

+
+ + + + + + + + + +
#define EDMA3_DRV_OPT_SAM_SET_MASK (mode   )    (((EDMA3_CCRL_OPT_SAM_MASK >> EDMA3_CCRL_OPT_SAM_SHIFT) & (mode)) << EDMA3_CCRL_OPT_SAM_SHIFT)
+
+
+ +

+OPT-SAM bit Set +

Referenced by EDMA3_DRV_setOptField(), and EDMA3_DRV_setSrcParams().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_OPT_STATIC_CLR_MASK   (~EDMA3_CCRL_OPT_STATIC_MASK)
+
+
+ +

+OPT-STATIC bit Clear +

Referenced by EDMA3_DRV_setOptField().

+ +
+

+ +

+
+ + + + + + + + + +
#define EDMA3_DRV_OPT_STATIC_GET_MASK (en   )    (((en)&(1u<<3u))>>3u)
+
+
+ +

+OPT-STATIC bit Get +

Referenced by EDMA3_DRV_getOptField().

+ +
+

+ +

+
+ + + + + + + + + +
#define EDMA3_DRV_OPT_STATIC_SET_MASK (en   )    (((EDMA3_CCRL_OPT_STATIC_MASK >> EDMA3_CCRL_OPT_STATIC_SHIFT) & (en)) << EDMA3_CCRL_OPT_STATIC_SHIFT)
+
+
+ +

+OPT-STATIC bit Set +

Referenced by EDMA3_DRV_setOptField().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_OPT_SYNCDIM_CLR_MASK   (~EDMA3_CCRL_OPT_SYNCDIM_MASK)
+
+
+ +

+OPT-SYNCDIM bit Clear +

Referenced by EDMA3_DRV_setOptField(), and EDMA3_DRV_setTransferParams().

+ +
+

+ +

+
+ + + + + + + + + +
#define EDMA3_DRV_OPT_SYNCDIM_GET_MASK (synctype   )    (((synctype)&(1u<<2u))>>2u)
+
+
+ +

+OPT-SYNCDIM bit Get +

Referenced by EDMA3_DRV_getOptField().

+ +
+

+ +

+
+ + + + + + + + + +
#define EDMA3_DRV_OPT_SYNCDIM_SET_MASK (synctype   )    (((EDMA3_CCRL_OPT_SYNCDIM_MASK >> EDMA3_CCRL_OPT_SYNCDIM_SHIFT) & (synctype)) << EDMA3_CCRL_OPT_SYNCDIM_SHIFT)
+
+
+ +

+OPT-SYNCDIM bit Set +

Referenced by EDMA3_DRV_setOptField(), and EDMA3_DRV_setTransferParams().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_OPT_TCC_CLR_MASK   (~EDMA3_CCRL_OPT_TCC_MASK)
+
+
+ +

+OPT-TCC bitfield Clear +

Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_linkChannel(), EDMA3_DRV_requestChannel(), and EDMA3_DRV_setOptField().

+ +
+

+ +

+
+ + + + + + + + + +
#define EDMA3_DRV_OPT_TCC_GET_MASK (tcc   )    (((tcc)&(0x3fu<<12u))>>12u)
+
+
+ +

+OPT-TCC bitfield Get +

Referenced by EDMA3_DRV_getOptField(), and EDMA3_DRV_linkChannel().

+ +
+

+ +

+
+ + + + + + + + + +
#define EDMA3_DRV_OPT_TCC_SET_MASK (tcc   )    (((EDMA3_CCRL_OPT_TCC_MASK >> EDMA3_CCRL_OPT_TCC_SHIFT) & (tcc)) << EDMA3_CCRL_OPT_TCC_SHIFT)
+
+
+ +

+OPT-TCC bitfield Set +

Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_linkChannel(), EDMA3_DRV_requestChannel(), and EDMA3_DRV_setOptField().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_OPT_TCCHEN_CLR_MASK   (~EDMA3_CCRL_OPT_TCCHEN_MASK)
+
+
+ +

+OPT-TCCHEN bit Clear +

Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_setOptField(), and EDMA3_DRV_unchainChannel().

+ +
+

+ +

+
+ + + + + + + + + +
#define EDMA3_DRV_OPT_TCCHEN_GET_MASK (tcchen   )    (((tcchen)&(1u<<22u))>>22u)
+
+
+ +

+OPT-TCCHEN bit Get +

Referenced by EDMA3_DRV_getOptField().

+ +
+

+ +

+
+ + + + + + + + + +
#define EDMA3_DRV_OPT_TCCHEN_SET_MASK (tcchen   )    (((EDMA3_CCRL_OPT_TCCHEN_MASK >> EDMA3_CCRL_OPT_TCCHEN_SHIFT) & (tcchen)) << EDMA3_CCRL_OPT_TCCHEN_SHIFT)
+
+
+ +

+OPT-TCCHEN bit Set +

Referenced by EDMA3_DRV_chainChannel(), and EDMA3_DRV_setOptField().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_OPT_TCCMODE_CLR_MASK   (~EDMA3_CCRL_OPT_TCCMODE_MASK)
+
+
+ +

+OPT-TCCMODE bit Clear +

Referenced by EDMA3_DRV_setOptField().

+ +
+

+ +

+
+ + + + + + + + + +
#define EDMA3_DRV_OPT_TCCMODE_GET_MASK (early   )    (((early)&(1u<<11u))>>11u)
+
+
+ +

+OPT-TCCMODE bit Get +

Referenced by EDMA3_DRV_getOptField().

+ +
+

+ +

+
+ + + + + + + + + +
#define EDMA3_DRV_OPT_TCCMODE_SET_MASK (early   )    (((EDMA3_CCRL_OPT_TCCMODE_MASK >> EDMA3_CCRL_OPT_TCCMODE_SHIFT) & (early)) << EDMA3_CCRL_OPT_TCCMODE_SHIFT)
+
+
+ +

+OPT-TCCMODE bit Set +

Referenced by EDMA3_DRV_setOptField().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_OPT_TCINTEN_CLR_MASK   (~EDMA3_CCRL_OPT_TCINTEN_MASK)
+
+
+ +

+OPT-TCINTEN bit Clear +

Referenced by EDMA3_DRV_chainChannel(), and EDMA3_DRV_setOptField().

+ +
+

+ +

+
+ + + + + + + + + +
#define EDMA3_DRV_OPT_TCINTEN_GET_MASK (tcinten   )    (((tcinten)&(1u<<20u))>>20u)
+
+
+ +

+OPT-TCINTEN bit Get +

Referenced by EDMA3_DRV_getOptField().

+ +
+

+ +

+
+ + + + + + + + + +
#define EDMA3_DRV_OPT_TCINTEN_SET_MASK (tcinten   )    (((EDMA3_CCRL_OPT_TCINTEN_MASK >> EDMA3_CCRL_OPT_TCINTEN_SHIFT) & (tcinten)) << EDMA3_CCRL_OPT_TCINTEN_SHIFT)
+
+
+ +

+OPT-TCINTEN bit Set +

Referenced by EDMA3_DRV_chainChannel(), and EDMA3_DRV_setOptField().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_QCH_TRWORD_CLR_MASK   (~EDMA3_CCRL_QCHMAP_TRWORD_MASK)
+
+
+ +

+QCHMAP-TrigWord bitfield Clear +

Referenced by EDMA3_DRV_setQdmaTrigWord().

+ +
+

+ +

+
+ + + + + + + + + +
#define EDMA3_DRV_QCH_TRWORD_SET_MASK (paRAMId   )    (((EDMA3_CCRL_QCHMAP_TRWORD_MASK >> EDMA3_CCRL_QCHMAP_TRWORD_SHIFT) & (paRAMId)) << EDMA3_CCRL_QCHMAP_TRWORD_SHIFT)
+
+
+ +

+QCHMAP-TrigWord bitfield Set +

Referenced by EDMA3_DRV_setQdmaTrigWord().

+ +
+

+ +

+
+ + + + + + + + + +
#define EDMA3_DRV_QDMAQNUM_CLR_MASK (chNum   )    (~(0x7u<<((chNum)*4u)))
+
+
+ +

+QDMAQNUM bits Clear +

Referenced by EDMA3_DRV_getMapChToEvtQ(), EDMA3_DRV_mapChToEvtQ(), EDMA3_DRV_requestChannel(), EDMA3_DRV_setDestParams(), EDMA3_DRV_setSrcParams(), and edma3RemoveMapping().

+ +
+

+ +

+
+ + + + + + + + + + + + +
#define EDMA3_DRV_QDMAQNUM_SET_MASK (chNum,
queNum   )    ((0x7u & (queNum)) << ((chNum)*4u))
+
+
+ +

+QDMAQNUM bits Set +

Referenced by EDMA3_DRV_mapChToEvtQ(), and EDMA3_DRV_requestChannel().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_QPRIORITY_MAX_VAL   (7u)
+
+
+ +

+Max value of Queue Priority +

Referenced by EDMA3_DRV_setEvtQPriority().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_QPRIORITY_MIN_VAL   (0u)
+
+
+ +

+Min value of Queue Priority +

+

+ +

+
+ + + + +
#define EDMA3_DRV_SRCBIDX_MAX_VAL   (0x7FFF)
+
+
+ +

+Max value of SrcBIdx +

Referenced by EDMA3_DRV_setSrcIndex().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_SRCBIDX_MIN_VAL   (-32768)
+
+
+ +

+Min value of SrcBIdx +

Referenced by EDMA3_DRV_setSrcIndex().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_SRCCIDX_MAX_VAL   (0x7FFF)
+
+
+ +

+Max value of SrcCIdx +

Referenced by EDMA3_DRV_setSrcIndex().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_SRCCIDX_MIN_VAL   (-32768)
+
+
+ +

+Min value of SrcCIdx +

Referenced by EDMA3_DRV_setSrcIndex().

+ +
+

+

Enumeration Type Documentation

+ +
+
+ + + + +
enum EDMA3_DRV_ChannelType
+
+
+ +

+EDMA3 Channel Type. +

+

Enumerator:
+ + + + + +
EDMA3_DRV_CHANNEL_TYPE_NONE  +Invalid Channel
EDMA3_DRV_CHANNEL_TYPE_DMA  +DMA Channel
EDMA3_DRV_CHANNEL_TYPE_QDMA  +QDMA Channel
EDMA3_DRV_CHANNEL_TYPE_LINK  +LINK Channel
+
+ +
+

+

+
Generated on Thu Oct 16 16:17:56 2008 for EDMA3 Driver by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/drv/docs/html/group__edma3drvintboundvals.html b/packages/ti/sdo/edma3/drv/docs/html/group__edma3drvintboundvals.html new file mode 100644 index 0000000..fb662fa --- /dev/null +++ b/packages/ti/sdo/edma3/drv/docs/html/group__edma3drvintboundvals.html @@ -0,0 +1,147 @@ + + +EDMA3 Driver: Boundary Values + + + + + +
+

Boundary Values
+ +[Internal Interface Definition for EDMA3 Driver] +

+ + + + + + + + + + + + + + +

Defines

#define EDMA3_DRV_DMA_CH_MAX_VAL   (EDMA3_MAX_DMA_CH - 1u)
#define EDMA3_DRV_LINK_CH_MIN_VAL   (EDMA3_DRV_DMA_CH_MAX_VAL + 1u)
#define EDMA3_DRV_LINK_CH_MAX_VAL   (EDMA3_DRV_LINK_CH_MIN_VAL + EDMA3_MAX_PARAM_SETS - 1u)
#define EDMA3_DRV_QDMA_CH_MIN_VAL   (EDMA3_DRV_LINK_CH_MAX_VAL + 1u)
#define EDMA3_DRV_QDMA_CH_MAX_VAL   (EDMA3_DRV_QDMA_CH_MIN_VAL + EDMA3_MAX_QDMA_CH - 1u)
#define EDMA3_DRV_LOG_CH_MAX_VAL   (EDMA3_DRV_QDMA_CH_MAX_VAL)
+

Detailed Description

+Boundary Values for Logical Channel Ranges

Define Documentation

+ +
+
+ + + + +
#define EDMA3_DRV_DMA_CH_MAX_VAL   (EDMA3_MAX_DMA_CH - 1u)
+
+
+ +

+Max of DMA Channels +

Referenced by EDMA3_DRV_clearErrorBits(), EDMA3_DRV_disableTransfer(), EDMA3_DRV_enableTransfer(), EDMA3_DRV_freeChannel(), EDMA3_DRV_getMapChToEvtQ(), EDMA3_DRV_mapChToEvtQ(), EDMA3_DRV_requestChannel(), EDMA3_DRV_setDestParams(), EDMA3_DRV_setSrcParams(), and edma3RemoveMapping().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_LINK_CH_MAX_VAL   (EDMA3_DRV_LINK_CH_MIN_VAL + EDMA3_MAX_PARAM_SETS - 1u)
+
+
+ +

+Max of Link Channels +

Referenced by EDMA3_DRV_freeChannel(), and EDMA3_DRV_requestChannel().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_LINK_CH_MIN_VAL   (EDMA3_DRV_DMA_CH_MAX_VAL + 1u)
+
+
+ +

+Min of Link Channels +

Referenced by EDMA3_DRV_freeChannel(), and EDMA3_DRV_requestChannel().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_LOG_CH_MAX_VAL   (EDMA3_DRV_QDMA_CH_MAX_VAL)
+
+
+ +

+Max of Logical Channels +

Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_disableTransfer(), EDMA3_DRV_enableTransfer(), EDMA3_DRV_freeChannel(), EDMA3_DRV_getMapChToEvtQ(), EDMA3_DRV_getOptField(), EDMA3_DRV_getPaRAM(), EDMA3_DRV_getPaRAMEntry(), EDMA3_DRV_getPaRAMField(), EDMA3_DRV_getPaRAMPhyAddr(), EDMA3_DRV_linkChannel(), EDMA3_DRV_setDestIndex(), EDMA3_DRV_setDestParams(), EDMA3_DRV_setOptField(), EDMA3_DRV_setPaRAM(), EDMA3_DRV_setPaRAMEntry(), EDMA3_DRV_setPaRAMField(), EDMA3_DRV_setSrcIndex(), EDMA3_DRV_setSrcParams(), EDMA3_DRV_setTransferParams(), EDMA3_DRV_unchainChannel(), EDMA3_DRV_unlinkChannel(), and edma3RemoveMapping().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_QDMA_CH_MAX_VAL   (EDMA3_DRV_QDMA_CH_MIN_VAL + EDMA3_MAX_QDMA_CH - 1u)
+
+
+ +

+Max of QDMA Channels +

Referenced by EDMA3_DRV_disableTransfer(), EDMA3_DRV_enableTransfer(), EDMA3_DRV_freeChannel(), EDMA3_DRV_getMapChToEvtQ(), EDMA3_DRV_mapChToEvtQ(), EDMA3_DRV_requestChannel(), EDMA3_DRV_setDestParams(), EDMA3_DRV_setQdmaTrigWord(), and EDMA3_DRV_setSrcParams().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_QDMA_CH_MIN_VAL   (EDMA3_DRV_LINK_CH_MAX_VAL + 1u)
+
+
+ +

+Min of QDMA Channels +

Referenced by EDMA3_DRV_disableTransfer(), EDMA3_DRV_enableTransfer(), EDMA3_DRV_freeChannel(), EDMA3_DRV_getMapChToEvtQ(), EDMA3_DRV_mapChToEvtQ(), EDMA3_DRV_requestChannel(), EDMA3_DRV_setDestParams(), EDMA3_DRV_setQdmaTrigWord(), EDMA3_DRV_setSrcParams(), and edma3RemoveMapping().

+ +
+

+

+
Generated on Thu Oct 16 16:17:56 2008 for EDMA3 Driver by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/drv/docs/html/group__edma3drvintobjmaint.html b/packages/ti/sdo/edma3/drv/docs/html/group__edma3drvintobjmaint.html new file mode 100644 index 0000000..170d2ac --- /dev/null +++ b/packages/ti/sdo/edma3/drv/docs/html/group__edma3drvintobjmaint.html @@ -0,0 +1,78 @@ + + +EDMA3 Driver: Object Maintenance + + + + + +
+

Object Maintenance
+ +[Internal Interface Definition for EDMA3 Driver] +

+ + + + + + + + + + + +

Data Structures

struct  EDMA3_DRV_Object
 EDMA3 Driver Object (HW Specific) Maintenance structure. More...
struct  EDMA3_DRV_Instance
 EDMA3 Driver Instance Configuration Structure. More...

Enumerations

enum  EDMA3_DRV_ObjState {
+  EDMA3_DRV_DELETED = 0, +
+  EDMA3_DRV_CREATED = 1, +
+  EDMA3_DRV_OPENED = 2, +
+  EDMA3_DRV_CLOSED = 3 +
+ }
+

Detailed Description

+Maintenance of the EDMA3 Driver Object

Enumeration Type Documentation

+ +
+
+ + + + +
enum EDMA3_DRV_ObjState
+
+
+ +

+To maintain the state of the EDMA3 Driver object

Enumerator:
+ + + + + +
EDMA3_DRV_DELETED  +Object deleted
EDMA3_DRV_CREATED  +Obect Created
EDMA3_DRV_OPENED  +Object Opened
EDMA3_DRV_CLOSED  +Object Closed
+
+ +
+

+

+
Generated on Thu Oct 16 16:17:56 2008 for EDMA3 Driver by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/drv/docs/html/group__edma3drvmain.html b/packages/ti/sdo/edma3/drv/docs/html/group__edma3drvmain.html new file mode 100644 index 0000000..199acea --- /dev/null +++ b/packages/ti/sdo/edma3/drv/docs/html/group__edma3drvmain.html @@ -0,0 +1,320 @@ + + +EDMA3 Driver: EDMA3 Driver Interface Definition + + + + + +
+

EDMA3 Driver Interface Definition

+ + + + + + + + +

+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Modules

 EDMA3 Driver Usage Guidelines
 EDMA3 Driver Error Codes
 Usage of EDMA3 Driver.
 EDMA3 Driver Channel Setup
 EDMA3 Driver Typical EDMA Transfer Setup
 EDMA3 Driver Optional Setup for EDMA

Data Structures

struct  EDMA3_DRV_GblConfigParams
 Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. More...
struct  EDMA3_DRV_InstanceInitConfig
 Init-time Region Specific Configuration structure for EDMA3 Driver, to provide region specific Information. More...
struct  EDMA3_DRV_InitConfig
 Used to Initialize the EDMA3 Driver Instance. More...
struct  EDMA3_DRV_MiscParam
 Used to specify the miscellaneous options during EDMA3 Driver Initialization. More...

Defines

#define EDMA3_DRV_CH_NO_PARAM_MAP   EDMA3_RM_CH_NO_PARAM_MAP
#define EDMA3_DRV_CH_NO_TCC_MAP   EDMA3_RM_CH_NO_TCC_MAP

Functions

EDMA3_DRV_Result EDMA3_DRV_create (unsigned int phyCtrllerInstId, const EDMA3_DRV_GblConfigParams *gblCfgParams, const void *miscParam)
 Create EDMA3 Driver Object.
EDMA3_DRV_Result EDMA3_DRV_delete (unsigned int phyCtrllerInstId, const void *param)
 Delete EDMA3 Driver Object.
EDMA3_DRV_Handle EDMA3_DRV_open (unsigned int phyCtrllerInstId, const EDMA3_DRV_InitConfig *initCfg, EDMA3_DRV_Result *errorCode)
 Open EDMA3 Driver Instance.
EDMA3_DRV_Result EDMA3_DRV_close (EDMA3_DRV_Handle hEdma, const void *param)
 Close the EDMA3 Driver Instance.
+

Detailed Description

+Top-level Encapsulation of all documentation for EDMA3 Driver

Define Documentation

+ +
+
+ + + + +
#define EDMA3_DRV_CH_NO_PARAM_MAP   EDMA3_RM_CH_NO_PARAM_MAP
+
+
+ +

+This define is used to specify that a DMA channel is NOT tied to any PaRAM Set and hence any available PaRAM Set could be used for that DMA channel. It could be used in dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH], in global configuration structure EDMA3_RM_GblConfigParams.

+This value should mandatorily be used to mark DMA channels with no initial mapping to specific PaRAM Sets. +

Referenced by EDMA3_DRV_requestChannel().

+ +
+

+ +

+
+ + + + +
#define EDMA3_DRV_CH_NO_TCC_MAP   EDMA3_RM_CH_NO_TCC_MAP
+
+
+ +

+This define is used to specify that the DMA/QDMA channel is not tied to any TCC and hence any available TCC could be used for that DMA/QDMA channel. It could be used in dmaChannelTccMap [EDMA3_MAX_DMA_CH], in global configuration structure EDMA3_RM_GblConfigParams.

+This value should mandatorily be used to mark DMA channels with no initial mapping to specific TCCs. +

Referenced by EDMA3_DRV_requestChannel().

+ +
+

+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Result EDMA3_DRV_close (EDMA3_DRV_Handle  hEdma,
const void *  param 
)
+
+
+ +

+Close the EDMA3 Driver Instance. +

+This API is used to close a previously opened EDMA3 Driver Instance.

+

Parameters:
+ + + +
hEdma [IN] Handle to the previously opened EDMA3 Driver Instance.
param [IN] For possible future use
+
+
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error code
+
Note:
This function disables the global interrupts (by calling API edma3OsProtectEntry with protection level EDMA3_OS_PROTECT_INTERRUPT) while modifying the global data structures, to make it re-entrant.
+ +

References EDMA3_DRV_Instance::drvInstInitConfig, EDMA3_DRV_CLOSED, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_E_OBJ_NOT_OPENED, EDMA3_DRV_E_RM_CLOSE_FAIL, EDMA3_DRV_OPENED, edma3MemSet(), EDMA3_DRV_Object::numOpens, EDMA3_DRV_Instance::pDrvObjectHandle, EDMA3_DRV_Instance::resMgrInstance, EDMA3_DRV_Instance::shadowRegs, and EDMA3_DRV_Object::state.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Result EDMA3_DRV_create (unsigned int  phyCtrllerInstId,
const EDMA3_DRV_GblConfigParams *  gblCfgParams,
const void *  miscParam 
)
+
+
+ +

+Create EDMA3 Driver Object. +

+This API is used to create the EDMA3 Driver Object. It should be called only ONCE for each EDMA3 hardware instance.

+Init-time Configuration structure for EDMA3 hardware is provided to pass the SoC specific information. This configuration information could be provided by the user at init-time. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c, in case it is available.

+This API clears the error specific registers (EMCR/EMCRh, QEMCR, CCERRCLR) and sets the TCs priorities and Event Queues' watermark levels, if the 'miscParam' argument is NULL. User can avoid these registers' programming (in some specific use cases) by SETTING the 'isSlave' field of 'EDMA3_RM_MiscParam' configuration structure and passing this structure as the third argument (miscParam).

+After successful completion of this API, Driver Object's state changes to EDMA3_DRV_CREATED from EDMA3_DRV_DELETED.

+

Parameters:
+ + + + +
phyCtrllerInstId [IN] EDMA3 Controller Instance Id (Hardware instance id, starting from 0).
gblCfgParams [IN] SoC specific configuration structure for the EDMA3 Hardware.
miscParam [IN] Misc configuration options provided in the structure 'EDMA3_DRV_MiscParam'. For default options, user can pass NULL in this argument.
+
+
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error code
+ +

+Used to reset the Internal EDMA3 Driver Data Structures for the first time.

+We are NOT checking 'gblCfgParams' for NULL. Whatever user has passed is given to RM. If user passed NULL, config info from config file will be taken else user specific info will be passed to the RM. Similarly, 'miscParam' is not being checked and passed as it is to the Resource Manager layer.

+Copy the global config info from the RM object to the driver object for future use. +

References EDMA3_DRV_CREATED, EDMA3_DRV_DELETED, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_E_OBJ_NOT_DELETED, EDMA3_DRV_TRIG_MODE_NONE, edma3MemCpy(), edma3MemSet(), EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_Object::numOpens, EDMA3_DRV_GblConfigParams::numRegions, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Object::phyCtrllerInstId, resMgrObj, EDMA3_DRV_Object::state, EDMA3_DRV_ChBoundResources::tcc, and EDMA3_DRV_ChBoundResources::trigMode.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Result EDMA3_DRV_delete (unsigned int  phyCtrllerInstId,
const void *  param 
)
+
+
+ +

+Delete EDMA3 Driver Object. +

+Use this API to delete the EDMA3 Driver Object. It should be called only ONCE for each EDMA3 hardware instance. It should be called ONLY after closing all the EDMA3 Driver Instances.

+This API is used to delete the EDMA3 Driver Object. It should be called once for each EDMA3 hardware instance, ONLY after closing all the previously opened EDMA3 Driver Instances.

+After successful completion of this API, Driver Object's state changes to EDMA3_DRV_DELETED.

+

Parameters:
+ + + +
phyCtrllerInstId [IN] EDMA3 Phy Controller Instance Id (Hardware instance id, starting from 0).
param [IN] For possible future use.
+
+
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error code
+ +

+If number of Driver Instances is 0, then state should be EDMA3_DRV_CLOSED OR EDMA3_DRV_CREATED.

+If number of Driver Instances is NOT 0, then this function SHOULD NOT be called by anybody.

+State is correct. Delete the RM Object.

+Change state to EDMA3_DRV_DELETED +

References EDMA3_DRV_CLOSED, EDMA3_DRV_CREATED, EDMA3_DRV_DELETED, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_E_INVALID_STATE, EDMA3_DRV_E_OBJ_NOT_CLOSED, edma3MemSet(), and EDMA3_DRV_Object::state.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Handle EDMA3_DRV_open (unsigned int  phyCtrllerInstId,
const EDMA3_DRV_InitConfig *  initCfg,
EDMA3_DRV_Result *  errorCode 
)
+
+
+ +

+Open EDMA3 Driver Instance. +

+This API is used to open an EDMA3 Driver Instance. It could be called multiple times, for each possible EDMA3 shadow region. Maximum EDMA3_MAX_REGIONS instances are allowed for each EDMA3 hardware instance. Multiple instances on the same shadow region are NOT allowed.

+Also, only ONE Master Driver Instance is permitted. This master instance (and hence the region to which it belongs) will only receive the EDMA3 interrupts, if enabled.

+User could pass the instance specific configuration structure (initCfg.drvInstInitConfig) as a part of the 'initCfg' structure, during init-time. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c, in case it is available.

+By default, this EDMA3 Driver instance will clear the PaRAM Sets while allocating them. To change the default behavior, user should use the IOCTL interface appropriately.

+

Parameters:
+ + + + +
phyCtrllerInstId [IN] EDMA3 Controller Instance Id (Hardware instance id, starting from 0).
initCfg [IN] Used to Initialize the EDMA3 Driver Instance (Master or Slave).
errorCode [OUT] Error code while opening DRV instance.
+
+
Returns:
EDMA3_DRV_Handle : If successfully opened, the API will return the associated driver's instance handle.
+
Note:
This function disables the global interrupts (by calling API edma3OsProtectEntry with protection level EDMA3_OS_PROTECT_INTERRUPT) while modifying the global data structures, to make it re-entrant.
+This API is used to open an EDMA3 Driver Instance. It could be called multiple times, for each possible EDMA3 shadow region. Maximum EDMA3_MAX_REGIONS instances are allowed for each EDMA3 hardware instance. Multiple instances on the same shadow region are NOT allowed.

+Also, only ONE Master Driver Instance is permitted. This master instance (and hence the region to which it belongs) will only receive the EDMA3 interrupts, if enabled.

+User could pass the instance specific configuration structure (initCfg.drvInstInitConfig) as a part of the 'initCfg' structure, during init-time. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c, in case it is available.

+

Parameters:
+ + + + +
phyCtrllerInstId [IN] EDMA3 Controller Instance Id (Hardware instance id, starting from 0).
initCfg [IN] Used to Initialize the EDMA3 Driver Instance (Master or Slave).
errorCode [OUT] Error code while opening DRV instance.
+
+
Returns:
EDMA3_DRV_Handle : If successfully opened, the API will return the associated driver's instance handle.
+
Note:
This function disables the global interrupts (by calling API edma3OsProtectEntry with protection level EDMA3_OS_PROTECT_INTERRUPT) while modifying the global data structures, to make it re-entrant.
+ +

References EDMA3_DRV_Instance::drvInstInitConfig, EDMA3_DRV_InitConfig::drvInstInitConfig, EDMA3_DRV_Instance::drvSemHandle, EDMA3_DRV_InitConfig::drvSemHandle, EDMA3_DRV_CLOSED, EDMA3_DRV_CREATED, EDMA3_DRV_E_INST_ALREADY_EXISTS, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_E_INVALID_STATE, EDMA3_DRV_OPENED, edma3MemCpy(), edma3OpenResMgr(), EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_InitConfig::gblerrCb, EDMA3_DRV_Instance::gblerrCbParams, EDMA3_DRV_InitConfig::gblerrData, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_InitConfig::isMaster, EDMA3_DRV_Instance::isMaster, EDMA3_DRV_Object::numOpens, EDMA3_DRV_GblConfigParams::numRegions, EDMA3_DRV_Instance::pDrvObjectHandle, EDMA3_DRV_Instance::regionId, EDMA3_DRV_InitConfig::regionId, EDMA3_DRV_Instance::shadowRegs, and EDMA3_DRV_Object::state.

+ +
+

+

+
Generated on Thu Oct 16 16:17:55 2008 for EDMA3 Driver by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/drv/docs/html/group__edma3drvtransfersetupopt.html b/packages/ti/sdo/edma3/drv/docs/html/group__edma3drvtransfersetupopt.html new file mode 100644 index 0000000..2c779fa --- /dev/null +++ b/packages/ti/sdo/edma3/drv/docs/html/group__edma3drvtransfersetupopt.html @@ -0,0 +1,1133 @@ + + +EDMA3 Driver: EDMA3 Driver Optional Setup for EDMA + + + + + +
+

EDMA3 Driver Optional Setup for EDMA
+ +[EDMA3 Driver Interface Definition] +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Data Structures

struct  EDMA3_DRV_ParamentryRegs
 EDMA3 PaRAM Set. More...
struct  EDMA3_DRV_PaRAMRegs
 EDMA3 Parameter RAM Set in User Configurable format. More...
struct  EDMA3_DRV_EvtQuePriority
 Event queue priorities setup. More...

Enumerations

enum  EDMA3_DRV_PaRAMEntry {
+  EDMA3_DRV_PARAM_ENTRY_OPT = 0, +
+  EDMA3_DRV_PARAM_ENTRY_SRC = 1, +
+  EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT = 2, +
+  EDMA3_DRV_PARAM_ENTRY_DST = 3, +
+  EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX = 4, +
+  EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD = 5, +
+  EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX = 6, +
+  EDMA3_DRV_PARAM_ENTRY_CCNT = 7 +
+ }
 PaRAM Set Entry type. More...
enum  EDMA3_DRV_PaRAMField {
+  EDMA3_DRV_PARAM_FIELD_OPT = 0, +
+  EDMA3_DRV_PARAM_FIELD_SRCADDR = 1, +
+  EDMA3_DRV_PARAM_FIELD_ACNT = 2, +
+  EDMA3_DRV_PARAM_FIELD_BCNT = 3, +
+  EDMA3_DRV_PARAM_FIELD_DESTADDR = 4, +
+  EDMA3_DRV_PARAM_FIELD_SRCBIDX = 5, +
+  EDMA3_DRV_PARAM_FIELD_DESTBIDX = 6, +
+  EDMA3_DRV_PARAM_FIELD_LINKADDR = 7, +
+  EDMA3_DRV_PARAM_FIELD_BCNTRELOAD = 8, +
+  EDMA3_DRV_PARAM_FIELD_SRCCIDX = 9, +
+  EDMA3_DRV_PARAM_FIELD_DESTCIDX = 10, +
+  EDMA3_DRV_PARAM_FIELD_CCNT = 11 +
+ }
 PaRAM Set Field type. More...
enum  EDMA3_DRV_IoctlCmd {
+  EDMA3_DRV_IOCTL_MIN_IOCTL = 0, +
+  EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION, +
+  EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION, +
+  EDMA3_DRV_IOCTL_MAX_IOCTL +
+ }
 EDMA3 Driver IOCTL commands. More...

Functions

EDMA3_DRV_Result EDMA3_DRV_setQdmaTrigWord (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_RM_QdmaTrigWord trigWord)
 Assign a Trigger Word to the specified QDMA channel.
EDMA3_DRV_Result EDMA3_DRV_setPaRAM (EDMA3_DRV_Handle hEdma, unsigned int lCh, const EDMA3_DRV_PaRAMRegs *newPaRAM)
 Copy the user specified PaRAM Set onto the PaRAM Set associated with the logical channel (DMA/QDMA/Link).
EDMA3_DRV_Result EDMA3_DRV_getPaRAM (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMRegs *currPaRAM)
 Retrieve existing PaRAM set associated with specified logical channel (DMA/QDMA/Link).
EDMA3_DRV_Result EDMA3_DRV_setPaRAMEntry (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMEntry paRAMEntry, unsigned int newPaRAMEntryVal)
 Set a particular PaRAM set entry of the specified PaRAM set.
EDMA3_DRV_Result EDMA3_DRV_getPaRAMEntry (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMEntry paRAMEntry, unsigned int *paRAMEntryVal)
 Get a particular PaRAM set entry of the specified PaRAM set.
EDMA3_DRV_Result EDMA3_DRV_setPaRAMField (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMField paRAMField, unsigned int newPaRAMFieldVal)
 Set a particular PaRAM set field of the specified PaRAM set.
EDMA3_DRV_Result EDMA3_DRV_getPaRAMField (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMField paRAMField, unsigned int *currPaRAMFieldVal)
 Get a particular PaRAM set field of the specified PaRAM set.
EDMA3_DRV_Result EDMA3_DRV_setEvtQPriority (EDMA3_DRV_Handle hEdma, const EDMA3_DRV_EvtQuePriority *evtQPriObj)
 Sets EDMA TC priority.
EDMA3_DRV_Result EDMA3_DRV_mapChToEvtQ (EDMA3_DRV_Handle hEdma, unsigned int channelId, EDMA3_RM_EventQueue eventQ)
 Associate Channel to Event Queue.
EDMA3_DRV_Result EDMA3_DRV_getMapChToEvtQ (EDMA3_DRV_Handle hEdma, unsigned int channelId, unsigned int *mappedEvtQ)
 Get the Event Queue mapped to the specified DMA/QDMA channel.
EDMA3_DRV_Result EDMA3_DRV_setCCRegister (EDMA3_DRV_Handle hEdma, unsigned int regOffset, unsigned int newRegValue)
 Set the Channel Controller (CC) Register value.
EDMA3_DRV_Result EDMA3_DRV_getCCRegister (EDMA3_DRV_Handle hEdma, unsigned int regOffset, unsigned int *regValue)
 Get the Channel Controller (CC) Register value.
EDMA3_DRV_Result EDMA3_DRV_waitAndClearTcc (EDMA3_DRV_Handle hEdma, unsigned int tccNo)
 Wait for a transfer completion interrupt to occur and clear it.
EDMA3_DRV_Result EDMA3_DRV_checkAndClearTcc (EDMA3_DRV_Handle hEdma, unsigned int tccNo, unsigned short *tccStatus)
 Returns the status of a previously initiated transfer.
EDMA3_DRV_Result EDMA3_DRV_getPaRAMPhyAddr (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int *paramPhyAddr)
 Get the PaRAM Set Physical Address associated with a logical channel.
EDMA3_DRV_Result EDMA3_DRV_Ioctl (EDMA3_DRV_Handle hEdma, EDMA3_DRV_IoctlCmd cmd, void *cmdArg, void *param)
 EDMA3 Driver IOCTL.
EDMA3_DRV_Handle EDMA3_DRV_getInstHandle (unsigned int phyCtrllerInstId, EDMA3_RM_RegionId regionId, EDMA3_DRV_Result *errorCode)
 Return the previously opened EDMA3 Driver Instance handle.
+

Detailed Description

+Transfer.

+The Optional EDMA transfer related Interface of the EDMA3 Driver

Enumeration Type Documentation

+ +
+
+ + + + +
enum EDMA3_DRV_IoctlCmd
+
+
+ +

+EDMA3 Driver IOCTL commands. +

+

Enumerator:
+ + + +
EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION  +PaRAM Sets will be cleared OR will not be cleared during allocation, depending upon this option.

+For e.g., To clear the PaRAM Sets during allocation, cmdArg = (void *)1;

+To NOT clear the PaRAM Sets during allocation, cmdArg = (void *)0;

+For all other values, it will return error.

+By default, PaRAM Sets will be cleared during allocation. Note: Since this enum can change the behavior how the resources are initialized during their allocation, user is adviced to not use this command while allocating the resources. User should first change the behavior of resources' initialization and then should use start allocating resources.

EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION  +To check whether PaRAM Sets will be cleared or not during allocation. If the value read is '1', it means that PaRAM Sets are getting cleared during allocation. If the value read is '0', it means that PaRAM Sets are NOT getting cleared during allocation.

+For e.g., unsigned short isParamClearingDone; cmdArg =

+
+ +
+

+ +

+
+ + + + +
enum EDMA3_DRV_PaRAMEntry
+
+
+ +

+PaRAM Set Entry type. +

+Use this enum to set or get any of the 8 DWords(unsigned int) within a Parameter RAM set

Enumerator:
+ + + + + + + + + +
EDMA3_DRV_PARAM_ENTRY_OPT  +The OPT field (Offset Address 0x0 Bytes)
EDMA3_DRV_PARAM_ENTRY_SRC  +The SRC field (Offset Address 0x4 Bytes)
EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT  +The (ACNT+BCNT) field (Offset Address 0x8 Bytes)
EDMA3_DRV_PARAM_ENTRY_DST  +The DST field (Offset Address 0xC Bytes)
EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX  +The (SRCBIDX+DSTBIDX) field (Offset Address 0x10 Bytes)
EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD  +The (LINK+BCNTRLD) field (Offset Address 0x14 Bytes)
EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX  +The (SRCCIDX+DSTCIDX) field (Offset Address 0x18 Bytes)
EDMA3_DRV_PARAM_ENTRY_CCNT  +The (CCNT+RSVD) field (Offset Address 0x1C Bytes)
+
+ +
+

+ +

+
+ + + + +
enum EDMA3_DRV_PaRAMField
+
+
+ +

+PaRAM Set Field type. +

+Use this enum to set or get any of the PaRAM set fields

Enumerator:
+ + + + + + + + + + + + + +
EDMA3_DRV_PARAM_FIELD_OPT  +OPT field of PaRAM Set
EDMA3_DRV_PARAM_FIELD_SRCADDR  +Starting byte address of Source For FIFO mode, srcAddr must be a 256-bit aligned address.
EDMA3_DRV_PARAM_FIELD_ACNT  +Number of bytes in each Array (ACNT).
EDMA3_DRV_PARAM_FIELD_BCNT  +Number of Arrays in each Frame (BCNT).
EDMA3_DRV_PARAM_FIELD_DESTADDR  +Starting byte address of destination For FIFO mode, destAddr must be a 256-bit aligned address.
EDMA3_DRV_PARAM_FIELD_SRCBIDX  +Index between consec. arrays of a Source Frame (SRCBIDX) If SAM is set to 1 (via channelOptions) then srcInterArrIndex should be an even multiple of 32 bytes.
EDMA3_DRV_PARAM_FIELD_DESTBIDX  +Index between consec. arrays of a Destination Frame (DSTBIDX) If DAM is set to 1 (via channelOptions) then destInterArrIndex should be an even multiple of 32 bytes.
EDMA3_DRV_PARAM_FIELD_LINKADDR  +Address for linking (AutoReloading of a PaRAM Set) This must point to a valid aligned 32-byte PaRAM set A value of 0xFFFF means no linking Linking is especially useful for use with ping-pong buffers and circular buffers.
EDMA3_DRV_PARAM_FIELD_BCNTRELOAD  +Reload value of the numArrInFrame (BCNT) Relevant only for A-sync transfers.
EDMA3_DRV_PARAM_FIELD_SRCCIDX  +Index between consecutive frames of a Source Block (SRCCIDX).
EDMA3_DRV_PARAM_FIELD_DESTCIDX  +Index between consecutive frames of a Dest Block (DSTCIDX).
EDMA3_DRV_PARAM_FIELD_CCNT  +Number of Frames in a block (CCNT).
+
+ +
+

+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Result EDMA3_DRV_checkAndClearTcc (EDMA3_DRV_Handle  hEdma,
unsigned int  tccNo,
unsigned short *  tccStatus 
)
+
+
+ +

+Returns the status of a previously initiated transfer. +

+This is a non-blocking function that returns the status of a previously initiated transfer, based on the IPR/IPRH bit. This bit corresponds to the tccNo specified by the user. It clears the corresponding bit, if SET, while returning also.

+

Parameters:
+ + + + +
hEdma [IN] Handle to the EDMA Driver Instance
tccNo [IN] TCC, specific to which the function checks the status of the IPR/IPRH bit.
tccStatus [IN/OUT] Status of the transfer is returned here. Returns "TRUE" if the transfer has completed (IPR/IPRH bit SET), "FALSE" if the transfer has not completed successfully (IPR/IPRH bit NOT SET).
+
+
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
+
Note:
This function is re-entrant for different tccNo.
+ +

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numTccs, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Instance::regionId.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Result EDMA3_DRV_getCCRegister (EDMA3_DRV_Handle  hEdma,
unsigned int  regOffset,
unsigned int *  regValue 
)
+
+
+ +

+Get the Channel Controller (CC) Register value. +

+

Parameters:
+ + + + +
hEdma [IN] Handle to the EDMA Driver Instance
regOffset [IN] CC Register offset whose value is needed
regValue [IN/OUT] CC Register Value
+
+
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
+
Note:
This function is re-entrant.
+ +

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, and EDMA3_DRV_Instance::pDrvObjectHandle.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Handle EDMA3_DRV_getInstHandle (unsigned int  phyCtrllerInstId,
EDMA3_RM_RegionId  regionId,
EDMA3_DRV_Result *  errorCode 
)
+
+
+ +

+Return the previously opened EDMA3 Driver Instance handle. +

+This API is used to return the previously opened EDMA3 Driver's Instance Handle (region specific), which could be used to call other EDMA3 Driver APIs. Since EDMA3 Driver does not allow multiple instances, for a single shadow region, this API is provided. This API is meant for users who DO NOT want to / could not open a new Driver Instance and hence re-use the existing Driver Instance to allocate EDMA3 resources and use various other EDMA3 Driver APIs.

+In case the Driver Instance is not yet opened, NULL is returned as the function return value whereas EDMA3_DRV_E_INST_NOT_OPENED is returned in the errorCode.

+

Parameters:
+ + + + +
phyCtrllerInstId [IN] EDMA3 Controller Instance Id (Hardware instance id, starting from 0).
regionId [IN] Shadow Region id for which the previously opened driver's instance handle is required.
errorCode [OUT] Error code while returning Driver Instance Handle.
+
+
Returns:
EDMA3_DRV_Handle : If successful, this API will return the driver's instance handle.
+
Note:
1) This API returns the previously opened EDMA3 Driver's Instance handle. The instance, if exists, could have been opened by some other user (most probably) or may be by the same user calling this API. If it was opened by some other user, then that user can very well close this instance anytime, without even knowing that the same instance handle is being used by other users as well. In that case, the handle becomes INVALID and user has to open a valid driver instance for his/her use.
+2) This function is re-entrant. +

References EDMA3_DRV_E_INST_NOT_OPENED, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::numRegions, and EDMA3_DRV_Instance::pDrvObjectHandle.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Result EDMA3_DRV_getMapChToEvtQ (EDMA3_DRV_Handle  hEdma,
unsigned int  channelId,
unsigned int *  mappedEvtQ 
)
+
+
+ +

+Get the Event Queue mapped to the specified DMA/QDMA channel. +

+

Parameters:
+ + + + +
hEdma [IN] Handle to the EDMA Driver Instance
channelId [IN] Logical Channel whose associated Event Queue is needed
mappedEvtQ [IN/OUT] The Event Queue which is mapped to the DMA/QDMA channel
+
+
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
+
Note:
This function is re-entrant.
+ +

References EDMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_DMAQNUM_CLR_MASK, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_QDMAQNUM_CLR_MASK, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, and EDMA3_DRV_Instance::pDrvObjectHandle.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Result EDMA3_DRV_getPaRAM (EDMA3_DRV_Handle  hEdma,
unsigned int  lCh,
EDMA3_DRV_PaRAMRegs *  currPaRAM 
)
+
+
+ +

+Retrieve existing PaRAM set associated with specified logical channel (DMA/QDMA/Link). +

+

Parameters:
+ + + + +
hEdma [IN] Handle to the EDMA Instance object
lCh [IN] Logical Channel whose PaRAM set is requested
currPaRAM [IN/OUT] User gets the existing PaRAM here
+
+
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
+
Note:
This function is re-entrant.
+ +

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, edma3MemCpy(), EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Result EDMA3_DRV_getPaRAMEntry (EDMA3_DRV_Handle  hEdma,
unsigned int  lCh,
EDMA3_DRV_PaRAMEntry  paRAMEntry,
unsigned int *  paRAMEntryVal 
)
+
+
+ +

+Get a particular PaRAM set entry of the specified PaRAM set. +

+

Parameters:
+ + + + + +
hEdma [IN] Handle to the EDMA Driver Instance
lCh [IN] Logical Channel bound to the Parameter RAM set whose specified field value is needed
paRAMEntry [IN] Specify the PaRAM set entry which needs to be obtained
paRAMEntryVal [IN/OUT] The value of the field is returned here
+
+
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
+
Note:
This function is re-entrant.
+ +

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_PARAM_ENTRY_CCNT, EDMA3_DRV_PARAM_ENTRY_OPT, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Result EDMA3_DRV_getPaRAMField (EDMA3_DRV_Handle  hEdma,
unsigned int  lCh,
EDMA3_DRV_PaRAMField  paRAMField,
unsigned int *  currPaRAMFieldVal 
)
+
+
+ +

+Get a particular PaRAM set field of the specified PaRAM set. +

+

Parameters:
+ + + + + +
hEdma [IN] Handle to the EDMA Driver Instance
lCh [IN] Logical Channel bound to the PaRAM set whose specified field value is needed
paRAMField [IN] Specify the PaRAM set field which needs to be obtained
currPaRAMFieldVal [IN/OUT] The value of the field is returned here
+
+
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
+
Note:
This function is re-entrant.
+ +

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT, EDMA3_DRV_PARAM_ENTRY_CCNT, EDMA3_DRV_PARAM_ENTRY_DST, EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD, EDMA3_DRV_PARAM_ENTRY_OPT, EDMA3_DRV_PARAM_ENTRY_SRC, EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX, EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX, EDMA3_DRV_PARAM_FIELD_ACNT, EDMA3_DRV_PARAM_FIELD_BCNT, EDMA3_DRV_PARAM_FIELD_BCNTRELOAD, EDMA3_DRV_PARAM_FIELD_CCNT, EDMA3_DRV_PARAM_FIELD_DESTADDR, EDMA3_DRV_PARAM_FIELD_DESTBIDX, EDMA3_DRV_PARAM_FIELD_DESTCIDX, EDMA3_DRV_PARAM_FIELD_LINKADDR, EDMA3_DRV_PARAM_FIELD_OPT, EDMA3_DRV_PARAM_FIELD_SRCADDR, EDMA3_DRV_PARAM_FIELD_SRCBIDX, EDMA3_DRV_PARAM_FIELD_SRCCIDX, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Result EDMA3_DRV_getPaRAMPhyAddr (EDMA3_DRV_Handle  hEdma,
unsigned int  lCh,
unsigned int *  paramPhyAddr 
)
+
+
+ +

+Get the PaRAM Set Physical Address associated with a logical channel. +

+This function returns the PaRAM Set Phy Address (unsigned 32 bits). The returned address could be used by the advanced users to program the PaRAM Set directly without using any APIs.

+Least significant 16 bits of this address could be used to program the LINK field in the PaRAM Set. Users which program the LINK field directly SHOULD use this API to get the associated PaRAM Set address with the LINK channel.

+

Parameters:
+ + + + +
hEdma [IN] Handle to the EDMA Driver Instance
lCh [IN] Logical Channel for which the PaRAM set physical address is required
paramPhyAddr [IN/OUT] PaRAM Set physical address is returned here.
+
+
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
+
Note:
This function is re-entrant.
+ +

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Result EDMA3_DRV_Ioctl (EDMA3_DRV_Handle  hEdma,
EDMA3_DRV_IoctlCmd  cmd,
void *  cmdArg,
void *  param 
)
+
+
+ +

+EDMA3 Driver IOCTL. +

+This function provides IOCTL functionality for EDMA3 Driver.

+

Parameters:
+ + + + + +
hEdma [IN] Handle to the EDMA Driver Instance
cmd [IN] IOCTL command to be performed
cmdArg [IN/OUT] IOCTL command argument (if any)
param [IN/OUT] Device/Cmd specific argument
+
+
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
+
Note:
For 'EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION', this function is re-entrant. For 'EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION', this function is re-entrant for different EDMA3 Driver Instances (handles).
+This function provides IOCTL functionality for EDMA3 Driver.

+

Parameters:
+ + + + + +
hEdma [IN] Handle to the EDMA Driver Instance
cmd [IN] IOCTL command to be performed
cmdArg [IN/OUT] IOCTL command argument (if any)
param [IN/OUT] Device/Cmd specific argument
+
+
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ +

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION, EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION, and EDMA3_DRV_Instance::resMgrInstance.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Result EDMA3_DRV_mapChToEvtQ (EDMA3_DRV_Handle  hEdma,
unsigned int  channelId,
EDMA3_RM_EventQueue  eventQ 
)
+
+
+ +

+Associate Channel to Event Queue. +

+

Parameters:
+ + + + +
hEdma [IN] Handle to the EDMA Driver Instance
channelId [IN] Logical Channel to which the Event Queue is to be mapped
eventQ [IN] The Event Queue which is to be mapped to the DMA channel
+
+
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
+
Note:
There should not be any data transfer going on while setting the mapping. Results could be unpredictable.
+This function disables the global interrupts while modifying the global CC Registers, to make it re-entrant. +

References EDMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_DMAQNUM_CLR_MASK, EDMA3_DRV_DMAQNUM_SET_MASK, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_QDMAQNUM_CLR_MASK, EDMA3_DRV_QDMAQNUM_SET_MASK, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numEvtQueue, and EDMA3_DRV_Instance::pDrvObjectHandle.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Result EDMA3_DRV_setCCRegister (EDMA3_DRV_Handle  hEdma,
unsigned int  regOffset,
unsigned int  newRegValue 
)
+
+
+ +

+Set the Channel Controller (CC) Register value. +

+

Parameters:
+ + + + +
hEdma [IN] Handle to the EDMA Driver Instance
regOffset [IN] CC Register offset whose value needs to be set
newRegValue [IN] New CC Register Value
+
+
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
+
Note:
This function is non re-entrant for users using the same EDMA handle i.e. working on the same shadow region. Before modifying a register, it tries to acquire a semaphore (Driver instance specific), to protect simultaneous modification of the same register by two different users. After the successful change, it releases the semaphore. For users working on different shadow regions, thus different EDMA handles, this function is re-entrant.
+ +

+Take the instance specific semaphore, to prevent simultaneous access to the shared resources. +

References EDMA3_DRV_Instance::drvSemHandle, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, and EDMA3_DRV_Instance::pDrvObjectHandle.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Result EDMA3_DRV_setEvtQPriority (EDMA3_DRV_Handle  hEdma,
const EDMA3_DRV_EvtQuePriority *  evtQPriObj 
)
+
+
+ +

+Sets EDMA TC priority. +

+User can program the priority of the Event Queues at a system-wide level. This means that the user can set the priority of an IO initiated by either of the TCs (Transfer Ctrllers) relative to IO initiated by the other bus masters on the device (ARM, DSP, USB, etc)

+

Parameters:
+ + + +
hEdma [IN] Handle to the EDMA Driver Instance
evtQPriObj [IN] Priority of the Event Queues
+
+
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
+
Note:
This function disables the global interrupts while modifying the global CC Registers, to make it re-entrant.
+ +

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_QPRIORITY_MAX_VAL, EDMA3_DRV_EvtQuePriority::evtQPri, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, and EDMA3_DRV_Instance::pDrvObjectHandle.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Result EDMA3_DRV_setPaRAM (EDMA3_DRV_Handle  hEdma,
unsigned int  lCh,
const EDMA3_DRV_PaRAMRegs *  newPaRAM 
)
+
+
+ +

+Copy the user specified PaRAM Set onto the PaRAM Set associated with the logical channel (DMA/QDMA/Link). +

+This API takes a PaRAM Set as input and copies it onto the actual PaRAM Set associated with the logical channel. OPT field of the PaRAM Set is written first and the CCNT field is written last.

+Caution: It should be used carefully when programming the QDMA channels whose trigger words are not CCNT field.

+

Parameters:
+ + + + +
hEdma [IN] Handle to the EDMA Instance object
lCh [IN] Logical Channel for which new PaRAM set is specified
newPaRAM [IN] Parameter RAM set to be copied onto existing PaRAM
+
+
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
+
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.
+ +

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, edma3MemCpy(), EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Result EDMA3_DRV_setPaRAMEntry (EDMA3_DRV_Handle  hEdma,
unsigned int  lCh,
EDMA3_DRV_PaRAMEntry  paRAMEntry,
unsigned int  newPaRAMEntryVal 
)
+
+
+ +

+Set a particular PaRAM set entry of the specified PaRAM set. +

+

Parameters:
+ + + + + +
hEdma [IN] Handle to the EDMA Driver Instance
lCh [IN] Logical Channel bound to the Parameter RAM set whose specified field needs to be set
paRAMEntry [IN] Specify the PaRAM set entry which needs to be set
newPaRAMEntryVal [IN] The new field setting
+
+
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
+
Note:
This API should be used while setting the PaRAM set entry for QDMA channels. If EDMA3_DRV_setPaRAMField () used, it will trigger the QDMA channel before complete PaRAM set entry is written. For DMA channels, no such constraint is there.
+This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. +

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_PARAM_ENTRY_CCNT, EDMA3_DRV_PARAM_ENTRY_OPT, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Result EDMA3_DRV_setPaRAMField (EDMA3_DRV_Handle  hEdma,
unsigned int  lCh,
EDMA3_DRV_PaRAMField  paRAMField,
unsigned int  newPaRAMFieldVal 
)
+
+
+ +

+Set a particular PaRAM set field of the specified PaRAM set. +

+

Parameters:
+ + + + + +
hEdma [IN] Handle to the EDMA Driver Instance
lCh [IN] Logical Channel bound to the PaRAM set whose specified field needs to be set
paRAMField [IN] Specify the PaRAM set field which needs to be set
newPaRAMFieldVal [IN] The new field setting
+
+
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
+
Note:
This API CANNOT be used while setting the PaRAM set field for QDMA channels. It can trigger the QDMA channel before complete PaRAM set ENTRY (4-bytes field) is written (for eg, as soon one sets the ACNT field for QDMA channel, transfer is started, before one modifies the BCNT field). For DMA channels, no such constraint is there.
+This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. +

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT, EDMA3_DRV_PARAM_ENTRY_CCNT, EDMA3_DRV_PARAM_ENTRY_DST, EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD, EDMA3_DRV_PARAM_ENTRY_OPT, EDMA3_DRV_PARAM_ENTRY_SRC, EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX, EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX, EDMA3_DRV_PARAM_FIELD_ACNT, EDMA3_DRV_PARAM_FIELD_BCNT, EDMA3_DRV_PARAM_FIELD_BCNTRELOAD, EDMA3_DRV_PARAM_FIELD_CCNT, EDMA3_DRV_PARAM_FIELD_DESTADDR, EDMA3_DRV_PARAM_FIELD_DESTBIDX, EDMA3_DRV_PARAM_FIELD_DESTCIDX, EDMA3_DRV_PARAM_FIELD_LINKADDR, EDMA3_DRV_PARAM_FIELD_OPT, EDMA3_DRV_PARAM_FIELD_SRCADDR, EDMA3_DRV_PARAM_FIELD_SRCBIDX, EDMA3_DRV_PARAM_FIELD_SRCCIDX, EDMA3_DRV_QDMA_CHANNEL_0, EDMA3_DRV_QDMA_CHANNEL_7, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Result EDMA3_DRV_setQdmaTrigWord (EDMA3_DRV_Handle  hEdma,
unsigned int  lCh,
EDMA3_RM_QdmaTrigWord  trigWord 
)
+
+
+ +

+Assign a Trigger Word to the specified QDMA channel. +

+This API sets the Trigger word for the specific QDMA channel in the QCHMAP Register. Default QDMA trigger word is CCNT.

+

Parameters:
+ + + + +
hEdma [IN] Handle to the EDMA Instance object
lCh [IN] QDMA Channel which needs to be assigned the Trigger Word
trigWord [IN] The Trigger Word for the QDMA channel. Trigger Word is the word in the PaRAM Register Set which, when written to by CPU, will start the QDMA transfer automatically.
+
+
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
+
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.
+ +

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_QCH_TRWORD_CLR_MASK, EDMA3_DRV_QCH_TRWORD_SET_MASK, EDMA3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, and EDMA3_DRV_Instance::pDrvObjectHandle.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Result EDMA3_DRV_waitAndClearTcc (EDMA3_DRV_Handle  hEdma,
unsigned int  tccNo 
)
+
+
+ +

+Wait for a transfer completion interrupt to occur and clear it. +

+This is a blocking function that returns when the IPR/IPRH bit corresponding to the tccNo specified, is SET. It clears the corresponding bit while returning also.

+This function waits for the specific bit indefinitely in a tight loop, with out any delay in between. USE IT CAUTIOUSLY.

+

Parameters:
+ + + +
hEdma [IN] Handle to the EDMA Driver Instance
tccNo [IN] TCC, specific to which the function waits on a IPR/IPRH bit.
+
+
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
+
Note:
This function is re-entrant for different tccNo.
+ +

+Bit found SET, transfer is completed, clear the pending interrupt and return.

+Bit found SET, transfer is completed, clear the pending interrupt and return. +

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numTccs, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Instance::regionId.

+ +
+

+

+
Generated on Thu Oct 16 16:17:56 2008 for EDMA3 Driver by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/drv/docs/html/group__edma3drvtransfersetuptype.html b/packages/ti/sdo/edma3/drv/docs/html/group__edma3drvtransfersetuptype.html new file mode 100644 index 0000000..f1049a6 --- /dev/null +++ b/packages/ti/sdo/edma3/drv/docs/html/group__edma3drvtransfersetuptype.html @@ -0,0 +1,1165 @@ + + +EDMA3 Driver: EDMA3 Driver Typical EDMA Transfer Setup + + + + + +
+

EDMA3 Driver Typical EDMA Transfer Setup
+ +[EDMA3 Driver Interface Definition] +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Data Structures

struct  EDMA3_DRV_ChainOptions
 Structure to be used to configure interrupt generation and chaining options. More...

Enumerations

enum  EDMA3_DRV_OptField {
+  EDMA3_DRV_OPT_FIELD_SAM = 0, +
+  EDMA3_DRV_OPT_FIELD_DAM = 1, +
+  EDMA3_DRV_OPT_FIELD_SYNCDIM = 2, +
+  EDMA3_DRV_OPT_FIELD_STATIC = 3, +
+  EDMA3_DRV_OPT_FIELD_FWID = 4, +
+  EDMA3_DRV_OPT_FIELD_TCCMODE = 5, +
+  EDMA3_DRV_OPT_FIELD_TCC = 6, +
+  EDMA3_DRV_OPT_FIELD_TCINTEN = 7, +
+  EDMA3_DRV_OPT_FIELD_ITCINTEN = 8, +
+  EDMA3_DRV_OPT_FIELD_TCCHEN = 9, +
+  EDMA3_DRV_OPT_FIELD_ITCCHEN = 10 +
+ }
 OPT Field Offset. More...
enum  EDMA3_DRV_AddrMode {
+  EDMA3_DRV_ADDR_MODE_INCR = 0, +
+  EDMA3_DRV_ADDR_MODE_FIFO = 1 +
+ }
 EDMA Addressing modes. More...
enum  EDMA3_DRV_SyncType {
+  EDMA3_DRV_SYNC_A = 0, +
+  EDMA3_DRV_SYNC_AB = 1 +
+ }
 EDMA Transfer Synchronization type. More...
enum  EDMA3_DRV_StaticMode {
+  EDMA3_DRV_STATIC_DIS = 0, +
+  EDMA3_DRV_STATIC_EN = 1 +
+ }
 True/False: PaRAM set is Static or not. A Static PaRAM set is updated or linked after TR is submitted. More...
enum  EDMA3_DRV_FifoWidth {
+  EDMA3_DRV_W8BIT = 0, +
+  EDMA3_DRV_W16BIT = 1, +
+  EDMA3_DRV_W32BIT = 2, +
+  EDMA3_DRV_W64BIT = 3, +
+  EDMA3_DRV_W128BIT = 4, +
+  EDMA3_DRV_W256BIT = 5 +
+ }
 EDMA3 FIFO width. More...
enum  EDMA3_DRV_TccMode {
+  EDMA3_DRV_TCCMODE_NORMAL = 0, +
+  EDMA3_DRV_TCCMODE_EARLY = 1 +
+ }
 Transfer complete code mode. Indicates the point at which a transfer is considered completed for chaining and interrupt generation. More...
enum  EDMA3_DRV_TcintEn {
+  EDMA3_DRV_TCINTEN_DIS = 0, +
+  EDMA3_DRV_TCINTEN_EN = 1 +
+ }
 Transfer complete interrupt enable. More...
enum  EDMA3_DRV_ItcintEn {
+  EDMA3_DRV_ITCINTEN_DIS = 0, +
+  EDMA3_DRV_ITCINTEN_EN = 1 +
+ }
 Intermediate Transfer complete interrupt enable. More...
enum  EDMA3_DRV_TcchEn {
+  EDMA3_DRV_TCCHEN_DIS = 0, +
+  EDMA3_DRV_TCCHEN_EN = 1 +
+ }
 Transfer complete chaining enable. More...
enum  EDMA3_DRV_ItcchEn {
+  EDMA3_DRV_ITCCHEN_DIS = 0, +
+  EDMA3_DRV_ITCCHEN_EN = 1 +
+ }
 Intermediate Transfer complete chaining enable. More...
enum  EDMA3_DRV_TrigMode {
+  EDMA3_DRV_TRIG_MODE_MANUAL = 0, +
+  EDMA3_DRV_TRIG_MODE_QDMA = 1, +
+  EDMA3_DRV_TRIG_MODE_EVENT = 2, +
+  EDMA3_DRV_TRIG_MODE_NONE = 3 +
+ }
 EDMA Trigger Mode Selection. More...

Functions

EDMA3_DRV_Result EDMA3_DRV_setOptField (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_OptField optField, unsigned int newOptFieldVal)
 Set a particular OPT field in the PaRAM set associated with the logical channel 'lCh'.
EDMA3_DRV_Result EDMA3_DRV_getOptField (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_OptField optField, unsigned int *optFieldVal)
 Get a particular OPT field in the PaRAM set associated with the logical channel 'lCh'.
EDMA3_DRV_Result EDMA3_DRV_setSrcParams (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int srcAddr, EDMA3_DRV_AddrMode addrMode, EDMA3_DRV_FifoWidth fifoWidth)
 DMA source parameters setup.
EDMA3_DRV_Result EDMA3_DRV_setDestParams (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int destAddr, EDMA3_DRV_AddrMode addrMode, EDMA3_DRV_FifoWidth fifoWidth)
 DMA Destination parameters setup.
EDMA3_DRV_Result EDMA3_DRV_setSrcIndex (EDMA3_DRV_Handle hEdma, unsigned int lCh, int srcBIdx, int srcCIdx)
 DMA source index setup.
EDMA3_DRV_Result EDMA3_DRV_setDestIndex (EDMA3_DRV_Handle hEdma, unsigned int lCh, int destBIdx, int destCIdx)
 DMA destination index setup.
EDMA3_DRV_Result EDMA3_DRV_setTransferParams (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int aCnt, unsigned int bCnt, unsigned int cCnt, unsigned int bCntReload, EDMA3_DRV_SyncType syncType)
 DMA transfer parameters setup.
EDMA3_DRV_Result EDMA3_DRV_chainChannel (EDMA3_DRV_Handle hEdma, unsigned int lCh1, unsigned int lCh2, const EDMA3_DRV_ChainOptions *chainOptions)
 Chain the two specified channels.
EDMA3_DRV_Result EDMA3_DRV_unchainChannel (EDMA3_DRV_Handle hEdma, unsigned int lCh)
 Unchain the two channels.
EDMA3_DRV_Result EDMA3_DRV_enableTransfer (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_TrigMode trigMode)
 Start EDMA transfer on the specified channel.
EDMA3_DRV_Result EDMA3_DRV_disableTransfer (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_TrigMode trigMode)
 Disable DMA transfer on the specified channel.
+

Detailed Description

+The typical EDMA transfer related Interface of the EDMA3 Driver

Enumeration Type Documentation

+ +
+
+ + + + +
enum EDMA3_DRV_AddrMode
+
+
+ +

+EDMA Addressing modes. +

+The EDMA3 TC supports two addressing modes

    +
  1. Increment transfer
  2. FIFO transfer
+

+The SAM (Source Addressing Mode) and the DAM (Destination Addressing Mode) can be independently set to either of the two via the OPT register.

Enumerator:
+ + + +
EDMA3_DRV_ADDR_MODE_INCR  +Increment (INCR) mode. Source addressing within an array increments. Source is not a FIFO.
EDMA3_DRV_ADDR_MODE_FIFO  +FIFO mode. Source addressing within an array wraps around upon reaching FIFO width.
+
+ +
+

+ +

+
+ + + + +
enum EDMA3_DRV_FifoWidth
+
+
+ +

+EDMA3 FIFO width. +

+The user can set the width of the FIFO using this enum. This is done via the OPT register. This is valid only if the EDMA3_DRV_ADDR_MODE_FIFO value is used for the enum EDMA3_DRV_AddrMode.

Enumerator:
+ + + + + + + +
EDMA3_DRV_W8BIT  +FIFO width is 8-bit.
EDMA3_DRV_W16BIT  +FIFO width is 16-bit.
EDMA3_DRV_W32BIT  +FIFO width is 32-bit.
EDMA3_DRV_W64BIT  +FIFO width is 64-bit.
EDMA3_DRV_W128BIT  +FIFO width is 128-bit.
EDMA3_DRV_W256BIT  +FIFO width is 256-bit.
+
+ +
+

+ +

+
+ + + + +
enum EDMA3_DRV_ItcchEn
+
+
+ +

+Intermediate Transfer complete chaining enable. +

+

Enumerator:
+ + + +
EDMA3_DRV_ITCCHEN_DIS  +Intermediate Transfer complete chaining is disabled
EDMA3_DRV_ITCCHEN_EN  +Intermediate transfer complete chaining is enabled. When enabled, the chained event register (CER/CERH) bit is set on every intermediate chained transfer completion (upon completion of every intermediate TR in the PaRAM set, except the final TR in the PaRAM set). The bit (position) set in CER or CERH is the TCC value specified.
+
+ +
+

+ +

+
+ + + + +
enum EDMA3_DRV_ItcintEn
+
+
+ +

+Intermediate Transfer complete interrupt enable. +

+

Enumerator:
+ + + +
EDMA3_DRV_ITCINTEN_DIS  +Intermediate Transfer complete interrupt is disabled
EDMA3_DRV_ITCINTEN_EN  +Intermediate transfer complete interrupt is enabled. When enabled, the interrupt pending register (IPR/IPRH) bit is set on every intermediate transfer completion (upon completion of every intermediate TR in the PaRAM set, except the final TR in the PaRAM set). The bit (position) set in IPR or IPRH is the TCC value specified. In order to generate a completion interrupt to the CPU, the corresponding IER [TCC] / IERH [TCC] bit must be set to 1.
+
+ +
+

+ +

+
+ + + + +
enum EDMA3_DRV_OptField
+
+
+ +

+OPT Field Offset. +

+Use this enum to set or get any of the Fields within an OPT of a Parameter RAM set.

Enumerator:
+ + + + + + + + + + + + +
EDMA3_DRV_OPT_FIELD_SAM  +Source addressing mode (INCR / FIFO) (Bit 0)
EDMA3_DRV_OPT_FIELD_DAM  +Destination addressing mode (INCR / FIFO) (Bit 1)
EDMA3_DRV_OPT_FIELD_SYNCDIM  +Transfer synchronization dimension (A-synchronized / AB-synchronized) (Bit 2)
EDMA3_DRV_OPT_FIELD_STATIC  +The STATIC field PaRAM set is static/non-static? (Bit 3)
EDMA3_DRV_OPT_FIELD_FWID  +FIFO Width. Applies if either SAM or DAM is set to FIFO mode. (Bitfield 8-10)
EDMA3_DRV_OPT_FIELD_TCCMODE  +Transfer complete code mode. Indicates the point at which a transfer is considered completed for chaining and interrupt generation. (Bit 11)
EDMA3_DRV_OPT_FIELD_TCC  +Transfer Complete Code (TCC). This 6-bit code is used to set the relevant bit in chaining enable register (CER[TCC]/CERH[TCC]) for chaining or in interrupt pending register (IPR[TCC]/IPRH[TCC]) for interrupts. (Bitfield 12-17)
EDMA3_DRV_OPT_FIELD_TCINTEN  +Transfer complete interrupt enable/disable. (Bit 20)
EDMA3_DRV_OPT_FIELD_ITCINTEN  +Intermediate transfer complete interrupt enable/disable. (Bit 21)
EDMA3_DRV_OPT_FIELD_TCCHEN  +Transfer complete chaining enable/disable (Bit 22)
EDMA3_DRV_OPT_FIELD_ITCCHEN  +Intermediate transfer completion chaining enable/disable (Bit 23)
+
+ +
+

+ +

+
+ + + + +
enum EDMA3_DRV_StaticMode
+
+
+ +

+True/False: PaRAM set is Static or not. A Static PaRAM set is updated or linked after TR is submitted. +

+

Enumerator:
+ + + +
EDMA3_DRV_STATIC_DIS  +PaRAM set is not Static. PaRAM set is updated or linked after TR is submitted. A value of 0 should be used for DMA channels and for nonfinal transfers in a linked list of QDMA transfers
EDMA3_DRV_STATIC_EN  +PaRAM set is Static. PaRAM set is not updated or linked after TR is submitted. A value of 1 should be used for isolated QDMA transfers or for the final transfer in a linked list of QDMA transfers.
+
+ +
+

+ +

+
+ + + + +
enum EDMA3_DRV_SyncType
+
+
+ +

+EDMA Transfer Synchronization type. +

+Two types of Synchronization of transfers are possible

    +
  1. A Synchronized
  2. AB Syncronized
+

+A Sync

    +
  1. Each Array is submitted as one TR
  2. (BCNT*CCNT) number of sync events are needed to completely service a PaRAM set. (Where BCNT = Num of Arrays in a Frame; CCNT = Num of Frames in a Block)
  3. (S/D)CIDX = (Addr of First array in next frame) minus (Addr of Last array in present frame) (Where CIDX is the Inter-Frame index)
+

+

    +
  • AB Sync
      +
    1. Each Frame is submitted as one TR
    2. Only CCNT number of sync events are needed to completely service a PaRAM set
    3. (S/D)CIDX = (Addr of First array in next frame) minus (Addr of First array of present frame)
    +
+

+

Note:
ABC sync transfers can be achieved logically by chaining multiple AB sync transfers
+
Enumerator:
+ + + +
EDMA3_DRV_SYNC_A  +A-synchronized. Each event triggers the transfer of a single array of ACNT bytes
EDMA3_DRV_SYNC_AB  +AB-synchronized. Each event triggers the transfer of BCNT arrays of ACNT bytes
+
+ +
+

+ +

+
+ + + + +
enum EDMA3_DRV_TcchEn
+
+
+ +

+Transfer complete chaining enable. +

+

Enumerator:
+ + + +
EDMA3_DRV_TCCHEN_DIS  +Transfer complete chaining is disabled
EDMA3_DRV_TCCHEN_EN  +Transfer complete chaining is enabled. When enabled, the chained event register (CER/CERH) bit is set on final chained transfer completion (upon completion of the final / last TR in the PaRAM set). The bit (position) set in CER or CERH is the TCC value specified.
+
+ +
+

+ +

+
+ + + + +
enum EDMA3_DRV_TccMode
+
+
+ +

+Transfer complete code mode. Indicates the point at which a transfer is considered completed for chaining and interrupt generation. +

+

Enumerator:
+ + + +
EDMA3_DRV_TCCMODE_NORMAL  +A transfer is considered completed after transfer of data
EDMA3_DRV_TCCMODE_EARLY  +A transfer is considered completed after the EDMA3CC submits a TR to the EDMA3TC. TC may still be transferring data when interrupt/chain is triggered.
+
+ +
+

+ +

+
+ + + + +
enum EDMA3_DRV_TcintEn
+
+
+ +

+Transfer complete interrupt enable. +

+

Enumerator:
+ + + +
EDMA3_DRV_TCINTEN_DIS  +Transfer complete interrupt is disabled
EDMA3_DRV_TCINTEN_EN  +Transfer complete interrupt is enabled. When enabled, the interrupt pending register (IPR/IPRH) bit is set on transfer completion (upon completion of the final TR in the PaRAM set). The bit (position) set in IPR or IPRH is the TCC value specified. In order to generate a completion interrupt to the CPU, the corresponding IER [TCC] / IERH [TCC] bit must be set to 1.
+
+ +
+

+ +

+
+ + + + +
enum EDMA3_DRV_TrigMode
+
+
+ +

+EDMA Trigger Mode Selection. +

+Use this enum to select the EDMA trigger mode while enabling the EDMA transfer

Enumerator:
+ + + + + +
EDMA3_DRV_TRIG_MODE_MANUAL  +Set the Trigger mode to Manual . The CPU manually triggers a transfer by writing a 1 to the corresponding bit in the event set register (ESR/ESRH).
EDMA3_DRV_TRIG_MODE_QDMA  +Set the Trigger mode to QDMA. A QDMA transfer is triggered when a CPU (or other EDMA3 programmer) writes to the trigger word of the QDMA channel parameter set (autotriggered) or when the EDMA3CC performs a link update on a PaRAM set that has been mapped to a QDMA channel (link triggered).
EDMA3_DRV_TRIG_MODE_EVENT  +Set the Trigger mode to Event. Allows for a peripheral, system, or externally-generated event to trigger a transfer request.
EDMA3_DRV_TRIG_MODE_NONE  +Used to specify the trigger mode NONE
+
+ +
+

+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Result EDMA3_DRV_chainChannel (EDMA3_DRV_Handle  hEdma,
unsigned int  lCh1,
unsigned int  lCh2,
const EDMA3_DRV_ChainOptions *  chainOptions 
)
+
+
+ +

+Chain the two specified channels. +

+This API is used to chain two previously allocated logical (DMA/QDMA) channels.

+Chaining is different from Linking. The EDMA3 link feature reloads the current channel parameter set with the linked parameter set. The EDMA3 chaining feature does not modify or update any channel parameter set; it provides a synchronization event to the chained channel.

+

Parameters:
+ + + + + +
hEdma [IN] Handle to the EDMA Driver Instance.
lCh1 [IN] Channel to which particular channel will be chained.
lCh2 [IN] Channel which needs to be chained to the first channel.
chainOptions [IN] Options such as intermediate interrupts are required or not, intermediate/final chaining is enabled or not etc.
+
+
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
+
Note:
This function is re-entrant for unique lCh1 & lCh2 values. It is non-re-entrant for same lCh1 & lCh2 values.
+ +

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_ITCCHEN_EN, EDMA3_DRV_ITCINTEN_EN, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_OPT_ITCCHEN_CLR_MASK, EDMA3_DRV_OPT_ITCCHEN_SET_MASK, EDMA3_DRV_OPT_ITCINTEN_CLR_MASK, EDMA3_DRV_OPT_ITCINTEN_SET_MASK, EDMA3_DRV_OPT_TCC_CLR_MASK, EDMA3_DRV_OPT_TCC_SET_MASK, EDMA3_DRV_OPT_TCCHEN_CLR_MASK, EDMA3_DRV_OPT_TCCHEN_SET_MASK, EDMA3_DRV_OPT_TCINTEN_CLR_MASK, EDMA3_DRV_OPT_TCINTEN_SET_MASK, EDMA3_DRV_TCCHEN_EN, EDMA3_DRV_TCINTEN_EN, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_ChainOptions::itcchEn, EDMA3_DRV_ChainOptions::itcintEn, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, EDMA3_DRV_Object::phyCtrllerInstId, EDMA3_DRV_ChainOptions::tcchEn, EDMA3_DRV_ChainOptions::tcintEn, and EDMA3_DRV_ChBoundResources::trigMode.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Result EDMA3_DRV_disableTransfer (EDMA3_DRV_Handle  hEdma,
unsigned int  lCh,
EDMA3_DRV_TrigMode  trigMode 
)
+
+
+ +

+Disable DMA transfer on the specified channel. +

+There are multiple ways by which an EDMA3 transfer could be triggered. The triggering mode option allows choosing from the available triggering modes: Event, Manual or QDMA.

+To disable a channel which was previously triggered in manual mode, this API clears the Secondary Event Register and Event Miss Register, if set, for the specific DMA channel.

+To disable a channel which was previously triggered in QDMA mode, this API clears the QDMA Even Enable Register, for the specific QDMA channel.

+To disable a channel which was previously triggered in event mode, this API clears the Event Enable Register, Event Register, Secondary Event Register and Event Miss Register, if set, for the specific DMA channel.

+

Parameters:
+ + + + +
hEdma [IN] Handle to the EDMA Driver Instance
lCh [IN] Channel on which transfer has to be stopped
trigMode [IN] Mode of triggering start of transfer
+
+
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
+
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.
+ +

References EDMA3_DRV_GblConfigParams::dmaChannelHwEvtMap, EDMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_TRIG_MODE_EVENT, EDMA3_DRV_TRIG_MODE_MANUAL, EDMA3_DRV_TRIG_MODE_QDMA, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Instance::shadowRegs.

+ +

Referenced by edma3RemoveMapping().

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Result EDMA3_DRV_enableTransfer (EDMA3_DRV_Handle  hEdma,
unsigned int  lCh,
EDMA3_DRV_TrigMode  trigMode 
)
+
+
+ +

+Start EDMA transfer on the specified channel. +

+There are multiple ways to trigger an EDMA3 transfer. The triggering mode option allows choosing from the available triggering modes: Event, Manual or QDMA.

+In event triggered, a peripheral or an externally generated event triggers the transfer. This API clears the Event and Event Miss Register and then enables the DMA channel by writing to the EESR.

+In manual triggered mode, CPU manually triggers a transfer by writing a 1 in the Event Set Register (ESR/ESRH). This API writes to the ESR/ESRH to start the transfer.

+In QDMA triggered mode, a QDMA transfer is triggered when a CPU (or other EDMA3 programmer) writes to the trigger word of the QDMA channel PaRAM set (auto-triggered) or when the EDMA3CC performs a link update on a PaRAM set that has been mapped to a QDMA channel (link triggered). This API enables the QDMA channel by writing to the QEESR register.

+

Parameters:
+ + + + +
hEdma [IN] Handle to the EDMA Driver Instance
lCh [IN] Channel on which transfer has to be started
trigMode [IN] Mode of triggering start of transfer (Manual, QDMA or Event)
+
+
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
+
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.
+ +

References EDMA3_DRV_GblConfigParams::dmaChannelHwEvtMap, EDMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_TRIG_MODE_EVENT, EDMA3_DRV_TRIG_MODE_MANUAL, EDMA3_DRV_TRIG_MODE_QDMA, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_Instance::pDrvObjectHandle, EDMA3_DRV_Object::phyCtrllerInstId, EDMA3_DRV_Instance::shadowRegs, and EDMA3_DRV_ChBoundResources::trigMode.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Result EDMA3_DRV_getOptField (EDMA3_DRV_Handle  hEdma,
unsigned int  lCh,
EDMA3_DRV_OptField  optField,
unsigned int *  optFieldVal 
)
+
+
+ +

+Get a particular OPT field in the PaRAM set associated with the logical channel 'lCh'. +

+This API can be used to read various optional parameters for an EDMA3 transfer. Like enable/disable completion interrupts, enable/disable chaining, setting the transfer mode (A/AB Sync), setting the FIFO width etc.

+

Parameters:
+ + + + + +
hEdma [IN] Handle to the EDMA Driver Instance.
lCh [IN] Logical Channel, bound to which PaRAM set OPT field is required.
optField [IN] The particular field of OPT Word that is needed
optFieldVal [IN/OUT] Value of the OPT field
+
+
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
+
Note:
This function is re-entrant.
+ +

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_OPT_DAM_GET_MASK, EDMA3_DRV_OPT_FIELD_DAM, EDMA3_DRV_OPT_FIELD_FWID, EDMA3_DRV_OPT_FIELD_ITCCHEN, EDMA3_DRV_OPT_FIELD_ITCINTEN, EDMA3_DRV_OPT_FIELD_SAM, EDMA3_DRV_OPT_FIELD_STATIC, EDMA3_DRV_OPT_FIELD_SYNCDIM, EDMA3_DRV_OPT_FIELD_TCC, EDMA3_DRV_OPT_FIELD_TCCHEN, EDMA3_DRV_OPT_FIELD_TCCMODE, EDMA3_DRV_OPT_FIELD_TCINTEN, EDMA3_DRV_OPT_FWID_GET_MASK, EDMA3_DRV_OPT_ITCCHEN_GET_MASK, EDMA3_DRV_OPT_ITCINTEN_GET_MASK, EDMA3_DRV_OPT_SAM_GET_MASK, EDMA3_DRV_OPT_STATIC_GET_MASK, EDMA3_DRV_OPT_SYNCDIM_GET_MASK, EDMA3_DRV_OPT_TCC_GET_MASK, EDMA3_DRV_OPT_TCCHEN_GET_MASK, EDMA3_DRV_OPT_TCCMODE_GET_MASK, EDMA3_DRV_OPT_TCINTEN_GET_MASK, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Result EDMA3_DRV_setDestIndex (EDMA3_DRV_Handle  hEdma,
unsigned int  lCh,
int  destBIdx,
int  destCIdx 
)
+
+
+ +

+DMA destination index setup. +

+It is used to program the destination B index and destination C index.

+DSTBIDX is a 16-bit signed value (2s complement) used for destination address modification between each array in the 2nd dimension. Valid values for DSTBIDX are between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-synchronized and AB-synchronized transfers.

+DSTCIDX is a 16-bit signed value (2s complement) used for destination address modification in the 3rd dimension. Valid values are between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array TR in the next frame. It applies to both A-synchronized and AB-synchronized transfers. Note that when DSTCIDX is applied, the current array in an A-synchronized transfer is the last array in the frame, while the current array in a AB-synchronized transfer is the first array in the frame

+

Parameters:
+ + + + + +
hEdma [IN] Handle to the EDMA Driver Instance
lCh [IN] Logical Channel for which dest indices are to be configured
destBIdx [IN] Destination B index
destCIdx [IN] Destination C index
+
+
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
+
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.
+ +

References EDMA3_DRV_DSTBIDX_MAX_VAL, EDMA3_DRV_DSTBIDX_MIN_VAL, EDMA3_DRV_DSTCIDX_MAX_VAL, EDMA3_DRV_DSTCIDX_MIN_VAL, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX, EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Result EDMA3_DRV_setDestParams (EDMA3_DRV_Handle  hEdma,
unsigned int  lCh,
unsigned int  destAddr,
EDMA3_DRV_AddrMode  addrMode,
EDMA3_DRV_FifoWidth  fifoWidth 
)
+
+
+ +

+DMA Destination parameters setup. +

+It is used to program the destination address, destination side addressing mode (INCR or FIFO) and the FIFO width in case the addressing mode is FIFO.

+In FIFO Addressing mode, memory location must be 32 bytes aligned.

+

Parameters:
+ + + + + + +
hEdma [IN] Handle to the EDMA Driver Instance
lCh [IN] Logical Channel for which the destination parameters are to be configured
destAddr [IN] Destination address
addrMode [IN] Address mode [FIFO or Increment]
fifoWidth [IN] Width of FIFO (Valid only if addrMode is FIFO)
    +
  1. 0 - 8 bit
  2. 1 - 16 bit
  3. 2 - 32 bit
  4. 3 - 64 bit
  5. 4 - 128 bit
  6. 5 - 256 bit
+
+
+
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
+
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.
+ +

+In FIFO Addressing mode, memory location must be 32 bytes aligned

+Memory is not 32 bytes aligned

+If request is for FIFO mode, check whether the FIFO size is supported by the Transfer Controller which will be used for this transfer or not.

+mappedEvtQ contains the event queue and hence the TC which will process this transfer request. Check whether this TC supports the FIFO size or not. +

References EDMA3_DRV_ADDR_MODE_FIFO, EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_DMAQNUM_CLR_MASK, EDMA3_DRV_E_ADDRESS_NOT_ALIGNED, EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_OPT_DAM_CLR_MASK, EDMA3_DRV_OPT_DAM_SET_MASK, EDMA3_DRV_OPT_FWID_CLR_MASK, EDMA3_DRV_OPT_FWID_SET_MASK, EDMA3_DRV_PARAM_ENTRY_DST, EDMA3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_QDMAQNUM_CLR_MASK, EDMA3_DRV_W256BIT, EDMA3_DRV_W8BIT, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, EDMA3_DRV_Object::phyCtrllerInstId, and EDMA3_DRV_GblConfigParams::tcDefaultBurstSize.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Result EDMA3_DRV_setOptField (EDMA3_DRV_Handle  hEdma,
unsigned int  lCh,
EDMA3_DRV_OptField  optField,
unsigned int  newOptFieldVal 
)
+
+
+ +

+Set a particular OPT field in the PaRAM set associated with the logical channel 'lCh'. +

+This API can be used to set various optional parameters for an EDMA3 transfer. Like enable/disable completion interrupts, enable/disable chaining, setting the transfer mode (A/AB Sync), setting the FIFO width etc.

+

Parameters:
+ + + + + +
hEdma [IN] Handle to the EDMA Driver Instance.
lCh [IN] Logical Channel, bound to which PaRAM set OPT field needs to be set.
optField [IN] The particular field of OPT Word that needs setting
newOptFieldVal [IN] The new OPT field value
+
+
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
+
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.
+ +

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_OPT_DAM_CLR_MASK, EDMA3_DRV_OPT_DAM_SET_MASK, EDMA3_DRV_OPT_FIELD_DAM, EDMA3_DRV_OPT_FIELD_FWID, EDMA3_DRV_OPT_FIELD_ITCCHEN, EDMA3_DRV_OPT_FIELD_ITCINTEN, EDMA3_DRV_OPT_FIELD_SAM, EDMA3_DRV_OPT_FIELD_STATIC, EDMA3_DRV_OPT_FIELD_SYNCDIM, EDMA3_DRV_OPT_FIELD_TCC, EDMA3_DRV_OPT_FIELD_TCCHEN, EDMA3_DRV_OPT_FIELD_TCCMODE, EDMA3_DRV_OPT_FIELD_TCINTEN, EDMA3_DRV_OPT_FWID_CLR_MASK, EDMA3_DRV_OPT_FWID_SET_MASK, EDMA3_DRV_OPT_ITCCHEN_CLR_MASK, EDMA3_DRV_OPT_ITCCHEN_SET_MASK, EDMA3_DRV_OPT_ITCINTEN_CLR_MASK, EDMA3_DRV_OPT_ITCINTEN_SET_MASK, EDMA3_DRV_OPT_SAM_CLR_MASK, EDMA3_DRV_OPT_SAM_SET_MASK, EDMA3_DRV_OPT_STATIC_CLR_MASK, EDMA3_DRV_OPT_STATIC_SET_MASK, EDMA3_DRV_OPT_SYNCDIM_CLR_MASK, EDMA3_DRV_OPT_SYNCDIM_SET_MASK, EDMA3_DRV_OPT_TCC_CLR_MASK, EDMA3_DRV_OPT_TCC_SET_MASK, EDMA3_DRV_OPT_TCCHEN_CLR_MASK, EDMA3_DRV_OPT_TCCHEN_SET_MASK, EDMA3_DRV_OPT_TCCMODE_CLR_MASK, EDMA3_DRV_OPT_TCCMODE_SET_MASK, EDMA3_DRV_OPT_TCINTEN_CLR_MASK, EDMA3_DRV_OPT_TCINTEN_SET_MASK, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Result EDMA3_DRV_setSrcIndex (EDMA3_DRV_Handle  hEdma,
unsigned int  lCh,
int  srcBIdx,
int  srcCIdx 
)
+
+
+ +

+DMA source index setup. +

+It is used to program the source B index and source C index.

+SRCBIDX is a 16-bit signed value (2s complement) used for source address modification between each array in the 2nd dimension. Valid values for SRCBIDX are between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-synchronized and AB-synchronized transfers.

+SRCCIDX is a 16-bit signed value (2s complement) used for source address modification in the 3rd dimension. Valid values for SRCCIDX are between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-synchronized and AB-synchronized transfers. Note that when SRCCIDX is applied, the current array in an A-synchronized transfer is the last array in the frame, while the current array in an AB-synchronized transfer is the first array in the frame.

+

Parameters:
+ + + + + +
hEdma [IN] Handle to the EDMA Driver Instance
lCh [IN] Logical Channel for which source indices are to be configured
srcBIdx [IN] Source B index
srcCIdx [IN] Source C index
+
+
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
+
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.
+ +

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX, EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX, EDMA3_DRV_SRCBIDX_MAX_VAL, EDMA3_DRV_SRCBIDX_MIN_VAL, EDMA3_DRV_SRCCIDX_MAX_VAL, EDMA3_DRV_SRCCIDX_MIN_VAL, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Result EDMA3_DRV_setSrcParams (EDMA3_DRV_Handle  hEdma,
unsigned int  lCh,
unsigned int  srcAddr,
EDMA3_DRV_AddrMode  addrMode,
EDMA3_DRV_FifoWidth  fifoWidth 
)
+
+
+ +

+DMA source parameters setup. +

+It is used to program the source address, source side addressing mode (INCR or FIFO) and the FIFO width in case the addressing mode is FIFO.

+In FIFO Addressing mode, memory location must be 32 bytes aligned.

+

Parameters:
+ + + + + + +
hEdma [IN] Handle to the EDMA Driver Instance
lCh [IN] Logical Channel for which the source parameters are to be configured
srcAddr [IN] Source address
addrMode [IN] Address mode [FIFO or Increment]
fifoWidth [IN] Width of FIFO (Valid only if addrMode is FIFO)
    +
  1. 0 - 8 bit
  2. 1 - 16 bit
  3. 2 - 32 bit
  4. 3 - 64 bit
  5. 4 - 128 bit
  6. 5 - 256 bit
+
+
+
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
+
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.
+ +

+In FIFO Addressing mode, memory location must be 32 bytes aligned

+Memory is not 32 bytes aligned

+If request is for FIFO mode, check whether the FIFO size is supported by the Transfer Controller which will be used for this transfer or not.

+mappedEvtQ contains the event queue and hence the TC which will process this transfer request. Check whether this TC supports the FIFO size or not. +

References EDMA3_DRV_ADDR_MODE_FIFO, EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_DMAQNUM_CLR_MASK, EDMA3_DRV_E_ADDRESS_NOT_ALIGNED, EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_OPT_FWID_CLR_MASK, EDMA3_DRV_OPT_FWID_SET_MASK, EDMA3_DRV_OPT_SAM_CLR_MASK, EDMA3_DRV_OPT_SAM_SET_MASK, EDMA3_DRV_PARAM_ENTRY_SRC, EDMA3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_QDMAQNUM_CLR_MASK, EDMA3_DRV_W256BIT, EDMA3_DRV_W8BIT, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, EDMA3_DRV_Object::phyCtrllerInstId, and EDMA3_DRV_GblConfigParams::tcDefaultBurstSize.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Result EDMA3_DRV_setTransferParams (EDMA3_DRV_Handle  hEdma,
unsigned int  lCh,
unsigned int  aCnt,
unsigned int  bCnt,
unsigned int  cCnt,
unsigned int  bCntReload,
EDMA3_DRV_SyncType  syncType 
)
+
+
+ +

+DMA transfer parameters setup. +

+It is used to specify the various counts (ACNT, BCNT and CCNT), B count reload and the synchronization type

+ACNT represents the number of bytes within the 1st dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K - 1 bytes). ACNT must be greater than or equal to 1 for a TR to be submitted to EDMA3 Transfer Controller. An ACNT equal to 0 is considered either a null or dummy transfer. A dummy or null transfer generates a completion code depending on the settings of the completion bit fields in OPT.

+BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT are between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K - 1 arrays). A BCNT equal to 0 is considered either a null or dummy transfer. A dummy or null transfer generates a completion code depending on the settings of the completion bit fields in OPT.

+CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT are between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K - 1 frames). A CCNT equal to 0 is considered either a null or dummy transfer. A dummy or null transfer generates a completion code depending on the settings of the completion bit fields in OPT. A CCNT value of 0 is considered either a null or dummy transfer.

+BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-synchronized transfers. In this case, the EDMA3CC decrements the BCNT value by 1 on each TR submission. When BCNT (conceptually) reaches 0, the EDMA3CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the EDMA3CC submits the BCNT in the TR and the EDMA3TC decrements BCNT appropriately. For AB-synchronized transfers, BCNTRLD is not used.

+

Parameters:
+ + + + + + + + +
hEdma [IN] Handle to the EDMA Driver Instance
lCh [IN] Logical Channel for which transfer parameters are to be configured
aCnt [IN] Count for 1st Dimension.
bCnt [IN] Count for 2nd Dimension.
cCnt [IN] Count for 3rd Dimension.
bCntReload [IN] Reload value for bCnt.
syncType [IN] Transfer synchronization dimension 0: A-synchronized. Each event triggers the transfer of a single array of ACNT bytes. 1: AB-synchronized. Each event triggers the transfer of BCNT arrays of ACNT bytes.
+
+
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
+
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.
+ +

References EDMA3_DRV_ACNT_MAX_VAL, EDMA3_DRV_BCNT_MAX_VAL, EDMA3_DRV_BCNTRELD_MAX_VAL, EDMA3_DRV_CCNT_MAX_VAL, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_OPT_SYNCDIM_CLR_MASK, EDMA3_DRV_OPT_SYNCDIM_SET_MASK, EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT, EDMA3_DRV_PARAM_ENTRY_CCNT, EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD, EDMA3_DRV_SYNC_A, EDMA3_DRV_SYNC_AB, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Result EDMA3_DRV_unchainChannel (EDMA3_DRV_Handle  hEdma,
unsigned int  lCh 
)
+
+
+ +

+Unchain the two channels. +

+

Parameters:
+ + + +
hEdma [IN] Handle to the EDMA Driver Instance.
lCh [IN] Channel whose chaining with the other channel has to be removed.
+
+
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
+
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.
+ +

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_OPT_ITCCHEN_CLR_MASK, EDMA3_DRV_OPT_TCCHEN_CLR_MASK, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

+ +
+

+

+
Generated on Thu Oct 16 16:17:56 2008 for EDMA3 Driver by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/drv/docs/html/group__edma3drvusage.html b/packages/ti/sdo/edma3/drv/docs/html/group__edma3drvusage.html new file mode 100644 index 0000000..f10b573 --- /dev/null +++ b/packages/ti/sdo/edma3/drv/docs/html/group__edma3drvusage.html @@ -0,0 +1,30 @@ + + +EDMA3 Driver: EDMA3 Driver Usage Guidelines + + + + + +
+

EDMA3 Driver Usage Guidelines
+ +[EDMA3 Driver Interface Definition] +

+ +
+Guidelines for typical usage of EDMA3 Driver.
+
Generated on Thu Oct 16 16:17:55 2008 for EDMA3 Driver by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/drv/docs/html/index.hhc b/packages/ti/sdo/edma3/drv/docs/html/index.hhc new file mode 100644 index 0000000..b54348c --- /dev/null +++ b/packages/ti/sdo/edma3/drv/docs/html/index.hhc @@ -0,0 +1,63 @@ + + + + + +
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+ + diff --git a/packages/ti/sdo/edma3/drv/docs/html/index.hhp b/packages/ti/sdo/edma3/drv/docs/html/index.hhp new file mode 100644 index 0000000..e21a806 --- /dev/null +++ b/packages/ti/sdo/edma3/drv/docs/html/index.hhp @@ -0,0 +1,62 @@ +[OPTIONS] +Compiled file=..\EDMA3_Driver.chm +Compatibility=1.1 +Full-text search=Yes +Contents file=index.hhc +Default Window=main +Default topic=index.html +Index file=index.hhk +Language=0x409 English (United States) +Title=EDMA3 Driver + +[WINDOWS] +main="EDMA3 Driver","index.hhc","index.hhk","index.html","index.html",,,,,0x23520,,0x10387e,,,,,,,,0 + +[FILES] +index.html +edma3_8h-source.html +edma3__drv_8h-source.html +edma3_8h.html +edma3__drv_8h.html +edma3__drv__adv_8c.html +edma3__drv__basic_8c.html +edma3__drv__init_8c.html +group__Edma3DrvMain.html +group__Edma3DrvUsage.html +group__Edma3DrvErrorCode.html +group__Edma3DrvChannelSetup.html +group__Edma3DrvTransferSetupType.html +group__Edma3DrvTransferSetupOpt.html +group__Edma3DrvInt.html +group__Edma3DrvIntBoundVals.html +group__Edma3DrvIntObjMaint.html +modules.html +annotated.html +classes.html +functions.html +functions_vars.html +structEDMA3__DRV__ChainOptions.html +structEDMA3__DRV__ChBoundResources.html +structEDMA3__DRV__EvtQuePriority.html +structEDMA3__DRV__GblConfigParams.html +structEDMA3__DRV__InitConfig.html +structEDMA3__DRV__Instance.html +structEDMA3__DRV__InstanceInitConfig.html +structEDMA3__DRV__MiscParam.html +structEDMA3__DRV__Object.html +structEDMA3__DRV__ParamentryRegs.html +structEDMA3__DRV__PaRAMRegs.html +files.html +globals.html +globals_0x65.html +globals_0x70.html +globals_0x72.html +globals_func.html +globals_vars.html +globals_enum.html +globals_eval.html +globals_defs.html +tabs.css +tab_b.gif +tab_l.gif +tab_r.gif diff --git a/packages/ti/sdo/edma3/drv/docs/html/index.html b/packages/ti/sdo/edma3/drv/docs/html/index.html new file mode 100644 index 0000000..d503839 --- /dev/null +++ b/packages/ti/sdo/edma3/drv/docs/html/index.html @@ -0,0 +1,26 @@ + + +EDMA3 Driver: Main Page + + + + + +
+

EDMA3 Driver Documentation

+

+

+
Generated on Thu Oct 16 16:17:55 2008 for EDMA3 Driver by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/drv/docs/html/modules.html b/packages/ti/sdo/edma3/drv/docs/html/modules.html new file mode 100644 index 0000000..c3eb629 --- /dev/null +++ b/packages/ti/sdo/edma3/drv/docs/html/modules.html @@ -0,0 +1,39 @@ + + +EDMA3 Driver: Module Index + + + + + +
+

Modules

Here is a list of all modules: +
+
Generated on Thu Oct 16 16:17:56 2008 for EDMA3 Driver by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/drv/docs/html/structedma3__drv__chainoptions.html b/packages/ti/sdo/edma3/drv/docs/html/structedma3__drv__chainoptions.html new file mode 100644 index 0000000..f69cc1e --- /dev/null +++ b/packages/ti/sdo/edma3/drv/docs/html/structedma3__drv__chainoptions.html @@ -0,0 +1,123 @@ + + +EDMA3 Driver: EDMA3_DRV_ChainOptions Struct Reference + + + + + +
+

EDMA3_DRV_ChainOptions Struct Reference
+ +[EDMA3 Driver Typical EDMA Transfer Setup] +

Structure to be used to configure interrupt generation and chaining options. +More... +

+#include <edma3_drv.h> +

+ + + + + + + + + + + +

Data Fields

EDMA3_DRV_TcchEn tcchEn
EDMA3_DRV_ItcchEn itcchEn
EDMA3_DRV_TcintEn tcintEn
EDMA3_DRV_ItcintEn itcintEn
+

Detailed Description

+Structure to be used to configure interrupt generation and chaining options.

Field Documentation

+ +
+
+ + + + +
EDMA3_DRV_TcchEn EDMA3_DRV_ChainOptions::tcchEn
+
+
+ +

+Transfer complete chaining enable +

Referenced by EDMA3_DRV_chainChannel().

+ +
+

+ +

+
+ + + + +
EDMA3_DRV_ItcchEn EDMA3_DRV_ChainOptions::itcchEn
+
+
+ +

+Intermediate Transfer complete chaining enable +

Referenced by EDMA3_DRV_chainChannel().

+ +
+

+ +

+
+ + + + +
EDMA3_DRV_TcintEn EDMA3_DRV_ChainOptions::tcintEn
+
+
+ +

+Transfer complete interrupt enable +

Referenced by EDMA3_DRV_chainChannel().

+ +
+

+ +

+
+ + + + +
EDMA3_DRV_ItcintEn EDMA3_DRV_ChainOptions::itcintEn
+
+
+ +

+Intermediate Transfer complete interrupt enable +

Referenced by EDMA3_DRV_chainChannel().

+ +
+

+

The documentation for this struct was generated from the following file: +
+
Generated on Thu Oct 16 16:17:56 2008 for EDMA3 Driver by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/drv/docs/html/structedma3__drv__chboundresources.html b/packages/ti/sdo/edma3/drv/docs/html/structedma3__drv__chboundresources.html new file mode 100644 index 0000000..5e93980 --- /dev/null +++ b/packages/ti/sdo/edma3/drv/docs/html/structedma3__drv__chboundresources.html @@ -0,0 +1,106 @@ + + +EDMA3 Driver: EDMA3_DRV_ChBoundResources Struct Reference + + + + + +
+

EDMA3_DRV_ChBoundResources Struct Reference
+ +[Internal Interface Definition for EDMA3 Driver] +

EDMA3 Channel-Bound resources. +More... +

+#include <edma3.h> +

+ + + + + + + + + +

Data Fields

int paRAMId
unsigned int tcc
EDMA3_DRV_TrigMode trigMode
+

Detailed Description

+EDMA3 Channel-Bound resources. +

+Used to maintain information of the EDMA3 resources (specifically Parameter RAM set and TCC) and the mode of triggering transfer (Manual, HW event driven etc) bound to the particular channel within EDMA3_DRV_requestChannel().

Field Documentation

+ +
+
+ + + + +
int EDMA3_DRV_ChBoundResources::paRAMId
+
+
+ +

+PaRAM Set number associated with the particular channel +

Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_create(), EDMA3_DRV_freeChannel(), EDMA3_DRV_getOptField(), EDMA3_DRV_getPaRAM(), EDMA3_DRV_getPaRAMEntry(), EDMA3_DRV_getPaRAMField(), EDMA3_DRV_getPaRAMPhyAddr(), EDMA3_DRV_linkChannel(), EDMA3_DRV_requestChannel(), EDMA3_DRV_setDestIndex(), EDMA3_DRV_setDestParams(), EDMA3_DRV_setOptField(), EDMA3_DRV_setPaRAM(), EDMA3_DRV_setPaRAMEntry(), EDMA3_DRV_setPaRAMField(), EDMA3_DRV_setSrcIndex(), EDMA3_DRV_setSrcParams(), EDMA3_DRV_setTransferParams(), EDMA3_DRV_unchainChannel(), and EDMA3_DRV_unlinkChannel().

+ +
+

+ +

+
+ + + + +
unsigned int EDMA3_DRV_ChBoundResources::tcc
+
+
+ +

+TCC associated with the particular channel +

Referenced by EDMA3_DRV_create(), EDMA3_DRV_freeChannel(), and EDMA3_DRV_requestChannel().

+ +
+

+ +

+
+ + + + +
EDMA3_DRV_TrigMode EDMA3_DRV_ChBoundResources::trigMode
+
+
+ +

+Mode of triggering transfer +

Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_create(), EDMA3_DRV_enableTransfer(), EDMA3_DRV_requestChannel(), and edma3RemoveMapping().

+ +
+

+

The documentation for this struct was generated from the following file: +
+
Generated on Thu Oct 16 16:17:56 2008 for EDMA3 Driver by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/drv/docs/html/structedma3__drv__evtquepriority.html b/packages/ti/sdo/edma3/drv/docs/html/structedma3__drv__evtquepriority.html new file mode 100644 index 0000000..521633c --- /dev/null +++ b/packages/ti/sdo/edma3/drv/docs/html/structedma3__drv__evtquepriority.html @@ -0,0 +1,52 @@ + + +EDMA3 Driver: EDMA3_DRV_EvtQuePriority Struct Reference + + + + + +
+

EDMA3_DRV_EvtQuePriority Struct Reference
+ +[EDMA3 Driver Optional Setup for EDMA] +

Event queue priorities setup. +More... +

+#include <edma3_drv.h> +

+ + + + + + +

Data Fields

+unsigned int evtQPri [EDMA3_MAX_EVT_QUE]
 Event Queue Priorities.
+

Detailed Description

+Event queue priorities setup. +

+It allows to change the priority of the individual queues and the priority of the transfer request (TR) associated with the events queued in the queue.

The documentation for this struct was generated from the following file: +
+
Generated on Thu Oct 16 16:17:56 2008 for EDMA3 Driver by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/drv/docs/html/structedma3__drv__gblconfigparams.html b/packages/ti/sdo/edma3/drv/docs/html/structedma3__drv__gblconfigparams.html new file mode 100644 index 0000000..f78b728 --- /dev/null +++ b/packages/ti/sdo/edma3/drv/docs/html/structedma3__drv__gblconfigparams.html @@ -0,0 +1,433 @@ + + +EDMA3 Driver: EDMA3_DRV_GblConfigParams Struct Reference + + + + + +
+

EDMA3_DRV_GblConfigParams Struct Reference
+ +[EDMA3 Driver Interface Definition] +

Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. +More... +

+#include <edma3_drv.h> +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Data Fields

unsigned int numDmaChannels
unsigned int numQdmaChannels
unsigned int numTccs
unsigned int numPaRAMSets
unsigned int numEvtQueue
unsigned int numTcs
unsigned int numRegions
unsigned short dmaChPaRAMMapExists
 Channel mapping existence.
unsigned short memProtectionExists
void * globalRegs
void * tcRegs [EDMA3_MAX_TC]
unsigned int xferCompleteInt
unsigned int ccError
unsigned int tcError [EDMA3_MAX_TC]
unsigned int evtQPri [EDMA3_MAX_EVT_QUE]
 EDMA3 TC priority setting.
unsigned int evtQueueWaterMarkLvl [EDMA3_MAX_EVT_QUE]
 Event Queues Watermark Levels.
unsigned int tcDefaultBurstSize [EDMA3_MAX_TC]
 Default Burst Size (DBS) of TCs.
unsigned int dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH]
 Mapping from DMA channels to PaRAM Sets.
unsigned int dmaChannelTccMap [EDMA3_MAX_DMA_CH]
 Mapping from DMA channels to TCCs.
unsigned int dmaChannelHwEvtMap [EDMA3_MAX_DMA_CHAN_DWRDS]
 Mapping from DMA channels to Hardware Events.
+

Detailed Description

+Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. +

+This configuration structure is used to specify the EDMA3 Driver global settings, specific to the SoC. For e.g. number of DMA/QDMA channels, number of PaRAM sets, TCCs, event queues, transfer controllers, base addresses of CC global registers and TC registers, interrupt number for EDMA3 transfer completion, CC error, event queues' priority, watermark threshold level etc. This configuration information is SoC specific and could be provided by the user at run-time while creating the EDMA3 Driver Object, using API EDMA3_DRV_create. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c, in case it is available.

Field Documentation

+ +
+
+ + + + +
unsigned int EDMA3_DRV_GblConfigParams::numDmaChannels
+
+
+ +

+Number of DMA Channels supported by the underlying EDMA3 Controller. +

Referenced by EDMA3_DRV_requestChannel().

+ +
+

+ +

+
+ + + + +
unsigned int EDMA3_DRV_GblConfigParams::numQdmaChannels
+
+
+ +

+Number of QDMA Channels supported by the underlying EDMA3 Controller +

+

+ +

+
+ + + + +
unsigned int EDMA3_DRV_GblConfigParams::numTccs
+
+
+ +

+Number of Interrupt Channels supported by the underlying EDMA3 Controller +

Referenced by EDMA3_DRV_checkAndClearTcc(), EDMA3_DRV_freeChannel(), and EDMA3_DRV_waitAndClearTcc().

+ +
+

+ +

+
+ + + + +
unsigned int EDMA3_DRV_GblConfigParams::numPaRAMSets
+
+
+ +

+Number of PaRAM Sets supported by the underlying EDMA3 Controller +

Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_freeChannel(), EDMA3_DRV_getOptField(), EDMA3_DRV_getPaRAM(), EDMA3_DRV_getPaRAMEntry(), EDMA3_DRV_getPaRAMField(), EDMA3_DRV_getPaRAMPhyAddr(), EDMA3_DRV_linkChannel(), EDMA3_DRV_setDestIndex(), EDMA3_DRV_setDestParams(), EDMA3_DRV_setOptField(), EDMA3_DRV_setPaRAM(), EDMA3_DRV_setPaRAMEntry(), EDMA3_DRV_setPaRAMField(), EDMA3_DRV_setSrcIndex(), EDMA3_DRV_setSrcParams(), EDMA3_DRV_setTransferParams(), EDMA3_DRV_unchainChannel(), and EDMA3_DRV_unlinkChannel().

+ +
+

+ +

+
+ + + + +
unsigned int EDMA3_DRV_GblConfigParams::numEvtQueue
+
+
+ +

+Number of Event Queues in the underlying EDMA3 Controller +

Referenced by EDMA3_DRV_clearErrorBits(), EDMA3_DRV_mapChToEvtQ(), and EDMA3_DRV_requestChannel().

+ +
+

+ +

+
+ + + + +
unsigned int EDMA3_DRV_GblConfigParams::numTcs
+
+
+ +

+Number of Transfer Controllers (TCs) in the underlying EDMA3 Controller +

+

+ +

+
+ + + + +
unsigned int EDMA3_DRV_GblConfigParams::numRegions
+
+
+ +

+Number of Regions in the underlying EDMA3 Controller +

Referenced by EDMA3_DRV_create(), EDMA3_DRV_getInstHandle(), and EDMA3_DRV_open().

+ +
+

+ +

+
+ + + + +
unsigned short EDMA3_DRV_GblConfigParams::dmaChPaRAMMapExists
+
+
+ +

+Channel mapping existence. +

+A value of 0 (No channel mapping) implies that there is fixed association between a DMA channel and a PaRAM Set or, in other words, DMA channel n can ONLY use PaRAM Set n (No availability of DCHMAP registers) for transfers to happen.

+A value of 1 implies the presence of DCHMAP registers for the DMA channels and hence the flexibility of associating any DMA channel to any PaRAM Set. In other words, ANY PaRAM Set can be used for ANY DMA channel (like QDMA Channels). +

Referenced by EDMA3_DRV_requestChannel(), and edma3RemoveMapping().

+ +
+

+ +

+
+ + + + +
unsigned short EDMA3_DRV_GblConfigParams::memProtectionExists
+
+
+ +

+Existence of memory protection feature +

+

+ +

+
+ + + + +
void* EDMA3_DRV_GblConfigParams::globalRegs
+
+
+ +

+Base address of EDMA3 CC memory mapped registers. +

Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_checkAndClearTcc(), EDMA3_DRV_clearErrorBits(), EDMA3_DRV_disableTransfer(), EDMA3_DRV_enableTransfer(), EDMA3_DRV_getCCRegister(), EDMA3_DRV_getMapChToEvtQ(), EDMA3_DRV_getOptField(), EDMA3_DRV_getPaRAM(), EDMA3_DRV_getPaRAMEntry(), EDMA3_DRV_getPaRAMField(), EDMA3_DRV_getPaRAMPhyAddr(), EDMA3_DRV_linkChannel(), EDMA3_DRV_mapChToEvtQ(), EDMA3_DRV_open(), EDMA3_DRV_requestChannel(), EDMA3_DRV_setCCRegister(), EDMA3_DRV_setDestIndex(), EDMA3_DRV_setDestParams(), EDMA3_DRV_setEvtQPriority(), EDMA3_DRV_setOptField(), EDMA3_DRV_setPaRAM(), EDMA3_DRV_setPaRAMEntry(), EDMA3_DRV_setPaRAMField(), EDMA3_DRV_setQdmaTrigWord(), EDMA3_DRV_setSrcIndex(), EDMA3_DRV_setSrcParams(), EDMA3_DRV_setTransferParams(), EDMA3_DRV_unchainChannel(), EDMA3_DRV_unlinkChannel(), EDMA3_DRV_waitAndClearTcc(), and edma3RemoveMapping().

+ +
+

+ +

+
+ + + + +
void* EDMA3_DRV_GblConfigParams::tcRegs[EDMA3_MAX_TC]
+
+
+ +

+Base address of EDMA3 TCs memory mapped registers. +

+

+ +

+
+ + + + +
unsigned int EDMA3_DRV_GblConfigParams::xferCompleteInt
+
+
+ +

+EDMA3 transfer completion interrupt line (could be different for ARM and DSP) +

+

+ +

+
+ + + + +
unsigned int EDMA3_DRV_GblConfigParams::ccError
+
+
+ +

+EDMA3 CC error interrupt line (could be different for ARM and DSP) +

+

+ +

+
+ + + + +
unsigned int EDMA3_DRV_GblConfigParams::tcError[EDMA3_MAX_TC]
+
+
+ +

+EDMA3 TCs error interrupt line (could be different for ARM and DSP) +

+

+ +

+
+ + + + +
unsigned int EDMA3_DRV_GblConfigParams::evtQPri[EDMA3_MAX_EVT_QUE]
+
+
+ +

+EDMA3 TC priority setting. +

+User can program the priority of the Event Queues at a system-wide level. This means that the user can set the priority of an IO initiated by either of the TCs (Transfer Controllers) relative to IO initiated by the other bus masters on the device (ARM, DSP, USB, etc) +

+

+ +

+
+ + + + +
unsigned int EDMA3_DRV_GblConfigParams::evtQueueWaterMarkLvl[EDMA3_MAX_EVT_QUE]
+
+
+ +

+Event Queues Watermark Levels. +

+To Configure the Threshold level of number of events that can be queued up in the Event queues. EDMA3CC error register (CCERR) will indicate whether or not at any instant of time the number of events queued up in any of the event queues exceeds or equals the threshold/watermark value that is set in the queue watermark threshold register (QWMTHRA). +

+

+ +

+
+ + + + +
unsigned int EDMA3_DRV_GblConfigParams::tcDefaultBurstSize[EDMA3_MAX_TC]
+
+
+ +

+Default Burst Size (DBS) of TCs. +

+An optimally-sized command is defined by the transfer controller default burst size (DBS). Different TCs can have different DBS values. It is defined in Bytes. +

Referenced by EDMA3_DRV_setDestParams(), and EDMA3_DRV_setSrcParams().

+ +
+

+ +

+
+ + + + +
unsigned int EDMA3_DRV_GblConfigParams::dmaChannelPaRAMMap[EDMA3_MAX_DMA_CH]
+
+
+ +

+Mapping from DMA channels to PaRAM Sets. +

+If channel mapping exists (DCHMAP registers are present), this array stores the respective PaRAM Set for each DMA channel. User can initialize each array member with a specific PaRAM Set or with EDMA3_DRV_CH_NO_PARAM_MAP. If channel mapping doesn't exist, it is of no use as the EDMA3 RM automatically uses the right PaRAM Set for that DMA channel. Useful only if mapping exists, otherwise of no use. +

Referenced by EDMA3_DRV_requestChannel().

+ +
+

+ +

+
+ + + + +
unsigned int EDMA3_DRV_GblConfigParams::dmaChannelTccMap[EDMA3_MAX_DMA_CH]
+
+
+ +

+Mapping from DMA channels to TCCs. +

+This array stores the respective TCC (interrupt channel) for each DMA channel. User can initialize each array member with a specific TCC or with EDMA3_DRV_CH_NO_TCC_MAP. This specific TCC code will be returned when the transfer is completed on the mapped DMA channel. +

Referenced by EDMA3_DRV_requestChannel().

+ +
+

+ +

+
+ + + + +
unsigned int EDMA3_DRV_GblConfigParams::dmaChannelHwEvtMap[EDMA3_MAX_DMA_CHAN_DWRDS]
+
+
+ +

+Mapping from DMA channels to Hardware Events. +

+Each bit in this array corresponds to one DMA channel and tells whether this DMA channel is tied to any peripheral. That is whether any peripheral can send the synch event on this DMA channel or not. 1 means the channel is tied to some peripheral; 0 means it is not. DMA channels which are tied to some peripheral are RESERVED for that peripheral only. They are not allocated when user asks for 'ANY' DMA channel. All channels need not be mapped, some can be free also. +

Referenced by EDMA3_DRV_disableTransfer(), and EDMA3_DRV_enableTransfer().

+ +
+

+

The documentation for this struct was generated from the following file: +
+
Generated on Thu Oct 16 16:17:56 2008 for EDMA3 Driver by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/drv/docs/html/structedma3__drv__initconfig.html b/packages/ti/sdo/edma3/drv/docs/html/structedma3__drv__initconfig.html new file mode 100644 index 0000000..8476380 --- /dev/null +++ b/packages/ti/sdo/edma3/drv/docs/html/structedma3__drv__initconfig.html @@ -0,0 +1,163 @@ + + +EDMA3 Driver: EDMA3_DRV_InitConfig Struct Reference + + + + + +
+

EDMA3_DRV_InitConfig Struct Reference
+ +[EDMA3 Driver Interface Definition] +

Used to Initialize the EDMA3 Driver Instance. +More... +

+#include <edma3_drv.h> +

+ + + + + + + + + + + + + + + +

Data Fields

EDMA3_RM_RegionId regionId
unsigned short isMaster
EDMA3_DRV_InstanceInitConfig * drvInstInitConfig
void * drvSemHandle
EDMA3_RM_GblErrCallback gblerrCb
void * gblerrData
+

Detailed Description

+Used to Initialize the EDMA3 Driver Instance. +

+This configuration structure is used to initialize the EDMA3 DRV Instance. This configuration information is passed while opening the DRV instance.

Field Documentation

+ +
+
+ + + + +
EDMA3_RM_RegionId EDMA3_DRV_InitConfig::regionId
+
+
+ +

+Region Identification +

Referenced by EDMA3_DRV_open().

+ +
+

+ +

+
+ + + + +
unsigned short EDMA3_DRV_InitConfig::isMaster
+
+
+ +

+It tells whether the EDMA3 DRV instance is Master or not. Only the shadow region associated with this master instance will receive the EDMA3 interrupts (if enabled). +

Referenced by EDMA3_DRV_open().

+ +
+

+ +

+
+ + + + +
EDMA3_DRV_InstanceInitConfig* EDMA3_DRV_InitConfig::drvInstInitConfig
+
+
+ +

+EDMA3 resources related shadow region specific information. Which all EDMA3 resources are owned and reserved by this particular instance are told in this configuration structure. User can also pass this structure as NULL. In that case, default static configuration would be taken from the platform specific configuration files (part of the Resource Manager), if available. +

Referenced by EDMA3_DRV_open().

+ +
+

+ +

+
+ + + + +
void* EDMA3_DRV_InitConfig::drvSemHandle
+
+
+ +

+EDMA3 Driver Instance specific semaphore handle. Used to share resources (DMA/QDMA channels, PaRAM Sets, TCCs etc) among different users. +

Referenced by EDMA3_DRV_open().

+ +
+

+ +

+
+ + + + +
EDMA3_RM_GblErrCallback EDMA3_DRV_InitConfig::gblerrCb
+
+
+ +

+Instance wide global callback function to catch non-channel specific errors from the Channel controller. for eg, TCC error, queue threshold exceed error etc. +

Referenced by EDMA3_DRV_open().

+ +
+

+ +

+
+ + + + +
void* EDMA3_DRV_InitConfig::gblerrData
+
+
+ +

+Application data to be passed back to the global error callback function +

Referenced by EDMA3_DRV_open().

+ +
+

+

The documentation for this struct was generated from the following file: +
+
Generated on Thu Oct 16 16:17:56 2008 for EDMA3 Driver by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/drv/docs/html/structedma3__drv__instance.html b/packages/ti/sdo/edma3/drv/docs/html/structedma3__drv__instance.html new file mode 100644 index 0000000..e74f7ad --- /dev/null +++ b/packages/ti/sdo/edma3/drv/docs/html/structedma3__drv__instance.html @@ -0,0 +1,201 @@ + + +EDMA3 Driver: EDMA3_DRV_Instance Struct Reference + + + + + +
+

EDMA3_DRV_Instance Struct Reference
+ +[Object Maintenance] +

EDMA3 Driver Instance Configuration Structure. +More... +

+#include <edma3.h> +

+ + + + + + + + + + + + + + + + + + + +

Data Fields

EDMA3_RM_RegionId regionId
unsigned short isMaster
EDMA3_DRV_InstanceInitConfig drvInstInitConfig
void * drvSemHandle
EDMA3_RM_GblErrCallbackParams gblerrCbParams
EDMA3_CCRL_ShadowRegs * shadowRegs
EDMA3_DRV_Object * pDrvObjectHandle
EDMA3_RM_Handle resMgrInstance
+

Detailed Description

+EDMA3 Driver Instance Configuration Structure. +

+Used to maintain information of the EDMA3 Driver Instances. One such storage exists for each instance of the EDMA3 Driver. There could be as many Driver Instances as there are shadow regions. Multiple EDMA3 Driver instances on the same shadow region are NOT allowed.

Field Documentation

+ +
+
+ + + + +
EDMA3_RM_RegionId EDMA3_DRV_Instance::regionId
+
+
+ +

+Region Identification +

Referenced by EDMA3_DRV_checkAndClearTcc(), EDMA3_DRV_open(), and EDMA3_DRV_waitAndClearTcc().

+ +
+

+ +

+
+ + + + +
unsigned short EDMA3_DRV_Instance::isMaster
+
+
+ +

+Whether EDMA3 driver instance is Master or not. Only the master instance shadow region will receive the EDMA3 interrupts, if enabled. +

Referenced by EDMA3_DRV_open(), and edma3OpenResMgr().

+ +
+

+ +

+
+ + + + +
EDMA3_DRV_InstanceInitConfig EDMA3_DRV_Instance::drvInstInitConfig
+
+
+ +

+EDMA3 Driver Instance (Shadow Region) specific init configuration. If NULL, static values will be taken +

Referenced by EDMA3_DRV_close(), and EDMA3_DRV_open().

+ +
+

+ +

+
+ + + + +
void* EDMA3_DRV_Instance::drvSemHandle
+
+
+ +

+EDMA3 Driver Instance specific semaphore handle +

Referenced by EDMA3_DRV_open(), EDMA3_DRV_setCCRegister(), and edma3OpenResMgr().

+ +
+

+ +

+
+ + + + +
EDMA3_RM_GblErrCallbackParams EDMA3_DRV_Instance::gblerrCbParams
+
+
+ +

+Instance wide Global Error callback parameters +

Referenced by EDMA3_DRV_open(), and edma3OpenResMgr().

+ +
+

+ +

+
+ + + + +
EDMA3_CCRL_ShadowRegs* EDMA3_DRV_Instance::shadowRegs
+
+
+ +

+Pointer to appropriate Shadow Register region of CC Registers +

Referenced by EDMA3_DRV_clearErrorBits(), EDMA3_DRV_close(), EDMA3_DRV_disableTransfer(), EDMA3_DRV_enableTransfer(), EDMA3_DRV_open(), and EDMA3_DRV_requestChannel().

+ +
+

+ +

+
+ + + + +
EDMA3_DRV_Object* EDMA3_DRV_Instance::pDrvObjectHandle
+
+
+ +

+Pointer to the EDMA3 Driver Object, for HW specific / Global Information. +

Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_checkAndClearTcc(), EDMA3_DRV_clearErrorBits(), EDMA3_DRV_close(), EDMA3_DRV_disableTransfer(), EDMA3_DRV_enableTransfer(), EDMA3_DRV_freeChannel(), EDMA3_DRV_getCCRegister(), EDMA3_DRV_getInstHandle(), EDMA3_DRV_getMapChToEvtQ(), EDMA3_DRV_getOptField(), EDMA3_DRV_getPaRAM(), EDMA3_DRV_getPaRAMEntry(), EDMA3_DRV_getPaRAMField(), EDMA3_DRV_getPaRAMPhyAddr(), EDMA3_DRV_linkChannel(), EDMA3_DRV_mapChToEvtQ(), EDMA3_DRV_open(), EDMA3_DRV_requestChannel(), EDMA3_DRV_setCCRegister(), EDMA3_DRV_setDestIndex(), EDMA3_DRV_setDestParams(), EDMA3_DRV_setEvtQPriority(), EDMA3_DRV_setOptField(), EDMA3_DRV_setPaRAM(), EDMA3_DRV_setPaRAMEntry(), EDMA3_DRV_setPaRAMField(), EDMA3_DRV_setQdmaTrigWord(), EDMA3_DRV_setSrcIndex(), EDMA3_DRV_setSrcParams(), EDMA3_DRV_setTransferParams(), EDMA3_DRV_unchainChannel(), EDMA3_DRV_unlinkChannel(), EDMA3_DRV_waitAndClearTcc(), edma3OpenResMgr(), and edma3RemoveMapping().

+ +
+

+ +

+
+ + + + +
EDMA3_RM_Handle EDMA3_DRV_Instance::resMgrInstance
+
+
+ +

+Pointer to the Resource Manager Instance opened by the EDMA3 Driver +

Referenced by EDMA3_DRV_close(), EDMA3_DRV_freeChannel(), EDMA3_DRV_Ioctl(), EDMA3_DRV_requestChannel(), edma3OpenResMgr(), and edma3RemoveMapping().

+ +
+

+

The documentation for this struct was generated from the following file: +
+
Generated on Thu Oct 16 16:17:56 2008 for EDMA3 Driver by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/drv/docs/html/structedma3__drv__instanceinitconfig.html b/packages/ti/sdo/edma3/drv/docs/html/structedma3__drv__instanceinitconfig.html new file mode 100644 index 0000000..6b8903d --- /dev/null +++ b/packages/ti/sdo/edma3/drv/docs/html/structedma3__drv__instanceinitconfig.html @@ -0,0 +1,208 @@ + + +EDMA3 Driver: EDMA3_DRV_InstanceInitConfig Struct Reference + + + + + +
+

EDMA3_DRV_InstanceInitConfig Struct Reference
+ +[EDMA3 Driver Interface Definition] +

Init-time Region Specific Configuration structure for EDMA3 Driver, to provide region specific Information. +More... +

+#include <edma3_drv.h> +

+ + + + + + + + + + + + + + + + + + + + + + + +

Data Fields

unsigned int ownPaRAMSets [EDMA3_MAX_PARAM_DWRDS]
unsigned int ownDmaChannels [EDMA3_MAX_DMA_CHAN_DWRDS]
unsigned int ownQdmaChannels [EDMA3_MAX_QDMA_CHAN_DWRDS]
unsigned int ownTccs [EDMA3_MAX_TCC_DWRDS]
unsigned int resvdPaRAMSets [EDMA3_MAX_PARAM_DWRDS]
 Reserved PaRAM Sets.
unsigned int resvdDmaChannels [EDMA3_MAX_DMA_CHAN_DWRDS]
 Reserved DMA channels.
unsigned int resvdQdmaChannels [EDMA3_MAX_QDMA_CHAN_DWRDS]
 Reserved QDMA channels.
unsigned int resvdTccs [EDMA3_MAX_TCC_DWRDS]
 Reserved TCCs.
+

Detailed Description

+Init-time Region Specific Configuration structure for EDMA3 Driver, to provide region specific Information. +

+This configuration structure is used to specify which EDMA3 resources are owned and reserved by the EDMA3 Driver instance. This configuration structure is shadow region specific and will be provided by the user at run-time while calling EDMA3_DRV_open ().

+Owned resources: ****************

+EDMA3 Driver Instances are tied to different shadow regions and hence different masters. Regions could be:

+a) ARM, b) DSP, c) IMCOP (Imaging Co-processor) etc.

+User can assign each EDMA3 resource to a shadow region using this structure. In this way, user specifies which resources are owned by the specific EDMA3 DRV Instance. This assignment should also ensure that the same resource is not assigned to more than one shadow regions (unless desired in that way). Any assignment not following the above mentioned approach may have catastrophic consequences.

+Reserved resources: *******************

+During EDMA3 DRV initialization, user can reserve some of the EDMA3 resources for future use, by specifying which resources to reserve in the configuration data structure. These (critical) resources are reserved in advance so that they should not be allocated to someone else and thus could be used in future for some specific purpose.

+User can request different EDMA3 resources using two methods: a) By passing the resource type and the actual resource id, b) By passing the resource type and ANY as resource id

+For e.g. to request DMA channel 31, user will pass 31 as the resource id. But to request ANY available DMA channel (mainly used for memory-to-memory data transfer operations), user will pass EDMA3_DRV_DMA_CHANNEL_ANY as the resource id.

+During initialization, user may have reserved some of the DMA channels for some specific purpose (mainly for peripherals using EDMA). These reserved DMA channels then will not be returned when user requests ANY as the resource id.

+Same logic applies for QDMA channels and TCCs.

+For PaRAM Set, there is one difference. If the DMA channels are one-to-one tied to their respective PaRAM Sets (i.e. user cannot 'choose' the PaRAM Set for a particular DMA channel), EDMA3 Driver automatically reserves all those PaRAM Sets which are tied to the DMA channels. Then those PaRAM Sets would not be returned when user requests for ANY PaRAM Set (specifically for linking purpose). This is done in order to avoid allocating the PaRAM Set, tied to a particular DMA channel, for linking purpose. If this constraint is not there, that DMA channel thus could not be used at all, because of the unavailability of the desired PaRAM Set.

Field Documentation

+ +
+
+ + + + +
unsigned int EDMA3_DRV_InstanceInitConfig::ownPaRAMSets[EDMA3_MAX_PARAM_DWRDS]
+
+
+ +

+PaRAM Sets owned by the EDMA3 Driver Instance. +

+

+ +

+
+ + + + +
unsigned int EDMA3_DRV_InstanceInitConfig::ownDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS]
+
+
+ +

+DMA Channels owned by the EDMA3 Driver Instance. +

+

+ +

+
+ + + + +
unsigned int EDMA3_DRV_InstanceInitConfig::ownQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS]
+
+
+ +

+QDMA Channels owned by the EDMA3 Driver Instance. +

+

+ +

+
+ + + + +
unsigned int EDMA3_DRV_InstanceInitConfig::ownTccs[EDMA3_MAX_TCC_DWRDS]
+
+
+ +

+TCCs owned by the EDMA3 Driver Instance. +

+

+ +

+
+ + + + +
unsigned int EDMA3_DRV_InstanceInitConfig::resvdPaRAMSets[EDMA3_MAX_PARAM_DWRDS]
+
+
+ +

+Reserved PaRAM Sets. +

+PaRAM Sets reserved during initialization for future use. These will not be given when user requests for ANY available PaRAM Set for linking using 'EDMA3_DRV_LINK_CHANNEL' as channel id. +

+

+ +

+
+ + + + +
unsigned int EDMA3_DRV_InstanceInitConfig::resvdDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS]
+
+
+ +

+Reserved DMA channels. +

+DMA channels reserved during initialization for future use. These will not be given when user requests for ANY available DMA channel using 'EDMA3_DRV_DMA_CHANNEL_ANY' as channel id. +

+

+ +

+
+ + + + +
unsigned int EDMA3_DRV_InstanceInitConfig::resvdQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS]
+
+
+ +

+Reserved QDMA channels. +

+QDMA channels reserved during initialization for future use. These will not be given when user requests for ANY available QDMA channel using 'EDMA3_DRV_QDMA_CHANNEL_ANY' as channel id. +

+

+ +

+
+ + + + +
unsigned int EDMA3_DRV_InstanceInitConfig::resvdTccs[EDMA3_MAX_TCC_DWRDS]
+
+
+ +

+Reserved TCCs. +

+TCCs reserved during initialization for future use. These will not be given when user requests for ANY available TCC using 'EDMA3_DRV_TCC_ANY' as resource id. +

+

+

The documentation for this struct was generated from the following file: +
+
Generated on Thu Oct 16 16:17:56 2008 for EDMA3 Driver by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/drv/docs/html/structedma3__drv__miscparam.html b/packages/ti/sdo/edma3/drv/docs/html/structedma3__drv__miscparam.html new file mode 100644 index 0000000..1084fc1 --- /dev/null +++ b/packages/ti/sdo/edma3/drv/docs/html/structedma3__drv__miscparam.html @@ -0,0 +1,83 @@ + + +EDMA3 Driver: EDMA3_DRV_MiscParam Struct Reference + + + + + +
+

EDMA3_DRV_MiscParam Struct Reference
+ +[EDMA3 Driver Interface Definition] +

Used to specify the miscellaneous options during EDMA3 Driver Initialization. +More... +

+#include <edma3_drv.h> +

+ + + + + + + +

Data Fields

unsigned short isSlave
unsigned short param
+

Detailed Description

+Used to specify the miscellaneous options during EDMA3 Driver Initialization. +

+This configuration structure is used to specify some misc options while creating the Driver object. New options may also be added into this structure in future.

Field Documentation

+ +
+
+ + + + +
unsigned short EDMA3_DRV_MiscParam::isSlave
+
+
+ +

+In a multi-master system (for e.g. ARM + DSP), this option is used to distinguish between Master and Slave. Only the Master is allowed to program the global EDMA3 registers (like Queue priority, Queue water- mark level, error registers etc). +

+

+ +

+
+ + + + +
unsigned short EDMA3_DRV_MiscParam::param
+
+
+ +

+For future use +

+

+

The documentation for this struct was generated from the following file: +
+
Generated on Thu Oct 16 16:17:56 2008 for EDMA3 Driver by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/drv/docs/html/structedma3__drv__object.html b/packages/ti/sdo/edma3/drv/docs/html/structedma3__drv__object.html new file mode 100644 index 0000000..f0fccd6 --- /dev/null +++ b/packages/ti/sdo/edma3/drv/docs/html/structedma3__drv__object.html @@ -0,0 +1,128 @@ + + +EDMA3 Driver: EDMA3_DRV_Object Struct Reference + + + + + +
+

EDMA3_DRV_Object Struct Reference
+ +[Object Maintenance] +

EDMA3 Driver Object (HW Specific) Maintenance structure. +More... +

+#include <edma3.h> +

+ + + + + + + + + + + + +

Data Fields

unsigned int phyCtrllerInstId
EDMA3_DRV_ObjState state
unsigned int numOpens
EDMA3_DRV_GblConfigParams gblCfgParams
 Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information.
+

Detailed Description

+EDMA3 Driver Object (HW Specific) Maintenance structure. +

+Used to maintain information of the EDMA3 HW configuration thoughout the lifetime of the EDMA3 Driver Object, one for each EDMA3 hardware instance.

Field Documentation

+ +
+
+ + + + +
unsigned int EDMA3_DRV_Object::phyCtrllerInstId
+
+
+ +

+Physical Instance ID of EDMA3 Controller +

Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_create(), EDMA3_DRV_enableTransfer(), EDMA3_DRV_freeChannel(), EDMA3_DRV_getOptField(), EDMA3_DRV_getPaRAM(), EDMA3_DRV_getPaRAMEntry(), EDMA3_DRV_getPaRAMField(), EDMA3_DRV_getPaRAMPhyAddr(), EDMA3_DRV_linkChannel(), EDMA3_DRV_requestChannel(), EDMA3_DRV_setDestIndex(), EDMA3_DRV_setDestParams(), EDMA3_DRV_setOptField(), EDMA3_DRV_setPaRAM(), EDMA3_DRV_setPaRAMEntry(), EDMA3_DRV_setPaRAMField(), EDMA3_DRV_setSrcIndex(), EDMA3_DRV_setSrcParams(), EDMA3_DRV_setTransferParams(), EDMA3_DRV_unchainChannel(), EDMA3_DRV_unlinkChannel(), and edma3RemoveMapping().

+ +
+

+ +

+
+ + + + +
EDMA3_DRV_ObjState EDMA3_DRV_Object::state
+
+
+ +

+State information of the EDMA3 Driver object +

Referenced by EDMA3_DRV_close(), EDMA3_DRV_create(), EDMA3_DRV_delete(), and EDMA3_DRV_open().

+ +
+

+ +

+
+ + + + +
unsigned int EDMA3_DRV_Object::numOpens
+
+
+ +

+Number of EDMA3 Driver instances +

Referenced by EDMA3_DRV_close(), EDMA3_DRV_create(), and EDMA3_DRV_open().

+ +
+

+ +

+
+ + + + +
EDMA3_DRV_GblConfigParams EDMA3_DRV_Object::gblCfgParams
+
+
+ +

+Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. +

+This configuration info can be provided by the user at run-time, while calling EDMA3_DRV_create(). If not provided at run-time, this info will be taken from the config file edma3Cfg.c. +

Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_checkAndClearTcc(), EDMA3_DRV_clearErrorBits(), EDMA3_DRV_create(), EDMA3_DRV_disableTransfer(), EDMA3_DRV_enableTransfer(), EDMA3_DRV_freeChannel(), EDMA3_DRV_getCCRegister(), EDMA3_DRV_getInstHandle(), EDMA3_DRV_getMapChToEvtQ(), EDMA3_DRV_getOptField(), EDMA3_DRV_getPaRAM(), EDMA3_DRV_getPaRAMEntry(), EDMA3_DRV_getPaRAMField(), EDMA3_DRV_getPaRAMPhyAddr(), EDMA3_DRV_linkChannel(), EDMA3_DRV_mapChToEvtQ(), EDMA3_DRV_open(), EDMA3_DRV_requestChannel(), EDMA3_DRV_setCCRegister(), EDMA3_DRV_setDestIndex(), EDMA3_DRV_setDestParams(), EDMA3_DRV_setEvtQPriority(), EDMA3_DRV_setOptField(), EDMA3_DRV_setPaRAM(), EDMA3_DRV_setPaRAMEntry(), EDMA3_DRV_setPaRAMField(), EDMA3_DRV_setQdmaTrigWord(), EDMA3_DRV_setSrcIndex(), EDMA3_DRV_setSrcParams(), EDMA3_DRV_setTransferParams(), EDMA3_DRV_unchainChannel(), EDMA3_DRV_unlinkChannel(), EDMA3_DRV_waitAndClearTcc(), and edma3RemoveMapping().

+ +
+

+

The documentation for this struct was generated from the following file: +
+
Generated on Thu Oct 16 16:17:56 2008 for EDMA3 Driver by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/drv/docs/html/structedma3__drv__paramentryregs.html b/packages/ti/sdo/edma3/drv/docs/html/structedma3__drv__paramentryregs.html new file mode 100644 index 0000000..043aa50 --- /dev/null +++ b/packages/ti/sdo/edma3/drv/docs/html/structedma3__drv__paramentryregs.html @@ -0,0 +1,139 @@ + + +EDMA3 Driver: EDMA3_DRV_ParamentryRegs Struct Reference + + + + + +
+

EDMA3_DRV_ParamentryRegs Struct Reference
+ +[EDMA3 Driver Optional Setup for EDMA] +

EDMA3 PaRAM Set. +More... +

+#include <edma3_drv.h> +

+ + + + + + + + + + + + + + + + + + + + + + + + +

Data Fields

volatile unsigned int OPT
+volatile unsigned int SRC
 Starting byte address of Source For FIFO mode, srcAddr must be a 256-bit aligned address.
volatile unsigned int A_B_CNT
+volatile unsigned int DST
 Starting byte address of destination For FIFO mode, destAddr must be a 256-bit aligned address. i.e. 5 LSBs should be 0.
volatile unsigned int SRC_DST_BIDX
volatile unsigned int LINK_BCNTRLD
 Address for linking (AutoReloading of a PaRAM Set) (16 bits) and Reload value of the numArrInFrame (BCNT) (16 bits).
+volatile unsigned int SRC_DST_CIDX
 Index between consecutive frames of a Source Block (SRCCIDX) (16 bits) and Index between consecutive frames of a Dest Block (DSTCIDX) (16 bits).
+volatile unsigned int CCNT
 Number of Frames in a block (CCNT) (16 bits).
+

Detailed Description

+EDMA3 PaRAM Set. +

+This is a mapping of the EDMA3 PaRAM set provided to the user for ease of modification of the individual PaRAM words.

Field Documentation

+ +
+
+ + + + +
volatile unsigned int EDMA3_DRV_ParamentryRegs::OPT
+
+
+ +

+OPT field of PaRAM Set +

+

+ +

+
+ + + + +
volatile unsigned int EDMA3_DRV_ParamentryRegs::A_B_CNT
+
+
+ +

+Number of bytes in each Array (ACNT) (16 bits) and Number of Arrays in each Frame (BCNT) (16 bits). +

+

+ +

+
+ + + + +
volatile unsigned int EDMA3_DRV_ParamentryRegs::SRC_DST_BIDX
+
+
+ +

+Index between consec. arrays of a Source Frame (SRCBIDX) (16 bits) and Index between consec. arrays of a Destination Frame (DSTBIDX) (16 bits).

+If SAM is set to 1 (via channelOptions) then srcInterArrIndex should be an even multiple of 32 bytes.

+If DAM is set to 1 (via channelOptions) then destInterArrIndex should be an even multiple of 32 bytes +

+

+ +

+
+ + + + +
volatile unsigned int EDMA3_DRV_ParamentryRegs::LINK_BCNTRLD
+
+
+ +

+Address for linking (AutoReloading of a PaRAM Set) (16 bits) and Reload value of the numArrInFrame (BCNT) (16 bits). +

+Link field must point to a valid aligned 32-byte PaRAM set A value of 0xFFFF means no linking.

+B count reload field is relevant only for A-sync transfers. +

+

+

The documentation for this struct was generated from the following file: +
+
Generated on Thu Oct 16 16:17:56 2008 for EDMA3 Driver by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/drv/docs/html/structedma3__drv__paramregs.html b/packages/ti/sdo/edma3/drv/docs/html/structedma3__drv__paramregs.html new file mode 100644 index 0000000..15be49e --- /dev/null +++ b/packages/ti/sdo/edma3/drv/docs/html/structedma3__drv__paramregs.html @@ -0,0 +1,110 @@ + + +EDMA3 Driver: EDMA3_DRV_PaRAMRegs Struct Reference + + + + + +
+

EDMA3_DRV_PaRAMRegs Struct Reference
+ +[EDMA3 Driver Optional Setup for EDMA] +

EDMA3 Parameter RAM Set in User Configurable format. +More... +

+#include <edma3_drv.h> +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Data Fields

volatile unsigned int opt
+volatile unsigned int srcAddr
 Starting byte address of Source For FIFO mode, srcAddr must be a 256-bit aligned address.
+volatile unsigned short aCnt
 Number of bytes in each Array (ACNT).
+volatile unsigned short bCnt
 Number of Arrays in each Frame (BCNT).
+volatile unsigned int destAddr
 Starting byte address of destination For FIFO mode, destAddr must be a 256-bit aligned address. i.e. 5 LSBs should be 0.
+volatile short srcBIdx
 Index between consec. arrays of a Source Frame (SRCBIDX) If SAM is set to 1 (via channelOptions) then srcInterArrIndex should be an even multiple of 32 bytes.
+volatile short destBIdx
 Index between consec. arrays of a Destination Frame (DSTBIDX) If DAM is set to 1 (via channelOptions) then destInterArrIndex should be an even multiple of 32 bytes.
+volatile unsigned short linkAddr
 Address for linking (AutoReloading of a PaRAM Set) This must point to a valid aligned 32-byte PaRAM set A value of 0xFFFF means no linking Linking is especially useful for use with ping-pong buffers and circular buffers.
+volatile unsigned short bCntReload
 Reload value of the numArrInFrame (BCNT) Relevant only for A-sync transfers.
+volatile short srcCIdx
 Index between consecutive frames of a Source Block (SRCCIDX).
+volatile short destCIdx
 Index between consecutive frames of a Dest Block (DSTCIDX).
+volatile unsigned short cCnt
 Number of Frames in a block (CCNT).
+

Detailed Description

+EDMA3 Parameter RAM Set in User Configurable format. +

+This is a mapping of the EDMA3 PaRAM set provided to the user for ease of modification of the individual fields

Field Documentation

+ +
+
+ + + + +
volatile unsigned int EDMA3_DRV_PaRAMRegs::opt
+
+
+ +

+OPT field of PaRAM Set +

+

+

The documentation for this struct was generated from the following file: +
+
Generated on Thu Oct 16 16:17:56 2008 for EDMA3 Driver by  + +doxygen 1.5.6
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EDMA3 Driver + uses the EDMA3 Resource Manager internally for resource allocation, + interrupt handling and EDMA3 registers programming. + + (C) Copyright 2006, Texas Instruments, Inc + + \version 0.0.1 Purushotam Kumar - Created + 0.1.0 Joseph Fernandez - Made generic + - Added documentation + - Moved SoC specific defines + to SoC specific header. + 0.2.0 Anuj Aggarwal - Modified it for EDMA3 package + - Added multiple instances + capability + 0.2.1 Anuj Aggarwal - Modified it for more run time + configuration. + - Made EDMA3 package OS + independent. + 0.2.2 Anuj Aggarwal - Critical section handling code + modification. Uses semaphore and + interrupts disabling mechanism + for resource sharing. + 0.3.0 Anuj Aggarwal - Renamed EDMA3_DVR to EDMA3_DRV + - IPR bit clearing in RM ISR + issue fixed. + - Sample application made generic + 0.3.1 Anuj Aggarwal - Added DMA/QDMA Channel to TCC + mapping, to fix QDMA missed + event issue. + 0.3.2 Anuj Aggarwal - Added support for POLL mode + - Added a new API to modify the + CC Register. + 1.0.0 Anuj Aggarwal - Fixed resource allocation related + bugs. + 1.0.0.1 Anuj Aggarwal - Fixed spurious missed event + generation related bug. + 1.0.0.2 Anuj Aggarwal - Made the EDMA3 package RTSC + compliant. + 1.0.0.3 Anuj Aggarwal - Changed the directory structure + as per RTSC standard. + 1.01.00.01 Anuj Aggarwal - a) Added new APIs to allocate + logical channels + b) Created EDMA3 config files + for different platforms + c) Misc changes + 1.02.00.01 Anuj Aggarwal - a) Added DM6467 support + b) Fixed some MRs + 1.03.00.01 Anuj Aggarwal - a) Added non-RTSC PJT files + b) IOCTL Interface added. + c) Fixed some MRs. + 1.04 Anuj Aggarwal - a) Header files modified to have + extern "C" declarations. + b) Implemented ECNs DPSP00009815 + & DPSP00010035. + + */ + +#ifndef _EDMA3_DRV_H_ +#define _EDMA3_DRV_H_ + + +/* Include the Resource Manager header file */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \defgroup Edma3DrvMain EDMA3 Driver Interface Definition + * + * Top-level Encapsulation of all documentation for EDMA3 Driver + * + * @{ + */ + + +/*---------------------------------------------------------------------------*/ +/*------------------Usage Guidelines Start-----------------------------------*/ +/*---------------------------------------------------------------------------*/ + +/** + * \defgroup Edma3DrvUsage EDMA3 Driver Usage Guidelines + * + * Guidelines for typical usage of EDMA3 Driver. + * + * @{ + */ + + +/** + \brief Usage of EDMA3 Driver. + + -# Create EDMA3 Driver Object (one for each EDMA3 hardware instance) + - EDMA3_DRV_Result result = EDMA3_DRV_SOK; + - unsigned int edma3HwInstanceId = 0; + - EDMA3_DRV_GblConfigParams *gblCfgParams = NULL; + - Init-time Configuration structure for EDMA3 controller, to provide + Global SoC specific Information. This could be NULL also. In that + case, static configuration will be taken. + - result = EDMA3_DRV_create (edma3HwInstanceId, gblCfgParams, NULL); + + -# Open EDMA3 driver Instance + - Steps + - EDMA3_DRV_InitConfig initCfg; + - EDMA3_DRV_Handle hEdma = NULL; + - EDMA3_OS_SemAttrs semAttrs = {EDMA3_OS_SEMTYPE_FIFO, NULL}; + - EDMA3_DRV_Result edmaResult; + -To get the error code while opening driver instance + + -# initCfg.regionId = One of the possible regions available + for eg, (EDMA3_RM_RegionId)0 or (EDMA3_RM_RegionId)1 etc, for + different masters. + + -# initCfg.isMaster = TRUE/FALSE (Whether this EDMA3 + DRV instance is Master or not. The EDMA3 Shadow Region tied to + the Master DRV Instance will ONLY receive the EDMA3 interrupts + (error or completion), if enabled). + + -# initCfg.drvSemHandle = + EDMA3 DRV Instance specific semaphore handle. It should + be provided by the user for proper sharing of resources. + - edma3Result = edma3OsSemCreate(1, &semAttrs, + &initCfg.drvSemHandle); + + -# initCfg.drvInstInitConfig = + Init-time Region Specific Configuration Structure. It can be + provided by the user at run-time. If not provided by the user, + this info would be taken from the platform specific config file, + if it exists. + + -# initCfg.drvInstInitConfig->ownDmaChannels[] = + The bitmap(s) which indicate the DMA channels owned by this + instance of the EDMA3 Driver\n + E.g. A '1' at bit position 24 indicates that this instance of + the EDMA3 Driver owns DMA Channel Id 24\n + Later when a request is made based on a particular Channel Id, + the EDMA3 Driver will check first if it owns that channel. + If it doesnot own it, EDMA3 Driver returns error. + -# initCfg.drvInstInitConfig->ownQdmaChannels[] = + The bitmap(s) which indicate the QDMA channels owned by this + instance of the EDMA3 Driver \n + -# initCfg.drvInstInitConfig->ownPaRAMSets[] = + The bitmap(s) which indicate the PaRAM Sets owned by this + instance of the EDMA3 Driver \n + -# initCfg.drvInstInitConfig->ownTccs[] = + The bitmap(s) which indicate the TCCs owned by this + instance of the EDMA3 Driver \n + + -# initCfg.drvInstInitConfig->resvdDmaChannels[] = + The bitmap(s) which indicate the DMA channels reserved by this + instance of the EDMA3 Driver \n + E.g. A '1' at bit position 24 indicates that this instance of + the EDMA3 Driver reserves Channel Id 24\n + These channels are reserved and may be mapped to HW events, + these are not given to 'EDMA3_DRV_DMA_CHANNEL_ANY' requests.\n + -# initCfg.drvInstInitConfig->resvdQdmaChannels[] = + The bitmap(s) which indicate the QDMA channels reserved by this + instance of the EDMA3 Driver \n + E.g. A '1' at bit position 1 indicates that this instance of + the EDMA3 Driver reserves QDMA Channel Id 1\n + These channels are reserved for some specific purpose, + these are not given to 'EDMA3_DRV_QDMA_CHANNEL_ANY' request\n + -# initCfg.drvInstInitConfig->resvdPaRAMSets[] = + PaRAM Sets which are reserved by this Region; + -# initCfg.drvInstInitConfig->resvdTccs[] = + TCCs which are reserved by this Region; + + + -# initCfg.gblerrCb = + Instance wide callback function to catch non-channel specific + errors; + -# initCfg.gblerrData = + Application data to be passed back to the callback function; + + -# hEdma = EDMA3_DRV_open(edma3HwInstanceId, &initCfg, &edmaResult); + + -# EDMA3 driver APIs + - EDMA3_RM_ResDesc resObj; + - EDMA3_DRV_Result result; + - unsigned int ch1Id = 0; + - unsigned int ch2Id = 0; + - unsigned int tcc1 = 0; + - unsigned int tcc2 = 0; + - unsigned int qCh1Id = 0; + - unsigned int qTcc1 = 0; + - unsigned int qCh2Id = 0; + - unsigned int qTcc2 = 0; + - unsigned int paRAMId; + - int srcbidx = 0; + - int desbidx = 0; + - int srccidx = 0; + - int descidx = 0; + - unsigned int acnt = 0; + - unsigned int bcnt = 0; + - unsigned int ccnt = 0; + - unsigned int bcntreload = 0; + - EDMA3_DRV_SyncType synctype; + - EDMA3_RM_TccCallback tccCb; + - void *cbData; + - + - Use Case 1: Memory to memory transfer on any available + - DMA Channel\n\n + - tcc1 = EDMA3_DRV_TCC_ANY; + - ch1Id = EDMA3_DRV_DMA_CHANNEL_ANY; + - result = EDMA3_DRV_requestChannel (hEdma, &ch1Id, &tcc1, + (EDMA3_RM_EventQueue)0, &callback1, NULL); + + - result = EDMA3_DRV_setSrcParams (hEdma, ch1Id, + (unsigned int)(srcBuff1), + EDMA3_DRV_ADDR_MODE_INCR, + EDMA3_DRV_W8BIT); + - result = EDMA3_DRV_setDestParams (hEdma, ch1Id, + (unsigned int)(dstBuff1), + EDMA3_DRV_ADDR_MODE_INCR, + EDMA3_DRV_W8BIT); + + - Set EDMA transfer parameters (aCnt, bCnt, cCnt, bCntReload, + SyncType) + acnt = 256; bcnt = 1; ccnt = 1, bcntreload = 0; + synctype = EDMA3_DRV_SYNC_A; + - result = EDMA3_DRV_setTransferParams (hEdma, ch1Id, acnt, bcnt, + ccnt, bcntreload, synctype); + + - Set srcbidx and srccidx to the appropriate values + - srcbidx = acnt; srccidx = acnt; + - result = EDMA3_DRV_setSrcIndex (hEdma, ch1Id, srcbidx, srccidx); + + - Set desbidx and descidx to the appropriate values + - desbidx = acnt; descidx = acnt; + - result = EDMA3_DRV_setDestIndex (hEdma, ch1Id, desbidx, descidx); + + - Enable the final completion interrupt. + - result = EDMA3_DRV_setOptField (hEdma, ch1Id, + EDMA3_DRV_OPT_FIELD_TCINTEN, 1); + + - Enable the transfer + - result = EDMA3_DRV_enableTransfer (hEdma, ch1Id, + EDMA3_DRV_TRIG_MODE_MANUAL); + + - Use Case 2: Linked memory to memory transfer on any available + - DMA Channel\n\n + - Perform steps as for Use Case 1 for the Master logical channel + ch1Id for configuration. DONOT enable the transfer for ch1Id. + - Configure link channel, ch2Id. + - tcc2 = EDMA3_DRV_TCC_ANY; + - ch2Id = EDMA3_DRV_LINK_CHANNEL; + - result = EDMA3_DRV_requestChannel (hEdma, &ch2Id, &tcc2, + (EDMA3_RM_EventQueue)0, &callback2, NULL); + + - result = EDMA3_DRV_setSrcParams (hEdma, ch2Id, + (unsigned int)(srcBuff2), + EDMA3_DRV_ADDR_MODE_INCR, + EDMA3_DRV_W8BIT); + - result = EDMA3_DRV_setDestParams (hEdma, ch2Id,( + unsigned int)(dstBuff2), + EDMA3_DRV_ADDR_MODE_INCR, + EDMA3_DRV_W8BIT); + + - result = EDMA3_DRV_setSrcIndex (hEdma, ch2Id, srcbidx, srccidx); + - result = EDMA3_DRV_setDestIndex (hEdma, ch2Id, desbidx, descidx); + + - result = EDMA3_DRV_setTransferParams (hEdma, ch2Id, acnt, bcnt, + ccnt, bcntreload, synctype); + + - Link both the channels + - result = EDMA3_DRV_linkChannel (hEdma, ch1Id, ch2Id); + + - Enable the final completion interrupts on both the channels + - result = EDMA3_DRV_setOptField (hEdma, ch1Id, + EDMA3_DRV_OPT_FIELD_TCINTEN, 1); + - result = EDMA3_DRV_setOptField (hEdma, ch2Id, + EDMA3_DRV_OPT_FIELD_TCINTEN, 1); + + - Enable the transfer on channel 1. + - result = EDMA3_DRV_enableTransfer (hEdma, ch1Id, + EDMA3_DRV_TRIG_MODE_MANUAL); + - Wait for the completion interrupt on Ch1 and then enable the + transfer again for the LINK channel, to provide the required + sync event. + - result = EDMA3_DRV_enableTransfer (hEdma, ch1Id, + EDMA3_DRV_TRIG_MODE_MANUAL); + + - Note: Enabling of transfers on channel 1 (for master and link + channel) is required as many number of times as the sync events + are required. For ASync mode, number of sync events=(bcnt * ccnt) + and for ABSync mode, number of sync events = ccnt. + + - Use Case 3: Memory to memory transfer on any available + - QDMA Channel\n\n + - qTcc1 = EDMA3_DRV_TCC_ANY; + - qCh1Id = EDMA3_DRV_QDMA_CHANNEL_ANY; + + - result = EDMA3_DRV_requestChannel (hEdma, &qCh1Id, &qTcc1, + (EDMA3_RM_EventQueue)0, &callback1, NULL); + + - Set the QDMA trigger word. + - result = EDMA3_DRV_setQdmaTrigWord (hEdma, qCh1Id, + EDMA3_RM_QDMA_TRIG_DST); + - Note: DONOT write the destination address (trigger word) before + completing the configuration as it will trigger the + transfer. Also, DONOT use EDMA3_DRV_setDestParams() to set + the destination address as it also sets other parameters. + Use EDMA3_DRV_setPaRAMEntry() to set the destination address + + - result = EDMA3_DRV_setSrcParams (hEdma, qCh1Id, + (unsigned int)(srcBuff1), + EDMA3_DRV_ADDR_MODE_INCR, + EDMA3_DRV_W8BIT); + + - Set QDMA transfer parameters (aCnt, bCnt, cCnt, bCntReload, + SyncType) + acnt = 256; bcnt = 1; ccnt = 1, bcntreload = 0; + synctype = EDMA3_DRV_SYNC_A; + - result = EDMA3_DRV_setTransferParams (hEdma, qCh1Id, acnt, bcnt, + ccnt, bcntreload, synctype); + + - srcbidx = acnt; srccidx = acnt; desbidx = acnt; descidx = acnt; + - result = EDMA3_DRV_setSrcIndex (hEdma, qCh1Id, srcbidx, srccidx); + - result = EDMA3_DRV_setDestIndex (hEdma, qCh1Id, desbidx, descidx); + + - Enable the final completion interrupt. + - result = EDMA3_DRV_setOptField (hEdma, qCh1Id, + EDMA3_DRV_OPT_FIELD_TCINTEN, 1); + + - Set the Destination Addressing Mode as Increment + - result = EDMA3_DRV_setOptField (hEdma, qCh1Id, + EDMA3_DRV_OPT_FIELD_DAM, + EDMA3_DRV_ADDR_MODE_INCR); + + - Trigger the QDMA channel by writing the destination address + - result = EDMA3_DRV_setPaRAMEntry (hEdma, qCh1Id, + EDMA3_DRV_PARAM_ENTRY_DST, + (unsigned int)(dstBuff1)); + + - + - Use Case 4: Linked memory to memory transfer on any available + - QDMA Channel\n\n + - Setup for any QDMA Channel + - qTcc1 = EDMA3_DRV_TCC_ANY; + - qCh1Id = EDMA3_DRV_QDMA_CHANNEL_ANY; + - result = EDMA3_DRV_requestChannel (hEdma, &qCh1Id, &qTcc1, + (EDMA3_RM_EventQueue)0, &callback1, NULL); + + - Setup for Channel 2 + - qCh2Id = EDMA3_DRV_LINK_CHANNEL; + - qTcc2 = EDMA3_DRV_TCC_ANY; + - result = EDMA3_DRV_requestChannel (hEdma, &qCh2Id, &qTcc2, + (EDMA3_RM_EventQueue)0, + &callback2, NULL); + + - result = EDMA3_DRV_setSrcParams (hEdma, qCh2Id, + (unsigned int)(srcBuff2), + EDMA3_DRV_ADDR_MODE_INCR, + EDMA3_DRV_W8BIT); + - result = EDMA3_DRV_setDestParams(hEdma, qCh2Id, + (unsigned int)(dstBuff2), + EDMA3_DRV_ADDR_MODE_INCR, + EDMA3_DRV_W8BIT); + + - acnt = 256; bcnt = 1; ccnt = 1, bcntreload = 0; + synctype = EDMA3_DRV_SYNC_A; + - result = EDMA3_DRV_setTransferParams (hEdma, qCh2Id, acnt, bcnt, + ccnt, BRCnt, + EDMA3_DRV_SYNC_A); + + - srcbidx = acnt; srccidx = acnt; desbidx = acnt; descidx = acnt; + - result = EDMA3_DRV_setSrcIndex (hEdma, qCh2Id, srcbidx, srccidx); + - result = EDMA3_DRV_setDestIndex (hEdma, qCh2Id, desbidx, descidx); + + - result = EDMA3_DRV_setOptField (hEdma, qCh2Id, + EDMA3_DRV_OPT_FIELD_TCINTEN, 1); + + - Make the PaRAM Set associated with qCh2Id as Static + - result = EDMA3_DRV_setOptField (hEdma, qCh2Id, + EDMA3_DRV_OPT_FIELD_STATIC, 1u); + + - Link both the channels + - result = EDMA3_DRV_linkChannel (hEdma,qCh1Id,qCh2Id); + + - Set the QDMA trigger word. + - result = EDMA3_DRV_setQdmaTrigWord (hEdma, qCh1Id, + EDMA3_DRV_QDMA_TRIG_DST); + - Note: DONOT write the destination address (trigger word) before + completing the configuration as it'll trigger the transfer. + Also, DONOT use EDMA3_DRV_setDestParams () function to set + the destination address as it also sets other parameters. + Use EDMA3_DRV_setPaRAMEntry() to set the dest address. + + - result = EDMA3_DRV_setSrcParams (hEdma, qCh1Id, + (unsigned int)(srcBuff1), + EDMA3_DRV_ADDR_MODE_INCR, + EDMA3_DRV_W8BIT); + + - Set QDMA transfer parameters (aCnt, bCnt, cCnt, bCntReload, + SyncType) + acnt = 256; bcnt = 1; ccnt = 1, bcntreload = 0; + synctype = EDMA3_DRV_SYNC_A; + - result = EDMA3_DRV_setTransferParams (hEdma, qCh1Id, acnt, bcnt, + ccnt, bcntreload, synctype); + + - srcbidx = acnt; srccidx = acnt; desbidx = acnt; descidx = acnt; + - result = EDMA3_DRV_setSrcIndex (hEdma, qCh1Id, srcbidx, srccidx); + - result = EDMA3_DRV_setDestIndex (hEdma, qCh1Id, desbidx, descidx); + + - result = EDMA3_DRV_setOptField (hEdma, qCh1Id, + EDMA3_DRV_OPT_FIELD_TCINTEN, 1); + + - Set the Destination Addressing Mode as Increment + - result = EDMA3_DRV_setOptField (hEdma, qCh1Id, + EDMA3_DRV_OPT_FIELD_DAM, + EDMA3_DRV_ADDR_MODE_INCR); + + - Trigger the QDMA channel by writing the destination address + - result = EDMA3_DRV_setPaRAMEntry (hEdma, qCh1Id, + EDMA3_DRV_PARAM_ENTRY_DST, + (unsigned int)(dstBuff1)); + +*/ +/* @} Edma3DrvUsage */ + +/*---------------------------------------------------------------------------*/ +/*------------------Usage Guidelines End-------------------------------------*/ +/*---------------------------------------------------------------------------*/ + + +/** + * \defgroup Edma3DrvErrorCode EDMA3 Driver Error Codes + * + * Error Codes returned by the EDMA3 Driver + * + * @{ + */ +/** EDMA3 Driver Error Codes Base define */ +#define EDMA3_DRV_E_BASE (-128) + +/** + * EDMA3 Driver Object Not Deleted yet. + * So it cannot be created. + */ +#define EDMA3_DRV_E_OBJ_NOT_DELETED (EDMA3_DRV_E_BASE) + +/** + * EDMA3 Driver Object Not Closed yet. + * So it cannot be deleted. + */ +#define EDMA3_DRV_E_OBJ_NOT_CLOSED (EDMA3_DRV_E_BASE-1) + +/** + * EDMA3 Driver Object Not Opened yet + * So it cannot be closed. + */ +#define EDMA3_DRV_E_OBJ_NOT_OPENED (EDMA3_DRV_E_BASE-2) + +/** + * While closing EDMA3 Driver, Resource Manager + * Close Failed. + */ +#define EDMA3_DRV_E_RM_CLOSE_FAIL (EDMA3_DRV_E_BASE-3) + +/** The requested DMA Channel not available */ +#define EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL (EDMA3_DRV_E_BASE-4) + +/** The requested QDMA Channel not available */ +#define EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL (EDMA3_DRV_E_BASE-5) + +/** The requested PaRAM Set not available */ +#define EDMA3_DRV_E_PARAM_SET_UNAVAIL (EDMA3_DRV_E_BASE-6) + +/** The requested TCC not available */ +#define EDMA3_DRV_E_TCC_UNAVAIL (EDMA3_DRV_E_BASE-7) + +/** The registration of TCC failed */ +#define EDMA3_DRV_E_TCC_REGISTER_FAIL (EDMA3_DRV_E_BASE-8) + +/** The binding of Channel and PaRAM Set failed */ +#define EDMA3_DRV_E_CH_PARAM_BIND_FAIL (EDMA3_DRV_E_BASE-9) + +/** + * The address of the memory location passed as argument + * is not properly aligned. It should be 32 bytes aligned. + */ +#define EDMA3_DRV_E_ADDRESS_NOT_ALIGNED (EDMA3_DRV_E_BASE-10) + +/** Invalid Parameter passed to API */ +#define EDMA3_DRV_E_INVALID_PARAM (EDMA3_DRV_E_BASE-11) + +/** Invalid State of EDMA3 HW Obj */ +#define EDMA3_DRV_E_INVALID_STATE (EDMA3_DRV_E_BASE-12) + +/** EDMA3 Driver instance already exists for the specified region */ +#define EDMA3_DRV_E_INST_ALREADY_EXISTS (EDMA3_DRV_E_BASE-13) + +/** FIFO width not supported by the requested TC */ +#define EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED (EDMA3_DRV_E_BASE-14) + +/** Semaphore related error */ +#define EDMA3_DRV_E_SEMAPHORE (EDMA3_DRV_E_BASE-15) + +/** EDMA3 Driver Instance does not exist, it is not opened yet */ +#define EDMA3_DRV_E_INST_NOT_OPENED (EDMA3_DRV_E_BASE-16) + +/* @} Edma3DrvErrorCode */ + + +/** + * This define is used to specify that a DMA channel is NOT tied to any PaRAM + * Set and hence any available PaRAM Set could be used for that DMA channel. + * It could be used in dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH], in global + * configuration structure EDMA3_RM_GblConfigParams. + * + * This value should mandatorily be used to mark DMA channels with no initial + * mapping to specific PaRAM Sets. + */ +#define EDMA3_DRV_CH_NO_PARAM_MAP EDMA3_RM_CH_NO_PARAM_MAP + +/** + * This define is used to specify that the DMA/QDMA channel is not tied to any + * TCC and hence any available TCC could be used for that DMA/QDMA channel. + * It could be used in dmaChannelTccMap [EDMA3_MAX_DMA_CH], in global + * configuration structure EDMA3_RM_GblConfigParams. + * + * This value should mandatorily be used to mark DMA channels with no initial + * mapping to specific TCCs. + */ +#define EDMA3_DRV_CH_NO_TCC_MAP EDMA3_RM_CH_NO_TCC_MAP + + + +/**\struct EDMA3_DRV_GblConfigParams + * \brief Init-time Configuration structure for EDMA3 + * controller, to provide Global SoC specific Information. + * + * This configuration structure is used to specify the EDMA3 Driver + * global settings, specific to the SoC. For e.g. number of DMA/QDMA channels, + * number of PaRAM sets, TCCs, event queues, transfer controllers, base + * addresses of CC global registers and TC registers, interrupt number for + * EDMA3 transfer completion, CC error, event queues' priority, watermark + * threshold level etc. + * This configuration information is SoC specific and could be provided by the + * user at run-time while creating the EDMA3 Driver Object, using API + * EDMA3_DRV_create. In case user doesn't provide it, this information could be + * taken from the SoC specific configuration file edma3__cfg.c, in + * case it is available. + */ +typedef struct { + /** Number of DMA Channels supported by the underlying EDMA3 Controller. */ + unsigned int numDmaChannels; + + /** Number of QDMA Channels supported by the underlying EDMA3 Controller */ + unsigned int numQdmaChannels; + + /** + * Number of Interrupt Channels supported by the underlying EDMA3 + * Controller + */ + unsigned int numTccs; + + /** Number of PaRAM Sets supported by the underlying EDMA3 Controller */ + unsigned int numPaRAMSets; + + /** Number of Event Queues in the underlying EDMA3 Controller */ + unsigned int numEvtQueue; + + /** + * Number of Transfer Controllers (TCs) in the underlying EDMA3 Controller + */ + unsigned int numTcs; + + /** Number of Regions in the underlying EDMA3 Controller */ + unsigned int numRegions; + + /** + * \brief Channel mapping existence + * + * A value of 0 (No channel mapping) implies that there is fixed + * association between a DMA channel and a PaRAM Set or, in other words, + * DMA channel n can ONLY use PaRAM Set n (No availability of DCHMAP + * registers) for transfers to happen. + * + * A value of 1 implies the presence of DCHMAP registers for the DMA + * channels and hence the flexibility of associating any DMA channel to + * any PaRAM Set. In other words, ANY PaRAM Set can be used for ANY DMA + * channel (like QDMA Channels). + */ + unsigned short dmaChPaRAMMapExists; + + /** Existence of memory protection feature */ + unsigned short memProtectionExists; + + /** Base address of EDMA3 CC memory mapped registers. */ + void *globalRegs; + + /** Base address of EDMA3 TCs memory mapped registers. */ + void *tcRegs[EDMA3_MAX_TC]; + + /** + * EDMA3 transfer completion interrupt line (could be different for ARM + * and DSP) + */ + unsigned int xferCompleteInt; + + /** EDMA3 CC error interrupt line (could be different for ARM and DSP) */ + unsigned int ccError; + + /** EDMA3 TCs error interrupt line (could be different for ARM and DSP) */ + unsigned int tcError[EDMA3_MAX_TC]; + + /** + * \brief EDMA3 TC priority setting + * + * User can program the priority of the Event Queues + * at a system-wide level. This means that the user can set the + * priority of an IO initiated by either of the TCs (Transfer Controllers) + * relative to IO initiated by the other bus masters on the + * device (ARM, DSP, USB, etc) + */ + unsigned int evtQPri [EDMA3_MAX_EVT_QUE]; + + /** + * \brief Event Queues Watermark Levels + + * To Configure the Threshold level of number of events + * that can be queued up in the Event queues. EDMA3CC error register + * (CCERR) will indicate whether or not at any instant of time the + * number of events queued up in any of the event queues exceeds + * or equals the threshold/watermark value that is set + * in the queue watermark threshold register (QWMTHRA). + */ + unsigned int evtQueueWaterMarkLvl [EDMA3_MAX_EVT_QUE]; + + /** + * \brief Default Burst Size (DBS) of TCs. + + * An optimally-sized command is defined by the transfer controller + * default burst size (DBS). Different TCs can have different + * DBS values. It is defined in Bytes. + */ + unsigned int tcDefaultBurstSize[EDMA3_MAX_TC]; + + /** + * \brief Mapping from DMA channels to PaRAM Sets + + * If channel mapping exists (DCHMAP registers are present), this array + * stores the respective PaRAM Set for each DMA channel. User can + * initialize each array member with a specific PaRAM Set or with + * EDMA3_DRV_CH_NO_PARAM_MAP. + * If channel mapping doesn't exist, it is of no use as the EDMA3 RM + * automatically uses the right PaRAM Set for that DMA channel. + * Useful only if mapping exists, otherwise of no use. + */ + unsigned int dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH]; + + /** + * \brief Mapping from DMA channels to TCCs + * + * This array stores the respective TCC (interrupt channel) for each + * DMA channel. User can initialize each array member with a specific TCC + * or with EDMA3_DRV_CH_NO_TCC_MAP. This specific + * TCC code will be returned when the transfer is completed + * on the mapped DMA channel. + */ + unsigned int dmaChannelTccMap [EDMA3_MAX_DMA_CH]; + + /** + * \brief Mapping from DMA channels to Hardware Events + * + * Each bit in this array corresponds to one DMA channel and tells whether + * this DMA channel is tied to any peripheral. That is whether any + * peripheral can send the synch event on this DMA channel or not. + * 1 means the channel is tied to some peripheral; 0 means it is not. + * DMA channels which are tied to some peripheral are RESERVED for that + * peripheral only. They are not allocated when user asks for 'ANY' DMA + * channel. + * All channels need not be mapped, some can be free also. + */ + unsigned int dmaChannelHwEvtMap [EDMA3_MAX_DMA_CHAN_DWRDS]; + } EDMA3_DRV_GblConfigParams; + + + +/**\struct EDMA3_DRV_InstanceInitConfig + * \brief Init-time Region Specific Configuration structure for + * EDMA3 Driver, to provide region specific Information. + * + * This configuration structure is used to specify which EDMA3 resources are + * owned and reserved by the EDMA3 Driver instance. This configuration + * structure is shadow region specific and will be provided by the user at + * run-time while calling EDMA3_DRV_open (). + * + * Owned resources: + * **************** + * + * EDMA3 Driver Instances are tied to different shadow regions and hence different + * masters. Regions could be: + * + * a) ARM, + * b) DSP, + * c) IMCOP (Imaging Co-processor) etc. + * + * User can assign each EDMA3 resource to a shadow region using this structure. + * In this way, user specifies which resources are owned by the specific EDMA3 + * DRV Instance. + * This assignment should also ensure that the same resource is not assigned + * to more than one shadow regions (unless desired in that way). Any assignment + * not following the above mentioned approach may have catastrophic + * consequences. + * + * + * Reserved resources: + * ******************* + * + * During EDMA3 DRV initialization, user can reserve some of the EDMA3 resources + * for future use, by specifying which resources to reserve in the configuration + * data structure. These (critical) resources are reserved in advance so that + * they should not be allocated to someone else and thus could be used in + * future for some specific purpose. + * + * User can request different EDMA3 resources using two methods: + * a) By passing the resource type and the actual resource id, + * b) By passing the resource type and ANY as resource id + * + * For e.g. to request DMA channel 31, user will pass 31 as the resource id. + * But to request ANY available DMA channel (mainly used for memory-to-memory + * data transfer operations), user will pass EDMA3_DRV_DMA_CHANNEL_ANY as the + * resource id. + * + * During initialization, user may have reserved some of the DMA channels for + * some specific purpose (mainly for peripherals using EDMA). These reserved + * DMA channels then will not be returned when user requests ANY as the + * resource id. + * + * Same logic applies for QDMA channels and TCCs. + * + * For PaRAM Set, there is one difference. If the DMA channels are one-to-one + * tied to their respective PaRAM Sets (i.e. user cannot 'choose' the PaRAM Set + * for a particular DMA channel), EDMA3 Driver automatically reserves all those + * PaRAM Sets which are tied to the DMA channels. Then those PaRAM Sets would + * not be returned when user requests for ANY PaRAM Set (specifically for + * linking purpose). This is done in order to avoid allocating the PaRAM Set, + * tied to a particular DMA channel, for linking purpose. If this constraint is + * not there, that DMA channel thus could not be used at all, because of the + * unavailability of the desired PaRAM Set. + */ +typedef struct +{ + /** PaRAM Sets owned by the EDMA3 Driver Instance. */ + unsigned int ownPaRAMSets[EDMA3_MAX_PARAM_DWRDS]; + + /** DMA Channels owned by the EDMA3 Driver Instance. */ + unsigned int ownDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS]; + + /** QDMA Channels owned by the EDMA3 Driver Instance. */ + unsigned int ownQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS]; + + /** TCCs owned by the EDMA3 Driver Instance. */ + unsigned int ownTccs[EDMA3_MAX_TCC_DWRDS]; + + /** + * \brief Reserved PaRAM Sets + * + * PaRAM Sets reserved during initialization for future use. These will not + * be given when user requests for ANY available PaRAM Set for linking + * using 'EDMA3_DRV_LINK_CHANNEL' as channel id. + */ + unsigned int resvdPaRAMSets[EDMA3_MAX_PARAM_DWRDS]; + + /** + * \brief Reserved DMA channels + * + * DMA channels reserved during initialization for future use. These will + * not be given when user requests for ANY available DMA channel using + * 'EDMA3_DRV_DMA_CHANNEL_ANY' as channel id. + */ + unsigned int resvdDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS]; + + /** + * \brief Reserved QDMA channels + * + * QDMA channels reserved during initialization for future use. These will + * not be given when user requests for ANY available QDMA channel using + * 'EDMA3_DRV_QDMA_CHANNEL_ANY' as channel id. + */ + unsigned int resvdQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS]; + + /** + * \brief Reserved TCCs + * + * TCCs reserved during initialization for future use. These will not + * be given when user requests for ANY available TCC using + * 'EDMA3_DRV_TCC_ANY' as resource id. + */ + unsigned int resvdTccs[EDMA3_MAX_TCC_DWRDS]; +}EDMA3_DRV_InstanceInitConfig; + + + +/**\struct EDMA3_DRV_InitConfig + * \brief Used to Initialize the EDMA3 Driver Instance + * + * This configuration structure is used to initialize the EDMA3 DRV Instance. + * This configuration information is passed while opening the DRV instance. + */ +typedef struct +{ + /** Region Identification */ + EDMA3_RM_RegionId regionId; + + /** + * It tells whether the EDMA3 DRV instance is Master or not. Only the shadow + * region associated with this master instance will receive the EDMA3 + * interrupts (if enabled). + */ + unsigned short isMaster; + + /** + * EDMA3 resources related shadow region specific information. Which all + * EDMA3 resources are owned and reserved by this particular instance are + * told in this configuration structure. + * User can also pass this structure as NULL. In that case, default static + * configuration would be taken from the platform specific configuration + * files (part of the Resource Manager), if available. + */ + EDMA3_DRV_InstanceInitConfig *drvInstInitConfig; + + /** + * EDMA3 Driver Instance specific semaphore handle. + * Used to share resources (DMA/QDMA channels, PaRAM Sets, TCCs etc) + * among different users. + */ + void *drvSemHandle; + + /** + * Instance wide global callback function to catch non-channel + * specific errors from the Channel controller. for eg, TCC + * error, queue threshold exceed error etc. + */ + EDMA3_RM_GblErrCallback gblerrCb; + + /** + * Application data to be passed back to the global error callback + * function + */ + void *gblerrData; +} EDMA3_DRV_InitConfig; + + + +/**\struct EDMA3_DRV_MiscParam + * \brief Used to specify the miscellaneous options during EDMA3 Driver + * Initialization. + * + * This configuration structure is used to specify some misc options + * while creating the Driver object. New options may also be added into this + * structure in future. + */ +typedef struct { + /** + * In a multi-master system (for e.g. ARM + DSP), this option is used to + * distinguish between Master and Slave. Only the Master is allowed to + * program the global EDMA3 registers (like Queue priority, Queue water- + * mark level, error registers etc). + */ + unsigned short isSlave; + + /** For future use **/ + unsigned short param; +}EDMA3_DRV_MiscParam; + + +/** + * \brief Create EDMA3 Driver Object + * + * This API is used to create the EDMA3 Driver Object. It should be + * called only ONCE for each EDMA3 hardware instance. + * + * Init-time Configuration structure for EDMA3 hardware is provided to pass the + * SoC specific information. This configuration information could be provided + * by the user at init-time. In case user doesn't provide it, this information + * could be taken from the SoC specific configuration file + * edma3__cfg.c, in case it is available. + * + * This API clears the error specific registers (EMCR/EMCRh, QEMCR, CCERRCLR) + * and sets the TCs priorities and Event Queues' watermark levels, if the 'miscParam' + * argument is NULL. User can avoid these registers' programming (in some specific + * use cases) by SETTING the 'isSlave' field of 'EDMA3_RM_MiscParam' configuration + * structure and passing this structure as the third argument (miscParam). + * + * After successful completion of this API, Driver Object's state + * changes to EDMA3_DRV_CREATED from EDMA3_DRV_DELETED. + * + * \param phyCtrllerInstId [IN] EDMA3 Controller Instance Id + * (Hardware instance id, starting from 0). + * \param gblCfgParams [IN] SoC specific configuration structure for the + * EDMA3 Hardware. + * \param miscParam [IN] Misc configuration options provided in the + * structure 'EDMA3_DRV_MiscParam'. + * For default options, user can pass NULL + * in this argument. + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error code + */ +EDMA3_DRV_Result EDMA3_DRV_create (unsigned int phyCtrllerInstId, + const EDMA3_DRV_GblConfigParams *gblCfgParams, + const void *miscParam); + + +/** + * \brief Delete EDMA3 Driver Object + * + * Use this API to delete the EDMA3 Driver Object. It should be called only + * ONCE for each EDMA3 hardware instance. It should be called ONLY after + * closing all the EDMA3 Driver Instances. + * + * This API is used to delete the EDMA3 Driver Object. It should be called + * once for each EDMA3 hardware instance, ONLY after closing all the + * previously opened EDMA3 Driver Instances. + * + * After successful completion of this API, Driver Object's state + * changes to EDMA3_DRV_DELETED. + * + * \param phyCtrllerInstId [IN] EDMA3 Phy Controller Instance Id (Hardware + * instance id, starting from 0). + * \param param [IN] For possible future use. + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error code + */ +EDMA3_DRV_Result EDMA3_DRV_delete (unsigned int phyCtrllerInstId, + const void *param); + + + +/** + * \brief Open EDMA3 Driver Instance + * + * This API is used to open an EDMA3 Driver Instance. It could be + * called multiple times, for each possible EDMA3 shadow region. Maximum + * EDMA3_MAX_REGIONS instances are allowed for each EDMA3 hardware + * instance. Multiple instances on the same shadow region are NOT allowed. + * + * Also, only ONE Master Driver Instance is permitted. This master + * instance (and hence the region to which it belongs) will only receive the + * EDMA3 interrupts, if enabled. + * + * User could pass the instance specific configuration structure + * (initCfg.drvInstInitConfig) as a part of the 'initCfg' structure, + * during init-time. In case user doesn't provide it, this information could + * be taken from the SoC specific configuration file edma3__cfg.c, + * in case it is available. + * + * By default, this EDMA3 Driver instance will clear the PaRAM Sets while + * allocating them. To change the default behavior, user should use the IOCTL + * interface appropriately. + * + * \param phyCtrllerInstId [IN] EDMA3 Controller Instance Id (Hardware + * instance id, starting from 0). + * \param initCfg [IN] Used to Initialize the EDMA3 Driver + * Instance (Master or Slave). + * \param errorCode [OUT] Error code while opening DRV instance. + * + * \return EDMA3_DRV_Handle : If successfully opened, the API will return the + * associated driver's instance handle. + * + * \note This function disables the global interrupts (by calling API + * edma3OsProtectEntry with protection level + * EDMA3_OS_PROTECT_INTERRUPT) while modifying the global data + * structures, to make it re-entrant. + */ +EDMA3_DRV_Handle EDMA3_DRV_open (unsigned int phyCtrllerInstId, + const EDMA3_DRV_InitConfig *initCfg, + EDMA3_DRV_Result *errorCode); + + +/** + * \brief Close the EDMA3 Driver Instance. + * + * This API is used to close a previously opened EDMA3 Driver Instance. + * + * \param hEdma [IN] Handle to the previously opened EDMA3 + * Driver Instance. + * \param param [IN] For possible future use + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error code + * + * \note This function disables the global interrupts (by calling API + * edma3OsProtectEntry with protection level + * EDMA3_OS_PROTECT_INTERRUPT) while modifying the global data + * structures, to make it re-entrant. + */ +EDMA3_DRV_Result EDMA3_DRV_close (EDMA3_DRV_Handle hEdma, + const void *param); + + + +/** + * \defgroup Edma3DrvChannelSetup EDMA3 Driver Channel Setup + * + * Channel related Interface of the EDMA3 Driver + * + * @{ + */ + +/* Defines for Logical Channel Values */ +/*---------------------------------------------------------------------------*/ +/** + * Used to specify any available DMA Channel while requesting + * one. Used in the API EDMA3_DRV_requestChannel(). + * DMA channel from the pool of (owned && non_reserved && available_right_now) + * DMA channels will be chosen and returned. + */ +#define EDMA3_DRV_DMA_CHANNEL_ANY 1002u + +/** + * Used to specify any available QDMA Channel while requesting + * one. Used in the API EDMA3_DRV_requestChannel(). + * QDMA channel from the pool of (owned && non_reserved && available_right_now) + * QDMA channels will be chosen and returned. + */ +#define EDMA3_DRV_QDMA_CHANNEL_ANY 1003u + +/** + * Used to specify any available TCC while requesting + * one. Used in the API EDMA3_DRV_requestChannel(), for + * both DMA and QDMA channels. + * TCC from the pool of (owned && non_reserved && available_right_now) + * TCCs will be chosen and returned. + */ +#define EDMA3_DRV_TCC_ANY 1004u + +/** + * Used to specify any available PaRAM Set while requesting + * one. Used in the API EDMA3_DRV_requestChannel(), for Link channels. + * PaRAM Set from the pool of (owned && non_reserved && available_right_now) + * PaRAM Sets will be chosen and returned. + */ +#define EDMA3_DRV_LINK_CHANNEL 1005u +/*---------------------------------------------------------------------------*/ + + +/** + * \brief DMA Channels assigned to different Hardware Events. + * They should be used while requesting a specific DMA channel. + * One possible usage is to maintain a SoC specific file, which will + * contain the mapping of these hardware events to the respective + * peripherals for better understanding and lesser probability of + * errors. Also, if any event associated with a particular peripheral + * gets changed, only that SoC specific file needs to be changed. + * + * for eg, the sample SoC specific file "soc.h" can have these defines: + * + * #define EDMA3_DRV_HW_CHANNEL_MCBSP_TX EDMA3_DRV_HW_CHANNEL_EVENT_2 + * #define EDMA3_DRV_HW_CHANNEL_MCBSP_RX EDMA3_DRV_HW_CHANNEL_EVENT_3 + * + * These defines will be used by the MCBSP driver. The same event + * EDMA3_DRV_HW_CHANNEL_EVENT_2/3 could be mapped to some other + * peripheral also. + */ +typedef enum +{ + /** Channel assigned to EDMA3 Event 0 */ + EDMA3_DRV_HW_CHANNEL_EVENT_0 = 0, + /** Channel assigned to EDMA3 Event 1 */ + EDMA3_DRV_HW_CHANNEL_EVENT_1, + /** Channel assigned to EDMA3 Event 2 */ + EDMA3_DRV_HW_CHANNEL_EVENT_2, + /** Channel assigned to EDMA3 Event 3 */ + EDMA3_DRV_HW_CHANNEL_EVENT_3, + /** Channel assigned to EDMA3 Event 4 */ + EDMA3_DRV_HW_CHANNEL_EVENT_4, + /** Channel assigned to EDMA3 Event 5 */ + EDMA3_DRV_HW_CHANNEL_EVENT_5, + /** Channel assigned to EDMA3 Event 6 */ + EDMA3_DRV_HW_CHANNEL_EVENT_6, + /** Channel assigned to EDMA3 Event 7 */ + EDMA3_DRV_HW_CHANNEL_EVENT_7, + /** Channel assigned to EDMA3 Event 8 */ + EDMA3_DRV_HW_CHANNEL_EVENT_8, + /** Channel assigned to EDMA3 Event 9 */ + EDMA3_DRV_HW_CHANNEL_EVENT_9, + /** Channel assigned to EDMA3 Event 10 */ + EDMA3_DRV_HW_CHANNEL_EVENT_10, + /** Channel assigned to EDMA3 Event 11 */ + EDMA3_DRV_HW_CHANNEL_EVENT_11, + /** Channel assigned to EDMA3 Event 12 */ + EDMA3_DRV_HW_CHANNEL_EVENT_12, + /** Channel assigned to EDMA3 Event 13 */ + EDMA3_DRV_HW_CHANNEL_EVENT_13, + /** Channel assigned to EDMA3 Event 14 */ + EDMA3_DRV_HW_CHANNEL_EVENT_14, + /** Channel assigned to EDMA3 Event 15 */ + EDMA3_DRV_HW_CHANNEL_EVENT_15, + /** Channel assigned to EDMA3 Event 16 */ + EDMA3_DRV_HW_CHANNEL_EVENT_16, + /** Channel assigned to EDMA3 Event 17 */ + EDMA3_DRV_HW_CHANNEL_EVENT_17, + /** Channel assigned to EDMA3 Event 18 */ + EDMA3_DRV_HW_CHANNEL_EVENT_18, + /** Channel assigned to EDMA3 Event 19 */ + EDMA3_DRV_HW_CHANNEL_EVENT_19, + /** Channel assigned to EDMA3 Event 20 */ + EDMA3_DRV_HW_CHANNEL_EVENT_20, + /** Channel assigned to EDMA3 Event 21 */ + EDMA3_DRV_HW_CHANNEL_EVENT_21, + /** Channel assigned to EDMA3 Event 22 */ + EDMA3_DRV_HW_CHANNEL_EVENT_22, + /** Channel assigned to EDMA3 Event 23 */ + EDMA3_DRV_HW_CHANNEL_EVENT_23, + /** Channel assigned to EDMA3 Event 24 */ + EDMA3_DRV_HW_CHANNEL_EVENT_24, + /** Channel assigned to EDMA3 Event 25 */ + EDMA3_DRV_HW_CHANNEL_EVENT_25, + /** Channel assigned to EDMA3 Event 26 */ + EDMA3_DRV_HW_CHANNEL_EVENT_26, + /** Channel assigned to EDMA3 Event 27 */ + EDMA3_DRV_HW_CHANNEL_EVENT_27, + /** Channel assigned to EDMA3 Event 28 */ + EDMA3_DRV_HW_CHANNEL_EVENT_28, + /** Channel assigned to EDMA3 Event 29 */ + EDMA3_DRV_HW_CHANNEL_EVENT_29, + /** Channel assigned to EDMA3 Event 30 */ + EDMA3_DRV_HW_CHANNEL_EVENT_30, + /** Channel assigned to EDMA3 Event 31 */ + EDMA3_DRV_HW_CHANNEL_EVENT_31, + /** Channel assigned to EDMA3 Event 32 */ + EDMA3_DRV_HW_CHANNEL_EVENT_32, + /** Channel assigned to EDMA3 Event 33 */ + EDMA3_DRV_HW_CHANNEL_EVENT_33, + /** Channel assigned to EDMA3 Event 34 */ + EDMA3_DRV_HW_CHANNEL_EVENT_34, + /** Channel assigned to EDMA3 Event 35 */ + EDMA3_DRV_HW_CHANNEL_EVENT_35, + /** Channel assigned to EDMA3 Event 36 */ + EDMA3_DRV_HW_CHANNEL_EVENT_36, + /** Channel assigned to EDMA3 Event 37 */ + EDMA3_DRV_HW_CHANNEL_EVENT_37, + /** Channel assigned to EDMA3 Event 38 */ + EDMA3_DRV_HW_CHANNEL_EVENT_38, + /** Channel assigned to EDMA3 Event 39 */ + EDMA3_DRV_HW_CHANNEL_EVENT_39, + /** Channel assigned to EDMA3 Event 40 */ + EDMA3_DRV_HW_CHANNEL_EVENT_40, + /** Channel assigned to EDMA3 Event 41 */ + EDMA3_DRV_HW_CHANNEL_EVENT_41, + /** Channel assigned to EDMA3 Event 42 */ + EDMA3_DRV_HW_CHANNEL_EVENT_42, + /** Channel assigned to EDMA3 Event 43 */ + EDMA3_DRV_HW_CHANNEL_EVENT_43, + /** Channel assigned to EDMA3 Event 44 */ + EDMA3_DRV_HW_CHANNEL_EVENT_44, + /** Channel assigned to EDMA3 Event 45 */ + EDMA3_DRV_HW_CHANNEL_EVENT_45, + /** Channel assigned to EDMA3 Event 46 */ + EDMA3_DRV_HW_CHANNEL_EVENT_46, + /** Channel assigned to EDMA3 Event 47 */ + EDMA3_DRV_HW_CHANNEL_EVENT_47, + /** Channel assigned to EDMA3 Event 48 */ + EDMA3_DRV_HW_CHANNEL_EVENT_48, + /** Channel assigned to EDMA3 Event 49 */ + EDMA3_DRV_HW_CHANNEL_EVENT_49, + /** Channel assigned to EDMA3 Event 50 */ + EDMA3_DRV_HW_CHANNEL_EVENT_50, + /** Channel assigned to EDMA3 Event 51 */ + EDMA3_DRV_HW_CHANNEL_EVENT_51, + /** Channel assigned to EDMA3 Event 52 */ + EDMA3_DRV_HW_CHANNEL_EVENT_52, + /** Channel assigned to EDMA3 Event 53 */ + EDMA3_DRV_HW_CHANNEL_EVENT_53, + /** Channel assigned to EDMA3 Event 54 */ + EDMA3_DRV_HW_CHANNEL_EVENT_54, + /** Channel assigned to EDMA3 Event 55 */ + EDMA3_DRV_HW_CHANNEL_EVENT_55, + /** Channel assigned to EDMA3 Event 56 */ + EDMA3_DRV_HW_CHANNEL_EVENT_56, + /** Channel assigned to EDMA3 Event 57 */ + EDMA3_DRV_HW_CHANNEL_EVENT_57, + /** Channel assigned to EDMA3 Event 58 */ + EDMA3_DRV_HW_CHANNEL_EVENT_58, + /** Channel assigned to EDMA3 Event 59 */ + EDMA3_DRV_HW_CHANNEL_EVENT_59, + /** Channel assigned to EDMA3 Event 60 */ + EDMA3_DRV_HW_CHANNEL_EVENT_60, + /** Channel assigned to EDMA3 Event 61 */ + EDMA3_DRV_HW_CHANNEL_EVENT_61, + /** Channel assigned to EDMA3 Event 62 */ + EDMA3_DRV_HW_CHANNEL_EVENT_62, + /** Channel assigned to EDMA3 Event 63 */ + EDMA3_DRV_HW_CHANNEL_EVENT_63 +} EDMA3_DRV_HW_CHANNEL_EVENT; + + +/** + * \brief QDMA Channel defines + * They should be used while requesting a specific QDMA channel. + */ +/** QDMA Channel 0 */ +#define EDMA3_DRV_QDMA_CHANNEL_0 (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS) +/** QDMA Channel 1 */ +#define EDMA3_DRV_QDMA_CHANNEL_1 (EDMA3_DRV_QDMA_CHANNEL_0+1u) +/** QDMA Channel 2 */ +#define EDMA3_DRV_QDMA_CHANNEL_2 (EDMA3_DRV_QDMA_CHANNEL_0+2u) +/** QDMA Channel 3 */ +#define EDMA3_DRV_QDMA_CHANNEL_3 (EDMA3_DRV_QDMA_CHANNEL_0+3u) +/** QDMA Channel 4 */ +#define EDMA3_DRV_QDMA_CHANNEL_4 (EDMA3_DRV_QDMA_CHANNEL_0+4u) +/** QDMA Channel 5 */ +#define EDMA3_DRV_QDMA_CHANNEL_5 (EDMA3_DRV_QDMA_CHANNEL_0+5u) +/** QDMA Channel 6 */ +#define EDMA3_DRV_QDMA_CHANNEL_6 (EDMA3_DRV_QDMA_CHANNEL_0+6u) +/** QDMA Channel 7 */ +#define EDMA3_DRV_QDMA_CHANNEL_7 (EDMA3_DRV_QDMA_CHANNEL_0+7u) + + + +/** + * \brief Request a DMA/QDMA/Link channel. + * + * Each channel (DMA/QDMA/Link) must be requested before initiating a DMA + * transfer on that channel. + * + * This API is used to allocate a logical channel (DMA/QDMA/Link) along with + * the associated resources. For DMA and QDMA channels, TCC and PaRAM Set are + * also allocated along with the requested channel. For Link channel, ONLY a + * PaRAM Set is allocated. + * + * User can request a specific logical channel by passing the channel id in + * 'pLCh'. Note that the channel id is the same as the actual resource id in + * case of DMA channels. To allocate specific QDMA channels, user SHOULD use the + * defines EDMA3_DRV_QDMA_CHANNEL_X mentioned above. + * + * User can also request ANY available logical channel also by specifying the + * below mentioned values in '*pLCh': + * a) EDMA3_DRV_DMA_CHANNEL_ANY: For DMA channels + * b) EDMA3_DRV_QDMA_CHANNEL_ANY: For QDMA channels, and + * c) EDMA3_DRV_LINK_CHANNEL: For Link channels. Normally user should use this + * value to request link channels (PaRAM Sets used for linking purpose + * only), unless he wants to use some specific link channels (PaRAM Sets) + * which is also allowed. + * + * This API internally uses EDMA3_RM_allocResource () to allocate the desired + * resources (DMA/QDMA channel, PaRAM Set and TCC). + * + * This API also registers a specific callback function against the allocated + * TCC. + * + * For DMA/QDMA channels, after allocating all the EDMA3 resources, this API + * sets the TCC field of the OPT PaRAM Word with the allocated TCC. It also sets + * the event queue for the channel allocated. The event queue needs to be + * specified by the user. + * + * For DMA channel, it also sets the DCHMAP register, if required. + * + * For QDMA channel, it sets the QCHMAP register and CCNT as trigger word and + * enables the QDMA channel by writing to the QEESR register. + * + * \param hEdma [IN] Handle to the previously opened Driver + * Instance. + * \param pLCh [IN/OUT] Requested logical channel id. + * Examples: + * - EDMA3_DRV_HW_CHANNEL_EVENT_0 + * - To request a DMA Master Channel + * mapped to EDMA Event 0. + * + * - EDMA3_DRV_DMA_CHANNEL_ANY + * - For requesting any DMA Master channel + * with no event mapping. + * + * - EDMA3_DRV_QDMA_CHANNEL_ANY + * - For requesting any QDMA Master channel + * + * - EDMA3_DRV_QDMA_CHANNEL_0 + * - For requesting the QDMA Channel 0. + * + * - EDMA3_DRV_LINK_CHANNEL + * - For requesting a DMA Slave Channel, + * - to be linked to some other Master + * - channel. + * + * In case user passes a specific channel + * Id, pLCh value is left unchanged. In + * case user requests ANY available + * resource, the allocated channel id is + * returned in pLCh. + * + * \note To request a PaRAM Set for the purpose of + * linking to another channel, call the function with + * + * *pLCh = EDMA3_DRV_LINK_CHANNEL; + * + * This function will update *pLCh with the allocated Link channel + * handle. This handle could be DIFFERENT from the actual PaRAM Set + * allocated by the Resource Manager internally. So user SHOULD NOT + * assume the handle as the PaRAM Set Id. + * + * \param pTcc [IN/OUT] The channel number on which the + * completion/error interrupt is generated. + * Not used if user requested for a Link + * channel. + * Examples: + * - EDMA3_DRV_HW_CHANNEL_EVENT_0 + * - To request TCC associated with + * - DMA Master Channel mapped to EDMA + * - event 0. + * + * - EDMA3_DRV_TCC_ANY + * - For requesting any TCC with no + * - channel mapping. + * In case user passes a specific TCC + * value, pTcc value is left unchanged. + * In case user requests ANY available TCC, + * the allocated one is returned in pTcc + * + * \param evtQueue [IN] Event Queue Number to which the channel + * will be mapped (valid only for the + * Master Channel (DMA/QDMA) request) + * + * \param tccCb [IN] TCC callback - caters to channel- + * specific events like "Event Miss Error" + * or "Transfer Complete" + * + * \param cbData [IN] Data which will be passed directly to + * the tccCb callback function + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error code + * + * \note This function internally uses EDMA3 Resource Manager, which + * acquires a RM Instance specific semaphore + * to prevent simultaneous access to the global pool of resources. + * It also disables the global interrupts while modifying + * the global CC registers. + * It is re-entrant, but SHOULD NOT be called from the user callback + * function (ISR context). + */ +EDMA3_DRV_Result EDMA3_DRV_requestChannel (EDMA3_DRV_Handle hEdma, + unsigned int *pLCh, + unsigned int *pTcc, + EDMA3_RM_EventQueue evtQueue, + EDMA3_RM_TccCallback tccCb, + void *cbData); + + +/** + * \brief Free the specified channel (DMA/QDMA/Link) and its associated + * resources (PaRAM Set, TCC etc) and removes various mappings. + * + * This API internally uses EDMA3_RM_freeResource () to free the desired + * resources. + * + * For Link channels, this API only frees the associated PaRAM Set. + * + * For DMA/QDMA channels, it does the following operations: + * a) Disable any ongoing transfer on the channel, + * b) Unregister the TCC Callback function and disable the interrupts, + * c) Remove the channel to Event Queue mapping, + * d) For DMA channels, clear the DCHMAP register, if available + * e) For QDMA channels, clear the QCHMAP register, + * f) Frees the DMA/QDMA channel in the end. + * + * \param hEdma [IN] Handle to the EDMA Driver Instance. + * \param channelId [IN] Logical Channel number to be freed. + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error code + * + * \note This function disables the global interrupts while modifying + * the global CC registers and while modifying global data structures, + * to prevent simultaneous access to the global pool of resources. + * It internally calls EDMA3_RM_freeResource () for resource + * de-allocation. It is re-entrant. + */ +EDMA3_DRV_Result EDMA3_DRV_freeChannel (EDMA3_DRV_Handle hEdma, + unsigned int channelId); + + + +/** + * \brief Clears Event Register and Error Register for a specific + * DMA channel and brings back EDMA3 to its initial state. + * + * This API clears the Event register, Event Miss register Event Enable + * register for a specific DMA channel. It also clears the CC Error register. + * + * \param hEdma [IN] Handle to the EDMA Driver Instance. + * \param channelId [IN] DMA Channel needs to be cleaned. + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error code + * + * \note This function is re-entrant for unique channelId values. It is non- + * re-entrant for same channelId value. + */ +EDMA3_DRV_Result EDMA3_DRV_clearErrorBits (EDMA3_DRV_Handle hEdma, + unsigned int channelId); + + +/** + * \brief Link two logical channels. + * + * This API is used to link two previously allocated logical (DMA/QDMA/Link) + * channels. + * + * It sets the Link field of the PaRAM set associated with first logical + * channel (lCh1) to point it to the PaRAM set associated with second logical + * channel (lCh2). + * + * It also sets the TCC field of PaRAM set associated with second logical + * channel to the same as that of the first logical channel. + * + * After linking the channels, user should not update any PaRAM Set of the + * channel. + * + * \param hEdma [IN] Handle to the EDMA Driver Instance. + * \param lCh1 [IN] Logical Channel to which particular channel + * will be linked. + * \param lCh2 [IN] Logical Channel which needs to be linked to + * the first channel. + * After the transfer based on the PaRAM set + * of lCh1 is over, the PaRAM set of lCh2 will + * be copied to the PaRAM set of lCh1 and + * transfer will resume. + * For DMA channels, another sync event is + * required to initiate the transfer on the + * Link channel. + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant for unique lCh1 & lCh2 values. It is + * non-re-entrant for same lCh1 & lCh2 values. + */ +EDMA3_DRV_Result EDMA3_DRV_linkChannel ( EDMA3_DRV_Handle hEdma, + unsigned int lCh1, + unsigned int lCh2); + + + +/** + * \brief Unlink the channel from the earlier linked logical channel. + * + * This function breaks the link between the specified + * channel and the earlier linked logical channel + * by clearing the Link Address field. + * + * \param hEdma [IN] Handle to the EDMA Driver Instance. + * \param lCh [IN] Channel for which linking has to be removed + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant for unique lCh values. It is non- + * re-entrant for same lCh value. + */ +EDMA3_DRV_Result EDMA3_DRV_unlinkChannel (EDMA3_DRV_Handle hEdma, + unsigned int lCh); + +/* @} Edma3DrvChannelSetup */ + + + +/** + * \defgroup Edma3DrvTransferSetupType EDMA3 Driver Typical EDMA Transfer Setup + * + * The typical EDMA transfer related Interface of the EDMA3 Driver + * + * @{ + */ + +/** + * \brief OPT Field Offset. + * + * Use this enum to set or get any of the + * Fields within an OPT of a Parameter RAM set. + */ +typedef enum +{ + /** + * Source addressing mode (INCR / FIFO) + * (Bit 0) + */ + EDMA3_DRV_OPT_FIELD_SAM = 0, + + /** + * Destination addressing mode (INCR / FIFO) + * (Bit 1) + */ + EDMA3_DRV_OPT_FIELD_DAM = 1, + + /** + * Transfer synchronization dimension (A-synchronized / AB-synchronized) + * (Bit 2) + */ + EDMA3_DRV_OPT_FIELD_SYNCDIM = 2, + + /** + * The STATIC field + * PaRAM set is static/non-static? + * (Bit 3) + */ + EDMA3_DRV_OPT_FIELD_STATIC = 3, + + /** + * FIFO Width. Applies if either SAM or DAM is set to FIFO mode. + * (Bitfield 8-10) + */ + EDMA3_DRV_OPT_FIELD_FWID = 4, + + /** + * Transfer complete code mode. Indicates the point at which a + * transfer is considered completed for chaining and interrupt + * generation. + * (Bit 11) + */ + EDMA3_DRV_OPT_FIELD_TCCMODE = 5, + + /** + * Transfer Complete Code (TCC). + * This 6-bit code is used to set the relevant bit in chaining enable + * register (CER[TCC]/CERH[TCC]) for chaining or in interrupt pending + * register (IPR[TCC]/IPRH[TCC]) for interrupts. + * (Bitfield 12-17) + */ + EDMA3_DRV_OPT_FIELD_TCC = 6, + + /** + * Transfer complete interrupt enable/disable. + * (Bit 20) + */ + EDMA3_DRV_OPT_FIELD_TCINTEN = 7, + + /** + * Intermediate transfer complete interrupt enable/disable. + * (Bit 21) + */ + EDMA3_DRV_OPT_FIELD_ITCINTEN = 8, + + /** + * Transfer complete chaining enable/disable + * (Bit 22) + */ + EDMA3_DRV_OPT_FIELD_TCCHEN = 9, + + /** + * Intermediate transfer completion chaining enable/disable + * (Bit 23) + */ + EDMA3_DRV_OPT_FIELD_ITCCHEN = 10 + +} EDMA3_DRV_OptField; + + +/** + * \brief EDMA Addressing modes + * + * The EDMA3 TC supports two addressing modes + * -# Increment transfer + * -# FIFO transfer + * + * The SAM (Source Addressing Mode) and the DAM (Destination Addressing Mode) + * can be independently set to either of the two via the OPT register. + * + */ +typedef enum +{ + /** + * Increment (INCR) mode. Source addressing within an array increments. + * Source is not a FIFO. + */ + EDMA3_DRV_ADDR_MODE_INCR = 0, + + /** + * FIFO mode. Source addressing within an array wraps around upon + * reaching FIFO width. + */ + EDMA3_DRV_ADDR_MODE_FIFO = 1 + +} EDMA3_DRV_AddrMode; + + + +/** + * \brief EDMA Transfer Synchronization type. + * + * Two types of Synchronization of transfers are possible + * -# A Synchronized + * -# AB Syncronized + * - A Sync + * -# Each Array is submitted as one TR + * -# (BCNT*CCNT) number of sync events are needed to completely service + * a PaRAM set. (Where BCNT = Num of Arrays in a Frame; + * CCNT = Num of Frames in a Block) + * -# (S/D)CIDX = (Addr of First array in next frame) + * minus (Addr of Last array in present frame) + * (Where CIDX is the Inter-Frame index) + * + * - AB Sync + * -# Each Frame is submitted as one TR + * -# Only CCNT number of sync events are needed to completely service + * a PaRAM set + * -# (S/D)CIDX = (Addr of First array in next frame) + * minus (Addr of First array of present frame) + * + * \note ABC sync transfers can be achieved logically by chaining multiple + * AB sync transfers + * + */ +typedef enum +{ + /** + * A-synchronized. + * Each event triggers the transfer of a single array of ACNT bytes + */ + EDMA3_DRV_SYNC_A = 0 , + + /** + * AB-synchronized. + * Each event triggers the transfer of BCNT arrays of ACNT bytes + */ + EDMA3_DRV_SYNC_AB = 1 + +} EDMA3_DRV_SyncType; + + + +/** + * \brief True/False: PaRAM set is Static or not. A Static PaRAM set + * is updated or linked after TR is submitted. + */ +typedef enum +{ + /** + * PaRAM set is not Static. PaRAM set is updated or linked + * after TR is submitted. A value of 0 should be used for + * DMA channels and for nonfinal transfers in a linked list + * of QDMA transfers + */ + EDMA3_DRV_STATIC_DIS = 0, + + /** + * PaRAM set is Static. PaRAM set is not updated or linked + * after TR is submitted. A value of 1 should be used for + * isolated QDMA transfers or for the final transfer in a + * linked list of QDMA transfers. + */ + EDMA3_DRV_STATIC_EN = 1 +} EDMA3_DRV_StaticMode; + + +/** + * \brief EDMA3 FIFO width. + * + * The user can set the width of the FIFO using this enum. + * This is done via the OPT register. + * This is valid only if the EDMA3_DRV_ADDR_MODE_FIFO value is used for the + * enum EDMA3_DRV_AddrMode. + */ +typedef enum +{ + /** FIFO width is 8-bit. */ + EDMA3_DRV_W8BIT = 0, + + /** FIFO width is 16-bit. */ + EDMA3_DRV_W16BIT = 1, + + /** FIFO width is 32-bit. */ + EDMA3_DRV_W32BIT = 2, + + /** FIFO width is 64-bit. */ + EDMA3_DRV_W64BIT = 3, + + /** FIFO width is 128-bit. */ + EDMA3_DRV_W128BIT = 4, + + /** FIFO width is 256-bit. */ + EDMA3_DRV_W256BIT = 5 + +} EDMA3_DRV_FifoWidth; + + + + +/** + * \brief Transfer complete code mode. + * Indicates the point at which a transfer is considered completed for + * chaining and interrupt generation + */ +typedef enum +{ + /** A transfer is considered completed after transfer of data */ + EDMA3_DRV_TCCMODE_NORMAL = 0, + + /** + * A transfer is considered completed after the EDMA3CC submits a TR + * to the EDMA3TC. TC may still be transferring data when interrupt/chain + * is triggered. + */ + EDMA3_DRV_TCCMODE_EARLY = 1 +} EDMA3_DRV_TccMode; + + +/** + * \brief Transfer complete interrupt enable. + */ +typedef enum +{ + /** Transfer complete interrupt is disabled */ + EDMA3_DRV_TCINTEN_DIS = 0, + + /** + * Transfer complete interrupt is enabled. + * When enabled, the interrupt pending register (IPR/IPRH) bit is set on + * transfer completion (upon completion of the final TR in the PaRAM set). + * The bit (position) set in IPR or IPRH is the TCC value specified. In + * order to generate a completion interrupt to the CPU, the corresponding + * IER [TCC] / IERH [TCC] bit must be set to 1. + */ + EDMA3_DRV_TCINTEN_EN = 1 +} EDMA3_DRV_TcintEn; + + +/** + * \brief Intermediate Transfer complete interrupt enable. + */ +typedef enum +{ + /** Intermediate Transfer complete interrupt is disabled */ + EDMA3_DRV_ITCINTEN_DIS = 0, + + /** + * Intermediate transfer complete interrupt is enabled. + * When enabled, the interrupt pending register (IPR/IPRH) bit is set on + * every intermediate transfer completion (upon completion of every + * intermediate TR in the PaRAM set, except the final TR in the PaRAM set). + * The bit (position) set in IPR or IPRH is the TCC value specified. In + * order to generate a completion interrupt to the CPU, the corresponding + * IER [TCC] / IERH [TCC] bit must be set to 1. + */ + EDMA3_DRV_ITCINTEN_EN = 1 +} EDMA3_DRV_ItcintEn; + + +/** + * \brief Transfer complete chaining enable. + */ +typedef enum +{ + /** Transfer complete chaining is disabled */ + EDMA3_DRV_TCCHEN_DIS = 0, + + /** + * Transfer complete chaining is enabled. + * When enabled, the chained event register (CER/CERH) bit is set on final + * chained transfer completion (upon completion of the final / last TR in + * the PaRAM set). The bit (position) set in CER or CERH is the TCC value + * specified. + */ + EDMA3_DRV_TCCHEN_EN = 1 +} EDMA3_DRV_TcchEn; + + +/** + * \brief Intermediate Transfer complete chaining enable. + */ +typedef enum +{ + /** Intermediate Transfer complete chaining is disabled */ + EDMA3_DRV_ITCCHEN_DIS = 0, + + /** + * Intermediate transfer complete chaining is enabled. + * When enabled, the chained event register (CER/CERH) bit is set on every + * intermediate chained transfer completion (upon completion of every + * intermediate TR in the PaRAM set, except the final TR in the PaRAM set). + * The bit (position) set in CER or CERH is the TCC value specified. + */ + EDMA3_DRV_ITCCHEN_EN = 1 +} EDMA3_DRV_ItcchEn; + + +/** + * \brief Structure to be used to configure interrupt generation + * and chaining options. + */ +typedef struct +{ + /** Transfer complete chaining enable */ + EDMA3_DRV_TcchEn tcchEn; + + /** Intermediate Transfer complete chaining enable */ + EDMA3_DRV_ItcchEn itcchEn; + + /** Transfer complete interrupt enable */ + EDMA3_DRV_TcintEn tcintEn; + + /** Intermediate Transfer complete interrupt enable */ + EDMA3_DRV_ItcintEn itcintEn; +} EDMA3_DRV_ChainOptions; + + + +/** + * \brief Set a particular OPT field in the PaRAM set associated with the + * logical channel 'lCh'. + * + * This API can be used to set various optional parameters for an EDMA3 + * transfer. Like enable/disable completion interrupts, enable/disable chaining, + * setting the transfer mode (A/AB Sync), setting the FIFO width etc. + * + * \param hEdma [IN] Handle to the EDMA Driver Instance. + * \param lCh [IN] Logical Channel, bound to which + * PaRAM set OPT field needs to be set. + * \param optField [IN] The particular field of OPT Word + * that needs setting + * \param newOptFieldVal [IN] The new OPT field value + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant for unique lCh values. It is non- + * re-entrant for same lCh value. + */ +EDMA3_DRV_Result EDMA3_DRV_setOptField (EDMA3_DRV_Handle hEdma, + unsigned int lCh, + EDMA3_DRV_OptField optField, + unsigned int newOptFieldVal); + + +/** + * \brief Get a particular OPT field in the PaRAM set associated with the + * logical channel 'lCh'. + * + * This API can be used to read various optional parameters for an EDMA3 + * transfer. Like enable/disable completion interrupts, enable/disable chaining, + * setting the transfer mode (A/AB Sync), setting the FIFO width etc. + * + * \param hEdma [IN] Handle to the EDMA Driver Instance. + * \param lCh [IN] Logical Channel, bound to which + * PaRAM set OPT field is required. + * \param optField [IN] The particular field of OPT Word + * that is needed + * \param optFieldVal [IN/OUT] Value of the OPT field + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant. + */ +EDMA3_DRV_Result EDMA3_DRV_getOptField (EDMA3_DRV_Handle hEdma, + unsigned int lCh, + EDMA3_DRV_OptField optField, + unsigned int *optFieldVal); + + +/** + * \brief DMA source parameters setup + * + * It is used to program the source address, source side addressing mode + * (INCR or FIFO) and the FIFO width in case the addressing mode is FIFO. + * + * In FIFO Addressing mode, memory location must be 32 bytes aligned. + * + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param lCh [IN] Logical Channel for which the source parameters + * are to be configured + * \param srcAddr [IN] Source address + * \param addrMode [IN] Address mode [FIFO or Increment] + * \param fifoWidth [IN] Width of FIFO (Valid only if addrMode is FIFO) + * -# 0 - 8 bit + * -# 1 - 16 bit + * -# 2 - 32 bit + * -# 3 - 64 bit + * -# 4 - 128 bit + * -# 5 - 256 bit + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant for unique lCh values. It is non- + * re-entrant for same lCh value. + */ +EDMA3_DRV_Result EDMA3_DRV_setSrcParams ( EDMA3_DRV_Handle hEdma, + unsigned int lCh, + unsigned int srcAddr, + EDMA3_DRV_AddrMode addrMode, + EDMA3_DRV_FifoWidth fifoWidth); + + + +/** + * \brief DMA Destination parameters setup + * + * It is used to program the destination address, destination side addressing + * mode (INCR or FIFO) and the FIFO width in case the addressing mode is FIFO. + * + * In FIFO Addressing mode, memory location must be 32 bytes aligned. + * + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param lCh [IN] Logical Channel for which the destination + * parameters are to be configured + * \param destAddr [IN] Destination address + * \param addrMode [IN] Address mode [FIFO or Increment] + * \param fifoWidth [IN] Width of FIFO (Valid only if addrMode is FIFO) + * -# 0 - 8 bit + * -# 1 - 16 bit + * -# 2 - 32 bit + * -# 3 - 64 bit + * -# 4 - 128 bit + * -# 5 - 256 bit + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant for unique lCh values. It is non- + * re-entrant for same lCh value. + */ +EDMA3_DRV_Result EDMA3_DRV_setDestParams ( EDMA3_DRV_Handle hEdma, + unsigned int lCh, + unsigned int destAddr, + EDMA3_DRV_AddrMode addrMode, + EDMA3_DRV_FifoWidth fifoWidth ); + + + +/** + * \brief DMA source index setup + * + * It is used to program the source B index and source C index. + * + * SRCBIDX is a 16-bit signed value (2s complement) used for source address + * modification between each array in the 2nd dimension. Valid values for + * SRCBIDX are between -32768 and 32767. It provides a byte address offset + * from the beginning of the source array to the beginning of the next source + * array. It applies to both A-synchronized and AB-synchronized transfers. + * + * SRCCIDX is a 16-bit signed value (2s complement) used for source address + * modification in the 3rd dimension. Valid values for SRCCIDX are between + * -32768 and 32767. It provides a byte address offset from the beginning of + * the current array (pointed to by SRC address) to the beginning of the first + * source array in the next frame. It applies to both A-synchronized and + * AB-synchronized transfers. Note that when SRCCIDX is applied, the current + * array in an A-synchronized transfer is the last array in the frame, while + * the current array in an AB-synchronized transfer is the first array in the + * frame. + * + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param lCh [IN] Logical Channel for which source + * indices are to be configured + * \param srcBIdx [IN] Source B index + * \param srcCIdx [IN] Source C index + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant for unique lCh values. It is non- + * re-entrant for same lCh value. + */ +EDMA3_DRV_Result EDMA3_DRV_setSrcIndex ( EDMA3_DRV_Handle hEdma, + unsigned int lCh, + int srcBIdx, + int srcCIdx ); + + + +/** + * \brief DMA destination index setup + * + * It is used to program the destination B index and destination C index. + * + * DSTBIDX is a 16-bit signed value (2s complement) used for destination + * address modification between each array in the 2nd dimension. Valid values + * for DSTBIDX are between -32768 and 32767. It provides a byte address offset + * from the beginning of the destination array to the beginning of the next + * destination array within the current frame. It applies to both + * A-synchronized and AB-synchronized transfers. + * + * DSTCIDX is a 16-bit signed value (2s complement) used for destination address + * modification in the 3rd dimension. Valid values are between -32768 and 32767. + * It provides a byte address offset from the beginning of the current array + * (pointed to by DST address) to the beginning of the first destination array + * TR in the next frame. It applies to both A-synchronized and AB-synchronized + * transfers. Note that when DSTCIDX is applied, the current array in an + * A-synchronized transfer is the last array in the frame, while the current + * array in a AB-synchronized transfer is the first array in the frame + * + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param lCh [IN] Logical Channel for which dest + * indices are to be configured + * \param destBIdx [IN] Destination B index + * \param destCIdx [IN] Destination C index + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant for unique lCh values. It is non- + * re-entrant for same lCh value. + */ +EDMA3_DRV_Result EDMA3_DRV_setDestIndex (EDMA3_DRV_Handle hEdma, + unsigned int lCh, + int destBIdx, + int destCIdx); + + +/** + * \brief DMA transfer parameters setup + * + * It is used to specify the various counts (ACNT, BCNT and CCNT), B count + * reload and the synchronization type + * + * ACNT represents the number of bytes within the 1st dimension of a transfer. + * ACNT is a 16-bit unsigned value with valid values between 0 and 65535. + * Therefore, the maximum number of bytes in an array is 65535 bytes (64K - 1 + * bytes). ACNT must be greater than or equal to 1 for a TR to be submitted to + * EDMA3 Transfer Controller. + * An ACNT equal to 0 is considered either a null or dummy transfer. A dummy or + * null transfer generates a completion code depending on the settings of the + * completion bit fields in OPT. + + * BCNT is a 16-bit unsigned value that specifies the number of arrays of length + * ACNT. For normal operation, valid values for BCNT are between 1 and 65535. + * Therefore, the maximum number of arrays in a frame is 65535 (64K - 1 arrays). + * A BCNT equal to 0 is considered either a null or dummy transfer. A dummy or + * null transfer generates a completion code depending on the settings of the + * completion bit fields in OPT. + * + * CCNT is a 16-bit unsigned value that specifies the number of frames in a + * block. Valid values for CCNT are between 1 and 65535. Therefore, the maximum + * number of frames in a block is 65535 (64K - 1 frames). A CCNT equal to 0 is + * considered either a null or dummy transfer. A dummy or null transfer + * generates a completion code depending on the settings of the completion bit + * fields in OPT. A CCNT value of 0 is considered either a null or dummy + * transfer. + * + * BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the + * last array in the 2nd dimension is transferred. This field is only used for + * A-synchronized transfers. In this case, the EDMA3CC decrements the BCNT + * value by 1 on each TR submission. When BCNT (conceptually) reaches 0, the + * EDMA3CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT + * value. + * For AB-synchronized transfers, the EDMA3CC submits the BCNT in the TR and the + * EDMA3TC decrements BCNT appropriately. For AB-synchronized transfers, + * BCNTRLD is not used. + + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param lCh [IN] Logical Channel for which transfer + * parameters are to be configured + * \param aCnt [IN] Count for 1st Dimension. + * \param bCnt [IN] Count for 2nd Dimension. + * \param cCnt [IN] Count for 3rd Dimension. + * \param bCntReload [IN] Reload value for bCnt. + * \param syncType [IN] Transfer synchronization dimension + * 0: A-synchronized. Each event triggers + * the transfer of a single array of + * ACNT bytes. + * 1: AB-synchronized. Each event triggers + * the transfer of BCNT arrays of ACNT + * bytes. + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant for unique lCh values. It is non- + * re-entrant for same lCh value. + */ +EDMA3_DRV_Result EDMA3_DRV_setTransferParams ( + EDMA3_DRV_Handle hEdma, + unsigned int lCh, + unsigned int aCnt, + unsigned int bCnt, + unsigned int cCnt, + unsigned int bCntReload, + EDMA3_DRV_SyncType syncType); + + + +/** + * \brief Chain the two specified channels. + * + * This API is used to chain two previously allocated logical (DMA/QDMA) + * channels. + * + * Chaining is different from Linking. The EDMA3 link feature reloads the + * current channel parameter set with the linked parameter set. The EDMA3 + * chaining feature does not modify or update any channel parameter set; + * it provides a synchronization event to the chained channel. + * + * \param hEdma [IN] Handle to the EDMA Driver Instance. + * + * \param lCh1 [IN] Channel to which particular channel + * will be chained. + * \param lCh2 [IN] Channel which needs to be chained to + * the first channel. + * \param chainOptions [IN] Options such as intermediate interrupts + * are required or not, intermediate/final + * chaining is enabled or not etc. + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant for unique lCh1 & lCh2 values. It is + * non-re-entrant for same lCh1 & lCh2 values. + */ +EDMA3_DRV_Result EDMA3_DRV_chainChannel (EDMA3_DRV_Handle hEdma, + unsigned int lCh1, + unsigned int lCh2, + const EDMA3_DRV_ChainOptions *chainOptions); + + +/** + * \brief Unchain the two channels. + * + * \param hEdma [IN] Handle to the EDMA Driver Instance. + * \param lCh [IN] Channel whose chaining with the other + * channel has to be removed. + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant for unique lCh values. It is non- + * re-entrant for same lCh value. + */ +EDMA3_DRV_Result EDMA3_DRV_unchainChannel (EDMA3_DRV_Handle hEdma, + unsigned int lCh); + + +/** + * \brief EDMA Trigger Mode Selection + * + * Use this enum to select the EDMA trigger mode while enabling + * the EDMA transfer + */ +typedef enum +{ + /** + * Set the Trigger mode to Manual . + * The CPU manually triggers a transfer by writing a 1 to the + * corresponding bit in the event set register (ESR/ESRH). + */ + EDMA3_DRV_TRIG_MODE_MANUAL = 0, + + /** + * Set the Trigger mode to QDMA. + * A QDMA transfer is triggered when a CPU (or other EDMA3 + * programmer) writes to the trigger word of the + * QDMA channel parameter set (autotriggered) or when the + * EDMA3CC performs a link update on a PaRAM + * set that has been mapped to a QDMA channel (link triggered). + */ + EDMA3_DRV_TRIG_MODE_QDMA = 1, + + /** + * Set the Trigger mode to Event. + * Allows for a peripheral, system, or externally-generated + * event to trigger a transfer request. + */ + EDMA3_DRV_TRIG_MODE_EVENT = 2, + + /** Used to specify the trigger mode NONE */ + EDMA3_DRV_TRIG_MODE_NONE = 3 +} EDMA3_DRV_TrigMode; + + +/** + * \brief Start EDMA transfer on the specified channel. + * + * There are multiple ways to trigger an EDMA3 transfer. The triggering mode + * option allows choosing from the available triggering modes: Event, + * Manual or QDMA. + * + * In event triggered, a peripheral or an externally generated event triggers + * the transfer. This API clears the Event and Event Miss Register and then + * enables the DMA channel by writing to the EESR. + * + * In manual triggered mode, CPU manually triggers a transfer by writing a 1 + * in the Event Set Register (ESR/ESRH). This API writes to the ESR/ESRH to + * start the transfer. + * + * In QDMA triggered mode, a QDMA transfer is triggered when a CPU (or other + * EDMA3 programmer) writes to the trigger word of the QDMA channel PaRAM set + * (auto-triggered) or when the EDMA3CC performs a link update on a PaRAM set + * that has been mapped to a QDMA channel (link triggered). This API enables + * the QDMA channel by writing to the QEESR register. + * + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param lCh [IN] Channel on which transfer has to be started + * \param trigMode [IN] Mode of triggering start of transfer (Manual, + * QDMA or Event) + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant for unique lCh values. It is non- + * re-entrant for same lCh value. + */ +EDMA3_DRV_Result EDMA3_DRV_enableTransfer (EDMA3_DRV_Handle hEdma, + unsigned int lCh, + EDMA3_DRV_TrigMode trigMode); + + +/** + * \brief Disable DMA transfer on the specified channel + * + * There are multiple ways by which an EDMA3 transfer could be triggered. + * The triggering mode option allows choosing from the available triggering + * modes: Event, Manual or QDMA. + * + * To disable a channel which was previously triggered in manual mode, + * this API clears the Secondary Event Register and Event Miss Register, + * if set, for the specific DMA channel. + * + * To disable a channel which was previously triggered in QDMA mode, this + * API clears the QDMA Even Enable Register, for the specific QDMA channel. + * + * To disable a channel which was previously triggered in event mode, this API + * clears the Event Enable Register, Event Register, Secondary Event Register + * and Event Miss Register, if set, for the specific DMA channel. + + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param lCh [IN] Channel on which transfer has to be stopped + * \param trigMode [IN] Mode of triggering start of transfer + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant for unique lCh values. It is non- + * re-entrant for same lCh value. + */ +EDMA3_DRV_Result EDMA3_DRV_disableTransfer (EDMA3_DRV_Handle hEdma, + unsigned int lCh, + EDMA3_DRV_TrigMode trigMode); + +/* @} Edma3DrvTransferSetupType */ + + + +/** + * \defgroup Edma3DrvTransferSetupOpt EDMA3 Driver Optional Setup for EDMA + * Transfer. + * + * The Optional EDMA transfer related Interface of the EDMA3 Driver + * + * @{ + */ + +/** + * \brief PaRAM Set Entry type + * + * Use this enum to set or get any of the + * 8 DWords(unsigned int) within a Parameter RAM set + */ +typedef enum +{ + /** + * The OPT field (Offset Address 0x0 Bytes) + */ + EDMA3_DRV_PARAM_ENTRY_OPT = 0, + + /** + * The SRC field (Offset Address 0x4 Bytes) + */ + EDMA3_DRV_PARAM_ENTRY_SRC = 1, + + /** + * The (ACNT+BCNT) field (Offset Address 0x8 Bytes) + */ + EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT = 2, + + /** + * The DST field (Offset Address 0xC Bytes) + */ + EDMA3_DRV_PARAM_ENTRY_DST = 3, + + /** + * The (SRCBIDX+DSTBIDX) field (Offset Address 0x10 Bytes) + */ + EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX = 4, + + /** + * The (LINK+BCNTRLD) field (Offset Address 0x14 Bytes) + */ + EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD = 5, + + /** + * The (SRCCIDX+DSTCIDX) field (Offset Address 0x18 Bytes) + */ + EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX = 6, + + /** + * The (CCNT+RSVD) field (Offset Address 0x1C Bytes) + */ + EDMA3_DRV_PARAM_ENTRY_CCNT = 7 + +} EDMA3_DRV_PaRAMEntry; + + + +/** + * \brief PaRAM Set Field type + * + * Use this enum to set or get any of the PaRAM set fields + */ +typedef enum +{ + /** OPT field of PaRAM Set */ + EDMA3_DRV_PARAM_FIELD_OPT = 0, + + /** + * \brief Starting byte address of Source + * For FIFO mode, srcAddr must be a 256-bit aligned address. + */ + EDMA3_DRV_PARAM_FIELD_SRCADDR = 1, + + /** + * \brief Number of bytes in each Array (ACNT) + */ + EDMA3_DRV_PARAM_FIELD_ACNT = 2, + + /** + * \brief Number of Arrays in each Frame (BCNT) + */ + EDMA3_DRV_PARAM_FIELD_BCNT = 3, + + /** + * \brief Starting byte address of destination + * For FIFO mode, destAddr must be a 256-bit aligned address. + */ + EDMA3_DRV_PARAM_FIELD_DESTADDR = 4, + + /** + * \brief Index between consec. arrays of a Source Frame (SRCBIDX) + * If SAM is set to 1 (via channelOptions) then srcInterArrIndex should + * be an even multiple of 32 bytes. + */ + EDMA3_DRV_PARAM_FIELD_SRCBIDX = 5, + + /** + * \brief Index between consec. arrays of a Destination Frame (DSTBIDX) + * If DAM is set to 1 (via channelOptions) then destInterArrIndex should + * be an even multiple of 32 bytes + */ + EDMA3_DRV_PARAM_FIELD_DESTBIDX = 6, + + /** + * \brief Address for linking (AutoReloading of a PaRAM Set) + * This must point to a valid aligned 32-byte PaRAM set + * A value of 0xFFFF means no linking + * Linking is especially useful for use with ping-pong buffers and + * circular buffers + */ + EDMA3_DRV_PARAM_FIELD_LINKADDR = 7, + + /** + * \brief Reload value of the numArrInFrame (BCNT) + * Relevant only for A-sync transfers + */ + EDMA3_DRV_PARAM_FIELD_BCNTRELOAD = 8, + + /** + * \brief Index between consecutive frames of a Source Block (SRCCIDX) + */ + EDMA3_DRV_PARAM_FIELD_SRCCIDX = 9, + + /** + * \brief Index between consecutive frames of a Dest Block (DSTCIDX) + */ + EDMA3_DRV_PARAM_FIELD_DESTCIDX = 10, + + /** + * \brief Number of Frames in a block (CCNT) + */ + EDMA3_DRV_PARAM_FIELD_CCNT = 11 + +} EDMA3_DRV_PaRAMField; + + + +/** + * \brief EDMA3 PaRAM Set + * + * This is a mapping of the EDMA3 PaRAM set provided to the user + * for ease of modification of the individual PaRAM words. + */ +typedef struct { + /** OPT field of PaRAM Set */ + volatile unsigned int OPT; + + /** + * \brief Starting byte address of Source + * For FIFO mode, srcAddr must be a 256-bit aligned address. + */ + volatile unsigned int SRC; + + /** + * Number of bytes in each Array (ACNT) (16 bits) and + * Number of Arrays in each Frame (BCNT) (16 bits). + */ + volatile unsigned int A_B_CNT; + + /** + * \brief Starting byte address of destination + * For FIFO mode, destAddr must be a 256-bit aligned address. + * i.e. 5 LSBs should be 0. + */ + volatile unsigned int DST; + + /** + * Index between consec. arrays of a Source Frame (SRCBIDX) (16 bits) and + * Index between consec. arrays of a Destination Frame (DSTBIDX) (16 bits). + * + * If SAM is set to 1 (via channelOptions) then srcInterArrIndex should + * be an even multiple of 32 bytes. + * + * If DAM is set to 1 (via channelOptions) then destInterArrIndex should + * be an even multiple of 32 bytes + */ + volatile unsigned int SRC_DST_BIDX; + + /** + * \brief Address for linking (AutoReloading of a PaRAM Set) (16 bits) + * and Reload value of the numArrInFrame (BCNT) (16 bits). + * + * Link field must point to a valid aligned 32-byte PaRAM set + * A value of 0xFFFF means no linking. + * + * B count reload field is relevant only for A-sync transfers. + */ + volatile unsigned int LINK_BCNTRLD; + + /** + * \brief Index between consecutive frames of a Source Block (SRCCIDX) + * (16 bits) and Index between consecutive frames of a Dest Block + * (DSTCIDX) (16 bits). + */ + volatile unsigned int SRC_DST_CIDX; + + /** + * \brief Number of Frames in a block (CCNT) (16 bits). + */ + volatile unsigned int CCNT; + +} EDMA3_DRV_ParamentryRegs; + + + +/** + * \brief EDMA3 Parameter RAM Set in User Configurable format + * + * This is a mapping of the EDMA3 PaRAM set provided to the user + * for ease of modification of the individual fields + */ +typedef struct { + /** OPT field of PaRAM Set */ + volatile unsigned int opt; + + /** + * \brief Starting byte address of Source + * For FIFO mode, srcAddr must be a 256-bit aligned address. + */ + volatile unsigned int srcAddr; + + /** + * \brief Number of bytes in each Array (ACNT) + */ + volatile unsigned short aCnt; + + /** + * \brief Number of Arrays in each Frame (BCNT) + */ + volatile unsigned short bCnt; + + /** + * \brief Starting byte address of destination + * For FIFO mode, destAddr must be a 256-bit aligned address. + * i.e. 5 LSBs should be 0. + */ + volatile unsigned int destAddr; + + /** + * \brief Index between consec. arrays of a Source Frame (SRCBIDX) + * If SAM is set to 1 (via channelOptions) then srcInterArrIndex should + * be an even multiple of 32 bytes. + */ + volatile short srcBIdx; + + /** + * \brief Index between consec. arrays of a Destination Frame (DSTBIDX) + * If DAM is set to 1 (via channelOptions) then destInterArrIndex should + * be an even multiple of 32 bytes + */ + volatile short destBIdx; + + /** + * \brief Address for linking (AutoReloading of a PaRAM Set) + * This must point to a valid aligned 32-byte PaRAM set + * A value of 0xFFFF means no linking + * Linking is especially useful for use with ping-pong buffers and + * circular buffers + */ + volatile unsigned short linkAddr; + + /** + * \brief Reload value of the numArrInFrame (BCNT) + * Relevant only for A-sync transfers + */ + volatile unsigned short bCntReload; + + /** + * \brief Index between consecutive frames of a Source Block (SRCCIDX) + */ + volatile short srcCIdx; + + /** + * \brief Index between consecutive frames of a Dest Block (DSTCIDX) + */ + volatile short destCIdx; + + /** + * \brief Number of Frames in a block (CCNT) + */ + volatile unsigned short cCnt; + +} EDMA3_DRV_PaRAMRegs; + + +/** + * \brief Event queue priorities setup + * + * It allows to change the priority of the individual queues and the + * priority of the transfer request (TR) associated with the + * events queued in the queue. + */ +typedef struct +{ + /** + * \brief Event Queue Priorities + */ + unsigned int evtQPri[EDMA3_MAX_EVT_QUE]; +}EDMA3_DRV_EvtQuePriority; + + + +/** + * \brief Assign a Trigger Word to the specified QDMA channel + * + * This API sets the Trigger word for the specific QDMA channel in the QCHMAP + * Register. Default QDMA trigger word is CCNT. + * + * \param hEdma [IN] Handle to the EDMA Instance object + * \param lCh [IN] QDMA Channel which needs to be assigned + * the Trigger Word + * \param trigWord [IN] The Trigger Word for the QDMA channel. + * Trigger Word is the word in the PaRAM + * Register Set which, when written to by CPU, + * will start the QDMA transfer automatically. + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant for unique lCh values. It is non- + * re-entrant for same lCh value. + */ +EDMA3_DRV_Result EDMA3_DRV_setQdmaTrigWord (EDMA3_DRV_Handle hEdma, + unsigned int lCh, + EDMA3_RM_QdmaTrigWord trigWord); + + +/** + * \brief Copy the user specified PaRAM Set onto the PaRAM Set + * associated with the logical channel (DMA/QDMA/Link). + * + * This API takes a PaRAM Set as input and copies it onto the actual PaRAM Set + * associated with the logical channel. OPT field of the PaRAM Set is written + * first and the CCNT field is written last. + * + * Caution: It should be used carefully when programming the QDMA channels whose + * trigger words are not CCNT field. + * + * \param hEdma [IN] Handle to the EDMA Instance object + * \param lCh [IN] Logical Channel for which new PaRAM set is + * specified + * \param newPaRAM [IN] Parameter RAM set to be copied onto existing PaRAM + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant for unique lCh values. It is non- + * re-entrant for same lCh value. + */ +EDMA3_DRV_Result EDMA3_DRV_setPaRAM ( EDMA3_DRV_Handle hEdma, + unsigned int lCh, + const EDMA3_DRV_PaRAMRegs *newPaRAM); + + +/** + * \brief Retrieve existing PaRAM set associated with specified logical + * channel (DMA/QDMA/Link). + * + * \param hEdma [IN] Handle to the EDMA Instance object + * \param lCh [IN] Logical Channel whose PaRAM set is + * requested + * \param currPaRAM [IN/OUT] User gets the existing PaRAM here + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant. + */ +EDMA3_DRV_Result EDMA3_DRV_getPaRAM (EDMA3_DRV_Handle hEdma, + unsigned int lCh, + EDMA3_DRV_PaRAMRegs *currPaRAM); + + + +/** + * \brief Set a particular PaRAM set entry of the specified PaRAM set + * + * + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param lCh [IN] Logical Channel bound to the Parameter RAM set + * whose specified field needs to be set + * \param paRAMEntry [IN] Specify the PaRAM set entry which needs + * to be set + * \param newPaRAMEntryVal [IN] The new field setting + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This API should be used while setting the PaRAM set entry + * for QDMA channels. If EDMA3_DRV_setPaRAMField () used, + * it will trigger the QDMA channel before complete + * PaRAM set entry is written. For DMA channels, no such + * constraint is there. + * + * This function is re-entrant for unique lCh values. It is non- + * re-entrant for same lCh value. + */ +EDMA3_DRV_Result EDMA3_DRV_setPaRAMEntry (EDMA3_DRV_Handle hEdma, + unsigned int lCh, + EDMA3_DRV_PaRAMEntry paRAMEntry, + unsigned int newPaRAMEntryVal); + + +/** + * \brief Get a particular PaRAM set entry of the specified PaRAM set + * + * + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param lCh [IN] Logical Channel bound to the Parameter RAM set + * whose specified field value is needed + * \param paRAMEntry [IN] Specify the PaRAM set entry which needs + * to be obtained + * \param paRAMEntryVal [IN/OUT] The value of the field is returned here + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant. + */ +EDMA3_DRV_Result EDMA3_DRV_getPaRAMEntry (EDMA3_DRV_Handle hEdma, + unsigned int lCh, + EDMA3_DRV_PaRAMEntry paRAMEntry, + unsigned int *paRAMEntryVal); + + +/** + * \brief Set a particular PaRAM set field of the specified PaRAM set + * + * + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param lCh [IN] Logical Channel bound to the PaRAM set + * whose specified field needs to be set + * \param paRAMField [IN] Specify the PaRAM set field which needs + * to be set + * \param newPaRAMFieldVal [IN] The new field setting + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This API CANNOT be used while setting the PaRAM set + * field for QDMA channels. It can trigger the QDMA channel before + * complete PaRAM set ENTRY (4-bytes field) is written (for eg, as + * soon one sets the ACNT field for QDMA channel, transfer is started, + * before one modifies the BCNT field). For DMA channels, no such + * constraint is there. + * + * This function is re-entrant for unique lCh values. It is non- + * re-entrant for same lCh value. + */ +EDMA3_DRV_Result EDMA3_DRV_setPaRAMField (EDMA3_DRV_Handle hEdma, + unsigned int lCh, + EDMA3_DRV_PaRAMField paRAMField, + unsigned int newPaRAMFieldVal); + + +/** + * \brief Get a particular PaRAM set field of the specified PaRAM set + * + * + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param lCh [IN] Logical Channel bound to the PaRAM set + * whose specified field value is needed + * \param paRAMField [IN] Specify the PaRAM set field which needs + * to be obtained + * \param currPaRAMFieldVal [IN/OUT] The value of the field is returned here + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant. + */ +EDMA3_DRV_Result EDMA3_DRV_getPaRAMField (EDMA3_DRV_Handle hEdma, + unsigned int lCh, + EDMA3_DRV_PaRAMField paRAMField, + unsigned int *currPaRAMFieldVal); + + +/** + * \brief Sets EDMA TC priority + * + * User can program the priority of the Event Queues at a system-wide level. + * This means that the user can set the priority of an IO initiated by either + * of the TCs (Transfer Ctrllers) relative to IO initiated by the other bus + * masters on the device (ARM, DSP, USB, etc) + * + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param evtQPriObj [IN] Priority of the Event Queues + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function disables the global interrupts while modifying + * the global CC Registers, to make it re-entrant. + */ +EDMA3_DRV_Result EDMA3_DRV_setEvtQPriority (EDMA3_DRV_Handle hEdma, + const EDMA3_DRV_EvtQuePriority *evtQPriObj); + + +/** + * \brief Associate Channel to Event Queue + * + * + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param channelId [IN] Logical Channel to which the Event + * Queue is to be mapped + * \param eventQ [IN] The Event Queue which is to be mapped + * to the DMA channel + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note There should not be any data transfer going on + * while setting the mapping. Results could be unpredictable. + * + * This function disables the global interrupts while modifying + * the global CC Registers, to make it re-entrant. + */ +EDMA3_DRV_Result EDMA3_DRV_mapChToEvtQ (EDMA3_DRV_Handle hEdma, + unsigned int channelId, + EDMA3_RM_EventQueue eventQ); + + +/** + * \brief Get the Event Queue mapped to the specified DMA/QDMA channel. + * + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param channelId [IN] Logical Channel whose associated + * Event Queue is needed + * \param mappedEvtQ [IN/OUT] The Event Queue which is mapped + * to the DMA/QDMA channel + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant. + */ +EDMA3_DRV_Result EDMA3_DRV_getMapChToEvtQ (EDMA3_DRV_Handle hEdma, + unsigned int channelId, + unsigned int *mappedEvtQ); + + + +/** + * \brief Set the Channel Controller (CC) Register value + * + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param regOffset [IN] CC Register offset whose value needs to be set + * \param newRegValue [IN] New CC Register Value + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is non re-entrant for users using the same + * EDMA handle i.e. working on the same shadow region. + * Before modifying a register, it tries to acquire a semaphore + * (Driver instance specific), to protect simultaneous + * modification of the same register by two different users. + * After the successful change, it releases the semaphore. + * For users working on different shadow regions, thus different + * EDMA handles, this function is re-entrant. + */ +EDMA3_DRV_Result EDMA3_DRV_setCCRegister (EDMA3_DRV_Handle hEdma, + unsigned int regOffset, + unsigned int newRegValue); + + +/** + * \brief Get the Channel Controller (CC) Register value + * + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param regOffset [IN] CC Register offset whose value is needed + * \param regValue [IN/OUT] CC Register Value + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant. + */ +EDMA3_DRV_Result EDMA3_DRV_getCCRegister (EDMA3_DRV_Handle hEdma, + unsigned int regOffset, + unsigned int *regValue); + + + +/** + * \brief Wait for a transfer completion interrupt to occur and clear it. + * + * This is a blocking function that returns when the IPR/IPRH bit corresponding + * to the tccNo specified, is SET. It clears the corresponding bit while + * returning also. + * + * This function waits for the specific bit indefinitely in a tight loop, with + * out any delay in between. USE IT CAUTIOUSLY. + * + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param tccNo [IN] TCC, specific to which the function + * waits on a IPR/IPRH bit. + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant for different tccNo. + */ +EDMA3_DRV_Result EDMA3_DRV_waitAndClearTcc (EDMA3_DRV_Handle hEdma, + unsigned int tccNo); + + + + +/** + * \brief Returns the status of a previously initiated transfer. + * + * This is a non-blocking function that returns the status of a previously + * initiated transfer, based on the IPR/IPRH bit. This bit corresponds to + * the tccNo specified by the user. It clears the corresponding bit, if SET, + * while returning also. + * + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param tccNo [IN] TCC, specific to which the function + * checks the status of the IPR/IPRH bit. + * \param tccStatus [IN/OUT] Status of the transfer is returned here. + * Returns "TRUE" if the transfer has + * completed (IPR/IPRH bit SET), + * "FALSE" if the transfer has not completed + * successfully (IPR/IPRH bit NOT SET). + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant for different tccNo. + */ +EDMA3_DRV_Result EDMA3_DRV_checkAndClearTcc (EDMA3_DRV_Handle hEdma, + unsigned int tccNo, + unsigned short *tccStatus); + + + +/** + * \brief Get the PaRAM Set Physical Address associated with a logical channel + * + * This function returns the PaRAM Set Phy Address (unsigned 32 bits). + * The returned address could be used by the advanced users to program the + * PaRAM Set directly without using any APIs. + * + * Least significant 16 bits of this address could be used to program + * the LINK field in the PaRAM Set. + * Users which program the LINK field directly SHOULD use this API + * to get the associated PaRAM Set address with the LINK channel. + * + * + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param lCh [IN] Logical Channel for which the PaRAM set + * physical address is required + * \param paramPhyAddr [IN/OUT] PaRAM Set physical address is returned + * here. + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant. + */ +EDMA3_DRV_Result EDMA3_DRV_getPaRAMPhyAddr(EDMA3_DRV_Handle hEdma, + unsigned int lCh, + unsigned int *paramPhyAddr); + + +/**\enum EDMA3_DRV_IoctlCmd + * \brief EDMA3 Driver IOCTL commands + */ +typedef enum +{ + /* Min IOCTL */ + EDMA3_DRV_IOCTL_MIN_IOCTL = 0, + + /** + * PaRAM Sets will be cleared OR will not be cleared + * during allocation, depending upon this option. + * + * For e.g., + * To clear the PaRAM Sets during allocation, + * cmdArg = (void *)1; + * + * To NOT clear the PaRAM Sets during allocation, + * cmdArg = (void *)0; + * + * For all other values, it will return error. + * + * By default, PaRAM Sets will be cleared during allocation. + * Note: Since this enum can change the behavior how the resources are + * initialized during their allocation, user is adviced to not use this + * command while allocating the resources. User should first change the + * behavior of resources' initialization and then should use start + * allocating resources. + */ + EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION, + + /** + * To check whether PaRAM Sets will be cleared or not + * during allocation. + * If the value read is '1', it means that PaRAM Sets are getting cleared + * during allocation. + * If the value read is '0', it means that PaRAM Sets are NOT getting cleared + * during allocation. + * + * For e.g., + * unsigned short isParamClearingDone; + * cmdArg = ¶mClearingRequired; + */ + EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION, + + /* Max IOCTLs */ + EDMA3_DRV_IOCTL_MAX_IOCTL +} EDMA3_DRV_IoctlCmd; + + +/** + * \brief EDMA3 Driver IOCTL + * + * This function provides IOCTL functionality for EDMA3 Driver. + * + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param cmd [IN] IOCTL command to be performed + * \param cmdArg [IN/OUT] IOCTL command argument (if any) + * \param param [IN/OUT] Device/Cmd specific argument + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note For 'EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION', this function is re-entrant. + * For 'EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION', this function is re-entrant for + * different EDMA3 Driver Instances (handles). + */ +EDMA3_DRV_Result EDMA3_DRV_Ioctl( + EDMA3_DRV_Handle hEdma, + EDMA3_DRV_IoctlCmd cmd, + void *cmdArg, + void *param + ); + + +/** + * \brief Return the previously opened EDMA3 Driver Instance handle + * + * This API is used to return the previously opened EDMA3 Driver's + * Instance Handle (region specific), which could be used to call other + * EDMA3 Driver APIs. Since EDMA3 Driver does not allow multiple instances, + * for a single shadow region, this API is provided. This API is meant + * for users who DO NOT want to / could not open a new Driver Instance and + * hence re-use the existing Driver Instance to allocate EDMA3 resources + * and use various other EDMA3 Driver APIs. + * + * In case the Driver Instance is not yet opened, NULL is returned as the + * function return value whereas EDMA3_DRV_E_INST_NOT_OPENED is returned + * in the errorCode. + * + * \param phyCtrllerInstId [IN] EDMA3 Controller Instance Id (Hardware + * instance id, starting from 0). + * \param regionId [IN] Shadow Region id for which the previously + * opened driver's instance handle is + * required. + * \param errorCode [OUT] Error code while returning Driver Instance + * Handle. + * + * \return EDMA3_DRV_Handle : If successful, this API will return the + * driver's instance handle. + * + * \note 1) This API returns the previously opened EDMA3 Driver's Instance + * handle. The instance, if exists, could have been opened by some other + * user (most probably) or may be by the same user calling this API. If + * it was opened by some other user, then that user can very well close + * this instance anytime, without even knowing that the same instance + * handle is being used by other users as well. In that case, the + * handle becomes INVALID and user has to open a valid driver + * instance for his/her use. + * + * 2) This function is re-entrant. + */ +EDMA3_DRV_Handle EDMA3_DRV_getInstHandle(unsigned int phyCtrllerInstId, + EDMA3_RM_RegionId regionId, + EDMA3_DRV_Result *errorCode); + + + +/* @} Edma3DrvTransferSetupOpt */ + + +/* @} Edma3DrvMain */ + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif /* _EDMA3_DRV_H_ */ diff --git a/packages/ti/sdo/edma3/drv/package.bld b/packages/ti/sdo/edma3/drv/package.bld new file mode 100644 index 0000000..29e7379 --- /dev/null +++ b/packages/ti/sdo/edma3/drv/package.bld @@ -0,0 +1,48 @@ +/* +* Copyright 2006 by Texas Instruments Incorporated. +* +* All rights reserved. Property of Texas Instruments Incorporated. +* Restricted rights to use, duplicate or disclose this code are +* granted through contract. +* +*/ + +var Build = xdc.useModule('xdc.bld.BuildEnvironment'); +var Pkg = xdc.useModule('xdc.bld.PackageContents'); + +var objList = [ + "src/edma3_drv_init.c", + "src/edma3_drv_basic.c", + "src/edma3_drv_adv.c", +]; + +for each (var targ in Build.targets) +{ + Pkg.addLibrary("lib/Debug/" + Pkg.name, targ, + { defs:"", profile: "debug"} + ).addObjects(objList); + Pkg.addLibrary("lib/Release/" + Pkg.name, targ, + { defs:"", profile: "release"} + ).addObjects(objList); +} + + +Pkg.otherFiles=[ + 'docs', + 'lib/Debug/ti.sdo.edma3.drv.a674', + 'lib/Release/ti.sdo.edma3.drv.a674', + 'src', + 'edma3_drv.h', + 'package.bld', + 'package.xs', +]; + + + + + + + + + + diff --git a/packages/ti/sdo/edma3/drv/package.xdc b/packages/ti/sdo/edma3/drv/package.xdc new file mode 100644 index 0000000..adc1bb5 --- /dev/null +++ b/packages/ti/sdo/edma3/drv/package.xdc @@ -0,0 +1,17 @@ +/* + * ======== package.xdc ======== + * + */ + +/* + * List the packages to be included in the bundle. The 'requires' + * statements must come before the 'package' statement. + */ +requires ti.sdo.edma3.rm; + + +/*! + * ======== ti.sdo.edma3.drv ======== + */ +package ti.sdo.edma3.drv [2, 00, 00] { +} diff --git a/packages/ti/sdo/edma3/drv/package.xs b/packages/ti/sdo/edma3/drv/package.xs new file mode 100644 index 0000000..c4d165b --- /dev/null +++ b/packages/ti/sdo/edma3/drv/package.xs @@ -0,0 +1,33 @@ +/* + * ======== package.xs ======== + * + */ + +/* + * ======== getLibs ======== + */ +function getLibs(prog) +{ + print ("Inside EDMA3 Drv getLibs"); + + /* Prepare variables to form the library path within this package */ + var name = "ti.sdo.edma3.drv.a674"; + var lib = "lib/"; + + switch (this.profile) { + case 'debug': + /* enable debug build for debug profile only */ + lib = lib + "Debug/" + name; + break; + + default: + /* release profile for everything else */ + lib = lib + "Release/" + name; + } + + print(" will link with " + this.$name + ":" + lib); + + /* return the library name */ + return (lib); +} + diff --git a/packages/ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h b/packages/ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h new file mode 100644 index 0000000..3ed2259 --- /dev/null +++ b/packages/ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h @@ -0,0 +1,185 @@ +/******************************************************************************* +**+--------------------------------------------------------------------------+** +**| **** |** +**| **** |** +**| ******o*** |** +**| ********_///_**** |** +**| ***** /_//_/ **** |** +**| ** ** (__/ **** |** +**| ********* |** +**| **** |** +**| *** |** +**| |** +**| Copyright (c) 1998-2006 Texas Instruments Incorporated |** +**| ALL RIGHTS RESERVED |** +**| |** +**| Permission is hereby granted to licensees of Texas Instruments |** +**| Incorporated (TI) products to use this computer program for the sole |** +**| purpose of implementing a licensee product based on TI products. |** +**| No other rights to reproduce, use, or disseminate this computer |** +**| program, whether in part or in whole, are granted. |** +**| |** +**| TI makes no representation or warranties with respect to the |** +**| performance of this computer program, and specifically disclaims |** +**| any responsibility for any damages, special or consequential, |** +**| connected with the use of this program. |** +**| |** +**+--------------------------------------------------------------------------+** +*******************************************************************************/ + +/** \file bios6_edma3_drv_sample.h + + \brief Header file for the Demo application for the EDMA3 Driver. + + (C) Copyright 2006, Texas Instruments, Inc + + \version 1.0 Anuj Aggarwal - Created + + */ + +#ifndef _BIOS6_EDMA3_DRV_SAMPLE_H_ +#define _BIOS6_EDMA3_DRV_SAMPLE_H_ + +#include +#include + +/* Include EDMA3 Driver */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Cache line size on the underlying SoC. It needs to be modified + * for different cache line sizes, if the Cache is Enabled. + */ +#define EDMA3_CACHE_LINE_SIZE_IN_BYTES (128u) + +/* Error returned in case of buffers are not aligned on the cache boundary */ +#define EDMA3_NON_ALIGNED_BUFFERS_ERROR (-2) + + +/** + * \brief SoC specific TC related information. Specified in the sample + * configuration file (bios_edma3_sample_cfg.c). + */ +extern unsigned int numEdma3Tc; +extern unsigned int ccXferCompInt; +extern unsigned int ccErrorInt; +extern unsigned int tcErrorInt[8]; + +extern unsigned int hwIntXferComp; +extern unsigned int hwIntCcErr; +extern unsigned int hwIntTcErr; + + + + +/** + * \brief EDMA3 Initialization + * + * This function initializes the EDMA3 Driver and registers the + * interrupt handlers. + * + * \return EDMA3_DRV_SOK if success, else error code + */ +EDMA3_DRV_Result edma3init (void); + +/** + * \brief EDMA3 De-initialization + * + * This function removes the EDMA3 RM Instance and un-registers the + * interrupt handlers. It also deletes the RM Object. + * + * \return EDMA3_DRV_SOK if success, else error code + */ +EDMA3_DRV_Result edma3deinit (void); + + +/** + * \brief EDMA3 Cache Invalidate + * + * This function invalidates the D cache. + * + * \param mem_start_ptr [IN] Starting address of memory. + * Please note that this should be + * aligned according to the cache line size. + * \param num_bytes [IN] length of buffer + * \return EDMA3_DRV_SOK if success, else error code in case of error + * or non-alignment of buffers. + * + * Note: This function is required if the buffer is in DDR. + * For other cases, where buffer is NOT in DDR, user + * may or may not require the below implementation and + * should modify it according to her need. + */ +EDMA3_DRV_Result Edma3_CacheInvalidate(unsigned int mem_start_ptr, + unsigned int num_bytes); + + + +/** + * \brief EDMA3 Cache Flush + * + * This function flushes (cleans) the Cache + * + * \param mem_start_ptr [IN] Starting address of memory. + * Please note that this should be + * aligned according to the cache line size. + * \param num_bytes [IN] length of buffer + * \return EDMA3_DRV_SOK if success, else error code in case of error + * or non-alignment of buffers. + * + * Note: This function is required if the buffer is in DDR. + * For other cases, where buffer is NOT in DDR, user + * may or may not require the below implementation and + * should modify it according to her need. + */ +EDMA3_DRV_Result Edma3_CacheFlush(unsigned int mem_start_ptr, + unsigned int num_bytes); + + + +/** + * Counting Semaphore related functions (OS dependent) should be + * called/implemented by the application. A handle to the semaphore + * is required while opening the driver/resource manager instance. + */ + +/** + * \brief EDMA3 OS Semaphore Create + * + * This function creates a counting semaphore with specified + * attributes and initial value. It should be used to create a semaphore + * with initial value as '1'. The semaphore is then passed by the user + * to the EDMA3 driver/RM for proper sharing of resources. + * \param initVal [IN] is initial value for semaphore + * \param semParams [IN] is the semaphore attributes. + * \param hSem [OUT] is location to receive the handle to just created + * semaphore. + * \return EDMA3_DRV_SOK if successful, else a suitable error code. + */ +EDMA3_DRV_Result edma3OsSemCreate(int initVal, + const Semaphore_Params *semParams, + EDMA3_OS_Sem_Handle *hSem); + + + +/** + * \brief EDMA3 OS Semaphore Delete + * + * This function deletes or removes the specified semaphore + * from the system. Associated dynamically allocated memory + * if any is also freed up. + * \param hSem [IN] handle to the semaphore to be deleted + * \return EDMA3_DRV_SOK if successful else a suitable error code + */ +EDMA3_DRV_Result edma3OsSemDelete(EDMA3_OS_Sem_Handle hSem); + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif /* _BIOS6_EDMA3_DRV_SAMPLE_H_ */ + diff --git a/packages/ti/sdo/edma3/drv/sample/package.bld b/packages/ti/sdo/edma3/drv/sample/package.bld new file mode 100644 index 0000000..804891f --- /dev/null +++ b/packages/ti/sdo/edma3/drv/sample/package.bld @@ -0,0 +1,68 @@ +/* +* Copyright 2006 by Texas Instruments Incorporated. +* +* All rights reserved. Property of Texas Instruments Incorporated. +* Restricted rights to use, duplicate or disclose this code are +* granted through contract. +* +*/ + +var Build = xdc.useModule('xdc.bld.BuildEnvironment'); +var Pkg = xdc.useModule('xdc.bld.PackageContents'); + +var objListDA830 = [ + "src/bios6_edma3_drv_sample_da830_cfg.c", + "src/bios6_edma3_drv_sample_cs.c", + "src/bios6_edma3_drv_sample_init.c", +]; + +var objList = [ + objListDA830, +]; + +/* Platforms supported */ +var plat_supported = [ + 'ti.platforms.evmDA830', + ]; + +/* Directories for each platform */ +var dir = [ + 'da830/', + ]; + +for each (var targ in Build.targets) +{ + for each (var plat in targ.platforms) + { + var lib = "lib/"; + var bool = 0; + + for (var i = 0; i < plat_supported.length; i++) + { + if (java.lang.String(plat).equals(plat_supported[i])) + { + /* Choose the selected platform */ + lib = lib + dir[i]; + bool = 1; + break; + } + } + + if (bool == 0) + throw new Error('Unexpected value in "platform" parameter') + + Pkg.addLibrary(lib + "Debug/" + Pkg.name, targ, { profile: "debug"}).addObjects(objList[i]); + Pkg.addLibrary(lib + "Release/" + Pkg.name, targ, { profile: "release"}).addObjects(objList[i]); + } +} + + +Pkg.otherFiles=[ + 'lib/da830/Debug/ti.sdo.edma3.drv.sample.a674', + 'lib/da830/Release/ti.sdo.edma3.drv.sample.a674', + 'src', + 'bios6_edma3_drv_sample.h', + 'package.bld', + 'package.xs', +]; + diff --git a/packages/ti/sdo/edma3/drv/sample/package.xdc b/packages/ti/sdo/edma3/drv/sample/package.xdc new file mode 100644 index 0000000..789909e --- /dev/null +++ b/packages/ti/sdo/edma3/drv/sample/package.xdc @@ -0,0 +1,17 @@ +/* + * ======== package.xdc ======== + * + */ + +/* + * List the packages to be included in the bundle. The 'requires' + * statements must come before the 'package' statement. + */ +requires ti.sdo.edma3.drv; + + +/*! + * ======== ti.sdo.edma3.drv.sample ======== + */ +package ti.sdo.edma3.drv.sample [2, 00, 00] { +} diff --git a/packages/ti/sdo/edma3/drv/sample/package.xs b/packages/ti/sdo/edma3/drv/sample/package.xs new file mode 100644 index 0000000..912406d --- /dev/null +++ b/packages/ti/sdo/edma3/drv/sample/package.xs @@ -0,0 +1,59 @@ +/* + * ======== package.xs ======== + * + */ + +/* + * ======== getLibs ======== + */ +function getLibs(prog) +{ + var bool = 0; + + print ("Inside EDMA3 Drv Sample getLibs"); + + /* Prepare variables to form the library path within this package */ + var name = "ti.sdo.edma3.drv.sample.a674"; + var lib = "lib/"; + + /* Devices supported */ + var devices = [ + 'TMS320DA830', + ]; + + /* Directories for each platform */ + var dir = [ + 'da830/', + ]; + + for (var i = 0; i < devices.length; i++) + { + if (java.lang.String(Program.cpu.deviceName).equals(devices[i])) + { + /* Choose the selected platform */ + lib = lib + dir[i]; + bool = 1; + break; + } + } + + if (bool == 0) + throw new Error('Unexpected value in "platform" parameter') + + switch (this.profile) { + case 'debug': + /* enable debug build for debug profile only */ + lib = lib + "Debug/" + name; + break; + + default: + /* release profile for everything else */ + lib = lib + "Release/" + name; + } + + print(" will link with " + this.$name + ":" + lib); + + /* return the library name */ + return (lib); +} + diff --git a/packages/ti/sdo/edma3/drv/sample/src/bios6_edma3_drv_sample_cs.c b/packages/ti/sdo/edma3/drv/sample/src/bios6_edma3_drv_sample_cs.c new file mode 100644 index 0000000..39e97b2 --- /dev/null +++ b/packages/ti/sdo/edma3/drv/sample/src/bios6_edma3_drv_sample_cs.c @@ -0,0 +1,411 @@ +/******************************************************************************* +**+--------------------------------------------------------------------------+** +**| **** |** +**| **** |** +**| ******o*** |** +**| ********_///_**** |** +**| ***** /_//_/ **** |** +**| ** ** (__/ **** |** +**| ********* |** +**| **** |** +**| *** |** +**| |** +**| Copyright (c) 1998-2006 Texas Instruments Incorporated |** +**| ALL RIGHTS RESERVED |** +**| |** +**| Permission is hereby granted to licensees of Texas Instruments |** +**| Incorporated (TI) products to use this computer program for the sole |** +**| purpose of implementing a licensee product based on TI products. |** +**| No other rights to reproduce, use, or disseminate this computer |** +**| program, whether in part or in whole, are granted. |** +**| |** +**| TI makes no representation or warranties with respect to the |** +**| performance of this computer program, and specifically disclaims |** +**| any responsibility for any damages, special or consequential, |** +**| connected with the use of this program. |** +**| |** +**+--------------------------------------------------------------------------+** +*******************************************************************************/ + +/** \file bios6_edma3_drv_sample_cs.c + + \brief Sample functions showing the implementation of Critical section + entry/exit routines and various semaphore related routines (all BIOS6 + depenedent). These implementations MUST be provided by the user / + application, using the EDMA3 driver, for its correct functioning. + + (C) Copyright 2006, Texas Instruments, Inc + + \version 1.0 Anuj Aggarwal - Created + + */ + +#include +#include +#include +#include +#include + +#include + +/** + * \brief EDMA3 OS Protect Entry + * + * This function saves the current state of protection in 'intState' + * variable passed by caller, if the protection level is + * EDMA3_OS_PROTECT_INTERRUPT. It then applies the requested level of + * protection. + * For EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION and + * EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR, variable 'intState' is ignored, + * and the requested interrupt is disabled. + * For EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR, '*intState' specifies the + * Transfer Controller number whose interrupt needs to be disabled. + * + * \param level is numeric identifier of the desired degree of protection. + * \param intState is memory location where current state of protection is + * saved for future use while restoring it via edma3OsProtectExit() (Only + * for EDMA3_OS_PROTECT_INTERRUPT protection level). + * \return None + */ +void edma3OsProtectEntry (int level, unsigned int *intState) + { + if (((level == EDMA3_OS_PROTECT_INTERRUPT) + || (level == EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR)) + && (intState == NULL)) + { + return; + } + else + { + switch (level) + { + /* Disable all (global) interrupts */ + case EDMA3_OS_PROTECT_INTERRUPT : + *intState = Hwi_disable(); + break; + + /* Disable scheduler */ + case EDMA3_OS_PROTECT_SCHEDULER : + Task_disable(); + break; + + /* Disable EDMA3 transfer completion interrupt only */ + case EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION : + EventCombiner_disableEvent(ccXferCompInt); + break; + + /* Disable EDMA3 CC error interrupt only */ + case EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR : + EventCombiner_disableEvent(ccErrorInt); + break; + + /* Disable EDMA3 TC error interrupt only */ + case EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR : + switch (*intState) + { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + /* Fall through... */ + /* Disable the corresponding interrupt */ + EventCombiner_disableEvent(tcErrorInt[*intState]); + break; + + default: + break; + } + + break; + + default: + break; + } + } + } + + +/** + * \brief EDMA3 OS Protect Exit + * + * This function undoes the protection enforced to original state + * as is specified by the variable 'intState' passed, if the protection + * level is EDMA3_OS_PROTECT_INTERRUPT. + * For EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION and + * EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR, variable 'intState' is ignored, + * and the requested interrupt is enabled. + * For EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR, 'intState' specifies the + * Transfer Controller number whose interrupt needs to be enabled. + * \param level is numeric identifier of the desired degree of protection. + * \param intState is original state of protection at time when the + * corresponding edma3OsProtectEntry() was called (Only + * for EDMA3_OS_PROTECT_INTERRUPT protection level). + * \return None + */ +void edma3OsProtectExit (int level, unsigned int intState) + { + switch (level) + { + /* Enable all (global) interrupts */ + case EDMA3_OS_PROTECT_INTERRUPT : + Hwi_restore(intState); + break; + + /* Enable scheduler */ + case EDMA3_OS_PROTECT_SCHEDULER : + Task_enable(); + break; + + /* Enable EDMA3 transfer completion interrupt only */ + case EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION : + EventCombiner_enableEvent(ccXferCompInt); + break; + + /* Enable EDMA3 CC error interrupt only */ + case EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR : + EventCombiner_enableEvent(ccErrorInt); + break; + + /* Enable EDMA3 TC error interrupt only */ + case EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR : + switch (intState) + { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + /* Fall through... */ + /* Enable the corresponding interrupt */ + EventCombiner_enableEvent(tcErrorInt[intState]); + break; + + default: + break; + } + + break; + + default: + break; + } + } + + +/** + * \brief EDMA3 Cache Invalidate + * + * This function invalidates the D cache. + * + * \param mem_start_ptr [IN] Starting address of memory. + * Please note that this should be + * aligned according to the cache line size. + * \param num_bytes [IN] length of buffer + * \return EDMA3_DRV_SOK if success, else error code in case of error + * or non-alignment of buffers. + * + * Note: This function is required if the buffer is in DDR. + * For other cases, where buffer is NOT in DDR, user + * may or may not require the below implementation and + * should modify it according to her need. + */ +EDMA3_DRV_Result Edma3_CacheInvalidate(unsigned int mem_start_ptr, + unsigned int num_bytes) + { + EDMA3_DRV_Result cacheInvResult = EDMA3_DRV_SOK; + + /* Verify whether the start address is cache aligned or not */ + if((mem_start_ptr & (EDMA3_CACHE_LINE_SIZE_IN_BYTES-1u)) != 0) + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("\r\n Cache : Memory is not %d bytes alinged\r\n", + EDMA3_CACHE_LINE_SIZE_IN_BYTES); +#endif + cacheInvResult = EDMA3_NON_ALIGNED_BUFFERS_ERROR; + } + else + { + Cache_inv((Ptr)mem_start_ptr, num_bytes, Cache_Type_ALL, TRUE); + } + + return cacheInvResult; +} + + + +/** + * \brief EDMA3 Cache Flush + * + * This function flushes (cleans) the Cache + * + * \param mem_start_ptr [IN] Starting address of memory. + * Please note that this should be + * aligned according to the cache line size. + * \param num_bytes [IN] length of buffer + * \return EDMA3_DRV_SOK if success, else error code in case of error + * or non-alignment of buffers. + * + * Note: This function is required if the buffer is in DDR. + * For other cases, where buffer is NOT in DDR, user + * may or may not require the below implementation and + * should modify it according to her need. + */ +EDMA3_DRV_Result Edma3_CacheFlush(unsigned int mem_start_ptr, + unsigned int num_bytes) + { + EDMA3_DRV_Result cacheFlushResult = EDMA3_DRV_SOK; + + /* Verify whether the start address is cache aligned or not */ + if((mem_start_ptr & (EDMA3_CACHE_LINE_SIZE_IN_BYTES-1u)) != 0) + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("\r\n Cache : Memory is not %d bytes alinged\r\n", + EDMA3_CACHE_LINE_SIZE_IN_BYTES); +#endif + cacheFlushResult = EDMA3_NON_ALIGNED_BUFFERS_ERROR; + } + else + { + Cache_wb((Ptr)mem_start_ptr, num_bytes, Cache_Type_ALL, TRUE); + } + + return cacheFlushResult; +} + + +/** + * Counting Semaphore related functions (OS dependent) should be + * called/implemented by the application. A handle to the semaphore + * is required while opening the driver/resource manager instance. + */ + +/** + * \brief EDMA3 OS Semaphore Create + * + * This function creates a counting semaphore with specified + * attributes and initial value. It should be used to create a semaphore + * with initial value as '1'. The semaphore is then passed by the user + * to the EDMA3 driver/RM for proper sharing of resources. + * \param initVal [IN] is initial value for semaphore + * \param semParams [IN] is the semaphore attributes. + * \param hSem [OUT] is location to recieve the handle to just created + * semaphore + * \return EDMA3_DRV_SOK if succesful, else a suitable error code. + */ +EDMA3_DRV_Result edma3OsSemCreate(int initVal, + const Semaphore_Params *semParams, + EDMA3_OS_Sem_Handle *hSem) + { + EDMA3_DRV_Result semCreateResult = EDMA3_DRV_SOK; + + if(NULL == hSem) + { + semCreateResult = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + *hSem = (EDMA3_OS_Sem_Handle)Semaphore_create(initVal, semParams, NULL); + if ( (*hSem) == NULL ) + { + semCreateResult = EDMA3_DRV_E_SEMAPHORE; + } + } + + return semCreateResult; + } + + +/** + * \brief EDMA3 OS Semaphore Delete + * + * This function deletes or removes the specified semaphore + * from the system. Associated dynamically allocated memory + * if any is also freed up. + * \param hSem [IN] handle to the semaphore to be deleted + * \return EDMA3_DRV_SOK if succesful else a suitable error code + */ +EDMA3_DRV_Result edma3OsSemDelete(EDMA3_OS_Sem_Handle hSem) + { + EDMA3_DRV_Result semDeleteResult = EDMA3_DRV_SOK; + + if(NULL == hSem) + { + semDeleteResult = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + Semaphore_delete((Semaphore_Handle *)&hSem); + } + + return semDeleteResult; + } + + +/** + * \brief EDMA3 OS Semaphore Take + * + * This function takes a semaphore token if available. + * If a semaphore is unavailable, it blocks currently + * running thread in wait (for specified duration) for + * a free semaphore. + * \param hSem [IN] is the handle of the specified semaphore + * \param mSecTimeout [IN] is wait time in milliseconds + * \return EDMA3_DRV_Result if successful else a suitable error code + */ +EDMA3_DRV_Result edma3OsSemTake(EDMA3_OS_Sem_Handle hSem, int mSecTimeout) + { + EDMA3_DRV_Result semTakeResult = EDMA3_DRV_SOK; + unsigned short semPendResult; + + if(NULL == hSem) + { + semTakeResult = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + semPendResult = Semaphore_pend(hSem, mSecTimeout); + if (semPendResult == FALSE) + { + semTakeResult = EDMA3_DRV_E_SEMAPHORE; + } + } + + return semTakeResult; + } + + +/** + * \brief EDMA3 OS Semaphore Give + * + * This function gives or relinquishes an already + * acquired semaphore token + * \param hSem [IN] is the handle of the specified semaphore + * \return EDMA3_DRV_Result if successful else a suitable error code + */ +EDMA3_DRV_Result edma3OsSemGive(EDMA3_OS_Sem_Handle hSem) + { + EDMA3_DRV_Result semGiveResult = EDMA3_DRV_SOK; + + if(NULL == hSem) + { + semGiveResult = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + Semaphore_post(hSem); + } + + return semGiveResult; + } + + + + + diff --git a/packages/ti/sdo/edma3/drv/sample/src/bios6_edma3_drv_sample_da830_cfg.c b/packages/ti/sdo/edma3/drv/sample/src/bios6_edma3_drv_sample_da830_cfg.c new file mode 100644 index 0000000..93cc42c --- /dev/null +++ b/packages/ti/sdo/edma3/drv/sample/src/bios6_edma3_drv_sample_da830_cfg.c @@ -0,0 +1,403 @@ +/******************************************************************************* +**+--------------------------------------------------------------------------+** +**| **** |** +**| **** |** +**| ******o*** |** +**| ********_///_**** |** +**| ***** /_//_/ **** |** +**| ** ** (__/ **** |** +**| ********* |** +**| **** |** +**| *** |** +**| |** +**| Copyright (c) 1998-2006 Texas Instruments Incorporated |** +**| ALL RIGHTS RESERVED |** +**| |** +**| Permission is hereby granted to licensees of Texas Instruments |** +**| Incorporated (TI) products to use this computer program for the sole |** +**| purpose of implementing a licensee product based on TI products. |** +**| No other rights to reproduce, use, or disseminate this computer |** +**| program, whether in part or in whole, are granted. |** +**| |** +**| TI makes no representation or warranties with respect to the |** +**| performance of this computer program, and specifically disclaims |** +**| any responsibility for any damages, special or consequential, |** +**| connected with the use of this program. |** +**| |** +**+--------------------------------------------------------------------------+** +*******************************************************************************/ + +/** \file bios6_edma3_drv_sample_da830_cfg.c + + \brief SoC specific EDMA3 hardware related information like number of + transfer controllers, various interrupt ids etc. It is used while + interrupts enabling / disabling. It needs to be ported for different + SoCs. + + (C) Copyright 2008, Texas Instruments, Inc + + \version 1.0 Anuj Aggarwal - Created + + */ + +#include + + +/* DA830 Specific EDMA3 Information */ + +/** Number of PaRAM Sets available */ +#define EDMA3_NUM_PARAMSET (128u) + +/** Number of TCCS available */ +#define EDMA3_NUM_TCC (32u) + +/** Number of Event Queues available */ +#define EDMA3_NUM_EVTQUE (2u) + +/** Number of Transfer Controllers available */ +#define EDMA3_NUM_TC (2u) + +/** Interrupt no. for Transfer Completion */ +#define EDMA3_CC_XFER_COMPLETION_INT (8u) + +/** Interrupt no. for CC Error */ +#define EDMA3_CC_ERROR_INT (56u) + +/** Interrupt no. for TCs Error */ +#define EDMA3_TC0_ERROR_INT (57u) +#define EDMA3_TC1_ERROR_INT (58u) +#define EDMA3_TC2_ERROR_INT (0u) +#define EDMA3_TC3_ERROR_INT (0u) +#define EDMA3_TC4_ERROR_INT (0u) +#define EDMA3_TC5_ERROR_INT (0u) +#define EDMA3_TC6_ERROR_INT (0u) +#define EDMA3_TC7_ERROR_INT (0u) + +/** +* EDMA3 interrupts (transfer completion, CC error etc.) correspond to different +* ECM events (SoC specific). These ECM events come +* under ECM block XXX (handling those specific ECM events). Normally, block +* 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events +* 32-63 and so on. This ECM block XXX (or interrupt selection number XXX) +* is mapped to a specific HWI_INT YYY in the tcf file. +* Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding +* to transfer completion interrupt. +* Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding +* to CC error interrupts. +* Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding +* to TC error interrupts. +*/ +#define EDMA3_HWI_INT_XFER_COMP (7u) +#define EDMA3_HWI_INT_CC_ERR (8u) +#define EDMA3_HWI_INT_TC_ERR (8u) + + +/** + * \brief Mapping of DMA channels 0-31 to Hardware Events from + * various peripherals, which use EDMA for data transfer. + * All channels need not be mapped, some can be free also. + * 1: Mapped + * 0: Not mapped + * + * This mapping will be used to allocate DMA channels when user passes + * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory + * copy). The same mapping is used to allocate the TCC when user passes + * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy). + * + * To allocate more DMA channels or TCCs, one has to modify the event mapping. + */ + /* 31 0 */ +#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0 (0xCF3FFFFFu) + +/** + * \brief Mapping of DMA channels 32-63 to Hardware Events from + * various peripherals, which use EDMA for data transfer. + * All channels need not be mapped, some can be free also. + * 1: Mapped + * 0: Not mapped + * + * This mapping will be used to allocate DMA channels when user passes + * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory + * copy). The same mapping is used to allocate the TCC when user passes + * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy). + * + * To allocate more DMA channels or TCCs, one has to modify the event mapping. + */ +/* DMA channels 32-63 DOES NOT exist in DA830. */ +#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1 (0x0u) + + +/* Variable which will be used internally for referring number of Event Queues. */ +unsigned int numEdma3EvtQue = EDMA3_NUM_EVTQUE; + +/* Variable which will be used internally for referring number of TCs. */ +unsigned int numEdma3Tc = EDMA3_NUM_TC; + +/** + * Variable which will be used internally for referring transfer completion + * interrupt. + */ +unsigned int ccXferCompInt = EDMA3_CC_XFER_COMPLETION_INT; + +/** + * Variable which will be used internally for referring channel controller's + * error interrupt. + */ +unsigned int ccErrorInt = EDMA3_CC_ERROR_INT; + +/** + * Variable which will be used internally for referring transfer controllers' + * error interrupts. + */ +unsigned int tcErrorInt[8] = { + EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT, + EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT, + EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT, + EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT + }; + +/** + * Variables which will be used internally for referring the hardware interrupt + * for various EDMA3 interrupts. + */ +unsigned int hwIntXferComp = EDMA3_HWI_INT_XFER_COMP; +unsigned int hwIntCcErr = EDMA3_HWI_INT_CC_ERR; +unsigned int hwIntTcErr = EDMA3_HWI_INT_TC_ERR; + + +/* Driver Object Initialization Configuration */ +EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams = + { + /** Total number of DMA Channels supported by the EDMA3 Controller */ + 32u, + /** Total number of QDMA Channels supported by the EDMA3 Controller */ + 8u, + /** Total number of TCCs supported by the EDMA3 Controller */ + 32u, + /** Total number of PaRAM Sets supported by the EDMA3 Controller */ + 128u, + /** Total number of Event Queues in the EDMA3 Controller */ + 2u, + /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */ + 2u, + /** Number of Regions on this EDMA3 controller */ + 4u, + + /** + * \brief Channel mapping existence + * A value of 0 (No channel mapping) implies that there is fixed association + * for a channel number to a parameter entry number or, in other words, + * PaRAM entry n corresponds to channel n. + */ + 0u, + + /** Existence of memory protection feature */ + 0u, + + /** Global Register Region of CC Registers */ + (void *)0x01C00000u, + /** Transfer Controller (TC) Registers */ + { + (void *)0x01C08000u, + (void *)0x01C08400u, + (void *)NULL, + (void *)NULL, + (void *)NULL, + (void *)NULL, + (void *)NULL, + (void *)NULL + }, + /** Interrupt no. for Transfer Completion */ + EDMA3_CC_XFER_COMPLETION_INT, + /** Interrupt no. for CC Error */ + EDMA3_CC_ERROR_INT, + /** Interrupt no. for TCs Error */ + { + EDMA3_TC0_ERROR_INT, + EDMA3_TC1_ERROR_INT, + EDMA3_TC2_ERROR_INT, + EDMA3_TC3_ERROR_INT, + EDMA3_TC4_ERROR_INT, + EDMA3_TC5_ERROR_INT, + EDMA3_TC6_ERROR_INT, + EDMA3_TC7_ERROR_INT + }, + + /** + * \brief EDMA3 TC priority setting + * + * User can program the priority of the Event Queues + * at a system-wide level. This means that the user can set the + * priority of an IO initiated by either of the TCs (Transfer Controllers) + * relative to IO initiated by the other bus masters on the + * device (ARM, DSP, USB, etc) + */ + { + 0u, + 1u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u + }, + /** + * \brief To Configure the Threshold level of number of events + * that can be queued up in the Event queues. EDMA3CC error register + * (CCERR) will indicate whether or not at any instant of time the + * number of events queued up in any of the event queues exceeds + * or equals the threshold/watermark value that is set + * in the queue watermark threshold register (QWMTHRA). + */ + { + 16u, + 16u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u + }, + + /** + * \brief To Configure the Default Burst Size (DBS) of TCs. + * An optimally-sized command is defined by the transfer controller + * default burst size (DBS). Different TCs can have different + * DBS values. It is defined in Bytes. + */ + { + 16u, + 16u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u + }, + + /** + * \brief Mapping from each DMA channel to a Parameter RAM set, + * if it exists, otherwise of no use. + */ + { + 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u, + 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u, + 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u, + 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u, + /* DMA channels 32-63 DOES NOT exist in DA830. */ + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS + }, + + /** + * \brief Mapping from each DMA channel to a TCC. This specific + * TCC code will be returned when the transfer is completed + * on the mapped channel. + */ + { + 0u, 1u, 2u, 3u, + 4u, 5u, 6u, 7u, + 8u, 9u, 10u, 11u, + 12u, 13u, 14u, 15u, + 16u, 17u, 18u, 19u, + 20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, + 24u, 25u, 26u, 27u, + EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, 30, 31, + /* DMA channels 32-63 DOES NOT exist in DA830. */ + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC + }, + + /** + * \brief Mapping of DMA channels to Hardware Events from + * various peripherals, which use EDMA for data transfer. + * All channels need not be mapped, some can be free also. + */ + { + EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0, + EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1 + } + }; + + +/* Driver Instance Initialization Configuration */ +EDMA3_DRV_InstanceInitConfig sampleInstInitConfig = + { + /* Resources owned by Region 1 */ + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0xFFFFFFFFu, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x000000FFu}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0xFFFFFFFFu, 0x00000000u}, + + /* Resources reserved by Region 1 */ + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* resvdDmaChannels */ + /* 31 0 */ + {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0, + /* 63 32 */ + EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 */ + {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0, + /* 63 32 */ + EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1} + }; + + +/* End of File */ + + diff --git a/packages/ti/sdo/edma3/drv/sample/src/bios6_edma3_drv_sample_init.c b/packages/ti/sdo/edma3/drv/sample/src/bios6_edma3_drv_sample_init.c new file mode 100644 index 0000000..9d0e8c3 --- /dev/null +++ b/packages/ti/sdo/edma3/drv/sample/src/bios6_edma3_drv_sample_init.c @@ -0,0 +1,325 @@ +/******************************************************************************* +**+--------------------------------------------------------------------------+** +**| **** |** +**| **** |** +**| ******o*** |** +**| ********_///_**** |** +**| ***** /_//_/ **** |** +**| ** ** (__/ **** |** +**| ********* |** +**| **** |** +**| *** |** +**| |** +**| Copyright (c) 1998-2006 Texas Instruments Incorporated |** +**| ALL RIGHTS RESERVED |** +**| |** +**| Permission is hereby granted to licensees of Texas Instruments |** +**| Incorporated (TI) products to use this computer program for the sole |** +**| purpose of implementing a licensee product based on TI products. |** +**| No other rights to reproduce, use, or disseminate this computer |** +**| program, whether in part or in whole, are granted. |** +**| |** +**| TI makes no representation or warranties with respect to the |** +**| performance of this computer program, and specifically disclaims |** +**| any responsibility for any damages, special or consequential, |** +**| connected with the use of this program. |** +**| |** +**+--------------------------------------------------------------------------+** +*******************************************************************************/ + +/** \file bios6_edma3_drv_sample_init.c + + \brief Sample Initialization for the EDMA3 Driver for BIOS 6 based + applications. It should be MANDATORILY done once before EDMA3 usage. + + (C) Copyright 2006, Texas Instruments, Inc + + \version 1.0 Anuj Aggarwal - Created + + */ + +#include +#include +#include + +#include + +/** @brief EDMA3 Driver Handle, used to call all the Driver APIs */ +EDMA3_DRV_Handle hEdma = NULL; + +/** @brief EDMA3 Driver Instance specific Semaphore handle */ +static EDMA3_OS_Sem_Handle semHandle = NULL; + +/** + * EDMA3 TC ISRs which need to be registered with the underlying OS by the user + * (Not all TC error ISRs need to be registered, register only for the + * available Transfer Controllers). + */ +void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) = + { + &lisrEdma3TC0ErrHandler0, + &lisrEdma3TC1ErrHandler0, + &lisrEdma3TC2ErrHandler0, + &lisrEdma3TC3ErrHandler0, + &lisrEdma3TC4ErrHandler0, + &lisrEdma3TC5ErrHandler0, + &lisrEdma3TC6ErrHandler0, + &lisrEdma3TC7ErrHandler0, + }; + + +/** To Register the ISRs with the underlying OS, if required. */ +static void registerEdma3Interrupts (void); +/** To Unregister the ISRs with the underlying OS, if previously registered. */ +static void unregisterEdma3Interrupts (void); + +/* External Global Configuration Structure */ +extern EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams; + +/* External Instance Specific Configuration Structure */ +extern EDMA3_DRV_InstanceInitConfig sampleInstInitConfig; + + +/** + * \brief EDMA3 Initialization + * + * This function initializes the EDMA3 Driver and registers the + * interrupt handlers. + * + * \return EDMA3_DRV_SOK if success, else error code + */ + EDMA3_DRV_Result edma3init (void) + { + unsigned int edma3InstanceId = 0; + EDMA3_DRV_InitConfig initCfg; + EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK; + Semaphore_Params semParams; + EDMA3_DRV_GblConfigParams *globalConfig = &sampleEdma3GblCfgParams; + EDMA3_DRV_InstanceInitConfig *instanceConfig = &sampleInstInitConfig; + EDMA3_RM_MiscParam miscParam; + + if (NULL == hEdma) + { + /* configuration structure for the Driver */ + initCfg.isMaster = TRUE; + initCfg.regionId = (EDMA3_RM_RegionId)1u; + initCfg.drvSemHandle = NULL; + + /* Driver instance specific config NULL */ + initCfg.drvInstInitConfig = instanceConfig; + initCfg.gblerrCb = NULL; + initCfg.gblerrData = NULL; + + miscParam.isSlave = FALSE; + + /* Create EDMA3 Driver Object first. */ + edma3Result = EDMA3_DRV_create (edma3InstanceId, globalConfig, (void *)&miscParam); + + if (edma3Result != EDMA3_DRV_SOK) + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("edma3init: EDMA3_DRV_create FAILED\r\n"); +#endif + } + else + { + /** + * Driver Object created successfully. + * Create a semaphore now for driver instance. + */ +// #if 0 + Semaphore_Params_init(&semParams); + + edma3Result = edma3OsSemCreate(1, &semParams, &initCfg.drvSemHandle); + if (edma3Result != EDMA3_DRV_SOK) + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("edma3init: edma3OsSemCreate FAILED\r\n"); +#endif + } + else + { + /* Save the semaphore handle for future use */ + semHandle = initCfg.drvSemHandle; +// #endif + +// //junk value +// initCfg.drvSemHandle = (EDMA3_OS_Sem_Handle)0x01100110; + + /* Open the Driver Instance */ + hEdma = EDMA3_DRV_open (edma3InstanceId, (void *) &initCfg, + &edma3Result); + if(NULL == hEdma) + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("edma3init: EDMA3_DRV_open FAILED\r\n"); +#endif + } + else + { + /** + * Register Interrupt Handlers for various interrupts + * like transfer completion interrupt, CC error + * interrupt, TC error interrupts etc, if required. + */ + registerEdma3Interrupts(); + } + } + } + } + else + { + /* EDMA3 Driver already initialized, no need to do that again. */ +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("edma3init: EDMA3 Driver Already Initialized...Init failed\r\n"); +#endif + edma3Result = EDMA3_DRV_E_INVALID_STATE; + } + + return edma3Result; + } + + +/** To Register the ISRs with the underlying OS, if required. */ +static void registerEdma3Interrupts (void) + { + static UInt32 cookie = 0; + unsigned int numTc = 0; + + /* Disabling the global interrupts */ + cookie = Hwi_disable(); + + /* Enable the Xfer Completion Event Interrupt */ + EventCombiner_dispatchPlug(ccXferCompInt, (EventCombiner_FuncPtr)(&lisrEdma3ComplHandler0), + NULL, 0); + EventCombiner_enableEvent(ccXferCompInt); + + /* Enable the CC Error Event Interrupt */ + EventCombiner_dispatchPlug(ccErrorInt, (EventCombiner_FuncPtr)(&lisrEdma3CCErrHandler0), + NULL, 0); + EventCombiner_enableEvent(ccErrorInt); + + /* Enable the TC Error Event Interrupt, according to the number of TCs. */ + while (numTc < numEdma3Tc) + { + EventCombiner_dispatchPlug(tcErrorInt[numTc], + (EventCombiner_FuncPtr)(ptrEdma3TcIsrHandler[numTc]), + NULL, 0); + EventCombiner_enableEvent(tcErrorInt[numTc]); + numTc++; + } + + + /** + * Enabling the HWI_ID. + * EDMA3 interrupts (transfer completion, CC error etc.) + * correspond to different ECM events (SoC specific). These ECM events come + * under ECM block XXX (handling those specific ECM events). Normally, block + * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events + * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX) + * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this + * mapped HWI_INT YYY, one should use the corresponding bitmask in the + * API C64_enableIER(), in which the YYY bit is SET. + */ + Hwi_enableInterrupt(hwIntXferComp); + Hwi_enableInterrupt(hwIntCcErr); + Hwi_enableInterrupt(hwIntTcErr); + + /* Restore interrupts */ + Hwi_restore(cookie); + } + + +/** + * \brief EDMA3 De-initialization + * + * This function removes the EDMA3 Driver instance and unregisters the + * interrupt handlers. + * + * \return EDMA3_DRV_SOK if success, else error code + */ + EDMA3_DRV_Result edma3deinit (void) + { + unsigned int edmaInstanceId = 0; + EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK; + + /* Unregister Interrupt Handlers first */ + unregisterEdma3Interrupts(); + + /* Delete the semaphore */ +// #if 0 + edma3Result = edma3OsSemDelete(semHandle); + if (EDMA3_DRV_SOK != edma3Result ) + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("edma3deinit: edma3OsSemDelete FAILED\r\n"); +#endif + } + else + { + /* Make the semaphore handle as NULL. */ + semHandle = NULL; +// #endif + + /* Now, close the EDMA3 Driver Instance */ + edma3Result = EDMA3_DRV_close (hEdma, NULL); + if (EDMA3_DRV_SOK != edma3Result ) + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("edma3deinit: EDMA3_DRV_close FAILED\r\n"); +#endif + } + else + { + /* Make the Drv handle as NULL. */ + hEdma = NULL; + + /* Now, delete the EDMA3 Driver Object */ + edma3Result = EDMA3_DRV_delete (edmaInstanceId, NULL); + if (EDMA3_DRV_SOK != edma3Result ) + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("edma3deinit: EDMA3_DRV_delete FAILED\r\n"); +#endif + } + else + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("edma3deinit: EDMA3 Deinitialization" \ + " Completed...\r\n"); +#endif + } + } + } + + return edma3Result; + } + + +/** To Unregister the ISRs with the underlying OS, if previously registered. */ +static void unregisterEdma3Interrupts (void) + { + static UInt32 cookie = 0; + unsigned int numTc = 0; + + /* Disabling the global interrupts */ + cookie = Hwi_disable(); + + /* Disable the Xfer Completion Event Interrupt */ + EventCombiner_disableEvent(ccXferCompInt); + + /* Disable the CC Error Event Interrupt */ + EventCombiner_disableEvent(ccErrorInt); + + /* Enable the TC Error Event Interrupt, according to the number of TCs. */ + while (numTc < numEdma3Tc) + { + EventCombiner_disableEvent(tcErrorInt[numTc]); + numTc++; + } + + /* Restore interrupts */ + Hwi_restore(cookie); + } + +/* End of File */ diff --git a/packages/ti/sdo/edma3/drv/src/edma3.h b/packages/ti/sdo/edma3/drv/src/edma3.h new file mode 100644 index 0000000..e95678b --- /dev/null +++ b/packages/ti/sdo/edma3/drv/src/edma3.h @@ -0,0 +1,416 @@ +/******************************************************************************* +**+--------------------------------------------------------------------------+** +**| **** |** +**| **** |** +**| ******o*** |** +**| ********_///_**** |** +**| ***** /_//_/ **** |** +**| ** ** (__/ **** |** +**| ********* |** +**| **** |** +**| *** |** +**| |** +**| Copyright (c) 1998-2006 Texas Instruments Incorporated |** +**| ALL RIGHTS RESERVED |** +**| |** +**| Permission is hereby granted to licensees of Texas Instruments |** +**| Incorporated (TI) products to use this computer program for the sole |** +**| purpose of implementing a licensee product based on TI products. |** +**| No other rights to reproduce, use, or disseminate this computer |** +**| program, whether in part or in whole, are granted. |** +**| |** +**| TI makes no representation or warranties with respect to the |** +**| performance of this computer program, and specifically disclaims |** +**| any responsibility for any damages, special or consequential, |** +**| connected with the use of this program. |** +**| |** +**+--------------------------------------------------------------------------+** +*******************************************************************************/ + +/** \file edma3.h + \brief EDMA3 Driver Internal header file. + + This file contains implementation specific details used by the EDMA3 + Driver internally. + + (C) Copyright 2006, Texas Instruments, Inc + + \version 0.1.0 Joseph Fernandez - Created + 0.2.0 Anuj Aggarwal - Modified it for EDMA3 package + - Added multiple instances + capability + 0.2.1 Anuj Aggarwal - Modified it for more run time + configuration. + - Made EDMA3 package OS + independent. + 0.2.2 Anuj Aggarwal - Critical section handling code + modification. Uses semaphore and + interrupts disabling mechanism + for resource sharing. + 0.3.0 Anuj Aggarwal - Renamed EDMA3_DVR to EDMA3_DRV + - IPR bit clearing in RM ISR + issue fixed. + - Sample application made generic + 0.3.1 Anuj Aggarwal - Added DMA/QDMA Channel to TCC + mapping, to fix QDMA missed + event issue. + 0.3.2 Anuj Aggarwal - Added support for POLL mode + - Added a new API to modify the + CC Register. + 1.0.0 Anuj Aggarwal - Fixed resource allocation related + bugs. + 1.0.0.1 Anuj Aggarwal - Fixed spurious missed event + generation related bug. + 1.0.0.2 Anuj Aggarwal - Made the EDMA3 package RTSC + compliant. + 1.0.0.3 Anuj Aggarwal - Changed the directory structure + as per RTSC standard. + 1.01.00.01 Anuj Aggarwal - a) Added new APIs to allocate + logical channels + b) Created EDMA3 config files + for different platforms + c) Misc changes + 1.02.00.01 Anuj Aggarwal - a) Added DM6467 support + b) Fixed some MRs + 1.03.00.01 Anuj Aggarwal - a) Added non-RTSC PJT files + b) IOCTL Interface added. + c) Fixed some MRs. + 1.04 Anuj Aggarwal - a) Header files modified to have + extern "C" declarations. + b) Implemented ECNs DPSP00009815 + & DPSP00010035. + + */ + +#ifndef _EDMA3_H_ +#define _EDMA3_H_ + + +/** Include EDMA3 Driver header file */ +#include + +/* For the EDMA3 CC Register Layer functionality */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * \defgroup Edma3DrvInt Internal Interface Definition for EDMA3 Driver + * + * Documentation of the Internal Interface of EDMA3 Driver + * + * @{ + */ + +/* Mask defines */ +/** Parameter RAM Set field OPT bit-field defines */ +/** OPT-SAM bit Clear */ +#define EDMA3_DRV_OPT_SAM_CLR_MASK (~EDMA3_CCRL_OPT_SAM_MASK) +/** OPT-SAM bit Set */ +#define EDMA3_DRV_OPT_SAM_SET_MASK(mode) (((EDMA3_CCRL_OPT_SAM_MASK >> EDMA3_CCRL_OPT_SAM_SHIFT) & (mode)) << EDMA3_CCRL_OPT_SAM_SHIFT) + +/** OPT-DAM bit Clear */ +#define EDMA3_DRV_OPT_DAM_CLR_MASK (~EDMA3_CCRL_OPT_DAM_MASK) +/** OPT-DAM bit Set */ +#define EDMA3_DRV_OPT_DAM_SET_MASK(mode) (((EDMA3_CCRL_OPT_DAM_MASK >> EDMA3_CCRL_OPT_DAM_SHIFT) & (mode)) << EDMA3_CCRL_OPT_DAM_SHIFT) + +/** OPT-SYNCDIM bit Clear */ +#define EDMA3_DRV_OPT_SYNCDIM_CLR_MASK (~EDMA3_CCRL_OPT_SYNCDIM_MASK) +/** OPT-SYNCDIM bit Set */ +#define EDMA3_DRV_OPT_SYNCDIM_SET_MASK(synctype) (((EDMA3_CCRL_OPT_SYNCDIM_MASK >> EDMA3_CCRL_OPT_SYNCDIM_SHIFT) & (synctype)) << EDMA3_CCRL_OPT_SYNCDIM_SHIFT) + +/** OPT-STATIC bit Clear */ +#define EDMA3_DRV_OPT_STATIC_CLR_MASK (~EDMA3_CCRL_OPT_STATIC_MASK) +/** OPT-STATIC bit Set */ +#define EDMA3_DRV_OPT_STATIC_SET_MASK(en) (((EDMA3_CCRL_OPT_STATIC_MASK >> EDMA3_CCRL_OPT_STATIC_SHIFT) & (en)) << EDMA3_CCRL_OPT_STATIC_SHIFT) + +/** OPT-FWID bitfield Clear */ +#define EDMA3_DRV_OPT_FWID_CLR_MASK (~EDMA3_CCRL_OPT_FWID_MASK) +/** OPT-FWID bitfield Set */ +#define EDMA3_DRV_OPT_FWID_SET_MASK(width) (((EDMA3_CCRL_OPT_FWID_MASK >> EDMA3_CCRL_OPT_FWID_SHIFT) & (width)) << EDMA3_CCRL_OPT_FWID_SHIFT) + +/** OPT-TCCMODE bit Clear */ +#define EDMA3_DRV_OPT_TCCMODE_CLR_MASK (~EDMA3_CCRL_OPT_TCCMODE_MASK) +/** OPT-TCCMODE bit Set */ +#define EDMA3_DRV_OPT_TCCMODE_SET_MASK(early) (((EDMA3_CCRL_OPT_TCCMODE_MASK >> EDMA3_CCRL_OPT_TCCMODE_SHIFT) & (early)) << EDMA3_CCRL_OPT_TCCMODE_SHIFT) + +/** OPT-TCC bitfield Clear */ +#define EDMA3_DRV_OPT_TCC_CLR_MASK (~EDMA3_CCRL_OPT_TCC_MASK) +/** OPT-TCC bitfield Set */ +#define EDMA3_DRV_OPT_TCC_SET_MASK(tcc) (((EDMA3_CCRL_OPT_TCC_MASK >> EDMA3_CCRL_OPT_TCC_SHIFT) & (tcc)) << EDMA3_CCRL_OPT_TCC_SHIFT) + +/** OPT-TCINTEN bit Clear */ +#define EDMA3_DRV_OPT_TCINTEN_CLR_MASK (~EDMA3_CCRL_OPT_TCINTEN_MASK) +/** OPT-TCINTEN bit Set */ +#define EDMA3_DRV_OPT_TCINTEN_SET_MASK(tcinten) (((EDMA3_CCRL_OPT_TCINTEN_MASK >> EDMA3_CCRL_OPT_TCINTEN_SHIFT) & (tcinten)) << EDMA3_CCRL_OPT_TCINTEN_SHIFT) + +/** OPT-ITCINTEN bit Clear */ +#define EDMA3_DRV_OPT_ITCINTEN_CLR_MASK (~EDMA3_CCRL_OPT_ITCINTEN_MASK) +/** OPT-ITCINTEN bit Set */ +#define EDMA3_DRV_OPT_ITCINTEN_SET_MASK(itcinten) (((EDMA3_CCRL_OPT_ITCINTEN_MASK >> EDMA3_CCRL_OPT_ITCINTEN_SHIFT) & (itcinten)) << EDMA3_CCRL_OPT_ITCINTEN_SHIFT) + +/** OPT-TCCHEN bit Clear */ +#define EDMA3_DRV_OPT_TCCHEN_CLR_MASK (~EDMA3_CCRL_OPT_TCCHEN_MASK) +/** OPT-TCCHEN bit Set */ +#define EDMA3_DRV_OPT_TCCHEN_SET_MASK(tcchen) (((EDMA3_CCRL_OPT_TCCHEN_MASK >> EDMA3_CCRL_OPT_TCCHEN_SHIFT) & (tcchen)) << EDMA3_CCRL_OPT_TCCHEN_SHIFT) + +/** OPT-ITCCHEN bit Clear */ +#define EDMA3_DRV_OPT_ITCCHEN_CLR_MASK (~EDMA3_CCRL_OPT_ITCCHEN_MASK) +/** OPT-ITCCHEN bit Set */ +#define EDMA3_DRV_OPT_ITCCHEN_SET_MASK(itcchen) (((EDMA3_CCRL_OPT_ITCCHEN_MASK >> EDMA3_CCRL_OPT_ITCCHEN_SHIFT) & (itcchen)) << EDMA3_CCRL_OPT_ITCCHEN_SHIFT) + +/** OPT-SAM bit Get */ +#define EDMA3_DRV_OPT_SAM_GET_MASK(mode) ((mode)&1u) +/** OPT-DAM bit Get */ +#define EDMA3_DRV_OPT_DAM_GET_MASK(mode) (((mode)&(1u<<1u))>>1u) +/** OPT-SYNCDIM bit Get */ +#define EDMA3_DRV_OPT_SYNCDIM_GET_MASK(synctype) (((synctype)&(1u<<2u))>>2u) +/** OPT-STATIC bit Get */ +#define EDMA3_DRV_OPT_STATIC_GET_MASK(en) (((en)&(1u<<3u))>>3u) +/** OPT-FWID bitfield Get */ +#define EDMA3_DRV_OPT_FWID_GET_MASK(width) (((width)&(0x7u<<8u))>>8u) +/** OPT-TCCMODE bit Get */ +#define EDMA3_DRV_OPT_TCCMODE_GET_MASK(early) (((early)&(1u<<11u))>>11u) +/** OPT-TCC bitfield Get */ +#define EDMA3_DRV_OPT_TCC_GET_MASK(tcc) (((tcc)&(0x3fu<<12u))>>12u) +/** OPT-TCINTEN bit Get */ +#define EDMA3_DRV_OPT_TCINTEN_GET_MASK(tcinten) (((tcinten)&(1u<<20u))>>20u) +/** OPT-ITCINTEN bit Get */ +#define EDMA3_DRV_OPT_ITCINTEN_GET_MASK(itcinten) (((itcinten)&(1u<<21u))>>21u) +/** OPT-TCCHEN bit Get */ +#define EDMA3_DRV_OPT_TCCHEN_GET_MASK(tcchen) (((tcchen)&(1u<<22u))>>22u) +/** OPT-ITCCHEN bit Get */ +#define EDMA3_DRV_OPT_ITCCHEN_GET_MASK(itcchen) (((itcchen)&(1u<<23u))>>23u) + +/** DMAQNUM bits Clear */ +#define EDMA3_DRV_DMAQNUM_CLR_MASK(chNum) (~(0x7u<<(((chNum)%8u)*4u))) +/** DMAQNUM bits Set */ +#define EDMA3_DRV_DMAQNUM_SET_MASK(chNum,queNum) ((0x7u & (queNum)) << (((chNum)%8u)*4u)) +/** QDMAQNUM bits Clear */ +#define EDMA3_DRV_QDMAQNUM_CLR_MASK(chNum) (~(0x7u<<((chNum)*4u))) +/** QDMAQNUM bits Set */ +#define EDMA3_DRV_QDMAQNUM_SET_MASK(chNum,queNum) ((0x7u & (queNum)) << ((chNum)*4u)) + + +/* Other Mask defines */ +/** QCHMAP-TrigWord bitfield Clear */ +#define EDMA3_DRV_QCH_TRWORD_CLR_MASK (~EDMA3_CCRL_QCHMAP_TRWORD_MASK) +/** QCHMAP-TrigWord bitfield Set */ +#define EDMA3_DRV_QCH_TRWORD_SET_MASK(paRAMId) (((EDMA3_CCRL_QCHMAP_TRWORD_MASK >> EDMA3_CCRL_QCHMAP_TRWORD_SHIFT) & (paRAMId)) << EDMA3_CCRL_QCHMAP_TRWORD_SHIFT) + + +/** Max value of ACnt */ +#define EDMA3_DRV_ACNT_MAX_VAL (0xFFFFu) +/** Max value of BCnt */ +#define EDMA3_DRV_BCNT_MAX_VAL (0xFFFFu) +/** Max value of CCnt */ +#define EDMA3_DRV_CCNT_MAX_VAL (0xFFFFu) +/** Max value of BCntReld */ +#define EDMA3_DRV_BCNTRELD_MAX_VAL (0xFFFFu) +/** Max value of SrcBIdx */ +#define EDMA3_DRV_SRCBIDX_MAX_VAL (0x7FFF) +/** Min value of SrcBIdx */ +#define EDMA3_DRV_SRCBIDX_MIN_VAL (-32768) +/** Max value of SrcCIdx */ +#define EDMA3_DRV_SRCCIDX_MAX_VAL (0x7FFF) +/** Min value of SrcCIdx */ +#define EDMA3_DRV_SRCCIDX_MIN_VAL (-32768) +/** Max value of DestBIdx */ +#define EDMA3_DRV_DSTBIDX_MAX_VAL (0x7FFF) +/** Min value of DestBIdx */ +#define EDMA3_DRV_DSTBIDX_MIN_VAL (-32768) +/** Max value of DestCIdx */ +#define EDMA3_DRV_DSTCIDX_MAX_VAL (0x7FFF) +/** Min value of DestCIdx */ +#define EDMA3_DRV_DSTCIDX_MIN_VAL (-32768) +/** Max value of Queue Priority */ +#define EDMA3_DRV_QPRIORITY_MAX_VAL (7u) +/** Min value of Queue Priority */ +#define EDMA3_DRV_QPRIORITY_MIN_VAL (0u) + + + + +/** + * \defgroup Edma3DrvIntBoundVals Boundary Values + * + * Boundary Values for Logical Channel Ranges + * + * @{ + */ +/** Max of DMA Channels */ +#define EDMA3_DRV_DMA_CH_MAX_VAL (EDMA3_MAX_DMA_CH - 1u) + +/** Min of Link Channels */ +#define EDMA3_DRV_LINK_CH_MIN_VAL (EDMA3_DRV_DMA_CH_MAX_VAL + 1u) + +/** Max of Link Channels */ +#define EDMA3_DRV_LINK_CH_MAX_VAL (EDMA3_DRV_LINK_CH_MIN_VAL + EDMA3_MAX_PARAM_SETS - 1u) + +/** Min of QDMA Channels */ +#define EDMA3_DRV_QDMA_CH_MIN_VAL (EDMA3_DRV_LINK_CH_MAX_VAL + 1u) + +/** Max of QDMA Channels */ +#define EDMA3_DRV_QDMA_CH_MAX_VAL (EDMA3_DRV_QDMA_CH_MIN_VAL + EDMA3_MAX_QDMA_CH - 1u) + +/** Max of Logical Channels */ +#define EDMA3_DRV_LOG_CH_MAX_VAL (EDMA3_DRV_QDMA_CH_MAX_VAL) + + +/* @} Edma3DrvIntBoundVals */ + + +/** + * \defgroup Edma3DrvIntObjMaint Object Maintenance + * + * Maintenance of the EDMA3 Driver Object + * + * @{ + */ +/** To maintain the state of the EDMA3 Driver object */ +typedef enum { + /** Object deleted */ + EDMA3_DRV_DELETED = 0, + /** Obect Created */ + EDMA3_DRV_CREATED = 1, + /** Object Opened */ + EDMA3_DRV_OPENED = 2, + /** Object Closed */ + EDMA3_DRV_CLOSED = 3 +} EDMA3_DRV_ObjState; + + + /** + * \brief EDMA3 Driver Object (HW Specific) Maintenance structure. + * + * Used to maintain information of the EDMA3 HW configuration + * thoughout the lifetime of the EDMA3 Driver Object, + * one for each EDMA3 hardware instance. + * + */ +typedef struct + { + /** Physical Instance ID of EDMA3 Controller */ + unsigned int phyCtrllerInstId; + + /** State information of the EDMA3 Driver object */ + EDMA3_DRV_ObjState state; + + /** Number of EDMA3 Driver instances */ + unsigned int numOpens; + + /** + * \brief Init-time Configuration structure for EDMA3 + * controller, to provide Global SoC specific Information. + * + * This configuration info can be provided by the user at run-time, + * while calling EDMA3_DRV_create(). If not provided at run-time, + * this info will be taken from the config file edma3Cfg.c. + */ + EDMA3_DRV_GblConfigParams gblCfgParams; + +} EDMA3_DRV_Object; + + +/** + * \brief EDMA3 Driver Instance Configuration Structure. + * + * Used to maintain information of the EDMA3 Driver Instances. + * One such storage exists for each instance of the EDMA3 Driver. + * There could be as many Driver Instances as there are shadow + * regions. Multiple EDMA3 Driver instances on the same shadow + * region are NOT allowed. + */ +typedef struct + { + /** Region Identification */ + EDMA3_RM_RegionId regionId; + + /** + * Whether EDMA3 driver instance is Master or not. + * Only the master instance shadow region will receive the + * EDMA3 interrupts, if enabled. + */ + unsigned short isMaster; + + /** + * EDMA3 Driver Instance (Shadow Region) specific + * init configuration. + * If NULL, static values will be taken + */ + EDMA3_DRV_InstanceInitConfig drvInstInitConfig; + + + /** EDMA3 Driver Instance specific semaphore handle */ + void *drvSemHandle; + + /** Instance wide Global Error callback parameters */ + EDMA3_RM_GblErrCallbackParams gblerrCbParams; + + /** Pointer to appropriate Shadow Register region of CC Registers */ + EDMA3_CCRL_ShadowRegs *shadowRegs; + + /** + * Pointer to the EDMA3 Driver Object, for HW specific / Global + * Information. + */ + EDMA3_DRV_Object *pDrvObjectHandle; + + /** Pointer to the Resource Manager Instance opened by the EDMA3 Driver */ + EDMA3_RM_Handle resMgrInstance; + + }EDMA3_DRV_Instance; + + +/* @} Edma3DrvIntObjMaint */ + + +/** + * \brief EDMA3 Channel-Bound resources. + * + * Used to maintain information of the EDMA3 resources + * (specifically Parameter RAM set and TCC) and the mode of triggering + * transfer (Manual, HW event driven etc) bound to the + * particular channel within EDMA3_DRV_requestChannel(). + */ +typedef struct { + /** PaRAM Set number associated with the particular channel */ + int paRAMId; + + /** TCC associated with the particular channel */ + unsigned int tcc; + + /** Mode of triggering transfer */ + EDMA3_DRV_TrigMode trigMode; + +} EDMA3_DRV_ChBoundResources; + + +/** + * \brief EDMA3 Channel Type + */ +typedef enum +{ + /** Invalid Channel */ + EDMA3_DRV_CHANNEL_TYPE_NONE, + + /** DMA Channel */ + EDMA3_DRV_CHANNEL_TYPE_DMA = 1, + + /** QDMA Channel */ + EDMA3_DRV_CHANNEL_TYPE_QDMA = 2, + + /** LINK Channel */ + EDMA3_DRV_CHANNEL_TYPE_LINK = 3 + +} EDMA3_DRV_ChannelType; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +/* @} Edma3DrvInt */ +#endif /* _EDMA3_H_ */ diff --git a/packages/ti/sdo/edma3/drv/src/edma3_drv_adv.c b/packages/ti/sdo/edma3/drv/src/edma3_drv_adv.c new file mode 100644 index 0000000..b2628b3 --- /dev/null +++ b/packages/ti/sdo/edma3/drv/src/edma3_drv_adv.c @@ -0,0 +1,2398 @@ +/******************************************************************************* +**+--------------------------------------------------------------------------+** +**| **** |** +**| **** |** +**| ******o*** |** +**| ********_///_**** |** +**| ***** /_//_/ **** |** +**| ** ** (__/ **** |** +**| ********* |** +**| **** |** +**| *** |** +**| |** +**| Copyright (c) 1998-2006 Texas Instruments Incorporated |** +**| ALL RIGHTS RESERVED |** +**| |** +**| Permission is hereby granted to licensees of Texas Instruments |** +**| Incorporated (TI) products to use this computer program for the sole |** +**| purpose of implementing a licensee product based on TI products. |** +**| No other rights to reproduce, use, or disseminate this computer |** +**| program, whether in part or in whole, are granted. |** +**| |** +**| TI makes no representation or warranties with respect to the |** +**| performance of this computer program, and specifically disclaims |** +**| any responsibility for any damages, special or consequential, |** +**| connected with the use of this program. |** +**| |** +**+--------------------------------------------------------------------------+** +*******************************************************************************/ + +/** +* \file edma3_drv_adv.c +* +* \brief EDMA3 Driver Advanced Interface Implementation +* This file contains advanced-level EDMA3 Driver APIs which are required +* to: +* a) Link and chain two channels. +* b) Set/get the whole PaRAM Set in one shot. +* c) Set/get each individual field of the PaRAM Set. +* d) Poll mode APIs. +* e) IOCTL interface. +* These APIs are provided to have complete control on the EDMA3 hardware and +* normally advanced users are expected to use them for their specific use-cases. +* +* @author: PSP Team, TII +* +*/ + + +/* EDMa3 Driver Internal Header Files */ +#include +/* Resource Manager Internal Header Files */ +#include + +/* Instrumentation Header File */ +#ifdef EDMA3_INSTRUMENTATION_ENABLED +#include +#endif + +/* Externel Variables */ +/*---------------------------------------------------------------------------*/ +/** + * Maximum Resource Manager Instances supported by the EDMA3 Package. + */ +extern const unsigned int EDMA3_MAX_RM_INSTANCES; + + +/** + * \brief EDMA3 Resource Manager Objects, tied to each EDMA3 HW Controller. + * + * Typically one RM object will cater to one EDMA3 HW controller + * and will have all the global config information. + */ +extern EDMA3_RM_Obj resMgrObj[EDMA3_MAX_EDMA3_INSTANCES]; + + +/** + * \brief Region Specific Configuration structure for + * EDMA3 controller, to provide region specific Information. + * + * This configuration info can also be provided by the user at run-time, + * while calling EDMA3_RM_open (). If not provided at run-time, + * this info will be taken from the config file "edma3__cfg.c", + * for the specified platform. + */ +extern EDMA3_RM_InstanceInitConfig *ptrInitCfgArray; + + +/** + * Handles of EDMA3 Resource Manager Instances. + * + * Used to maintain information of the EDMA3 RM Instances + * for each HW controller. + * There could be a maximum of EDMA3_MAX_RM_INSTANCES instances per + * EDMA3 HW. + */ +extern EDMA3_RM_Instance *ptrRMIArray; + +/** Local MemSet function */ +extern void edma3MemSet(void *dst, unsigned char data, unsigned int len); +/** Local MemCpy function */ +extern void edma3MemCpy(void *dst, const void *src, unsigned int len); + +/** + * \brief EDMA3 Driver Objects, tied to each EDMA3 HW Controller. + * + * Typically one object will cater to one EDMA3 HW controller + * and will have all regions' (ARM, DSP etc) specific config information. + */ +extern EDMA3_DRV_Object drvObj [EDMA3_MAX_EDMA3_INSTANCES]; + + +/** + * Handles of EDMA3 Driver Instances. + * + * Used to maintain information of the EDMA3 Driver Instances for + * each region, for each HW controller. + * There could be as many Driver Instances as there are shadow + * regions. Multiple EDMA3 Driver instances on the same shadow + * region are NOT allowed. + */ +extern EDMA3_DRV_Instance drvInstance [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS]; + +/** + * \brief Resources bound to a Channel + * + * When a request for a channel is made, the resources PaRAM Set and TCC + * get bound to that channel. This information is needed internally by the + * driver when a request is made to free the channel (Since it is the + * responsibility of the driver to free up the channel-associated resources + * from the Resource Manager layer). + */ +extern EDMA3_DRV_ChBoundResources edma3DrvChBoundRes [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_LOGICAL_CH]; + + +/** + * \brief Link two logical channels. + * + * This API is used to link two previously allocated logical (DMA/QDMA/Link) + * channels. + * + * It sets the Link field of the PaRAM set associated with first logical + * channel (lCh1) to point it to the PaRAM set associated with second logical + * channel (lCh2). + * + * It also sets the TCC field of PaRAM set associated with second logical + * channel to the same as that of the first logical channel. + * + * After linking the channels, user should not update any PaRAM Set of the + * channel. + * + * \param hEdma [IN] Handle to the EDMA Driver Instance. + * \param lCh1 [IN] Logical Channel to which particular channel + * will be linked. + * \param lCh2 [IN] Logical Channel which needs to be linked to + * the first channel. + * After the transfer based on the PaRAM set + * of lCh1 is over, the PaRAM set of lCh2 will + * be copied to the PaRAM set of lCh1 and + * transfer will resume. + * For DMA channels, another sync event is + * required to initiate the transfer on the + * Link channel. + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant for unique lCh1 & lCh2 values. It is + * non-re-entrant for same lCh1 & lCh2 values. + */ +EDMA3_DRV_Result EDMA3_DRV_linkChannel (EDMA3_DRV_Handle hEdma, + unsigned int lCh1, unsigned int lCh2) + { + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + EDMA3_DRV_Instance *drvInst = NULL; + EDMA3_DRV_Object *drvObject = NULL; + unsigned int linkBcntReld; + int paRAM1Id = 0; + int paRAM2Id = 0; + unsigned int oldTccVal = 0; + unsigned int optVal = 0; + unsigned int newOptVal = 0; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if (((lCh1 > EDMA3_DRV_LOG_CH_MAX_VAL) + || (lCh2 > EDMA3_DRV_LOG_CH_MAX_VAL)) + || (hEdma == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_DRV_SOK == result) + { + drvInst = (EDMA3_DRV_Instance *)hEdma; + drvObject = drvInst->pDrvObjectHandle; + + if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + paRAM1Id = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh1].paRAMId; + paRAM2Id = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh2].paRAMId; + globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs); + + if ((paRAM1Id < 0) || (paRAM1Id >= drvObject->gblCfgParams.numPaRAMSets)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + + if ((paRAM2Id < 0) || (paRAM2Id >= drvObject->gblCfgParams.numPaRAMSets)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + + if (result == EDMA3_DRV_SOK) + { + /* Get the Link-bcntReload PaRAM set entry */ + linkBcntReld = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAM1Id].OPT) + + (unsigned int)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD)); + linkBcntReld &= 0xFFFF0000u; + /* Update the Link field with lch2 PaRAM set */ + linkBcntReld |= (0xFFFFu & (unsigned int)(&(globalRegs->PARAMENTRY [paRAM2Id].OPT))); + + /* Store it back */ + *((&globalRegs->PARAMENTRY[paRAM1Id].OPT) + + (unsigned int)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD) = linkBcntReld; + + /* + * Set the TCC field of PaRAM set associated with lch2 to + * the same as that of lch1. + */ + /* for channel 1 */ + optVal = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAM1Id].OPT)); + oldTccVal = EDMA3_DRV_OPT_TCC_GET_MASK(optVal); + + /* for channel 2 */ + optVal = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAM2Id].OPT)); + newOptVal = (optVal & EDMA3_DRV_OPT_TCC_CLR_MASK) + | + (EDMA3_DRV_OPT_TCC_SET_MASK(oldTccVal)); + *(&globalRegs->PARAMENTRY[paRAM2Id].OPT) = newOptVal; + } + } + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + + +/** + * \brief Unlink the channel from the earlier linked logical channel. + * + * This function breaks the link between the specified + * channel and the earlier linked logical channel + * by clearing the Link Address field. + * + * \param hEdma [IN] Handle to the EDMA Driver Instance. + * \param lCh [IN] Channel for which linking has to be removed + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant for unique lCh values. It is non- + * re-entrant for same lCh value. + */ +EDMA3_DRV_Result EDMA3_DRV_unlinkChannel (EDMA3_DRV_Handle hEdma, unsigned int lCh) + { + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + unsigned int linkBcntReld; + int paRAMId = 0; + EDMA3_DRV_Instance *drvInst = NULL; + EDMA3_DRV_Object *drvObject = NULL; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if ((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_DRV_SOK == result) + { + drvInst = (EDMA3_DRV_Instance *)hEdma; + drvObject = drvInst->pDrvObjectHandle; + + if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId; + globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs); + + if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + + if (result == EDMA3_DRV_SOK) + { + /* Get the Link-bcntReload PaRAM set entry */ + linkBcntReld = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + + (unsigned int)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD)); + + /* Remove any linking */ + linkBcntReld |= 0xFFFFu; + + /* Store it back */ + *((&globalRegs->PARAMENTRY[paRAMId].OPT) + + (unsigned int)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD) = linkBcntReld; + } + } + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + +/** + * \brief Chain the two specified channels. + * + * This API is used to chain two previously allocated logical (DMA/QDMA) + * channels. + * + * Chaining is different from Linking. The EDMA3 link feature reloads the + * current channel parameter set with the linked parameter set. The EDMA3 + * chaining feature does not modify or update any channel parameter set; + * it provides a synchronization event to the chained channel. + * + * \param hEdma [IN] Handle to the EDMA Driver Instance. + * + * \param lCh1 [IN] Channel to which particular channel + * will be chained. + * \param lCh2 [IN] Channel which needs to be chained to + * the first channel. + * \param chainOptions [IN] Options such as intermediate interrupts + * are required or not, intermediate/final + * chaining is enabled or not etc. + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant for unique lCh1 & lCh2 values. It is + * non-re-entrant for same lCh1 & lCh2 values. + */ +EDMA3_DRV_Result EDMA3_DRV_chainChannel (EDMA3_DRV_Handle hEdma, + unsigned int lCh1, + unsigned int lCh2, + const EDMA3_DRV_ChainOptions *chainOptions) + { + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + unsigned int opt = 0x0; + EDMA3_DRV_Instance *drvInst = NULL; + EDMA3_DRV_Object *drvObject = NULL; + int paRAMId = 0; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if (((lCh1 > EDMA3_DRV_LOG_CH_MAX_VAL) || (lCh2 > EDMA3_DRV_LOG_CH_MAX_VAL)) + || (hEdma == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + + if (chainOptions == NULL) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + if (result == EDMA3_DRV_SOK) + { + drvInst = (EDMA3_DRV_Instance *)hEdma; + drvObject = drvInst->pDrvObjectHandle; + + if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + } + + if (result == EDMA3_DRV_SOK) + { + paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh1].paRAMId; + globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs); + + if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + } + + if (result == EDMA3_DRV_SOK) + { + opt = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAMId].OPT)); + + /* set Transfer complete chaining */ + if (chainOptions->tcchEn == EDMA3_DRV_TCCHEN_EN) + { + opt |= EDMA3_DRV_OPT_TCCHEN_SET_MASK(1u); + } + else + { + opt &= EDMA3_DRV_OPT_TCCHEN_CLR_MASK; + } + + /*set Intermediate transfer completion chaining */ + if (chainOptions->itcchEn == EDMA3_DRV_ITCCHEN_EN) + { + opt |= EDMA3_DRV_OPT_ITCCHEN_SET_MASK(1u); + } + else + { + opt &= EDMA3_DRV_OPT_ITCCHEN_CLR_MASK; + } + + /*set Transfer complete interrupt */ + if (chainOptions->tcintEn == EDMA3_DRV_TCINTEN_EN) + { + opt |= EDMA3_DRV_OPT_TCINTEN_SET_MASK(1u); + } + else + { + opt &= EDMA3_DRV_OPT_TCINTEN_CLR_MASK; + } + + /*set Intermediate transfer completion interrupt */ + if (chainOptions->itcintEn == EDMA3_DRV_ITCINTEN_EN) + { + opt |= EDMA3_DRV_OPT_ITCINTEN_SET_MASK(1u); + } + else + { + opt &= EDMA3_DRV_OPT_ITCINTEN_CLR_MASK; + } + + opt &= EDMA3_DRV_OPT_TCC_CLR_MASK; + opt |= EDMA3_DRV_OPT_TCC_SET_MASK(lCh2); + + *(&globalRegs->PARAMENTRY[paRAMId].OPT) = opt; + + /* Set the trigger mode of lch2 as the same as of lch1 */ + edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh2].trigMode = + edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh1].trigMode; + } + + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + + +/** + * \brief Unchain the two channels. + * + * \param hEdma [IN] Handle to the EDMA Driver Instance. + * \param lCh [IN] Channel whose chaining with the other + * channel has to be removed. + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant for unique lCh values. It is non- + * re-entrant for same lCh value. + */ +EDMA3_DRV_Result EDMA3_DRV_unchainChannel (EDMA3_DRV_Handle hEdma, + unsigned int lCh) + { + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + unsigned int opt; + EDMA3_DRV_Instance *drvInst = NULL; + EDMA3_DRV_Object *drvObject = NULL; + int paRAMId = 0; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if ((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + if (result == EDMA3_DRV_SOK) + { + drvInst = (EDMA3_DRV_Instance *)hEdma; + drvObject = drvInst->pDrvObjectHandle; + + if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + } + + if (result == EDMA3_DRV_SOK) + { + paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId; + globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs); + + if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + } + + if (result == EDMA3_DRV_SOK) + { + opt = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAMId].OPT)); + + /* Reset TCCHEN */ + opt &= EDMA3_DRV_OPT_TCCHEN_CLR_MASK; + /* Reset ITCCHEN */ + opt &= EDMA3_DRV_OPT_ITCCHEN_CLR_MASK; + + *(&globalRegs->PARAMENTRY[paRAMId].OPT) = opt; + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + +/** + * \brief Assign a Trigger Word to the specified QDMA channel + * + * This API sets the Trigger word for the specific QDMA channel in the QCHMAP + * Register. Default QDMA trigger word is CCNT. + * + * \param hEdma [IN] Handle to the EDMA Instance object + * \param lCh [IN] QDMA Channel which needs to be assigned + * the Trigger Word + * \param trigWord [IN] The Trigger Word for the QDMA channel. + * Trigger Word is the word in the PaRAM + * Register Set which, when written to by CPU, + * will start the QDMA transfer automatically. + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant for unique lCh values. It is non- + * re-entrant for same lCh value. + */ +EDMA3_DRV_Result EDMA3_DRV_setQdmaTrigWord (EDMA3_DRV_Handle hEdma, + unsigned int lCh, + EDMA3_RM_QdmaTrigWord trigWord) + { + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + EDMA3_DRV_Instance *drvInst = NULL; + EDMA3_DRV_Object *drvObject = NULL; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if((hEdma == NULL) + || (((lCh < EDMA3_DRV_QDMA_CH_MIN_VAL) + || (lCh > EDMA3_DRV_QDMA_CH_MAX_VAL)) + || ((trigWord < EDMA3_RM_QDMA_TRIG_OPT) + || (trigWord > EDMA3_RM_QDMA_TRIG_CCNT)))) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_DRV_SOK == result) + { + drvInst = (EDMA3_DRV_Instance *)hEdma; + drvObject = drvInst->pDrvObjectHandle; + + if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs); + + globalRegs->QCHMAP[lCh -EDMA3_DRV_QDMA_CH_MIN_VAL] &= EDMA3_DRV_QCH_TRWORD_CLR_MASK; + globalRegs->QCHMAP[lCh -EDMA3_DRV_QDMA_CH_MIN_VAL] |= EDMA3_DRV_QCH_TRWORD_SET_MASK(trigWord); + } + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + +/** + * \brief Copy the user specified PaRAM Set onto the PaRAM Set + * associated with the logical channel (DMA/QDMA/Link). + * + * This API takes a PaRAM Set as input and copies it onto the actual PaRAM Set + * associated with the logical channel. OPT field of the PaRAM Set is written + * first and the CCNT field is written last. + * + * Caution: It should be used carefully when programming the QDMA channels whose + * trigger words are not CCNT field. + * + * \param hEdma [IN] Handle to the EDMA Instance object + * \param lCh [IN] Logical Channel for which new PaRAM set is + * specified + * \param newPaRAM [IN] Parameter RAM set to be copied onto existing PaRAM + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant for unique lCh values. It is non- + * re-entrant for same lCh value. + */ +EDMA3_DRV_Result EDMA3_DRV_setPaRAM (EDMA3_DRV_Handle hEdma, + unsigned int lCh, + const EDMA3_DRV_PaRAMRegs *newPaRAM) + { + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + EDMA3_DRV_Instance *drvInst = NULL; + EDMA3_DRV_Object *drvObject = NULL; + int paRAMId = 0; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if (((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL)) + || (newPaRAM == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + if (result == EDMA3_DRV_SOK) + { + drvInst = (EDMA3_DRV_Instance *)hEdma; + drvObject = drvInst->pDrvObjectHandle; + + if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + } + + if (result == EDMA3_DRV_SOK) + { + globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs); + paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId; + + if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + } + + if (result == EDMA3_DRV_SOK) + { + edma3MemCpy ((void *)(&(globalRegs->PARAMENTRY[paRAMId].OPT)), + (const void *)newPaRAM, + sizeof(EDMA3_CCRL_ParamentryRegs)); + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + +/** + * \brief Retrieve existing PaRAM set associated with specified logical + * channel (DMA/QDMA/Link). + * + * \param hEdma [IN] Handle to the EDMA Instance object + * \param lCh [IN] Logical Channel whose PaRAM set is + * requested + * \param currPaRAM [IN/OUT] User gets the existing PaRAM here + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant. + */ +EDMA3_DRV_Result EDMA3_DRV_getPaRAM (EDMA3_DRV_Handle hEdma, + unsigned int lCh, + EDMA3_DRV_PaRAMRegs *currPaRAM) + { + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + EDMA3_DRV_Instance *drvInst = NULL; + EDMA3_DRV_Object *drvObject = NULL; + int paRAMId = 0; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if (((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL)) + || (currPaRAM == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + if (result == EDMA3_DRV_SOK) + { + drvInst = (EDMA3_DRV_Instance *)hEdma; + drvObject = drvInst->pDrvObjectHandle; + + if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + } + + if (result == EDMA3_DRV_SOK) + { + globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs); + paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId; + + if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + } + + if (result == EDMA3_DRV_SOK) + { + edma3MemCpy ((void *)currPaRAM , + (const void *)(&(globalRegs->PARAMENTRY [paRAMId].OPT)), + sizeof(EDMA3_CCRL_ParamentryRegs)); + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + +/** + * \brief Set a particular PaRAM set entry of the specified PaRAM set + * + * + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param lCh [IN] Logical Channel bound to the Parameter RAM set + * whose specified field needs to be set + * \param paRAMEntry [IN] Specify the PaRAM set entry which needs + * to be set + * \param newPaRAMEntryVal [IN] The new field setting + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This API should be used while setting the PaRAM set entry + * for QDMA channels. If EDMA3_DRV_setPaRAMField () used, + * it will trigger the QDMA channel before complete + * PaRAM set entry is written. For DMA channels, no such + * constraint is there. + * + * This function is re-entrant for unique lCh values. It is non- + * re-entrant for same lCh value. + */ +EDMA3_DRV_Result EDMA3_DRV_setPaRAMEntry (EDMA3_DRV_Handle hEdma, + unsigned int lCh, + EDMA3_DRV_PaRAMEntry paRAMEntry, + unsigned int newPaRAMEntryVal) + { + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + EDMA3_DRV_Instance *drvInst = NULL; + EDMA3_DRV_Object *drvObject = NULL; + int paRAMId = 0; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if(((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL)) + || ((paRAMEntry < EDMA3_DRV_PARAM_ENTRY_OPT) + || (paRAMEntry > EDMA3_DRV_PARAM_ENTRY_CCNT))) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_DRV_SOK == result) + { + drvInst = (EDMA3_DRV_Instance *)hEdma; + drvObject = drvInst->pDrvObjectHandle; + + if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId; + globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs); + + if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + *((&globalRegs->PARAMENTRY[paRAMId].OPT) + (unsigned int)paRAMEntry) = newPaRAMEntryVal; + } + } + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + +/** + * \brief Get a particular PaRAM set entry of the specified PaRAM set + * + * + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param lCh [IN] Logical Channel bound to the Parameter RAM set + * whose specified field value is needed + * \param paRAMEntry [IN] Specify the PaRAM set entry which needs + * to be obtained + * \param paRAMEntryVal [IN/OUT] The value of the field is returned here + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant. + */ +EDMA3_DRV_Result EDMA3_DRV_getPaRAMEntry (EDMA3_DRV_Handle hEdma, + unsigned int lCh, + EDMA3_DRV_PaRAMEntry paRAMEntry, + unsigned int *paRAMEntryVal) + { + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + EDMA3_DRV_Instance *drvInst = NULL; + EDMA3_DRV_Object *drvObject = NULL; + int paRAMId = 0; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if(((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) + || ((hEdma == NULL) || (paRAMEntryVal == NULL))) + || ((paRAMEntry < EDMA3_DRV_PARAM_ENTRY_OPT) + || (paRAMEntry > EDMA3_DRV_PARAM_ENTRY_CCNT))) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_DRV_SOK == result) + { + drvInst = (EDMA3_DRV_Instance *)hEdma; + drvObject = drvInst->pDrvObjectHandle; + + if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId; + globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs); + + + if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + *paRAMEntryVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned int)paRAMEntry)); + } + } + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + +/** + * \brief Set a particular PaRAM set field of the specified PaRAM set + * + * + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param lCh [IN] Logical Channel bound to the PaRAM set + * whose specified field needs to be set + * \param paRAMField [IN] Specify the PaRAM set field which needs + * to be set + * \param newPaRAMFieldVal [IN] The new field setting + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This API CANNOT be used while setting the PaRAM set + * field for QDMA channels. It can trigger the QDMA channel before + * complete PaRAM set ENTRY (4-bytes field) is written (for eg, as + * soon one sets the ACNT field for QDMA channel, transfer is started, + * before one modifies the BCNT field). For DMA channels, no such + * constraint is there. + * + * This function is re-entrant for unique lCh values. It is non- + * re-entrant for same lCh value. + */ +EDMA3_DRV_Result EDMA3_DRV_setPaRAMField (EDMA3_DRV_Handle hEdma, + unsigned int lCh, + EDMA3_DRV_PaRAMField paRAMField, + unsigned int newPaRAMFieldVal) + { + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + EDMA3_DRV_Instance *drvInst = NULL; + EDMA3_DRV_Object *drvObject = NULL; + unsigned int paramEntryVal = 0; + int paRAMId = 0; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + /* + * THIS API IS NOT ALLOWED FOR QDMA CHANNELS. + * Reason being setting one PaRAM field might trigger the + * transfer if the word written happends to be the trigger + * word. One should use EDMA3_DRV_setPaRAMEntry () + * API instead to write the whole 32 bit word. + */ + if ((lCh >= EDMA3_DRV_QDMA_CHANNEL_0) && (lCh <= EDMA3_DRV_QDMA_CHANNEL_7)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + + if(lCh > EDMA3_DRV_LOG_CH_MAX_VAL) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + + if((hEdma == NULL) + || ((paRAMField < EDMA3_DRV_PARAM_FIELD_OPT) + || (paRAMField > EDMA3_DRV_PARAM_FIELD_CCNT))) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + if (result == EDMA3_DRV_SOK) + { + drvInst = (EDMA3_DRV_Instance *)hEdma; + drvObject = drvInst->pDrvObjectHandle; + + if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + } + + if (result == EDMA3_DRV_SOK) + { + paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId; + globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs); + + if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + } + + + if (result == EDMA3_DRV_SOK) + { + switch (paRAMField) + { + case EDMA3_DRV_PARAM_FIELD_OPT: + *((&globalRegs->PARAMENTRY[paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_OPT) = newPaRAMFieldVal; + break; + + case EDMA3_DRV_PARAM_FIELD_SRCADDR: + *((&globalRegs->PARAMENTRY[paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_SRC) = newPaRAMFieldVal; + break; + + case EDMA3_DRV_PARAM_FIELD_ACNT: + paramEntryVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT)); + paramEntryVal &= 0xFFFF0000u; + newPaRAMFieldVal &= 0x0000FFFFu; + paramEntryVal |= newPaRAMFieldVal; + *((&globalRegs->PARAMENTRY[paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT) = paramEntryVal; + break; + + case EDMA3_DRV_PARAM_FIELD_BCNT: + paramEntryVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT)); + paramEntryVal &= 0x0000FFFFu; + newPaRAMFieldVal <<= 0x10u; + paramEntryVal |= newPaRAMFieldVal; + *((&globalRegs->PARAMENTRY[paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT) = paramEntryVal; + break; + + case EDMA3_DRV_PARAM_FIELD_DESTADDR: + *((&globalRegs->PARAMENTRY[paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_DST) = newPaRAMFieldVal; + break; + + case EDMA3_DRV_PARAM_FIELD_SRCBIDX: + paramEntryVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX)); + paramEntryVal &= 0xFFFF0000u; + newPaRAMFieldVal &= 0x0000FFFFu; + paramEntryVal |= newPaRAMFieldVal; + *((&globalRegs->PARAMENTRY[paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX) = paramEntryVal; + break; + + case EDMA3_DRV_PARAM_FIELD_DESTBIDX: + paramEntryVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX)); + paramEntryVal &= 0x0000FFFFu; + newPaRAMFieldVal <<= 0x10u; + paramEntryVal |= newPaRAMFieldVal; + *((&globalRegs->PARAMENTRY[paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX) = paramEntryVal; + break; + + case EDMA3_DRV_PARAM_FIELD_LINKADDR: + paramEntryVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD)); + paramEntryVal &= 0xFFFF0000u; + newPaRAMFieldVal &= 0x0000FFFFu; + paramEntryVal |= newPaRAMFieldVal; + *((&globalRegs->PARAMENTRY[paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD) = paramEntryVal; + break; + + case EDMA3_DRV_PARAM_FIELD_BCNTRELOAD: + paramEntryVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD)); + paramEntryVal &= 0x0000FFFFu; + newPaRAMFieldVal <<= 0x10u; + paramEntryVal |= newPaRAMFieldVal; + *((&globalRegs->PARAMENTRY[paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD) = paramEntryVal; + break; + + case EDMA3_DRV_PARAM_FIELD_SRCCIDX: + paramEntryVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX)); + paramEntryVal &= 0xFFFF0000u; + newPaRAMFieldVal &= 0x0000FFFFu; + paramEntryVal |= newPaRAMFieldVal; + *((&globalRegs->PARAMENTRY[paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX) = paramEntryVal; + break; + + case EDMA3_DRV_PARAM_FIELD_DESTCIDX: + paramEntryVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX)); + paramEntryVal &= 0x0000FFFFu; + newPaRAMFieldVal <<= 0x10u; + paramEntryVal |= newPaRAMFieldVal; + *((&globalRegs->PARAMENTRY[paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX) = paramEntryVal; + break; + + case EDMA3_DRV_PARAM_FIELD_CCNT: + newPaRAMFieldVal &= 0x0000FFFFu; + *((&globalRegs->PARAMENTRY[paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_CCNT) = newPaRAMFieldVal; + break; + + default: + break; + } + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + +/** + * \brief Get a particular PaRAM set field of the specified PaRAM set + * + * + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param lCh [IN] Logical Channel bound to the PaRAM set + * whose specified field value is needed + * \param paRAMField [IN] Specify the PaRAM set field which needs + * to be obtained + * \param currPaRAMFieldVal [IN/OUT] The value of the field is returned here + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant. + */ +EDMA3_DRV_Result EDMA3_DRV_getPaRAMField (EDMA3_DRV_Handle hEdma, + unsigned int lCh, + EDMA3_DRV_PaRAMField paRAMField, + unsigned int *currPaRAMFieldVal) + { + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + EDMA3_DRV_Instance *drvInst = NULL; + EDMA3_DRV_Object *drvObject = NULL; + unsigned int paramEntryVal = 0; + int paRAMId = 0; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if(((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) + || ((hEdma == NULL) || (currPaRAMFieldVal == NULL))) + || ((paRAMField < EDMA3_DRV_PARAM_FIELD_OPT) + || (paRAMField > EDMA3_DRV_PARAM_FIELD_CCNT))) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + if (result == EDMA3_DRV_SOK) + { + drvInst = (EDMA3_DRV_Instance *)hEdma; + drvObject = drvInst->pDrvObjectHandle; + + if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + } + + if (result == EDMA3_DRV_SOK) + { + paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId; + globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs); + + if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + } + + if (result == EDMA3_DRV_SOK) + { + switch (paRAMField) + { + case EDMA3_DRV_PARAM_FIELD_OPT: + *currPaRAMFieldVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_OPT)); + break; + + case EDMA3_DRV_PARAM_FIELD_SRCADDR: + *currPaRAMFieldVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_SRC)); + break; + + case EDMA3_DRV_PARAM_FIELD_ACNT: + paramEntryVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT)); + paramEntryVal &= 0x0000FFFFu; + *currPaRAMFieldVal = paramEntryVal; + break; + + case EDMA3_DRV_PARAM_FIELD_BCNT: + paramEntryVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT)); + paramEntryVal = paramEntryVal >> 0x10u; + *currPaRAMFieldVal = paramEntryVal; + break; + + case EDMA3_DRV_PARAM_FIELD_DESTADDR: + *currPaRAMFieldVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_DST)); + break; + + case EDMA3_DRV_PARAM_FIELD_SRCBIDX: + paramEntryVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX)); + paramEntryVal &= 0x0000FFFFu; + *currPaRAMFieldVal = paramEntryVal; + break; + + case EDMA3_DRV_PARAM_FIELD_DESTBIDX: + paramEntryVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX)); + paramEntryVal = paramEntryVal >> 0x10u; + *currPaRAMFieldVal = paramEntryVal; + break; + + case EDMA3_DRV_PARAM_FIELD_LINKADDR: + paramEntryVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD)); + paramEntryVal &= 0x0000FFFFu; + *currPaRAMFieldVal = paramEntryVal; + break; + + case EDMA3_DRV_PARAM_FIELD_BCNTRELOAD: + paramEntryVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD)); + paramEntryVal = paramEntryVal >> 0x10u; + *currPaRAMFieldVal = paramEntryVal; + break; + + case EDMA3_DRV_PARAM_FIELD_SRCCIDX: + paramEntryVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX)); + paramEntryVal &= 0x0000FFFFu; + *currPaRAMFieldVal = paramEntryVal; + break; + + case EDMA3_DRV_PARAM_FIELD_DESTCIDX: + paramEntryVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX)); + paramEntryVal = paramEntryVal >> 0x10u; + *currPaRAMFieldVal = paramEntryVal; + break; + + case EDMA3_DRV_PARAM_FIELD_CCNT: + *currPaRAMFieldVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_CCNT)); + break; + + default: + break; + } + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + +/** + * \brief Sets EDMA TC priority + * + * User can program the priority of the Event Queues at a system-wide level. + * This means that the user can set the priority of an IO initiated by either + * of the TCs (Transfer Ctrllers) relative to IO initiated by the other bus + * masters on the device (ARM, DSP, USB, etc) + * + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param evtQPriObj [IN] Priority of the Event Queues + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function disables the global interrupts while modifying + * the global CC Registers, to make it re-entrant. + */ +EDMA3_DRV_Result EDMA3_DRV_setEvtQPriority (EDMA3_DRV_Handle hEdma, + const EDMA3_DRV_EvtQuePriority *evtQPriObj) + { + unsigned int intState; + EDMA3_DRV_Instance *drvInst = NULL; + EDMA3_DRV_Object *drvObject = NULL; + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + unsigned int evtQNum = 0; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if ((hEdma == NULL) || (evtQPriObj== NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_DRV_SOK == result) + { + drvInst = (EDMA3_DRV_Instance *)hEdma; + drvObject = drvInst->pDrvObjectHandle; + + if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs); + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + /* check event queue priority first*/ + while (evtQNum < drvObject->gblCfgParams.numEvtQueue) + { + if (evtQPriObj->evtQPri[evtQNum] > EDMA3_DRV_QPRIORITY_MAX_VAL) + { + result = EDMA3_DRV_E_INVALID_PARAM; + break; + } + evtQNum++; + } +#endif + + if (result == EDMA3_DRV_SOK) + { + edma3OsProtectEntry (EDMA3_OS_PROTECT_INTERRUPT, &intState); + + /* Set TC Priority among system-wide bus-masters and Queue Watermark Level */ + evtQNum = 0; + while (evtQNum < drvObject->gblCfgParams.numEvtQueue) + { + globalRegs->QUEPRI = globalRegs->QUEPRI & (unsigned int)EDMA3_RM_QUEPRI_CLR_MASK(evtQNum); + globalRegs->QUEPRI |= EDMA3_RM_QUEPRI_SET_MASK(evtQNum, evtQPriObj->evtQPri[evtQNum]); + + evtQNum++; + } + + edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT, intState); + } + } + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + + +/** + * \brief Associate Channel to Event Queue + * + * + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param channelId [IN] Logical Channel to which the Event + * Queue is to be mapped + * \param eventQ [IN] The Event Queue which is to be mapped + * to the DMA channel + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note There should not be any data transfer going on + * while setting the mapping. Results could be unpredictable. + * + * This function disables the global interrupts while modifying + * the global CC Registers, to make it re-entrant. + */ +EDMA3_DRV_Result EDMA3_DRV_mapChToEvtQ(EDMA3_DRV_Handle hEdma, + unsigned int channelId, + EDMA3_RM_EventQueue eventQ) + { + EDMA3_DRV_Instance *drvInst = NULL; + EDMA3_DRV_Object *drvObject = NULL; + unsigned int intState; + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if (hEdma == NULL) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + if (result == EDMA3_DRV_SOK) + { + drvInst = (EDMA3_DRV_Instance *)hEdma; + drvObject = drvInst->pDrvObjectHandle; + + if (drvObject == NULL) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + } + + if (result == EDMA3_DRV_SOK) + { + if (drvObject->gblCfgParams.globalRegs == NULL) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + } + + if (result == EDMA3_DRV_SOK) + { + globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs); + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + /* Check the event queue */ + if (eventQ >= drvObject->gblCfgParams.numEvtQueue) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + } + + if (result == EDMA3_DRV_SOK) + { + if (channelId <= EDMA3_DRV_DMA_CH_MAX_VAL) + { + /* DMA channel */ + edma3OsProtectEntry (EDMA3_OS_PROTECT_INTERRUPT, &intState); + + globalRegs->DMAQNUM[channelId >> 3u] &= + EDMA3_DRV_DMAQNUM_CLR_MASK(channelId); + globalRegs->DMAQNUM[channelId >> 3u] |= + EDMA3_DRV_DMAQNUM_SET_MASK(channelId, eventQ); + + edma3OsProtectExit(EDMA3_OS_PROTECT_INTERRUPT,intState); + } + else + { + if ((channelId >= EDMA3_DRV_QDMA_CH_MIN_VAL) + && (channelId <= EDMA3_DRV_QDMA_CH_MAX_VAL)) + { + /* QDMA channel */ + edma3OsProtectEntry (EDMA3_OS_PROTECT_INTERRUPT, &intState); + + globalRegs->QDMAQNUM &= + EDMA3_DRV_QDMAQNUM_CLR_MASK(channelId-EDMA3_DRV_QDMA_CH_MIN_VAL); + globalRegs->QDMAQNUM |= + EDMA3_DRV_QDMAQNUM_SET_MASK(channelId-EDMA3_DRV_QDMA_CH_MIN_VAL, eventQ); + + edma3OsProtectExit(EDMA3_OS_PROTECT_INTERRUPT,intState); + } + else + { + /* API valid for DMA/QDMA channel only, return error... */ + result = EDMA3_DRV_E_INVALID_PARAM; + } + } + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + +/** + * \brief Get the Event Queue mapped to the specified DMA/QDMA channel. + * + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param channelId [IN] Logical Channel whose associated + * Event Queue is needed + * \param mappedEvtQ [IN/OUT] The Event Queue which is mapped + * to the DMA/QDMA channel + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant. + */ +EDMA3_DRV_Result EDMA3_DRV_getMapChToEvtQ (EDMA3_DRV_Handle hEdma, + unsigned int channelId, + unsigned int *mappedEvtQ) + { + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + EDMA3_DRV_Instance *drvInst = NULL; + EDMA3_DRV_Object *drvObject = NULL; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if (((hEdma == NULL) || (mappedEvtQ == NULL)) + || (channelId > EDMA3_DRV_LOG_CH_MAX_VAL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_DRV_SOK == result) + { + drvInst = (EDMA3_DRV_Instance *)hEdma; + drvObject = drvInst->pDrvObjectHandle; + + if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs); + + if (channelId <= EDMA3_DRV_DMA_CH_MAX_VAL) + { + *mappedEvtQ = ((globalRegs->DMAQNUM[channelId >> 3u]) + & (~(EDMA3_DRV_DMAQNUM_CLR_MASK(channelId)))) + >> ((channelId%8u)*4u); + } + else + { + if ((channelId >= EDMA3_DRV_QDMA_CH_MIN_VAL) + &&(channelId <= EDMA3_DRV_QDMA_CH_MAX_VAL)) + { + *mappedEvtQ = ((globalRegs->QDMAQNUM) + & (~(EDMA3_DRV_QDMAQNUM_CLR_MASK(channelId -EDMA3_DRV_QDMA_CH_MIN_VAL)))) + >> (channelId*4u); + } + else + { + /* Only valid for DMA/QDMA channel, return error... */ + result = EDMA3_DRV_E_INVALID_PARAM; + } + } + } + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + + +/** + * \brief Set the Channel Controller (CC) Register value + * + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param regOffset [IN] CC Register offset whose value needs to be set + * \param newRegValue [IN] New CC Register Value + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is non re-entrant for users using the same + * EDMA handle i.e. working on the same shadow region. + * Before modifying a register, it tries to acquire a semaphore + * (Driver instance specific), to protect simultaneous + * modification of the same register by two different users. + * After the successful change, it releases the semaphore. + * For users working on different shadow regions, thus different + * EDMA handles, this function is re-entrant. + */ +EDMA3_DRV_Result EDMA3_DRV_setCCRegister (EDMA3_DRV_Handle hEdma, + unsigned int regOffset, + unsigned int newRegValue) + { + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + EDMA3_DRV_Instance *drvInst = NULL; + EDMA3_DRV_Object *drvObject = NULL; + volatile unsigned int regPhyAddr = 0x0u; + + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if ((hEdma == NULL) || ((regOffset % 4u) != 0)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_DRV_SOK == result) + { + drvInst = (EDMA3_DRV_Instance *)hEdma; + drvObject = drvInst->pDrvObjectHandle; + + if (drvObject == NULL) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + if (drvObject->gblCfgParams.globalRegs != NULL) + { + /** + * Take the instance specific semaphore, to prevent simultaneous + * access to the shared resources. + */ + result = edma3OsSemTake(drvInst->drvSemHandle, + EDMA3_OSSEM_NO_TIMEOUT); + + if (EDMA3_DRV_SOK == result) + { + /* Semaphore taken successfully, modify the registers. */ + regPhyAddr = (unsigned int)(drvObject->gblCfgParams.globalRegs) + regOffset; + + *(unsigned int *)regPhyAddr = newRegValue; + + /* Return the semaphore back */ + result = edma3OsSemGive(drvInst->drvSemHandle); + } + } + } + } + + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + + return result; + } + + + + +/** + * \brief Get the Channel Controller (CC) Register value + * + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param regOffset [IN] CC Register offset whose value is needed + * \param regValue [IN/OUT] CC Register Value + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant. + */ +EDMA3_DRV_Result EDMA3_DRV_getCCRegister ( EDMA3_DRV_Handle hEdma, + unsigned int regOffset, + unsigned int *regValue) + { + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + EDMA3_DRV_Instance *drvInst = NULL; + EDMA3_DRV_Object *drvObject = NULL; + volatile unsigned int regPhyAddr = 0x0u; + + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if (((hEdma == NULL) || (regValue == NULL)) + || ((regOffset % 4u) != 0)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_DRV_SOK == result) + { + drvInst = (EDMA3_DRV_Instance *)hEdma; + drvObject = drvInst->pDrvObjectHandle; + + if (drvObject == NULL) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + if (drvObject->gblCfgParams.globalRegs != NULL) + { + regPhyAddr = (unsigned int)(drvObject->gblCfgParams.globalRegs) + regOffset; + + *regValue = *(unsigned int *)regPhyAddr; + } + } + } + + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + + return result; + } + + + +/** + * \brief Wait for a transfer completion interrupt to occur and clear it. + * + * This is a blocking function that returns when the IPR/IPRH bit corresponding + * to the tccNo specified, is SET. It clears the corresponding bit while + * returning also. + * + * This function waits for the specific bit indefinitely in a tight loop, with + * out any delay in between. USE IT CAUTIOUSLY. + * + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param tccNo [IN] TCC, specific to which the function + * waits on a IPR/IPRH bit. + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant for different tccNo. + */ +EDMA3_DRV_Result EDMA3_DRV_waitAndClearTcc (EDMA3_DRV_Handle hEdma, + unsigned int tccNo) + { + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + EDMA3_DRV_Instance *drvInst = NULL; + EDMA3_DRV_Object *drvObject = NULL; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + volatile EDMA3_CCRL_ShadowRegs *shadowRegs = NULL; + unsigned int tccBitMask = 0x0u; + + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if (hEdma == NULL) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_DRV_SOK == result) + { + drvInst = (EDMA3_DRV_Instance *)hEdma; + drvObject = drvInst->pDrvObjectHandle; + + if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if (tccNo >= drvObject->gblCfgParams.numTccs) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_DRV_SOK == result) + { + globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs); + shadowRegs = (volatile EDMA3_CCRL_ShadowRegs *) + (&globalRegs->SHADOW[drvInst->regionId]); + + + if (shadowRegs != NULL) + { + if(tccNo < 32u) + { + tccBitMask = (1u << tccNo); + + /* Check the status of the IPR[tccNo] bit. */ + while (FALSE == (shadowRegs->IPR & tccBitMask)) + { + /* Transfer not yet completed, bit not SET */ + } + + /** + * Bit found SET, transfer is completed, + * clear the pending interrupt and return. + */ + shadowRegs->ICR = tccBitMask; + } + else + { + tccBitMask = (1u << (tccNo - 32u)); + + /* Check the status of the IPRH[tccNo-32] bit. */ + while (FALSE == (shadowRegs->IPRH & tccBitMask)) + { + /* Transfer not yet completed, bit not SET */ + } + + /** + * Bit found SET, transfer is completed, + * clear the pending interrupt and return. + */ + shadowRegs->ICRH = tccBitMask; + } + } + } + } + } + + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + + return result; + } + + +/** + * \brief Returns the status of a previously initiated transfer. + * + * This is a non-blocking function that returns the status of a previously + * initiated transfer, based on the IPR/IPRH bit. This bit corresponds to + * the tccNo specified by the user. It clears the corresponding bit, if SET, + * while returning also. + * + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param tccNo [IN] TCC, specific to which the function + * checks the status of the IPR/IPRH bit. + * \param tccStatus [IN/OUT] Status of the transfer is returned here. + * Returns "TRUE" if the transfer has + * completed (IPR/IPRH bit SET), + * "FALSE" if the transfer has not completed + * successfully (IPR/IPRH bit NOT SET). + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant for different tccNo. + */ +EDMA3_DRV_Result EDMA3_DRV_checkAndClearTcc (EDMA3_DRV_Handle hEdma, + unsigned int tccNo, + unsigned short *tccStatus) + { + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + EDMA3_DRV_Instance *drvInst = NULL; + EDMA3_DRV_Object *drvObject = NULL; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + volatile EDMA3_CCRL_ShadowRegs *shadowRegs = NULL; + unsigned int tccBitMask = 0x0u; + + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if ((hEdma == NULL) || (tccStatus == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_DRV_SOK == result) + { + drvInst = (EDMA3_DRV_Instance *)hEdma; + drvObject = drvInst->pDrvObjectHandle; + + if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if (tccNo >= drvObject->gblCfgParams.numTccs) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_DRV_SOK == result) + { + globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs); + shadowRegs = (volatile EDMA3_CCRL_ShadowRegs *) + (&globalRegs->SHADOW[drvInst->regionId]); + + /* Reset the tccStatus */ + *tccStatus = FALSE; + + if (shadowRegs != NULL) + { + if(tccNo < 32u) + { + tccBitMask = (1u << tccNo); + + /* Check the status of the IPR[tccNo] bit. */ + if ((shadowRegs->IPR & tccBitMask) != FALSE) + { + /* Transfer completed, bit found SET */ + *tccStatus = TRUE; + + /* Clear the pending interrupt also. */ + shadowRegs->ICR = tccBitMask; + } + } + else + { + tccBitMask = (1u << (tccNo - 32u)); + + /* Check the status of the IPRH[tccNo-32] bit. */ + if ((shadowRegs->IPRH & tccBitMask) != FALSE) + { + /* Transfer completed, bit found SET */ + *tccStatus = TRUE; + + /* Clear the pending interrupt also. */ + shadowRegs->ICRH = tccBitMask; + } + } + } + } + } + } + + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + + return result; + } + + + +/** + * \brief Get the PaRAM Set Physical Address associated with a logical channel + * + * This function returns the PaRAM Set Phy Address (unsigned 32 bits). + * The returned address could be used by the advanced users to program the + * PaRAM Set directly without using any APIs. + * + * Least significant 16 bits of this address could be used to program + * the LINK field in the PaRAM Set. + * Users which program the LINK field directly SHOULD use this API + * to get the associated PaRAM Set address with the LINK channel. + * + * + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param lCh [IN] Logical Channel for which the PaRAM set + * physical address is required + * \param paramPhyAddr [IN/OUT] PaRAM Set physical address is returned + * here. + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant. + */ +EDMA3_DRV_Result EDMA3_DRV_getPaRAMPhyAddr(EDMA3_DRV_Handle hEdma, + unsigned int lCh, + unsigned int *paramPhyAddr) + { + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + EDMA3_DRV_Instance *drvInst = NULL; + EDMA3_DRV_Object *drvObject = NULL; + int paRAMId = 0; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if (((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL)) + || (paramPhyAddr == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_DRV_SOK == result) + { + drvInst = (EDMA3_DRV_Instance *)hEdma; + drvObject = drvInst->pDrvObjectHandle; + + if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs); + paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId; + + if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + *paramPhyAddr = (unsigned int)&(globalRegs->PARAMENTRY [paRAMId].OPT); + } + } + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + + } + + + +/** + * \brief EDMA3 Driver IOCTL + * + * This function provides IOCTL functionality for EDMA3 Driver. + * + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param cmd [IN] IOCTL command to be performed + * \param cmdArg [IN/OUT] IOCTL command argument (if any) + * \param param [IN/OUT] Device/Cmd specific argument + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + */ +EDMA3_DRV_Result EDMA3_DRV_Ioctl( + EDMA3_DRV_Handle hEdma, + EDMA3_DRV_IoctlCmd cmd, + void *cmdArg, + void *param + ) + { + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + EDMA3_DRV_Instance *drvInst = NULL; + + /* To remove CCS warnings */ + (void)param; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if (hEdma == NULL) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + + if ((cmd <= EDMA3_DRV_IOCTL_MIN_IOCTL) + || (cmd >= EDMA3_DRV_IOCTL_MAX_IOCTL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + if (result == EDMA3_DRV_SOK) + { + drvInst = (EDMA3_DRV_Instance *)hEdma; + + if (drvInst == NULL) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + } + + if (result == EDMA3_DRV_SOK) + { + switch (cmd) + { + case EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION: + { + result = EDMA3_RM_Ioctl (drvInst->resMgrInstance, EDMA3_RM_IOCTL_SET_PARAM_CLEAR_OPTION, cmdArg, param); + + break; + } + + case EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION: + { + if (NULL == cmdArg) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + result = EDMA3_RM_Ioctl (drvInst->resMgrInstance, EDMA3_RM_IOCTL_GET_PARAM_CLEAR_OPTION, cmdArg, param); + } + + break; + } + + default: + /* You passed invalid IOCTL cmd */ + result = EDMA3_DRV_E_INVALID_PARAM; + } + } + + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + + } + + + +/** + * \brief Return the previously opened EDMA3 Driver Instance handle + * + * This API is used to return the previously opened EDMA3 Driver's + * Instance Handle (region specific), which could be used to call other + * EDMA3 Driver APIs. Since EDMA3 Driver does not allow multiple instances, + * for a single shadow region, this API is provided. This API is meant + * for users who DO NOT want to / could not open a new Driver Instance and + * hence re-use the existing Driver Instance to allocate EDMA3 resources + * and use various other EDMA3 Driver APIs. + * + * In case the Driver Instance is not yet opened, NULL is returned as the + * function return value whereas EDMA3_DRV_E_INST_NOT_OPENED is returned + * in the errorCode. + * + * \param phyCtrllerInstId [IN] EDMA3 Controller Instance Id (Hardware + * instance id, starting from 0). + * \param regionId [IN] Shadow Region id for which the previously + * opened driver's instance handle is + * required. + * \param errorCode [OUT] Error code while returning Driver Instance + * Handle. + * + * \return EDMA3_DRV_Handle : If successful, this API will return the + * driver's instance handle. + * + * \note 1) This API returns the previously opened EDMA3 Driver's Instance + * handle. The instance, if exists, could have been opened by some other + * user (most probably) or may be by the same user calling this API. If + * it was opened by some other user, then that user can very well close + * this instance anytime, without even knowing that the same instance + * handle is being used by other users as well. In that case, the + * handle becomes INVALID and user has to open a valid driver + * instance for his/her use. + * + * 2) This function is re-entrant. + */ +EDMA3_DRV_Handle EDMA3_DRV_getInstHandle(unsigned int phyCtrllerInstId, + EDMA3_RM_RegionId regionId, + EDMA3_DRV_Result *errorCode) + { + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + EDMA3_DRV_Object *drvObject = NULL; + EDMA3_DRV_Instance *drvInstanceHandle = NULL; + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if ((phyCtrllerInstId >= EDMA3_MAX_EDMA3_INSTANCES) + || (errorCode == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + if (EDMA3_DRV_SOK == result) + { + drvObject = &drvObj[phyCtrllerInstId]; + + if (NULL == drvObject) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + /* Check regionId. */ + if (regionId >= drvObject->gblCfgParams.numRegions) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + } + + if (EDMA3_DRV_SOK == result) + { + /* If the driver instance is already opened for this specific region, + * return it, else return an error. + */ + drvInstanceHandle = &drvInstance[phyCtrllerInstId][regionId]; + + if (NULL == drvInstanceHandle->pDrvObjectHandle) + { + /* Instance not opened yet!!! */ + drvInstanceHandle = NULL; + result = EDMA3_DRV_E_INST_NOT_OPENED; + } + } + + *errorCode = result; + return (EDMA3_DRV_Handle)drvInstanceHandle; + } + + +/* End of File */ diff --git a/packages/ti/sdo/edma3/drv/src/edma3_drv_basic.c b/packages/ti/sdo/edma3/drv/src/edma3_drv_basic.c new file mode 100644 index 0000000..cdb786c --- /dev/null +++ b/packages/ti/sdo/edma3/drv/src/edma3_drv_basic.c @@ -0,0 +1,2487 @@ +/******************************************************************************* +**+--------------------------------------------------------------------------+** +**| **** |** +**| **** |** +**| ******o*** |** +**| ********_///_**** |** +**| ***** /_//_/ **** |** +**| ** ** (__/ **** |** +**| ********* |** +**| **** |** +**| *** |** +**| |** +**| Copyright (c) 1998-2006 Texas Instruments Incorporated |** +**| ALL RIGHTS RESERVED |** +**| |** +**| Permission is hereby granted to licensees of Texas Instruments |** +**| Incorporated (TI) products to use this computer program for the sole |** +**| purpose of implementing a licensee product based on TI products. |** +**| No other rights to reproduce, use, or disseminate this computer |** +**| program, whether in part or in whole, are granted. |** +**| |** +**| TI makes no representation or warranties with respect to the |** +**| performance of this computer program, and specifically disclaims |** +**| any responsibility for any damages, special or consequential, |** +**| connected with the use of this program. |** +**| |** +**+--------------------------------------------------------------------------+** +*******************************************************************************/ + +/** +* \file edma3_drv_basic.c +* +* \brief EDMA3 Driver Basic Interface Implementation +* This file contains beginner-level EDMA3 Driver APIs which are required +* to: +* a) Request/free a DMA, QDMA and Link channel. +* b) Program various fields in the PaRAM Set like source/destination +* parameters, transfer parameters etc. +* c) Enable/disable a transfer. +* These APIs are provided to program a DMA/QDMA channel for simple use-cases +* and don't expose all the features of EDMA3 hardware. Users who want to go +* beyond this and have complete control on the EDMA3 hardware are advised +* to refer edma3_drv_adv.c source file. +* +* @author: PSP Team, TII +* +*/ + + +/* EDMa3 Driver Internal Header Files */ +#include +/* Resource Manager Internal Header Files */ +#include + +/* Instrumentation Header File */ +#ifdef EDMA3_INSTRUMENTATION_ENABLED +#include +#endif + +/* For assert() */ +/** + * Define NDEBUG to ignore assert(). + * NDEBUG should be defined before including assert.h header file. + */ +#include + + +/* Externel Variables */ +/*---------------------------------------------------------------------------*/ +/** + * Maximum Resource Manager Instances supported by the EDMA3 Package. + */ +extern const unsigned int EDMA3_MAX_RM_INSTANCES; + + +/** + * \brief EDMA3 Resource Manager Objects, tied to each EDMA3 HW Controller. + * + * Typically one RM object will cater to one EDMA3 HW controller + * and will have all the global config information. + */ +extern EDMA3_RM_Obj resMgrObj[EDMA3_MAX_EDMA3_INSTANCES]; + + +/** + * \brief Region Specific Configuration structure for + * EDMA3 controller, to provide region specific Information. + * + * This configuration info can also be provided by the user at run-time, + * while calling EDMA3_RM_open (). If not provided at run-time, + * this info will be taken from the config file "edma3__cfg.c", + * for the specified platform. + */ +extern EDMA3_RM_InstanceInitConfig *ptrInitCfgArray; + + +/** + * Handles of EDMA3 Resource Manager Instances. + * + * Used to maintain information of the EDMA3 RM Instances + * for each HW controller. + * There could be a maximum of EDMA3_MAX_RM_INSTANCES instances per + * EDMA3 HW. + */ +extern EDMA3_RM_Instance *ptrRMIArray; + +/** Local MemSet function */ +extern void edma3MemSet(void *dst, unsigned char data, unsigned int len); +/** Local MemCpy function */ +extern void edma3MemCpy(void *dst, const void *src, unsigned int len); + +/** + * \brief EDMA3 Driver Objects, tied to each EDMA3 HW Controller. + * + * Typically one object will cater to one EDMA3 HW controller + * and will have all regions' (ARM, DSP etc) specific config information. + */ +extern EDMA3_DRV_Object drvObj [EDMA3_MAX_EDMA3_INSTANCES]; + + +/** + * Handles of EDMA3 Driver Instances. + * + * Used to maintain information of the EDMA3 Driver Instances for + * each region, for each HW controller. + * There could be as many Driver Instances as there are shadow + * regions. Multiple EDMA3 Driver instances on the same shadow + * region are NOT allowed. + */ +extern EDMA3_DRV_Instance drvInstance [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS]; + + +/** + * \brief Resources bound to a Channel + * + * When a request for a channel is made, the resources PaRAM Set and TCC + * get bound to that channel. This information is needed internally by the + * driver when a request is made to free the channel (Since it is the + * responsibility of the driver to free up the channel-associated resources + * from the Resource Manager layer). + */ +extern EDMA3_DRV_ChBoundResources edma3DrvChBoundRes [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_LOGICAL_CH]; + + + +/* Local functions prototypes */ +/*---------------------------------------------------------------------------*/ +/** Remove various mappings and do cleanup for DMA/QDMA channels */ +static EDMA3_DRV_Result edma3RemoveMapping (EDMA3_DRV_Handle hEdma, + unsigned int channelId); + +/*---------------------------------------------------------------------------*/ + + +/** + * \brief Request a DMA/QDMA/Link channel. + * + * Each channel (DMA/QDMA/Link) must be requested before initiating a DMA + * transfer on that channel. + * + * This API is used to allocate a logical channel (DMA/QDMA/Link) along with + * the associated resources. For DMA and QDMA channels, TCC and PaRAM Set are + * also allocated along with the requested channel. For Link channel, ONLY a + * PaRAM Set is allocated. + * + * User can request a specific logical channel by passing the channel id in + * 'pLCh'. Note that the channel id is the same as the actual resource id in + * case of DMA channels. To allocate specific QDMA channels, user SHOULD use the + * defines EDMA3_DRV_QDMA_CHANNEL_X mentioned above. + * + * User can also request ANY available logical channel also by specifying the + * below mentioned values in '*pLCh': + * a) EDMA3_DRV_DMA_CHANNEL_ANY: For DMA channels + * b) EDMA3_DRV_QDMA_CHANNEL_ANY: For QDMA channels, and + * c) EDMA3_DRV_LINK_CHANNEL: For Link channels. Normally user should use this + * value to request link channels (PaRAM Sets used for linking purpose + * only), unless he wants to use some specific link channels (PaRAM Sets) + * which is also allowed. + * + * This API internally uses EDMA3_RM_allocResource () to allocate the desired + * resources (DMA/QDMA channel, PaRAM Set and TCC). + * + * This API also registers a specific callback function against the allocated + * TCC. + * + * For DMA/QDMA channels, after allocating all the EDMA3 resources, this API + * sets the TCC field of the OPT PaRAM Word with the allocated TCC. It also sets + * the event queue for the channel allocated. The event queue needs to be + * specified by the user. + * + * For DMA channel, it also sets the DCHMAP register, if required. + * + * For QDMA channel, it sets the QCHMAP register and CCNT as trigger word and + * enables the QDMA channel by writing to the QEESR register. + * + * \param hEdma [IN] Handle to the previously opened Driver + * Instance. + * \param pLCh [IN/OUT] Requested logical channel id. + * Examples: + * - EDMA3_DRV_HW_CHANNEL_EVENT_0 + * - To request a DMA Master Channel + * mapped to EDMA Event 0. + * + * - EDMA3_DRV_DMA_CHANNEL_ANY + * - For requesting any DMA Master channel + * with no event mapping. + * + * - EDMA3_DRV_QDMA_CHANNEL_ANY + * - For requesting any QDMA Master channel + * + * - EDMA3_DRV_QDMA_CHANNEL_0 + * - For requesting the QDMA Channel 0. + * + * - EDMA3_DRV_LINK_CHANNEL + * - For requesting a DMA Slave Channel, + * - to be linked to some other Master + * - channel. + * + * In case user passes a specific channel + * Id, pLCh value is left unchanged. In + * case user requests ANY available + * resource, the allocated channel id is + * returned in pLCh. + * + * \note To request a PaRAM Set for the purpose of + * linking to another channel, call the function with + * + * *pLCh = EDMA3_DRV_LINK_CHANNEL; + * + * This function will update *pLCh with the allocated Link channel + * handle. This handle could be DIFFERENT from the actual PaRAM Set + * allocated by the Resource Manager internally. So user SHOULD NOT + * assume the handle as the PaRAM Set Id. + * + * \param pTcc [IN/OUT] The channel number on which the + * completion/error interrupt is generated. + * Not used if user requested for a Link + * channel. + * Examples: + * - EDMA3_DRV_HW_CHANNEL_EVENT_0 + * - To request TCC associated with + * - DMA Master Channel mapped to EDMA + * - event 0. + * + * - EDMA3_DRV_TCC_ANY + * - For requesting any TCC with no + * - channel mapping. + * In case user passes a specific TCC + * value, pTcc value is left unchanged. + * In case user requests ANY available TCC, + * the allocated one is returned in pTcc + * + * \param evtQueue [IN] Event Queue Number to which the channel + * will be mapped (valid only for the + * Master Channel (DMA/QDMA) request) + * + * \param tccCb [IN] TCC callback - caters to channel- + * specific events like "Event Miss Error" + * or "Transfer Complete" + * + * \param cbData [IN] Data which will be passed directly to + * the tccCb callback function + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error code + * + * \note This function internally uses EDMA3 Resource Manager, which + * acquires a RM Instance specific semaphore + * to prevent simultaneous access to the global pool of resources. + * It also disables the global interrupts while modifying + * the global CC registers. + * It is re-entrant, but SHOULD NOT be called from the user callback + * function (ISR context). + */ +EDMA3_DRV_Result EDMA3_DRV_requestChannel (EDMA3_DRV_Handle hEdma, + unsigned int *pLCh, + unsigned int *pTcc, + EDMA3_RM_EventQueue evtQueue, + EDMA3_RM_TccCallback tccCb, + void *cbData) + { + unsigned int intState=0; + EDMA3_RM_ResDesc resObj; + EDMA3_RM_ResDesc channelObj; + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + unsigned int linkBcntReld = 0; + EDMA3_DRV_Instance *drvInst = NULL; + EDMA3_DRV_Object *drvObject = NULL; + EDMA3_RM_ResType savedResType; + unsigned int mappedTcc = EDMA3_DRV_CH_NO_TCC_MAP; + int paRAMId = (int)EDMA3_RM_RES_ANY; + EDMA3_DRV_ChannelType chType = EDMA3_DRV_CHANNEL_TYPE_QDMA; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + int mappedPaRAMId; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if ((pLCh == NULL) || (hEdma == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_DRV_SOK == result) + { + drvInst = (EDMA3_DRV_Instance *)hEdma; + drvObject = drvInst->pDrvObjectHandle; + + if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs); + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if (((*pLCh) != EDMA3_DRV_LINK_CHANNEL) && + ((evtQueue >= drvObject->gblCfgParams.numEvtQueue) || (pTcc == NULL))) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_DRV_SOK == result) + { + if ((*pLCh) == EDMA3_DRV_LINK_CHANNEL) + { + /* + * Do nothing. Do not allocate channel. + * Typically this option is for request + * of a PaRAM Set for linking purpose. + */ + result = EDMA3_DRV_SOK; + } + else if ((*pLCh) == EDMA3_DRV_DMA_CHANNEL_ANY) + { + /* First request for any available DMA channel */ + resObj.type = EDMA3_RM_RES_DMA_CHANNEL; + resObj.resId = EDMA3_RM_RES_ANY; + result = EDMA3_RM_allocResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj); + + if (result == EDMA3_RM_SOK) + { + *pLCh = resObj.resId; + mappedPaRAMId = drvObject->gblCfgParams.dmaChannelPaRAMMap[*pLCh]; + mappedTcc = drvObject->gblCfgParams.dmaChannelTccMap[*pLCh]; + if (mappedPaRAMId != EDMA3_DRV_CH_NO_PARAM_MAP) + { + /* + * There is a PaRAM Set statically mapped to the returned + * channel number. + * This imposes a constraint on the PaRAM Set which we + * next request for. + * We update the PaRAM Set number with the one statically + * reserved for the afore-returned channel number. + */ + paRAMId = mappedPaRAMId; + } + chType = EDMA3_DRV_CHANNEL_TYPE_DMA; + + /* Save the Resource Type for TCC registeration */ + channelObj.type = EDMA3_RM_RES_DMA_CHANNEL; + } + else + { + result = EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL; + } + } + else if ((*pLCh) == EDMA3_DRV_QDMA_CHANNEL_ANY) + { + /* First request for any available QDMA channel */ + resObj.type = EDMA3_RM_RES_QDMA_CHANNEL; + resObj.resId = EDMA3_RM_RES_ANY; + result = EDMA3_RM_allocResource(drvInst->resMgrInstance, + (EDMA3_RM_ResDesc *)&resObj); + if (result == EDMA3_DRV_SOK) + { + (*pLCh) = resObj.resId + EDMA3_DRV_QDMA_CH_MIN_VAL; + chType = EDMA3_DRV_CHANNEL_TYPE_QDMA; + + /* Save the Resource Type for TCC registeration */ + channelObj.type = EDMA3_RM_RES_QDMA_CHANNEL; + } + else + { + result = EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL; + } + } + else if ((*pLCh) <= EDMA3_DRV_DMA_CH_MAX_VAL) + { + /* Request for a specific DMA channel */ + resObj.type = EDMA3_RM_RES_DMA_CHANNEL; + resObj.resId = *pLCh; + result = EDMA3_RM_allocResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj); + if (result != EDMA3_RM_SOK) + { + result = EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL; + } + else + { + mappedPaRAMId = drvObject->gblCfgParams.dmaChannelPaRAMMap[*pLCh]; + mappedTcc = drvObject->gblCfgParams.dmaChannelTccMap[*pLCh]; + if (mappedPaRAMId != EDMA3_DRV_CH_NO_PARAM_MAP) + { + /* + * There is a PaRAM Set statically mapped to the returned + * channel number. + * This imposes a constraint on the PaRAM Set which we + * next request for. + * We update the PaRAM Set number with the one statically + * reserved for the afore-returned channel number. + */ + paRAMId = mappedPaRAMId; + } + chType = EDMA3_DRV_CHANNEL_TYPE_DMA; + + /* Save the Resource Type for TCC registeration */ + channelObj.type = EDMA3_RM_RES_DMA_CHANNEL; + } + } + else if (((*pLCh) >= EDMA3_DRV_QDMA_CH_MIN_VAL) && ((*pLCh) <= EDMA3_DRV_QDMA_CH_MAX_VAL)) + { + /* Request for a specific QDMA channel */ + resObj.type = EDMA3_RM_RES_QDMA_CHANNEL; + resObj.resId = (((*pLCh)) - EDMA3_DRV_QDMA_CH_MIN_VAL); + result = EDMA3_RM_allocResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj); + if (result != EDMA3_RM_SOK) + { + result = EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL; + } + else + { + chType = EDMA3_DRV_CHANNEL_TYPE_QDMA; + + /* Save the Resource Type for TCC registeration */ + channelObj.type = EDMA3_RM_RES_QDMA_CHANNEL; + } + } + else + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + + if (result == EDMA3_DRV_SOK) + { + /* Request for a PaRAM Set */ + savedResType = resObj.type; + resObj.type = EDMA3_RM_RES_PARAM_SET; + resObj.resId = (unsigned int)paRAMId; + result = EDMA3_RM_allocResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj); + + paRAMId = (int)resObj.resId; + if ((*pLCh) == EDMA3_DRV_LINK_CHANNEL) + { + if (result == EDMA3_RM_SOK) + { + unsigned int linkCh = EDMA3_DRV_LINK_CH_MIN_VAL; + + /* + * Search for the next Link channel handle available, + * starting from EDMA3_DRV_LINK_CH_MIN_VAL. + */ + while ((edma3DrvChBoundRes[drvObject->phyCtrllerInstId][linkCh].paRAMId != -1) + && (linkCh <= EDMA3_DRV_LINK_CH_MAX_VAL)) + { + /* Move to the next handle. */ + linkCh++; + } + + /* Verify the returned handle, it should lie in the correct range */ + if (linkCh > EDMA3_DRV_LINK_CH_MAX_VAL) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + *pLCh = linkCh; + } + } + } + else + { + if (result != EDMA3_DRV_SOK) + { + /* + * Free the already allocated channel + * (only if channel is a Non-Link Channel) + */ + resObj.type = savedResType; + resObj.resId = *pLCh; + EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj); + } + else + { + /* Request for a TCC */ + resObj.type = EDMA3_RM_RES_TCC; + if ((*pTcc) == EDMA3_DRV_TCC_ANY) + { + if (mappedTcc == EDMA3_DRV_CH_NO_TCC_MAP) + { + resObj.resId = EDMA3_RM_RES_ANY; + } + else + { + resObj.resId = mappedTcc; + } + } + else + { + resObj.resId = *pTcc; + } + + result = EDMA3_RM_allocResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj); + if (result == EDMA3_DRV_SOK) + { + *pTcc = resObj.resId; + } + else + { + resObj.type = savedResType; + resObj.resId = *pLCh; + EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj); + + resObj.type = EDMA3_RM_RES_PARAM_SET; + resObj.resId = (unsigned int)paRAMId; + EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj); + result = EDMA3_DRV_E_TCC_UNAVAIL; + } + + if (result == EDMA3_DRV_SOK) + { + /* If callback function is not null, register it with the RM. */ + if (NULL != tccCb) + { + /** + * Fill the resource id, whose associated TCC + * needs to be registered. + * For QDMA channels, pass the actual QDMA + * channel no instead of (*pLCh). + */ + if (((*pLCh) >= EDMA3_DRV_QDMA_CH_MIN_VAL) + && ((*pLCh) <= EDMA3_DRV_QDMA_CH_MAX_VAL)) + { + channelObj.resId = (*pLCh) - EDMA3_DRV_QDMA_CH_MIN_VAL; + } + else + { + channelObj.resId = (*pLCh); + } + + result = EDMA3_RM_registerTccCb ( + drvInst->resMgrInstance, + (EDMA3_RM_ResDesc *)&channelObj, + *pTcc, tccCb, cbData); + + if (result != EDMA3_DRV_SOK) + { + EDMA3_DRV_freeChannel (hEdma, *pLCh); + result = EDMA3_DRV_E_TCC_REGISTER_FAIL; + } + } + + if (result == EDMA3_DRV_SOK) + { + edma3OsProtectEntry(EDMA3_OS_PROTECT_INTERRUPT, &intState); + + /* Associate Channel to Event Queue */ + if ((*pLCh) < drvObject->gblCfgParams.numDmaChannels) + { + globalRegs->DMAQNUM[(*pLCh) >> 3u] &= EDMA3_DRV_DMAQNUM_CLR_MASK(*pLCh); + globalRegs->DMAQNUM[(*pLCh) >> 3u] |= EDMA3_DRV_DMAQNUM_SET_MASK((*pLCh),evtQueue); + } + else if (((*pLCh) >= EDMA3_DRV_QDMA_CH_MIN_VAL) + && ((*pLCh) <= EDMA3_DRV_QDMA_CH_MAX_VAL)) + { + globalRegs->QDMAQNUM &= + EDMA3_DRV_QDMAQNUM_CLR_MASK((*pLCh)-EDMA3_DRV_QDMA_CH_MIN_VAL); + globalRegs->QDMAQNUM |= + EDMA3_DRV_QDMAQNUM_SET_MASK((*pLCh)-EDMA3_DRV_QDMA_CH_MIN_VAL,evtQueue); + } + + edma3OsProtectExit(EDMA3_OS_PROTECT_INTERRUPT,intState); + + /** + * Map the allocated PaRAM Set to the logical + * DMa/QDMA channel. + */ + if (chType == EDMA3_DRV_CHANNEL_TYPE_QDMA) + { + result = EDMA3_RM_mapQdmaChannel (drvInst->resMgrInstance, + ((*pLCh)-EDMA3_DRV_QDMA_CH_MIN_VAL), + paRAMId, + EDMA3_RM_QDMA_TRIG_DEFAULT); + } + else + { + /** + * First check whether the mapping feature is supported on the underlying + * platform. In case it is not supported, dont call this API, because this + * API returns error in case the feature is not there. + */ + if (TRUE == drvObject->gblCfgParams.dmaChPaRAMMapExists) + { + result = EDMA3_RM_mapEdmaChannel (drvInst->resMgrInstance, + *pLCh, + paRAMId); + } + } + + if (result != EDMA3_DRV_SOK) + { + EDMA3_DRV_freeChannel (hEdma, *pLCh); + result = EDMA3_DRV_E_CH_PARAM_BIND_FAIL; + } + else + { + /* Bind the resources PaRAM Set and TCC */ + /* Set TCC of Param Set corresponding to specified paramId */ + globalRegs->PARAMENTRY [paRAMId].OPT &= EDMA3_DRV_OPT_TCC_CLR_MASK; + globalRegs->PARAMENTRY [paRAMId].OPT |= EDMA3_DRV_OPT_TCC_SET_MASK(*pTcc); + + edma3DrvChBoundRes[drvObject->phyCtrllerInstId][*pLCh].tcc = *pTcc; + } + } + } + } + } + + if (result == EDMA3_DRV_SOK) + { + /* Save the PaRAM Id and Trigger mode */ + edma3DrvChBoundRes[drvObject->phyCtrllerInstId][*pLCh].paRAMId = paRAMId; + edma3DrvChBoundRes[drvObject->phyCtrllerInstId][*pLCh].trigMode = + EDMA3_DRV_TRIG_MODE_NONE; + + /* Make the Link field NULL */ + /* Get the Link-bcntReload PaRAM set entry */ + linkBcntReld = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + + (unsigned int)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD)); + + /* Remove any linking */ + linkBcntReld |= 0xFFFFu; + + /* Store it back */ + *((&globalRegs->PARAMENTRY[paRAMId].OPT) + + (unsigned int)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD) = linkBcntReld; + + /* + * For QDMA channels, Enable the transfer. + * So that user doesn't have to call EDMA3_DRV_enableTransfer() again. + */ + if (((*pLCh) >= EDMA3_DRV_QDMA_CH_MIN_VAL) + && ((*pLCh) <= EDMA3_DRV_QDMA_CH_MAX_VAL)) + { + drvInst->shadowRegs->QEESR = (1u<<((*pLCh)-EDMA3_DRV_QDMA_CH_MIN_VAL)); + /* save the trigger mode for future use */ + edma3DrvChBoundRes[drvObject->phyCtrllerInstId][*pLCh].trigMode = EDMA3_DRV_TRIG_MODE_QDMA; + } + } + } + } + } + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; +} + + +/** + * \brief Free the specified channel (DMA/QDMA/Link) and its associated + * resources (PaRAM Set, TCC etc) and removes various mappings. + * + * This API internally uses EDMA3_RM_freeResource () to free the desired + * resources. + * + * For Link channels, this API only frees the associated PaRAM Set. + * + * For DMA/QDMA channels, it does the following operations: + * a) Disable any ongoing transfer on the channel, + * b) Unregister the TCC Callback function and disable the interrupts, + * c) Remove the channel to Event Queue mapping, + * d) For DMA channels, clear the DCHMAP register, if available + * e) For QDMA channels, clear the QCHMAP register, + * f) Frees the DMA/QDMA channel in the end. + * + * \param hEdma [IN] Handle to the EDMA Driver Instance. + * \param channelId [IN] Logical Channel number to be freed. + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error code + * + * \note This function disables the global interrupts while modifying + * the global CC registers and while modifying global data structures, + * to prevent simultaneous access to the global pool of resources. + * It internally calls EDMA3_RM_freeResource () for resource + * de-allocation. It is re-entrant. + */ +EDMA3_DRV_Result EDMA3_DRV_freeChannel (EDMA3_DRV_Handle hEdma, + unsigned int channelId) + { + EDMA3_RM_ResDesc resObj; + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + EDMA3_DRV_Instance *drvInst = NULL; + EDMA3_DRV_Object *drvObject = NULL; + int paRAMId; + unsigned int tcc; + EDMA3_DRV_ChannelType chType = EDMA3_DRV_CHANNEL_TYPE_NONE; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if ((channelId > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + if (result == EDMA3_DRV_SOK) + { + drvInst = (EDMA3_DRV_Instance *)hEdma; + drvObject = drvInst->pDrvObjectHandle; + + if (drvObject == NULL) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + } + + if (result == EDMA3_DRV_SOK) + { + /* Check the channel type */ + if (channelId <= EDMA3_DRV_DMA_CH_MAX_VAL) + { + /* DMA Channel */ + chType = EDMA3_DRV_CHANNEL_TYPE_DMA; + } + + if ((channelId >= EDMA3_DRV_LINK_CH_MIN_VAL) && (channelId <= EDMA3_DRV_LINK_CH_MAX_VAL)) + { + /* LINK Channel */ + chType = EDMA3_DRV_CHANNEL_TYPE_LINK; + } + + if ((channelId >= EDMA3_DRV_QDMA_CH_MIN_VAL) && (channelId <= EDMA3_DRV_QDMA_CH_MAX_VAL)) + { + /* QDMA Channel */ + chType = EDMA3_DRV_CHANNEL_TYPE_QDMA; + } + + if (chType == 0) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + } + + + if (result == EDMA3_DRV_SOK) + { + if (chType == EDMA3_DRV_CHANNEL_TYPE_LINK) + { + /* LINK Channel */ + resObj.type = EDMA3_RM_RES_PARAM_SET; + + /* Get the PaRAM id from the book-keeping info. */ + resObj.resId = (unsigned int)(edma3DrvChBoundRes[drvObject->phyCtrllerInstId][channelId].paRAMId); + + result = EDMA3_RM_freeResource(drvInst->resMgrInstance, + (EDMA3_RM_ResDesc *)&resObj); + + if (result == EDMA3_DRV_SOK) + { + edma3DrvChBoundRes[drvObject->phyCtrllerInstId][channelId].paRAMId = -1; + } + } + else + { + /* DMA/QDMA Channel */ + paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][channelId].paRAMId; + tcc = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][channelId].tcc; + + /* Check the paRAMId and tcc values first */ + if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + + if (tcc >= drvObject->gblCfgParams.numTccs) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + + if (result == EDMA3_DRV_SOK) + { + /* Disable the transfer and remove various mappings. */ + result = edma3RemoveMapping(hEdma, channelId); + } + + if (result == EDMA3_DRV_SOK) + { + /* Now Free the PARAM set and TCC */ + resObj.type = EDMA3_RM_RES_PARAM_SET; + resObj.resId = (unsigned int)paRAMId; + result = EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj); + + if (result == EDMA3_DRV_SOK) + { + /* PaRAM Set Freed */ + edma3DrvChBoundRes[drvObject->phyCtrllerInstId][channelId].paRAMId = -1; + + /* Free the TCC */ + resObj.type = EDMA3_RM_RES_TCC; + resObj.resId = tcc; + result = EDMA3_RM_freeResource(drvInst->resMgrInstance, + (EDMA3_RM_ResDesc *)&resObj); + } + + if (result == EDMA3_DRV_SOK) + { + /* TCC Freed. */ + edma3DrvChBoundRes[drvObject->phyCtrllerInstId][channelId].tcc = 0; + + /* Now free the DMA/QDMA Channel in the end. */ + if (chType == EDMA3_DRV_CHANNEL_TYPE_QDMA) + { + resObj.type = EDMA3_RM_RES_QDMA_CHANNEL; + resObj.resId = (channelId - EDMA3_DRV_QDMA_CH_MIN_VAL); + result = EDMA3_RM_freeResource(drvInst->resMgrInstance, + (EDMA3_RM_ResDesc *)&resObj); + } + else + { + resObj.type = EDMA3_RM_RES_DMA_CHANNEL; + resObj.resId = channelId; + result = EDMA3_RM_freeResource(drvInst->resMgrInstance, + (EDMA3_RM_ResDesc *)&resObj); + } + } + } + } + } + + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + +/** + * \brief Clears Event Register and Error Register for a specific + * DMA channel and brings back EDMA3 to its initial state. + * + * This API clears the Event register, Event Miss register Event Enable + * register for a specific DMA channel. It also clears the CC Error register. + * + * \param hEdma [IN] Handle to the EDMA Driver Instance. + * \param channelId [IN] DMA Channel needs to be cleaned. + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error code + * + * \note This function is re-entrant for unique channelId values. It is non- + * re-entrant for same channelId value. + */ +EDMA3_DRV_Result EDMA3_DRV_clearErrorBits (EDMA3_DRV_Handle hEdma, + unsigned int channelId) +{ + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + EDMA3_DRV_Instance *drvInst = NULL; + EDMA3_DRV_Object *drvObject = NULL; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + unsigned int count; + unsigned int value = 0; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if (hEdma == NULL) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_DRV_SOK == result) + { + drvInst = (EDMA3_DRV_Instance *)hEdma; + drvObject = drvInst->pDrvObjectHandle; + + if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if (channelId > EDMA3_DRV_DMA_CH_MAX_VAL) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_DRV_SOK == result) + { + globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs); + +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("EMR =%l\r\n", globalRegs->EMR); +#endif + if(channelId < 32u) + { + /* Clear the Event Register */ + drvInst->shadowRegs->ECR = (1u << channelId); + /* Write to EMCR to clear the corresponding EMR bit*/ + globalRegs->EMCR = (1u << channelId); + /* Clear any SER*/ + drvInst->shadowRegs->SECR = (1u << channelId); + /* Clear any EER */ + drvInst->shadowRegs->EECR = (1u << channelId); + } + else + { +#ifdef EDMA3_DRV_DEBUG + EDMA3_DRV_PRINTF("EMRH =%l\r\n", globalRegs->EMRH); +#endif + /* Clear the Event Register */ + drvInst->shadowRegs->ECRH = (1u << (channelId - 32u)); + /* Write to EMCR to clear the corresponding EMR bit*/ + globalRegs->EMCRH = (1u << (channelId - 32u)); + /* Clear any SER*/ + drvInst->shadowRegs->SECRH = (1u << (channelId - 32u)); + /* Clear any EER */ + drvInst->shadowRegs->EECRH = (1u << (channelId - 32u)); + } + + /* Clear the global CC Error Register */ + for (count = 0; count < drvObject->gblCfgParams.numEvtQueue; count++) + { + value |= (1u << count); + } + + globalRegs->CCERRCLR = (EDMA3_CCRL_CCERR_TCCERR_MASK | value); + } + } + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + +/** + * \brief Set a particular OPT field in the PaRAM set associated with the + * logical channel 'lCh'. + * + * This API can be used to set various optional parameters for an EDMA3 + * transfer. Like enable/disable completion interrupts, enable/disable chaining, + * setting the transfer mode (A/AB Sync), setting the FIFO width etc. + * + * \param hEdma [IN] Handle to the EDMA Driver Instance. + * \param lCh [IN] Logical Channel, bound to which + * PaRAM set OPT field needs to be set. + * \param optField [IN] The particular field of OPT Word + * that needs setting + * \param newOptFieldVal [IN] The new OPT field value + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant for unique lCh values. It is non- + * re-entrant for same lCh value. + */ +EDMA3_DRV_Result EDMA3_DRV_setOptField (EDMA3_DRV_Handle hEdma, + unsigned int lCh, + EDMA3_DRV_OptField optField, + unsigned int newOptFieldVal) + { + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + EDMA3_DRV_Instance *drvInst = NULL; + EDMA3_DRV_Object *drvObject = NULL; + unsigned int newOptVal = 0; + unsigned int oldOptVal = 0; + int paRAMId = 0; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if (((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL)) + || ((optField < EDMA3_DRV_OPT_FIELD_SAM) + || (optField > EDMA3_DRV_OPT_FIELD_ITCCHEN))) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_DRV_SOK == result) + { + drvInst = (EDMA3_DRV_Instance *)hEdma; + drvObject = drvInst->pDrvObjectHandle; + + if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId; + globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs); + + if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + + if (result == EDMA3_DRV_SOK) + { + oldOptVal = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAMId].OPT)); + + switch (optField) + { + case EDMA3_DRV_OPT_FIELD_SAM : + newOptVal = (oldOptVal & EDMA3_DRV_OPT_SAM_CLR_MASK) + | + (EDMA3_DRV_OPT_SAM_SET_MASK(newOptFieldVal)); + break; + case EDMA3_DRV_OPT_FIELD_DAM : + newOptVal = (oldOptVal & EDMA3_DRV_OPT_DAM_CLR_MASK) + | + (EDMA3_DRV_OPT_DAM_SET_MASK(newOptFieldVal)); + break; + case EDMA3_DRV_OPT_FIELD_SYNCDIM : + newOptVal = (oldOptVal & EDMA3_DRV_OPT_SYNCDIM_CLR_MASK) + | + (EDMA3_DRV_OPT_SYNCDIM_SET_MASK(newOptFieldVal)); + break; + case EDMA3_DRV_OPT_FIELD_STATIC : + newOptVal = (oldOptVal & EDMA3_DRV_OPT_STATIC_CLR_MASK) + | + (EDMA3_DRV_OPT_STATIC_SET_MASK(newOptFieldVal)); + break; + case EDMA3_DRV_OPT_FIELD_FWID : + newOptVal = (oldOptVal & EDMA3_DRV_OPT_FWID_CLR_MASK) + | + (EDMA3_DRV_OPT_FWID_SET_MASK(newOptFieldVal)); + break; + case EDMA3_DRV_OPT_FIELD_TCCMODE : + newOptVal = (oldOptVal & EDMA3_DRV_OPT_TCCMODE_CLR_MASK) + | + (EDMA3_DRV_OPT_TCCMODE_SET_MASK(newOptFieldVal)); + break; + case EDMA3_DRV_OPT_FIELD_TCC : + newOptVal = (oldOptVal & EDMA3_DRV_OPT_TCC_CLR_MASK) + | + (EDMA3_DRV_OPT_TCC_SET_MASK(newOptFieldVal)); + break; + case EDMA3_DRV_OPT_FIELD_TCINTEN : + newOptVal = (oldOptVal & EDMA3_DRV_OPT_TCINTEN_CLR_MASK) + | + (EDMA3_DRV_OPT_TCINTEN_SET_MASK(newOptFieldVal)); + break; + case EDMA3_DRV_OPT_FIELD_ITCINTEN : + newOptVal = (oldOptVal & EDMA3_DRV_OPT_ITCINTEN_CLR_MASK) + | + (EDMA3_DRV_OPT_ITCINTEN_SET_MASK(newOptFieldVal)); + break; + case EDMA3_DRV_OPT_FIELD_TCCHEN : + newOptVal = (oldOptVal & EDMA3_DRV_OPT_TCCHEN_CLR_MASK) + | + (EDMA3_DRV_OPT_TCCHEN_SET_MASK(newOptFieldVal)); + break; + case EDMA3_DRV_OPT_FIELD_ITCCHEN : + newOptVal = (oldOptVal & EDMA3_DRV_OPT_ITCCHEN_CLR_MASK) + | + (EDMA3_DRV_OPT_ITCCHEN_SET_MASK(newOptFieldVal)); + break; + default: + break; + } + + *(&globalRegs->PARAMENTRY[paRAMId].OPT) = newOptVal; + } + } + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + +/** + * \brief Get a particular OPT field in the PaRAM set associated with the + * logical channel 'lCh'. + * + * This API can be used to read various optional parameters for an EDMA3 + * transfer. Like enable/disable completion interrupts, enable/disable chaining, + * setting the transfer mode (A/AB Sync), setting the FIFO width etc. + * + * \param hEdma [IN] Handle to the EDMA Driver Instance. + * \param lCh [IN] Logical Channel, bound to which + * PaRAM set OPT field is required. + * \param optField [IN] The particular field of OPT Word + * that is needed + * \param optFieldVal [IN/OUT] Value of the OPT field + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant. + */ +EDMA3_DRV_Result EDMA3_DRV_getOptField (EDMA3_DRV_Handle hEdma, + unsigned int lCh, + EDMA3_DRV_OptField optField, + unsigned int *optFieldVal) + { + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + EDMA3_DRV_Instance *drvInst = NULL; + EDMA3_DRV_Object *drvObject = NULL; + unsigned int optVal = 0; + int paRAMId = 0; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if (((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) + || ((hEdma == NULL) || (optFieldVal == NULL))) + || ((optField < EDMA3_DRV_OPT_FIELD_SAM) + || (optField > EDMA3_DRV_OPT_FIELD_ITCCHEN))) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_DRV_SOK == result) + { + drvInst = (EDMA3_DRV_Instance *)hEdma; + drvObject = drvInst->pDrvObjectHandle; + + if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId; + globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs); + + if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + + if (result == EDMA3_DRV_SOK) + { + optVal = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAMId].OPT)); + + switch (optField) + { + case EDMA3_DRV_OPT_FIELD_SAM : + *optFieldVal = EDMA3_DRV_OPT_SAM_GET_MASK(optVal); + break; + case EDMA3_DRV_OPT_FIELD_DAM : + *optFieldVal = EDMA3_DRV_OPT_DAM_GET_MASK(optVal); + break; + case EDMA3_DRV_OPT_FIELD_SYNCDIM : + *optFieldVal = EDMA3_DRV_OPT_SYNCDIM_GET_MASK(optVal); + break; + case EDMA3_DRV_OPT_FIELD_STATIC : + *optFieldVal = EDMA3_DRV_OPT_STATIC_GET_MASK(optVal); + break; + case EDMA3_DRV_OPT_FIELD_FWID : + *optFieldVal = EDMA3_DRV_OPT_FWID_GET_MASK(optVal); + break; + case EDMA3_DRV_OPT_FIELD_TCCMODE : + *optFieldVal = EDMA3_DRV_OPT_TCCMODE_GET_MASK(optVal); + break; + case EDMA3_DRV_OPT_FIELD_TCC : + *optFieldVal = EDMA3_DRV_OPT_TCC_GET_MASK(optVal); + break; + case EDMA3_DRV_OPT_FIELD_TCINTEN : + *optFieldVal = EDMA3_DRV_OPT_TCINTEN_GET_MASK(optVal); + break; + case EDMA3_DRV_OPT_FIELD_ITCINTEN : + *optFieldVal = EDMA3_DRV_OPT_ITCINTEN_GET_MASK(optVal); + break; + case EDMA3_DRV_OPT_FIELD_TCCHEN : + *optFieldVal = EDMA3_DRV_OPT_TCCHEN_GET_MASK(optVal); + break; + case EDMA3_DRV_OPT_FIELD_ITCCHEN : + *optFieldVal = EDMA3_DRV_OPT_ITCCHEN_GET_MASK(optVal); + break; + default: + break; + } + } + } + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + + +/** + * \brief DMA source parameters setup + * + * It is used to program the source address, source side addressing mode + * (INCR or FIFO) and the FIFO width in case the addressing mode is FIFO. + * + * In FIFO Addressing mode, memory location must be 32 bytes aligned. + * + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param lCh [IN] Logical Channel for which the source parameters + * are to be configured + * \param srcAddr [IN] Source address + * \param addrMode [IN] Address mode [FIFO or Increment] + * \param fifoWidth [IN] Width of FIFO (Valid only if addrMode is FIFO) + * -# 0 - 8 bit + * -# 1 - 16 bit + * -# 2 - 32 bit + * -# 3 - 64 bit + * -# 4 - 128 bit + * -# 5 - 256 bit + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant for unique lCh values. It is non- + * re-entrant for same lCh value. + */ +EDMA3_DRV_Result EDMA3_DRV_setSrcParams (EDMA3_DRV_Handle hEdma, + unsigned int lCh, + unsigned int srcAddr, + EDMA3_DRV_AddrMode addrMode, + EDMA3_DRV_FifoWidth fifoWidth) + { + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + unsigned int opt = 0; + EDMA3_DRV_Instance *drvInst = NULL; + EDMA3_DRV_Object *drvObject = NULL; + int paRAMId = 0; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + unsigned int mappedEvtQ = 0; + unsigned int defaultBurstSize = 0; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if ((((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL)) + || ((addrMode < EDMA3_DRV_ADDR_MODE_INCR) || (addrMode > EDMA3_DRV_ADDR_MODE_FIFO))) + || ((fifoWidth < EDMA3_DRV_W8BIT) || (fifoWidth > EDMA3_DRV_W256BIT))) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + + /** In FIFO Addressing mode, memory location must be 32 bytes aligned */ + if ((addrMode == EDMA3_DRV_ADDR_MODE_FIFO) + && ((srcAddr & 0x1Fu) != NULL)) + { + /** Memory is not 32 bytes aligned */ + result = EDMA3_DRV_E_ADDRESS_NOT_ALIGNED; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_DRV_SOK == result) + { + drvInst = (EDMA3_DRV_Instance *)hEdma; + drvObject = drvInst->pDrvObjectHandle; + + if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId; + globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs); + + if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + + if (result == EDMA3_DRV_SOK) + { + /** + * If request is for FIFO mode, check whether the FIFO size + * is supported by the Transfer Controller which will be used for + * this transfer or not. + */ + if (addrMode == EDMA3_DRV_ADDR_MODE_FIFO) + { + if (lCh <= EDMA3_DRV_DMA_CH_MAX_VAL) + { + mappedEvtQ = ((globalRegs->DMAQNUM[lCh >> 3u]) + & (~(EDMA3_DRV_DMAQNUM_CLR_MASK(lCh)))) + >> ((lCh%8u)*4u); + } + else + { + if ((lCh >= EDMA3_DRV_QDMA_CH_MIN_VAL) + &&(lCh <= EDMA3_DRV_QDMA_CH_MAX_VAL)) + { + mappedEvtQ = ((globalRegs->QDMAQNUM) + & (~(EDMA3_DRV_QDMAQNUM_CLR_MASK(lCh -EDMA3_DRV_QDMA_CH_MIN_VAL)))) + >> (lCh*4u); + } + } + + /** + * mappedEvtQ contains the event queue and hence the TC which will + * process this transfer request. Check whether this TC supports the + * FIFO size or not. + */ + defaultBurstSize = 1u << fifoWidth; + if (defaultBurstSize > drvObject->gblCfgParams.tcDefaultBurstSize[mappedEvtQ]) + { + result = EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED; + } + } + + if (EDMA3_DRV_SOK == result) + { + /* Set Src Address */ + *((&globalRegs->PARAMENTRY[paRAMId].OPT) + + (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC) = srcAddr; + + opt = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAMId].OPT)); + + /* Set SAM */ + opt &= EDMA3_DRV_OPT_SAM_CLR_MASK; + opt |= EDMA3_DRV_OPT_SAM_SET_MASK(addrMode); + /* Set FIFO Width */ + opt &= EDMA3_DRV_OPT_FWID_CLR_MASK; + opt |= EDMA3_DRV_OPT_FWID_SET_MASK(fifoWidth); + + /* Set the OPT */ + *(&globalRegs->PARAMENTRY[paRAMId].OPT) = opt; + } + } + } + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + + +/** + * \brief DMA Destination parameters setup + * + * It is used to program the destination address, destination side addressing + * mode (INCR or FIFO) and the FIFO width in case the addressing mode is FIFO. + * + * In FIFO Addressing mode, memory location must be 32 bytes aligned. + * + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param lCh [IN] Logical Channel for which the destination + * parameters are to be configured + * \param destAddr [IN] Destination address + * \param addrMode [IN] Address mode [FIFO or Increment] + * \param fifoWidth [IN] Width of FIFO (Valid only if addrMode is FIFO) + * -# 0 - 8 bit + * -# 1 - 16 bit + * -# 2 - 32 bit + * -# 3 - 64 bit + * -# 4 - 128 bit + * -# 5 - 256 bit + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant for unique lCh values. It is non- + * re-entrant for same lCh value. + */ +EDMA3_DRV_Result EDMA3_DRV_setDestParams (EDMA3_DRV_Handle hEdma, + unsigned int lCh, + unsigned int destAddr, + EDMA3_DRV_AddrMode addrMode, + EDMA3_DRV_FifoWidth fifoWidth) + { + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + unsigned int opt = 0; + EDMA3_DRV_Instance *drvInst = NULL; + EDMA3_DRV_Object *drvObject = NULL; + int paRAMId = 0; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + unsigned int mappedEvtQ = 0; + unsigned int defaultBurstSize = 0; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if ((((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL)) + || ((addrMode < EDMA3_DRV_ADDR_MODE_INCR) || (addrMode > EDMA3_DRV_ADDR_MODE_FIFO))) + || ((fifoWidth < EDMA3_DRV_W8BIT) || (fifoWidth > EDMA3_DRV_W256BIT))) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + + /** In FIFO Addressing mode, memory location must be 32 bytes aligned */ + if ((addrMode == EDMA3_DRV_ADDR_MODE_FIFO) + && ((destAddr & 0x1Fu)!=NULL)) + { + /** Memory is not 32 bytes aligned */ + result = EDMA3_DRV_E_ADDRESS_NOT_ALIGNED; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_DRV_SOK == result) + { + drvInst = (EDMA3_DRV_Instance *)hEdma; + drvObject = drvInst->pDrvObjectHandle; + + if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId; + globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs); + + if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + + if (result == EDMA3_DRV_SOK) + { + /** + * If request is for FIFO mode, check whether the FIFO size + * is supported by the Transfer Controller which will be used for + * this transfer or not. + */ + if (addrMode == EDMA3_DRV_ADDR_MODE_FIFO) + { + if (lCh <= EDMA3_DRV_DMA_CH_MAX_VAL) + { + mappedEvtQ = ((globalRegs->DMAQNUM[lCh >> 3u]) + & (~(EDMA3_DRV_DMAQNUM_CLR_MASK(lCh)))) + >> ((lCh%8u)*4u); + } + else + { + if ((lCh >= EDMA3_DRV_QDMA_CH_MIN_VAL) + &&(lCh <= EDMA3_DRV_QDMA_CH_MAX_VAL)) + { + mappedEvtQ = ((globalRegs->QDMAQNUM) + & (~(EDMA3_DRV_QDMAQNUM_CLR_MASK(lCh -EDMA3_DRV_QDMA_CH_MIN_VAL)))) + >> (lCh*4u); + } + } + + /** + * mappedEvtQ contains the event queue and hence the TC which will + * process this transfer request. Check whether this TC supports the + * FIFO size or not. + */ + defaultBurstSize = 1u << fifoWidth; + if (defaultBurstSize > drvObject->gblCfgParams.tcDefaultBurstSize[mappedEvtQ]) + { + result = EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED; + } + } + + if (EDMA3_DRV_SOK == result) + { + /* Set the Dest address */ + *((&globalRegs->PARAMENTRY[paRAMId].OPT) + + (unsigned int)EDMA3_DRV_PARAM_ENTRY_DST) = destAddr; + + opt = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAMId].OPT)); + + /* Set DAM */ + opt &= EDMA3_DRV_OPT_DAM_CLR_MASK; + opt |= EDMA3_DRV_OPT_DAM_SET_MASK(addrMode); + /* Set FIFO Width */ + opt &= EDMA3_DRV_OPT_FWID_CLR_MASK; + opt |= EDMA3_DRV_OPT_FWID_SET_MASK(fifoWidth); + + /* Set the OPT */ + *(&globalRegs->PARAMENTRY[paRAMId].OPT) = opt; + } + } + } + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + + +/** + * \brief DMA source index setup + * + * It is used to program the source B index and source C index. + * + * SRCBIDX is a 16-bit signed value (2s complement) used for source address + * modification between each array in the 2nd dimension. Valid values for + * SRCBIDX are between -32768 and 32767. It provides a byte address offset + * from the beginning of the source array to the beginning of the next source + * array. It applies to both A-synchronized and AB-synchronized transfers. + * + * SRCCIDX is a 16-bit signed value (2s complement) used for source address + * modification in the 3rd dimension. Valid values for SRCCIDX are between + * -32768 and 32767. It provides a byte address offset from the beginning of + * the current array (pointed to by SRC address) to the beginning of the first + * source array in the next frame. It applies to both A-synchronized and + * AB-synchronized transfers. Note that when SRCCIDX is applied, the current + * array in an A-synchronized transfer is the last array in the frame, while + * the current array in an AB-synchronized transfer is the first array in the + * frame. + * + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param lCh [IN] Logical Channel for which source + * indices are to be configured + * \param srcBIdx [IN] Source B index + * \param srcCIdx [IN] Source C index + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant for unique lCh values. It is non- + * re-entrant for same lCh value. + */ +EDMA3_DRV_Result EDMA3_DRV_setSrcIndex (EDMA3_DRV_Handle hEdma, + unsigned int lCh, + int srcBIdx, int srcCIdx) + { + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + unsigned int srcDstBidx; + unsigned int srcDstCidx; + EDMA3_DRV_Instance *drvInst = NULL; + EDMA3_DRV_Object *drvObject = NULL; + int paRAMId = 0; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if ((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + + if (((srcBIdx > EDMA3_DRV_SRCBIDX_MAX_VAL) + || (srcBIdx < EDMA3_DRV_SRCBIDX_MIN_VAL)) + || ((srcCIdx > EDMA3_DRV_SRCCIDX_MAX_VAL) + || (srcCIdx < EDMA3_DRV_SRCCIDX_MIN_VAL))) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_DRV_SOK == result) + { + drvInst = (EDMA3_DRV_Instance *)hEdma; + drvObject = drvInst->pDrvObjectHandle; + + if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId; + globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs); + + if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + + if (result == EDMA3_DRV_SOK) + { + /* Get SrcDestBidx PaRAM Set entry */ + srcDstBidx = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + + (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX)); + + srcDstBidx &= 0xFFFF0000u; + /* Update it */ + srcDstBidx |= (unsigned int)(srcBIdx & 0xFFFF); + + /* Store it back */ + *((&globalRegs->PARAMENTRY[paRAMId].OPT) + + (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX) = srcDstBidx; + + /* Get SrcDestCidx PaRAM Set entry */ + srcDstCidx = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + + (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX)); + + srcDstCidx &= 0xFFFF0000u; + /* Update it */ + srcDstCidx |= (unsigned int)(srcCIdx & 0xFFFF); + + /* Store it back */ + *((&globalRegs->PARAMENTRY[paRAMId].OPT) + + (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX) = srcDstCidx; + } + } + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + + +/** + * \brief DMA destination index setup + * + * It is used to program the destination B index and destination C index. + * + * DSTBIDX is a 16-bit signed value (2s complement) used for destination + * address modification between each array in the 2nd dimension. Valid values + * for DSTBIDX are between -32768 and 32767. It provides a byte address offset + * from the beginning of the destination array to the beginning of the next + * destination array within the current frame. It applies to both + * A-synchronized and AB-synchronized transfers. + * + * DSTCIDX is a 16-bit signed value (2s complement) used for destination address + * modification in the 3rd dimension. Valid values are between -32768 and 32767. + * It provides a byte address offset from the beginning of the current array + * (pointed to by DST address) to the beginning of the first destination array + * TR in the next frame. It applies to both A-synchronized and AB-synchronized + * transfers. Note that when DSTCIDX is applied, the current array in an + * A-synchronized transfer is the last array in the frame, while the current + * array in a AB-synchronized transfer is the first array in the frame + * + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param lCh [IN] Logical Channel for which dest + * indices are to be configured + * \param destBIdx [IN] Destination B index + * \param destCIdx [IN] Destination C index + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant for unique lCh values. It is non- + * re-entrant for same lCh value. + */ +EDMA3_DRV_Result EDMA3_DRV_setDestIndex (EDMA3_DRV_Handle hEdma, unsigned int lCh, + int destBIdx, int destCIdx) + { + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + unsigned int srcDstBidx; + unsigned int srcDstCidx; + EDMA3_DRV_Instance *drvInst = NULL; + EDMA3_DRV_Object *drvObject = NULL; + int paRAMId = 0; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if ((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + + if (((destBIdx > EDMA3_DRV_DSTBIDX_MAX_VAL) + || (destBIdx < EDMA3_DRV_DSTBIDX_MIN_VAL)) + || ((destCIdx > EDMA3_DRV_DSTCIDX_MAX_VAL) + || (destCIdx < EDMA3_DRV_DSTCIDX_MIN_VAL))) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_DRV_SOK == result) + { + drvInst = (EDMA3_DRV_Instance *)hEdma; + drvObject = drvInst->pDrvObjectHandle; + + if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId; + globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs); + + if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + + if (result == EDMA3_DRV_SOK) + { + /* Get SrcDestBidx PaRAM Set entry */ + srcDstBidx = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + + (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX)); + + srcDstBidx &= 0xFFFFu; + /* Update it */ + srcDstBidx |= (unsigned int)((destBIdx & 0xFFFF) << 16u); + + /* Store it back */ + *((&globalRegs->PARAMENTRY[paRAMId].OPT) + + (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX) = srcDstBidx; + + /* Get SrcDestCidx PaRAM Set entry */ + srcDstCidx = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + + (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX)); + + srcDstCidx &= 0xFFFFu; + /* Update it */ + srcDstCidx |= (unsigned int)((destCIdx & 0xFFFF) << 16u); + + /* Store it back */ + *((&globalRegs->PARAMENTRY[paRAMId].OPT) + + (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX) = srcDstCidx; + } + } + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + +/** + * \brief DMA transfer parameters setup + * + * It is used to specify the various counts (ACNT, BCNT and CCNT), B count + * reload and the synchronization type + * + * ACNT represents the number of bytes within the 1st dimension of a transfer. + * ACNT is a 16-bit unsigned value with valid values between 0 and 65535. + * Therefore, the maximum number of bytes in an array is 65535 bytes (64K - 1 + * bytes). ACNT must be greater than or equal to 1 for a TR to be submitted to + * EDMA3 Transfer Controller. + * An ACNT equal to 0 is considered either a null or dummy transfer. A dummy or + * null transfer generates a completion code depending on the settings of the + * completion bit fields in OPT. + + * BCNT is a 16-bit unsigned value that specifies the number of arrays of length + * ACNT. For normal operation, valid values for BCNT are between 1 and 65535. + * Therefore, the maximum number of arrays in a frame is 65535 (64K - 1 arrays). + * A BCNT equal to 0 is considered either a null or dummy transfer. A dummy or + * null transfer generates a completion code depending on the settings of the + * completion bit fields in OPT. + * + * CCNT is a 16-bit unsigned value that specifies the number of frames in a + * block. Valid values for CCNT are between 1 and 65535. Therefore, the maximum + * number of frames in a block is 65535 (64K - 1 frames). A CCNT equal to 0 is + * considered either a null or dummy transfer. A dummy or null transfer + * generates a completion code depending on the settings of the completion bit + * fields in OPT. A CCNT value of 0 is considered either a null or dummy + * transfer. + * + * BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the + * last array in the 2nd dimension is transferred. This field is only used for + * A-synchronized transfers. In this case, the EDMA3CC decrements the BCNT + * value by 1 on each TR submission. When BCNT (conceptually) reaches 0, the + * EDMA3CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT + * value. + * For AB-synchronized transfers, the EDMA3CC submits the BCNT in the TR and the + * EDMA3TC decrements BCNT appropriately. For AB-synchronized transfers, + * BCNTRLD is not used. + + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param lCh [IN] Logical Channel for which transfer + * parameters are to be configured + * \param aCnt [IN] Count for 1st Dimension. + * \param bCnt [IN] Count for 2nd Dimension. + * \param cCnt [IN] Count for 3rd Dimension. + * \param bCntReload [IN] Reload value for bCnt. + * \param syncType [IN] Transfer synchronization dimension + * 0: A-synchronized. Each event triggers + * the transfer of a single array of + * ACNT bytes. + * 1: AB-synchronized. Each event triggers + * the transfer of BCNT arrays of ACNT + * bytes. + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant for unique lCh values. It is non- + * re-entrant for same lCh value. + */ +EDMA3_DRV_Result EDMA3_DRV_setTransferParams (EDMA3_DRV_Handle hEdma, + unsigned int lCh, unsigned int aCnt, unsigned int bCnt, unsigned int cCnt, + unsigned int bCntReload, EDMA3_DRV_SyncType syncType) + { + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + unsigned int abCnt = 0; + unsigned int linkBCntReld = 0; + unsigned int opt = 0; + EDMA3_DRV_Instance *drvInst = NULL; + EDMA3_DRV_Object *drvObject = NULL; + int paRAMId = 0; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if ((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + + if ((((aCnt > EDMA3_DRV_ACNT_MAX_VAL) + || (bCnt > EDMA3_DRV_BCNT_MAX_VAL)) + || ((cCnt > EDMA3_DRV_CCNT_MAX_VAL) + || (bCntReload > EDMA3_DRV_BCNTRELD_MAX_VAL))) + || ((syncType < EDMA3_DRV_SYNC_A) || (syncType > EDMA3_DRV_SYNC_AB))) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_DRV_SOK == result) + { + drvInst = (EDMA3_DRV_Instance *)hEdma; + drvObject = drvInst->pDrvObjectHandle; + + if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + abCnt = aCnt | ((bCnt&0xFFFFu) << 16u); + paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId; + globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs); + + if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + + if (result == EDMA3_DRV_SOK) + { + /* Set aCnt and bCnt */ + *((&globalRegs->PARAMENTRY[paRAMId].OPT) + + (unsigned int)EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT) = abCnt; + + /* Set cCnt */ + *((&globalRegs->PARAMENTRY[paRAMId].OPT) + + (unsigned int)EDMA3_DRV_PARAM_ENTRY_CCNT) = cCnt; + + + linkBCntReld = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + + (unsigned int)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD)); + + linkBCntReld |= ((bCntReload & 0xFFFFu) << 16u); + + /* Set bCntReload */ + *((&globalRegs->PARAMENTRY[paRAMId].OPT) + + (unsigned int)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD) = linkBCntReld; + + opt = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAMId].OPT)); + + /* Set Sync Type */ + opt &= EDMA3_DRV_OPT_SYNCDIM_CLR_MASK; + opt |= EDMA3_DRV_OPT_SYNCDIM_SET_MASK(syncType); + + *(&globalRegs->PARAMENTRY[paRAMId].OPT) = opt; + } + } + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + +/** + * \brief Start EDMA transfer on the specified channel. + * + * There are multiple ways to trigger an EDMA3 transfer. The triggering mode + * option allows choosing from the available triggering modes: Event, + * Manual or QDMA. + * + * In event triggered, a peripheral or an externally generated event triggers + * the transfer. This API clears the Event and Event Miss Register and then + * enables the DMA channel by writing to the EESR. + * + * In manual triggered mode, CPU manually triggers a transfer by writing a 1 + * in the Event Set Register (ESR/ESRH). This API writes to the ESR/ESRH to + * start the transfer. + * + * In QDMA triggered mode, a QDMA transfer is triggered when a CPU (or other + * EDMA3 programmer) writes to the trigger word of the QDMA channel PaRAM set + * (auto-triggered) or when the EDMA3CC performs a link update on a PaRAM set + * that has been mapped to a QDMA channel (link triggered). This API enables + * the QDMA channel by writing to the QEESR register. + * + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param lCh [IN] Channel on which transfer has to be started + * \param trigMode [IN] Mode of triggering start of transfer (Manual, + * QDMA or Event) + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant for unique lCh values. It is non- + * re-entrant for same lCh value. + */ +EDMA3_DRV_Result EDMA3_DRV_enableTransfer (EDMA3_DRV_Handle hEdma, + unsigned int lCh, + EDMA3_DRV_TrigMode trigMode) + { + EDMA3_DRV_Instance *drvInst = NULL; + EDMA3_DRV_Object *drvObject = NULL; + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if ((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + + /* Trigger type is Manual */ + if ((EDMA3_DRV_TRIG_MODE_MANUAL == trigMode) + && (lCh > EDMA3_DRV_DMA_CH_MAX_VAL)) + { + /* Channel Id lies outside DMA channel range */ + result = EDMA3_DRV_E_INVALID_PARAM; + } + + /* Trigger type is QDMA */ + if ((EDMA3_DRV_TRIG_MODE_QDMA == trigMode) + && ((lCh < EDMA3_DRV_QDMA_CH_MIN_VAL) + || (lCh > EDMA3_DRV_QDMA_CH_MAX_VAL))) + { + /* Channel Id lies outside QDMA channel range */ + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_DRV_SOK == result) + { + drvInst = (EDMA3_DRV_Instance *)hEdma; + drvObject = drvInst->pDrvObjectHandle; + + if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs); + + switch (trigMode) + { + case EDMA3_DRV_TRIG_MODE_MANUAL : + { + if (lCh < 32u) + { + drvInst->shadowRegs->ESR = (1UL << lCh); + } + else + { + drvInst->shadowRegs->ESRH = (1UL << (lCh-32u)); + } + edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].trigMode = EDMA3_DRV_TRIG_MODE_MANUAL; + } + break; + + case EDMA3_DRV_TRIG_MODE_QDMA : + { + drvInst->shadowRegs->QEESR = (1u<<(lCh - EDMA3_DRV_QDMA_CH_MIN_VAL)); + edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].trigMode = EDMA3_DRV_TRIG_MODE_QDMA; + } + break; + + case EDMA3_DRV_TRIG_MODE_EVENT : + { + /* Trigger type is Event */ +/* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if (((drvObject->gblCfgParams.dmaChannelHwEvtMap [lCh/32u] + & (1u<<(lCh%32u))) == FALSE)) + { + /* Channel was not mapped to any Hw Event. */ + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + if (EDMA3_DRV_SOK == result) + { + if (lCh < 32u) + { + /*clear SECR to clean any previous NULL request */ + drvInst->shadowRegs->SECR = (1UL << lCh); + + /*clear EMCR to clean any previous NULL request */ + globalRegs->EMCR = (1UL << lCh); + + drvInst->shadowRegs->EESR = (1UL << lCh); + } + else + { + /*clear SECR to clean any previous NULL request */ + drvInst->shadowRegs->SECRH = (1UL << (lCh-32u)); + + /*clear EMCR to clean any previous NULL request */ + globalRegs->EMCRH = (1UL << (lCh-32u)); + + drvInst->shadowRegs->EESRH = (1UL << (lCh-32u)); + } + + edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].trigMode = EDMA3_DRV_TRIG_MODE_EVENT; + } + } + break; + + default : + result = EDMA3_DRV_E_INVALID_PARAM; + break; + } + } + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + +/** + * \brief Disable DMA transfer on the specified channel + * + * There are multiple ways by which an EDMA3 transfer could be triggered. + * The triggering mode option allows choosing from the available triggering + * modes: Event, Manual or QDMA. + * + * To disable a channel which was previously triggered in manual mode, + * this API clears the Secondary Event Register and Event Miss Register, + * if set, for the specific DMA channel. + * + * To disable a channel which was previously triggered in QDMA mode, this + * API clears the QDMA Even Enable Register, for the specific QDMA channel. + * + * To disable a channel which was previously triggered in event mode, this API + * clears the Event Enable Register, Event Register, Secondary Event Register + * and Event Miss Register, if set, for the specific DMA channel. + + * \param hEdma [IN] Handle to the EDMA Driver Instance + * \param lCh [IN] Channel on which transfer has to be stopped + * \param trigMode [IN] Mode of triggering start of transfer + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code + * + * \note This function is re-entrant for unique lCh values. It is non- + * re-entrant for same lCh value. + */ +EDMA3_DRV_Result EDMA3_DRV_disableTransfer (EDMA3_DRV_Handle hEdma, + unsigned int lCh, EDMA3_DRV_TrigMode trigMode) +{ + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + EDMA3_DRV_Instance *drvInst = NULL; + EDMA3_DRV_Object *drvObject = NULL; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if ((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + + /* Trigger type is Manual */ + if ((EDMA3_DRV_TRIG_MODE_MANUAL == trigMode) + && (lCh > EDMA3_DRV_DMA_CH_MAX_VAL)) + { + /* Channel Id lies outside DMA channel range */ + result = EDMA3_DRV_E_INVALID_PARAM; + } + + /* Trigger type is QDMA */ + if ((EDMA3_DRV_TRIG_MODE_QDMA == trigMode) + && ((lCh < EDMA3_DRV_QDMA_CH_MIN_VAL) + || (lCh > EDMA3_DRV_QDMA_CH_MAX_VAL))) + { + /* Channel Id lies outside QDMA channel range */ + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_DRV_SOK == result) + { + drvInst = (EDMA3_DRV_Instance *)hEdma; + drvObject = drvInst->pDrvObjectHandle; + + if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs); + + switch (trigMode) + { + case EDMA3_DRV_TRIG_MODE_MANUAL : + { + if (lCh < 32u) + { + if((drvInst->shadowRegs->SER & (1u<shadowRegs->SECR = (1u<EMR & (1u<EMCR = (1u<shadowRegs->SERH & (1u<<(lCh-32u)))!=FALSE) + { + drvInst->shadowRegs->SECRH = (1u<<(lCh-32u)); + } + + if((globalRegs->EMRH & (1u<<(lCh-32u)))!=FALSE) + { + globalRegs->EMCRH = (1u<<(lCh-32u)); + } + } + } + break; + + case EDMA3_DRV_TRIG_MODE_QDMA : + { + drvInst->shadowRegs->QEECR = (1u<<(lCh - EDMA3_DRV_QDMA_CH_MIN_VAL)); + } + break; + + case EDMA3_DRV_TRIG_MODE_EVENT : + { + /* Trigger type is Event */ +/* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if (((drvObject->gblCfgParams.dmaChannelHwEvtMap [lCh/32u] + & (1u<<(lCh%32u))) == FALSE)) + { + /* Channel was not mapped to any Hw Event. */ + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + if (EDMA3_DRV_SOK == result) + { + if (lCh < 32u) + { + drvInst->shadowRegs->EECR = (1u << lCh); + + if((drvInst->shadowRegs->ER & (1u<shadowRegs->ECR = (1u<shadowRegs->SER & (1u<shadowRegs->SECR = (1u<EMR & (1u<EMCR = (1u<shadowRegs->EECRH = (1u << (lCh-32u)); + if((drvInst->shadowRegs->ERH & (1u<<(lCh-32u)))!=FALSE) + { + drvInst->shadowRegs->ECRH = (1u<<(lCh-32u)); + } + + if((drvInst->shadowRegs->SERH & (1u<<(lCh-32u)))!=FALSE) + { + drvInst->shadowRegs->SECRH = (1u<<(lCh-32u)); + } + + if((globalRegs->EMRH & (1u<<(lCh-32u)))!=FALSE) + { + globalRegs->EMCRH = (1u<<(lCh-32u)); + } + } + } + } + break; + + default : + result = EDMA3_DRV_E_INVALID_PARAM; + break; + } + } + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + + +/* Definitions of Local functions - Start */ +/** Remove various mappings and do cleanup for DMA/QDMA channels */ +static EDMA3_DRV_Result edma3RemoveMapping (EDMA3_DRV_Handle hEdma, + unsigned int channelId) + { + unsigned int intState; + EDMA3_DRV_Instance *drvInst = NULL; + EDMA3_DRV_Object *drvObject = NULL; + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + EDMA3_RM_ResDesc channelObj; + + assert ((hEdma != NULL) && (channelId <= EDMA3_DRV_LOG_CH_MAX_VAL)); + + drvInst = (EDMA3_DRV_Instance *)hEdma; + drvObject = drvInst->pDrvObjectHandle; + + if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + globalRegs = (volatile EDMA3_CCRL_Regs *) + (drvObject->gblCfgParams.globalRegs); + + /** + * Disable any ongoing transfer on the channel, if transfer was + * enabled earlier. + */ + if (EDMA3_DRV_TRIG_MODE_NONE != + edma3DrvChBoundRes[drvObject->phyCtrllerInstId][channelId].trigMode) + { + result = EDMA3_DRV_disableTransfer(hEdma, channelId, + edma3DrvChBoundRes[drvObject->phyCtrllerInstId][channelId].trigMode); + } + + if (result == EDMA3_DRV_SOK) + { + /* + * Unregister the TCC Callback function and disable the interrupts. + */ + if (channelId < drvObject->gblCfgParams.numDmaChannels) + { + /* DMA channel */ + channelObj.type = EDMA3_RM_RES_DMA_CHANNEL; + channelObj.resId = channelId; + } + else + { + /* QDMA channel */ + channelObj.type = EDMA3_RM_RES_QDMA_CHANNEL; + channelObj.resId = channelId - EDMA3_DRV_QDMA_CH_MIN_VAL; + } + + result = EDMA3_RM_unregisterTccCb(drvInst->resMgrInstance, + (EDMA3_RM_ResDesc *)&channelObj); + + if (result == EDMA3_RM_SOK) + { + edma3OsProtectEntry(EDMA3_OS_PROTECT_INTERRUPT, &intState); + + if (channelId <= EDMA3_DRV_DMA_CH_MAX_VAL) + { + /* DMA channel */ + /* Remove the channel to Event Queue mapping */ + globalRegs->DMAQNUM[channelId >> 3u] &= + EDMA3_DRV_DMAQNUM_CLR_MASK(channelId); + + /** + * If DMA channel to PaRAM Set mapping exists, + * remove it too. + */ + if (TRUE == drvObject->gblCfgParams.dmaChPaRAMMapExists) + { + globalRegs->DCHMAP[channelId] &= + EDMA3_RM_DCH_PARAM_CLR_MASK; + } + } + else + { + /* QDMA channel */ + /* Remove the channel to Event Queue mapping */ + globalRegs->QDMAQNUM = (globalRegs->QDMAQNUM) & + (EDMA3_DRV_QDMAQNUM_CLR_MASK(channelId-EDMA3_DRV_QDMA_CH_MIN_VAL)); + + /* Remove the channel to PARAM set mapping */ + /* Unmap PARAM Set Number for specified channelId */ + globalRegs->QCHMAP[channelId-EDMA3_DRV_QDMA_CH_MIN_VAL] &= + EDMA3_RM_QCH_PARAM_CLR_MASK; + + /* Reset the Trigger Word */ + globalRegs->QCHMAP[channelId-EDMA3_DRV_QDMA_CH_MIN_VAL] &= + EDMA3_RM_QCH_TRWORD_CLR_MASK; + } + + edma3OsProtectExit(EDMA3_OS_PROTECT_INTERRUPT, intState); + } + } + } + + return result; + } +/* Definitions of Local functions - End */ + +/* End of File */ diff --git a/packages/ti/sdo/edma3/drv/src/edma3_drv_init.c b/packages/ti/sdo/edma3/drv/src/edma3_drv_init.c new file mode 100644 index 0000000..5b37ed9 --- /dev/null +++ b/packages/ti/sdo/edma3/drv/src/edma3_drv_init.c @@ -0,0 +1,738 @@ +/******************************************************************************* +**+--------------------------------------------------------------------------+** +**| **** |** +**| **** |** +**| ******o*** |** +**| ********_///_**** |** +**| ***** /_//_/ **** |** +**| ** ** (__/ **** |** +**| ********* |** +**| **** |** +**| *** |** +**| |** +**| Copyright (c) 1998-2006 Texas Instruments Incorporated |** +**| ALL RIGHTS RESERVED |** +**| |** +**| Permission is hereby granted to licensees of Texas Instruments |** +**| Incorporated (TI) products to use this computer program for the sole |** +**| purpose of implementing a licensee product based on TI products. |** +**| No other rights to reproduce, use, or disseminate this computer |** +**| program, whether in part or in whole, are granted. |** +**| |** +**| TI makes no representation or warranties with respect to the |** +**| performance of this computer program, and specifically disclaims |** +**| any responsibility for any damages, special or consequential, |** +**| connected with the use of this program. |** +**| |** +**+--------------------------------------------------------------------------+** +*******************************************************************************/ + +/** +* \file edma3_drv_init.c +* +* \brief EDMA3 Driver Initialization Interface Implementation +* This file contains EDMA3 Driver APIs used to: +* a) Create/delete EDMA3 Driver Object +* b) Open/close EDMA3 Driver Instance. +* These APIs are required to initialize EDMA3 properly. +* +* @author: PSP Team, TII +* +*/ + + +/* EDMa3 Driver Internal Header Files */ +#include +/* Resource Manager Internal Header Files */ +#include + +/* For assert() */ +/** + * Define NDEBUG to ignore assert(). + * NDEBUG should be defined before including assert.h header file. + */ +#include + + +/* Externel Variables */ +/*---------------------------------------------------------------------------*/ +/** + * Maximum Resource Manager Instances supported by the EDMA3 Package. + */ +extern const unsigned int EDMA3_MAX_RM_INSTANCES; + + +/** + * \brief EDMA3 Resource Manager Objects, tied to each EDMA3 HW Controller. + * + * Typically one RM object will cater to one EDMA3 HW controller + * and will have all the global config information. + */ +extern EDMA3_RM_Obj resMgrObj[EDMA3_MAX_EDMA3_INSTANCES]; + + +/** + * \brief Region Specific Configuration structure for + * EDMA3 controller, to provide region specific Information. + * + * This configuration info can also be provided by the user at run-time, + * while calling EDMA3_RM_open (). If not provided at run-time, + * this info will be taken from the config file "edma3__cfg.c", + * for the specified platform. + */ +extern EDMA3_RM_InstanceInitConfig *ptrInitCfgArray; + + +/** + * Handles of EDMA3 Resource Manager Instances. + * + * Used to maintain information of the EDMA3 RM Instances + * for each HW controller. + * There could be a maximum of EDMA3_MAX_RM_INSTANCES instances per + * EDMA3 HW. + */ +// extern EDMA3_RM_Instance *resMgrInstance; +extern EDMA3_RM_Instance *ptrRMIArray; + +/** Local MemSet function */ +extern void edma3MemSet(void *dst, unsigned char data, unsigned int len); +/** Local MemCpy function */ +extern void edma3MemCpy(void *dst, const void *src, unsigned int len); + +/** + * \brief EDMA3 Driver Objects, tied to each EDMA3 HW Controller. + * + * Typically one object will cater to one EDMA3 HW controller + * and will have all regions' (ARM, DSP etc) specific config information. + */ +EDMA3_DRV_Object drvObj [EDMA3_MAX_EDMA3_INSTANCES]; + + +/** + * Handles of EDMA3 Driver Instances. + * + * Used to maintain information of the EDMA3 Driver Instances for + * each region, for each HW controller. + * There could be as many Driver Instances as there are shadow + * regions. Multiple EDMA3 Driver instances on the same shadow + * region are NOT allowed. + */ +EDMA3_DRV_Instance drvInstance [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS]; + + +/** + * \brief Resources bound to a Channel + * + * When a request for a channel is made, the resources PaRAM Set and TCC + * get bound to that channel. This information is needed internally by the + * driver when a request is made to free the channel (Since it is the + * responsibility of the driver to free up the channel-associated resources + * from the Resource Manager layer). + */ +EDMA3_DRV_ChBoundResources edma3DrvChBoundRes [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_LOGICAL_CH]; + + + +/* Local functions prototypes */ +/*---------------------------------------------------------------------------*/ +/** + * Local function to prepare the init config structure for + * open of Resource Manager + */ +static EDMA3_DRV_Result edma3OpenResMgr (unsigned int instId, + unsigned int regionId, + unsigned short flag); + +/*---------------------------------------------------------------------------*/ + + + +/** + * \brief Create EDMA3 Driver Object + * + * This API is used to create the EDMA3 Driver Object. It should be + * called only ONCE for each EDMA3 hardware instance. + * + * Init-time Configuration structure for EDMA3 hardware is provided to pass the + * SoC specific information. This configuration information could be provided + * by the user at init-time. In case user doesn't provide it, this information + * could be taken from the SoC specific configuration file + * edma3__cfg.c, in case it is available. + * + * This API clears the error specific registers (EMCR/EMCRh, QEMCR, CCERRCLR) + * and sets the TCs priorities and Event Queues' watermark levels, if the 'miscParam' + * argument is NULL. User can avoid these registers' programming (in some specific + * use cases) by SETTING the 'isSlave' field of 'EDMA3_RM_MiscParam' configuration + * structure and passing this structure as the third argument (miscParam). + * + * After successful completion of this API, Driver Object's state + * changes to EDMA3_DRV_CREATED from EDMA3_DRV_DELETED. + * + * \param phyCtrllerInstId [IN] EDMA3 Controller Instance Id + * (Hardware instance id, starting from 0). + * \param gblCfgParams [IN] SoC specific configuration structure for the + * EDMA3 Hardware. + * \param miscParam [IN] Misc configuration options provided in the + * structure 'EDMA3_DRV_MiscParam'. + * For default options, user can pass NULL + * in this argument. + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error code + */ +EDMA3_DRV_Result EDMA3_DRV_create (unsigned int phyCtrllerInstId, + const EDMA3_DRV_GblConfigParams *gblCfgParams, + const void *miscParam) + { + unsigned int count = 0; + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + EDMA3_RM_GblConfigParams rmGblCfgParams; + /** + * Used to reset the Internal EDMA3 Driver Data Structures for the first time. + */ + static unsigned short drvInitDone = FALSE; + + /** + * We are NOT checking 'gblCfgParams' for NULL. Whatever user has passed + * is given to RM. If user passed NULL, config info from config file will be + * taken else user specific info will be passed to the RM. + * Similarly, 'miscParam' is not being checked and passed as it is to the + * Resource Manager layer. + */ + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if (phyCtrllerInstId >= EDMA3_MAX_EDMA3_INSTANCES) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_DRV_SOK == result) + { + /* Initialize the global variables for the first time */ + if (FALSE == drvInitDone) + { + for (count = 0; count < EDMA3_MAX_EDMA3_INSTANCES; count++) + { + edma3MemSet((void *)&(drvObj[count]) , 0x00u, + sizeof(EDMA3_DRV_Object)); + } + drvInitDone = TRUE; + } + + /* Initialization has been done */ + if (drvObj[phyCtrllerInstId].state != EDMA3_DRV_DELETED) + { + result = EDMA3_DRV_E_OBJ_NOT_DELETED; + } + else + { + if (NULL != gblCfgParams) + { + /* User has passed the configuration info */ + /* copy the global info */ + edma3MemCpy((void *)(&drvObj[phyCtrllerInstId].gblCfgParams), + (const void *)(gblCfgParams), + sizeof (EDMA3_DRV_GblConfigParams)); + + /* Reset the RM global info struct first */ + edma3MemSet((void *)&(rmGblCfgParams) , + 0x00u, + sizeof (EDMA3_RM_GblConfigParams)); + + /* Fill the RM global info struct with the DRV global info */ + edma3MemCpy((void *)(&rmGblCfgParams), + (const void *)(&drvObj[phyCtrllerInstId].gblCfgParams), + sizeof (EDMA3_RM_GblConfigParams)); + + result = EDMA3_RM_create(phyCtrllerInstId, (EDMA3_RM_GblConfigParams *)&rmGblCfgParams, miscParam); + } + else + { + /* User has not passed any global info. */ + result = EDMA3_RM_create(phyCtrllerInstId, NULL, miscParam); + + if (EDMA3_RM_SOK == result) + { + /** + * Copy the global config info from the RM object to the + * driver object for future use. + */ + /* Fill the RM global info struct with the DRV global info */ + edma3MemCpy((void *)(&drvObj[phyCtrllerInstId].gblCfgParams), + (const void *)(&resMgrObj[phyCtrllerInstId].gblCfgParams), + sizeof (EDMA3_RM_GblConfigParams)); + } + } + + if (EDMA3_RM_SOK == result) + { + drvObj[phyCtrllerInstId].state = EDMA3_DRV_CREATED; + drvObj[phyCtrllerInstId].numOpens = 0; + drvObj[phyCtrllerInstId].phyCtrllerInstId = phyCtrllerInstId; + + /* Make all the Driver instances for this EDMA3 HW NULL */ + for (count = 0; count < drvObj[phyCtrllerInstId].gblCfgParams.numRegions; count++) + { + edma3MemSet((void *)&(drvInstance[phyCtrllerInstId][count]) , 0x00u, + sizeof(EDMA3_DRV_Instance)); + } + + /* Reset edma3DrvChBoundRes Array*/ + for (count = 0; count < EDMA3_MAX_LOGICAL_CH; count++) + { + edma3DrvChBoundRes[phyCtrllerInstId][count].paRAMId = -1; + edma3DrvChBoundRes[phyCtrllerInstId][count].tcc = EDMA3_MAX_TCC; + edma3DrvChBoundRes[phyCtrllerInstId][count].trigMode = + EDMA3_DRV_TRIG_MODE_NONE; + } + } + } + } + + return result; + } + + + +/** + * \brief Delete EDMA3 Driver Object + * + * Use this API to delete the EDMA3 Driver Object. It should be called only + * ONCE for each EDMA3 hardware instance. It should be called ONLY after + * closing all the EDMA3 Driver Instances. + * + * This API is used to delete the EDMA3 Driver Object. It should be called + * once for each EDMA3 hardware instance, ONLY after closing all the + * previously opened EDMA3 Driver Instances. + * + * After successful completion of this API, Driver Object's state + * changes to EDMA3_DRV_DELETED. + * + * \param phyCtrllerInstId [IN] EDMA3 Phy Controller Instance Id (Hardware + * instance id, starting from 0). + * \param param [IN] For possible future use. + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error code + */ +EDMA3_DRV_Result EDMA3_DRV_delete(unsigned int phyCtrllerInstId, + const void *param) + { + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + + /*to remove CCS remark: parameter "param" was never referenced */ + (void)param; + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if (phyCtrllerInstId >= EDMA3_MAX_EDMA3_INSTANCES) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_DRV_SOK == result) + { + /** + * If number of Driver Instances is 0, then state should be + * EDMA3_DRV_CLOSED OR EDMA3_DRV_CREATED. + */ + if ((NULL == drvObj[phyCtrllerInstId].numOpens) + && ((drvObj[phyCtrllerInstId].state != EDMA3_DRV_CLOSED) + && (drvObj[phyCtrllerInstId].state != EDMA3_DRV_CREATED))) + { + result = EDMA3_DRV_E_OBJ_NOT_CLOSED; + } + else + { + /** + * If number of Driver Instances is NOT 0, then this function + * SHOULD NOT be called by anybody. + */ + if (NULL != drvObj[phyCtrllerInstId].numOpens) + { + result = EDMA3_DRV_E_INVALID_STATE; + } + else + { + /** + * State is correct. Delete the RM Object. + */ + result = EDMA3_RM_delete (phyCtrllerInstId, NULL); + + if (EDMA3_RM_SOK == result) + { + /** Change state to EDMA3_DRV_DELETED */ + drvObj[phyCtrllerInstId].state = EDMA3_DRV_DELETED; + + /* Also, reset the Driver Object Global Config Info */ + edma3MemSet((void *)&(drvObj[phyCtrllerInstId].gblCfgParams) , 0x00u, + sizeof(EDMA3_DRV_GblConfigParams)); + } + } + } + } + + return result; + } + + +/** + * \brief Open EDMA3 Driver Instance + * + * This API is used to open an EDMA3 Driver Instance. It could be + * called multiple times, for each possible EDMA3 shadow region. Maximum + * EDMA3_MAX_REGIONS instances are allowed for each EDMA3 hardware + * instance. Multiple instances on the same shadow region are NOT allowed. + * + * Also, only ONE Master Driver Instance is permitted. This master + * instance (and hence the region to which it belongs) will only receive the + * EDMA3 interrupts, if enabled. + * + * User could pass the instance specific configuration structure + * (initCfg.drvInstInitConfig) as a part of the 'initCfg' structure, + * during init-time. In case user doesn't provide it, this information could + * be taken from the SoC specific configuration file edma3__cfg.c, + * in case it is available. + * + * \param phyCtrllerInstId [IN] EDMA3 Controller Instance Id (Hardware + * instance id, starting from 0). + * \param initCfg [IN] Used to Initialize the EDMA3 Driver + * Instance (Master or Slave). + * \param errorCode [OUT] Error code while opening DRV instance. + * + * \return EDMA3_DRV_Handle : If successfully opened, the API will return the + * associated driver's instance handle. + * + * \note This function disables the global interrupts (by calling API + * edma3OsProtectEntry with protection level + * EDMA3_OS_PROTECT_INTERRUPT) while modifying the global data + * structures, to make it re-entrant. + */ +EDMA3_DRV_Handle EDMA3_DRV_open (unsigned int phyCtrllerInstId, + const EDMA3_DRV_InitConfig *initCfg, + EDMA3_DRV_Result *errorCode) + { + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + EDMA3_DRV_Object *drvObject = NULL; + EDMA3_DRV_Instance *drvInstanceHandle = NULL; + unsigned int intState = 0; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + unsigned short flag = 0; + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if (((initCfg == NULL) || (phyCtrllerInstId >= EDMA3_MAX_EDMA3_INSTANCES)) + || (errorCode == NULL)) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_DRV_SOK == result) + { + /* Check whether the semaphore handle is null or not */ + if (NULL== initCfg->drvSemHandle) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + drvObject = &drvObj[phyCtrllerInstId]; + if (NULL == drvObject) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + if (initCfg->regionId >= drvObject->gblCfgParams.numRegions) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + /* if no instance is opened and this is the first one, + * then state should be created/closed. + */ + if (((drvObject->numOpens == NULL) && (drvObject->state != EDMA3_DRV_CREATED)) + && (drvObject->state != EDMA3_DRV_CLOSED)) + { + result = EDMA3_DRV_E_INVALID_STATE; + } + else + { + /* if num of instances opened is more than 0 and less than no of regions, + * then state should be opened. + */ + if (((drvObject->numOpens > 0) && (drvObject->numOpens < drvObject->gblCfgParams.numRegions)) + && (drvObject->state != EDMA3_DRV_OPENED)) + { + result = EDMA3_DRV_E_INVALID_STATE; + } + else + { + /* if a driver instance is already there for a specific region, + * it should return an error. + */ + drvInstanceHandle = &drvInstance[phyCtrllerInstId][initCfg->regionId]; + if (drvInstanceHandle->pDrvObjectHandle != NULL) + { + drvInstanceHandle = NULL; + result = EDMA3_DRV_E_INST_ALREADY_EXISTS; + } + } + } + } + } + } + } + + if (EDMA3_DRV_SOK == result) + { + /* Save the region specific information in the region specific drv instance*/ + drvInstanceHandle->regionId = initCfg->regionId; + drvInstanceHandle->isMaster = initCfg->isMaster; + drvInstanceHandle->drvSemHandle = initCfg->drvSemHandle; + drvInstanceHandle->gblerrCbParams.gblerrCb = initCfg->gblerrCb; + drvInstanceHandle->gblerrCbParams.gblerrData = initCfg->gblerrData; + + if (NULL != initCfg->drvInstInitConfig) + { + edma3MemCpy((void *)(&drvInstanceHandle->drvInstInitConfig), + (const void *)(initCfg->drvInstInitConfig), + sizeof (EDMA3_DRV_InstanceInitConfig)); + + /* Flag to remember that driver has passed config info to RM */ + flag = 1u; + } + + if (NULL == drvObject->gblCfgParams.globalRegs) + { + drvInstanceHandle = NULL; + result = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + globalRegs = (volatile EDMA3_CCRL_Regs *)drvObject->gblCfgParams.globalRegs; + + /* Update shadowRegs */ + drvInstanceHandle->shadowRegs = (EDMA3_CCRL_ShadowRegs *) + (&(globalRegs->SHADOW[initCfg->regionId])); + + result = edma3OpenResMgr (phyCtrllerInstId, initCfg->regionId, flag); + if (EDMA3_DRV_SOK != result) + { + drvInstanceHandle = NULL; + } + else + { + drvObject->state = EDMA3_DRV_OPENED; + edma3OsProtectEntry (EDMA3_OS_PROTECT_INTERRUPT, &intState); + drvObject->numOpens++; + edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT, intState); + } + } + } + + *errorCode = result; + return (EDMA3_DRV_Handle)drvInstanceHandle; + } + + +/** + * \brief Close the EDMA3 Driver Instance. + * + * This API is used to close a previously opened EDMA3 Driver Instance. + * + * \param hEdma [IN] Handle to the previously opened EDMA3 + * Driver Instance. + * \param param [IN] For possible future use + * + * \return EDMA3_DRV_SOK or EDMA3_DRV Error code + * + * \note This function disables the global interrupts (by calling API + * edma3OsProtectEntry with protection level + * EDMA3_OS_PROTECT_INTERRUPT) while modifying the global data + * structures, to make it re-entrant. + */ +EDMA3_DRV_Result EDMA3_DRV_close(EDMA3_DRV_Handle hEdma, + const void *param) + { + unsigned int intState = 0; + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + EDMA3_DRV_Instance *drvInst = NULL; + EDMA3_DRV_Object *drvObject = NULL; + + /*to remove CCS remark: parameter "param" was never referenced */ + (void)param; + + /* If parameter checking is enabled... */ +#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE + if (hEdma == NULL) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_DRV_SOK == result) + { + drvInst = (EDMA3_DRV_Instance *)hEdma; + drvObject = drvInst->pDrvObjectHandle; + + if (drvObject == NULL) + { + result = EDMA3_DRV_E_INVALID_PARAM; + } + else + { + /* Check state of driver */ + if (drvObject->state != EDMA3_DRV_OPENED) + { + result = EDMA3_DRV_E_OBJ_NOT_OPENED; + } + else + { + result = EDMA3_RM_close (drvInst->resMgrInstance, NULL); + + if (result != EDMA3_RM_SOK) + { + result = EDMA3_DRV_E_RM_CLOSE_FAIL; + } + else + { + /* Set the driver instance specific info null */ + drvInst->resMgrInstance = NULL; + drvInst->pDrvObjectHandle = NULL; + edma3MemSet((void *)&(drvInst->drvInstInitConfig), 0x00, + sizeof (EDMA3_DRV_InstanceInitConfig)); + drvInst->shadowRegs = NULL; + + edma3OsProtectEntry (EDMA3_OS_PROTECT_INTERRUPT, &intState); + /* Decrease the Number of Opens */ + --drvObject->numOpens; + if (NULL == drvObject->numOpens) + { + drvObject->state = EDMA3_DRV_CLOSED; + } + edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT, intState); + } + } + } + } + + return (result); + } + + +/* Definitions of Local functions - Start */ +/* Local function to prepare the init config structure for open of Resource Manager */ +static EDMA3_DRV_Result edma3OpenResMgr (unsigned int instId, + unsigned int regionId, + unsigned short flag) + { + EDMA3_DRV_Result result = EDMA3_DRV_SOK; + EDMA3_RM_Param initParam; + EDMA3_RM_InstanceInitConfig rmInstanceCfg; + EDMA3_RM_Handle hResMgr = NULL; + EDMA3_RM_Result rmResult; + unsigned int resMgrIdx = 0u; + EDMA3_RM_Instance *temp_rm_instance = NULL; + + assert ((instId < EDMA3_MAX_EDMA3_INSTANCES) + && (regionId < drvObj[instId].gblCfgParams.numRegions)); + + initParam.regionId = regionId; + initParam.rmSemHandle = drvInstance[instId][regionId].drvSemHandle; + /* + * If the EDMA driver instance is MASTER, do the + * (global + region_specific) init. For all other instances, + * only do the (region_specific) init. + */ + initParam.isMaster = drvInstance[instId][regionId].isMaster; + initParam.regionInitEnable = TRUE; + + initParam.gblerrCbParams.gblerrCb = drvInstance[instId][regionId].gblerrCbParams.gblerrCb; + initParam.gblerrCbParams.gblerrData = drvInstance[instId][regionId].gblerrCbParams.gblerrData; + + if (flag == 1u) + { + /** + * User has passed the instance initialization specific info, + * which we have saved previously too, so use it. + */ + edma3MemCpy((void *)(&rmInstanceCfg), + (const void *)(&drvInstance[instId][regionId].drvInstInitConfig), + sizeof (EDMA3_RM_InstanceInitConfig)); + + initParam.rmInstInitConfig = &rmInstanceCfg; + + hResMgr = EDMA3_RM_open (instId, (EDMA3_RM_Param *)&initParam, &rmResult); + + if (NULL == hResMgr) + { + result = rmResult; + } + } + else + { + /** + * User has NOT passed the instance initialization specific info. + * Pass NULL to the Resource Manager. + */ + initParam.rmInstInitConfig = NULL; + + hResMgr = EDMA3_RM_open (instId, (EDMA3_RM_Param *)&initParam, &rmResult); + + if (NULL == hResMgr) + { + result = rmResult; + } + else + { + /** + * Save the RM Instance specific information in the driver. + * Earlier this was easier, now a bit tricky. + * Search for the RM instance number based on the handle + * just returned, to fetch the correct config info from the + * userInitConfig[]. + */ + for (resMgrIdx = 0u; resMgrIdx < EDMA3_MAX_RM_INSTANCES; resMgrIdx++) + { + temp_rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (instId*EDMA3_MAX_RM_INSTANCES) + resMgrIdx); + + if (hResMgr == temp_rm_instance) + { + /* RM Id found. Copy the specific config info to the drvInstance [] */ + edma3MemCpy((void *)(&drvInstance[instId][regionId].drvInstInitConfig), + (const void *)((EDMA3_RM_InstanceInitConfig *)(ptrInitCfgArray) + (instId*EDMA3_MAX_RM_INSTANCES) + resMgrIdx), + sizeof (EDMA3_RM_InstanceInitConfig)); + break; + } + } + + if (EDMA3_MAX_RM_INSTANCES == resMgrIdx) + { + /* RM Id not found, report error... */ + result = EDMA3_DRV_E_INVALID_PARAM; + } + } + } + + + if (EDMA3_RM_SOK == result) + { + /* Save handle to Resource Manager Instance */ + drvInstance[instId][regionId].resMgrInstance = hResMgr; + /* Save handle to EDMA Driver Object */ + drvInstance[instId][regionId].pDrvObjectHandle = &drvObj[instId]; + } + + return result; + } + +/* Definitions of Local functions - End */ + +/* End of File */ diff --git a/packages/ti/sdo/edma3/rm/RM.xdc b/packages/ti/sdo/edma3/rm/RM.xdc new file mode 100644 index 0000000..ddc1edb --- /dev/null +++ b/packages/ti/sdo/edma3/rm/RM.xdc @@ -0,0 +1,15 @@ +/* + * ======== RM.xdc ======== + * + */ + +/*! + * ======== RM ======== + * EDMA3 Resource Manager. + */ +@Template("./RM.xdt") + +metaonly module RM { + config UInt edma3_max_rm_instances = 8u; +} + diff --git a/packages/ti/sdo/edma3/rm/RM.xdt b/packages/ti/sdo/edma3/rm/RM.xdt new file mode 100644 index 0000000..c9a6197 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/RM.xdt @@ -0,0 +1,79 @@ +%%{ +/****************************************************************************** +**+-------------------------------------------------------------------------+** +**| **** |** +**| **** |** +**| ******o*** |** +**| ********_///_**** |** +**| ***** /_//_/ **** |** +**| ** ** (__/ **** |** +**| ********* |** +**| **** |** +**| *** |** +**| |** +**| Copyright (c) 1998-2006 Texas Instruments Incorporated |** +**| ALL RIGHTS RESERVED |** +**| |** +**| Permission is hereby granted to licensees of Texas Instruments |** +**| Incorporated (TI) products to use this computer program for the sole |** +**| purpose of implementing a licensee product based on TI products. |** +**| No other rights to reproduce, use, or disseminate this computer |** +**| program, whether in part or in whole, are granted. |** +**| |** +**| TI makes no representation or warranties with respect to the |** +**| performance of this computer program, and specifically disclaims |** +**| any responsibility for any damages, special or consequential, |** +**| connected with the use of this program. |** +**| |** +**+-------------------------------------------------------------------------+** +******************************************************************************/ + +/** \file RM.xdt + \brief Template file for the Resource Manager for generating internal + data structures. + + (C) Copyright 2006, Texas Instruments, Inc + + \version + 0.1.0 Anuj Aggarwal - Created + + */ + +%%} + + + + +/* Resource Manager Internal Header Files */ +#include + +/** + * Maximum Resource Manager Instances supported by the EDMA3 Package. + * USE THE SAME VALUE FOR BOTH THE #DEFINE AND CONST UNSIGNED INT BELOW. + */ +% var max_rm_instances = this.edma3_max_rm_instances; + +/** + * Maximum Resource Manager Instances supported by the EDMA3 Package. + * This #define is needed for array declarations. + */ +#define MAX_EDMA3_RM_INSTANCES `max_rm_instances` + +/* This const is required to access this constant in other header files */ +const unsigned int EDMA3_MAX_RM_INSTANCES = `max_rm_instances`; + +EDMA3_RM_InstanceInitConfig userInstInitConfigArray[EDMA3_MAX_EDMA3_INSTANCES][MAX_EDMA3_RM_INSTANCES]; +EDMA3_RM_Instance resMgrInstanceArray[EDMA3_MAX_EDMA3_INSTANCES][MAX_EDMA3_RM_INSTANCES]; + + +/* These pointers will be used to refer the above mentioned arrays. */ +EDMA3_RM_Instance *resMgrInstance = (EDMA3_RM_Instance *)resMgrInstanceArray; +EDMA3_RM_InstanceInitConfig *userInitConfig = (EDMA3_RM_InstanceInitConfig *)userInstInitConfigArray; + +/* Pointer to the above mentioned 2-D arrays, used for address calculation purpose */ +EDMA3_RM_Instance *ptrRMIArray = (EDMA3_RM_Instance *)resMgrInstanceArray; +EDMA3_RM_InstanceInitConfig *ptrInitCfgArray = (EDMA3_RM_InstanceInitConfig *)userInstInitConfigArray; + + + + diff --git a/packages/ti/sdo/edma3/rm/docs/EDMA3_RM_Datasheet.doc b/packages/ti/sdo/edma3/rm/docs/EDMA3_RM_Datasheet.doc new file mode 100644 index 0000000000000000000000000000000000000000..3349148478005df71fd4e2352313f8c8e098153e GIT binary patch literal 727552 zcmeEv2Rv2(|NpU9HraIxWhD{~l0CDprs%r&;tE&y8kH1n8I_DCLM2U-Hd-{KNkvmb zX=v&b$^Z2}ceq#jeENLH@Av)v``-I_I`6$+^Zh>e9M`VOKiXcV{ut}`vBre3@4XV3 zC{Owz2x|+n6XY;V7s3J%{odQ#i&BR`d?2oJ{UwS+Ni z2LT-0HCVZAlDwsW2OvrY^!CbfGkzB46ez|6!uqT@y7Gom>K*ooc&|FF;`rZh?EG^i zRwD1!8U&Syd;M8kq$nZheop6n#;8E^1j~x$-XQlVQk{d7# zm>#3T6@7l?ipF1g1H;0g;*drRQ-yJ*Kz(Jr1^z#rd2gK0pU#N|$6{C@L~7t#0_||h zajvLc-cSGa<;<5;2F>>z@J1fgbAiN-i&!~7Twy$WAq%zV0PDzUCv6mly@hlX$2p>3 z|D1MMt^WF7&V0~%^L{w(p=+=(hAGxy*lHM$ixG?q)?=YDYkhd@{GIU7I#y}U{LTTN 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\pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 +\par Interface Definition for EDMA3 Resource Manager Layer\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 PAGEREF _Toc211937555 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 +{\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003500350035000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 10}}}\sectd +\pgnlcrm\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 +\par EDMA3 Resource Manager Usage Guidelines\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 PAGEREF _Toc211937556 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003500350036000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 15}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 +\par Error Codes\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 PAGEREF _Toc211937557 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003500350037000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 15}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 +\par EDMA3 Resources Management\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 PAGEREF _Toc211937558 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003500350038000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 24}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 +\par Log Service\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 PAGEREF _Toc211937559 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003500350039000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 48}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 +\par Internal Interface Definition for Resource Manager\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 PAGEREF _Toc211937560 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 +{\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003500360030000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 48}}}\sectd +\pgnlcrm\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 +\par Object Maintenance\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 PAGEREF _Toc211937561 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003500360031000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 49}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 +\par Boundary Values\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 PAGEREF _Toc211937562 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003500360032000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 49}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 +\par }\pard\plain \ltrpar\s82\ql \li0\ri0\widctlpar\tqr\tldot\tx8630\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Data Structure Documentation\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 PAGEREF _Toc211937563 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003500360033000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 51}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 +\par }\pard\plain \ltrpar\s83\ql \li200\ri0\widctlpar\tqr\tldot\tx8630\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_ChBoundResources\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 PAGEREF _Toc211937564 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003500360034000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 51}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 +\par EDMA3_RM_GblConfigParams\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 PAGEREF _Toc211937565 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 {\*\datafield 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\lang1024\langfe1024\noproof\insrsid7370340 PAGEREF _Toc211937567 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003500360037000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 57}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 +\par EDMA3_RM_InstanceInitConfig\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 PAGEREF _Toc211937568 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003500360038000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 60}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 +\par EDMA3_RM_MiscParam\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 PAGEREF _Toc211937569 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003500360039000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 63}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 +\par EDMA3_RM_Obj\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 PAGEREF _Toc211937570 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003500370030000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 64}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 +\par EDMA3_RM_Param\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 PAGEREF _Toc211937571 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003500370031000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 66}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 +\par EDMA3_RM_ParamentryRegs\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 PAGEREF _Toc211937572 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 {\*\datafield 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\lang1024\langfe1024\noproof\insrsid7370340 PAGEREF _Toc211937574 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003500370034000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 72}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 +\par EDMA3_RM_TccCallbackParams\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 PAGEREF _Toc211937575 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003500370035000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 73}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 +\par }\pard\plain \ltrpar\s82\ql \li0\ri0\widctlpar\tqr\tldot\tx8630\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 File Documentation\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 PAGEREF _Toc211937576 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003500370036000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 74}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 +\par }\pard\plain \ltrpar\s83\ql \li200\ri0\widctlpar\tqr\tldot\tx8630\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 PAGEREF _Toc211937577 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003500370037000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 74}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 +\par edma3_da830_cfg.c\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 PAGEREF _Toc211937578 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003500370038000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 83}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 +\par edma3_log.h\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 PAGEREF _Toc211937579 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003500370039000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 87}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 +\par edma3_rl_cc.h\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 PAGEREF _Toc211937580 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003500380030000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 88}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 +\par edma3_rl_tc.h\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 PAGEREF _Toc211937581 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003500380031000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 182}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 +\par edma3_rm.h\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 PAGEREF _Toc211937582 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003500380032000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 191}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 +\par edma3_rm_gbl_data.c\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 PAGEREF _Toc211937583 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003500380033000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 197}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 +\par edma3resmgr.c\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 PAGEREF _Toc211937584 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003500380034000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 199}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 +\par edma3resmgr.h\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 PAGEREF _Toc211937585 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003500380035000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 211}}}\sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 +\par }\pard\plain \ltrpar\s82\ql \li0\ri0\widctlpar\tqr\tldot\tx8630\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Index\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 PAGEREF _Toc211937586 \\h }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 +{\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003200310031003900330037003500380036000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 215}}}\sectd +\pgnlcrm\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 }}\pard\plain \ltrpar +\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 \sectd \pgnlcrm\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid7370340 +\par \sect }\sectd \ltrsect\pgnrestart\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \sect }\sectd \ltrsect\sbknone\linex0\sectdefaultcl\sftnbj {\footerr \ltrpar \pard\plain \ltrpar\s20\qr \li0\ri0\widctlpar\tqc\tx4320\tqr\tx8640\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \chpgn +\par }}\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \sect +}\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s1\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs36\alang1025 \ltrch\fcs0 +\b\f1\fs36\lang1033\langfe1033\kerning36\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Module Index +\par }\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 +{\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\tc { +\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 {\*\bkmkstart _Toc211937546}Module Index{\*\bkmkend _Toc211937546}}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Modules +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Here is a list of all modu +les:}{\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s53\ql \li360\ri0\sb27\sa27\widctlpar\tqr\tldot\tx8640\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 EDMA3 Interrupt Manager Interface\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 PAGEREF AAAAAAAIBJ \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 5}}} +\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s54\ql \li720\ri0\sb24\sa24\widctlpar\tqr\tldot\tx8640\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 Instance Wide Interface\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 PAGEREF AAAAAAAIBK \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 5}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s55\ql \li1080\ri0\sb21\sa21\widctlpar\tqr\tldot\tx8640\wrapdefault\faauto\adjustright\rin0\lin1080\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 Completion status\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 PAGEREF AAAAAAAIBL \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 5}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Channel Specific Interface\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 PAGEREF AAAAAAAIBY \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 7}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s56\ql \li1440\ri0\sb18\sa18\widctlpar\tqr\tldot\tx8640\wrapdefault\faauto\adjustright\rin0\lin1440\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 Resource Type\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 PAGEREF AAAAAAAICC \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 9}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s55\ql \li1080\ri0\sb21\sa21\widctlpar\tqr\tldot\tx8640\wrapdefault\faauto\adjustright\rin0\lin1080\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s54\ql \li720\ri0\sb24\sa24\widctlpar\tqr\tldot\tx8640\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 Interface Definition for EDMA3 Resource Manager Layer\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 PAGEREF AAAAAAAICI \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 10}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s55\ql \li1080\ri0\sb21\sa21\widctlpar\tqr\tldot\tx8640\wrapdefault\faauto\adjustright\rin0\lin1080\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 EDMA3 Resource Manager Usage Guidelines\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 PAGEREF AAAAAAAICP \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 15}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Error Codes\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 PAGEREF AAAAAAAICQ \\*MERGEFORMAT} +}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 15}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s54\ql \li720\ri0\sb24\sa24\widctlpar\tqr\tldot\tx8640\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 EDMA3 Resources Management\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 PAGEREF AAAAAAAIDH \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 24}}} +\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s53\ql \li360\ri0\sb27\sa27\widctlpar\tqr\tldot\tx8640\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 Log Service\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 PAGEREF AAAAAAAIHT \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 48}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Internal Interface Definition for Resource Manager\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 PAGEREF AAAAAAAIHU \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 +\af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 48}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s54\ql \li720\ri0\sb24\sa24\widctlpar\tqr\tldot\tx8640\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 Object Maintenance\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 PAGEREF AAAAAAAIHV \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 49}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s55\ql \li1080\ri0\sb21\sa21\widctlpar\tqr\tldot\tx8640\wrapdefault\faauto\adjustright\rin0\lin1080\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 Boundary Values\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 PAGEREF AAAAAAAIIB \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 49}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s54\ql \li720\ri0\sb24\sa24\widctlpar\tqr\tldot\tx8640\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s53\ql \li360\ri0\sb27\sa27\widctlpar\tqr\tldot\tx8640\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \sect +}\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s1\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs36\alang1025 \ltrch\fcs0 +\b\f1\fs36\lang1033\langfe1033\kerning36\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Data Structure Index +\par }\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 +{\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\tc { +\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 {\*\bkmkstart _Toc211937547}Data Structure Index{\*\bkmkend _Toc211937547}}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Data Structures +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Here are the data structures with brief descriptions:}{\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s53\ql \li360\ri0\sb27\sa27\widctlpar\tqr\tldot\tx8640\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ChBoundResources (EDMA3 Channel-Bound resources )}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 PAGEREF AAAAAAAIII \\*MERGEFORMAT}}{\fldrslt { +\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 51}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_GblConfigParams (Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information )}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \tab }{\field{\*\fldinst { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 PAGEREF AAAAAAAIIJ \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 52}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 + +\par }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_GblErrCallbackParams (Global Error Callback parameters )}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 PAGEREF AAAAAAAIIK +\\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 56}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Instance (EDMA3 RM Instance Specific Configuration Structure )}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +PAGEREF AAAAAAAIIL \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 57}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_InstanceInitConfig (Init-time Region Specific Configuration structure for EDMA3 RM, to provide region specific Information )}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \tab } +{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 PAGEREF AAAAAAAIIM \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 60}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 +\par }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_MiscParam (Used to specify the miscellaneous options during Resource Manager Initialization )}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 PAGEREF AAAAAAAIIN \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 63}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Obj (EDMA3 Hardware Instance Configuration Structure )}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 PAGEREF AAAAAAAIIO \\ +*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 64}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Param (Used to Initialize the Resource Manager Instance )}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 PAGEREF AAAAAAA +IIP \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 66}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ParamentryRegs (EDMA3 PaRAM Set )}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 PAGEREF AAAAAAAIIQ \\*MERGEFORMAT} +}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 68}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_PaRAMRegs (EDMA3 PaRAM Set in User Configurable format )}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 PAGEREF AAAAAAAIIR +\\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 70}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc (Handle to a Resource )}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 PAGEREF AAAAAAAIIS \\*MERGEFORMAT} +}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 72}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_TccCallbackParams (TCC Callback - Caters to channel specific status reporting )}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 PAGEREF AAAAAAAIIT \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 73}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \sect +}\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s1\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs36\alang1025 \ltrch\fcs0 +\b\f1\fs36\lang1033\langfe1033\kerning36\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 File Index +\par }\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 +{\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\tc { +\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 {\*\bkmkstart _Toc211937548}File Index{\*\bkmkend _Toc211937548}}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 File List +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Here is a list of all documented files with brief descriptions:}{\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s53\ql \li360\ri0\sb27\sa27\widctlpar\tqr\tldot\tx8640\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid7370340 edma3_common.h (EDMA3 Common header provides generic defines/typedefs and debugging info )}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +PAGEREF AAAAAAAAAA \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 74}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 edma3_da830_cfg.c (EDMA3 Driver Adaptation Configuration File (Soc Specific) for DA8xx platform )}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 PAGEREF AAAAAAAABU \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 83}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 edma3_log.h (EDMA3 logging/tracing service )}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 PAGEREF AAAAAAAADB \\*MERGEFORMAT} +}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 87}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 edma3_rl_cc.h (EDMA3 Channel Controller Register Desciption )}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 PAGEREF AAAAAAAADI \\ +*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 88}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 edma3_rl_tc.h (EDMA3 Transfer Controller Register Desciption )}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 PAGEREF AAAAAAAHJB \\ +*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 182}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 edma3_rm.h (EDMA3 Controller Resource Manager Interface )}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 PAGEREF AAAAAAAHYP \\ +*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 191}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 edma3_rm_gbl_data.c (Source file for the Resource Manager, for internal data structures )}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 PAGEREF AAAAAAAHYR \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 197}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 edma3resmgr.c (EDMA3 Controller Resource Manager Interface Implementation )}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +PAGEREF AAAAAAAHZA \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 199}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 edma3resmgr.h (EDMA3 Resource Manager Internal header file )}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 PAGEREF AAAAAAAIAT \\ +*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 211}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \sect +}\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s1\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs36\alang1025 \ltrch\fcs0 +\b\f1\fs36\lang1033\langfe1033\kerning36\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Module Documentation}{\pard\plain \ltrpar +\s1\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs36\alang1025 \ltrch\fcs0 \b\v\f1\fs36\lang1033\langfe1033\kerning36\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 {\*\bkmkstart _Toc211937549}Module Documentation{\*\bkmkend _Toc211937549}}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3 Interrupt Manager Interface +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 \tcl2{\*\bkmkstart _Toc211937550}EDMA3 Interrupt Manager Interface{\*\bkmkend _Toc211937550}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 EDMA3 Interrupt Manager Interface}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIBJ}{\*\bkmkend AAAAAAAIBJ}Modules +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +Instance Wide Interface}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 Interface Definition for EDMA3 Resource Manager Layer}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 + +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3 Resources Management}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 Include common header file +\par Top-level Encapsulation of documentation for EDMA3 Interrupt Manager Layer +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 +\ltrch\fcs0 \fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Instance Wide Interface +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 \tcl2{\*\bkmkstart _Toc211937551}Instance Wide Interface{\*\bkmkend _Toc211937551}}}}\sectd +\linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Instance Wide Interface}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIBK} +{\*\bkmkend AAAAAAAIBK}Modules +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +Completion status}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 Channel Specific Interface}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 Instance Wide Interface of the EDMA3 Interrupt Manager Layer +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 +\ltrch\fcs0 \fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Completion status +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 \tcl2{\*\bkmkstart _Toc211937552}Completion status{\*\bkmkend _Toc211937552}}}}\sectd +\linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Completion status}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIBL} +{\*\bkmkend AAAAAAAIBL}Data Structures +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_GblErrCallbackParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Global Error Callback parameters. +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Typedefs +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +typedef void(* }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_GblErrCallback}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 )(}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_GlobalError}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 deviceStatus, unsigned int instanceId, void *gblerrData) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Global Error callback - caters to module events like bus error etc which are not channel specific. Runs in ISR context. +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Enumerations +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_TccStatus}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_XFER_COMPLETE}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 1, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_CC_DMA_EVT_MISS}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 2, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_CC_QDMA_EVT_MISS}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 = 3 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 This enum defines the channel specific status codes of an EDMA3 transfer. It is returned while calling the channel specific callback function to tell the status. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_GlobalError}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_CC_QUE_THRES_EXCEED}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 + = 1, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_CC_TCC}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 2, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_TC_MEM_LOCATION_READ_ERROR}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 = 3, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_TC_MEM_LOCATION_WRITE_ERROR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 4, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_TC_INVALID_ADDR}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 5, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_TC_TR_ERROR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 6 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 This enum defines the global (not specific to any channel) error codes of completion of an EDMA3 transfer. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 This group defines the error codes of completion of an EDMA3 transfer. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Typedef Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_GblErrCallback\:Edma3RMStatus}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 Edma3RMStatus\:EDMA3_RM_GblErrCallback}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +typedef void(* EDMA3_RM_GblErrCallback)(EDMA3_RM_GlobalError deviceStatus, unsigned int instanceId, void *gblerrData) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIBM}{\*\bkmkend AAAAAAAIBM}Global Error callback - caters to module events like bus error etc which are not channel specific. Runs in ISR context. +\par gblerrData is application provided data when open'ing the Resource Manager. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Enumeration Type Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_GlobalError\:Edma3RMStatus}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 Edma3RMStatus\:EDMA3_RM_GlobalError}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +enum EDMA3_RM_GlobalError +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIBN}{\*\bkmkend AAAAAAAIBN}This enum defines the global (not specific to any channel) error codes of completion of an EDMA3 transfer. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +\par Enumerator: }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_E_CC_QUE_THRES_EXCEED\:Edma3RMStatus}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3RMStatus\:EDMA3_RM_E_CC_QUE_THRES_EXCEED}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_E_CC_QUE_THRES_EXCEED}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIBO}{\*\bkmkend AAAAAAAIBO} + Threshold exceed:- for all event queues. These get latched in EDMA3CC error register (CCERR). This error has a direct relation with the setting of }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_GblConfigParams.evtQueueWaterMarkLvl}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_E_CC_TCC\:Edma3RMStatus}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3RMStatus\:EDMA3_RM_E_CC_TCC}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_E_CC_TCC}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIBP}{\*\bkmkend AAAAAAAIBP} + TCC error:- for outstanding transfer requests expected to return completion code (TCCHEN or TCINTEN bit in OPT is set to 1) exceeding the maximum limit of 63. This also gets latched in the CCERR. +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_E_TC_MEM_LOCATION_READ_ERROR\:Edma3RMStatus}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3RMStatus\:EDMA3_RM_E_TC_MEM_LOCATION_READ_ERROR}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_E_TC_MEM_LOCATION_READ_ERROR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIBQ}{\*\bkmkend AAAAAAAIBQ} Transfer Controller has r +eported an error Detection of a Read error signaled by the source or destination address +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_E_TC_MEM_LOCATION_WRITE_ERROR\:Edma3RMStatus}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec +}\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3RMStatus\:EDMA3_RM_E_TC_MEM_LOCATION_WRITE_ERROR}}} +\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_E_TC_MEM_LOCATION_WRITE_ERROR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIBR}{\*\bkmkend AAAAAAAIBR} Detectio +n of a Write error signaled by the source or destination address +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_E_TC_INVALID_ADDR\:Edma3RMStatus}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3RMStatus\:EDMA3_RM_E_TC_INVALID_ADDR}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_E_TC_INVALID_ADDR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIBS}{\*\bkmkend AAAAAAAIBS} + Attempt to read or write to an invalid address in the configuration memory map. +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_E_TC_TR_ERROR\:Edma3RMStatus}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3RMStatus\:EDMA3_RM_E_TC_TR_ERROR}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_E_TC_TR_ERROR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIBT}{\*\bkmkend AAAAAAAIBT} + Detection of a FIFO mode TR violating the FIFO mode transfer rules (the source/destination addresses and source/destination indexes must be aligned to 32 bytes). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_TccStatus\:Edma3RMStatus}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3RMStatus\:EDMA3_RM_TccStatus}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 enum EDMA3_RM_TccStatus + +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIBU}{\*\bkmkend AAAAAAAIBU}This enum defines the channel specific status codes of an EDMA3 transfer. It is returned while calling the channel specific callback function to tell the status. + +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +\par Enumerator: }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_XFER_COMPLETE\:Edma3RMStatus}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3RMStatus\:EDMA3_RM_XFER_COMPLETE}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_XFER_COMPLETE}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIBV}{\*\bkmkend AAAAAAAIBV} + DMA Transfer successfully completed (true completion mode) or submitted to the TC (early completion mode). +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_E_CC_DMA_EVT_MISS\:Edma3RMStatus}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3RMStatus\:EDMA3_RM_E_CC_DMA_EVT_MISS}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_E_CC_DMA_EVT_MISS}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIBW}{\*\bkmkend AAAAAAAIBW} + Channel Controller has reported an error DMA missed events:- for all 64 DMA channels. These get latched in the event missed registers (EMR/EMRH). +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_E_CC_QDMA_EVT_MISS\:Edma3RMStatus}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3RMStatus\:EDMA3_RM_E_CC_QDMA_EVT_MISS}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_E_CC_QDMA_EVT_MISS}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIBX}{\*\bkmkend AAAAAAAIBX} + QDMA missed events:- for all QDMA channels. These get latched in the QDMA event missed register (QEMR). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Channel Specific Interface +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 \tcl2{\*\bkmkstart _Toc211937553}Channel Specific Interface{\*\bkmkend _Toc211937553}}}}\sectd +\linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Channel Specific Interface}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIBY} +{\*\bkmkend AAAAAAAIBY}Modules +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +Resource Type}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Typedefs +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +typedef void(* }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_TccCallback}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 )(unsigned int tcc, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_TccStatus}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 status, void *appData) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 TCC callback - caters to channel-specific events like "Event Miss Error" or "Transfer Complete". Runs in ISR context. +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Functions +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_registerTccCb}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *channelObj, unsigned int tcc, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 EDMA3_RM_TccCallback}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 tccCb, void *cbData) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Register Interrupt / Completion Handler for a given TCC. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_unregisterTccCb}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *channelObj) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Unregister the previously registered callback function against a DMA/QDMA channel. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 Channel Specific Interface of the EDMA3 Interrupt Manager Layer +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Typedef Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_TccCallback\:Edma3RMIntrMgrChannel}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 Edma3RMIntrMgrChannel\:EDMA3_RM_TccCallback}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +typedef void(* EDMA3_RM_TccCallback)(unsigned int tcc, EDMA3_RM_TccStatus status, void *appData) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIBZ}{\*\bkmkend AAAAAAAIBZ}TCC callback - caters to channel-specific events like "Event Miss Error" or "Transfer Complete". Runs in ISR context. +\par appData is passed by the application during Register'ing of TCC Callback function. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Function Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_registerTccCb\:Edma3RMIntrMgrChannel}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 Edma3RMIntrMgrChannel\:EDMA3_RM_registerTccCb}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_Result EDMA3_RM_registerTccCb (EDMA3_RM_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , const EDMA3_RM_ResDesc * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 +channelObj}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 tcc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , EDMA3_RM_TccCallback }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 +tccCb}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , void * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 cbData}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAICA}{\*\bkmkend AAAAAAAICA}Register Interrupt / Completion Handler for a given TCC. +\par This function enables the interrupts in IESR/IESRH, only if the callback function provided by the user is NON-NULL. Moreover, if a call-back function +is already registered against that TCC, the API fails with the error code EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED. For a NULL callback function, this API returns error. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Handle to the previously opened EDMA3 Resource Manager Instance +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 channelObj}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 + [IN] Channel ID and type (DMA or QDMA Channel), allocated earlier, and corresponding to which a callback function needs to be registered against the associated TCC. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 tcc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] TCC against which the handler needs to be registered. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 tccCb}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] The Callback function to be registered against the TCC. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 cbData}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Callback data to be passed while calling the callback function. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_SOK or EDMA3_RM Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 This function is re-entrant for unique tcc values. It is non- re-entrant for same tcc value. +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Enable the interrupts in IESR/IESRH, only if the Callback function is NOT NULL. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 References EDMA3_RM_TccCallbackParams::cbData, EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_RES_DMA_CHANNEL, EDMA3_RM_RES +_QDMA_CHANNEL, EDMA3_RM_SOK, edma3DmaChTccMapping, edma3QdmaChTccMapping, EDMA3_RM_Obj::gblCfgParams, NULL, EDMA3_RM_GblConfigParams::numDmaChannels, EDMA3_RM_GblConfigParams::numQdmaChannels, EDMA3_RM_GblConfigParams::numTccs, EDMA3_RM_Instance::pResMgrO +bjHandle, EDMA3_RM_ResDesc::resId, EDMA3_RM_Instance::shadowRegs, EDMA3_RM_TccCallbackParams::tccCb, and EDMA3_RM_ResDesc::type. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_unregisterTccCb\:Edma3RMIntrMgrChannel}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3RMIntrMgrChannel\:EDMA3_RM_unregisterTccCb}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_Result EDMA3_RM_unregisterTccCb (EDMA3_RM_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , const EDMA3_RM_ResDesc * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 +channelObj}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAICB}{\*\bkmkend AAAAAAAICB}Unregister the previously registered callback function against a DMA/QDMA channel. +\par This function unregisters the previously registered callback function against a DMA/ +QDMA channel by removing any stored callback function. Moreover, it clears the interrupt enable register (IESR/IESRH) by writing to the IECR/ IECRH register, for the TCC associated with that particular channel. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Handle to the previously opened EDMA3 Resource Manager Instance +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 channelObj}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 + [IN] Channel ID and type, allocated earlier (DMA or QDMA Channel ONLY), and corresponding to which a TCC is there. Against that TCC, the callback needs to be un-registered. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_SOK or EDMA3_RM Error Code. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 This function is re-entrant for unique (channelObj->type + channelObj->resId) combination. It is non-re-entrant for same channelObj Resource. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 References EDMA3_RM_TccCallbackParams::cbData, EDMA3_MAX_TCC, EDMA3_RM_E_INVALID_PAR +AM, EDMA3_RM_RES_DMA_CHANNEL, EDMA3_RM_RES_QDMA_CHANNEL, EDMA3_RM_SOK, edma3DmaChTccMapping, edma3QdmaChTccMapping, EDMA3_RM_Obj::gblCfgParams, NULL, EDMA3_RM_GblConfigParams::numDmaChannels, EDMA3_RM_GblConfigParams::numQdmaChannels, EDMA3_RM_Instance::p +ResMgrObjHandle, EDMA3_RM_ResDesc::resId, EDMA3_RM_Instance::shadowRegs, EDMA3_RM_TccCallbackParams::tccCb, and EDMA3_RM_ResDesc::type. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Resource Type +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 \tcl2{\*\bkmkstart _Toc211937554}Resource Type{\*\bkmkend _Toc211937554}}}}\sectd +\linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Resource Type}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAICC} +{\*\bkmkend AAAAAAAICC}Data Structures +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Handle to a Resource. +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Defines +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define } +{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_RES_ANY}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (1010u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Used to specify any available Resource Id (}{\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_ResDesc.resId}{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 ). +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Enumerations +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResType}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_RES_DMA_CHANNEL}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 1, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_RES_QDMA_CHANNEL}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 2, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_RES_TCC}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 3, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_RES_PARAM_SET}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 4 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 EDMA3 Resource Type. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 Resource Type part of the EDMA3 Resource Manager. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Enumeration Type Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_ResType\:Edma3ResType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 Edma3ResType\:EDMA3_RM_ResType}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +enum EDMA3_RM_ResType +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAICD}{\*\bkmkend AAAAAAAICD}EDMA3 Resource Type. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +\par Enumerator: }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_RES_DMA_CHANNEL\:Edma3ResType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResType\:EDMA3_RM_RES_DMA_CHANNEL}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_RES_DMA_CHANNEL}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAICE}{\*\bkmkend AAAAAAAICE} DMA Channel resource +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_RES_QDMA_CHANNEL\:Edma3ResType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResType\:EDMA3_RM_RES_QDMA_CHANNEL}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_RES_QDMA_CHANNEL}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAICF}{\*\bkmkend AAAAAAAICF} QDMA Channel resource +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_RES_TCC\:Edma3ResType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResType\:EDMA3_RM_RES_TCC}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_RES_TCC}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAICG}{\*\bkmkend AAAAAAAICG} TCC resource +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_RES_PARAM_SET\:Edma3ResType}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResType\:EDMA3_RM_RES_PARAM_SET}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_RES_PARAM_SET}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAICH}{\*\bkmkend AAAAAAAICH} Parameter RAM Set resource +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Interface Definition for EDMA3 Resource Manager Layer +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 \tcl2{\*\bkmkstart _Toc211937555}Interface Definition for EDMA3 Resource Manager Layer +{\*\bkmkend _Toc211937555}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Interface Definition for EDMA3 Resource Manager Layer}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 +\af1 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAICI}{\*\bkmkend AAAAAAAICI}Modules +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3 Resource Manager Usage Guidelines}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 Error Codes}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Usage of Resource Manager. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Data Structures +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_GblConfigParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_InstanceInitConfig}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Init-time Region Specific Configuration structure for EDMA3 RM, to provide region specific Information. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Param}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Used to Initialize the Resource Manager Instance. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_MiscParam}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Used to specify the miscellaneous options during Resource Manager Initialization. +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Typedefs +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 ty +pedef unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_RegionId}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 EDMA3 Region Id. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +typedef unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_EventQueue}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 EDMA3 Event Queue assignment. +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Functions +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_create}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (unsigned int phyCtrllerInstId, const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 EDMA3_RM_GblConfigParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *gblCfgParams, const void *miscParam) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Create EDMA3 Resource Manager Object. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_delete}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (unsigned int phyCtrllerInstId, const void *param) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Delete EDMA3 Resource Manager Object. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Handle}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_open}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (unsigned int phyCtrllerInstId, const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 EDMA3_RM_Param}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *initParam, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *errorCode) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Open EDMA3 Resource Manager Instance. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_close}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, const void *param) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Close EDMA3 Resource Manager Instance. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 Top-level Encapsulation of all documentation for EDMA3 Resource Manager Layer +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Typedef Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_EventQueue\:Edma3RMMain}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 Edma3RMMain\:EDMA3_RM_EventQueue}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_EventQueue +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAICJ}{\*\bkmkend AAAAAAAICJ}EDMA3 Event Queue assignment. +\par There can be 8 Event Queues. Either of them can be assigned to a DMA/QDMA channel using this. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_RegionId\:Edma3RMMain}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3RMMain\:EDMA3_RM_RegionId}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_RegionId +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAICK}{\*\bkmkend AAAAAAAICK}EDMA3 Region Id. +\par Use this to assign channels/PaRAM sets/TCCs to a particular Region. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Function Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_close\:Edma3RMMain}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 Edma3RMMain\:EDMA3_RM_close}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_Result EDMA3_RM_close (EDMA3_RM_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , const void * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 param}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAICL}{\*\bkmkend AAAAAAAICL}Close EDMA3 Resource Manager Instance. +\par This API is used to close a previously opened EDMA3 RM Instance. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Handle to the previously opened Resource Manager Instance. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 param}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] For possible future use. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_SOK or EDMA3_RM Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 This function disables the global interrupts (by calling API edma3OsProtectEntry with protection level EDMA3_OS_PROTECT_INTERRUPT) while modifying the global RM data structures, to make it re-entrant. +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 If this is the Master Instance, reset the static variable 'masterExists'. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 References EDMA3_RM_Instance::avlblDmaChannels, EDMA3_RM_Instance::avlblPaRAMSets +, EDMA3_RM_Instance::avlblQdmaChannels, EDMA3_RM_Instance::avlblTccs, EDMA3_MAX_REGIONS, EDMA3_OS_PROTECT_INTERRUPT, EDMA3_RM_CLOSED, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_E_OBJ_NOT_OPENED, EDMA3_RM_OPENED, EDMA3_RM_SOK, edma3MemSet(), edma3OsProtectEntry(), + +edma3OsProtectExit(), edma3RegionId, FALSE, EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_Instance::initParam, EDMA3_RM_Param::isMaster, masterExists, NULL, EDMA3_RM_GblConfigParams::numDmaChannels, EDMA3_RM_Obj::numOpens, EDMA3_RM_GblConfigParams::numPaRAMSets, E +DMA3_RM_GblConfigParams::numTccs, EDMA3_RM_Obj::phyCtrllerInstId, EDMA3_RM_Instance::pResMgrObjHandle, EDMA3_RM_Instance::shadowRegs, EDMA3_RM_Obj::state, and TRUE. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_create\:Edma3RMMain}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3RMMain\:EDMA3_RM_create}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_Result EDMA3_RM +_create (unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 phyCtrllerInstId}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , const EDMA3_RM_GblConfigParams * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 gblCfgParams}{\rtlch\fcs1 +\af1 \ltrch\fcs0 \insrsid7370340 , const void * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 miscParam}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAICM}{\*\bkmkend AAAAAAAICM}Create EDMA3 Resource Manager Object. +\par This API is used to create the EDMA3 Resource Manager Object. It should be called only ONCE for each EDMA3 hardware instance. +\par Init-time Configuration structure for EDMA3 hardware is provided to pass the SoC specific information. This configuration information could be provided by the user at init-time. In case user doesn't provide it, this information coul +d be taken from the SoC specific configuration file edma3__cfg.c, in case it is available. +\par This API clears the error specific registers (EMCR/EMCRh, QEMCR, CCERRCLR) and sets the TCs priorities and Event Queues' watermark levels, if the 'miscPara +m' argument is NULL. User can avoid these registers' programming (in some specific use cases) by SETTING the 'isSlave' field of 'EDMA3_RM_MiscParam' configuration structure and passing this structure as the third argument (miscParam). +\par After successful completion of this API, Resource Manager Object's state changes to EDMA3_RM_CREATED from EDMA3_RM_DELETED. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid7370340 phyCtrllerInstId}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] EDMA3 Controller Instance Id (Hardware instance id, starting from 0). +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 gblCfgParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] SoC specific configuration structure for the EDMA3 Hardware. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 miscParam}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Misc configuration options provided in the structure 'EDMA3_RM_MiscParam'. For default options, user can pass NULL in this argument. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_SOK or EDMA3_RM Error Code +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Used to reset the Internal EDMA3 Resource Manager Data Structures for the first time. +\par We are NOT checking 'gblCfgParams' for NULL. If user has passed NULL, default config info will be taken from config file. 'param' is also not being checked because it could be NULL also. +\par Check whether user has passed the Global Config Info. If yes, copy it to the driver data structures. Else, use the info from the config file edma3Cfg.c +\par Check whether DMA channel to PaRAM Set mapping exists or not. If it does not exist, set the mapping array as 1-to-1 mapped. +\par Update the actual number of PaRAM sets. +\par Check the misc configuration options structure. Check whether the global registers' initialization is required or not. It is required ONLY if RM is running on the Master Processor. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 References contiguousParamR +es, EDMA3_RM_GblConfigParams::dmaChannelPaRAMMap, EDMA3_RM_GblConfigParams::dmaChPaRAMMapExists, EDMA3_MAX_EDMA3_INSTANCES, EDMA3_MAX_LOGICAL_CH, EDMA3_MAX_RM_INSTANCES, EDMA3_MAX_TCC, EDMA3_RM_CREATED, EDMA3_RM_DELETED, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM +_ +E_OBJ_NOT_DELETED, EDMA3_RM_SOK, edma3DmaChTccMapping, edma3GlobalRegionInit(), edma3MemCpy(), edma3MemSet(), edma3NumPaRAMSets, edma3QdmaChTccMapping, FALSE, EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_MiscParam::isSlave, NULL, EDMA3_RM_GblConfigParams::numDmaC +hannels, EDMA3_RM_Obj::numOpens, EDMA3_RM_GblConfigParams::numPaRAMSets, EDMA3_RM_GblConfigParams::numQdmaChannels, EDMA3_RM_ChBoundResources::paRAMId, EDMA3_RM_Obj::phyCtrllerInstId, EDMA3_RM_Obj::state, EDMA3_RM_ChBoundResources::tcc, and TRUE. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_delete\:Edma3RMMain}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3RMMain\:EDMA3_RM_delete}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_Result EDMA3_RM_delete (unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 phyCtrllerInstId}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , const void * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 param}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAICN}{\*\bkmkend AAAAAAAICN}Delete EDMA3 Resource Manager Object. +\par This API is used to delete the EDMA3 RM Object. It should be called once for each EDMA3 hardware instance, ONLY after closing all the previously opened EDMA3 RM Instances. +\par After successful completion of this API, Resource Manager Object's state changes to EDMA3_RM_DELETED. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid7370340 phyCtrllerInstId}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] EDMA3 Phy Controller Instance Id (Hardware instance id, starting from 0). +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 param}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] For possible future use. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_SOK or EDMA3_RM Error Code +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 If number of RM Instances is 0, then state should be EDMA3_RM_CLOSED OR EDMA3_RM_CREATED. +\par If number of RM Instances is NOT 0, then this function SHOULD NOT be called by anybody. +\par Change state to EDMA3_RM_DELETED +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 References allocatedTCCs, EDMA3_MAX_EDMA3_INSTANCES, EDMA3_RM_CLOSED, EDMA3_RM_CREATED, EDMA3_RM_DELETED, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_E_INVALID_STATE, EDMA3_ +RM_E_OBJ_NOT_CLOSED, EDMA3_RM_SOK, edma3MemSet(), NULL, and EDMA3_RM_Obj::state. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_open\:Edma3RMMain}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3RMMain\:EDMA3_RM_open}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_Handle EDMA3_RM_open (unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 phyCtrllerInstId}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , const EDMA3_RM_Param * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 initParam}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , EDMA3_RM_Result * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 errorCode}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAICO}{\*\bkmkend AAAAAAAICO}Open EDMA3 Resource Manager Instance. +\par This API is used to open an EDMA3 Resource Manager Instance. It could be called multiple times, for each possible EDMA3 shadow region. Maximum EDMA3_MAX_RM_INSTANCES instances are allowed for each EDMA3 hardware instance. +\par Also, only ONE Master Resource Manager Instance is permitted. This master instance (and hence the region to which it belongs) will only receive the EDMA3 interrupts, if enabled. +\par User could pass the instance specific configuration str +ucture (initParam->rmInstInitConfig) as a part of the 'initParam' structure, during init-time. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3__cfg.c, in case it is available. + +\par By default, this Resource Manager instance will clear the PaRAM Sets while allocating them. To change the default behavior, user should use the IOCTL interface appropriately. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid7370340 phyCtrllerInstId}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] EDMA3 Controller Instance Id (Hardware instance id, starting from 0). +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 initParam}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Used to Initialize the Resource Manager Instance (Master or Slave). +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 errorCode}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [OUT] Error code while opening RM instance. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 Handle to the opened Resource Manager instance Or NULL in case of error. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 This function disables the global interrupts (by calling API edma3OsProtectEntry with protection level EDMA3_OS_PROTECT_INTERRUPT) while modifying the global RM data structures, to make it re-entrant. +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 This API is used to open an EDMA3 Resource Manager Instance. It cou +ld be called multiple times, for each possible EDMA3 shadow region. Maximum EDMA3_MAX_RM_INSTANCES instances are allowed for each EDMA3 hardware instance. +\par Also, only ONE Master Resource Manager Instance is permitted. This master instance (and hence the region to which it belongs) will only receive the EDMA3 interrupts, if enabled. +\par User could pass the instance specific configuration structure (initParam->rmInstInitConfig) as a part of the 'initParam' structure, during init-time. In case user doesn't provide +it, this information could be taken from the SoC specific configuration file edma3__cfg.c, in case it is available. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid7370340 phyCtrllerInstId}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] EDMA3 Controller Instance Id (Hardware instance id, starting from 0). +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 initParam}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Used to Initialize the Resource Manager Instance (Master or Slave). +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 errorCode}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [OUT] Error code while opening RM instance. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 Handle to the opened Resource Manager instance Or NULL in case of error. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 This function disables the global interrupts (by calling API edma3OsProtectEntry with protection level EDMA3_OS_PROTECT_INTERRUPT) while modifying the global RM data structures, to make it re-entrant. +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Check state of RM Object. If no RM instance is opened and this is the first one, then state should be created/closed. +\par If num of instances opened is more than 0 and less than max allowed, then state should be opened. +\par Check whether user has passed information about resources owned and reserved by this instance. This is region specific information. If he has not pas +sed, dafault static config info will be taken from the config file edma3Cfg.c, according to the regionId specified. +\par resMgrIdx specifies the RM instance number created just now. Use it to populate the userInitConfig []. +\par By default, PaRAM Sets allocated using this RM Instance will get cleared during their allocation. User can stop their clearing by calling specific IOCTL command. +\par By default, during the EDMA3_RM_allocLogicalChannel (), global EDMA3 registers (DCHMAP/QCHMAP) and the allocated PaRAM Set will be +programmed accordingly, for users using this RM Instance. User can stop their pre-programming by calling EDMA3_RM_IOCTL_SET_GBL_REG_MODIFY_OPTION IOCTL command. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 References EDMA3_RM_Instance::avlblDmaChannels, EDMA3_RM_Instance::avlblPaRAMSets, EDMA3_RM_In +stance::avlblQdmaChannels, EDMA3_RM_Instance::avlblTccs, EDMA3_RM_GblConfigParams::dmaChannelPaRAMMap, EDMA3_RM_GblConfigParams::dmaChPaRAMMapExists, EDMA3_MAX_EDMA3_INSTANCES, EDMA3_MAX_RM_INSTANCES, EDMA3_OS_PROTECT_INTERRUPT, EDMA3_RM_CH_NO_PARAM_MAP, +E +DMA3_RM_CLOSED, EDMA3_RM_CREATED, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_E_INVALID_STATE, EDMA3_RM_E_MAX_RM_INST_OPENED, EDMA3_RM_E_RM_MASTER_ALREADY_EXISTS, EDMA3_RM_OPENED, EDMA3_RM_SOK, edma3MemCpy(), edma3MemSet(), edma3OsProtectEntry(), edma3OsProtectExi +t +(), edma3RegionId, edma3ShadowRegionInit(), EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_GblConfigParams::globalRegs, EDMA3_RM_Instance::initParam, EDMA3_RM_Param::isMaster, masterExists, NULL, EDMA3_RM_GblConfigParams::numDmaChannels, EDMA3_RM_Obj::numOpens, EDM +A +3_RM_GblConfigParams::numPaRAMSets, EDMA3_RM_GblConfigParams::numRegions, EDMA3_RM_GblConfigParams::numTccs, EDMA3_RM_InstanceInitConfig::ownDmaChannels, EDMA3_RM_InstanceInitConfig::ownPaRAMSets, EDMA3_RM_InstanceInitConfig::ownQdmaChannels, EDMA3_RM_Ins +t +anceInitConfig::ownTccs, EDMA3_RM_Instance::paramInitRequired, EDMA3_RM_Instance::pResMgrObjHandle, EDMA3_RM_Param::regionId, EDMA3_RM_Param::regionInitEnable, EDMA3_RM_Instance::regModificationRequired, EDMA3_RM_InstanceInitConfig::resvdPaRAMSets, EDMA3_ +RM_Param::rmInstInitConfig, EDMA3_RM_Param::rmSemHandle, EDMA3_RM_Instance::shadowRegs, EDMA3_RM_Obj::state, and TRUE. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3 Resource Manager Usage Guidelines +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc { +\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \tcl2{\*\bkmkstart _Toc211937556}EDMA3 Resource Manager Usage Guidelines{\*\bkmkend _Toc211937556}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 +\ltrch\fcs0 \fs24\insrsid7370340 EDMA3 Resource Manager Usage Guidelines}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAICP}{\*\bkmkend AAAAAAAICP} +Guidelines for typical usage of EDMA3 Resource Manager. +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 +\ltrch\fcs0 \fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Error Codes +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc { +\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \tcl2{\*\bkmkstart _Toc211937557}Error Codes{\*\bkmkend _Toc211937557}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn +\pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 Error Codes}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAICQ}{\*\bkmkend AAAAAAAICQ}Usage of Resource Manager. +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Defines +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define } +{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_BASE}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (-155) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_OBJ_NOT_DELETED}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (EDMA3_RM_E_BASE) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_OBJ_NOT_CLOSED}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (EDMA3_RM_E_BASE-1) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_OBJ_NOT_OPENED}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (EDMA3_RM_E_BASE-2) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_INVALID_PARAM}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (EDMA3_RM_E_BASE-3) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_RES_ALREADY_FREE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (EDMA3_RM_E_BASE-4) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_RES_NOT_OWNED}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (EDMA3_RM_E_BASE-5) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (EDMA3_RM_E_BASE-6) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_ALL_RES_NOT_AVAILABLE}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (EDMA3_RM_E_BASE-7) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_INVALID_STATE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (EDMA3_RM_E_BASE-8) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_MAX_RM_INST_OPENED}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (EDMA3_RM_E_BASE-9) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_RM_MASTER_ALREADY_EXISTS}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (EDMA3_RM_E_BASE-10) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (EDMA3_RM_E_BASE-11) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_SEMAPHORE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (EDMA3_RM_E_BASE-12) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_FEATURE_UNSUPPORTED}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (EDMA3_RM_E_BASE-13) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_RES_NOT_ALLOCATED}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (EDMA3_RM_E_BASE-14) +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Usage of Resource Manager. +\par +\par }\pard\plain \ltrpar\s72\ql \fi-360\li360\ri0\widctlpar\wrapdefault\faauto\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 1.\tab +Create Resource Manager Object (one for each EDMA3 hardware instance) +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_Result result = EDMA3_RM_SOK; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 unsigned int edma3HwInstanceId = 0u; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_GblConfigParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *gblCfgParams = NULL; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. This could be NULL also. In that case, static configuration will be taken. +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 result = EDMA3_RM_create (edma3HwInstanceId, gblCfgParams, NULL); +\par }\pard\plain \ltrpar\s72\ql \fi-360\li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 2.\tab Open Resource Manager Instance +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Steps + +\par {\pntext\pard\plain\ltrpar \s64 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s64\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin1080\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Param}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 initParam; +\par {\pntext\pard\plain\ltrpar \s64 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s64\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 unsigned int resMgrIdx = 0; +\par {\pntext\pard\plain\ltrpar \s64 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s64\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_Handle hRes = NULL; +\par {\pntext\pard\plain\ltrpar \s64 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s64\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 unsigned int mappedPaRAMId; +\par {\pntext\pard\plain\ltrpar \s64 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s64\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_OS_SemAttrs semAttrs = \{EDMA3_OS_SEMTYPE_FIFO, NULL\}; +\par {\pntext\pard\plain\ltrpar \s64 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s64\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_Result edma3Result; -To get the error code while opening Resource Manager instance +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s72\ql \fi-360\li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s72\ql \fi-360\li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 1.\tab initParam.regionId = Region Id e.g. (EDMA3_RM_RegionId)0u OR (EDMA3_RM_RegionId)1u +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s72\ql \fi-360\li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 1.\tab initParam.isMaster = TRUE/FALSE (Whether this EDMA3 RM instance is Master or not. The EDMA3 Shadow Region tied to the Master RM Instance will ONLY receive the EDMA3 interrupts (error or completion), if enabled). +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s72\ql \fi-360\li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 1.\tab initParam.rmSemHandle = EDMA3 RM Instance specific semaphore handle. It should be provided by the user for proper sharing of resources. +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 edma3Res +ult = edma3OsSemCreate(1, &semAttrs, &initParam.rmSemHandle ); +\par }\pard\plain \ltrpar\s72\ql \fi-360\li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s72\ql \fi-360\li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 1.\tab initParam.regionInitEnable = TRUE/FALSE (Whether init of Region Specifc registers should be done or not?); +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s72\ql \fi-360\li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 1.\tab initParam.gblerrCbParams.gblerrCb = Instance wide callback function to catch non-channel specific errors +\par 2.\tab initParam.gblerrCbParams.gblerrData = Data to be passed to global error callback function, gblerrCb. +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s72\ql \fi-360\li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 1.\tab initParam.rmInstInitConfig->ownDmaChannels[] = The bitmap(s) which indicate the DMA channels owned by this instance of the Resource Manager +\par E.g. A '1' at bit position 24 indicates that this instance of the Resource Manager owns DMA Channel Id 24 +\par Later when a request is made based on a particular Channel Id, the Resource Manager will check first if it owns that channel. If it doesnot own it, Resource Manager returns error EDMA3_RM_E_RES_NOT_OWNED. +\par 2.\tab initParam.rmInstInitConfig->ownQdmaChannels[] = The bitmap(s) which indicate the QDMA channels owned by this instance of the Resource Manager +\par 3.\tab initParam.rmInstInitConfig->ownPaRAMSets[] = The bitmap(s) which indicate the PaRAM Sets owned by this instance of the Resource Manager +\par 4.\tab initParam.rmInstInitConfig->ownTccs[] = The bitmap(s) which indicate the TCCs owned by this instance of the Resource Manager +\par +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s72\ql \fi-360\li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 1.\tab initParam.rmInstInitConfig->resvdDmaChannels[] = The bitmap(s) which indicate the DMA channels reserved by this instance of the Resource Manager +\par E.g. A '1' at bit position 24 indicates that this instance of the Resource Manager reserves Channel Id 24 +\par These channels are reserved and may be mapped to HW events, these are not given to 'EDMA3_RM_DMA_CHANNEL_ANY' or 'EDMA3_RM_RES_ANY' requests. +\par 2.\tab initParam.rmInstInitConfig->resvdQdmaChannels[] = The bitmap(s) which indicate the QDMA channels reserved by this instance of the Resource Manager +\par E.g. A '1' at bit position 1 indicates that this instance of the Resource Manager reserves QDMA Channel Id 1 +\par These channels are reserved for some specific purpose, these are not given to 'EDMA3_RM_QDMA_CHANNEL_ANY' or 'EDMA3_RM_RES_ANY' request +\par 3.\tab initParam.rmInstInitConfig->resvdPaRAMSets[] = PaRAM Sets which are reserved by this Region; +\par 4.\tab initParam.rmInstInitConfig->resvdTccs[] = TCCs which are reserved by this Region; +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 -hRes = EDMA3_RM_open (instId, &initParam, &edma3Result); +\par +\par }\pard\plain \ltrpar\s72\ql \fi-360\li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 1.\tab Register Interrupt Handlers for various interrupts like transfer completion interrupt, CC error interrupt, TC error interrupts etc, if required. +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s72\ql \fi-360\li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 1.\tab Resource Management APIs: +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 resObj; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_Result result; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 unsigned int dmaChId; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 unsigned int qdmaChId; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 unsigned int paRAMId; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 unsigned int tcc; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_QdmaTrigWord trigword; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_TccCallback tccCb; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 void *cbData; +\par }\pard\plain \ltrpar\s72\ql \fi-360\li360\ri0\widctlpar\wrapdefault\faauto\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Use Case 1: Request specific DMA Channel, say EDMA Channel 5. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +dmaChId = 5; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 resObj.type = EDMA3_RM_RES_DMA_CHANNEL; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 resObj.resId = dmaChId; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 result = EDMA3_RM_allocResource(hRes, &resObj); +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Use Case 2: Request any available DMA Channel. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +dmaChId = EDMA3_RM_RES_ANY; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 resObj.type = EDMA3_RM_RES_DMA_CHANNEL; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 resObj.resId = dmaChId; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 result = EDMA3_RM_allocResource(hRes, &resObj); +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 dmaCh1Id = resObj.resId; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Use Case 3: Request a specific QDMA Channel, say QDMA Channel 0. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +qdmaChId = 0; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 resObj.type = EDMA3_RM_RES_QDMA_CHANNEL; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 resObj.resId = qdmaChId; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 result = EDMA3_RM_allocResource(hRes, &resObj); +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Use Case 4: Request any available QDMA Channel. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +qdmaChId = EDMA3_RM_RES_ANY; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 resObj.type = EDMA3_RM_RES_QDMA_CHANNEL; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 resObj.resId = qdmaChId; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 result = EDMA3_RM_allocResource(hRes, &resObj); +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 qdmaChId = resObj.resId; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Use Case 5: Request specific Parameter RAM Set, say 20. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +paRAMId = 20; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 resObj.type = EDMA3_RM_RES_PARAM_SET; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 resObj.resId = paRAMId; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 result = EDMA3_RM_allocResource(hRes, &resObj); +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Use Case 6: Request any available Parameter RAM Set. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +paRAMId = EDMA3_RM_RES_ANY; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 resObj.type = EDMA3_RM_RES_PARAM_SET; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 resObj.resId = paRAMId; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 result = EDMA3_RM_allocResource(hRes, &resObj); +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 paRAMId = resObj.resId; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Use Case 7: Request a specific TCC, say TCC 35. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +tcc = 35; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 resObj.type = EDMA3_RM_RES_TCC; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 resObj.resId = tcc; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 result = EDMA3_RM_allocResource(hRes, &resObj); +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Use Case 8: Request any available TCC. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +tcc = EDMA3_RM_RES_ANY; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 resObj.type = EDMA3_RM_RES_TCC; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 resObj.resId = tcc; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 result = EDMA3_RM_allocResource(hRes, &resObj); +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 tcc = resObj.resId; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Use Case 9: Free the already allocated DMA channel +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +resObj.type = EDMA3_RM_RES_DMA_CHANNEL; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 resObj.resId = dmaChId; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 result = EDMA3_RM_freeResource(hRes, &resObj); +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Use Case 10: Free the already allocated QDMA channel +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +resObj.type = EDMA3_RM_RES_QDMA_CHANNEL; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 resObj.resId = qdmaChId; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 result = EDMA3_RM_freeResource(hRes, &resObj); +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Use Case 11: Free the already allocated PaRAM Set +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +resObj.type = EDMA3_RM_RES_PARAM_SET; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 resObj.resId = paRAMId; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 result = EDMA3_RM_freeResource(hRes, &resObj); +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Use Case 12: Free the already allocated TCC +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +resObj.type = EDMA3_RM_RES_TCC; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 resObj.resId = tcc; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 result = EDMA3_RM_freeResource(hRes, &resObj); +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Use Case 13: Bind DMA Channel and a PaRAM Set +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +result = EDMA3_RM_mapEdmaChannel (hRes,dmaChId,paRAMId); +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Use Case 14: Bind QDMA Channel and a PaRAM Set. Also, specify the Trigger word for the QDMA channel. +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +result = EDMA3_RM_mapQdmaChannel (hRes, qdmaChId, paRAMId, trigword); +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Use Case 15: Register a Callback function associated with a TCC +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +result = EDMA3_RM_registerTccCb (hRes,tcc,tccCb,cbData); +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Use Case 16: Unregister a Callback function associated with a TCC +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +result = EDMA3_RM_unregisterTccCb (hRes,tcc); +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Use Case 17: Allocate a logical (ANY) DMA channel. It will also allocate PaRAM Set and TCC alongwitht a DMA channel. +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +resObj.type = EDMA3_RM_RES_DMA_CHANNEL; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 resObj.resId = EDMA3_RM_DMA_CHANNEL_ANY; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 result = EDMA3_RM_allocLogicalChannel (hRes, &resObj, paRAMId, tcc); +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 dmaCh1Id = resObj.resId; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Use Case 18: Allocate a logical (ANY) QDMA channel. It will also allocate PaRAM Set and TCC alongwitht a QDMA channel. +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +resObj.type = EDMA3_RM_RES_QDMA_CHANNEL; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 resObj.resId = EDMA3_RM_QDMA_CHANNEL_ANY; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 result = EDMA3_RM_allocLogicalChannel (hRes, &resObj, paRAMId, tcc); +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 qdmaChId = resObj.resId; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Use Case 19: Allocate a Link channel. Link channel is nothing but a PaRAM Set, used for Linking purpose specifically. The allocated PaRAM Set is returned in the resObj.resId value. +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +resObj.type = EDMA3_RM_RES_PARAM_SET; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 resObj.resId = EDMA3_RM_PARAM_ANY; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 result = EDMA3_RM_allocLogicalChannel (hRes, &resObj, NULL, NULL); +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Use Ca +se 20: Free the previously allocated Link channel. It will free the PaRAM Set used for linking. +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +result = EDMA3_RM_freeLogicalChannel (hRes, &resObj); +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Use Case 21: Free the previously allocated logical DMA channel. It will also free the associated PaRAM Set and TCC. +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +resObj.type = EDMA3_RM_RES_DMA_CHANNEL; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 resObj.resId = dmaCh1Id; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 result = EDMA3_RM_freeLogicalChannel (hRes, &resObj); +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Use Case 22: Free the previously allocated logical QDMA channel. It will also free the associated PaRAM Set and TCC. +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 resObj +.type = EDMA3_RM_RES_QDMA_CHANNEL; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 resObj.resId = qdmaChId; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 result = EDMA3_RM_freeLogicalChannel (hRes, &resObj); +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s72\ql \fi-360\li360\ri0\widctlpar\wrapdefault\faauto\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 1.\tab +Close Resource Manager Instance +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Steps + +\par {\pntext\pard\plain\ltrpar \s64 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s64\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin1080\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_Result edma3Result = EDMA3_RM_SOK; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s72\ql \fi-360\li360\ri0\widctlpar\wrapdefault\faauto\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Unregister Interrupt Handlers first, if previously registered. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Delete the semaphore created during RM Instance Opening. +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +edma3Result = edma3OsSemDelete (rmSemHandle); +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Close the EDMA3 RM Instance +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +edma3Result = EDMA3_RM_close (hRes, NULL); +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s72\ql \fi-360\li360\ri0\widctlpar\wrapdefault\faauto\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 1.\tab +Delete Resource Manager Object +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Steps + +\par {\pntext\pard\plain\ltrpar \s64 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s64\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin1080\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_Result edma3Result = EDMA3_RM_SOK; +\par {\pntext\pard\plain\ltrpar \s64 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s64\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 unsigned int edmaInstanceId = 0; +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s72\ql \fi-360\li360\ri0\widctlpar\wrapdefault\faauto\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +edma3Result = EDMA3_RM_delete (edmaInstanceId, NULL); +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 Error Codes returned by the EDMA3 Resource Manager Layer +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Define Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_E_ALL_RES_NOT_AVAILABLE\:Edma3RMErrCode}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 Edma3RMErrCode\:EDMA3_RM_E_ALL_RES_NOT_AVAILABLE}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 #define EDMA3_RM_E_ALL_RES_NOT_AVAILABLE\~ (EDMA3_RM_E_BASE-7) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAICR}{\*\bkmkend AAAAAAAICR}No Resource of specified type is available +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by EDMA3_RM_allocResource(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_E_BASE\:Edma3RMErrCode}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3RMErrCode\:EDMA3_RM_E_BASE}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 #define EDMA3_RM_E_BASE\~ + (-155) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAICS}{\*\bkmkend AAAAAAAICS}Resource Manager Error Codes base define +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED\:Edma3RMErrCode}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3RMErrCode\:EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED\~ (EDMA3_RM_E_BASE-11) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAICT}{\*\bkmkend AAAAAAAICT}Callback function already registered. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by EDMA3_RM_registerTccCb(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_E_FEATURE_UNSUPPORTED\:Edma3RMErrCode}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3RMErrCode\:EDMA3_RM_E_FEATURE_UNSUPPORTED}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_RM_E_FEATURE_UNSUPPORTED\~ (EDMA3_RM_E_BASE-13) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAICU}{\*\bkmkend AAAAAAAICU}Hardware feature NOT supported +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by EDMA3_RM_mapEdmaChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_E_INVALID_PARAM\:Edma3RMErrCode}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3RMErrCode\:EDMA3_RM_E_INVALID_PARAM}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_RM_E_INVALID_PARAM\~ (EDMA3_RM_E_BASE-3) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAICV}{\*\bkmkend AAAAAAAICV}Invalid Parameter passed to API +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenc +ed by allocAnyContigRes(), EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocLogicalChannel(), EDMA3_RM_allocResource(), EDMA3_RM_checkAndClearTcc(), EDMA3_RM_close(), EDMA3_RM_create(), EDMA3_RM_delete(), EDMA3_RM_freeContiguousResource(), EDMA3_RM_freeL +o +gicalChannel(), EDMA3_RM_freeResource(), EDMA3_RM_getBaseAddress(), EDMA3_RM_getCCRegister(), EDMA3_RM_getGblConfigParams(), EDMA3_RM_getInstanceInitCfg(), EDMA3_RM_getPaRAM(), EDMA3_RM_getPaRAMPhyAddr(), EDMA3_RM_Ioctl(), EDMA3_RM_mapEdmaChannel(), EDMA3 +_RM_mapQdmaChannel(), EDMA3_RM_open(), EDMA3_RM_registerTccCb(), EDMA3_RM_setCCRegister(), EDMA3_RM_setPaRAM(), EDMA3_RM_unregisterTccCb(), EDMA3_RM_waitAndClearTcc(), findBit(), and gblChngAllocContigRes(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_E_INVALID_STATE\:Edma3RMErrCode}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3RMErrCode\:EDMA3_RM_E_INVALID_STATE}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_RM_E_INVALID_STATE\~ (EDMA3_RM_E_BASE-8) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAICW}{\*\bkmkend AAAAAAAICW}Invalid State of EDMA3 RM Obj +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by EDMA3_RM_delete(), and EDMA3_RM_open(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_E_MAX_RM_INST_OPENED\:Edma3RMErrCode}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3RMErrCode\:EDMA3_RM_E_MAX_RM_INST_OPENED}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_RM_E_MAX_RM_INST_OPENED\~ (EDMA3_RM_E_BASE-9) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAICX}{\*\bkmkend AAAAAAAICX}Maximum no of Res Mgr Instances already Opened +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by EDMA3_RM_open(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_E_OBJ_NOT_CLOSED\:Edma3RMErrCode}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3RMErrCode\:EDMA3_RM_E_OBJ_NOT_CLOSED}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_RM_E_OBJ_NOT_CLOSED\~ (EDMA3_RM_E_BASE-1) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAICY}{\*\bkmkend AAAAAAAICY}Resource Manager Object Not Closed yet. So the object cannot be deleted. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by EDMA3_RM_delete(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_E_OBJ_NOT_DELETED\:Edma3RMErrCode}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3RMErrCode\:EDMA3_RM_E_OBJ_NOT_DELETED}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_RM_E_OBJ_NOT_DELETED\~ (EDMA3_RM_E_BASE) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAICZ}{\*\bkmkend AAAAAAAICZ}Resource Manager Object Not Deleted yet. So the object cannot be created. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by EDMA3_RM_create(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_E_OBJ_NOT_OPENED\:Edma3RMErrCode}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3RMErrCode\:EDMA3_RM_E_OBJ_NOT_OPENED}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_RM_E_OBJ_NOT_OPENED\~ (EDMA3_RM_E_BASE-2) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIDA}{\*\bkmkend AAAAAAAIDA}Resource Manager Object Not Opened yet So the object cannot be closed. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by EDMA3_RM_close(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_E_RES_ALREADY_FREE\:Edma3RMErrCode}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3RMErrCode\:EDMA3_RM_E_RES_ALREADY_FREE}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_RM_E_RES_ALREADY_FREE\~ (EDMA3_RM_E_BASE-4) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIDB}{\*\bkmkend AAAAAAAIDB}Resource requested for freeing is already free +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by EDMA3_RM_freeResource(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_E_RES_NOT_ALLOCATED\:Edma3RMErrCode}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3RMErrCode\:EDMA3_RM_E_RES_NOT_ALLOCATED}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 #defi +ne EDMA3_RM_E_RES_NOT_ALLOCATED\~ (EDMA3_RM_E_BASE-14) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIDC}{\*\bkmkend AAAAAAAIDC}EDMA3 Resource NOT allocated +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by EDMA3_RM_mapEdmaChannel(), and EDMA3_RM_mapQdmaChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_E_RES_NOT_OWNED\:Edma3RMErrCode}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3RMErrCode\:EDMA3_RM_E_RES_NOT_OWNED}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 #define +EDMA3_RM_E_RES_NOT_OWNED\~ (EDMA3_RM_E_BASE-5) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIDD}{\*\bkmkend AAAAAAAIDD}Resource requested for allocation/freeing is not owned +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), and EDMA3_RM_freeResource(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_E_RM_MASTER_ALREADY_EXISTS\:Edma3RMErrCode}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3RMErrCode\:EDMA3_RM_E_RM_MASTER_ALREADY_EXISTS}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_RM_E_RM_MASTER_ALREADY_EXISTS\~ (EDMA3_RM_E_BASE-10) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIDE}{\*\bkmkend AAAAAAAIDE}More than one Res Mgr Master Instance NOT supported. Only 1 master can exist. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by EDMA3_RM_open(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_E_SEMAPHORE\:Edma3RMErrCode}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3RMErrCode\:EDMA3_RM_E_SEMAPHORE}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_RM_E_SEMAPHORE\~ (EDMA3_RM_E_BASE-12) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIDF}{\*\bkmkend AAAAAAAIDF}Semaphore related error +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE\:Edma3RMErrCode}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3RMErrCode\:EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE\~ (EDMA3_RM_E_BASE-6) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIDG}{\*\bkmkend AAAAAAAIDG}Resource is not available +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by allocAnyContigRes(), EDMA3_RM_allocContiguousResource(), and EDMA3_RM_allocResource(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3 Resources Management +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 \tcl2{\*\bkmkstart _Toc211937558}EDMA3 Resources Management{\*\bkmkend _Toc211937558}}}}\sectd +\linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3 Resources Management}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIDH} +{\*\bkmkend AAAAAAAIDH}Data Structures +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ParamentryRegs}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 EDMA3 PaRAM Set. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_PaRAMRegs}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 EDMA3 PaRAM Set in User Configurable format. +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Defines +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define } +{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_DMA_CHANNEL_ANY}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (1011u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_QDMA_CHANNEL_ANY}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (1012u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_TCC_ANY}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ (1013u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_PARAM_ANY}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ (1014u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_CH_NO_PARAM_MAP}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (1015u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_CH_NO_TCC_MAP}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (1016u) +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Enumerations +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_0}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 + = 0, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_1}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_2}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_3}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_4}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_5}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_6}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_7}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_8}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_9}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_10 +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_11}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_HW_CHANNEL_EVENT_12}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_13}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_14}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_15}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_16}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_17}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 +\ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_18}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_19}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_20}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_21}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_22}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_23}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_24}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_25}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_26}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_27}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_28}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_29}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_30}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_HW_CHANNEL_EVENT_31}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_32}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_33}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_34}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_35}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_36}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 +\ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_37}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_38}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_39}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_40}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_41}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_42}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_43}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_44}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_45}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_46}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_47}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_48}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_49}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_HW_CHANNEL_EVENT_50}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_51}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_52}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_53}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_54}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_55}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 +\ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_56}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_57}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_58}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_59}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_60}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_61}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_62}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_63}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 DMA Channels assigned to different Hardware Events. They should be used while requesting a specific DMA channel. One possible usage is to maintain a SoC specific file, + which will contain the mapping of these hardware events to the respective peripherals for better understanding and lesser probability of errors. Also, if any event associated with a particular peripheral gets changed, only that SoC specific file needs to + be changed. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_QdmaTrigWord}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_QDMA_TRIG_OPT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 0, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_QDMA_TRIG_SRC}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 1, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_QDMA_TRIG_ACNT_BCNT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 + = 2, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_QDMA_TRIG_DST}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 3, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_QDMA_TRIG_SRC_DST_BIDX}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 = 4, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_QDMA_TRIG_LINK_BCNTRLD}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 5, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_QDMA_TRIG_SRC_DST_CIDX}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 6, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_QDMA_TRIG_CCNT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 7, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_QDMA_TRIG_DEFAULT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 7 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 QDMA Trigger Word. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Cntrlr_PhyAddr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_CC_PHY_ADDR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 0, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_TC0_PHY_ADDR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_TC1_PHY_ADDR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_TC2_PHY_ADDR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_TC3_PHY_ADDR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_TC4_PHY_ADDR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_TC5_PHY_ADDR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_TC6_PHY_ADDR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_TC7_PHY_ADDR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 CC/TC Physical Address. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_IoctlCmd}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_IOCTL_MIN_IOCTL}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 0, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_IOCTL_SET_PARAM_CLEAR_OPTION}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_IOCTL_GET_PARAM_CLEAR_OPTION}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_IOCTL_SET_GBL_REG_MODIFY_OPTION}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_IOCTL_GET_GBL_REG_MODIFY_OPTION}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_IOCTL_MAX_IOCTL}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 EDMA3 Resource Manager IOCTL commands. +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Functions +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_allocResource}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *resObj) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 This API is used to allocate specified EDMA3 Resources like DMA/QDMA channel, PaRAM Set or TCC. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_freeResource}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *resObj) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 This API is used to free previously allocated EDMA3 Resources like DMA/QDMA channel, PaRAM Set or TCC. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_allocContiguousResource}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Handle}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *firstResIdObj, unsigned int numResources) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Allocate a contiguous region of specified EDMA3 Resource like DMA channel, QDMA channel, PaRAM Set or TCC. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_freeContiguousResource}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Handle}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *firstResIdObj, unsigned int numResources) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Free a contiguous region of specified EDMA3 Resource like DMA channel, QDMA channel, PaRAM Set or TCC, previously allocated. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_allocLogicalChannel}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Handle}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *lChObj, unsigned int *pParam, unsigned int *pTcc) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Request a DMA/QDMA/Link channel. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_freeLogicalChannel}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Handle}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *lChObj) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 This API is used to free the specified channel (DMA/QDMA/Link) and its associated resources (PaRAM Set, TCC etc). +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_mapEdmaChannel}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle} +{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, unsigned int channelId, unsigned int paRAMId) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Bind the resources DMA Channel and PaRAM Set. Both the DMA channel and the PaRAM set should be previously allocated. If they are not, this API will result in error. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_mapQdmaChannel}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle} +{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, unsigned int channelId, unsigned int paRAMId, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_QdmaTrigWord}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 trigWord) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Bind the resources QDMA Channel and PaRAM Set. Also, Set the trigger word for the QDMA channel. Both the QDMA channel and the PaRAM set should be previously alloc +ated. If they are not, this API will result in error. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_setCCRegister}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, unsigned int regOffset, unsigned int newRegValue) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Set the Channel Controller (CC) Register value. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_getCCRegister}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, unsigned int regOffset, unsigned int *regValue) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Get the Channel Controller (CC) Register value. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_waitAndClearTcc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, unsigned int tccNo) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Wait for a transfer completion interrupt to occur and clear it. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_checkAndClearTcc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Handle}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, unsigned int tccNo, unsigned short *tccStatus) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Returns the status of a previously initiated transfer. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_setPaRAM}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *lChObj, const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_PaRAMRegs}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *newPaRAM) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Copy the user specified PaRAM Set onto the PaRAM Set associated with the logical channel (DMA/QDMA/Link). +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_getPaRAM}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *lChObj, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_PaRAMRegs} +{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *currPaRAM) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Retrieve existing PaRAM set associated with specified logical channel (DMA/QDMA/Link). +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_getPaRAMPhyAddr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *lChObj, unsigned int *paramPhyAddr) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Get the PaRAM Set Physical Address associated with a logical channel. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_getBaseAddress}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle} +{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Cntrlr_PhyAddr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 controllerId, unsigned int *phyAddress) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Get the Channel Controller or Transfer Controller (n) Physical Address. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_getGblConfigParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (unsigned int phyCtrllerInstId, }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_GblConfigParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *gblCfgParams) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Get the SoC specific configuration structure for the EDMA3 Hardware. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_getInstanceInitCfg}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Handle}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_InstanceInitConfig}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *instanceInitConfig) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Get the RM Instance specific configuration structure for different EDMA3 resources' usage (owned resources, reserved resources etc). +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Ioctl}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_IoctlCmd}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 cmd, void *cmdArg, void *param) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 EDMA3 Resource Manager IOCTL. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 Resource Management part of the EDMA3 Resource Manager. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Define Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_CH_NO_PARAM_MAP\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 Edma3ResMgr\:EDMA3_RM_CH_NO_PARAM_MAP}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_RM_CH_NO_PARAM_MAP\~ (1015u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIDI}{\*\bkmkend AAAAAAAIDI} +This define is used to specify that a DMA channel is NOT tied to any PaRAM Set and hence any available PaRAM Set could be used for that DMA channel. It could be used in dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH], in global configuration structure }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_GblConfigParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 . +\par This value should mandatorily be used to mark DMA channels with no initial mapping to specific PaRAM Sets. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by EDMA3_RM_allocLogicalChannel(), and EDMA3_RM_open(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_CH_NO_TCC_MAP\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_CH_NO_TCC_MAP}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_RM_CH_NO_TCC_MAP\~ (1016u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIDJ}{\*\bkmkend AAAAAAAIDJ}This define is used to specify that the DMA/QDMA channel is not tied to any TCC and hence any available TCC could be used for th +at DMA/QDMA channel. It could be used in dmaChannelTccMap [EDMA3_MAX_DMA_CH], in global configuration structure }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_GblConfigParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 . +\par This value should mandatorily be used to mark DMA channels with no initial mapping to specific TCCs. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by EDMA3_RM_allocLogicalChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_DMA_CHANNEL_ANY\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_DMA_CHANNEL_ANY}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_RM_DMA_CHANNEL_ANY\~ (1011u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIDK}{\*\bkmkend AAAAAAAIDK}Used to specify any available DMA Channel while requesting one. Used in the API EDMA3_RM_allocLogi +calChannel (). DMA channel from the pool of (owned && non_reserved && available_right_now) DMA channels will be chosen and returned. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by EDMA3_RM_allocLogicalChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_PARAM_ANY\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_PARAM_ANY}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 #d +efine EDMA3_RM_PARAM_ANY\~ (1014u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIDL}{\*\bkmkend AAAAAAAIDL}Used to specify any available PaRAM Set while requesting one. Used in the API }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_allocLogicalChannel()}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , for both DMA/QDMA and Link channels. PaRAM Set from the pool of (owned && non_reserved && available_right_now) PaRAM Sets will be chosen and returned. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by EDMA3_RM_allocLogicalChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_QDMA_CHANNEL_ANY\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_QDMA_CHANNEL_ANY}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_RM_QDMA_CHANNEL_ANY\~ (1012u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIDM}{\*\bkmkend AAAAAAAIDM}Used to specify any available QDMA Channel while requesting one. Used in the API }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_allocLogicalChannel()}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 . QDMA channel from the pool of (owned && non_reserved && available_right_now) QDMA channels will be chosen and returned. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by EDMA3_RM_allocLogicalChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_TCC_ANY\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_TCC_ANY}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 #define EDMA3_RM_TCC_ANY\~ + (1013u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIDN}{\*\bkmkend AAAAAAAIDN}Used to specify any available TCC while requesting one. Used in the API }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_allocLogicalChannel()}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , for both DMA and QDMA channels. TCC from the pool of (owned && non_reserved && available_right_now) TCCs will be chosen and returned. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by EDMA3_RM_allocLogicalChannel(). +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Enumeration Type Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_Cntrlr_PhyAddr\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 Edma3ResMgr\:EDMA3_RM_Cntrlr_PhyAddr}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +enum EDMA3_RM_Cntrlr_PhyAddr +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIDO}{\*\bkmkend AAAAAAAIDO}CC/TC Physical Address. +\par Use this enum to get the physical address of the Channel Controller or the Transfer Controller. The address returned could be used by the advanced usres to set/get some specific registers direclty. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 Enumerator: }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_CC_PHY_ADDR\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_CC_PHY_ADDR}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_CC_PHY_ADDR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIDP}{\*\bkmkend AAAAAAAIDP} Channel Controller Physical Address +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_TC0_PHY_ADDR\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_TC0_PHY_ADDR}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_TC0_PHY_ADDR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIDQ}{\*\bkmkend AAAAAAAIDQ} Transfer Controller 0 Physical Address +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_TC1_PHY_ADDR\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_TC1_PHY_ADDR}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_TC1_PHY_ADDR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIDR}{\*\bkmkend AAAAAAAIDR} Transfer Controller 1 Physical Address +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_TC2_PHY_ADDR\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_TC2_PHY_ADDR}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_TC2_PHY_ADDR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIDS}{\*\bkmkend AAAAAAAIDS} Transfer Controller 2 Physical Address +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_TC3_PHY_ADDR\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_TC3_PHY_ADDR}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_TC3_PHY_ADDR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIDT}{\*\bkmkend AAAAAAAIDT} Transfer Controller 3 Physical Address +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_TC4_PHY_ADDR\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_TC4_PHY_ADDR}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_TC4_PHY_ADDR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIDU}{\*\bkmkend AAAAAAAIDU} Transfer Controller 4 Physical Address +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_TC5_PHY_ADDR\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_TC5_PHY_ADDR}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_TC5_PHY_ADDR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIDV}{\*\bkmkend AAAAAAAIDV} Transfer Controller 5 Physical Address +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_TC6_PHY_ADDR\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_TC6_PHY_ADDR}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_TC6_PHY_ADDR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIDW}{\*\bkmkend AAAAAAAIDW} Transfer Controller 6 Physical Address +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_TC7_PHY_ADDR\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_TC7_PHY_ADDR}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_TC7_PHY_ADDR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIDX}{\*\bkmkend AAAAAAAIDX} Transfer Controller 7 Physical Address +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +enum EDMA3_RM_HW_CHANNEL_EVENT +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIDY}{\*\bkmkend AAAAAAAIDY}DMA Channels assigned to different Hardware Events. They should be used while requesting a specific DMA channel. One possible usage is to maintain a + SoC specific file, which will contain the mapping of these hardware events to the respective peripherals for better understanding and lesser probability of errors. Also, if any event associated with a particular peripheral gets changed, only that SoC spe +cific file needs to be changed. +\par for eg, the sample SoC specific file "soc.h" can have these defines: +\par define EDMA3_RM_HW_CHANNEL_MCBSP_TX EDMA3_RM_HW_CHANNEL_EVENT_2 define EDMA3_RM_HW_CHANNEL_MCBSP_RX EDMA3_RM_HW_CHANNEL_EVENT_3 +\par These defines will be used by the MCBSP driver. The same event EDMA3_RM_HW_CHANNEL_EVENT_2/3 could be mapped to some other peripheral also. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 Enumerator: }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_0\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_0}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_0}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIDZ}{\*\bkmkend AAAAAAAIDZ} Channel assigned to EDMA3 Event 0 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_1\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_1}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_1}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIEA}{\*\bkmkend AAAAAAAIEA} Channel assigned to EDMA3 Event 1 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_2\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_2}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_2}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIEB}{\*\bkmkend AAAAAAAIEB} Channel assigned to EDMA3 Event 2 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_3\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_3}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_3}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIEC}{\*\bkmkend AAAAAAAIEC} Channel assigned to EDMA3 Event 3 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_4\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_4}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_4}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIED}{\*\bkmkend AAAAAAAIED} Channel assigned to EDMA3 Event 4 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_5\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_5}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_5}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIEE}{\*\bkmkend AAAAAAAIEE} Channel assigned to EDMA3 Event 5 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_6\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_6}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_6}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIEF}{\*\bkmkend AAAAAAAIEF} Channel assigned to EDMA3 Event 6 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_7\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_7}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_7}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIEG}{\*\bkmkend AAAAAAAIEG} Channel assigned to EDMA3 Event 7 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_8\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_8}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_8}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIEH}{\*\bkmkend AAAAAAAIEH} Channel assigned to EDMA3 Event 8 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_9\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_9}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_9}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIEI}{\*\bkmkend AAAAAAAIEI} Channel assigned to EDMA3 Event 9 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_10\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_10}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_10}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIEJ}{\*\bkmkend AAAAAAAIEJ} Channel assigned to EDMA3 Event 10 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_11\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_11}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_11}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIEK}{\*\bkmkend AAAAAAAIEK} Channel assigned to EDMA3 Event 11 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_12\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_12}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_12}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIEL}{\*\bkmkend AAAAAAAIEL} Channel assigned to EDMA3 Event 12 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_13\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_13}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_13}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIEM}{\*\bkmkend AAAAAAAIEM} Channel assigned to EDMA3 Event 13 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_14\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_14}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_14}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIEN}{\*\bkmkend AAAAAAAIEN} Channel assigned to EDMA3 Event 14 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_15\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_15}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_15}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIEO}{\*\bkmkend AAAAAAAIEO} Channel assigned to EDMA3 Event 15 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_16\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_16}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_16}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIEP}{\*\bkmkend AAAAAAAIEP} Channel assigned to EDMA3 Event 16 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_17\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_17}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_17}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIEQ}{\*\bkmkend AAAAAAAIEQ} Channel assigned to EDMA3 Event 17 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_18\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_18}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_18}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIER}{\*\bkmkend AAAAAAAIER} Channel assigned to EDMA3 Event 18 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_19\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_19}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_19}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIES}{\*\bkmkend AAAAAAAIES} Channel assigned to EDMA3 Event 19 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_20\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_20}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_20}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIET}{\*\bkmkend AAAAAAAIET} Channel assigned to EDMA3 Event 20 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_21\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_21}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_21}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIEU}{\*\bkmkend AAAAAAAIEU} Channel assigned to EDMA3 Event 21 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_22\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_22}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_22}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIEV}{\*\bkmkend AAAAAAAIEV} Channel assigned to EDMA3 Event 22 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_23\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_23}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_23}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIEW}{\*\bkmkend AAAAAAAIEW} Channel assigned to EDMA3 Event 23 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_24\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_24}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_24}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIEX}{\*\bkmkend AAAAAAAIEX} Channel assigned to EDMA3 Event 24 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_25\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_25}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_25}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIEY}{\*\bkmkend AAAAAAAIEY} Channel assigned to EDMA3 Event 25 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_26\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_26}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_26}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIEZ}{\*\bkmkend AAAAAAAIEZ} Channel assigned to EDMA3 Event 26 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_27\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_27}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_27}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIFA}{\*\bkmkend AAAAAAAIFA} Channel assigned to EDMA3 Event 27 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_28\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_28}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_28}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIFB}{\*\bkmkend AAAAAAAIFB} Channel assigned to EDMA3 Event 28 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_29\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_29}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_29}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIFC}{\*\bkmkend AAAAAAAIFC} Channel assigned to EDMA3 Event 29 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_30\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_30}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_30}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIFD}{\*\bkmkend AAAAAAAIFD} Channel assigned to EDMA3 Event 30 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_31\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_31}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_31}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIFE}{\*\bkmkend AAAAAAAIFE} Channel assigned to EDMA3 Event 31 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_32\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_32}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_32}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIFF}{\*\bkmkend AAAAAAAIFF} Channel assigned to EDMA3 Event 32 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_33\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_33}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_33}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIFG}{\*\bkmkend AAAAAAAIFG} Channel assigned to EDMA3 Event 33 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_34\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_34}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_34}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIFH}{\*\bkmkend AAAAAAAIFH} Channel assigned to EDMA3 Event 34 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_35\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_35}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_35}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIFI}{\*\bkmkend AAAAAAAIFI} Channel assigned to EDMA3 Event 35 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_36\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_36}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_36}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIFJ}{\*\bkmkend AAAAAAAIFJ} Channel assigned to EDMA3 Event 36 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_37\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_37}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_37}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIFK}{\*\bkmkend AAAAAAAIFK} Channel assigned to EDMA3 Event 37 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_38\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_38}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_38}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIFL}{\*\bkmkend AAAAAAAIFL} Channel assigned to EDMA3 Event 38 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_39\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_39}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_39}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIFM}{\*\bkmkend AAAAAAAIFM} Channel assigned to EDMA3 Event 39 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_40\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_40}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_40}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIFN}{\*\bkmkend AAAAAAAIFN} Channel assigned to EDMA3 Event 40 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_41\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_41}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_41}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIFO}{\*\bkmkend AAAAAAAIFO} Channel assigned to EDMA3 Event 41 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_42\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_42}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_42}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIFP}{\*\bkmkend AAAAAAAIFP} Channel assigned to EDMA3 Event 42 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_43\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_43}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_43}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIFQ}{\*\bkmkend AAAAAAAIFQ} Channel assigned to EDMA3 Event 43 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_44\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_44}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_44}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIFR}{\*\bkmkend AAAAAAAIFR} Channel assigned to EDMA3 Event 44 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_45\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_45}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_45}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIFS}{\*\bkmkend AAAAAAAIFS} Channel assigned to EDMA3 Event 45 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_46\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_46}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_46}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIFT}{\*\bkmkend AAAAAAAIFT} Channel assigned to EDMA3 Event 46 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_47\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_47}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_47}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIFU}{\*\bkmkend AAAAAAAIFU} Channel assigned to EDMA3 Event 47 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_48\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_48}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_48}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIFV}{\*\bkmkend AAAAAAAIFV} Channel assigned to EDMA3 Event 48 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_49\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_49}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_49}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIFW}{\*\bkmkend AAAAAAAIFW} Channel assigned to EDMA3 Event 49 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_50\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_50}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_50}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIFX}{\*\bkmkend AAAAAAAIFX} Channel assigned to EDMA3 Event 50 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_51\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_51}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_51}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIFY}{\*\bkmkend AAAAAAAIFY} Channel assigned to EDMA3 Event 51 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_52\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_52}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_52}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIFZ}{\*\bkmkend AAAAAAAIFZ} Channel assigned to EDMA3 Event 52 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_53\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_53}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_53}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIGA}{\*\bkmkend AAAAAAAIGA} Channel assigned to EDMA3 Event 53 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_54\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_54}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_54}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIGB}{\*\bkmkend AAAAAAAIGB} Channel assigned to EDMA3 Event 54 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_55\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_55}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_55}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIGC}{\*\bkmkend AAAAAAAIGC} Channel assigned to EDMA3 Event 55 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_56\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_56}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_56}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIGD}{\*\bkmkend AAAAAAAIGD} Channel assigned to EDMA3 Event 56 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_57\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_57}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_57}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIGE}{\*\bkmkend AAAAAAAIGE} Channel assigned to EDMA3 Event 57 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_58\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_58}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_58}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIGF}{\*\bkmkend AAAAAAAIGF} Channel assigned to EDMA3 Event 58 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_59\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_59}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_59}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIGG}{\*\bkmkend AAAAAAAIGG} Channel assigned to EDMA3 Event 59 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_60\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_60}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_60}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIGH}{\*\bkmkend AAAAAAAIGH} Channel assigned to EDMA3 Event 60 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_61\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_61}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_61}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIGI}{\*\bkmkend AAAAAAAIGI} Channel assigned to EDMA3 Event 61 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_62\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_62}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_62}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIGJ}{\*\bkmkend AAAAAAAIGJ} Channel assigned to EDMA3 Event 62 +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_63\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_HW_CHANNEL_EVENT_63}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_63}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIGK}{\*\bkmkend AAAAAAAIGK} Channel assigned to EDMA3 Event 63 +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_IoctlCmd\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_IoctlCmd}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 enum EDMA3_RM_IoctlCmd + +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIGL}{\*\bkmkend AAAAAAAIGL}EDMA3 Resource Manager IOCTL commands. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +\par Enumerator: }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_IOCTL_SET_PARAM_CLEAR_OPTION\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_IOCTL_SET_PARAM_CLEAR_OPTION}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_IOCTL_SET_PARAM_CLEAR_OPTION}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIGM}{\*\bkmkend AAAAAAAIGM} + PaRAM Sets will be cleared OR will not be cleared during allocation, depending upon this option. +\par For e.g., To clear the PaRAM Sets during allocation, cmdArg = (void *)1; +\par To NOT clear the PaRAM Sets during allocation, cmdArg = (void *)0; +\par For all other values, it will return error. +\par By default, PaRAM Sets will be cleared during allocation. +\par Note: Since this enum can change the behav +ior how the resources are initialized during their allocation, user is adviced to not use this command while allocating the resources. User should first change the behavior of resources' initialization and then should use start allocating resources. + +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_IOCTL_GET_PARAM_CLEAR_OPTION\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_IOCTL_GET_PARAM_CLEAR_OPTION}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_IOCTL_GET_PARAM_CLEAR_OPTION}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIGN}{\*\bkmkend AAAAAAAIGN} + To check whether PaRAM Sets will be cleared or not during allocation. If the value read is '1', it means that PaRAM Sets are getting cleared during allocation. If the value read is '0', it means that PaRAM Sets are NOT getting cleared during allocation. + +\par For e.g., unsigned int *isParamClearingDone = (unsigned int *)cmdArg; (*isParamClearingDone) = paramClearingRequired; +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_IOCTL_SET_GBL_REG_MODIFY_OPTION\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec +}\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_IOCTL_SET_GBL_REG_MODIFY_OPTION}}} +\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_IOCTL_SET_GBL_REG_MODIFY_OPTION}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIGO}{\*\bkmkend AAAAAAAIGO} + Global EDMA3 registers (DCHMAP/QCHMAP) and PaRAM Sets will be modified OR will not be modified during EDMA3_RM_allocLogicalChannel (), depending upon this option. +\par For e.g., To modify the Registers or PaRAM Sets during allocation, cmdArg = (void *)1; +\par To NOT modify the Registers or PaRAM Sets during allocation, cmdArg = (void *)0; +\par For all other values, it will return error. +\par By default, Registers or PaRAM Sets will be programmed during allocation. +\par Note: Since this enum can change the behavior how the resources are initialized during their allocation, user is adviced to not use this command while a +llocating the resources. User should first change the behavior of resources' initialization and then should use start allocating resources. +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_IOCTL_GET_GBL_REG_MODIFY_OPTION\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec +}\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_IOCTL_GET_GBL_REG_MODIFY_OPTION}}} +\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_IOCTL_GET_GBL_REG_MODIFY_OPTION}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIGP}{\*\bkmkend AAAAAAAIGP} + To check whether Global EDMA3 registers (DCHMAP/QCHMAP) and PaRAM Sets will be programmed or not during allocation (EDMA3_RM_allocLogicalChannel ()). If the value read is '1', it means that the registers/PaRAMs +are getting programmed during allocation. If the value read is '0', it means that the registers/PaRAMs are NOT getting programmed during allocation. +\par For e.g., unsigned int *isParamClearingDone = (unsigned int *)cmdArg; (*isParamClearingDone) = paramClearingRequired; +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_QdmaTrigWord\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_QdmaTrigWord}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +enum EDMA3_RM_QdmaTrigWord +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIGQ}{\*\bkmkend AAAAAAAIGQ}QDMA Trigger Word. +\par Use this enum to set the QDMA trigger word to any of the 8 DWords(unsigned int) within a Parameter RAM set +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 Enumerator: }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_QDMA_TRIG_OPT\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_QDMA_TRIG_OPT}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_QDMA_TRIG_OPT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIGR}{\*\bkmkend AAAAAAAIGR} + Set the OPT field (Offset Address 0h Bytes) as the QDMA trigger word +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_QDMA_TRIG_SRC\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_QDMA_TRIG_SRC}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_QDMA_TRIG_SRC}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIGS}{\*\bkmkend AAAAAAAIGS} + Set the SRC field (Offset Address 4h Bytes) as the QDMA trigger word +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_QDMA_TRIG_ACNT_BCNT\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_QDMA_TRIG_ACNT_BCNT}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_QDMA_TRIG_ACNT_BCNT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIGT}{\*\bkmkend AAAAAAAIGT} Set the (ACNT + BCNT) field (Off +set Address 8h Bytes) as the QDMA trigger word +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_QDMA_TRIG_DST\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_QDMA_TRIG_DST}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_QDMA_TRIG_DST}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIGU}{\*\bkmkend AAAAAAAIGU} + Set the DST field (Offset Address Ch Bytes) as the QDMA trigger word +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_QDMA_TRIG_SRC_DST_BIDX\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_QDMA_TRIG_SRC_DST_BIDX}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_QDMA_TRIG_SRC_DST_BIDX}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIGV}{\*\bkmkend AAAAAAAIGV} + Set the (SRCBIDX + DSTBIDX) field (Offset Address 10h Bytes) as the QDMA trigger word +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_QDMA_TRIG_LINK_BCNTRLD\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_QDMA_TRIG_LINK_BCNTRLD}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_QDMA_TRIG_LINK_BCNTRLD}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIGW}{\*\bkmkend AAAAAAAIGW} + Set the (LINK + BCNTRLD) field (Offset Address 14h Bytes) as the QDMA trigger word +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_QDMA_TRIG_SRC_DST_CIDX\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_QDMA_TRIG_SRC_DST_CIDX}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_QDMA_TRIG_SRC_DST_CIDX}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIGX}{\*\bkmkend AAAAAAAIGX} + Set the (SRCCIDX + DSTCIDX) field (Offset Address 18h Bytes) as the QDMA trigger word +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_QDMA_TRIG_CCNT\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_QDMA_TRIG_CCNT}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_QDMA_TRIG_CCNT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIGY}{\*\bkmkend AAAAAAAIGY} Set the (CCNT + RSVD) field (Offse +t Address 1Ch Bytes) as the QDMA trigger word +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_QDMA_TRIG_DEFAULT\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_QDMA_TRIG_DEFAULT}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_QDMA_TRIG_DEFAULT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIGZ}{\*\bkmkend AAAAAAAIGZ} Default Trigger Word +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Function Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_allocContiguousResource\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 Edma3ResMgr\:EDMA3_RM_allocContiguousResource}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_Result EDMA3_RM_allocContiguousResource (EDMA3_RM_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , EDMA3_RM_ResDesc * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 +firstResIdObj}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 numResources}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIHA}{\*\bkmkend AAAAAAAIHA}Allocate a contiguous region of specified EDMA3 Resource like DMA channel, QDMA channel, PaRAM Set or TCC. +\par This API is used to allocate a contiguous region of specified EDMA3 Resources like DMA channel, QDMA channel, PaRAM Set or TCC. +\par User can specify a particular resource Id to start with and go up to the number of resources requested. The specific resource id to start from could be passed in 'firstResIdObject->resId' and the number of resources requested in 'numResources'. +\par User can also request ANY available resource(s) of the type 'firstResIdObject->type' by specifying 'firstResIdObject->resId' as EDMA3_RM_RES_ANY. +\par ANY types of resources are those resources when user doesn't care about the actual resource allocated; user just wants a resource of the type specified. One use-case is to perform memory-to-memory + data transfer operation. This operation can be performed using any available DMA or QDMA channel. User doesn't need any specific channel for the same. +\par To allocate specific contiguous resources, first this API checks whether those requested resources are OWNED by the Resource Manager instance. Then it checks the current availability of those resources. +\par To allocate ANY available contiguous resources, this API tries to allocate resources from the pool of (owned && non_reserved && available_right_now) resources. +\par After allocating DMA/QDMA channels or TCCs, the same resources are enabled in the shadow region specific register (DRAE/DRAEH/QRAE). Allocated PaRAM Sets are initialized to NULL before this API returns. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Handle to the previously opened Resource Manager Instance. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 firstResIdObj}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 + [IN] Handle to the first resource descriptor object, which needs to be allocated. firstResIdObject->resId could be a valid resource id in case user wants to allocate specific resources OR it could be EDM +A3_RM_RES_ANY in case user wants only the required number of resources and doesn't care about which resources were allocated. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 numResources}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Number of contiguous resources user wants to allocate. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_SOK or EDMA3_RM Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 This function acquires a RM Instance specific semaphore to prevent simultaneous access to the global pool of resources. It is re-entrant, but should not be called from the user callback function (ISR context). +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Take the instance specific semaphore, to prevent simultaneous access to the shared resources. +\par Enable the DMA channel in the DRAE registers also. +\par Enable the DMA channel in the DRAEH registers also. +\par Enable the QDMA channel in the QRAE register also. +\par Enable the Interrupt channel in the DRAE/DRAEH registers a +lso. Also, If the region id coming from this RM instance is same as the Master RM Instance's region id, only then we will be getting the interrupts on the same side. So save the TCC in the allocatedTCCs[] array. +\par Also, make the actual PARAM Set NULL, checking the flag whether it is required or not. +\par Take the instance specific semaphore, to prevent simultaneous access to the shared resources. +\par We have to search three different arrays, namely ownedResoures, avlblResources and resvdResources, to find the 'common' contiguous resources. For this, take an 'AND' of all three arrays in one single array and use your algorithm on that array. +\par Try to allocate 'numResources' contiguous resources of type RES_ANY. +\par If result != EDMA3_RM_SOK, resource allocation failed. Else resources successfully allocated. +\par Check the Resource Allocation Result 'result' first. If Resource Allocation has resulted in an error, return it (having more priority than semResult. Else, return semResult. +\par Resource Allocation successful, return semResult for returning semaphore. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +References allocAnyContigRes(), allocatedTCCs, EDMA3_RM_Instance::avlblDmaChannels, EDMA3_RM_Instance::avlblPaRAMSets, EDMA3_RM_Instance::avlblQdmaChannels, EDMA3_RM_Instance::avlblTccs, contiguousDmaRes, contiguousParamRes, contig +uousQdmaRes, contiguousTccRes, EDMA3_OSSEM_NO_TIMEOUT, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_E_RES_NOT_OWNED, EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE, EDMA3_RM_RES_ANY, EDMA3_RM_RES_DMA_CHANNEL, EDMA3_RM_RES_PARAM_SET, EDMA3_RM_RES_QDMA_CHANNEL, EDMA3_RM_RES_ +T +CC, EDMA3_RM_SOK, edma3MemSet(), edma3OsSemGive(), edma3OsSemTake(), edma3RegionId, FALSE, EDMA3_RM_Obj::gblCfgParams, gblChngAllocContigRes(), EDMA3_RM_GblConfigParams::globalRegs, EDMA3_RM_Instance::initParam, NULL, EDMA3_RM_GblConfigParams::numDmaChann +e +ls, EDMA3_RM_GblConfigParams::numPaRAMSets, EDMA3_RM_GblConfigParams::numQdmaChannels, EDMA3_RM_GblConfigParams::numTccs, EDMA3_RM_InstanceInitConfig::ownDmaChannels, EDMA3_RM_InstanceInitConfig::ownPaRAMSets, EDMA3_RM_InstanceInitConfig::ownQdmaChannels, + +EDMA3_RM_InstanceInitConfig::ownTccs, EDMA3_RM_Instance::paramInitRequired, EDMA3_RM_Instance::pResMgrObjHandle, EDMA3_RM_Param::regionId, EDMA3_RM_ResDesc::resId, EDMA3_RM_InstanceInitConfig::resvdDmaChannels, EDMA3_RM_InstanceInitConfig::resvdPaRAMSets, + EDMA3_RM_InstanceInitConfig::resvdQdmaChannels, EDMA3_RM_InstanceInitConfig::resvdTccs, EDMA3_RM_Param::rmInstInitConfig, EDMA3_RM_Param::rmSemHandle, EDMA3_RM_Instance::shadowRegs, TRUE, and EDMA3_RM_ResDesc::type. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_allocLogicalChannel\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_allocLogicalChannel}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_Result EDMA3_RM_allocLogicalChannel (EDMA3_RM_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , EDMA3_RM_ResDesc * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 lChObj}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , unsigned int * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 pParam}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , unsigned int * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 pTcc}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIHB}{\*\bkmkend AAAAAAAIHB}Request a DMA/QDMA/Link channel. +\par This API is used to allocate a logical channel (DMA/QDMA/Link) along with the associated resources. For DMA and QDMA channels, TCC and PaRAM Set are also allocated along with the requested channel. For Link channel, ONLY a PaRAM Set is allocated. +\par Note: To free the logical channel allocated by this API, user should call EDMA3_RM_freeLogicalChannel () ONLY to de-allocate all the allocated resources and remove certain mappings. +\par User can request a specific logical channel by passing the channel id in 'lChObj->resId' and channe +l type in 'lChObj->type'. Note that the channel id is the same as the actual resource id. For e.g. in the case of QDMA channels, valid channel ids are from 0 to 7 only. +\par User can also request ANY available logical channel of the type 'lChObj->type' by speci +fying 'lChObj->resId' as: a) EDMA3_RM_DMA_CHANNEL_ANY: For DMA channels b) EDMA3_RM_QDMA_CHANNEL_ANY: For QDMA channels, and c) EDMA3_RM_PARAM_ANY: For Link channels. Normally user should use this value to request link channels (PaRAM Sets used for linkin +g purpose only), unless he wants to use some specific link channels (PaRAM Sets) which is also allowed. +\par This API internally uses EDMA3_RM_allocResource () to allocate the desired resources (DMA/QDMA channel, PaRAM Set and TCC). +\par For DMA/QDMA channels, after allocating all the EDMA3 resources, this API sets the TCC field of the OPT PaRAM Word with the allocated TCC. +\par For DMA channel, it also sets the DCHMAP register, if required. +\par For QDMA channel, it sets the QCHMAP register and CCNT as trigger word and enables the QDMA channel by writing to the QEESR register. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Handle to the previously opened Resource Manager Instance. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 lChObj}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN/OUT] Handle to the requested logical channel object, which needs to be allocated. It could be a specific + logical channel or ANY available logical channel of the requested type. In case user passes a specific resource Id, lChObj value is left unchanged. In case user requests ANY available resource, the allocated resource id is returned in lChObj->resId. + +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 pParam}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 + [IN/OUT] PaRAM Set for a particular logical (DMA/QDMA) channel. Not used if user requested for a Link channel. In case user passes a specific PaRAM Set value, pParam value is left unchanged. In case user requests ANY available PaRAM Set by passing 'EDMA3 +_RM_PARAM_ANY' in pParam, the allocated one is returned in pParam. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 pTcc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 + [IN/OUT] TCC for a particular logical (DMA/QDMA) channel. Not used if user requested for a Link channel. In case user passes a specific TCC value, pTcc value is left unchanged. In case + user requests ANY available TCC by passing 'EDMA3_RM_TCC_ANY' in pTcc, the allocated one is returned in pTcc. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_SOK or EDMA_RM Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 This function internally calls EDMA3_RM_allocResource (), which acquires a RM Instance specific + semaphore to prevent simultaneous access to the global pool of resources. It is re-entrant for unique logical channel values, but SHOULD NOT be called from the user callback function (ISR context). +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 This API is used to allocate a logical channel (DMA/QDMA/ +Link) along with the associated resources. For DMA and QDMA channels, TCC and PaRAM Set are also allocated along with the requested channel. For Link channel, ONLY a PaRAM Set is allocated. +\par Note: To free the logical channel allocated by this API, user should call EDMA3_RM_freeLogicalChannel () ONLY to de-allocate all the allocated resources and remove certain mappings. +\par User can request a specific logical channel by passing the channel id in 'lChObj->resId' and channel type in 'lChObj->type'. Note that the c +hannel id is the same as the actual resource id. For e.g. in the case of QDMA channels, valid channel ids are from 0 to 7 only. +\par User can also request ANY available logical channel of the type 'lChObj->type' by specifying 'lChObj->resId' as: a) EDMA3_RM_DMA +_CHANNEL_ANY: For DMA channels b) EDMA3_RM_QDMA_CHANNEL_ANY: For QDMA channels, and c) EDMA3_RM_PARAM_ANY: For Link channels. Normally user should use this value to request link channels (PaRAM Sets used for linking purpose only), unless he wants to use s +ome specific link channels (PaRAM Sets) which is also allowed. +\par This API internally uses EDMA3_RM_allocResource () to allocate the desired resources (DMA/QDMA channel, PaRAM Set and TCC). +\par For DMA/QDMA channels, after allocating all the EDMA3 resources, this API sets the TCC field of the OPT PaRAM Word with the allocated TCC. +\par For DMA channel, it also sets the DCHMAP register, if required. +\par For QDMA channel, it sets the QCHMAP register and CCNT as trigger word and enables the QDMA channel by writing to the QEESR register. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Handle to the previously opened Resource Manager Instance. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 lChObj}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN/OUT] Handle to the requested logical channel object, which needs to be allocated. It could be a specific logical channel or ANY available logical + channel of the requested type. In case user passes a specific resource Id, lChObj value is left unchanged. In case user requests ANY available resource, the allocated resource id is returned in lChObj->resId. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 pParam}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN/OUT] PaRAM Set for a particular log +ical (DMA/QDMA) channel. Not used if user requested for a Link channel. In case user passes a specific PaRAM Set value, pParam value is left unchanged. In case user requests ANY available PaRAM Set, the allocated one is returned in pParam. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 pTcc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN/OUT] TC +C for a particular logical (DMA/QDMA) channel. Not used if user requested for a Link channel. In case user passes a specific TCC value, pTcc value is left unchanged. In case user requests ANY available TCC, the allocated one is returned in pTcc +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_SOK or EDMA_RM Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 This function internally calls EDMA3_RM_allocResource (), which acquires a RM Instance specific semaphore to prevent simultaneous access to the global pool of resources. It is re-entrant for unique logical channel val +ues, but SHOULD NOT be called from the user callback function (ISR context). +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 If the request is for a DMA or QDMA channel, check the pParam and pTcc objects also. For the Link channel request, they could be NULL. +\par Check the PaRAM Set user has specified for this DMA channel. Two cases exist: a) DCHMAP exists: Any PaRAM Set can be used b) DCHMAP does not exist: Should not be possible only if the channel allocated (ANY) and PaRAM requested are same. +\par If some PaRAM set is statically mapped to the returned channel number, use that. +\par Channel mapping does not exist. If the PaRAM Set requested is the same as dma channel allocated (coincidentally), it is fine. Else return error. +\par Free the previously allocated DMA channel also. +\par Check the PaRAM Set user has specified for this DMA channel. Two cases exist: a) DCHMAP exists: Any PaRAM Set can be used b) DCHMAP does not exist: Should not be possible only if the channel allocated (ANY) and PaRAM requested are same. +\par If some PaRAM set is statically mapped to the returned channel number, use that. +\par Channel mapping does not exist. If the PaRAM Set requested is the same as dma channel allocated (coincidentally), it is fine. Else return error. +\par Free the previously allocated DMA channel also. +\par Check the PaRAM Set user has specified for this QDMA channel. If he has specified any particular PaRAM Set, use that. +\par Check the PaRAM Set user has specified for this QDMA channel. If he has specified any particular PaRAM Set, use that. +\par Remove any linking. Before doing that, check whether it is permitted or not. +\par For DMA/QDMA channels, we still have to allocate more resources like TCC, PaRAM Set etc. For Link channel, only the PaRAMSet is required and that has been allocated so no further operations required. +\par PaRAM Set allocation succeeded. Save the PaRAM Set first. +\par Check first whether the global registers and the allocated PaRAM Set can be modified or not. If yes, do the needful. Else leave this for the user. +\par Do the mapping between DMA channel and PaRAM Set. Do this for the EDMA3 Controllers which have a register for mapping DMA Channel to a particular PaRAM Set. +\par TCC allocation failed, free the previously allocated PaRAM Set and DMA channel. +\par PaRAM Set allocation failed, free the previously allocated DMA channel also. +\par PaRAM Set allocation succeeded. Save the PaRAM Set first. +\par Check first whether the global registers and the allocated PaRAM Set can be modified or not. If yes, do the needful. Else leave this for the user. +\par TCC allocation failed, free the previously allocated PaRAM Set and QDMA channel. +\par PaRAM Set allocation failed, free the previously allocated QDMA channel also. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 References EDMA3_RM_GblConfigParams::dmaChannelPaRAMMap, EDMA3_RM_GblConfigParams::dmaChannelTccMap, EDMA3_RM_GblConfigParams::dmaChPaRAMMapExists, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_QDMA +_CH, EDMA3_RM_allocResource(), EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_DCH_PARAM_CLR_MASK, EDMA3_RM_DCH_PARAM_SET_MASK, EDMA3_RM_DMA_CH_MAX_VAL, EDMA3_RM_DMA_CHANNEL_ANY, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_freeResource(), EDMA3_RM_LINK_ +C +H_MAX_VAL, EDMA3_RM_LINK_CH_MIN_VAL, EDMA3_RM_OPT_TCC_CLR_MASK, EDMA3_RM_OPT_TCC_SET_MASK, EDMA3_RM_PARAM_ANY, EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD, EDMA3_RM_QCH_PARAM_CLR_MASK, EDMA3_RM_QCH_PARAM_SET_MASK, EDMA3_RM_QCH_TRWORD_CLR_MASK, EDMA3_RM_QCH_TRWORD_S +E +T_MASK, EDMA3_RM_QDMA_CH_MIN_VAL, EDMA3_RM_QDMA_CHANNEL_ANY, EDMA3_RM_QDMA_TRIG_DEFAULT, EDMA3_RM_RES_ANY, EDMA3_RM_RES_DMA_CHANNEL, EDMA3_RM_RES_PARAM_SET, EDMA3_RM_RES_QDMA_CHANNEL, EDMA3_RM_RES_TCC, EDMA3_RM_SOK, EDMA3_RM_TCC_ANY, edma3NumPaRAMSets, ED +M +A3_RM_Obj::gblCfgParams, EDMA3_RM_GblConfigParams::globalRegs, NULL, EDMA3_RM_ChBoundResources::paRAMId, EDMA3_RM_Obj::phyCtrllerInstId, EDMA3_RM_Instance::pResMgrObjHandle, EDMA3_RM_Instance::regModificationRequired, EDMA3_RM_ResDesc::resId, EDMA3_RM_Ins +tance::shadowRegs, EDMA3_RM_ChBoundResources::tcc, TRUE, and EDMA3_RM_ResDesc::type. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_allocResource\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_allocResource}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_Result EDMA3_RM_allocResource (EDMA3_RM_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , EDMA3_RM_ResDesc * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 resObj}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIHC}{\*\bkmkend AAAAAAAIHC}This API is used to allocate specified EDMA3 Resources like DMA/QDMA channel, PaRAM Set or TCC. +\par Note: To free the resources allocated by this API, user should call EDMA3_RM_freeResource () ONLY to de-allocate all the allocated resources. +\par User can either request a specific resource by passing the resource id in 'resObj->resId' OR request ANY available resource of the type 'resObj->type'. +\par ANY types of resources are those resources when user doesn't care about the actual resource allocated; user just +wants a resource of the type specified. One use-case is to perform memory-to-memory data transfer operation. This operation can be performed using any available DMA or QDMA channel. User doesn't need any specific channel for the same. +\par To allocate a specific resource, first this API checks whether that resource is OWNED by the Resource Manager instance. Then it checks the current availability of that resource. +\par To allocate ANY available resource, this API tries to allocate a resource from the pool of (owned && non_reserved && available_right_now) resources. +\par After allocating a DMA/QDMA channel or TCC, the same resource is enabled in the shadow region specific register (DRAE/DRAEH/QRAE). +\par Allocated PaRAM Set is initialized to NULL before this API returns if user has requested for one. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Handle to the previously opened Resource Manager Instance. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 resObj}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN/OUT] Handle to the resource descriptor object, which needs to be allocated. In case user passes a specific resource Id, resObj value +is left unchanged. In case user requests ANY available resource, the allocated resource id is returned in resObj. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_SOK or EDMA3_RM Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 This function acquires a RM Instance specific semaphore to prevent simultaneous access to the global pool of resources. It is re-entrant, but should not be called from the user callback function (ISR context). +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Take the instance specific semaphore, to prevent simultaneous access to the shared resources. +\par Check if the register modification flag is set or not. +\par Enable the DMA channel in the DRAE/DRAEH registers also. +\par Check if the register modification flag is set or not. +\par Enable the DMA channel in the DRAE registers also. +\par Enable the DMA channel in the DRAEH registers also. +\par Check if the register modification flag is set or not. +\par Enable the QDMA channel in the QRAE register also. +\par Check if the register modification flag is set or not. +\par Enable the QDMA channel in the QRAE register also. +\par Check if the register modification flag is set or not. +\par Enable the Interr +upt channel in the DRAE/DRAEH registers also. Also, If the region id coming from this RM instance is same as the Master RM Instance's region id, only then we will be getting the interrupts on the same side. So save the TCC in the allocatedTCCs[] array. + +\par Do not modify this global array if the register modificatio flag is not set. Reason being is based on this flag, the IPR/ICR or error bit is cleared in the completion or error handler ISR. +\par Do not modify this global array if the register modificatio flag is not set. Reason being is based on this flag, the IPR/ICR or error bit is cleared in the completion or error handler ISR. +\par Check if the register modification flag is set or not. +\par Enable the Interrupt channel in the DRAE/DRAEH registers also. Also, If the region + id coming from this RM instance is same as the Master RM Instance's region id, only then we will be getting the interrupts on the same side. So save the TCC in the allocatedTCCs[] array. +\par Do not modify this global array if the register modificatio flag is not set. Reason being is based on this flag, the IPR/ICR or error bit is cleared in the completion or error handler ISR. +\par Do not modify this global array if the register modificatio flag is not set. Reason being is based on this flag, the IPR/ICR or error bit is cleared in the completion or error handler ISR. +\par Also, make the actual PARAM Set NULL, checking the flag whether it is required or not. +\par Also, make the actual PARAM Set NULL, checking the flag whether it is required or not. +\par Check the Resource Allocation Result 'result' first. If Resource Allocation has resulted in an error, return it (having more priority than semResult. Else, return semResult. +\par Resource Allocation successful, return semResult for returning semaphore. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 References allocatedTCCs, EDMA3_RM_ +Instance::avlblDmaChannels, EDMA3_RM_Instance::avlblPaRAMSets, EDMA3_RM_Instance::avlblQdmaChannels, EDMA3_RM_Instance::avlblTccs, EDMA3_OSSEM_NO_TIMEOUT, EDMA3_RM_E_ALL_RES_NOT_AVAILABLE, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_E_RES_NOT_OWNED, EDMA3_RM_E_SPE +C +IFIED_RES_NOT_AVAILABLE, EDMA3_RM_RES_ANY, EDMA3_RM_RES_DMA_CHANNEL, EDMA3_RM_RES_PARAM_SET, EDMA3_RM_RES_QDMA_CHANNEL, EDMA3_RM_RES_TCC, EDMA3_RM_SOK, edma3MemSet(), edma3OsSemGive(), edma3OsSemTake(), edma3RegionId, FALSE, EDMA3_RM_Obj::gblCfgParams, ED +M +A3_RM_GblConfigParams::globalRegs, EDMA3_RM_Instance::initParam, NULL, EDMA3_RM_GblConfigParams::numDmaChannels, EDMA3_RM_GblConfigParams::numPaRAMSets, EDMA3_RM_GblConfigParams::numQdmaChannels, EDMA3_RM_GblConfigParams::numTccs, EDMA3_RM_InstanceInitCon +f +ig::ownDmaChannels, EDMA3_RM_InstanceInitConfig::ownPaRAMSets, EDMA3_RM_InstanceInitConfig::ownQdmaChannels, EDMA3_RM_InstanceInitConfig::ownTccs, EDMA3_RM_Instance::paramInitRequired, EDMA3_RM_Instance::pResMgrObjHandle, EDMA3_RM_Param::regionId, EDMA3_R +M +_Instance::regModificationRequired, EDMA3_RM_ResDesc::resId, EDMA3_RM_InstanceInitConfig::resvdDmaChannels, EDMA3_RM_InstanceInitConfig::resvdPaRAMSets, EDMA3_RM_InstanceInitConfig::resvdQdmaChannels, EDMA3_RM_InstanceInitConfig::resvdTccs, EDMA3_RM_Param +::rmInstInitConfig, EDMA3_RM_Param::rmSemHandle, EDMA3_RM_Instance::shadowRegs, TRUE, and EDMA3_RM_ResDesc::type. +\par Referenced by EDMA3_RM_allocLogicalChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_checkAndClearTcc\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_checkAndClearTcc}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_ +Result EDMA3_RM_checkAndClearTcc (EDMA3_RM_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 tccNo}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 , unsigned short * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 tccStatus}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIHD}{\*\bkmkend AAAAAAAIHD}Returns the status of a previously initiated transfer. +\par This is a non-blocking function that returns the status of a previously initiated transfer, based on the IPR/IPRH bit. This bit corresponds to the tccNo specified by the user. It clears the corresponding bit, if SET, while returning also. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Handle to the previously opened Resource Manager Instance. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 tccNo}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] TCC, specific to which the function checks the status of the IPR/IPRH bit. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 tccStatus}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 + [IN/OUT] Status of the transfer is returned here. Returns "TRUE" if the transfer has completed (IPR/IPRH bit SET), "FALSE" if the transfer has not completed successfully (IPR/IPRH bit NOT SET). +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_SOK or EDMA3_RM Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 This function is re-entrant for different tccNo. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 References EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_SOK, FALSE, EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_GblConfigParams::globalRegs, EDMA3_RM_ +Instance::initParam, NULL, EDMA3_RM_GblConfigParams::numTccs, EDMA3_RM_Instance::pResMgrObjHandle, EDMA3_RM_Param::regionId, and TRUE. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_freeContiguousResource\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_freeContiguousResource}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_Result EDMA3_RM_freeContiguousResource (EDMA3_RM_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , EDMA3_RM_ResDesc * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 +firstResIdObj}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 numResources}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIHE}{\*\bkmkend AAAAAAAIHE}Free a contiguous region of specified EDMA3 Resource like DMA channel, QDMA channel, PaRAM Set or TCC, previously allocated. +\par This API + frees a contiguous region of specified EDMA3 Resources like DMA channel, QDMA channel, PaRAM Set or TCC, which have been previously allocated. In case of an error during the freeing of any specific resource, user can check the 'firstResIdObj' object to k +now the last resource id whose freeing has failed. In case of success, there is no need to check this object. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Handle to the previously opened Resource Manager Instance. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 firstResIdObj}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN/OUT] Handle to the first resource descri +ptor object, which needs to be freed. In case of an error while freeing any particular resource, the last resource id whose freeing has failed is returned in this resource descriptor object. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 numResources}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Number of contiguous resources allocated previously which user wants to release +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 This is a re-entrant function which internally calls }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_freeResource()}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 for resource de-allocation. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 References EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_freeResource(), EDMA3_RM_RES_DMA_CHANNEL, EDMA3_RM_RES_PARAM_SET +, EDMA3_RM_RES_QDMA_CHANNEL, EDMA3_RM_RES_TCC, EDMA3_RM_SOK, EDMA3_RM_Obj::gblCfgParams, NULL, EDMA3_RM_GblConfigParams::numDmaChannels, EDMA3_RM_GblConfigParams::numPaRAMSets, EDMA3_RM_GblConfigParams::numQdmaChannels, EDMA3_RM_GblConfigParams::numTccs, +EDMA3_RM_Instance::pResMgrObjHandle, EDMA3_RM_ResDesc::resId, and EDMA3_RM_ResDesc::type. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_freeLogicalChannel\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_freeLogicalChannel}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_Result EDMA3_RM_freeLogicalChannel (EDMA3_RM_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , EDMA3_RM_ResDesc * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 lChObj}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIHF}{\*\bkmkend AAAAAAAIHF}This API is used to free the specified channel (DMA/QDMA/Link) and its associated resources (PaRAM Set, TCC etc). +\par This API internally uses EDMA3_RM_freeResource () to free the desired resources. +\par For DMA/QDMA channels, it also clears the DCHMAP/QCHMAP registers +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Handle to the previously opened Resource Manager Instance. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 lChObj}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Handle to the logical channel object, which needs to be freed +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_SOK or EDMA_RM Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 This is a re-entrant function which internally calls EDMA3_RM_freeResource () for resource de-allocation. +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Validate DMA channel id first. It should be a valid channel id. +\par Perfectly valid channel id. Clear some channel specific registers, if it is permitted. +\par Try to free the DMA Channel now. DMA Channel should be freed only in the end because while freeing, DRAE registers will be RESET. After that, no shadow region specific DMA channel register can be modified. So reset that DRAE register ONLY in the end. + +\par Calculate QDMA Logical Channel Id first. User has given the actual QDMA channel id. So we have to convert it to make the logical QDMA channel id first. +\par Validate QDMA channel id first. It should be a valid channel id. +\par Perfectly valid channel id. Clear some channel specific registers, if it is permitted. +\par Try to free the QDMA Channel now. QDMA Channel should be freed only in the end because while freeing, QRAE registers will be RESET. After that, no shadow region specific QDMA channel register can be modified. So reset that QDRAE register ONLY in the end. + +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +References EDMA3_RM_Instance::avlblDmaChannels, EDMA3_RM_Instance::avlblQdmaChannels, EDMA3_RM_GblConfigParams::dmaChPaRAMMapExists, EDMA3_MAX_DMA_CH, EDMA3_MAX_QDMA_CH, EDMA3_MAX_TCC, EDMA3_RM_DCH_PARAM_CLR_MASK, EDMA3_ +RM_E_INVALID_PARAM, EDMA3_RM_freeResource(), EDMA3_RM_LINK_CH_MAX_VAL, EDMA3_RM_LINK_CH_MIN_VAL, EDMA3_RM_QCH_PARAM_CLR_MASK, EDMA3_RM_QCH_TRWORD_CLR_MASK, EDMA3_RM_QDMA_CH_MIN_VAL, EDMA3_RM_RES_DMA_CHANNEL, EDMA3_RM_RES_PARAM_SET, EDMA3_RM_RES_QDMA_CHANN +E +L, EDMA3_RM_RES_TCC, EDMA3_RM_SOK, edma3NumPaRAMSets, FALSE, EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_GblConfigParams::globalRegs, EDMA3_RM_Instance::initParam, NULL, EDMA3_RM_InstanceInitConfig::ownDmaChannels, EDMA3_RM_InstanceInitConfig::ownQdmaChannels, E +D +MA3_RM_ChBoundResources::paRAMId, EDMA3_RM_Obj::phyCtrllerInstId, EDMA3_RM_Instance::pResMgrObjHandle, EDMA3_RM_Instance::regModificationRequired, EDMA3_RM_ResDesc::resId, EDMA3_RM_Param::rmInstInitConfig, EDMA3_RM_Instance::shadowRegs, EDMA3_RM_ChBoundRe +sources::tcc, TRUE, and EDMA3_RM_ResDesc::type. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_freeResource\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_freeResource}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_Result EDMA3_RM_freeResource (EDMA3_RM_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , const EDMA3_RM_ResDesc * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 resObj}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIHG}{\*\bkmkend AAAAAAAIHG}This API is used to free previously allocated EDMA3 Resources like DMA/QDMA channel, PaRAM Set or TCC. +\par To free a specific resource, first this API checks whether that resource is OWNED by the Resource Manager Instance. Then it checks whether that resource has been allocated by the Resource Manager instance or not. +\par After freeing a DMA/QDMA channel or TCC, the same resource is disabled in the shadow region specific register (DRAE/DRAEH/QRAE). +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Handle to the previously opened Resource Manager Instance. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 resObj}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Handle to the resource descriptor object, which needs to be freed. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_SOK or EDMA3_RM Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 This function disables the global interrupts to prevent simultaneous access to the global pool of resources. It is re-entrant. +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Check if the register modification flag is set or not. +\par DMA Channel is freed. Reset the bit specific to the DMA channel in the DRAE/DRAEH register also. +\par Check if the register modification flag is set or not. +\par QDMA Channel is freed. Reset the bit specific to the QDMA channel in the QRAE register also. +\par Check if the register modification flag is set or not. +\par Interrupt Channel is freed. Reset the bit specific to the Interrupt channel in the DRAE/DRAEH register also. Also, if we have earlier saved this TCC in allocatedTCCs[] array, remove it from there too. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +References allocatedTCCs, EDMA3_RM_Instance::avlblDmaChannels, EDMA3_RM_Instance::avlblPaRAMSets, EDMA3_RM_Instance::avlblQdmaChannels, EDMA3_RM_Instance::avlblTccs, EDMA3_OS_PROTECT_INTERRUPT, EDMA3_RM_E_INVALID +_PARAM, EDMA3_RM_E_RES_ALREADY_FREE, EDMA3_RM_E_RES_NOT_OWNED, EDMA3_RM_RES_DMA_CHANNEL, EDMA3_RM_RES_PARAM_SET, EDMA3_RM_RES_QDMA_CHANNEL, EDMA3_RM_RES_TCC, EDMA3_RM_SOK, edma3OsProtectEntry(), edma3OsProtectExit(), edma3RegionId, FALSE, EDMA3_RM_Obj::gb +l +CfgParams, EDMA3_RM_GblConfigParams::globalRegs, EDMA3_RM_Instance::initParam, NULL, EDMA3_RM_InstanceInitConfig::ownDmaChannels, EDMA3_RM_InstanceInitConfig::ownPaRAMSets, EDMA3_RM_InstanceInitConfig::ownQdmaChannels, EDMA3_RM_InstanceInitConfig::ownTccs +, EDMA3_RM_Instance::pResMgrObjHandle, EDMA3_RM_Param::regionId, EDMA3_RM_Instance::regModificationRequired, EDMA3_RM_ResDesc::resId, EDMA3_RM_Param::rmInstInitConfig, TRUE, and EDMA3_RM_ResDesc::type. +\par Referenced by EDMA3_RM_allocLogicalChannel(), EDMA3_RM_freeContiguousResource(), and EDMA3_RM_freeLogicalChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_getBaseAddress\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_getBaseAddress}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_Result EDMA3_RM_getBaseAddress (EDMA3_RM_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , EDMA3_RM_Cntrlr_PhyAddr }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 +controllerId}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , unsigned int * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 phyAddress}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIHH}{\*\bkmkend AAAAAAAIHH}Get the Channel Controller or Transfer Controller (n) Physical Address. +\par +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Handle to the previously opened Resource Manager Instance. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 controllerId}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Channel Controller or Transfer Controller (n) for which the physical address is required. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 phyAddress}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN/OUT] Physical address is returned here. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_SOK or EDMA3_RM Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 This function is re-entrant. +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Since the TCs enum start from 1, and TCs start from 0, subtract 1 from the enum to get the actual address. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +References EDMA3_RM_CC_PHY_ADDR, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_SOK, EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_GblConfigParams::globalRegs, NULL, EDMA3_RM_GblConfigParams::numTcs, EDMA3_RM_Instance::pResMgrObjHandle, and EDMA3_RM_GblConfigParams::tcRegs. + +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_getCCRegister\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_getCCRegister}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_Result EDMA3_RM_getCCRegister (EDMA3_RM_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 regOffset}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , unsigned int * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 regValue}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIHI}{\*\bkmkend AAAAAAAIHI}Get the Channel Controller (CC) Register value. +\par +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Handle to the previously opened Resource Manager Instance. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 regOffset}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] CC Register offset whose value is needed. It should be word-aligned. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 regValue}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN/OUT] Fetched CC Register Value +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_SOK or EDMA3_RM Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 This function is re-entrant. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 References EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_SOK, EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_GblConfigParams::globalRegs, NULL, and EDMA3_RM_Instance::pResMgrObjHandle. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_getGblConfigParams\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_getGblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_Result EDMA3_RM_getGblConfigParams (unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 phyCtrllerInstId}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , EDMA3_RM_GblConfigParams * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\insrsid7370340 gblCfgParams}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIHJ}{\*\bkmkend AAAAAAAIHJ}Get the SoC specific configuration structure for the EDMA3 Hardware. +\par This API is used to fetch the global SoC specific configuration structure for the EDMA3 Hardware. It is useful for the user who has not passed this information during }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_create()}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 and taken the default configuration coming along with the package. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid7370340 phyCtrllerInstId}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] EDMA3 Controller Instance Id (Hardware instance id, starting from 0). +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 gblCfgParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN/OUT] SoC specific configuration structure for the EDMA3 Hardware will be returned here. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_SOK or EDMA3_RM Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 This function is re-entrant. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 References EDMA3_MAX_EDMA3_INSTANCES, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_SOK, edma3MemCpy(), and NULL. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_getInstanceInitCfg\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_getInstanceInitCfg}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_Result EDMA3_RM_getInstanceInitCfg (EDMA3_RM_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , EDMA3_RM_InstanceInitConfig * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\insrsid7370340 instanceInitConfig}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIHK}{\*\bkmkend AAAAAAAIHK}Get the RM Instance specific configuration structure for different EDMA3 resources' usage (owned resources, reserved resources etc). +\par This API is used to fe +tch the Resource Manager Instance specific configuration structure, for a specific shadow region. It is useful for the user who has not passed this information during EDMA3_RM_opn() and taken the default configuration coming along with the package. EDMA3 +resources, owned and reserved by this RM instance, will be returned from this API. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Handle to the previously opened Resource Manager Instance. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 instanceInitConfig}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN/OUT] RM Instance specific configuration structure will be returned here. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_SOK or EDMA3_RM Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 This function is re-entrant. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 References EDMA3_MAX_RM_INSTANCES, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_SOK, edma3MemCpy(), NULL, EDMA3_RM_Obj::phyCtrllerInstId, and EDMA3_RM_Instance::pResMgrObjHandle. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_getPaRAM\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_getPaRAM}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_Result EDMA3_RM_getPaRAM (EDMA3_RM_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , EDMA3_RM_ResDesc * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 lChObj}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , EDMA3_RM_PaRAMRegs * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 currPaRAM}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIHL}{\*\bkmkend AAAAAAAIHL}Retrieve existing PaRAM set associated with specified logical channel (DMA/QDMA/Link). +\par +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Handle to the previously opened Resource Manager Instance. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 lChObj}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Logical Channel object for which the PaRAM set is requested. User should pass the resource type and id in this object. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 currPaRAM}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN/OUT] User gets the existing PaRAM here. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_SOK or EDMA3_RM Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 This function is re-entrant. +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 User has passed the actual param set value here. Use this value only +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 References EDMA3_MAX_QDMA_CH, EDMA3_RM_DMA_CH_MAX +_VAL, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_QDMA_CH_MIN_VAL, EDMA3_RM_RES_DMA_CHANNEL, EDMA3_RM_RES_PARAM_SET, EDMA3_RM_RES_QDMA_CHANNEL, EDMA3_RM_SOK, edma3MemCpy(), edma3NumPaRAMSets, EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_GblConfigParams::globalRegs, NULL, +EDMA3_RM_ChBoundResources::paRAMId, EDMA3_RM_Obj::phyCtrllerInstId, EDMA3_RM_Instance::pResMgrObjHandle, EDMA3_RM_ResDesc::resId, and EDMA3_RM_ResDesc::type. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_getPaRAMPhyAddr\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_getPaRAMPhyAddr}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_Resu +lt EDMA3_RM_getPaRAMPhyAddr (EDMA3_RM_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , EDMA3_RM_ResDesc * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 lChObj}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 , unsigned int * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 paramPhyAddr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIHM}{\*\bkmkend AAAAAAAIHM}Get the PaRAM Set Physical Address associated with a logical channel. +\par This function returns the PaRAM Set Phy Address (unsigned 32 bits). The returned address could be used by the advanced users to program the PaRAM Set directly without using any APIs. +\par Least significant 16 bits of this address could be used to program the LINK field in the PaRAM Set. Users which program the LINK field directly SHOULD use this API to get the associated PaRAM Set address with the LINK channel. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Handle to the previously opened Resource Manager Instance. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 lChObj}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Logical Channel object for which the PaRAM set physical address is required. User should pass the resource type and id in this object. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 paramPhyAddr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN/OUT] PaRAM Set physical address is returned here. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_SOK or EDMA3_RM Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 This function is re-entrant. +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 User has passed the actual param set value here. Use this value only +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +References EDMA3_MAX_QDMA_CH, EDMA3_RM_DMA_CH_MAX_VAL, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_QDMA_CH_MIN_VAL, EDMA3_RM_RES_DMA_CHANNEL, EDMA3_RM_RES_PARAM_SET, EDMA3_RM_RES_QDMA_CHANNEL, EDMA3_RM_SOK, edma3NumPaRAMSets, EDMA3_RM_ +Obj::gblCfgParams, EDMA3_RM_GblConfigParams::globalRegs, NULL, EDMA3_RM_ChBoundResources::paRAMId, EDMA3_RM_Obj::phyCtrllerInstId, EDMA3_RM_Instance::pResMgrObjHandle, EDMA3_RM_ResDesc::resId, and EDMA3_RM_ResDesc::type. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_Ioctl\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_Ioctl}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_Result EDMA3_RM_Ioctl (EDMA3_RM_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , EDMA3_RM_IoctlCmd }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 cmd}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 , void * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 cmdArg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , void * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 param}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIHN}{\*\bkmkend AAAAAAAIHN}EDMA3 Resource Manager IOCTL. +\par This function provides IOCTL functionality for EDMA3 Resource Manager +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Handle to the previously opened Resource Manager Instance. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 cmd}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] IOCTL command to be performed +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 cmdArg}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN/OUT] IOCTL command argument (if any) +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 param}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN/OUT] Device/Cmd specific argument. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_SOK or EDMA3_RM Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 For 'EDMA3_RM_IOCTL_GET_PARAM_CLEAR_OPTION', this function is re-entrant. For 'EDMA3_RM_IOCTL_SET_PARAM_CLEAR_OPTION', this function is re-entrant for different Resource Manager Instances (handles). +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 This function provides IOCTL functionality for EDMA3 Resource Manager +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Handle to the previously opened Resource Manager Instance. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 cmd}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] IOCTL command to be performed +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 cmdArg}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN/OUT] IOCTL command argument (if any) +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 param}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN/OUT] Device/Cmd specific argument +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_SOK or EDMA3_RM Error Code +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Set/Reset the flag which is being used to do the global registers and PaRAM modification. +\par Get the flag which is being used to do the global registers and PaRAM modification. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 References EDMA3_RM_E_INVALID_PARAM, EDMA3_ +RM_IOCTL_GET_GBL_REG_MODIFY_OPTION, EDMA3_RM_IOCTL_GET_PARAM_CLEAR_OPTION, EDMA3_RM_IOCTL_SET_GBL_REG_MODIFY_OPTION, EDMA3_RM_IOCTL_SET_PARAM_CLEAR_OPTION, EDMA3_RM_SOK, NULL, EDMA3_RM_Instance::paramInitRequired, and EDMA3_RM_Instance::regModificationReq +uired. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_mapEdmaChannel\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_mapEdmaChannel}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_Result EDMA3_RM_mapEdmaChannel (EDMA3_RM_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 channelId}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 paRAMId}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIHO}{\*\bkmkend AAAAAAAIHO}Bind the resources DMA Channel and PaRAM Set. +Both the DMA channel and the PaRAM set should be previously allocated. If they are not, this API will result in error. +\par This API sets the DCHMAP register for a specific DMA channel. This register is used to specify the PaRAM Set associated with that particular DMA Channel. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Handle to the previously opened Resource Manager Instance. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 channelId}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Previously allocated DMA Channel on which Transfer will occur. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 paRAMId}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Previously allocated PaRAM Set which needs to be associated with the dma channel. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_SOK or EDMA_RM Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 This API is useful only for the EDMA3 Controllers which have a register for mapping a DMA Channel to a particular PaRAM Set (DCHMAP register). On platforms where this feature is not + supported, this API returns error code: EDMA3_RM_E_FEATURE_UNSUPPORTED. This function is re-entrant for unique channelId. It is non-re-entrant for same channelId values. +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Do this for the EDMA3 Controllers which have a register for mapping DMA Channel to a particular PaRAM Set. So check dmaChPaRAMMapExists first. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 References EDMA3_RM_Instance::avlblDmaChannels, EDMA3_RM_Instance::avlblPaRAMSets, EDMA3_RM_GblConfigParams::dmaChPaRAMMapExists, EDMA3_RM_DCH_PARAM_CLR_MASK, EDMA3_RM_DCH_PARAM_SET_MASK, EDMA3_RM +_E_FEATURE_UNSUPPORTED, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_E_RES_NOT_ALLOCATED, EDMA3_RM_SOK, FALSE, EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_GblConfigParams::globalRegs, EDMA3_RM_Instance::initParam, NULL, EDMA3_RM_GblConfigParams::numDmaChannels, EDMA3_RM_G +blConfigParams::numPaRAMSets, EDMA3_RM_InstanceInitConfig::ownDmaChannels, EDMA3_RM_InstanceInitConfig::ownPaRAMSets, EDMA3_RM_Instance::pResMgrObjHandle, EDMA3_RM_Param::rmInstInitConfig, and TRUE. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_mapQdmaChannel\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_mapQdmaChannel}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_Result EDMA3_RM_mapQdmaChannel (EDMA3_RM_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 channelId}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 paRAMId}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , EDMA3_RM_QdmaTrigWord }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 trigWord} +{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIHP}{\*\bkmkend AAAAAAAIHP}Bind the resources QDMA Channel and PaRAM Set. Also, Set the trigger word fo +r the QDMA channel. Both the QDMA channel and the PaRAM set should be previously allocated. If they are not, this API will result in error. +\par This API sets the QCHMAP register for a specific QDMA channel. This register is used to specify the PaRAM Set associated with that particular QDMA Channel along with the trigger word. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Handle to the previously opened Resource Manager Instance. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 channelId}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Previously allocated QDMA Channel on which Transfer will occur. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 paRAMId}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Previously allocated PaRAM Set, which needs to be associated with channelId +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 trigWord}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 + [IN] The Trigger Word for the channel. Trigger Word is the word in the PaRAM Register Set which - when written to by CPU -will start the QDMA transfer automatically +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_SOK or EDMA3_RM Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 This function is re-entrant for unique channelId. It is non-re-entrant for same channelId values. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 References EDMA3_RM_Instance::avlblPaRAMSets, EDMA3_RM_Instance::avlblQdmaChannels, EDMA3_RM_E_INVALID_PARAM, EDMA3_ +RM_E_RES_NOT_ALLOCATED, EDMA3_RM_QCH_PARAM_CLR_MASK, EDMA3_RM_QCH_PARAM_SET_MASK, EDMA3_RM_QCH_TRWORD_CLR_MASK, EDMA3_RM_QCH_TRWORD_SET_MASK, EDMA3_RM_QDMA_TRIG_CCNT, EDMA3_RM_QDMA_TRIG_OPT, EDMA3_RM_SOK, FALSE, EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_GblCon +f +igParams::globalRegs, EDMA3_RM_Instance::initParam, NULL, EDMA3_RM_GblConfigParams::numPaRAMSets, EDMA3_RM_GblConfigParams::numQdmaChannels, EDMA3_RM_InstanceInitConfig::ownPaRAMSets, EDMA3_RM_InstanceInitConfig::ownQdmaChannels, EDMA3_RM_Instance::pResMg +rObjHandle, and EDMA3_RM_Param::rmInstInitConfig. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_setCCRegister\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_setCCRegister}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_Result EDMA3_RM_setCCRegister (EDMA3_RM_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 regOffset}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 newRegValue}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIHQ}{\*\bkmkend AAAAAAAIHQ}Set the Channel Controller (CC) Register value. +\par +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Handle to the previously opened Resource Manager Instance. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 regOffset}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] CC Register offset whose value needs to be set. It should be word-aligned. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 newRegValue}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] New CC Register Value +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_SOK or EDMA3_RM Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 This function is non re-entrant for users using the same Resource Manager handle. Before modifying a register, it tries to acquire a semaphore (RM instance specific), to protect simultaneous mod +ification of the same register by two different users. After the successful change, it releases the semaphore. For users using different RM handles, this function is re-entrant. +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Take the instance specific semaphore, to prevent simultaneous access to the shared resources. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +References EDMA3_OSSEM_NO_TIMEOUT, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_SOK, edma3OsSemGive(), edma3OsSemTake(), EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_GblConfigParams::globalRegs, EDMA3_RM_Instance::initParam, NULL, EDMA3_RM_Instance::pResMg +rObjHandle, and EDMA3_RM_Param::rmSemHandle. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_setPaRAM\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_setPaRAM}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_Result EDMA3_RM_setPaRAM (EDMA3_RM_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , EDMA3_RM_ResDesc * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 lChObj}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , const EDMA3_RM_PaRAMRegs * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 newPaRAM}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIHR}{\*\bkmkend AAAAAAAIHR}Copy the user specified PaRAM Set onto the PaRAM Set associated with the logical channel (DMA/QDMA/Link). +\par This API takes a PaRAM Set as input and copies it onto the actual PaRAM Set associated with the logical channel. OPT field of the PaRAM Set is written first and the CCNT field is written last. +\par Caution: It should be used carefully when programming the QDMA channels whose trigger words are not CCNT field. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Handle to the previously opened Resource Manager Instance. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 lChObj}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Logical Channel object for which new PaRAM set is specified. User should pass the resource type and id in this object. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 newPaRAM}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] PaRAM set to be copied onto existing one +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_SOK or EDMA3_RM Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 This function is re-entrant for unique lChObj values. It is non- re-entrant for same lChObj value. +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 User has passed the actual param set value here. Use this value only +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 References EDMA3_MAX_QDMA_CH, EDMA3_RM_DMA_CH_MAX_VAL, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_QDMA_CH_MIN_VAL, EDMA3_RM_RES_DM +A_CHANNEL, EDMA3_RM_RES_PARAM_SET, EDMA3_RM_RES_QDMA_CHANNEL, EDMA3_RM_SOK, edma3MemCpy(), edma3NumPaRAMSets, EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_GblConfigParams::globalRegs, NULL, EDMA3_RM_ChBoundResources::paRAMId, EDMA3_RM_Obj::phyCtrllerInstId, EDMA3 +_RM_Instance::pResMgrObjHandle, EDMA3_RM_ResDesc::resId, and EDMA3_RM_ResDesc::type. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_waitAndClearTcc\:Edma3ResMgr}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3ResMgr\:EDMA3_RM_waitAndClearTcc}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_Result EDMA3_RM_waitAndClearTcc (EDMA3_RM_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 tccNo}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIHS}{\*\bkmkend AAAAAAAIHS}Wait for a transfer completion interrupt to occur and clear it. +\par This is a blocking function that returns when the IPR/IPRH bit corresponding to the tccNo specified, is SET. It clears the corresponding bit while returning also. +\par This function waits for the specific bit indefinitely in a tight loop, with out any delay in between. USE IT CAUTIOUSLY. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\ai\af0 \ltrch\fcs0 \i\insrsid7370340 hEdmaResMgr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] Handle to the previously opened Resource Manager Instance. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 tccNo}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] TCC, specific to which the function waits on a IPR/IPRH bit. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_SOK or EDMA3_RM Error Code +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 This function is re-entrant for different tccNo. +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Bit found SET, transfer is completed, clear the pending interrupt and return. +\par Bit found SET, transfer is completed, clear the pending interrupt and return. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +References EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_SOK, FALSE, EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_GblConfigParams::globalRegs, EDMA3_RM_Instance::initParam, NULL, EDMA3_RM_GblConfigParams::numTccs, EDMA3_RM_Instance::pResMgrObjHandle, and EDMA3_RM_Para +m::regionId. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Log Service +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 \tcl2{\*\bkmkstart _Toc211937559}Log Service{\*\bkmkend _Toc211937559}}}}\sectd +\linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Log Service}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIHT} +{\*\bkmkend AAAAAAAIHT}Defines +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define } +{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 ARG1}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (arg1)\~ (arg1 << 8) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 ARG2}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 (arg2)\~ (arg2 << 16) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 ARG3}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 (arg3)\~ (arg3 << 24) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_DESC}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 (event, arg1, arg2, arg3)\~ (event | ARG1(arg1) | ARG2(arg2) | ARG3(arg3)) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_LOG_EVENT}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ LOG_printf4 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Enumerations +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_logEventType}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_eINT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 +\ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_eINT_START}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_eINT_END}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_eFUNC}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_eFUNC_START}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 EDMA3_DVT_eFUNC_END}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_ePACKET_START}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 EDMA3_DVT_ePACKET_END}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_eDATA_SND}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 EDMA3_DVT_eDATA_SND_START}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_eDATA_SND_END}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 EDMA3_DVT_eDATA_RCV}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_eRCV_START}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 EDMA3_DVT_eRCV_END}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_eSMPL_COUNTER}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 EDMA3_DVT_eEVENT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_eEVENT_START}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 EDMA3_DVT_eEVENT_END}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 enum }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_logDataDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_dNONE}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_dINST}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_dINITIATOR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_dMSG_ID}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 +\ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_dCOUNTER}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_dSIZE_BYTES}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_dSIZE_WORDS}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_dPADD}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 EDMA3_DVT_dDADD}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_dDATA}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_DVT_dPACKET_ID}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_dCHANNEL_ID}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \} +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Variables +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +far LOG_Obj }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 DVTEvent_Log}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 EDMA3 error/event/message logging/tracing service +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 +\ltrch\fcs0 \fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Internal Interface Definition for Resource Manager +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 \tcl2{\*\bkmkstart _Toc211937560}Internal Interface Definition for Resource Manager +{\*\bkmkend _Toc211937560}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Internal Interface Definition for Resource Manager}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 +\af1 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIHU}{\*\bkmkend AAAAAAAIHU}Modules +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +Object Maintenance}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Data Structures +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ChBoundResources}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 EDMA3 Channel-Bound resources. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_TccCallbackParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 TCC Callback - Caters to channel specific status reporting. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 Documentation of the Internal Interface of Resource Manager +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 +\ltrch\fcs0 \fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Object Maintenance +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 \tcl2{\*\bkmkstart _Toc211937561}Object Maintenance{\*\bkmkend _Toc211937561}}}}\sectd +\linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Object Maintenance}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIHV} +{\*\bkmkend AAAAAAAIHV}Modules +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +Boundary Values}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Data Structures +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Obj}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 EDMA3 Hardware Instance Configuration Structure. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Instance}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 EDMA3 RM Instance Specific Configuration Structure. +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Enumerations +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ObjState}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_DELETED}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 0, }{\rtlch\fcs1 +\ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_CREATED}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 1, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_OPENED}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 2, }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_CLOSED}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 3 \} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 Maintenance of the EDMA3 Resource Manager Object +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Enumeration Type Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_ObjState\:Edma3ResMgrIntObjMaint}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 Edma3ResMgrIntObjMaint\:EDMA3_RM_ObjState}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +enum EDMA3_RM_ObjState +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIHW}{\*\bkmkend AAAAAAAIHW}To maintain the state of the EDMA3 Resource Manager Object +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 Enumerator: }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_DELETED\:Edma3ResMgrIntObjMaint}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgrIntObjMaint\:EDMA3_RM_DELETED}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_DELETED}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIHX}{\*\bkmkend AAAAAAAIHX} Object deleted +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_CREATED\:Edma3ResMgrIntObjMaint}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgrIntObjMaint\:EDMA3_RM_CREATED}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_CREATED}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIHY}{\*\bkmkend AAAAAAAIHY} Obect Created +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_OPENED\:Edma3ResMgrIntObjMaint}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgrIntObjMaint\:EDMA3_RM_OPENED}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_OPENED}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIHZ}{\*\bkmkend AAAAAAAIHZ} Object Opened +\par }{\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_CLOSED\:Edma3ResMgrIntObjMaint}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li720\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec } +\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \v\fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Edma3ResMgrIntObjMaint\:EDMA3_RM_CLOSED}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_CLOSED}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIIA}{\*\bkmkend AAAAAAAIIA} Object Closed +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Boundary Values +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 \tcl2{\*\bkmkstart _Toc211937562}Boundary Values{\*\bkmkend _Toc211937562}}}}\sectd +\linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Boundary Values}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIIB} +{\*\bkmkend AAAAAAAIIB}Defines +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define } +{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_DMA_CH_MAX_VAL}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (EDMA3_MAX_DMA_CH - 1u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_LINK_CH_MIN_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (EDMA3_MAX_DMA_CH) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_LINK_CH_MAX_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS - 1u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_QDMA_CH_MIN_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_QDMA_CH_MAX_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS + EDMA3_MAX_QDMA_CH - 1u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_LOG_CH_MAX_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (EDMA3_RM_QDMA_CH_MAX_VAL) +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 Boundary Values for Logical Channel Ranges +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Define Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_DMA_CH_MAX_VAL\:Edma3RMIntBoundVals}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 Edma3RMIntBoundVals\:EDMA3_RM_DMA_CH_MAX_VAL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_RM_DMA_CH_MAX_VAL\~ (EDMA3_MAX_DMA_CH - 1u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIIC}{\*\bkmkend AAAAAAAIIC}Max of DMA Channels +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by EDMA3_RM_allocLogicalChannel(), EDMA3_RM_getPaRAM(), EDMA3_RM_getPaRAMPhyAddr(), and EDMA3_RM_setPaRAM(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_LINK_CH_MAX_VAL\:Edma3RMIntBoundVals}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3RMIntBoundVals\:EDMA3_RM_LINK_CH_MAX_VAL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_RM_LINK_CH_MAX_VAL\~ (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS - 1u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIID}{\*\bkmkend AAAAAAAIID}Max of Link Channels +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by EDMA3_RM_allocLogicalChannel(), and EDMA3_RM_freeLogicalChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_LINK_CH_MIN_VAL\:Edma3RMIntBoundVals}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3RMIntBoundVals\:EDMA3_RM_LINK_CH_MIN_VAL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_RM_LINK_CH_MIN_VAL\~ (EDMA3_MAX_DMA_CH) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIIE}{\*\bkmkend AAAAAAAIIE}Min of Link Channels +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by EDMA3_RM_allocLogicalChannel(), and EDMA3_RM_freeLogicalChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_LOG_CH_MAX_VAL\:Edma3RMIntBoundVals}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3RMIntBoundVals\:EDMA3_RM_LOG_CH_MAX_VAL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_RM_LOG_CH_MAX_VAL\~ (EDMA3_RM_QDMA_CH_MAX_VAL) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIIF}{\*\bkmkend AAAAAAAIIF}Max of Logical Channels +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_QDMA_CH_MAX_VAL\:Edma3RMIntBoundVals}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3RMIntBoundVals\:EDMA3_RM_QDMA_CH_MAX_VAL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_RM_QDMA_CH_MAX_VAL\~ (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS + EDMA3_MAX_QDMA_CH - 1u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIIG}{\*\bkmkend AAAAAAAIIG}Max of QDMA Channels +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_QDMA_CH_MIN_VAL\:Edma3RMIntBoundVals}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Edma3RMIntBoundVals\:EDMA3_RM_QDMA_CH_MIN_VAL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_RM_QDMA_CH_MIN_VAL\~ (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIIH}{\*\bkmkend AAAAAAAIIH}Min of QDMA Channels +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by EDMA3_RM_allocLogicalChannel(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_getPaRAM(), EDMA3_RM_getPaRAMPhyAddr(), and EDMA3_RM_setPaRAM(). +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 +\ltrch\fcs0 \fs24\insrsid7370340 \sect }\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s1\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 +\rtlch\fcs1 \ab\af1\afs36\alang1025 \ltrch\fcs0 \b\f1\fs36\lang1033\langfe1033\kerning36\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Data Structure Documentation}{\pard\plain \ltrpar +\s1\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs36\alang1025 \ltrch\fcs0 +\b\v\f1\fs36\lang1033\langfe1033\kerning36\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart _Toc211937563}Data Structure Documentation{\*\bkmkend _Toc211937563}}}}\sectd \linex0\sectdefaultcl\sftnbj { +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_ChBoundResources Struct Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc { +\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \tcl2{\*\bkmkstart _Toc211937564}EDMA3_RM_ChBoundResources{\*\bkmkend _Toc211937564}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn +\pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_ChBoundResources}}} +\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIII}{\*\bkmkend AAAAAAAIII}EDMA3 Channel-Bound resources. +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Data Fields +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 int }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 paRAMId}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 tcc}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +EDMA3 Channel-Bound resources. +\par Used to maintain information of the EDMA3 resources (specifically Parameter RAM set and TCC), bound to the particular channel within EDMA3_RM_allocLogicalChannel (). +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Field Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 +\ltrch\fcs0 \fs24\insrsid7370340 paRAMId\:EDMA3_RM_ChBoundResources}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_ChBoundResources\:paRAMId}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 int EDMA3_RM_ChBoundResources::paRAMId +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIIU}{\*\bkmkend AAAAAAAIIU}PaRAM Set number associated with the particular channel +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocLogicalChannel(), EDMA3_RM_create(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_getPaRAM(), EDMA3_RM_getPaRAMPhyAddr(), and EDMA3_RM_setPaRAM(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 tcc\:EDMA3_RM_ChBoundResources}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_ChBoundResources\:tcc}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 unsigne +d int EDMA3_RM_ChBoundResources::tcc +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIIV}{\*\bkmkend AAAAAAAIIV}TCC associated with the particular channel +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocLogicalChannel(), EDMA3_RM_create(), and EDMA3_RM_freeLogicalChannel(). +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\fs22\insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +The documentation for this struct was generated from the following file: +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 e +dma3resmgr.h}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \sect +}\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_GblConfigParams Struct Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \tcl2 +{\*\bkmkstart _Toc211937565}EDMA3_RM_GblConfigParams{\*\bkmkend _Toc211937565}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 +\v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIIJ} +{\*\bkmkend AAAAAAAIIJ}Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Data Fields +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 numDmaChannels}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 numQdmaChannels}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 numTccs}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 numPaRAMSets}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 numEvtQueue}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 numTcs}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 numRegions}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 unsigned short }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 dmaChPaRAMMapExists}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Channel mapping existence. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +unsigned short }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 memProtectionExists}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 void * }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 globalRegs}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 void * }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 tcRegs}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 [EDMA3_MAX_TC] +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 xferCompleteInt}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 ccError}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 tcError}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 [EDMA3_MAX_TC] +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 evtQPri}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 [EDMA3_MAX_EVT_QUE] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 EDMA3 TC priority setting. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 evtQueueWaterMarkLvl}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [EDMA3_MAX_EVT_QUE] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Event Queues Watermark Levels. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 tcDefaultBurstSize}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [EDMA3_MAX_TC] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Default Burst Size (DBS) of TCs. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 dmaChannelPaRAMMap}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [EDMA3_MAX_DMA_CH] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Mapping from DMA channels to PaRAM Sets. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 dmaChannelTccMap}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [EDMA3_MAX_DMA_CH] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Mapping from DMA channels to TCCs. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 dmaChannelHwEvtMap}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [EDMA3_MAX_DMA_CHAN_DWRDS] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 +\i\insrsid7370340 Mapping from DMA channels to Hardware Events. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. +\par This configuration structure is used to specify the EDMA3 Resource Manager global settings, specific to the SoC. For e.g. number of DMA/QDMA channels, number of PaRAM sets, TCCs, event queues, transfer controllers, base addresse +s of CC global registers and TC registers, interrupt number for EDMA3 transfer completion, CC error, event queues' priority, watermark threshold level etc. This configuration information is SoC specific and could be provided by the user at run-time while +creating the EDMA3 RM Object, using API EDMA3_RM_create. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3__cfg.c, in case it is available. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Field Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 +\ltrch\fcs0 \fs24\insrsid7370340 numDmaChannels\:EDMA3_RM_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_GblConfigParams\:numDmaChannels}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 +\af1 \ltrch\fcs0 \insrsid7370340 unsigned int EDMA3_RM_GblConfigParams::numDmaChannels +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIIW}{\*\bkmkend AAAAAAAIIW}Number of DMA Channels supported by the underlying EDMA3 Controller. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_close(), EDMA3_RM_create(), EDMA3_RM_freeContiguousResource(), EDMA3_RM_mapEdmaChannel(), EDMA3_RM_open(), EDMA3_RM_registerTccCb(), and EDMA3_RM_unregisterTccCb(). + +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 numQdmaChannels\:EDMA3_RM_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_GblConfigParams\:numQdmaChannels}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 unsigned int EDMA3_RM_GblConfigParams::numQdmaChannels +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIIX}{\*\bkmkend AAAAAAAIIX}Number of QDMA Channels supported by the underlying EDMA3 Controller +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_create(), EDMA3_RM_freeContiguousResource(), EDMA3_RM_mapQdmaChannel(), EDMA3_RM_registerTccCb(), and EDMA3_RM_unregisterTccCb(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 numTccs\:EDMA3_RM_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_GblConfigParams\:numTccs}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +unsigned int EDMA3_RM_GblConfigParams::numTccs +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIIY}{\*\bkmkend AAAAAAAIIY}Number of Interrupt Channels supported by the underlying EDMA3 Controller +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_checkAndClearTcc(), EDMA3_RM_close(), EDMA3_RM_freeContiguousResource(), EDMA3_RM_open(), EDMA3_RM_registerTccCb(), and EDMA3_RM_waitAndClearTcc(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 numPaRAMSets\:EDMA3_RM_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_GblConfigParams\:numPaRAMSets}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +unsigned int EDMA3_RM_GblConfigParams::numPaRAMSets +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIIZ}{\*\bkmkend AAAAAAAIIZ}Number of PaRAM Sets supported by the underlying EDMA3 Controller +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_close(), EDMA3_RM_create(), EDMA3_RM_freeContiguousResource(), EDMA3_RM_mapEdmaChannel(), EDMA3_RM_mapQdmaChannel(), and EDMA3_RM_open(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 numEvtQueue\:EDMA3_RM_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_GblConfigParams\:numEvtQueue}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +unsigned int EDMA3_RM_GblConfigParams::numEvtQueue +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIJA}{\*\bkmkend AAAAAAAIJA}Number of Event Queues in the underlying EDMA3 Controller +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by edma3CCErrHandler(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 numTcs\:EDMA3_RM_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_GblConfigParams\:numTcs}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 u +nsigned int EDMA3_RM_GblConfigParams::numTcs +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIJB}{\*\bkmkend AAAAAAAIJB}Number of Transfer Controllers (TCs) in the underlying EDMA3 Controller +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_getBaseAddress(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 numRegions\:EDMA3_RM_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_GblConfigParams\:numRegions}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +unsigned int EDMA3_RM_GblConfigParams::numRegions +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIJC}{\*\bkmkend AAAAAAAIJC}Number of Regions in the underlying EDMA3 Controller +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_open(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 dmaChPaRAMMapExists\:EDMA3_RM_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_GblConfigParams\:dmaChPaRAMMapExists}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 unsigned short EDMA3_RM_GblConfigParams::dmaChPaRAMMapExists +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIJD}{\*\bkmkend AAAAAAAIJD}Channel mapping existence. +\par A value of 0 (No channel mapping) implies that there is fixed association between a DMA channel and a PaRAM Set or, in other words, DMA channel n can ONLY use PaRAM Set n (No availability of DCHMAP registers) for transfers to happen. +\par A value of 1 implies the presence of DCHMAP registers for the DMA channels and hence the flexibility of associating any DMA channel to any PaRAM Set. In other words, ANY PaRAM Set can be used for ANY DMA channel (like QDMA Channels). +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocLogicalChannel(), EDMA3_RM_create(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_mapEdmaChannel(), and EDMA3_RM_open(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 memProtectionExists\:EDMA3_RM_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_GblConfigParams\:memProtectionExists}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 unsigned short EDMA3_RM_GblConfigParams::memProtectionExists +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIJE}{\*\bkmkend AAAAAAAIJE}Existence of memory protection feature +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 globalRegs\:EDMA3_RM_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_GblConfigParams\:globalRegs}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +void* EDMA3_RM_GblConfigParams::globalRegs +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIJF}{\*\bkmkend AAAAAAAIJF}Base address of EDMA3 CC memory mapped registers. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocLogicalChannel(), EDMA3_RM_allocResource(), EDMA3_RM_checkAndClearTcc(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_freeResource(), EDMA3_RM_getBaseAddress(), EDMA3_RM_ +getCCRegister(), EDMA3_RM_getPaRAM(), EDMA3_RM_getPaRAMPhyAddr(), EDMA3_RM_mapEdmaChannel(), EDMA3_RM_mapQdmaChannel(), EDMA3_RM_open(), EDMA3_RM_setCCRegister(), EDMA3_RM_setPaRAM(), EDMA3_RM_waitAndClearTcc(), edma3CCErrHandler(), edma3ComplHandler(), a +nd gblChngAllocContigRes(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 tcRegs\:EDMA3_RM_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_GblConfigParams\:tcRegs}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +void* EDMA3_RM_GblConfigParams::tcRegs[EDMA3_MAX_TC] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIJG}{\*\bkmkend AAAAAAAIJG}Base address of EDMA3 TCs memory mapped registers. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_getBaseAddress(), and edma3TCErrHandler(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 xferCompleteInt\:EDMA3_RM_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_GblConfigParams\:xferCompleteInt}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 unsigned int EDMA3_RM_GblConfigParams::xferCompleteInt +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIJH}{\*\bkmkend AAAAAAAIJH}EDMA3 transfer completion interrupt line (could be different for ARM and DSP) +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 ccError\:EDMA3_RM_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_GblConfigParams\:ccError}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +unsigned int EDMA3_RM_GblConfigParams::ccError +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIJI}{\*\bkmkend AAAAAAAIJI}EDMA3 CC error interrupt line (could be different for ARM and DSP) +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 tcError\:EDMA3_RM_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_GblConfigParams\:tcError}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +unsigned int EDMA3_RM_GblConfigParams::tcError[EDMA3_MAX_TC] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIJJ}{\*\bkmkend AAAAAAAIJJ}EDMA3 TCs error interrupt line (could be different for ARM and DSP) +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 evtQPri\:EDMA3_RM_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_GblConfigParams\:evtQPri}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +unsigned int EDMA3_RM_GblConfigParams::evtQPri[EDMA3_MAX_EVT_QUE] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIJK}{\*\bkmkend AAAAAAAIJK}EDMA3 TC priority setting. +\par User can program the priority of the Event Queues at a system-wide level. This means that the user can set the priority of an IO initiated by either of the TCs (Transfer Controllers) relative to IO initiat +ed by the other bus masters on the device (ARM, DSP, USB, etc) +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 evtQueueWaterMarkLvl\:EDMA3_RM_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_GblConfigParams\:evtQueueWaterMarkLvl}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 unsigned int EDMA3_RM_GblConfigParams::evtQueueWaterMarkLvl[EDMA3_MAX_EVT_QUE] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIJL}{\*\bkmkend AAAAAAAIJL}Event Queues Watermark Levels. +\par To Configure the Threshold level of number of events that can be queued up in the Event queues. EDMA3CC error register (CCERR) will indicate whether or not at any instant of time the number of events queued up in any of the event que +ues exceeds or equals the threshold/watermark value that is set in the queue watermark threshold register (QWMTHRA). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 tcDefaultBurstSize\:EDMA3_RM_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_GblConfigParams\:tcDefaultBurstSize}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 unsigned int EDMA3_RM_GblConfigParams::tcDefaultBurstSize[EDMA3_MAX_TC] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIJM}{\*\bkmkend AAAAAAAIJM}Default Burst Size (DBS) of TCs. +\par An optimally-sized command is defined by the transfer controller default burst size (DBS). Different TCs can have different DBS values. It is defined in Bytes. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 dmaChannelPaRAMMap\:EDMA3_RM_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_GblConfigParams\:dmaChannelPaRAMMap}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 unsigned int EDMA3_RM_GblConfigParams::dmaChannelPaRAMMap[EDMA3_MAX_DMA_CH] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIJN}{\*\bkmkend AAAAAAAIJN}Mapping from DMA channels to PaRAM Sets. +\par If channel mapping exists (DCHMAP registers are present), this ar +ray stores the respective PaRAM Set for each DMA channel. User can initialize each array member with a specific PaRAM Set or with EDMA3_DRV_CH_NO_PARAM_MAP. If channel mapping doesn't exist, it is of no use as the EDMA3 RM automatically uses the right PaR +AM Set for that DMA channel. Useful only if mapping exists, otherwise of no use. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocLogicalChannel(), EDMA3_RM_create(), and EDMA3_RM_open(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 dmaChannelTccMap\:EDMA3_RM_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_GblConfigParams\:dmaChannelTccMap}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 unsigned int EDMA3_RM_GblConfigParams::dmaChannelTccMap[EDMA3_MAX_DMA_CH] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIJO}{\*\bkmkend AAAAAAAIJO}Mapping from DMA channels to TCCs. +\par This array stores the respective TCC (interrupt channel) for each DMA channel. User can initialize each array member with a specific TCC or + with EDMA3_DRV_CH_NO_TCC_MAP. This specific TCC code will be returned when the transfer is completed on the mapped DMA channel. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocLogicalChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 dmaChannelHwEvtMap\:EDMA3_RM_GblConfigParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_GblConfigParams\:dmaChannelHwEvtMap}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 unsigned int EDMA3_RM_GblConfigParams::dmaChannelHwEvtMap[EDMA3_MAX_DMA_CHAN_DWRDS] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIJP}{\*\bkmkend AAAAAAAIJP}Mapping from DMA channels to Hardware Events. +\par Each bit in this array corresponds to one DMA channel and tells whether this DMA channel is tied to any p +eripheral. That is whether any peripheral can send the synch event on this DMA channel or not. 1 means the channel is tied to some peripheral; 0 means it is not. DMA channels which are tied to some peripheral are RESERVED for that peripheral only. They ar +e not allocated when user asks for 'ANY' DMA channel. All channels need not be mapped, some can be free also. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\fs22\insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +The documentation for this struct was generated from the following file: +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +edma3_rm.h}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \sect +}\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_GblErrCallbackParams Struct Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \tcl2 +{\*\bkmkstart _Toc211937566}EDMA3_RM_GblErrCallbackParams{\*\bkmkend _Toc211937566}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 +\ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_GblErrCallbackParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIIK}{\*\bkmkend AAAAAAAIIK}Global Error Callback parameters. +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Data Fields +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_GblErrCallback}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 gblerrCb}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 void * }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 gblerrData}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Global Error Callback parameters. +\par Consists of the Callback function and the data to be passed to it. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Field Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 +\ltrch\fcs0 \fs24\insrsid7370340 gblerrCb\:EDMA3_RM_GblErrCallbackParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_GblErrCallbackParams\:gblerrCb}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 +\af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_GblErrCallback EDMA3_RM_GblErrCallbackParams::gblerrCb +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIJQ}{\*\bkmkend AAAAAAAIJQ}Instance wide callback function to catch non-channel specific errors. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by edma3CCErrHandler(), and edma3TCErrHandler(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 gblerrData\:EDMA3_RM_GblErrCallbackParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_GblErrCallbackParams\:gblerrData}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 void* EDMA3_RM_GblErrCallbackParams::gblerrData +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIJR}{\*\bkmkend AAAAAAAIJR}Application data to be passed back to the Global Error callback +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by edma3CCErrHandler(), and edma3TCErrHandler(). +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\fs22\insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +The documentation for this struct was generated from the following file: +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +edma3_rm.h}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \sect +}\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_Instance Struct Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \tcl2 +{\*\bkmkstart _Toc211937567}EDMA3_RM_Instance{\*\bkmkend _Toc211937567}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 +\v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_Instance}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIIL} +{\*\bkmkend AAAAAAAIIL}EDMA3 RM Instance Specific Configuration Structure. +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Data Fields +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Param}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 initParam}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3_CCRL_ShadowRegs * }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 shadowRegs}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Obj}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 * }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 pResMgrObjHandle}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 avlblDmaChannels}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 [EDMA3_MAX_DMA_CHAN_DWRDS] +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 avlblQdmaChannels}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 [EDMA3_MAX_QDMA_CHAN_DWRDS] +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 avlblPaRAMSets}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 [EDMA3_MAX_PARAM_DWRDS] +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 avlblTccs}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 [EDMA3_MAX_TCC_DWRDS] +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 paramInitRequired}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 regModificationRequired}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +EDMA3 RM Instance Specific Configuration Structure. +\par Used to maintain information of the EDMA3 Res Mgr instances. One such storage exists for each instance of the EDMA3 Res Mgr. +\par Maximum EDMA3_MAX_RM_INSTANCES instances are allowed for each EDMA3 hardware instance, for same or different shadow regions. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Field Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 +\ltrch\fcs0 \fs24\insrsid7370340 initParam\:EDMA3_RM_Instance}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_Instance\:initParam}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 EDMA3_RM_Param EDMA3_RM_Instance::initParam +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIJS}{\*\bkmkend AAAAAAAIJS}Configuration such as region id, IsMaster, Callback function Thi +s configuration is passed to the "Open" API. For a single EDMA3 HW controller, there can be EDMA3_MAX_REGIONS different instances tied to different regions. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_checkAndClear +Tcc(), EDMA3_RM_close(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_freeResource(), EDMA3_RM_mapEdmaChannel(), EDMA3_RM_mapQdmaChannel(), EDMA3_RM_open(), EDMA3_RM_setCCRegister(), EDMA3_RM_waitAndClearTcc(), edma3CCErrHandler(), edma3ShadowRegionInit(), edm +a3TCErrHandler(), and gblChngAllocContigRes(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 shadowRegs\:EDMA3_RM_Instance}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_Instance\:shadowRegs}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_CCRL_ShadowRegs* EDMA3_RM_Instance::shadowRegs +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIJT}{\*\bkmkend AAAAAAAIJT}Pointer to appropriate Shadow Register region of CC Registers +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocLogicalChannel(), EDMA3_RM_allocResource(), EDMA3_RM_close(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_open(), EDMA3_RM_registerTccCb(), and EDMA3_RM_unregisterTccCb(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 pResMgrObjHandle\:EDMA3_RM_Instance}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_Instance\:pResMgrObjHandle}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_Obj* EDMA3_RM_Instance::pResMgrObjHandle +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIJU}{\*\bkmkend AAAAAAAIJU}Pointer to the EDMA3 RM Object (HW specific) opened by RM instance. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocLogicalChannel(), EDMA3_RM_allocResourc +e(), EDMA3_RM_checkAndClearTcc(), EDMA3_RM_close(), EDMA3_RM_freeContiguousResource(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_freeResource(), EDMA3_RM_getBaseAddress(), EDMA3_RM_getCCRegister(), EDMA3_RM_getInstanceInitCfg(), EDMA3_RM_getPaRAM(), EDMA3_R +M +_getPaRAMPhyAddr(), EDMA3_RM_mapEdmaChannel(), EDMA3_RM_mapQdmaChannel(), EDMA3_RM_open(), EDMA3_RM_registerTccCb(), EDMA3_RM_setCCRegister(), EDMA3_RM_setPaRAM(), EDMA3_RM_unregisterTccCb(), EDMA3_RM_waitAndClearTcc(), edma3ShadowRegionInit(), and gblChn +gAllocContigRes(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 avlblDmaChannels\:EDMA3_RM_Instance}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_Instance\:avlblDmaChannels}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +unsigned int EDMA3_RM_Instance::avlblDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIJV}{\*\bkmkend AAAAAAAIJV}Available DMA Channels to the RM Instance +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_close(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_freeResource(), EDMA3_RM_mapEdmaChannel(), EDMA3_RM_open(), and gblChngAllocContigRes(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 avlblQdmaChannels\:EDMA3_RM_Instance}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_Instance\:avlblQdmaChannels}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +unsigned int EDMA3_RM_Instance::avlblQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIJW}{\*\bkmkend AAAAAAAIJW}Available QDMA Channels to the RM Instance +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_close(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_freeResource(), EDMA3_RM_mapQdmaChannel(), EDMA3_RM_open(), and gblChngAllocContigRes(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 avlblPaRAMSets\:EDMA3_RM_Instance}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_Instance\:avlblPaRAMSets}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +unsigned int EDMA3_RM_Instance::avlblPaRAMSets[EDMA3_MAX_PARAM_DWRDS] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIJX}{\*\bkmkend AAAAAAAIJX}Available PaRAM Sets to the RM Instance +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_close(), EDMA3_RM_freeResource(), EDMA3_RM_mapEdmaChannel(), EDMA3_RM_mapQdmaChannel(), EDMA3_RM_open(), and gblChngAllocContigRes(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 avlblTccs\:EDMA3_RM_Instance}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_Instance\:avlblTccs}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +unsigned int EDMA3_RM_Instance::avlblTccs[EDMA3_MAX_TCC_DWRDS] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIJY}{\*\bkmkend AAAAAAAIJY}Available TCCs to the RM Instance +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_close(), EDMA3_RM_freeResource(), EDMA3_RM_open(), and gblChngAllocContigRes(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 paramInitRequired\:EDMA3_RM_Instance}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_Instance\:paramInitRequired}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +unsigned int EDMA3_RM_Instance::paramInitRequired +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIJZ}{\*\bkmkend AAAAAAAIJZ}Sometimes, PaRAM clearing is not required for some + particular RM Instances. In that case, PaRAM Sets allocated will NOT be cleared before allocating to any particular user. It is the responsibility of user to program it accordingly, without assuming anything for a specific field because the PaRAM Set mig +h +t contain junk values. Not programming it fully might result in erroneous behavior. On the other hand, RM instances can also use this variable to get the PaRAM Sets cleared before allocating them to the specific user. User can program only the selected fi +elds in this case. +\par Value '0' : PaRAM Sets will NOT be cleared during their allocation. Value '1' : PaRAM Sets will be cleared during their allocation. +\par This value can be modified using the IOCTL commands. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_Ioctl(), EDMA3_RM_open(), and gblChngAllocContigRes(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 regModificationRequired\:EDMA3_RM_Instance}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_Instance\:regModificationRequired}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 unsigned int EDMA3_RM_Instance::regModificationRequired +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIKA}{\*\bkmkend AAAAAAAIKA}Sometimes, globa +l EDMA3 registers (DCHMAP/QCHMAP) and PaRAM Sets should not be modified during EDMA3_RM_allocLogicalChannel (), for some particular RM Instances. In that case, it is the responsibility of user to program them accordingly, when needed, without assuming any +t +hing because they might contain junk values. Not programming the registers/PaRAMs fully might result in erroneous behavior. On the other hand, RM instances can also use this variable to get the global registers and PaRAM Sets minimally programmed before a +llocating them to the specific user. User can program only the remaining fields in this case. +\par Value '0' : EDMA3 registers (DCHMAP/QCHMAP) and PaRAM Sets will NOT be programmed during their allocation. Value '1' : EDMA3 registers (DCHMAP/QCHMAP) and PaRAM Sets will be programmed during their allocation. +\par This value can be modified using the IOCTL commands. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocLogicalChannel(), EDMA3_RM_allocResource(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_freeResource(), EDMA3_RM_Ioctl(), and EDMA3_RM_open(). +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\fs22\insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +The documentation for this struct was generated from the following file: +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +edma3resmgr.h}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \sect +}\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_InstanceInitConfig Struct Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \tcl2 +{\*\bkmkstart _Toc211937568}EDMA3_RM_InstanceInitConfig{\*\bkmkend _Toc211937568}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 +\ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_InstanceInitConfig}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIIM}{\*\bkmkend AAAAAAAIIM}Init-time Region Specific Configuration structure for EDMA3 RM, to provide region specific Information. +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Data Fields +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 ownPaRAMSets}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [EDMA3_MAX_PARAM_DWRDS] +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 ownDmaChannels}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 [EDMA3_MAX_DMA_CHAN_DWRDS] +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 ownQdmaChannels}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 [EDMA3_MAX_QDMA_CHAN_DWRDS] +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 ownTccs}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 [EDMA3_MAX_TCC_DWRDS] +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 resvdPaRAMSets}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 [EDMA3_MAX_PARAM_DWRDS] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Reserved PaRAM Sets. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 resvdDmaChannels}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [EDMA3_MAX_DMA_CHAN_DWRDS] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Reserved DMA channels. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 resvdQdmaChannels}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [EDMA3_MAX_QDMA_CHAN_DWRDS] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Reserved QDMA channels. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 resvdTccs}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [EDMA3_MAX_TCC_DWRDS] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 +\i\insrsid7370340 Reserved TCCs. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Init-time Region Specific Configuration structure for EDMA3 RM, to provide region specific Information. +\par This configuration structure is used to specify which EDMA3 resources are owned and reserved by the EDMA3 RM instance. This configuration structure is shadow region specific and will be provided by the user at run-time while calling EDMA3_RM_open (). + +\par Owned resources: **************** +\par EDMA3 RM Instances are tied to different shadow regions and hence different masters. Regions could be: +\par a) ARM, b) DSP, c) IMCOP (Imaging Co-processor) etc. +\par User can assign each EDMA3 resource to a shadow region using this structure. In this way, user specifi +es which resources are owned by the specific EDMA3 RM Instance. This assignment should also ensure that the same resource is not assigned to more than one shadow regions (unless desired in that way). Any assignment not following the above mentioned approa +ch may have catastrophic consequences. +\par Reserved resources: ******************* +\par During EDMA3 RM initialization, user can reserve some of the EDMA3 resources for future use, by specifying which resources to reserve in the configuration data structure. These ( +critical) resources are reserved in advance so that they should not be allocated to someone else and thus could be used in future for some specific purpose. +\par User can request different EDMA3 resources using two methods: a) By passing the resource type and the actual resource id, b) By passing the resource type and ANY as resource id +\par For e.g. to request DMA channel 31, user will pass 31 as the resource id. But to request ANY available DMA channel (mainly used for memory-to-memory data transfer operations), user will pass EDMA3_DRV_DMA_CHANNEL_ANY as the resource id. +\par During initialization, user may have reserved some of the DMA channels for some specific purpose (mainly for peripherals using EDMA). These reserved DMA channels then will not be returned when user requests ANY as the resource id. +\par Same logic applies for QDMA channels and TCCs. +\par For PaRAM Set, there is one difference. If the DMA channels are one-to-one tied to their respective PaRAM Sets (i.e. user cannot 'choose' the PaRAM Set for a particular DMA ch +annel), EDMA3 RM automatically reserves all those PaRAM Sets which are tied to the DMA channels. Then those PaRAM Sets would not be returned when user requests for ANY PaRAM Set (specifically for linking purpose). This is done in order to avoid allocating + the PaRAM Set, tied to a particular DMA channel, for linking purpose. If this constraint is not there, that DMA channel thus could not be used at all, because of the unavailability of the desired PaRAM Set. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Field Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 +\ltrch\fcs0 \fs24\insrsid7370340 ownPaRAMSets\:EDMA3_RM_InstanceInitConfig}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_InstanceInitConfig\:ownPaRAMSets}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 +\af1 \ltrch\fcs0 \insrsid7370340 unsigned int EDMA3_RM_InstanceInitConfig::ownPaRAMSets[EDMA3_MAX_PARAM_DWRDS] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIKB}{\*\bkmkend AAAAAAAIKB}PaRAM Sets owned by the EDMA3 RM Instance. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_freeResource(), EDMA3_RM_mapEdmaChannel(), EDMA3_RM_mapQdmaChannel(), and EDMA3_RM_open(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 ownDmaChannels\:EDMA3_RM_InstanceInitConfig}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_InstanceInitConfig\:ownDmaChannels}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 unsigned int EDMA3_RM_InstanceInitConfig::ownDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIKC}{\*\bkmkend AAAAAAAIKC}DMA Channels owned by the EDMA3 RM Instance. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_freeResource(), EDMA3_RM_mapEdmaChannel(), EDMA3_RM_open(), edma3CCErrHandler(), and edma3ShadowRegionInit(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 ownQdmaChannels\:EDMA3_RM_InstanceInitConfig}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_InstanceInitConfig\:ownQdmaChannels}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 unsigned int EDMA3_RM_InstanceInitConfig::ownQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIKD}{\*\bkmkend AAAAAAAIKD}QDMA Channels owned by the EDMA3 RM Instance. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_freeResource(), EDMA3_RM_mapQdmaChannel(), EDMA3_RM_open(), edma3CCErrHandler(), and edma3ShadowRegionInit(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 ownTccs\:EDMA3_RM_InstanceInitConfig}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_InstanceInitConfig\:ownTccs}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +unsigned int EDMA3_RM_InstanceInitConfig::ownTccs[EDMA3_MAX_TCC_DWRDS] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIKE}{\*\bkmkend AAAAAAAIKE}TCCs owned by the EDMA3 RM Instance. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_freeResource(), EDMA3_RM_open(), and edma3ShadowRegionInit(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 resvdPaRAMSets\:EDMA3_RM_InstanceInitConfig}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_InstanceInitConfig\:resvdPaRAMSets}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 unsigned int EDMA3_RM_InstanceInitConfig::resvdPaRAMSets[EDMA3_MAX_PARAM_DWRDS] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIKF}{\*\bkmkend AAAAAAAIKF}Reserved PaRAM Sets. +\par PaRAM Sets reserved during initialization for future use. These will not be given when user requests for ANY available PaRAM Set using 'EDMA3_RM_PARAM_ANY' as resource/channel id. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), and EDMA3_RM_open(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 resvdDmaChannels\:EDMA3_RM_InstanceInitConfig}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_InstanceInitConfig\:resvdDmaChannels}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 unsigned int EDMA3_RM_InstanceInitConfig::resvdDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIKG}{\*\bkmkend AAAAAAAIKG}Reserved DMA channels. +\par DMA channels reserved during initialization for future use. These will not be given when user requests for ANY available DMA channel using 'EDMA3_RM_DMA_CHANNEL_ANY' as resource/channel id. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocContiguousResource(), and EDMA3_RM_allocResource(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 resvdQdmaChannels\:EDMA3_RM_InstanceInitConfig}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_InstanceInitConfig\:resvdQdmaChannels}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 unsigned int EDMA3_RM_InstanceInitConfig::resvdQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIKH}{\*\bkmkend AAAAAAAIKH}Reserved QDMA channels. +\par QDMA channels reserved during initialization for future use. These will not be given when user requests for ANY available QDMA channel using 'EDMA3_RM_QDMA_CHANNEL_ANY' as resource/channel id. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocContiguousResource(), and EDMA3_RM_allocResource(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 resvdTccs\:EDMA3_RM_InstanceInitConfig}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_InstanceInitConfig\:resvdTccs}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +unsigned int EDMA3_RM_InstanceInitConfig::resvdTccs[EDMA3_MAX_TCC_DWRDS] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIKI}{\*\bkmkend AAAAAAAIKI}Reserved TCCs. +\par TCCs reserved during initialization for future use. These will not be given when user requests for ANY available TCC using 'EDMA3_RM_TCC_ANY' as resource/channel id. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocContiguousResource(), and EDMA3_RM_allocResource(). +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\fs22\insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +The documentation for this struct was generated from the following file: +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +edma3_rm.h}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \sect +}\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_MiscParam Struct Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \tcl2 +{\*\bkmkstart _Toc211937569}EDMA3_RM_MiscParam{\*\bkmkend _Toc211937569}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 +\v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_MiscParam}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIIN} +{\*\bkmkend AAAAAAAIIN}Used to specify the miscellaneous options during Resource Manager Initialization. +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Data Fields +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +unsigned short }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 isSlave}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 unsigned short }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 param}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Used to specify the miscellaneous options during Resource Manager Initialization. +\par This configuration structure is used to specify some misc options while creating the RM Object. New options may also be added into this structure in future. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Field Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 +\ltrch\fcs0 \fs24\insrsid7370340 isSlave\:EDMA3_RM_MiscParam}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_MiscParam\:isSlave}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 unsigned short EDMA3_RM_MiscParam::isSlave +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIKJ}{\*\bkmkend AAAAAAAIKJ}In a multi-master system (for e.g. ARM + DSP), this option is used to distinguish between Master and Slave. Only the Master is a +llowed to program the global EDMA3 registers (like Queue priority, Queue water- mark level, error registers etc). +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_create(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 param\:EDMA3_RM_MiscParam}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_MiscParam\:param}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +unsigned short EDMA3_RM_MiscParam::param +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIKK}{\*\bkmkend AAAAAAAIKK}For future use +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\fs22\insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +The documentation for this struct was generated from the following file: +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +edma3_rm.h}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \sect +}\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_Obj Struct Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \tcl2 +{\*\bkmkstart _Toc211937570}EDMA3_RM_Obj{\*\bkmkend _Toc211937570}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 +\v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_Obj}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIIO} +{\*\bkmkend AAAAAAAIIO}EDMA3 Hardware Instance Configuration Structure. +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Data Fields +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 phyCtrllerInstId}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ObjState}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 state}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 numOpens}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_GblConfigParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid7370340 gblCfgParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 +\i\insrsid7370340 Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 EDMA3 Hardware +Instance Configuration Structure. +\par Used to maintain information of the EDMA3 HW configuration. One such storage exists for each instance of the EDMA 3 HW. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Field Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 +\ltrch\fcs0 \fs24\insrsid7370340 phyCtrllerInstId\:EDMA3_RM_Obj}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_Obj\:phyCtrllerInstId}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 unsigned int EDMA3_RM_Obj::phyCtrllerInstId +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIKL}{\*\bkmkend AAAAAAAIKL}HW Instance Id of the EDMA3 Controller +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocLogicalChannel(), EDMA3_RM_close(), EDMA3_RM_create(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_getInstanceInitCfg(), EDMA3_RM_getPaRAM(), EDMA3_RM_getP +aRAMPhyAddr(), EDMA3_RM_setPaRAM(), edma3CCErrHandler(), edma3ShadowRegionInit(), and edma3TCErrHandler(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 state\:EDMA3_RM_Obj}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_Obj\:state}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_ObjState EDMA3_RM_Obj::state + +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIKM}{\*\bkmkend AAAAAAAIKM}State information of the Resource Manager object +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_close(), EDMA3_RM_create(), EDMA3_RM_delete(), and EDMA3_RM_open(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 numOpens\:EDMA3_RM_Obj}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_Obj\:numOpens}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +unsigned int EDMA3_RM_Obj::numOpens +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIKN}{\*\bkmkend AAAAAAAIKN}Number of active opens of RM Instances +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_close(), EDMA3_RM_create(), EDMA3_RM_open(), edma3CCErrHandler(), and edma3TCErrHandler(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 gblCfgParams\:EDMA3_RM_Obj}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_Obj\:gblCfgParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_GblConfigParams EDMA3_RM_Obj::gblCfgParams +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIKO}{\*\bkmkend AAAAAAAIKO}Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. +\par This configuration will can be provided by the user at run-time, while calling }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_create()}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 . +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocLogicalChannel(), EDMA3_RM_allocResource(), EDMA3_RM_checkAndC +learTcc(), EDMA3_RM_close(), EDMA3_RM_create(), EDMA3_RM_freeContiguousResource(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_freeResource(), EDMA3_RM_getBaseAddress(), EDMA3_RM_getCCRegister(), EDMA3_RM_getPaRAM(), EDMA3_RM_getPaRAMPhyAddr(), EDMA3_RM_mapEd +m +aChannel(), EDMA3_RM_mapQdmaChannel(), EDMA3_RM_open(), EDMA3_RM_registerTccCb(), EDMA3_RM_setCCRegister(), EDMA3_RM_setPaRAM(), EDMA3_RM_unregisterTccCb(), EDMA3_RM_waitAndClearTcc(), edma3CCErrHandler(), edma3ComplHandler(), edma3TCErrHandler(), and gbl +ChngAllocContigRes(). +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\fs22\insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +The documentation for this struct was generated from the following file: +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +edma3resmgr.h}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \sect +}\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_Param Struct Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \tcl2 +{\*\bkmkstart _Toc211937571}EDMA3_RM_Param{\*\bkmkend _Toc211937571}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 +\v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_Param}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIIP} +{\*\bkmkend AAAAAAAIIP}Used to Initialize the Resource Manager Instance. +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Data Fields +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_RegionId}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 regionId}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 unsigned short }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 isMaster}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_InstanceInitConfig}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 * }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid7370340 rmInstInitConfig}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 void * }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 rmSemHandle}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 unsigned short }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 regionInitEnable}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_GblErrCallbackParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid7370340 gblerrCbParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Used to Initialize the Resource Manager Instance. +\par This configuration structure is used to initialize the EDMA3 RM Instance. This configuration information is passed while opening the RM instance. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Field Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 +\ltrch\fcs0 \fs24\insrsid7370340 regionId\:EDMA3_RM_Param}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_Param\:regionId}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 EDMA3_RM_RegionId EDMA3_RM_Param::regionId +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIKP}{\*\bkmkend AAAAAAAIKP}Shadow Region Identification +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_checkAndClearTcc(), EDMA3_RM_freeResource(), EDMA3_RM_open(), EDMA3_RM_waitAndClearTcc(), edma +3CCErrHandler(), edma3ShadowRegionInit(), edma3TCErrHandler(), and gblChngAllocContigRes(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 isMaster\:EDMA3_RM_Param}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_Param\:isMaster}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +unsigned short EDMA3_RM_Param::isMaster +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIKQ}{\*\bkmkend AAAAAAAIKQ}It tells whether the EDMA3 RM instance is Master or not. Only the shadow region associated with this master instance will receive the EDMA3 interrupts (if enabled). +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_close(), and EDMA3_RM_open(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 rmInstInitConfig\:EDMA3_RM_Param}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_Param\:rmInstInitConfig}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_InstanceInitConfig* EDMA3_RM_Param::rmInstInitConfig +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIKR}{\*\bkmkend AAAAAAAIKR} +EDMA3 resources related shadow region specific information. Which all EDMA3 resources are owned and reserved by this particular instance are told in this configuration structure. User can also pass this structure as NUL +L. In that case, default static configuration would be taken from the platform specific configuration files (part of the Resource Manager), if available. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_freeResource(), EDMA3_RM_mapEdmaChannel(), EDMA3_RM_mapQdmaChannel(), EDMA3_RM_open(), edma3CCErrHandler(), and edma3ShadowRegionInit(). + +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 rmSemHandle\:EDMA3_RM_Param}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_Param\:rmSemHandle}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +void* EDMA3_RM_Param::rmSemHandle +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIKS}{\*\bkmkend AAAAAAAIKS}EDMA3 RM Instance specific semaphore handle. Used to share resources (DMA/QDMA channels, PaRAM Sets, TCCs etc) among different users. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_open(), and EDMA3_RM_setCCRegister(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 regionInitEnable\:EDMA3_RM_Param}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_Param\:regionInitEnable}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +unsigned short EDMA3_RM_Param::regionInitEnable +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIKT}{\*\bkmkend AAAAAAAIKT}Whether initialization of Region Specific Registers is required or not? +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_open(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 gblerrCbParams\:EDMA3_RM_Param}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_Param\:gblerrCbParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_GblErrCallbackParams EDMA3_RM_Param::gblerrCbParams +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIKU}{\*\bkmkend AAAAAAAIKU}Instance wide Global Error callback parameters +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by edma3CCErrHandler(), and edma3TCErrHandler(). +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\fs22\insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +The documentation for this struct was generated from the following file: +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +edma3_rm.h}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \sect +}\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_ParamentryRegs Struct Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \tcl2 +{\*\bkmkstart _Toc211937572}EDMA3_RM_ParamentryRegs{\*\bkmkend _Toc211937572}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 +\v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_ParamentryRegs}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIIQ} +{\*\bkmkend AAAAAAAIIQ}EDMA3 PaRAM Set. +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Data Fields +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +volatile unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 OPT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 volatile unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 SRC}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 {\*\bkmkstart AAAAAAAIKV}{\*\bkmkend AAAAAAAIKV} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Starting byte address of Source For FIFO mode, srcAddr must be a 256-bit aligned address. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +volatile unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 A_B_CNT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 volatile unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 DST}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 {\*\bkmkstart AAAAAAAIKW}{\*\bkmkend AAAAAAAIKW} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Starting byte address of destination For FIFO mode, destAddr must be a 256-bit aligned address. i.e. 5 LSBs should be 0. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +volatile unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 SRC_DST_BIDX}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 volatile unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 LINK_BCNTRLD}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Address for linking (AutoReloading of a PaRAM Set) (16 bits) and Reload value of the numArrInFrame (BCNT) (16 bits). +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +volatile unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 SRC_DST_CIDX}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIKX}{\*\bkmkend AAAAAAAIKX} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Index between consecutive frames of a Source Block (SRCCIDX) (16 bits) and Index between consecutive frames of a Dest Block (DSTCIDX) (16 bits). +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +volatile unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 CCNT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIKY}{\*\bkmkend AAAAAAAIKY} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 +\i\insrsid7370340 Number of Frames in a block (CCNT) (16 bits). +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +EDMA3 PaRAM Set. +\par This is a mapping of the EDMA3 PaRAM set provided to the user for ease of modification of the individual PaRAM words. +\par It could be used by the advanced users to program the PaRAM Set directly, without using any API. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Field Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 +\ltrch\fcs0 \fs24\insrsid7370340 OPT\:EDMA3_RM_ParamentryRegs}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_ParamentryRegs\:OPT}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 volatile unsigned int EDMA3_RM_ParamentryRegs::OPT +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIKZ}{\*\bkmkend AAAAAAAIKZ}OPT field of PaRAM Set +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 A_B_CNT\:EDMA3_RM_ParamentryRegs}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_ParamentryRegs\:A_B_CNT}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +volatile unsigned int EDMA3_RM_ParamentryRegs::A_B_CNT +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAILA}{\*\bkmkend AAAAAAAILA}Number of bytes in each Array (ACNT) (16 bits) and Number of Arrays in each Frame (BCNT) (16 bits). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 SRC_DST_BIDX\:EDMA3_RM_ParamentryRegs}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_ParamentryRegs\:SRC_DST_BIDX}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +volatile unsigned int EDMA3_RM_ParamentryRegs::SRC_DST_BIDX +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAILB}{\*\bkmkend AAAAAAAILB}Index between consec. arrays of a Source Frame (SRCBIDX) (16 bits) and Index between consec. arrays of a Destination Frame (DSTBIDX) (16 bits). +\par If SAM is set to 1 (via channelOptions) then srcInterArrIndex should be an even multiple of 32 bytes. +\par If DAM is set to 1 (via channelOptions) then destInterArrIndex should be an even multiple of 32 bytes +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 LINK_BCNTRLD\:EDMA3_RM_ParamentryRegs}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_ParamentryRegs\:LINK_BCNTRLD}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +volatile unsigned int EDMA3_RM_ParamentryRegs::LINK_BCNTRLD +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAILC}{\*\bkmkend AAAAAAAILC}Address for linking (AutoReloading of a PaRAM Set) (16 bits) and Reload value of the numArrInFrame (BCNT) (16 bits). +\par Link field must point to a valid aligned 32-byte PaRAM set A value of 0xFFFF means no linking. +\par B count reload field is relevant only for A-sync transfers. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\fs22\insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +The documentation for this struct was generated from the following file: +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +edma3_rm.h}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \sect +}\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_PaRAMRegs Struct Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \tcl2 +{\*\bkmkstart _Toc211937573}EDMA3_RM_PaRAMRegs{\*\bkmkend _Toc211937573}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 +\v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_PaRAMRegs}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIIR} +{\*\bkmkend AAAAAAAIIR}EDMA3 PaRAM Set in User Configurable format. +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Data Fields +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +volatile unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 opt}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 volatile unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 srcAddr}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAILD}{\*\bkmkend AAAAAAAILD} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Starting byte address of Source For FIFO mode, srcAddr must be a 256-bit aligned address. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +volatile unsigned short }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 aCnt}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAILE}{\*\bkmkend AAAAAAAILE} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Number of bytes in each Array (ACNT). +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +volatile unsigned short }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 bCnt}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAILF}{\*\bkmkend AAAAAAAILF} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Number of Arrays in each Frame (BCNT). +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +volatile unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 destAddr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAILG}{\*\bkmkend AAAAAAAILG} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Starting byte address of destination For FIFO mode, destAddr must be a 256-bit aligned address. i.e. 5 LSBs should be 0. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +volatile short }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 srcBIdx}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAILH}{\*\bkmkend AAAAAAAILH} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Index between consec. arrays of a Source Frame (SRCBIDX) If SAM is set to 1 (via channelOptions) then srcInterArrIndex should be an even multiple of 32 bytes. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +volatile short }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 destBIdx}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAILI}{\*\bkmkend AAAAAAAILI} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Index between consec. arrays of a Destination Frame (DSTBIDX) If DAM is set to 1 (via channelOptions) then destInterArrIndex should be an even multiple of 32 bytes. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +volatile unsigned short }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 linkAddr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAILJ}{\*\bkmkend AAAAAAAILJ} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Address for linking (AutoReloading of a PaRAM Set) This must point to a valid aligned 32-byte PaRAM set A value of 0xFFFF means no linking Linking is especially useful for use with ping-pong buffers and c +ircular buffers. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +volatile unsigned short }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 bCntReload}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAILK}{\*\bkmkend AAAAAAAILK} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Reload value of the numArrInFrame (BCNT) Relevant only for A-sync transfers. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +volatile short }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 srcCIdx}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAILL}{\*\bkmkend AAAAAAAILL} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Index between consecutive frames of a Source Block (SRCCIDX). +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +volatile short }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 destCIdx}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAILM}{\*\bkmkend AAAAAAAILM} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Index between consecutive frames of a Dest Block (DSTCIDX). +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +volatile unsigned short }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 cCnt}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAILN}{\*\bkmkend AAAAAAAILN} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 +\i\insrsid7370340 Number of Frames in a block (CCNT). +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +EDMA3 PaRAM Set in User Configurable format. +\par This is a mapping of the EDMA3 PaRAM set provided to the user for ease of modification of the individual fields. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Field Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 +\ltrch\fcs0 \fs24\insrsid7370340 opt\:EDMA3_RM_PaRAMRegs}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 +\ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_PaRAMRegs\:opt}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +volatile unsigned int EDMA3_RM_PaRAMRegs::opt +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAILO}{\*\bkmkend AAAAAAAILO}OPT field of PaRAM Set +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\fs22\insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +The documentation for this struct was generated from the following file: +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +edma3_rm.h}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \sect +}\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_ResDesc Struct Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \tcl2 +{\*\bkmkstart _Toc211937574}EDMA3_RM_ResDesc{\*\bkmkend _Toc211937574}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 +\v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_ResDesc}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIIS} +{\*\bkmkend AAAAAAAIIS}Handle to a Resource. +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Data Fields +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 resId}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResType}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 type}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Handle to a Resource. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Field Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 +\ltrch\fcs0 \fs24\insrsid7370340 resId\:EDMA3_RM_ResDesc}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 +\ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_ResDesc\:resId}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +unsigned int EDMA3_RM_ResDesc::resId +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAILP}{\*\bkmkend AAAAAAAILP}Resource Id Range of resId values : As an example, for resource Type = EDMA3_RM_RES_DMA_CHANNEL, resId can take values from 0 to EDMA3_MAX_DMA_CH Or resId can take the value EDMA3_RM_RES_ANY. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocLogicalChannel(), EDMA3_RM_allocResource(), EDMA3_RM_freeContiguousResource(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_freeResource(), EDMA3_RM_get +PaRAM(), EDMA3_RM_getPaRAMPhyAddr(), EDMA3_RM_registerTccCb(), EDMA3_RM_setPaRAM(), EDMA3_RM_unregisterTccCb(), and gblChngAllocContigRes(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 type\:EDMA3_RM_ResDesc}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_ResDesc\:type}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_ResType EDMA3_RM_ResDesc::type +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAILQ}{\*\bkmkend AAAAAAAILQ}Resource Type +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Refe +renced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocLogicalChannel(), EDMA3_RM_allocResource(), EDMA3_RM_freeContiguousResource(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_freeResource(), EDMA3_RM_getPaRAM(), EDMA3_RM_getPaRAMPhyAddr(), EDMA3_RM_re +gisterTccCb(), EDMA3_RM_setPaRAM(), EDMA3_RM_unregisterTccCb(), and gblChngAllocContigRes(). +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\fs22\insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +The documentation for this struct was generated from the following file: +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +edma3_rm.h}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \sect +}\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_TccCallbackParams Struct Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \tcl2 +{\*\bkmkstart _Toc211937575}EDMA3_RM_TccCallbackParams{\*\bkmkend _Toc211937575}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 +\ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_TccCallbackParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIIT}{\*\bkmkend AAAAAAAIIT}TCC Callback - Caters to channel specific status reporting. +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Data Fields +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_TccCallback}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 tccCb}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 void * }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 cbData}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +TCC Callback - Caters to channel specific status reporting. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Field Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 +\ltrch\fcs0 \fs24\insrsid7370340 tccCb\:EDMA3_RM_TccCallbackParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_TccCallbackParams\:tccCb}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 EDMA3_RM_TccCallback EDMA3_RM_TccCallbackParams::tccCb +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAILR}{\*\bkmkend AAAAAAAILR}Callback function +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_registerTccCb(), EDMA3_RM_unregisterTccCb(), edma3CCErrHandler(), and edma3ComplHandler(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 cbData\:EDMA3_RM_TccCallbackParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_TccCallbackParams\:cbData}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +void* EDMA3_RM_TccCallbackParams::cbData +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAILS}{\*\bkmkend AAAAAAAILS}Callback data, passed to the Callback function +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_registerTccCb(), and EDMA3_RM_unregisterTccCb(). +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\fs22\insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +The documentation for this struct was generated from the following file: +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +edma3resmgr.h}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \sect +}\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s1\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs36\alang1025 \ltrch\fcs0 +\b\f1\fs36\lang1033\langfe1033\kerning36\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 File Documentation}{\pard\plain \ltrpar +\s1\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs36\alang1025 \ltrch\fcs0 \b\v\f1\fs36\lang1033\langfe1033\kerning36\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 {\*\bkmkstart _Toc211937576}File Documentation{\*\bkmkend _Toc211937576}}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h File Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \tcl2 +{\*\bkmkstart _Toc211937577}edma3_common.h{\*\bkmkend _Toc211937577}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 +\v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAAAA} +{\*\bkmkend AAAAAAAAAA}EDMA3 Common header provides generic defines/typedefs and debugging info. +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Defines +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define } +{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_DEBUG}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DRV_DEBUG}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 TRUE}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ (1u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 FALSE}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ (0u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 NULL}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ 0u +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_SOK}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ (0u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DRV_SOK}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ (0u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_OSSEM_NO_TIMEOUT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (-1) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_MAX_EDMA3_INSTANCES}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (1u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_MAX_DMA_CH}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ (64u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_MAX_QDMA_CH}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ (8u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_MAX_PARAM_SETS}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (512u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_MAX_LOGICAL_CH}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_MAX_TCC}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ (64u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_MAX_EVT_QUE}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ (8u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_MAX_TC}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ (8u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_MAX_REGIONS}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ (8u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_MAX_DMA_CHAN_DWRDS}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (EDMA3_MAX_DMA_CH / 32u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_MAX_QDMA_CHAN_DWRDS}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (1u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_MAX_PARAM_DWRDS}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (EDMA3_MAX_PARAM_SETS / 32u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_MAX_TCC_DWRDS}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ (EDMA3_MAX_TCC / 32u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_OS_PROTECT_INTERRUPT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ 1 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_OS_PROTECT_SCHEDULER}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ 2 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ 3 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ 4 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ 5 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Typedefs +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +typedef int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 typedef int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DRV_Result}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 typedef void * }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 typedef void * }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DRV_Handle}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 typedef void * }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_OS_Sem_Handle}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Functions +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 void }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 lisrEdma3ComplHandler0}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (unsigned int arg) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 void }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 lisrEdma3CCErrHandler0}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 (unsigned int arg) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 void }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 lisrEdma3TC0ErrHandler0}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 (unsigned int arg) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 void }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 lisrEdma3TC1ErrHandler0}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 (unsigned int arg) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 void }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 lisrEdma3TC2ErrHandler0}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 (unsigned int arg) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 void }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 lisrEdma3TC3ErrHandler0}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 (unsigned int arg) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 void }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 lisrEdma3TC4ErrHandler0}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 (unsigned int arg) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 void }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 lisrEdma3TC5ErrHandler0}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 (unsigned int arg) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 void }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 lisrEdma3TC6ErrHandler0}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 (unsigned int arg) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 void }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 lisrEdma3TC7ErrHandler0}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 (unsigned int arg) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 void }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 edma3OsProtectEntry}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 (int level, unsigned int *intState) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 EDMA3 OS Protect Entry. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 void }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 edma3OsProtectExit}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (int level, unsigned int intState) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 EDMA3 OS Protect Exit. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_DRV_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 edma3OsSemTake}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_OS_Sem_Handle}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hSem, int mSecTimeout) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 EDMA3 OS Semaphore Take. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_DRV_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 edma3OsSemGive}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_OS_Sem_Handle}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hSem) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 +\i\insrsid7370340 EDMA3 OS Semaphore Give. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +EDMA3 Common header provides generic defines/typedefs and debugging info. +\par This file contains the generic defines and typedefs and the debugging info that are common across interfaces of EDMA Res Mgr and EDMA Driver and visible to the application. +\par (C) Copyright 2006, Texas Instruments, Inc +\par }\pard\plain \ltrpar\s5\qj \li0\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Version: +\par }\pard\plain \ltrpar\s43\ql \li360\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +0.2.0 Anuj Aggarwal - Created 0.2.1 Anuj Aggarwal - Modified it for more run time configuration. +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Made EDMA3 package OS independent. 0.2.2 Anuj Aggarwal - Critical section handling code modification. Uses semaphore and interrupts disabling mechanism for resource sharing. 0.3.0 Anuj Aggarwal - Renamed EDMA3_DVR to EDMA3_DRV +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 IPR bit clearing in RM ISR issue fixed. +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Sample application made generic 0.3.1 Anuj Aggarwal - Added DMA/QDMA Channel to TCC mapping, to fix QDMA missed event issue. 0.3.2 Anuj Aggarwal - Added support for POLL mode +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Added a new API to modify the CC Register. 1.0.0 Anuj Aggarwal - Fixed resource allocation related bugs. 1.0.0.1 Anuj Aggarwal - Fixed spurious missed event generation related bug. 1.0.0.2 Anuj Aggarwal - Made the EDMA3 pack +age RTSC compliant. 1.0.0.3 Anuj Aggarwal - Changed the directory structure as per RTSC standard. 1.01.00.01 Anuj Aggarwal - a) Added new APIs to allocate logical channels b) Created EDMA3 config files for different platforms c) Misc changes 1.02.00.01 An +u +j Aggarwal - a) Added DM6467 support b) Fixed some MRs 1.03.00.01 Anuj Aggarwal - a) Added non-RTSC PJT files b) IOCTL Interface added. c) Fixed some MRs. 1.04 Anuj Aggarwal - a) Added new IOCTLs and APIs. b) Number of maximum Resource Manager Instances i +s configurable. c) Header files modified to have extern "C" declarations. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Define Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_DRV_DEBUG\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 edma3_common.h\:EDMA3_DRV_DEBUG}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_DRV_DEBUG +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAAAB}{\*\bkmkend AAAAAAAAAB}define to enable/disable EDMA3 Driver debug messages +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_DRV_SOK\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:EDMA3_DRV_SOK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 #define EDMA3_DRV_SOK\~ + (0u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAAAC}{\*\bkmkend AAAAAAAAAC}EDMA3 Driver Result OK +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_MAX_DMA_CH\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:EDMA3_MAX_DMA_CH}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 #define EDMA3_MAX_DMA_CH +\~ (64u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAAAD}{\*\bkmkend AAAAAAAAAD}Maximum DMA channels supported by the EDMA3 Controller +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by allocAnyContigRes(), and EDMA3_RM_freeLogicalChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_MAX_DMA_CHAN_DWRDS\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:EDMA3_MAX_DMA_CHAN_DWRDS}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_MAX_DMA_CHAN_DWRDS\~ (EDMA3_MAX_DMA_CH / 32u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAAAE}{\*\bkmkend AAAAAAAAAE}Maximum Words (4-bytes region) required for the book-keeping information specific to the maximum possible DMA channels. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_MAX_EDMA3_INSTANCES\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:EDMA3_MAX_EDMA3_INSTANCES}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_MAX_EDMA3_INSTANCES\~ (1u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAAAF}{\*\bkmkend AAAAAAAAAF}Defines used t +o support the maximum resources supported by the EDMA3 controller. These are used to allocate the maximum memory for different data structures of the EDMA3 Driver and Resource Manager. Maximum EDMA3 Controllers on the SoC +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by EDMA3_RM_create(), EDMA3_RM_delete(), EDMA3_RM_getGblConfigParams(), EDMA3_RM_open(), and edma3GlobalRegionInit(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_MAX_EVT_QUE\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:EDMA3_MAX_EVT_QUE}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_MAX_EVT_QUE\~ (8u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAAAG}{\*\bkmkend AAAAAAAAAG}Maximum Event Queues supported by the EDMA3 Controller +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_MAX_LOGICAL_CH\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:EDMA3_MAX_LOGICAL_CH}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_MAX_LOGICAL_CH +\par }\pard\plain \ltrpar\s23\ql \li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \shading1000\cbpat8 \rtlch\fcs1 \af2\afs16\alang1025 \ltrch\fcs0 +\f2\fs16\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af2 \ltrch\fcs0 \b\insrsid7370340 {\*\bkmkstart AAAAAAAAAH}{\*\bkmkend AAAAAAAAAH}Value:}{\rtlch\fcs1 \af2 \ltrch\fcs0 \insrsid7370340 (EDMA3_MAX_DMA_CH + \\ +\par EDMA3_MAX_PARAM_SETS + \\ +\par EDMA3_MAX_QDMA_CH) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Maximum Logical channels supported by the EDMA3 Package +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by EDMA3_RM_create(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_MAX_PARAM_DWRDS\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:EDMA3_MAX_PARAM_DWRDS}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_MAX_PARAM_DWRDS\~ (EDMA3_MAX_PARAM_SETS / 32u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAAAI}{\*\bkmkend AAAAAAAAAI}Maximum Words (4-bytes region) required for the book-keeping information specific to the maximum possible PaRAM Sets. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_MAX_PARAM_SETS\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:EDMA3_MAX_PARAM_SETS}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_MAX_PARAM_SETS\~ (512u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAAAJ}{\*\bkmkend AAAAAAAAAJ}Maximum PaRAM Sets supported by the EDMA3 Controller +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by EDMA3_RM_allocLogicalChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_MAX_QDMA_CH\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:EDMA3_MAX_QDMA_CH}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_MAX_QDMA_CH\~ (8u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAAAK}{\*\bkmkend AAAAAAAAAK}Maximum QDMA channels supported by the EDMA3 Controller +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by allocAnyContigRes(), EDMA3_RM_allocLogicalChannel(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_getPaRAM(), EDMA3_RM_getPaRAMPhyAddr(), and EDMA3_RM_setPaRAM(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_MAX_QDMA_CHAN_DWRDS\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:EDMA3_MAX_QDMA_CHAN_DWRDS}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_MAX_QDMA_CHAN_DWRDS\~ (1u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAAAL}{\*\bkmkend AAAAAAAAAL}Maximum Words (4-bytes region) required for the book-keeping information specific to the maximum possible QDMA channels. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_MAX_REGIONS\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:EDMA3_MAX_REGIONS}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_MAX_REGIONS\~ (8u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAAAM}{\*\bkmkend AAAAAAAAAM}Maximum Shadow Regions supported by the EDMA3 Controller +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by EDMA3_RM_close(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_MAX_TC\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:EDMA3_MAX_TC}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 #define EDMA3_MAX_TC\~ (8u) + +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAAAN}{\*\bkmkend AAAAAAAAAN}Maximum Transfer Controllers supported by the EDMA3 Controller +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_MAX_TCC\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:EDMA3_MAX_TCC}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 #define EDMA3_MAX_TCC\~ + (64u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAAAO}{\*\bkmkend AAAAAAAAAO}Maximum TCCs (Interrupt Channels) supported by the EDMA3 Controller +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by allocAnyContigRes(), EDMA3_RM_create(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_unregisterTccCb(), and edma3CCErrHandler(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_MAX_TCC_DWRDS\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:EDMA3_MAX_TCC_DWRDS}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_MAX_TCC_DWRDS\~ (EDMA3_MAX_TCC / 32u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAAAP}{\*\bkmkend AAAAAAAAAP}Maximum Words (4-bytes region) required for the book-keeping information specific to the maximum possible TCCs. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_OS_PROTECT_INTERRUPT\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:EDMA3_OS_PROTECT_INTERRUPT}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_OS_PROTECT_INTERRUPT\~ 1 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAAAQ}{\*\bkmkend AAAAAAAAAQ}Defines for the level of OS protection needed when calling }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 edma3OsProtectEntry()}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 Protection from All Interrupts required +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by EDMA3_RM_close(), EDMA3_RM_freeResource(), EDMA3_RM_open(), and edma3ShadowRegionInit(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR\~ 4 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAAAR}{\*\bkmkend AAAAAAAAAR}Protection from EDMA3 CC Error Interrupt required +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by edma3CCErrHandler(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR\~ 5 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAAAS}{\*\bkmkend AAAAAAAAAS}Protection from EDMA3 TC Error Interrupt required +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by edma3TCErrHandler(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 #define EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION\~ 3 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAAAT}{\*\bkmkend AAAAAAAAAT}Protection from EDMA3 Transfer Completion Interrupt required +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by edma3ComplHandler(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_OS_PROTECT_SCHEDULER\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:EDMA3_OS_PROTECT_SCHEDULER}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_OS_PROTECT_SCHEDULER\~ 2 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAAAU}{\*\bkmkend AAAAAAAAAU}Protection from scheduling required +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_OSSEM_NO_TIMEOUT\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:EDMA3_OSSEM_NO_TIMEOUT}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_OSSEM_NO_TIMEOUT\~ (-1) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAAAV}{\*\bkmkend AAAAAAAAAV}Blocking call without timeout +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), and EDMA3_RM_setCCRegister(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_DEBUG\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:EDMA3_RM_DEBUG}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 #define EDMA3_RM_DEBUG + +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAAAW}{\*\bkmkend AAAAAAAAAW}define to enable/disable Resource Manager debug messages +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_SOK\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:EDMA3_RM_SOK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 #define EDMA3_RM_SOK\~ (0u) + +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAAAX}{\*\bkmkend AAAAAAAAAX}EDMA3 Resource Manager Result OK +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by allocAnyContigRes(), EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocLogicalChannel(), EDMA3_RM_allocResource(), EDMA3 +_RM_checkAndClearTcc(), EDMA3_RM_close(), EDMA3_RM_create(), EDMA3_RM_delete(), EDMA3_RM_freeContiguousResource(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_freeResource(), EDMA3_RM_getBaseAddress(), EDMA3_RM_getCCRegister(), EDMA3_RM_getGblConfigParams(), +E +DMA3_RM_getInstanceInitCfg(), EDMA3_RM_getPaRAM(), EDMA3_RM_getPaRAMPhyAddr(), EDMA3_RM_Ioctl(), EDMA3_RM_mapEdmaChannel(), EDMA3_RM_mapQdmaChannel(), EDMA3_RM_open(), EDMA3_RM_registerTccCb(), EDMA3_RM_setCCRegister(), EDMA3_RM_setPaRAM(), EDMA3_RM_unreg +isterTccCb(), EDMA3_RM_waitAndClearTcc(), findBit(), and gblChngAllocContigRes(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 FALSE\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:FALSE}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 #define FALSE\~ (0u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAAAY}{\*\bkmkend AAAAAAAAAY}FALSE +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_checkAndC +learTcc(), EDMA3_RM_close(), EDMA3_RM_create(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_freeResource(), EDMA3_RM_mapEdmaChannel(), EDMA3_RM_mapQdmaChannel(), and EDMA3_RM_waitAndClearTcc(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 NULL\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:NULL}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 #define NULL\~ 0u +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAAAZ}{\*\bkmkend AAAAAAAAAZ}Define for NULL values +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by allocAnyContigRes(), EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocLogicalChannel(), EDMA3_RM_allocResource(), EDMA3_RM_checkAndClearTcc(), EDMA3_RM_close(), EDMA3_RM_create(), EDMA3_RM_delete(), EDMA3_RM_freeCo +ntiguousResource(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_freeResource(), EDMA3_RM_getBaseAddress(), EDMA3_RM_getCCRegister(), EDMA3_RM_getGblConfigParams(), EDMA3_RM_getInstanceInitCfg(), EDMA3_RM_getPaRAM(), EDMA3_RM_getPaRAMPhyAddr(), EDMA3_RM_Ioctl( +) +, EDMA3_RM_mapEdmaChannel(), EDMA3_RM_mapQdmaChannel(), EDMA3_RM_open(), EDMA3_RM_registerTccCb(), EDMA3_RM_setCCRegister(), EDMA3_RM_setPaRAM(), EDMA3_RM_unregisterTccCb(), EDMA3_RM_waitAndClearTcc(), edma3CCErrHandler(), edma3ComplHandler(), edma3Global +RegionInit(), edma3MemCpy(), edma3MemSet(), edma3ShadowRegionInit(), edma3TCErrHandler(), and gblChngAllocContigRes(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 TRUE\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:TRUE}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 #define TRUE\~ (1u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAABA}{\*\bkmkend AAAAAAAABA}Debug mechanism used for Resource Manager Debug mechanism used for EDMA Driver Defines for boolean variables TRUE +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocLogicalChannel(), EDMA3_RM_allocResource(), EDMA3_RM_checkAndClearTcc(), EDMA3_RM_close(), EDMA3_RM_create(), EDMA3_RM_freeLogicalChannel(), EDM +A3_RM_freeResource(), EDMA3_RM_mapEdmaChannel(), EDMA3_RM_open(), edma3CCErrHandler(), edma3ComplHandler(), and gblChngAllocContigRes(). +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Typedef Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_DRV_Handle\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 edma3_common.h\:EDMA3_DRV_Handle}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +typedef void* EDMA3_DRV_Handle +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAABB}{\*\bkmkend AAAAAAAABB}EDMA3 Driver Handle. It will be returned from EDMA3_DRV_open() and will be used to call other EDMA3 Driver APIs. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_DRV_Result\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:EDMA3_DRV_Result}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +typedef int EDMA3_DRV_Result +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAABC}{\*\bkmkend AAAAAAAABC}EDMA3_DRV Result - return value of a function +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_OS_Sem_Handle\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:EDMA3_OS_Sem_Handle}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +typedef void* EDMA3_OS_Sem_Handle +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAABD}{\*\bkmkend AAAAAAAABD}OS specific Semaphore Handle. Used to acquire/free the semaphore, used for sharing of resources among multiple users. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_Handle\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:EDMA3_RM_Handle}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +typedef void* EDMA3_RM_Handle +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAABE}{\*\bkmkend AAAAAAAABE}EDMA3 Resource Manager Handle. It will be returned from }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_open()}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 and will be used to call other Resource Manager APIs. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_Result\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:EDMA3_RM_Result}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +typedef int EDMA3_RM_Result +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAABF}{\*\bkmkend AAAAAAAABF}EDMA3_RM Result - return value of a function +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Function Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 edma3OsProtectEntry\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 edma3_common.h\:edma3OsProtectEntry}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +void edma3OsProtectEntry (int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 level}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , unsigned int * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 intState}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAABG}{\*\bkmkend AAAAAAAABG}EDMA3 OS Protect Entry. +\par Critical section entry and exit functions (OS dependent) should be implemented by the application for proper linking with the EDMA3 Driver and/or EDMA3 Resource Manager. Without the definitions being provided, the image won\rquote t get linked properly. + +\par It is possible that for some regions of code, user needs ultimate degree of protection where some or all external interrupts are blocked, essentially locking out the CPU exclusively for the critical sect +ion of code. On the other hand, user may wish to merely avoid thread or task switch from occuring inside said region of code, but he may wish to entertain ISRs to run if so required. +\par Depending on the underlying OS, the number of levels of protection offered may vary. At the least, these basic levels of protection are supported -- +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +EDMA3_OS_PROTECT_INTERRUPT - Mask interrupts globally. This has real-time implications and must be used with descretion. +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +EDMA3_OS_PROTECT_SCHEDULER - Only turns off Kernel scheduler completely, but still allows h/w interrupts from being serviced. +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION - Mask EDMA3 Transfer Completion Interrupt. +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR - Mask EDMA3 CC Error Interrupt. +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR - Mask EDMA3 TC Error Interrupt. +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +These APIs should be mandatorily implemented ONCE by the global initialization routine or by the user itself. This function saves the current state of protection in 'intState' variable passed by caller, if the protec +tion level is EDMA3_OS_PROTECT_INTERRUPT. It then applies the requested level of protection. For EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION and EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR, variable 'intState' is ignored, and the requested interrupt is disabled. F +or EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR, '*intState' specifies the Transfer Controller number whose interrupt needs to be disabled. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 level +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 is numeric identifier of the desired degree of protection. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 intState}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 is memory location where current state of protection is saved for future use while restoring it via }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 edma3OsProtectExit()}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (Only for EDMA3_OS_PROTECT_INTERRUPT protection level). +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 None + +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_close(), EDMA3_RM_freeResource(), EDMA3_RM_open(), edma3CCErrHandler(), edma3ComplHandler(), edma3ShadowRegionInit(), and edma3TCErrHandler(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 edma3OsProtectExit\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:edma3OsProtectExit}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +void edma3OsProtectExit (int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 level}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 intState}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAABH}{\*\bkmkend AAAAAAAABH}EDMA3 OS Protect Exit. +\par This function undoes the pro +tection enforced to original state as is specified by the variable 'intState' passed, if the protection level is EDMA3_OS_PROTECT_INTERRUPT. For EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION and EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR, variable 'intState' is ign +ored, and the requested interrupt is enabled. For EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR, 'intState' specifies the Transfer Controller number whose interrupt needs to be enabled. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 level +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 is numeric identifier of the desired degree of protection. +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 intState}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 is original state of protection at time when the corresponding }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 edma3OsProtectEntry()}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 was called (Only for EDMA3_OS_PROTECT_INTERRUPT protection level). +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 None + +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_close(), EDMA3_RM_freeResource(), EDMA3_RM_open(), edma3CCErrHandler(), edma3ComplHandler(), edma3ShadowRegionInit(), and edma3TCErrHandler(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 edma3OsSemGive\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:edma3OsSemGive}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_DRV_Result edma3OsSemGive (EDMA3_OS_Sem_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 hSem}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAABI}{\*\bkmkend AAAAAAAABI}EDMA3 OS Semaphore Give. +\par This function gives or relinquishes an already acquired semaphore token +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 hSem} +{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] is the handle of the specified semaphore +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +EDMA3_DRV_Result if successful else a suitable error code +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), and EDMA3_RM_setCCRegister(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 edma3OsSemTake\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:edma3OsSemTake}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_DRV_Result edma3OsSemTake (EDMA3_OS_Sem_Handle }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 hSem}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 mSecTimeout}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAABJ}{\*\bkmkend AAAAAAAABJ}EDMA3 OS Semaphore Take. +\par Counting Semaphore related functions (OS de +pendent) should be implemented by the application for proper linking with the EDMA3 Driver and Resource Manager. The EDMA3 Resource Manager uses these functions for proper sharing of resources (among various users) and assume the implementation of these f +unctions to be provided by the application. Without the definitions being provided, the image won\rquote +t get linked properly. This function takes a semaphore token if available. If a semaphore is unavailable, it blocks currently running thread in wait (for specified duration) for a free semaphore. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Parameters: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 hSem} +{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] is the handle of the specified semaphore +\par }{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 mSecTimeout}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [IN] is wait time in milliseconds +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +EDMA3_DRV_Result if successful else a suitable error code +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), and EDMA3_RM_setCCRegister(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 lisrEdma3CCErrHandler0\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:lisrEdma3CCErrHandler0}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +void lisrEdma3CCErrHandler0 (unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 arg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAABK}{\*\bkmkend AAAAAAAABK}EDMA3 CC Error Interrupt Handler ISR Routine +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +References edma3CCErrHandler(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 lisrEdma3ComplHandler0\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:lisrEdma3ComplHandler0}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +void lisrEdma3ComplHandler0 (unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 arg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAABL}{\*\bkmkend AAAAAAAABL}EDMA3 ISRs which need to be registered with the underlying OS by the user (Not all TC error ISRs ne +ed to be registered, register only for the available Transfer Controllers). EDMA3 Completion Handler ISR Routine +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +References edma3ComplHandler(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 lisrEdma3TC0ErrHandler0\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:lisrEdma3TC0ErrHandler0}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +void lisrEdma3TC0ErrHandler0 (unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 arg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAABM}{\*\bkmkend AAAAAAAABM}EDMA3 TC0 Error Interrupt Handler ISR Routine +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +References edma3TCErrHandler(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 lisrEdma3TC1ErrHandler0\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:lisrEdma3TC1ErrHandler0}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +void lisrEdma3TC1ErrHandler0 (unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 arg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAABN}{\*\bkmkend AAAAAAAABN}EDMA3 TC1 Error Interrupt Handler ISR Routine +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +References edma3TCErrHandler(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 lisrEdma3TC2ErrHandler0\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:lisrEdma3TC2ErrHandler0}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +void lisrEdma3TC2ErrHandler0 (unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 arg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAABO}{\*\bkmkend AAAAAAAABO}EDMA3 TC2 Error Interrupt Handler ISR Routine +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +References edma3TCErrHandler(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 lisrEdma3TC3ErrHandler0\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:lisrEdma3TC3ErrHandler0}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +void lisrEdma3TC3ErrHandler0 (unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 arg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAABP}{\*\bkmkend AAAAAAAABP}EDMA3 TC3 Error Interrupt Handler ISR Routine +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +References edma3TCErrHandler(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 lisrEdma3TC4ErrHandler0\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:lisrEdma3TC4ErrHandler0}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +void lisrEdma3TC4ErrHandler0 (unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 arg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAABQ}{\*\bkmkend AAAAAAAABQ}EDMA3 TC4 Error Interrupt Handler ISR Routine +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +References edma3TCErrHandler(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 lisrEdma3TC5ErrHandler0\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:lisrEdma3TC5ErrHandler0}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +void lisrEdma3TC5ErrHandler0 (unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 arg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAABR}{\*\bkmkend AAAAAAAABR}EDMA3 TC5 Error Interrupt Handler ISR Routine +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +References edma3TCErrHandler(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 lisrEdma3TC6ErrHandler0\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:lisrEdma3TC6ErrHandler0}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +void lisrEdma3TC6ErrHandler0 (unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 arg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAABS}{\*\bkmkend AAAAAAAABS}EDMA3 TC6 Error Interrupt Handler ISR Routine +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +References edma3TCErrHandler(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 lisrEdma3TC7ErrHandler0\:edma3_common.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_common.h\:lisrEdma3TC7ErrHandler0}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +void lisrEdma3TC7ErrHandler0 (unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 arg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAABT}{\*\bkmkend AAAAAAAABT}EDMA3 TC7 Error Interrupt Handler ISR Routine +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +References edma3TCErrHandler(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \sect +}\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_da830_cfg.c File Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \tcl2 +{\*\bkmkstart _Toc211937578}edma3_da830_cfg.c{\*\bkmkend _Toc211937578}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 +\v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 edma3_da830_cfg.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAABU} +{\*\bkmkend AAAAAAAABU}EDMA3 Driver Adaptation Configuration File (Soc Specific) for DA8xx platform. +\par }\pard\plain \ltrpar\s18\ql \li0\ri0\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 +#include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Defines +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define } +{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 NUM_DMA_CHANNELS}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (32u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 NUM_QDMA_CHANNELS}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ (8u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 NUM_TCC}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ (32u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 NUM_PARAM_SETS}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ (128u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 NUM_EVENT_QUEUE}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ (2u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 NUM_TC}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ (2u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 NUM_REGION}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ (4u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 CHANNEL_MAPPING_EXISTENCE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0u){\*\bkmkstart AAAAAAAABV}{\*\bkmkend AAAAAAAABV} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 +Channel mapping existence A value of 0 (No channel mapping) implies that there is fixed association for a channel number to a parameter entry number or, in other words, PaRAM entry n corresponds to channel n. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define } +{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 MEM_PROTECTION_EXISTENCE}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 CC_BASE_ADDRESS}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ (0x01C00000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 TC0_BASE_ADDRESS}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ (0x01C08000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 TC1_BASE_ADDRESS}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ (0x01C08400u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 TC2_BASE_ADDRESS}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ NULL +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 TC3_BASE_ADDRESS}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ NULL +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 TC4_BASE_ADDRESS}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ NULL +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 TC5_BASE_ADDRESS}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ NULL +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 TC6_BASE_ADDRESS}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ NULL +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 TC7_BASE_ADDRESS}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ NULL +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 XFER_COMPLETION_INT}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ (8u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 CC_ERROR_INT}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ (56u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 TC0_ERROR_INT}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ (57u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 TC1_ERROR_INT}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ (58u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 TC2_ERROR_INT}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ (0u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 TC3_ERROR_INT}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ (0u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 TC4_ERROR_INT}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ (0u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 TC5_ERROR_INT}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ (0u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 TC6_ERROR_INT}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ (0u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 TC7_ERROR_INT}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ (0u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 DMA_CHANNEL_TO_EVENT_MAPPING_0}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xCF3FFFFFu) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Mapping of DMA channels 0-31 to Hardware Events from various peripherals, which use EDMA for data transfer. All channels need not be mapped, some can be free also. 1: Mapped 0: Not mapped. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define } +{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 DMA_CHANNEL_TO_EVENT_MAPPING_1}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0x0u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Mapping of DMA channels 32-63 to Hardware Events from various peripherals, which use EDMA for data transfer. All channels need not be mapped, some can be free also. 1: Mapped 0: Not mapped. +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Variables +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_GblConfigParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 edma3GblCfgParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [EDMA3_MAX_EDMA3_INSTANCES] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Static Configuration structure for EDMA3 controller, to provide Global SoC specific Information. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_InstanceInitConfig}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 defInstInitConfig}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [EDMA3_MAX_EDMA3_INSTANCES][NUM_REGION]{\*\bkmkstart AAAAAAAABW +}{\*\bkmkend AAAAAAAABW} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Default Static Region Specific Configuration structure for EDMA3 controller, to provide region specific Information. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 EDMA3 Driver Adaptation Configuration File (Soc Specific) for DA8xx platform. +\par This file contains configuration data for adaptation of EDMA3 RM +\par (C) Copyright 2008, Texas Instruments, Inc +\par }\pard\plain \ltrpar\s5\qj \li0\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Version: +\par }\pard\plain \ltrpar\s43\ql \li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 0.1 Anuj Aggarwal - Created +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Define Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 CC_BASE_ADDRESS\:edma3_da830_cfg.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 edma3_da830_cfg.c\:CC_BASE_ADDRESS}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define CC_BASE_ADDRESS\~ (0x01C00000u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAABX}{\*\bkmkend AAAAAAAABX}Global Register Region of CC Registers +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 CC_ERROR_INT\:edma3_da830_cfg.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_da830_cfg.c\:CC_ERROR_INT}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 #define CC_ERROR_INT\~ + (56u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAABY}{\*\bkmkend AAAAAAAABY}Interrupt no. for CC Error +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 DMA_CHANNEL_TO_EVENT_MAPPING_0\:edma3_da830_cfg.c}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_da830_cfg.c\:DMA_CHANNEL_TO_EVENT_MAPPING_0}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define DMA_CHANNEL_TO_EVENT_MAPPING_0\~ (0xCF3FFFFFu) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAABZ}{\*\bkmkend AAAAAAAABZ}Mapping of DMA channels 0-31 to Hardware Events from various peripherals, which use EDMA for data transfe +r. All channels need not be mapped, some can be free also. 1: Mapped 0: Not mapped. +\par This mapping will be used to allocate DMA channels when user passes EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory copy). The same mapping is us +ed to allocate the TCC when user passes EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy). +\par To allocate more DMA channels or TCCs, one has to modify the event mapping. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 DMA_CHANNEL_TO_EVENT_MAPPING_1\:edma3_da830_cfg.c}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_da830_cfg.c\:DMA_CHANNEL_TO_EVENT_MAPPING_1}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define DMA_CHANNEL_TO_EVENT_MAPPING_1\~ (0x0u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAACA}{\*\bkmkend AAAAAAAACA} +Mapping of DMA channels 32-63 to Hardware Events from various peripherals, which use EDMA for data transfer. All channels need not be mapped, some can be free also. 1: Mapped 0: Not mapped. +\par EDMA channels 22, 23, 28 & 29 which correspond to GPIO bank interrupts will be used for memory-to-memory data transfers, since there are no free dma channels. This mapping will be used to allocate DMA channels when user passes EDMA3_RM_DM +A_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory copy). The same mapping is used to allocate the TCC when user passes EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy). +\par To allocate more DMA channels or TCCs, one has to modify the event mapping. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 MEM_PROTECTION_EXISTENCE\:edma3_da830_cfg.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_da830_cfg.c\:MEM_PROTECTION_EXISTENCE}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define MEM_PROTECTION_EXISTENCE\~ (0u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAACB}{\*\bkmkend AAAAAAAACB}Existence of memory protection feature +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 NUM_DMA_CHANNELS\:edma3_da830_cfg.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_da830_cfg.c\:NUM_DMA_CHANNELS}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define NUM_DMA_CHANNELS\~ (32u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAACC}{\*\bkmkend AAAAAAAACC}Total number of DMA Channels supported by the EDMA3 Controller +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 NUM_EVENT_QUEUE\:edma3_da830_cfg.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_da830_cfg.c\:NUM_EVENT_QUEUE}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define NUM_EVENT_QUEUE\~ (2u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAACD}{\*\bkmkend AAAAAAAACD}Total number of Event Queues in the EDMA3 Controller +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 NUM_PARAM_SETS\:edma3_da830_cfg.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_da830_cfg.c\:NUM_PARAM_SETS}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 #define NUM_PARAM_SETS +\~ (128u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAACE}{\*\bkmkend AAAAAAAACE}Total number of PaRAM Sets supported by the EDMA3 Controller +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 NUM_QDMA_CHANNELS\:edma3_da830_cfg.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_da830_cfg.c\:NUM_QDMA_CHANNELS}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define NUM_QDMA_CHANNELS\~ (8u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAACF}{\*\bkmkend AAAAAAAACF}Total number of QDMA Channels supported by the EDMA3 Controller +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 NUM_REGION\:edma3_da830_cfg.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_da830_cfg.c\:NUM_REGION}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 #define NUM_REGION\~ (4u) + +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAACG}{\*\bkmkend AAAAAAAACG}Number of Regions on this EDMA3 controller +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 NUM_TC\:edma3_da830_cfg.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_da830_cfg.c\:NUM_TC}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 #define NUM_TC\~ (2u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAACH}{\*\bkmkend AAAAAAAACH}Total number of Transfer Controllers (TCs) in the EDMA3 Controller +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 NUM_TCC\:edma3_da830_cfg.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_da830_cfg.c\:NUM_TCC}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 #define NUM_TCC\~ (32u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAACI}{\*\bkmkend AAAAAAAACI}Total number of TCCs supported by the EDMA3 Controller +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 TC0_BASE_ADDRESS\:edma3_da830_cfg.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_da830_cfg.c\:TC0_BASE_ADDRESS}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define TC0_BASE_ADDRESS\~ (0x01C08000u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAACJ}{\*\bkmkend AAAAAAAACJ}Transfer Controller 0 Registers +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 TC0_ERROR_INT\:edma3_da830_cfg.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_da830_cfg.c\:TC0_ERROR_INT}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 #define TC0_ERROR_INT\~ + (57u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAACK}{\*\bkmkend AAAAAAAACK}Interrupt no. for TC 0 Error +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 TC1_BASE_ADDRESS\:edma3_da830_cfg.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_da830_cfg.c\:TC1_BASE_ADDRESS}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define TC1_BASE_ADDRESS\~ (0x01C08400u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAACL}{\*\bkmkend AAAAAAAACL}Transfer Controller 1 Registers +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 TC1_ERROR_INT\:edma3_da830_cfg.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_da830_cfg.c\:TC1_ERROR_INT}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 #define TC1_ERROR_INT\~ + (58u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAACM}{\*\bkmkend AAAAAAAACM}Interrupt no. for TC 1 Error +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 TC2_BASE_ADDRESS\:edma3_da830_cfg.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_da830_cfg.c\:TC2_BASE_ADDRESS}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define TC2_BASE_ADDRESS\~ NULL +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAACN}{\*\bkmkend AAAAAAAACN}Transfer Controller 2 Registers +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 TC2_ERROR_INT\:edma3_da830_cfg.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_da830_cfg.c\:TC2_ERROR_INT}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 #define TC2_ERROR_INT\~ + (0u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAACO}{\*\bkmkend AAAAAAAACO}Interrupt no. for TC 2 Error +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 TC3_BASE_ADDRESS\:edma3_da830_cfg.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_da830_cfg.c\:TC3_BASE_ADDRESS}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define TC3_BASE_ADDRESS\~ NULL +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAACP}{\*\bkmkend AAAAAAAACP}Transfer Controller 3 Registers +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 TC3_ERROR_INT\:edma3_da830_cfg.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_da830_cfg.c\:TC3_ERROR_INT}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 #define TC3_ERROR_INT\~ + (0u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAACQ}{\*\bkmkend AAAAAAAACQ}Interrupt no. for TC 3 Error +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 TC4_BASE_ADDRESS\:edma3_da830_cfg.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_da830_cfg.c\:TC4_BASE_ADDRESS}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 #define TC4_BASE +_ADDRESS\~ NULL +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAACR}{\*\bkmkend AAAAAAAACR}Transfer Controller 4 Registers +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 TC4_ERROR_INT\:edma3_da830_cfg.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_da830_cfg.c\:TC4_ERROR_INT}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 #define TC4_ERROR_INT\~ + (0u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAACS}{\*\bkmkend AAAAAAAACS}Interrupt no. for TC 4 Error +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 TC5_BASE_ADDRESS\:edma3_da830_cfg.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_da830_cfg.c\:TC5_BASE_ADDRESS}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define TC5_BASE_ADDRESS\~ NULL +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAACT}{\*\bkmkend AAAAAAAACT}Transfer Controller 5 Registers +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 TC5_ERROR_INT\:edma3_da830_cfg.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_da830_cfg.c\:TC5_ERROR_INT}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 #define TC5_ERROR_INT\~ + (0u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAACU}{\*\bkmkend AAAAAAAACU}Interrupt no. for TC 5 Error +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 TC6_BASE_ADDRESS\:edma3_da830_cfg.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_da830_cfg.c\:TC6_BASE_ADDRESS}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define TC6_BASE_ADDRESS\~ NULL +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAACV}{\*\bkmkend AAAAAAAACV}Transfer Controller 6 Registers +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 TC6_ERROR_INT\:edma3_da830_cfg.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_da830_cfg.c\:TC6_ERROR_INT}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 #define TC6_ERROR_INT\~ + (0u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAACW}{\*\bkmkend AAAAAAAACW}Interrupt no. for TC 6 Error +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 TC7_BASE_ADDRESS\:edma3_da830_cfg.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_da830_cfg.c\:TC7_BASE_ADDRESS}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define TC7_BASE_ADDRESS\~ NULL +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAACX}{\*\bkmkend AAAAAAAACX}Transfer Controller 7 Registers +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 TC7_ERROR_INT\:edma3_da830_cfg.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_da830_cfg.c\:TC7_ERROR_INT}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 #define TC7_ERROR_INT\~ + (0u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAACY}{\*\bkmkend AAAAAAAACY}Interrupt no. for TC 7 Error +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 XFER_COMPLETION_INT\:edma3_da830_cfg.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_da830_cfg.c\:XFER_COMPLETION_INT}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define XFER_COMPLETION_INT\~ (8u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAACZ}{\*\bkmkend AAAAAAAACZ}Interrupt no. for Transfer Completion +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Variable Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 edma3GblCfgParams\:edma3_da830_cfg.c}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 edma3_da830_cfg.c\:edma3GblCfgParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_GblConfigParams edma3GblCfgParams[EDMA3_MAX_EDMA3_INSTANCES] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAADA}{\*\bkmkend AAAAAAAADA}Static Configuration structure for EDMA3 controller, to provide Global SoC specific Information. +\par This configuration info can also be provided by the user at run-time, while calling EDMA3_RM_create (). If not provided at run-time, this info will be taken from the config file "edma3__cfg.c", for the specified platform. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 +\ltrch\fcs0 \fs24\insrsid7370340 \sect }\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 +\rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_log.h File Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc { +\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \tcl2{\*\bkmkstart _Toc211937579}edma3_log.h{\*\bkmkend _Toc211937579}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn +\pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 edma3_log.h}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAADB}{\*\bkmkend AAAAAAAADB}EDMA3 logging/tracing service. +\par }\pard\plain \ltrpar\s18\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af2 +\ltrch\fcs0 \f2\insrsid7370340 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Defines +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define } +{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 ARG1}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (arg1)\~ (arg1 << 8){\*\bkmkstart AAAAAAAADC}{\*\bkmkend AAAAAAAADC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 ARG2}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 (arg2)\~ (arg2 << 16){\*\bkmkstart AAAAAAAADD}{\*\bkmkend AAAAAAAADD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 ARG3}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 (arg3)\~ (arg3 << 24){\*\bkmkstart AAAAAAAADE}{\*\bkmkend AAAAAAAADE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_DESC}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 (event, arg1, arg2, arg3)\~ (event | ARG1(arg1) | ARG2(arg2) | ARG3(arg3)){\*\bkmkstart AAAAAAAADF}{\*\bkmkend AAAAAAAADF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_LOG_EVENT}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ LOG_printf4{\*\bkmkstart AAAAAAAADG}{\*\bkmkend AAAAAAAADG} +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Enumerations +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_logEventType}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_eINT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 +\ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_eINT_START}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_eINT_END}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_eFUNC}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_eFUNC_START}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 EDMA3_DVT_eFUNC_END}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_ePACKET_START}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 EDMA3_DVT_ePACKET_END}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_eDATA_SND}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 EDMA3_DVT_eDATA_SND_START}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_eDATA_SND_END}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 EDMA3_DVT_eDATA_RCV}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_eRCV_START}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 EDMA3_DVT_eRCV_END}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_eSMPL_COUNTER}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 EDMA3_DVT_eEVENT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_eEVENT_START}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 EDMA3_DVT_eEVENT_END}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 enum }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_logDataDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_dNONE}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_dINST}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_dINITIATOR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_dMSG_ID}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 +\ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_dCOUNTER}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_dSIZE_BYTES}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_dSIZE_WORDS}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_dPADD}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 EDMA3_DVT_dDADD}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_dDATA}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_DVT_dPACKET_ID}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_DVT_dCHANNEL_ID}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \} +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Variables +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +far LOG_Obj }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 DVTEvent_Log}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAADH}{\*\bkmkend AAAAAAAADH} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 EDMA3 logging/tracing service. +\par This file contains interface for EDMA3 error/event/message logging and tracing service. +\par (C) Copyright 2006, Texas Instruments, Inc +\par }\pard\plain \ltrpar\s5\qj \li0\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Author: +\par }\pard\plain \ltrpar\s43\ql \li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 EDMA3 Architecture Team +\par }\pard\plain \ltrpar\s5\qj \li0\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Version: +\par }\pard\plain \ltrpar\s43\ql \li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 1.0 Anant Gole Created +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 +\ltrch\fcs0 \fs24\insrsid7370340 +\par \sect }\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 +\ltrch\fcs0 \b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_rl_cc.h File Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc { +\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \tcl2{\*\bkmkstart _Toc211937580}edma3_rl_cc.h{\*\bkmkend _Toc211937580}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn +\pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 edma3_rl_cc.h}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAADI}{\*\bkmkend AAAAAAAADI}EDMA3 Channel Controller Register Desciption. +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Data Structures +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DraRegs}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 struct }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QueevtentryRegs}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 struct }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ShadowRegs}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 struct }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ParamentryRegs}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 struct }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_Regs}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Defines +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define } +{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_REV_TYPE_MASK}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00FF0000u){\*\bkmkstart AAAAAAAADJ}{\*\bkmkend AAAAAAAADJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_REV_TYPE_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAADK}{\*\bkmkend AAAAAAAADK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_REV_TYPE_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAADL}{\*\bkmkend AAAAAAAADL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_REV_CLASS_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000FF00u){\*\bkmkstart AAAAAAAADM}{\*\bkmkend AAAAAAAADM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_REV_CLASS_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAADN}{\*\bkmkend AAAAAAAADN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_REV_CLASS_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAADO}{\*\bkmkend AAAAAAAADO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_REV_RESERVED_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x000000FFu){\*\bkmkstart AAAAAAAADP}{\*\bkmkend AAAAAAAADP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_REV_RESERVED_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAADQ}{\*\bkmkend AAAAAAAADQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_REV_RESERVED_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAADR}{\*\bkmkend AAAAAAAADR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_REV_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00070400u){\*\bkmkstart AAAAAAAADS}{\*\bkmkend AAAAAAAADS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_MP_EXIST_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x02000000u){\*\bkmkstart AAAAAAAADT}{\*\bkmkend AAAAAAAADT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_MP_EXIST_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000019u){\*\bkmkstart AAAAAAAADU}{\*\bkmkend AAAAAAAADU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_MP_EXIST_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAADV}{\*\bkmkend AAAAAAAADV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_MP_EXIST_NONE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAADW}{\*\bkmkend AAAAAAAADW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_MP_EXIST_INCLUDED}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAADX}{\*\bkmkend AAAAAAAADX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_CHMAP_EXIST_MASK}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x01000000u){\*\bkmkstart AAAAAAAADY}{\*\bkmkend AAAAAAAADY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_CHMAP_EXIST_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAAADZ}{\*\bkmkend AAAAAAAADZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_CHMAP_EXIST_RESETVAL}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAEA}{\*\bkmkend AAAAAAAAEA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_CHMAP_EXIST_NONE}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAEB}{\*\bkmkend AAAAAAAAEB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_CHMAP_EXIST_INCLUDED}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAAEC}{\*\bkmkend AAAAAAAAEC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_REGN_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00300000u){\*\bkmkstart AAAAAAAAED}{\*\bkmkend AAAAAAAAED} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_REGN_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAAAEE}{\*\bkmkend AAAAAAAAEE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_REGN_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAEF}{\*\bkmkend AAAAAAAAEF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_REGN_0}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAEG}{\*\bkmkend AAAAAAAAEG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_REGN_2}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAAEH}{\*\bkmkend AAAAAAAAEH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_REGN_4}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAAEI}{\*\bkmkend AAAAAAAAEI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_REGN_8}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAAEJ}{\*\bkmkend AAAAAAAAEJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_TC_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00070000u){\*\bkmkstart AAAAAAAAEK}{\*\bkmkend AAAAAAAAEK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_TC_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAAEL}{\*\bkmkend AAAAAAAAEL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_TC_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAEM}{\*\bkmkend AAAAAAAAEM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_TC_1}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAEN}{\*\bkmkend AAAAAAAAEN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_TC_2}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAAEO}{\*\bkmkend AAAAAAAAEO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_TC_3}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAAEP}{\*\bkmkend AAAAAAAAEP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_TC_4}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAAEQ}{\*\bkmkend AAAAAAAAEQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_TC_5}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAAER}{\*\bkmkend AAAAAAAAER} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_TC_6}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAAAES}{\*\bkmkend AAAAAAAAES} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_TC_7}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAAAET}{\*\bkmkend AAAAAAAAET} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_TC_8}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAAEU}{\*\bkmkend AAAAAAAAEU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_PAENTRY_MASK}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00007000u){\*\bkmkstart AAAAAAAAEV}{\*\bkmkend AAAAAAAAEV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_PAENTRY_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAAAEW}{\*\bkmkend AAAAAAAAEW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_PAENTRY_RESETVAL}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAEX}{\*\bkmkend AAAAAAAAEX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_PAENTRY_16}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAEY}{\*\bkmkend AAAAAAAAEY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_PAENTRY_32}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAAEZ}{\*\bkmkend AAAAAAAAEZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_PAENTRY_64}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAAFA}{\*\bkmkend AAAAAAAAFA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_PAENTRY_128}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAAFB}{\*\bkmkend AAAAAAAAFB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_PAENTRY_256}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAAFC}{\*\bkmkend AAAAAAAAFC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_PAENTRY_512}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAAAFD}{\*\bkmkend AAAAAAAAFD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_INTCH_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000700u){\*\bkmkstart AAAAAAAAFE}{\*\bkmkend AAAAAAAAFE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_INTCH_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAAFF}{\*\bkmkend AAAAAAAAFF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_INTCH_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAFG}{\*\bkmkend AAAAAAAAFG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_INTCH_8}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAAFH}{\*\bkmkend AAAAAAAAFH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_INTCH_16}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAAFI}{\*\bkmkend AAAAAAAAFI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_INTCH_32}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAAFJ}{\*\bkmkend AAAAAAAAFJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_INTCH_64}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAAFK}{\*\bkmkend AAAAAAAAFK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_QDMACH_MASK}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000070u){\*\bkmkstart AAAAAAAAFL}{\*\bkmkend AAAAAAAAFL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_QDMACH_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAAFM}{\*\bkmkend AAAAAAAAFM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_QDMACH_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAFN}{\*\bkmkend AAAAAAAAFN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_QDMACH_NONE}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAFO}{\*\bkmkend AAAAAAAAFO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_QDMACH_2}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAAFP}{\*\bkmkend AAAAAAAAFP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_QDMACH_4}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAAFQ}{\*\bkmkend AAAAAAAAFQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_QDMACH_6}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAAFR}{\*\bkmkend AAAAAAAAFR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_QDMACH_8}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAAFS}{\*\bkmkend AAAAAAAAFS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_DMACH_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAAFT}{\*\bkmkend AAAAAAAAFT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_DMACH_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAFU}{\*\bkmkend AAAAAAAAFU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_DMACH_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAFV}{\*\bkmkend AAAAAAAAFV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_DMACH_NONE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAFW}{\*\bkmkend AAAAAAAAFW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_DMACH_4}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAAFX}{\*\bkmkend AAAAAAAAFX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_DMACH_8}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAAFY}{\*\bkmkend AAAAAAAAFY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_DMACH_16}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAAFZ}{\*\bkmkend AAAAAAAAFZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_DMACH_32}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAAGA}{\*\bkmkend AAAAAAAAGA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_NUM_DMACH_64}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAAAGB}{\*\bkmkend AAAAAAAAGB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCCFG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAGC}{\*\bkmkend AAAAAAAAGC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DCHMAP_PAENTRY_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00003FE0u){\*\bkmkstart AAAAAAAAGD}{\*\bkmkend AAAAAAAAGD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DCHMAP_PAENTRY_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAAAGE}{\*\bkmkend AAAAAAAAGE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DCHMAP_PAENTRY_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAGF}{\*\bkmkend AAAAAAAAGF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DCHMAP_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAGG}{\*\bkmkend AAAAAAAAGG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QCHMAP_PAENTRY_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00003FE0u){\*\bkmkstart AAAAAAAAGH}{\*\bkmkend AAAAAAAAGH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QCHMAP_PAENTRY_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAAAGI}{\*\bkmkend AAAAAAAAGI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QCHMAP_PAENTRY_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAGJ}{\*\bkmkend AAAAAAAAGJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QCHMAP_TRWORD_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAAAGK}{\*\bkmkend AAAAAAAAGK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QCHMAP_TRWORD_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAAGL}{\*\bkmkend AAAAAAAAGL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QCHMAP_TRWORD_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAGM}{\*\bkmkend AAAAAAAAGM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QCHMAP_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAGN}{\*\bkmkend AAAAAAAAGN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DMAQNUM_E7_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x70000000u){\*\bkmkstart AAAAAAAAGO}{\*\bkmkend AAAAAAAAGO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DMAQNUM_E7_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAAAGP}{\*\bkmkend AAAAAAAAGP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DMAQNUM_E7_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAGQ}{\*\bkmkend AAAAAAAAGQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DMAQNUM_E6_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x07000000u){\*\bkmkstart AAAAAAAAGR}{\*\bkmkend AAAAAAAAGR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DMAQNUM_E6_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAAAGS}{\*\bkmkend AAAAAAAAGS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DMAQNUM_E6_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAGT}{\*\bkmkend AAAAAAAAGT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DMAQNUM_E5_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00700000u){\*\bkmkstart AAAAAAAAGU}{\*\bkmkend AAAAAAAAGU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DMAQNUM_E5_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAAAGV}{\*\bkmkend AAAAAAAAGV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DMAQNUM_E5_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAGW}{\*\bkmkend AAAAAAAAGW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DMAQNUM_E4_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00070000u){\*\bkmkstart AAAAAAAAGX}{\*\bkmkend AAAAAAAAGX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DMAQNUM_E4_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAAGY}{\*\bkmkend AAAAAAAAGY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DMAQNUM_E4_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAGZ}{\*\bkmkend AAAAAAAAGZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DMAQNUM_E3_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00007000u){\*\bkmkstart AAAAAAAAHA}{\*\bkmkend AAAAAAAAHA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DMAQNUM_E3_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAAAHB}{\*\bkmkend AAAAAAAAHB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DMAQNUM_E3_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAHC}{\*\bkmkend AAAAAAAAHC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DMAQNUM_E2_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000700u){\*\bkmkstart AAAAAAAAHD}{\*\bkmkend AAAAAAAAHD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DMAQNUM_E2_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAAHE}{\*\bkmkend AAAAAAAAHE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DMAQNUM_E2_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAHF}{\*\bkmkend AAAAAAAAHF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DMAQNUM_E1_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000070u){\*\bkmkstart AAAAAAAAHG}{\*\bkmkend AAAAAAAAHG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DMAQNUM_E1_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAAHH}{\*\bkmkend AAAAAAAAHH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DMAQNUM_E1_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAHI}{\*\bkmkend AAAAAAAAHI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DMAQNUM_E0_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAAHJ}{\*\bkmkend AAAAAAAAHJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DMAQNUM_E0_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAHK}{\*\bkmkend AAAAAAAAHK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DMAQNUM_E0_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAHL}{\*\bkmkend AAAAAAAAHL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DMAQNUM_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAHM}{\*\bkmkend AAAAAAAAHM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QDMAQNUM_E7_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x70000000u){\*\bkmkstart AAAAAAAAHN}{\*\bkmkend AAAAAAAAHN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QDMAQNUM_E7_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAAAHO}{\*\bkmkend AAAAAAAAHO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QDMAQNUM_E7_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAHP}{\*\bkmkend AAAAAAAAHP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QDMAQNUM_E6_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x07000000u){\*\bkmkstart AAAAAAAAHQ}{\*\bkmkend AAAAAAAAHQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QDMAQNUM_E6_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAAAHR}{\*\bkmkend AAAAAAAAHR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QDMAQNUM_E6_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAHS}{\*\bkmkend AAAAAAAAHS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QDMAQNUM_E5_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00700000u){\*\bkmkstart AAAAAAAAHT}{\*\bkmkend AAAAAAAAHT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QDMAQNUM_E5_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAAAHU}{\*\bkmkend AAAAAAAAHU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QDMAQNUM_E5_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAHV}{\*\bkmkend AAAAAAAAHV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QDMAQNUM_E4_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00070000u){\*\bkmkstart AAAAAAAAHW}{\*\bkmkend AAAAAAAAHW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QDMAQNUM_E4_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAAHX}{\*\bkmkend AAAAAAAAHX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QDMAQNUM_E4_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAHY}{\*\bkmkend AAAAAAAAHY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QDMAQNUM_E3_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00007000u){\*\bkmkstart AAAAAAAAHZ}{\*\bkmkend AAAAAAAAHZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QDMAQNUM_E3_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAAAIA}{\*\bkmkend AAAAAAAAIA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QDMAQNUM_E3_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAIB}{\*\bkmkend AAAAAAAAIB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QDMAQNUM_E2_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000700u){\*\bkmkstart AAAAAAAAIC}{\*\bkmkend AAAAAAAAIC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QDMAQNUM_E2_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAAID}{\*\bkmkend AAAAAAAAID} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QDMAQNUM_E2_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAIE}{\*\bkmkend AAAAAAAAIE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QDMAQNUM_E1_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000070u){\*\bkmkstart AAAAAAAAIF}{\*\bkmkend AAAAAAAAIF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QDMAQNUM_E1_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAAIG}{\*\bkmkend AAAAAAAAIG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QDMAQNUM_E1_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAIH}{\*\bkmkend AAAAAAAAIH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QDMAQNUM_E0_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAAII}{\*\bkmkend AAAAAAAAII} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QDMAQNUM_E0_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAIJ}{\*\bkmkend AAAAAAAAIJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QDMAQNUM_E0_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAIK}{\*\bkmkend AAAAAAAAIK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QDMAQNUM_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAIL}{\*\bkmkend AAAAAAAAIL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUETCMAP_TCNUMQ7_MASK}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x70000000u){\*\bkmkstart AAAAAAAAIM}{\*\bkmkend AAAAAAAAIM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUETCMAP_TCNUMQ7_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAAAIN}{\*\bkmkend AAAAAAAAIN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUETCMAP_TCNUMQ7_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAIO}{\*\bkmkend AAAAAAAAIO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUETCMAP_TCNUMQ6_MASK}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x07000000u){\*\bkmkstart AAAAAAAAIP}{\*\bkmkend AAAAAAAAIP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUETCMAP_TCNUMQ6_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAAAIQ}{\*\bkmkend AAAAAAAAIQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUETCMAP_TCNUMQ6_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAIR}{\*\bkmkend AAAAAAAAIR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUETCMAP_TCNUMQ5_MASK}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00700000u){\*\bkmkstart AAAAAAAAIS}{\*\bkmkend AAAAAAAAIS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUETCMAP_TCNUMQ5_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAAAIT}{\*\bkmkend AAAAAAAAIT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUETCMAP_TCNUMQ5_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAIU}{\*\bkmkend AAAAAAAAIU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUETCMAP_TCNUMQ4_MASK}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00070000u){\*\bkmkstart AAAAAAAAIV}{\*\bkmkend AAAAAAAAIV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUETCMAP_TCNUMQ4_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAAIW}{\*\bkmkend AAAAAAAAIW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUETCMAP_TCNUMQ4_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAIX}{\*\bkmkend AAAAAAAAIX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUETCMAP_TCNUMQ3_MASK}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00007000u){\*\bkmkstart AAAAAAAAIY}{\*\bkmkend AAAAAAAAIY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUETCMAP_TCNUMQ3_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAAAIZ}{\*\bkmkend AAAAAAAAIZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUETCMAP_TCNUMQ3_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAJA}{\*\bkmkend AAAAAAAAJA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUETCMAP_TCNUMQ2_MASK}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000700u){\*\bkmkstart AAAAAAAAJB}{\*\bkmkend AAAAAAAAJB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUETCMAP_TCNUMQ2_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAAJC}{\*\bkmkend AAAAAAAAJC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUETCMAP_TCNUMQ2_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAJD}{\*\bkmkend AAAAAAAAJD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUETCMAP_TCNUMQ1_MASK}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000070u){\*\bkmkstart AAAAAAAAJE}{\*\bkmkend AAAAAAAAJE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUETCMAP_TCNUMQ1_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAAJF}{\*\bkmkend AAAAAAAAJF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUETCMAP_TCNUMQ1_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAJG}{\*\bkmkend AAAAAAAAJG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUETCMAP_TCNUMQ0_MASK}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAAJH}{\*\bkmkend AAAAAAAAJH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUETCMAP_TCNUMQ0_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAJI}{\*\bkmkend AAAAAAAAJI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUETCMAP_TCNUMQ0_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAJJ}{\*\bkmkend AAAAAAAAJJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUETCMAP_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAJK}{\*\bkmkend AAAAAAAAJK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUEPRI_PRIQ7_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x70000000u){\*\bkmkstart AAAAAAAAJL}{\*\bkmkend AAAAAAAAJL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUEPRI_PRIQ7_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAAAJM}{\*\bkmkend AAAAAAAAJM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUEPRI_PRIQ7_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAJN}{\*\bkmkend AAAAAAAAJN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUEPRI_PRIQ6_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x07000000u){\*\bkmkstart AAAAAAAAJO}{\*\bkmkend AAAAAAAAJO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUEPRI_PRIQ6_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAAAJP}{\*\bkmkend AAAAAAAAJP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUEPRI_PRIQ6_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAJQ}{\*\bkmkend AAAAAAAAJQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUEPRI_PRIQ5_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00700000u){\*\bkmkstart AAAAAAAAJR}{\*\bkmkend AAAAAAAAJR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUEPRI_PRIQ5_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAAAJS}{\*\bkmkend AAAAAAAAJS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUEPRI_PRIQ5_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAJT}{\*\bkmkend AAAAAAAAJT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUEPRI_PRIQ4_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00070000u){\*\bkmkstart AAAAAAAAJU}{\*\bkmkend AAAAAAAAJU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUEPRI_PRIQ4_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAAJV}{\*\bkmkend AAAAAAAAJV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUEPRI_PRIQ4_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAJW}{\*\bkmkend AAAAAAAAJW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUEPRI_PRIQ3_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00007000u){\*\bkmkstart AAAAAAAAJX}{\*\bkmkend AAAAAAAAJX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUEPRI_PRIQ3_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAAAJY}{\*\bkmkend AAAAAAAAJY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUEPRI_PRIQ3_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAJZ}{\*\bkmkend AAAAAAAAJZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUEPRI_PRIQ2_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000700u){\*\bkmkstart AAAAAAAAKA}{\*\bkmkend AAAAAAAAKA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUEPRI_PRIQ2_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAAKB}{\*\bkmkend AAAAAAAAKB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUEPRI_PRIQ2_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAKC}{\*\bkmkend AAAAAAAAKC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUEPRI_PRIQ1_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000070u){\*\bkmkstart AAAAAAAAKD}{\*\bkmkend AAAAAAAAKD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUEPRI_PRIQ1_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAAKE}{\*\bkmkend AAAAAAAAKE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUEPRI_PRIQ1_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAKF}{\*\bkmkend AAAAAAAAKF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUEPRI_PRIQ0_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAAKG}{\*\bkmkend AAAAAAAAKG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUEPRI_PRIQ0_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAKH}{\*\bkmkend AAAAAAAAKH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUEPRI_PRIQ0_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAKI}{\*\bkmkend AAAAAAAAKI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUEPRI_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAKJ}{\*\bkmkend AAAAAAAAKJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E31_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x80000000u){\*\bkmkstart AAAAAAAAKK}{\*\bkmkend AAAAAAAAKK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E31_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAAAKL}{\*\bkmkend AAAAAAAAKL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E31_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAKM}{\*\bkmkend AAAAAAAAKM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E30_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x40000000u){\*\bkmkstart AAAAAAAAKN}{\*\bkmkend AAAAAAAAKN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E30_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Eu){\*\bkmkstart AAAAAAAAKO}{\*\bkmkend AAAAAAAAKO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E30_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAKP}{\*\bkmkend AAAAAAAAKP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E29_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x20000000u){\*\bkmkstart AAAAAAAAKQ}{\*\bkmkend AAAAAAAAKQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E29_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Du){\*\bkmkstart AAAAAAAAKR}{\*\bkmkend AAAAAAAAKR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E29_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAKS}{\*\bkmkend AAAAAAAAKS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E28_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x10000000u){\*\bkmkstart AAAAAAAAKT}{\*\bkmkend AAAAAAAAKT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E28_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAAAKU}{\*\bkmkend AAAAAAAAKU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E28_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAKV}{\*\bkmkend AAAAAAAAKV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E27_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x08000000u){\*\bkmkstart AAAAAAAAKW}{\*\bkmkend AAAAAAAAKW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E27_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Bu){\*\bkmkstart AAAAAAAAKX}{\*\bkmkend AAAAAAAAKX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E27_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAKY}{\*\bkmkend AAAAAAAAKY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E26_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x04000000u){\*\bkmkstart AAAAAAAAKZ}{\*\bkmkend AAAAAAAAKZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E26_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Au){\*\bkmkstart AAAAAAAALA}{\*\bkmkend AAAAAAAALA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E26_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAALB}{\*\bkmkend AAAAAAAALB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E25_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x02000000u){\*\bkmkstart AAAAAAAALC}{\*\bkmkend AAAAAAAALC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E25_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000019u){\*\bkmkstart AAAAAAAALD}{\*\bkmkend AAAAAAAALD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E25_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAALE}{\*\bkmkend AAAAAAAALE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E24_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x01000000u){\*\bkmkstart AAAAAAAALF}{\*\bkmkend AAAAAAAALF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E24_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAAALG}{\*\bkmkend AAAAAAAALG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E24_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAALH}{\*\bkmkend AAAAAAAALH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E23_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00800000u){\*\bkmkstart AAAAAAAALI}{\*\bkmkend AAAAAAAALI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E23_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000017u){\*\bkmkstart AAAAAAAALJ}{\*\bkmkend AAAAAAAALJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E23_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAALK}{\*\bkmkend AAAAAAAALK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E22_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAAALL}{\*\bkmkend AAAAAAAALL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E22_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAAALM}{\*\bkmkend AAAAAAAALM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E22_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAALN}{\*\bkmkend AAAAAAAALN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E21_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00200000u){\*\bkmkstart AAAAAAAALO}{\*\bkmkend AAAAAAAALO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E21_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAAALP}{\*\bkmkend AAAAAAAALP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E21_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAALQ}{\*\bkmkend AAAAAAAALQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E20_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAAALR}{\*\bkmkend AAAAAAAALR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E20_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAAALS}{\*\bkmkend AAAAAAAALS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E20_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAALT}{\*\bkmkend AAAAAAAALT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E19_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00080000u){\*\bkmkstart AAAAAAAALU}{\*\bkmkend AAAAAAAALU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E19_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000013u){\*\bkmkstart AAAAAAAALV}{\*\bkmkend AAAAAAAALV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E19_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAALW}{\*\bkmkend AAAAAAAALW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E18_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00040000u){\*\bkmkstart AAAAAAAALX}{\*\bkmkend AAAAAAAALX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E18_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000012u){\*\bkmkstart AAAAAAAALY}{\*\bkmkend AAAAAAAALY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E18_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAALZ}{\*\bkmkend AAAAAAAALZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E17_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00020000u){\*\bkmkstart AAAAAAAAMA}{\*\bkmkend AAAAAAAAMA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E17_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000011u){\*\bkmkstart AAAAAAAAMB}{\*\bkmkend AAAAAAAAMB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E17_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAMC}{\*\bkmkend AAAAAAAAMC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E16_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAAAMD}{\*\bkmkend AAAAAAAAMD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E16_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAAME}{\*\bkmkend AAAAAAAAME} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E16_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAMF}{\*\bkmkend AAAAAAAAMF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E15_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00008000u){\*\bkmkstart AAAAAAAAMG}{\*\bkmkend AAAAAAAAMG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E15_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAAAMH}{\*\bkmkend AAAAAAAAMH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E15_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAMI}{\*\bkmkend AAAAAAAAMI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E14_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00004000u){\*\bkmkstart AAAAAAAAMJ}{\*\bkmkend AAAAAAAAMJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E14_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Eu){\*\bkmkstart AAAAAAAAMK}{\*\bkmkend AAAAAAAAMK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E14_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAML}{\*\bkmkend AAAAAAAAML} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E13_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00002000u){\*\bkmkstart AAAAAAAAMM}{\*\bkmkend AAAAAAAAMM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E13_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Du){\*\bkmkstart AAAAAAAAMN}{\*\bkmkend AAAAAAAAMN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E13_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAMO}{\*\bkmkend AAAAAAAAMO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E12_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001000u){\*\bkmkstart AAAAAAAAMP}{\*\bkmkend AAAAAAAAMP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E12_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAAAMQ}{\*\bkmkend AAAAAAAAMQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E12_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAMR}{\*\bkmkend AAAAAAAAMR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E11_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAAAMS}{\*\bkmkend AAAAAAAAMS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E11_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAAAMT}{\*\bkmkend AAAAAAAAMT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E11_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAMU}{\*\bkmkend AAAAAAAAMU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E10_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000400u){\*\bkmkstart AAAAAAAAMV}{\*\bkmkend AAAAAAAAMV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E10_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAAAMW}{\*\bkmkend AAAAAAAAMW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E10_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAMX}{\*\bkmkend AAAAAAAAMX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E9_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000200u){\*\bkmkstart AAAAAAAAMY}{\*\bkmkend AAAAAAAAMY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E9_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAAAMZ}{\*\bkmkend AAAAAAAAMZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E9_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAANA}{\*\bkmkend AAAAAAAANA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E8_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAAANB}{\*\bkmkend AAAAAAAANB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E8_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAANC}{\*\bkmkend AAAAAAAANC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E8_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAND}{\*\bkmkend AAAAAAAAND} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E7_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAAANE}{\*\bkmkend AAAAAAAANE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E7_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAANF}{\*\bkmkend AAAAAAAANF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E7_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAANG}{\*\bkmkend AAAAAAAANG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E6_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAAANH}{\*\bkmkend AAAAAAAANH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E6_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAAANI}{\*\bkmkend AAAAAAAANI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E6_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAANJ}{\*\bkmkend AAAAAAAANJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E5_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAAANK}{\*\bkmkend AAAAAAAANK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E5_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAAANL}{\*\bkmkend AAAAAAAANL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E5_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAANM}{\*\bkmkend AAAAAAAANM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E4_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAANN}{\*\bkmkend AAAAAAAANN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E4_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAANO}{\*\bkmkend AAAAAAAANO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E4_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAANP}{\*\bkmkend AAAAAAAANP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E3_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAANQ}{\*\bkmkend AAAAAAAANQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E3_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAANR}{\*\bkmkend AAAAAAAANR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E3_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAANS}{\*\bkmkend AAAAAAAANS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E2_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAANT}{\*\bkmkend AAAAAAAANT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E2_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAANU}{\*\bkmkend AAAAAAAANU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E2_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAANV}{\*\bkmkend AAAAAAAANV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E1_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAANW}{\*\bkmkend AAAAAAAANW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E1_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAANX}{\*\bkmkend AAAAAAAANX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E1_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAANY}{\*\bkmkend AAAAAAAANY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E0_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAANZ}{\*\bkmkend AAAAAAAANZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E0_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAOA}{\*\bkmkend AAAAAAAAOA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_E0_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAOB}{\*\bkmkend AAAAAAAAOB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAOC}{\*\bkmkend AAAAAAAAOC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E63_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x80000000u){\*\bkmkstart AAAAAAAAOD}{\*\bkmkend AAAAAAAAOD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E63_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAAAOE}{\*\bkmkend AAAAAAAAOE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E63_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAOF}{\*\bkmkend AAAAAAAAOF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E62_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x40000000u){\*\bkmkstart AAAAAAAAOG}{\*\bkmkend AAAAAAAAOG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E62_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Eu){\*\bkmkstart AAAAAAAAOH}{\*\bkmkend AAAAAAAAOH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E62_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAOI}{\*\bkmkend AAAAAAAAOI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E61_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x20000000u){\*\bkmkstart AAAAAAAAOJ}{\*\bkmkend AAAAAAAAOJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E61_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Du){\*\bkmkstart AAAAAAAAOK}{\*\bkmkend AAAAAAAAOK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E61_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAOL}{\*\bkmkend AAAAAAAAOL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E60_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x10000000u){\*\bkmkstart AAAAAAAAOM}{\*\bkmkend AAAAAAAAOM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E60_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAAAON}{\*\bkmkend AAAAAAAAON} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E60_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAOO}{\*\bkmkend AAAAAAAAOO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E59_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x08000000u){\*\bkmkstart AAAAAAAAOP}{\*\bkmkend AAAAAAAAOP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E59_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Bu){\*\bkmkstart AAAAAAAAOQ}{\*\bkmkend AAAAAAAAOQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E59_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAOR}{\*\bkmkend AAAAAAAAOR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E58_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x04000000u){\*\bkmkstart AAAAAAAAOS}{\*\bkmkend AAAAAAAAOS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E58_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Au){\*\bkmkstart AAAAAAAAOT}{\*\bkmkend AAAAAAAAOT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E58_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAOU}{\*\bkmkend AAAAAAAAOU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E57_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x02000000u){\*\bkmkstart AAAAAAAAOV}{\*\bkmkend AAAAAAAAOV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E57_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000019u){\*\bkmkstart AAAAAAAAOW}{\*\bkmkend AAAAAAAAOW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E57_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAOX}{\*\bkmkend AAAAAAAAOX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E56_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x01000000u){\*\bkmkstart AAAAAAAAOY}{\*\bkmkend AAAAAAAAOY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E56_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAAAOZ}{\*\bkmkend AAAAAAAAOZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E56_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAPA}{\*\bkmkend AAAAAAAAPA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E55_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00800000u){\*\bkmkstart AAAAAAAAPB}{\*\bkmkend AAAAAAAAPB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E55_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000017u){\*\bkmkstart AAAAAAAAPC}{\*\bkmkend AAAAAAAAPC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E55_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAPD}{\*\bkmkend AAAAAAAAPD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E54_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAAAPE}{\*\bkmkend AAAAAAAAPE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E54_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAAAPF}{\*\bkmkend AAAAAAAAPF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E54_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAPG}{\*\bkmkend AAAAAAAAPG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E53_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00200000u){\*\bkmkstart AAAAAAAAPH}{\*\bkmkend AAAAAAAAPH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E53_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAAAPI}{\*\bkmkend AAAAAAAAPI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E53_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAPJ}{\*\bkmkend AAAAAAAAPJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E52_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAAAPK}{\*\bkmkend AAAAAAAAPK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E52_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAAAPL}{\*\bkmkend AAAAAAAAPL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E52_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAPM}{\*\bkmkend AAAAAAAAPM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E51_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00080000u){\*\bkmkstart AAAAAAAAPN}{\*\bkmkend AAAAAAAAPN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E51_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000013u){\*\bkmkstart AAAAAAAAPO}{\*\bkmkend AAAAAAAAPO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E51_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAPP}{\*\bkmkend AAAAAAAAPP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E50_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00040000u){\*\bkmkstart AAAAAAAAPQ}{\*\bkmkend AAAAAAAAPQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E50_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000012u){\*\bkmkstart AAAAAAAAPR}{\*\bkmkend AAAAAAAAPR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E50_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAPS}{\*\bkmkend AAAAAAAAPS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E49_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00020000u){\*\bkmkstart AAAAAAAAPT}{\*\bkmkend AAAAAAAAPT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E49_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000011u){\*\bkmkstart AAAAAAAAPU}{\*\bkmkend AAAAAAAAPU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E49_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAPV}{\*\bkmkend AAAAAAAAPV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E48_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAAAPW}{\*\bkmkend AAAAAAAAPW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E48_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAAPX}{\*\bkmkend AAAAAAAAPX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E48_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAPY}{\*\bkmkend AAAAAAAAPY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E47_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00008000u){\*\bkmkstart AAAAAAAAPZ}{\*\bkmkend AAAAAAAAPZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E47_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAAAQA}{\*\bkmkend AAAAAAAAQA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E47_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAQB}{\*\bkmkend AAAAAAAAQB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E46_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00004000u){\*\bkmkstart AAAAAAAAQC}{\*\bkmkend AAAAAAAAQC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E46_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Eu){\*\bkmkstart AAAAAAAAQD}{\*\bkmkend AAAAAAAAQD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E46_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAQE}{\*\bkmkend AAAAAAAAQE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E45_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00002000u){\*\bkmkstart AAAAAAAAQF}{\*\bkmkend AAAAAAAAQF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E45_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Du){\*\bkmkstart AAAAAAAAQG}{\*\bkmkend AAAAAAAAQG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E45_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAQH}{\*\bkmkend AAAAAAAAQH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E44_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001000u){\*\bkmkstart AAAAAAAAQI}{\*\bkmkend AAAAAAAAQI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E44_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAAAQJ}{\*\bkmkend AAAAAAAAQJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E44_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAQK}{\*\bkmkend AAAAAAAAQK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E43_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAAAQL}{\*\bkmkend AAAAAAAAQL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E43_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAAAQM}{\*\bkmkend AAAAAAAAQM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E43_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAQN}{\*\bkmkend AAAAAAAAQN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E42_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000400u){\*\bkmkstart AAAAAAAAQO}{\*\bkmkend AAAAAAAAQO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E42_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAAAQP}{\*\bkmkend AAAAAAAAQP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E42_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAQQ}{\*\bkmkend AAAAAAAAQQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E41_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000200u){\*\bkmkstart AAAAAAAAQR}{\*\bkmkend AAAAAAAAQR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E41_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAAAQS}{\*\bkmkend AAAAAAAAQS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E41_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAQT}{\*\bkmkend AAAAAAAAQT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E40_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAAAQU}{\*\bkmkend AAAAAAAAQU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E40_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAAQV}{\*\bkmkend AAAAAAAAQV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E40_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAQW}{\*\bkmkend AAAAAAAAQW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E39_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAAAQX}{\*\bkmkend AAAAAAAAQX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E39_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAAQY}{\*\bkmkend AAAAAAAAQY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E39_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAQZ}{\*\bkmkend AAAAAAAAQZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E38_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAAARA}{\*\bkmkend AAAAAAAARA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E38_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAAARB}{\*\bkmkend AAAAAAAARB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E38_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAARC}{\*\bkmkend AAAAAAAARC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E37_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAAARD}{\*\bkmkend AAAAAAAARD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E37_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAAARE}{\*\bkmkend AAAAAAAARE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E37_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAARF}{\*\bkmkend AAAAAAAARF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E36_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAARG}{\*\bkmkend AAAAAAAARG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E36_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAARH}{\*\bkmkend AAAAAAAARH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E36_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAARI}{\*\bkmkend AAAAAAAARI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E35_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAARJ}{\*\bkmkend AAAAAAAARJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E35_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAARK}{\*\bkmkend AAAAAAAARK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E35_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAARL}{\*\bkmkend AAAAAAAARL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E34_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAARM}{\*\bkmkend AAAAAAAARM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E34_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAARN}{\*\bkmkend AAAAAAAARN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E34_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAARO}{\*\bkmkend AAAAAAAARO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E33_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAARP}{\*\bkmkend AAAAAAAARP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E33_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAARQ}{\*\bkmkend AAAAAAAARQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E33_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAARR}{\*\bkmkend AAAAAAAARR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E32_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAARS}{\*\bkmkend AAAAAAAARS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E32_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAART}{\*\bkmkend AAAAAAAART} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_E32_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAARU}{\*\bkmkend AAAAAAAARU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMRH_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAARV}{\*\bkmkend AAAAAAAARV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E31_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x80000000u){\*\bkmkstart AAAAAAAARW}{\*\bkmkend AAAAAAAARW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E31_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAAARX}{\*\bkmkend AAAAAAAARX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E31_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAARY}{\*\bkmkend AAAAAAAARY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E30_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x40000000u){\*\bkmkstart AAAAAAAARZ}{\*\bkmkend AAAAAAAARZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E30_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Eu){\*\bkmkstart AAAAAAAASA}{\*\bkmkend AAAAAAAASA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E30_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAASB}{\*\bkmkend AAAAAAAASB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E29_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x20000000u){\*\bkmkstart AAAAAAAASC}{\*\bkmkend AAAAAAAASC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E29_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Du){\*\bkmkstart AAAAAAAASD}{\*\bkmkend AAAAAAAASD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E29_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAASE}{\*\bkmkend AAAAAAAASE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E28_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x10000000u){\*\bkmkstart AAAAAAAASF}{\*\bkmkend AAAAAAAASF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E28_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAAASG}{\*\bkmkend AAAAAAAASG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E28_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAASH}{\*\bkmkend AAAAAAAASH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E27_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x08000000u){\*\bkmkstart AAAAAAAASI}{\*\bkmkend AAAAAAAASI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E27_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Bu){\*\bkmkstart AAAAAAAASJ}{\*\bkmkend AAAAAAAASJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E27_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAASK}{\*\bkmkend AAAAAAAASK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E26_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x04000000u){\*\bkmkstart AAAAAAAASL}{\*\bkmkend AAAAAAAASL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E26_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Au){\*\bkmkstart AAAAAAAASM}{\*\bkmkend AAAAAAAASM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E26_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAASN}{\*\bkmkend AAAAAAAASN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E25_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x02000000u){\*\bkmkstart AAAAAAAASO}{\*\bkmkend AAAAAAAASO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E25_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000019u){\*\bkmkstart AAAAAAAASP}{\*\bkmkend AAAAAAAASP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E25_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAASQ}{\*\bkmkend AAAAAAAASQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E24_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x01000000u){\*\bkmkstart AAAAAAAASR}{\*\bkmkend AAAAAAAASR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E24_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAAASS}{\*\bkmkend AAAAAAAASS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E24_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAST}{\*\bkmkend AAAAAAAAST} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E23_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00800000u){\*\bkmkstart AAAAAAAASU}{\*\bkmkend AAAAAAAASU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E23_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000017u){\*\bkmkstart AAAAAAAASV}{\*\bkmkend AAAAAAAASV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E23_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAASW}{\*\bkmkend AAAAAAAASW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E22_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAAASX}{\*\bkmkend AAAAAAAASX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E22_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAAASY}{\*\bkmkend AAAAAAAASY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E22_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAASZ}{\*\bkmkend AAAAAAAASZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E21_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00200000u){\*\bkmkstart AAAAAAAATA}{\*\bkmkend AAAAAAAATA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E21_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAAATB}{\*\bkmkend AAAAAAAATB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E21_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAATC}{\*\bkmkend AAAAAAAATC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E20_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAAATD}{\*\bkmkend AAAAAAAATD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E20_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAAATE}{\*\bkmkend AAAAAAAATE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E20_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAATF}{\*\bkmkend AAAAAAAATF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E19_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00080000u){\*\bkmkstart AAAAAAAATG}{\*\bkmkend AAAAAAAATG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E19_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000013u){\*\bkmkstart AAAAAAAATH}{\*\bkmkend AAAAAAAATH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E19_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAATI}{\*\bkmkend AAAAAAAATI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E18_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00040000u){\*\bkmkstart AAAAAAAATJ}{\*\bkmkend AAAAAAAATJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E18_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000012u){\*\bkmkstart AAAAAAAATK}{\*\bkmkend AAAAAAAATK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E18_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAATL}{\*\bkmkend AAAAAAAATL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E17_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00020000u){\*\bkmkstart AAAAAAAATM}{\*\bkmkend AAAAAAAATM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E17_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000011u){\*\bkmkstart AAAAAAAATN}{\*\bkmkend AAAAAAAATN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E17_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAATO}{\*\bkmkend AAAAAAAATO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E16_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAAATP}{\*\bkmkend AAAAAAAATP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E16_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAATQ}{\*\bkmkend AAAAAAAATQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E16_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAATR}{\*\bkmkend AAAAAAAATR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E15_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00008000u){\*\bkmkstart AAAAAAAATS}{\*\bkmkend AAAAAAAATS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E15_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAAATT}{\*\bkmkend AAAAAAAATT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E15_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAATU}{\*\bkmkend AAAAAAAATU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E14_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00004000u){\*\bkmkstart AAAAAAAATV}{\*\bkmkend AAAAAAAATV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E14_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Eu){\*\bkmkstart AAAAAAAATW}{\*\bkmkend AAAAAAAATW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E14_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAATX}{\*\bkmkend AAAAAAAATX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E13_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00002000u){\*\bkmkstart AAAAAAAATY}{\*\bkmkend AAAAAAAATY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E13_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Du){\*\bkmkstart AAAAAAAATZ}{\*\bkmkend AAAAAAAATZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E13_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAUA}{\*\bkmkend AAAAAAAAUA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E12_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001000u){\*\bkmkstart AAAAAAAAUB}{\*\bkmkend AAAAAAAAUB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E12_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAAAUC}{\*\bkmkend AAAAAAAAUC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E12_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAUD}{\*\bkmkend AAAAAAAAUD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E11_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAAAUE}{\*\bkmkend AAAAAAAAUE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E11_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAAAUF}{\*\bkmkend AAAAAAAAUF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E11_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAUG}{\*\bkmkend AAAAAAAAUG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E10_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000400u){\*\bkmkstart AAAAAAAAUH}{\*\bkmkend AAAAAAAAUH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E10_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAAAUI}{\*\bkmkend AAAAAAAAUI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E10_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAUJ}{\*\bkmkend AAAAAAAAUJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E9_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000200u){\*\bkmkstart AAAAAAAAUK}{\*\bkmkend AAAAAAAAUK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E9_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAAAUL}{\*\bkmkend AAAAAAAAUL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E9_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAUM}{\*\bkmkend AAAAAAAAUM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E8_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAAAUN}{\*\bkmkend AAAAAAAAUN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E8_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAAUO}{\*\bkmkend AAAAAAAAUO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E8_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAUP}{\*\bkmkend AAAAAAAAUP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E7_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAAAUQ}{\*\bkmkend AAAAAAAAUQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E7_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAAUR}{\*\bkmkend AAAAAAAAUR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E7_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAUS}{\*\bkmkend AAAAAAAAUS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E6_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAAAUT}{\*\bkmkend AAAAAAAAUT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E6_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAAAUU}{\*\bkmkend AAAAAAAAUU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E6_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAUV}{\*\bkmkend AAAAAAAAUV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E5_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAAAUW}{\*\bkmkend AAAAAAAAUW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E5_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAAAUX}{\*\bkmkend AAAAAAAAUX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E5_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAUY}{\*\bkmkend AAAAAAAAUY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E4_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAAUZ}{\*\bkmkend AAAAAAAAUZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E4_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAAVA}{\*\bkmkend AAAAAAAAVA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E4_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAVB}{\*\bkmkend AAAAAAAAVB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E3_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAAVC}{\*\bkmkend AAAAAAAAVC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E3_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAAVD}{\*\bkmkend AAAAAAAAVD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E3_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAVE}{\*\bkmkend AAAAAAAAVE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E2_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAAVF}{\*\bkmkend AAAAAAAAVF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E2_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAAVG}{\*\bkmkend AAAAAAAAVG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E2_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAVH}{\*\bkmkend AAAAAAAAVH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E1_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAAVI}{\*\bkmkend AAAAAAAAVI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E1_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAAVJ}{\*\bkmkend AAAAAAAAVJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E1_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAVK}{\*\bkmkend AAAAAAAAVK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E0_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAAVL}{\*\bkmkend AAAAAAAAVL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E0_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAVM}{\*\bkmkend AAAAAAAAVM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_E0_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAVN}{\*\bkmkend AAAAAAAAVN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAVO}{\*\bkmkend AAAAAAAAVO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E63_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x80000000u){\*\bkmkstart AAAAAAAAVP}{\*\bkmkend AAAAAAAAVP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E63_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAAAVQ}{\*\bkmkend AAAAAAAAVQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E63_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAVR}{\*\bkmkend AAAAAAAAVR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E62_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x40000000u){\*\bkmkstart AAAAAAAAVS}{\*\bkmkend AAAAAAAAVS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E62_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Eu){\*\bkmkstart AAAAAAAAVT}{\*\bkmkend AAAAAAAAVT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E62_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAVU}{\*\bkmkend AAAAAAAAVU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E61_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x20000000u){\*\bkmkstart AAAAAAAAVV}{\*\bkmkend AAAAAAAAVV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E61_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Du){\*\bkmkstart AAAAAAAAVW}{\*\bkmkend AAAAAAAAVW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E61_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAVX}{\*\bkmkend AAAAAAAAVX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E60_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x10000000u){\*\bkmkstart AAAAAAAAVY}{\*\bkmkend AAAAAAAAVY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E60_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAAAVZ}{\*\bkmkend AAAAAAAAVZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E60_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAWA}{\*\bkmkend AAAAAAAAWA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E59_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x08000000u){\*\bkmkstart AAAAAAAAWB}{\*\bkmkend AAAAAAAAWB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E59_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Bu){\*\bkmkstart AAAAAAAAWC}{\*\bkmkend AAAAAAAAWC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E59_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAWD}{\*\bkmkend AAAAAAAAWD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E58_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x04000000u){\*\bkmkstart AAAAAAAAWE}{\*\bkmkend AAAAAAAAWE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E58_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Au){\*\bkmkstart AAAAAAAAWF}{\*\bkmkend AAAAAAAAWF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E58_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAWG}{\*\bkmkend AAAAAAAAWG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E57_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x02000000u){\*\bkmkstart AAAAAAAAWH}{\*\bkmkend AAAAAAAAWH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E57_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000019u){\*\bkmkstart AAAAAAAAWI}{\*\bkmkend AAAAAAAAWI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E57_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAWJ}{\*\bkmkend AAAAAAAAWJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E56_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x01000000u){\*\bkmkstart AAAAAAAAWK}{\*\bkmkend AAAAAAAAWK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E56_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAAAWL}{\*\bkmkend AAAAAAAAWL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E56_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAWM}{\*\bkmkend AAAAAAAAWM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E55_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00800000u){\*\bkmkstart AAAAAAAAWN}{\*\bkmkend AAAAAAAAWN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E55_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000017u){\*\bkmkstart AAAAAAAAWO}{\*\bkmkend AAAAAAAAWO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E55_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAWP}{\*\bkmkend AAAAAAAAWP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E54_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAAAWQ}{\*\bkmkend AAAAAAAAWQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E54_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAAAWR}{\*\bkmkend AAAAAAAAWR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E54_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAWS}{\*\bkmkend AAAAAAAAWS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E53_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00200000u){\*\bkmkstart AAAAAAAAWT}{\*\bkmkend AAAAAAAAWT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E53_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAAAWU}{\*\bkmkend AAAAAAAAWU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E53_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAWV}{\*\bkmkend AAAAAAAAWV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E52_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAAAWW}{\*\bkmkend AAAAAAAAWW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E52_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAAAWX}{\*\bkmkend AAAAAAAAWX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E52_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAWY}{\*\bkmkend AAAAAAAAWY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E51_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00080000u){\*\bkmkstart AAAAAAAAWZ}{\*\bkmkend AAAAAAAAWZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E51_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000013u){\*\bkmkstart AAAAAAAAXA}{\*\bkmkend AAAAAAAAXA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E51_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAXB}{\*\bkmkend AAAAAAAAXB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E50_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00040000u){\*\bkmkstart AAAAAAAAXC}{\*\bkmkend AAAAAAAAXC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E50_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000012u){\*\bkmkstart AAAAAAAAXD}{\*\bkmkend AAAAAAAAXD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E50_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAXE}{\*\bkmkend AAAAAAAAXE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E49_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00020000u){\*\bkmkstart AAAAAAAAXF}{\*\bkmkend AAAAAAAAXF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E49_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000011u){\*\bkmkstart AAAAAAAAXG}{\*\bkmkend AAAAAAAAXG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E49_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAXH}{\*\bkmkend AAAAAAAAXH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E48_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAAAXI}{\*\bkmkend AAAAAAAAXI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E48_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAAXJ}{\*\bkmkend AAAAAAAAXJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E48_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAXK}{\*\bkmkend AAAAAAAAXK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E47_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00008000u){\*\bkmkstart AAAAAAAAXL}{\*\bkmkend AAAAAAAAXL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E47_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAAAXM}{\*\bkmkend AAAAAAAAXM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E47_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAXN}{\*\bkmkend AAAAAAAAXN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E46_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00004000u){\*\bkmkstart AAAAAAAAXO}{\*\bkmkend AAAAAAAAXO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E46_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Eu){\*\bkmkstart AAAAAAAAXP}{\*\bkmkend AAAAAAAAXP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E46_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAXQ}{\*\bkmkend AAAAAAAAXQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E45_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00002000u){\*\bkmkstart AAAAAAAAXR}{\*\bkmkend AAAAAAAAXR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E45_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Du){\*\bkmkstart AAAAAAAAXS}{\*\bkmkend AAAAAAAAXS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E45_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAXT}{\*\bkmkend AAAAAAAAXT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E44_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001000u){\*\bkmkstart AAAAAAAAXU}{\*\bkmkend AAAAAAAAXU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E44_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAAAXV}{\*\bkmkend AAAAAAAAXV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E44_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAXW}{\*\bkmkend AAAAAAAAXW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E43_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAAAXX}{\*\bkmkend AAAAAAAAXX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E43_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAAAXY}{\*\bkmkend AAAAAAAAXY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E43_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAXZ}{\*\bkmkend AAAAAAAAXZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E42_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000400u){\*\bkmkstart AAAAAAAAYA}{\*\bkmkend AAAAAAAAYA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E42_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAAAYB}{\*\bkmkend AAAAAAAAYB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E42_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAYC}{\*\bkmkend AAAAAAAAYC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E41_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000200u){\*\bkmkstart AAAAAAAAYD}{\*\bkmkend AAAAAAAAYD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E41_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAAAYE}{\*\bkmkend AAAAAAAAYE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E41_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAYF}{\*\bkmkend AAAAAAAAYF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E40_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAAAYG}{\*\bkmkend AAAAAAAAYG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E40_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAAYH}{\*\bkmkend AAAAAAAAYH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E40_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAYI}{\*\bkmkend AAAAAAAAYI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E39_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAAAYJ}{\*\bkmkend AAAAAAAAYJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E39_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAAYK}{\*\bkmkend AAAAAAAAYK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E39_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAYL}{\*\bkmkend AAAAAAAAYL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E38_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAAAYM}{\*\bkmkend AAAAAAAAYM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E38_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAAAYN}{\*\bkmkend AAAAAAAAYN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E38_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAYO}{\*\bkmkend AAAAAAAAYO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E37_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAAAYP}{\*\bkmkend AAAAAAAAYP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E37_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAAAYQ}{\*\bkmkend AAAAAAAAYQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E37_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAYR}{\*\bkmkend AAAAAAAAYR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E36_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAAYS}{\*\bkmkend AAAAAAAAYS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E36_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAAYT}{\*\bkmkend AAAAAAAAYT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E36_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAYU}{\*\bkmkend AAAAAAAAYU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E35_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAAYV}{\*\bkmkend AAAAAAAAYV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E35_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAAYW}{\*\bkmkend AAAAAAAAYW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E35_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAYX}{\*\bkmkend AAAAAAAAYX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E34_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAAYY}{\*\bkmkend AAAAAAAAYY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E34_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAAYZ}{\*\bkmkend AAAAAAAAYZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E34_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAZA}{\*\bkmkend AAAAAAAAZA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E33_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAAZB}{\*\bkmkend AAAAAAAAZB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E33_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAAZC}{\*\bkmkend AAAAAAAAZC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E33_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAZD}{\*\bkmkend AAAAAAAAZD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E32_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAAZE}{\*\bkmkend AAAAAAAAZE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E32_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAZF}{\*\bkmkend AAAAAAAAZF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_E32_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAZG}{\*\bkmkend AAAAAAAAZG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EMCRH_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAZH}{\*\bkmkend AAAAAAAAZH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMR_E7_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAAAZI}{\*\bkmkend AAAAAAAAZI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMR_E7_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAAZJ}{\*\bkmkend AAAAAAAAZJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMR_E7_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAZK}{\*\bkmkend AAAAAAAAZK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMR_E6_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAAAZL}{\*\bkmkend AAAAAAAAZL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMR_E6_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAAAZM}{\*\bkmkend AAAAAAAAZM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMR_E6_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAZN}{\*\bkmkend AAAAAAAAZN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMR_E5_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAAAZO}{\*\bkmkend AAAAAAAAZO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMR_E5_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAAAZP}{\*\bkmkend AAAAAAAAZP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMR_E5_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAZQ}{\*\bkmkend AAAAAAAAZQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMR_E4_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAAZR}{\*\bkmkend AAAAAAAAZR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMR_E4_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAAZS}{\*\bkmkend AAAAAAAAZS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMR_E4_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAZT}{\*\bkmkend AAAAAAAAZT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMR_E3_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAAZU}{\*\bkmkend AAAAAAAAZU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMR_E3_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAAZV}{\*\bkmkend AAAAAAAAZV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMR_E3_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAZW}{\*\bkmkend AAAAAAAAZW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMR_E2_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAAZX}{\*\bkmkend AAAAAAAAZX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMR_E2_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAAZY}{\*\bkmkend AAAAAAAAZY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMR_E2_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAAZZ}{\*\bkmkend AAAAAAAAZZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMR_E1_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAABAA}{\*\bkmkend AAAAAAABAA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMR_E1_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABAB}{\*\bkmkend AAAAAAABAB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMR_E1_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABAC}{\*\bkmkend AAAAAAABAC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMR_E0_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABAD}{\*\bkmkend AAAAAAABAD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMR_E0_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABAE}{\*\bkmkend AAAAAAABAE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMR_E0_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABAF}{\*\bkmkend AAAAAAABAF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABAG}{\*\bkmkend AAAAAAABAG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMCR_E7_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAABAH}{\*\bkmkend AAAAAAABAH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMCR_E7_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAABAI}{\*\bkmkend AAAAAAABAI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMCR_E7_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABAJ}{\*\bkmkend AAAAAAABAJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMCR_E6_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAABAK}{\*\bkmkend AAAAAAABAK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMCR_E6_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAABAL}{\*\bkmkend AAAAAAABAL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMCR_E6_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABAM}{\*\bkmkend AAAAAAABAM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMCR_E5_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAABAN}{\*\bkmkend AAAAAAABAN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMCR_E5_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAABAO}{\*\bkmkend AAAAAAABAO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMCR_E5_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABAP}{\*\bkmkend AAAAAAABAP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMCR_E4_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAABAQ}{\*\bkmkend AAAAAAABAQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMCR_E4_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAABAR}{\*\bkmkend AAAAAAABAR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMCR_E4_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABAS}{\*\bkmkend AAAAAAABAS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMCR_E3_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAABAT}{\*\bkmkend AAAAAAABAT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMCR_E3_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAABAU}{\*\bkmkend AAAAAAABAU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMCR_E3_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABAV}{\*\bkmkend AAAAAAABAV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMCR_E2_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAABAW}{\*\bkmkend AAAAAAABAW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMCR_E2_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAABAX}{\*\bkmkend AAAAAAABAX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMCR_E2_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABAY}{\*\bkmkend AAAAAAABAY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMCR_E1_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAABAZ}{\*\bkmkend AAAAAAABAZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMCR_E1_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABBA}{\*\bkmkend AAAAAAABBA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMCR_E1_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABBB}{\*\bkmkend AAAAAAABBB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMCR_E0_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABBC}{\*\bkmkend AAAAAAABBC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMCR_E0_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABBD}{\*\bkmkend AAAAAAABBD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMCR_E0_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABBE}{\*\bkmkend AAAAAAABBE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEMCR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABBF}{\*\bkmkend AAAAAAABBF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERR_TCCERR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAABBG}{\*\bkmkend AAAAAAABBG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERR_TCCERR_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAABBH}{\*\bkmkend AAAAAAABBH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERR_TCCERR_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABBI}{\*\bkmkend AAAAAAABBI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERR_QTHRXCD7_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAABBJ}{\*\bkmkend AAAAAAABBJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERR_QTHRXCD7_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAABBK}{\*\bkmkend AAAAAAABBK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERR_QTHRXCD7_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABBL}{\*\bkmkend AAAAAAABBL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERR_QTHRXCD6_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAABBM}{\*\bkmkend AAAAAAABBM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERR_QTHRXCD6_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAABBN}{\*\bkmkend AAAAAAABBN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERR_QTHRXCD6_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABBO}{\*\bkmkend AAAAAAABBO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERR_QTHRXCD5_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAABBP}{\*\bkmkend AAAAAAABBP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERR_QTHRXCD5_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAABBQ}{\*\bkmkend AAAAAAABBQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERR_QTHRXCD5_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABBR}{\*\bkmkend AAAAAAABBR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERR_QTHRXCD4_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAABBS}{\*\bkmkend AAAAAAABBS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERR_QTHRXCD4_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAABBT}{\*\bkmkend AAAAAAABBT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERR_QTHRXCD4_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABBU}{\*\bkmkend AAAAAAABBU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERR_QTHRXCD3_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAABBV}{\*\bkmkend AAAAAAABBV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERR_QTHRXCD3_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAABBW}{\*\bkmkend AAAAAAABBW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERR_QTHRXCD3_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABBX}{\*\bkmkend AAAAAAABBX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERR_QTHRXCD2_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAABBY}{\*\bkmkend AAAAAAABBY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERR_QTHRXCD2_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAABBZ}{\*\bkmkend AAAAAAABBZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERR_QTHRXCD2_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABCA}{\*\bkmkend AAAAAAABCA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERR_QTHRXCD1_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAABCB}{\*\bkmkend AAAAAAABCB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERR_QTHRXCD1_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABCC}{\*\bkmkend AAAAAAABCC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERR_QTHRXCD1_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABCD}{\*\bkmkend AAAAAAABCD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERR_QTHRXCD0_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABCE}{\*\bkmkend AAAAAAABCE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERR_QTHRXCD0_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABCF}{\*\bkmkend AAAAAAABCF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERR_QTHRXCD0_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABCG}{\*\bkmkend AAAAAAABCG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABCH}{\*\bkmkend AAAAAAABCH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERRCLR_TCCERR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAABCI}{\*\bkmkend AAAAAAABCI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERRCLR_TCCERR_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAABCJ}{\*\bkmkend AAAAAAABCJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERRCLR_TCCERR_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABCK}{\*\bkmkend AAAAAAABCK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERRCLR_QTHRXCD7_MASK}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAABCL}{\*\bkmkend AAAAAAABCL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERRCLR_QTHRXCD7_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAABCM}{\*\bkmkend AAAAAAABCM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERRCLR_QTHRXCD7_RESETVAL}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABCN}{\*\bkmkend AAAAAAABCN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERRCLR_QTHRXCD6_MASK}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAABCO}{\*\bkmkend AAAAAAABCO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERRCLR_QTHRXCD6_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAABCP}{\*\bkmkend AAAAAAABCP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERRCLR_QTHRXCD6_RESETVAL}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABCQ}{\*\bkmkend AAAAAAABCQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERRCLR_QTHRXCD5_MASK}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAABCR}{\*\bkmkend AAAAAAABCR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERRCLR_QTHRXCD5_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAABCS}{\*\bkmkend AAAAAAABCS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERRCLR_QTHRXCD5_RESETVAL}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABCT}{\*\bkmkend AAAAAAABCT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERRCLR_QTHRXCD4_MASK}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAABCU}{\*\bkmkend AAAAAAABCU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERRCLR_QTHRXCD4_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAABCV}{\*\bkmkend AAAAAAABCV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERRCLR_QTHRXCD4_RESETVAL}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABCW}{\*\bkmkend AAAAAAABCW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERRCLR_QTHRXCD3_MASK}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAABCX}{\*\bkmkend AAAAAAABCX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERRCLR_QTHRXCD3_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAABCY}{\*\bkmkend AAAAAAABCY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERRCLR_QTHRXCD3_RESETVAL}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABCZ}{\*\bkmkend AAAAAAABCZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERRCLR_QTHRXCD2_MASK}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAABDA}{\*\bkmkend AAAAAAABDA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERRCLR_QTHRXCD2_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAABDB}{\*\bkmkend AAAAAAABDB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERRCLR_QTHRXCD2_RESETVAL}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABDC}{\*\bkmkend AAAAAAABDC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERRCLR_QTHRXCD1_MASK}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAABDD}{\*\bkmkend AAAAAAABDD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERRCLR_QTHRXCD1_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABDE}{\*\bkmkend AAAAAAABDE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERRCLR_QTHRXCD1_RESETVAL}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABDF}{\*\bkmkend AAAAAAABDF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERRCLR_QTHRXCD0_MASK}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABDG}{\*\bkmkend AAAAAAABDG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERRCLR_QTHRXCD0_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABDH}{\*\bkmkend AAAAAAABDH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERRCLR_QTHRXCD0_RESETVAL}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABDI}{\*\bkmkend AAAAAAABDI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCERRCLR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABDJ}{\*\bkmkend AAAAAAABDJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EEVAL_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAABDK}{\*\bkmkend AAAAAAABDK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EEVAL_SET_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABDL}{\*\bkmkend AAAAAAABDL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EEVAL_SET_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABDM}{\*\bkmkend AAAAAAABDM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EEVAL_SET_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABDN}{\*\bkmkend AAAAAAABDN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EEVAL_EVAL_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABDO}{\*\bkmkend AAAAAAABDO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EEVAL_EVAL_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABDP}{\*\bkmkend AAAAAAABDP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EEVAL_EVAL_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABDQ}{\*\bkmkend AAAAAAABDQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EEVAL_EVAL_EVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABDR}{\*\bkmkend AAAAAAABDR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EEVAL_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABDS}{\*\bkmkend AAAAAAABDS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E31_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x80000000u){\*\bkmkstart AAAAAAABDT}{\*\bkmkend AAAAAAABDT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E31_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAABDU}{\*\bkmkend AAAAAAABDU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E31_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABDV}{\*\bkmkend AAAAAAABDV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E30_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x40000000u){\*\bkmkstart AAAAAAABDW}{\*\bkmkend AAAAAAABDW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E30_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Eu){\*\bkmkstart AAAAAAABDX}{\*\bkmkend AAAAAAABDX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E30_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABDY}{\*\bkmkend AAAAAAABDY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E29_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x20000000u){\*\bkmkstart AAAAAAABDZ}{\*\bkmkend AAAAAAABDZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E29_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Du){\*\bkmkstart AAAAAAABEA}{\*\bkmkend AAAAAAABEA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E29_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABEB}{\*\bkmkend AAAAAAABEB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E28_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x10000000u){\*\bkmkstart AAAAAAABEC}{\*\bkmkend AAAAAAABEC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E28_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAABED}{\*\bkmkend AAAAAAABED} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E28_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABEE}{\*\bkmkend AAAAAAABEE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E27_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x08000000u){\*\bkmkstart AAAAAAABEF}{\*\bkmkend AAAAAAABEF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E27_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Bu){\*\bkmkstart AAAAAAABEG}{\*\bkmkend AAAAAAABEG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E27_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABEH}{\*\bkmkend AAAAAAABEH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E26_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x04000000u){\*\bkmkstart AAAAAAABEI}{\*\bkmkend AAAAAAABEI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E26_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Au){\*\bkmkstart AAAAAAABEJ}{\*\bkmkend AAAAAAABEJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E26_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABEK}{\*\bkmkend AAAAAAABEK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E25_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x02000000u){\*\bkmkstart AAAAAAABEL}{\*\bkmkend AAAAAAABEL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E25_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000019u){\*\bkmkstart AAAAAAABEM}{\*\bkmkend AAAAAAABEM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E25_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABEN}{\*\bkmkend AAAAAAABEN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E24_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x01000000u){\*\bkmkstart AAAAAAABEO}{\*\bkmkend AAAAAAABEO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E24_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAABEP}{\*\bkmkend AAAAAAABEP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E24_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABEQ}{\*\bkmkend AAAAAAABEQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E23_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00800000u){\*\bkmkstart AAAAAAABER}{\*\bkmkend AAAAAAABER} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E23_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000017u){\*\bkmkstart AAAAAAABES}{\*\bkmkend AAAAAAABES} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E23_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABET}{\*\bkmkend AAAAAAABET} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E22_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAABEU}{\*\bkmkend AAAAAAABEU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E22_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAABEV}{\*\bkmkend AAAAAAABEV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E22_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABEW}{\*\bkmkend AAAAAAABEW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E21_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00200000u){\*\bkmkstart AAAAAAABEX}{\*\bkmkend AAAAAAABEX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E21_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAABEY}{\*\bkmkend AAAAAAABEY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E21_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABEZ}{\*\bkmkend AAAAAAABEZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E20_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAABFA}{\*\bkmkend AAAAAAABFA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E20_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAABFB}{\*\bkmkend AAAAAAABFB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E20_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABFC}{\*\bkmkend AAAAAAABFC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E19_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00080000u){\*\bkmkstart AAAAAAABFD}{\*\bkmkend AAAAAAABFD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E19_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000013u){\*\bkmkstart AAAAAAABFE}{\*\bkmkend AAAAAAABFE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E19_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABFF}{\*\bkmkend AAAAAAABFF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E18_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00040000u){\*\bkmkstart AAAAAAABFG}{\*\bkmkend AAAAAAABFG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E18_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000012u){\*\bkmkstart AAAAAAABFH}{\*\bkmkend AAAAAAABFH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E18_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABFI}{\*\bkmkend AAAAAAABFI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E17_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00020000u){\*\bkmkstart AAAAAAABFJ}{\*\bkmkend AAAAAAABFJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E17_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000011u){\*\bkmkstart AAAAAAABFK}{\*\bkmkend AAAAAAABFK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E17_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABFL}{\*\bkmkend AAAAAAABFL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E16_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAABFM}{\*\bkmkend AAAAAAABFM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E16_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAABFN}{\*\bkmkend AAAAAAABFN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E16_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABFO}{\*\bkmkend AAAAAAABFO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E15_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00008000u){\*\bkmkstart AAAAAAABFP}{\*\bkmkend AAAAAAABFP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E15_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAABFQ}{\*\bkmkend AAAAAAABFQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E15_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABFR}{\*\bkmkend AAAAAAABFR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E14_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00004000u){\*\bkmkstart AAAAAAABFS}{\*\bkmkend AAAAAAABFS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E14_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Eu){\*\bkmkstart AAAAAAABFT}{\*\bkmkend AAAAAAABFT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E14_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABFU}{\*\bkmkend AAAAAAABFU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E13_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00002000u){\*\bkmkstart AAAAAAABFV}{\*\bkmkend AAAAAAABFV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E13_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Du){\*\bkmkstart AAAAAAABFW}{\*\bkmkend AAAAAAABFW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E13_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABFX}{\*\bkmkend AAAAAAABFX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E12_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001000u){\*\bkmkstart AAAAAAABFY}{\*\bkmkend AAAAAAABFY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E12_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAABFZ}{\*\bkmkend AAAAAAABFZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E12_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABGA}{\*\bkmkend AAAAAAABGA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E11_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAABGB}{\*\bkmkend AAAAAAABGB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E11_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAABGC}{\*\bkmkend AAAAAAABGC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E11_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABGD}{\*\bkmkend AAAAAAABGD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E10_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000400u){\*\bkmkstart AAAAAAABGE}{\*\bkmkend AAAAAAABGE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E10_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAABGF}{\*\bkmkend AAAAAAABGF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E10_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABGG}{\*\bkmkend AAAAAAABGG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E9_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000200u){\*\bkmkstart AAAAAAABGH}{\*\bkmkend AAAAAAABGH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E9_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAABGI}{\*\bkmkend AAAAAAABGI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E9_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABGJ}{\*\bkmkend AAAAAAABGJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E8_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAABGK}{\*\bkmkend AAAAAAABGK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E8_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAABGL}{\*\bkmkend AAAAAAABGL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E8_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABGM}{\*\bkmkend AAAAAAABGM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E7_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAABGN}{\*\bkmkend AAAAAAABGN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E7_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAABGO}{\*\bkmkend AAAAAAABGO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E7_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABGP}{\*\bkmkend AAAAAAABGP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E6_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAABGQ}{\*\bkmkend AAAAAAABGQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E6_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAABGR}{\*\bkmkend AAAAAAABGR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E6_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABGS}{\*\bkmkend AAAAAAABGS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E5_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAABGT}{\*\bkmkend AAAAAAABGT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E5_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAABGU}{\*\bkmkend AAAAAAABGU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E5_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABGV}{\*\bkmkend AAAAAAABGV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E4_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAABGW}{\*\bkmkend AAAAAAABGW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E4_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAABGX}{\*\bkmkend AAAAAAABGX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E4_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABGY}{\*\bkmkend AAAAAAABGY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E3_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAABGZ}{\*\bkmkend AAAAAAABGZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E3_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAABHA}{\*\bkmkend AAAAAAABHA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E3_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABHB}{\*\bkmkend AAAAAAABHB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E2_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAABHC}{\*\bkmkend AAAAAAABHC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E2_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAABHD}{\*\bkmkend AAAAAAABHD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E2_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABHE}{\*\bkmkend AAAAAAABHE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E1_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAABHF}{\*\bkmkend AAAAAAABHF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E1_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABHG}{\*\bkmkend AAAAAAABHG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E1_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABHH}{\*\bkmkend AAAAAAABHH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E0_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABHI}{\*\bkmkend AAAAAAABHI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E0_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABHJ}{\*\bkmkend AAAAAAABHJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_E0_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABHK}{\*\bkmkend AAAAAAABHK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAE_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABHL}{\*\bkmkend AAAAAAABHL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E63_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x80000000u){\*\bkmkstart AAAAAAABHM}{\*\bkmkend AAAAAAABHM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E63_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAABHN}{\*\bkmkend AAAAAAABHN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E63_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABHO}{\*\bkmkend AAAAAAABHO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E62_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x40000000u){\*\bkmkstart AAAAAAABHP}{\*\bkmkend AAAAAAABHP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E62_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Eu){\*\bkmkstart AAAAAAABHQ}{\*\bkmkend AAAAAAABHQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E62_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABHR}{\*\bkmkend AAAAAAABHR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E61_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x20000000u){\*\bkmkstart AAAAAAABHS}{\*\bkmkend AAAAAAABHS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E61_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Du){\*\bkmkstart AAAAAAABHT}{\*\bkmkend AAAAAAABHT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E61_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABHU}{\*\bkmkend AAAAAAABHU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E60_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x10000000u){\*\bkmkstart AAAAAAABHV}{\*\bkmkend AAAAAAABHV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E60_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAABHW}{\*\bkmkend AAAAAAABHW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E60_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABHX}{\*\bkmkend AAAAAAABHX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E59_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x08000000u){\*\bkmkstart AAAAAAABHY}{\*\bkmkend AAAAAAABHY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E59_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Bu){\*\bkmkstart AAAAAAABHZ}{\*\bkmkend AAAAAAABHZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E59_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABIA}{\*\bkmkend AAAAAAABIA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E58_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x04000000u){\*\bkmkstart AAAAAAABIB}{\*\bkmkend AAAAAAABIB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E58_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Au){\*\bkmkstart AAAAAAABIC}{\*\bkmkend AAAAAAABIC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E58_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABID}{\*\bkmkend AAAAAAABID} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E57_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x02000000u){\*\bkmkstart AAAAAAABIE}{\*\bkmkend AAAAAAABIE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E57_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000019u){\*\bkmkstart AAAAAAABIF}{\*\bkmkend AAAAAAABIF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E57_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABIG}{\*\bkmkend AAAAAAABIG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E56_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x01000000u){\*\bkmkstart AAAAAAABIH}{\*\bkmkend AAAAAAABIH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E56_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAABII}{\*\bkmkend AAAAAAABII} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E56_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABIJ}{\*\bkmkend AAAAAAABIJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E55_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00800000u){\*\bkmkstart AAAAAAABIK}{\*\bkmkend AAAAAAABIK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E55_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000017u){\*\bkmkstart AAAAAAABIL}{\*\bkmkend AAAAAAABIL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E55_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABIM}{\*\bkmkend AAAAAAABIM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E54_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAABIN}{\*\bkmkend AAAAAAABIN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E54_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAABIO}{\*\bkmkend AAAAAAABIO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E54_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABIP}{\*\bkmkend AAAAAAABIP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E53_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00200000u){\*\bkmkstart AAAAAAABIQ}{\*\bkmkend AAAAAAABIQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E53_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAABIR}{\*\bkmkend AAAAAAABIR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E53_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABIS}{\*\bkmkend AAAAAAABIS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E52_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAABIT}{\*\bkmkend AAAAAAABIT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E52_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAABIU}{\*\bkmkend AAAAAAABIU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E52_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABIV}{\*\bkmkend AAAAAAABIV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E51_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00080000u){\*\bkmkstart AAAAAAABIW}{\*\bkmkend AAAAAAABIW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E51_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000013u){\*\bkmkstart AAAAAAABIX}{\*\bkmkend AAAAAAABIX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E51_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABIY}{\*\bkmkend AAAAAAABIY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E50_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00040000u){\*\bkmkstart AAAAAAABIZ}{\*\bkmkend AAAAAAABIZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E50_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000012u){\*\bkmkstart AAAAAAABJA}{\*\bkmkend AAAAAAABJA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E50_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABJB}{\*\bkmkend AAAAAAABJB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E49_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00020000u){\*\bkmkstart AAAAAAABJC}{\*\bkmkend AAAAAAABJC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E49_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000011u){\*\bkmkstart AAAAAAABJD}{\*\bkmkend AAAAAAABJD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E49_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABJE}{\*\bkmkend AAAAAAABJE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E48_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAABJF}{\*\bkmkend AAAAAAABJF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E48_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAABJG}{\*\bkmkend AAAAAAABJG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E48_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABJH}{\*\bkmkend AAAAAAABJH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E47_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00008000u){\*\bkmkstart AAAAAAABJI}{\*\bkmkend AAAAAAABJI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E47_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAABJJ}{\*\bkmkend AAAAAAABJJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E47_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABJK}{\*\bkmkend AAAAAAABJK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E46_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00004000u){\*\bkmkstart AAAAAAABJL}{\*\bkmkend AAAAAAABJL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E46_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Eu){\*\bkmkstart AAAAAAABJM}{\*\bkmkend AAAAAAABJM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E46_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABJN}{\*\bkmkend AAAAAAABJN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E45_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00002000u){\*\bkmkstart AAAAAAABJO}{\*\bkmkend AAAAAAABJO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E45_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Du){\*\bkmkstart AAAAAAABJP}{\*\bkmkend AAAAAAABJP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E45_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABJQ}{\*\bkmkend AAAAAAABJQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E44_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001000u){\*\bkmkstart AAAAAAABJR}{\*\bkmkend AAAAAAABJR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E44_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAABJS}{\*\bkmkend AAAAAAABJS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E44_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABJT}{\*\bkmkend AAAAAAABJT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E43_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAABJU}{\*\bkmkend AAAAAAABJU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E43_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAABJV}{\*\bkmkend AAAAAAABJV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E43_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABJW}{\*\bkmkend AAAAAAABJW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E42_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000400u){\*\bkmkstart AAAAAAABJX}{\*\bkmkend AAAAAAABJX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E42_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAABJY}{\*\bkmkend AAAAAAABJY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E42_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABJZ}{\*\bkmkend AAAAAAABJZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E41_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000200u){\*\bkmkstart AAAAAAABKA}{\*\bkmkend AAAAAAABKA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E41_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAABKB}{\*\bkmkend AAAAAAABKB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E41_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABKC}{\*\bkmkend AAAAAAABKC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E40_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAABKD}{\*\bkmkend AAAAAAABKD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E40_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAABKE}{\*\bkmkend AAAAAAABKE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E40_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABKF}{\*\bkmkend AAAAAAABKF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E39_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAABKG}{\*\bkmkend AAAAAAABKG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E39_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAABKH}{\*\bkmkend AAAAAAABKH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E39_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABKI}{\*\bkmkend AAAAAAABKI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E38_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAABKJ}{\*\bkmkend AAAAAAABKJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E38_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAABKK}{\*\bkmkend AAAAAAABKK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E38_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABKL}{\*\bkmkend AAAAAAABKL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E37_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAABKM}{\*\bkmkend AAAAAAABKM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E37_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAABKN}{\*\bkmkend AAAAAAABKN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E37_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABKO}{\*\bkmkend AAAAAAABKO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E36_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAABKP}{\*\bkmkend AAAAAAABKP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E36_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAABKQ}{\*\bkmkend AAAAAAABKQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E36_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABKR}{\*\bkmkend AAAAAAABKR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E35_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAABKS}{\*\bkmkend AAAAAAABKS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E35_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAABKT}{\*\bkmkend AAAAAAABKT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E35_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABKU}{\*\bkmkend AAAAAAABKU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E34_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAABKV}{\*\bkmkend AAAAAAABKV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E34_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAABKW}{\*\bkmkend AAAAAAABKW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E34_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABKX}{\*\bkmkend AAAAAAABKX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E33_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAABKY}{\*\bkmkend AAAAAAABKY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E33_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABKZ}{\*\bkmkend AAAAAAABKZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E33_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABLA}{\*\bkmkend AAAAAAABLA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E32_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABLB}{\*\bkmkend AAAAAAABLB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E32_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABLC}{\*\bkmkend AAAAAAABLC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_E32_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABLD}{\*\bkmkend AAAAAAABLD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DRAEH_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABLE}{\*\bkmkend AAAAAAABLE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QRAE_E7_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAABLF}{\*\bkmkend AAAAAAABLF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QRAE_E7_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAABLG}{\*\bkmkend AAAAAAABLG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QRAE_E7_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABLH}{\*\bkmkend AAAAAAABLH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QRAE_E6_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAABLI}{\*\bkmkend AAAAAAABLI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QRAE_E6_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAABLJ}{\*\bkmkend AAAAAAABLJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QRAE_E6_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABLK}{\*\bkmkend AAAAAAABLK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QRAE_E5_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAABLL}{\*\bkmkend AAAAAAABLL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QRAE_E5_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAABLM}{\*\bkmkend AAAAAAABLM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QRAE_E5_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABLN}{\*\bkmkend AAAAAAABLN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QRAE_E4_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAABLO}{\*\bkmkend AAAAAAABLO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QRAE_E4_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAABLP}{\*\bkmkend AAAAAAABLP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QRAE_E4_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABLQ}{\*\bkmkend AAAAAAABLQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QRAE_E3_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAABLR}{\*\bkmkend AAAAAAABLR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QRAE_E3_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAABLS}{\*\bkmkend AAAAAAABLS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QRAE_E3_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABLT}{\*\bkmkend AAAAAAABLT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QRAE_E2_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAABLU}{\*\bkmkend AAAAAAABLU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QRAE_E2_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAABLV}{\*\bkmkend AAAAAAABLV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QRAE_E2_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABLW}{\*\bkmkend AAAAAAABLW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QRAE_E1_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAABLX}{\*\bkmkend AAAAAAABLX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QRAE_E1_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAABLY}{\*\bkmkend AAAAAAABLY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QRAE_E1_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABLZ}{\*\bkmkend AAAAAAABLZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QRAE_E0_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAABMA}{\*\bkmkend AAAAAAABMA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QRAE_E0_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAABMB}{\*\bkmkend AAAAAAABMB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QRAE_E0_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABMC}{\*\bkmkend AAAAAAABMC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QRAE_RESERVED_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000007Fu){\*\bkmkstart AAAAAAABMD}{\*\bkmkend AAAAAAABMD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QRAE_RESERVED_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABME}{\*\bkmkend AAAAAAABME} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QRAE_RESERVED_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABMF}{\*\bkmkend AAAAAAABMF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QRAE_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABMG}{\*\bkmkend AAAAAAABMG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUEEVT_ENTRY_RESV_MASK}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFF00u){\*\bkmkstart AAAAAAABMH}{\*\bkmkend AAAAAAABMH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUEEVT_ENTRY_RESV_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAABMI}{\*\bkmkend AAAAAAABMI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUEEVT_ENTRY_RESV_RESETVAL}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABMJ}{\*\bkmkend AAAAAAABMJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUEEVT_ENTRY_EVT_SRC_MASK}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x000000C0u){\*\bkmkstart AAAAAAABMK}{\*\bkmkend AAAAAAABMK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUEEVT_ENTRY_EVT_SRC_SHIFT}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAABML}{\*\bkmkend AAAAAAABML} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUEEVT_ENTRY_EVT_SRC_RESETVAL}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABMM}{\*\bkmkend AAAAAAABMM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUEEVT_ENTRY_EVT_MASK}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x0000003Fu){\*\bkmkstart AAAAAAABMN}{\*\bkmkend AAAAAAABMN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUEEVT_ENTRY_EVT_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABMO}{\*\bkmkend AAAAAAABMO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUEEVT_ENTRY_EVT_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABMP}{\*\bkmkend AAAAAAABMP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QUEEVT_ENTRY_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABMQ}{\*\bkmkend AAAAAAABMQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSTAT_THRXD_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x01000000u){\*\bkmkstart AAAAAAABMR}{\*\bkmkend AAAAAAABMR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSTAT_THRXD_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAABMS}{\*\bkmkend AAAAAAABMS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSTAT_THRXD_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABMT}{\*\bkmkend AAAAAAABMT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSTAT_RESERVED_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00600000u){\*\bkmkstart AAAAAAABMU}{\*\bkmkend AAAAAAABMU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSTAT_RESERVED_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAABMV}{\*\bkmkend AAAAAAABMV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSTAT_RESERVED_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABMW}{\*\bkmkend AAAAAAABMW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSTAT_WM_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x001F0000u){\*\bkmkstart AAAAAAABMX}{\*\bkmkend AAAAAAABMX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSTAT_WM_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAABMY}{\*\bkmkend AAAAAAABMY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSTAT_WM_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABMZ}{\*\bkmkend AAAAAAABMZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSTAT_NUMVAL_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001F00u){\*\bkmkstart AAAAAAABNA}{\*\bkmkend AAAAAAABNA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSTAT_NUMVAL_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAABNB}{\*\bkmkend AAAAAAABNB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSTAT_NUMVAL_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABNC}{\*\bkmkend AAAAAAABNC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSTAT_STRTPTR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAABND}{\*\bkmkend AAAAAAABND} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSTAT_STRTPTR_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABNE}{\*\bkmkend AAAAAAABNE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSTAT_STRTPTR_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABNF}{\*\bkmkend AAAAAAABNF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSTAT_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABNG}{\*\bkmkend AAAAAAABNG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QWMTHRA_Q3_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x1F000000u){\*\bkmkstart AAAAAAABNH}{\*\bkmkend AAAAAAABNH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QWMTHRA_Q3_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAABNI}{\*\bkmkend AAAAAAABNI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QWMTHRA_Q3_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAABNJ}{\*\bkmkend AAAAAAABNJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QWMTHRA_Q2_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x001F0000u){\*\bkmkstart AAAAAAABNK}{\*\bkmkend AAAAAAABNK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QWMTHRA_Q2_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAABNL}{\*\bkmkend AAAAAAABNL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QWMTHRA_Q2_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAABNM}{\*\bkmkend AAAAAAABNM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QWMTHRA_Q1_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001F00u){\*\bkmkstart AAAAAAABNN}{\*\bkmkend AAAAAAABNN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QWMTHRA_Q1_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAABNO}{\*\bkmkend AAAAAAABNO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QWMTHRA_Q1_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAABNP}{\*\bkmkend AAAAAAABNP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QWMTHRA_Q0_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAABNQ}{\*\bkmkend AAAAAAABNQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QWMTHRA_Q0_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABNR}{\*\bkmkend AAAAAAABNR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QWMTHRA_Q0_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAABNS}{\*\bkmkend AAAAAAABNS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QWMTHRA_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x10101010u){\*\bkmkstart AAAAAAABNT}{\*\bkmkend AAAAAAABNT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QWMTHRB_Q7_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x1F000000u){\*\bkmkstart AAAAAAABNU}{\*\bkmkend AAAAAAABNU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QWMTHRB_Q7_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAABNV}{\*\bkmkend AAAAAAABNV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QWMTHRB_Q7_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAABNW}{\*\bkmkend AAAAAAABNW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QWMTHRB_Q6_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x001F0000u){\*\bkmkstart AAAAAAABNX}{\*\bkmkend AAAAAAABNX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QWMTHRB_Q6_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAABNY}{\*\bkmkend AAAAAAABNY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QWMTHRB_Q6_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAABNZ}{\*\bkmkend AAAAAAABNZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QWMTHRB_Q5_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001F00u){\*\bkmkstart AAAAAAABOA}{\*\bkmkend AAAAAAABOA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QWMTHRB_Q5_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAABOB}{\*\bkmkend AAAAAAABOB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QWMTHRB_Q5_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAABOC}{\*\bkmkend AAAAAAABOC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QWMTHRB_Q4_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAABOD}{\*\bkmkend AAAAAAABOD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QWMTHRB_Q4_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABOE}{\*\bkmkend AAAAAAABOE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QWMTHRB_Q4_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAABOF}{\*\bkmkend AAAAAAABOF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QWMTHRB_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x10101010u){\*\bkmkstart AAAAAAABOG}{\*\bkmkend AAAAAAABOG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV7_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00800000u){\*\bkmkstart AAAAAAABOH}{\*\bkmkend AAAAAAABOH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV7_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000017u){\*\bkmkstart AAAAAAABOI}{\*\bkmkend AAAAAAABOI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV7_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABOJ}{\*\bkmkend AAAAAAABOJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV7_NONE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABOK}{\*\bkmkend AAAAAAABOK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV7_ACTIVE}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABOL}{\*\bkmkend AAAAAAABOL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV6_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAABOM}{\*\bkmkend AAAAAAABOM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV6_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAABON}{\*\bkmkend AAAAAAABON} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV6_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABOO}{\*\bkmkend AAAAAAABOO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV6_NONE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABOP}{\*\bkmkend AAAAAAABOP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV6_ACTIVE}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABOQ}{\*\bkmkend AAAAAAABOQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV5_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00200000u){\*\bkmkstart AAAAAAABOR}{\*\bkmkend AAAAAAABOR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV5_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAABOS}{\*\bkmkend AAAAAAABOS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV5_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABOT}{\*\bkmkend AAAAAAABOT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV5_NONE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABOU}{\*\bkmkend AAAAAAABOU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV5_ACTIVE}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABOV}{\*\bkmkend AAAAAAABOV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV4_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAABOW}{\*\bkmkend AAAAAAABOW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV4_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAABOX}{\*\bkmkend AAAAAAABOX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV4_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABOY}{\*\bkmkend AAAAAAABOY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV4_NONE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABOZ}{\*\bkmkend AAAAAAABOZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV4_ACTIVE}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABPA}{\*\bkmkend AAAAAAABPA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV3_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00080000u){\*\bkmkstart AAAAAAABPB}{\*\bkmkend AAAAAAABPB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV3_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000013u){\*\bkmkstart AAAAAAABPC}{\*\bkmkend AAAAAAABPC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV3_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABPD}{\*\bkmkend AAAAAAABPD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV3_NONE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABPE}{\*\bkmkend AAAAAAABPE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV3_ACTIVE}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABPF}{\*\bkmkend AAAAAAABPF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV2_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00040000u){\*\bkmkstart AAAAAAABPG}{\*\bkmkend AAAAAAABPG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV2_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000012u){\*\bkmkstart AAAAAAABPH}{\*\bkmkend AAAAAAABPH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV2_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABPI}{\*\bkmkend AAAAAAABPI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV2_NONE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABPJ}{\*\bkmkend AAAAAAABPJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV2_ACTIVE}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABPK}{\*\bkmkend AAAAAAABPK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV1_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00020000u){\*\bkmkstart AAAAAAABPL}{\*\bkmkend AAAAAAABPL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV1_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000011u){\*\bkmkstart AAAAAAABPM}{\*\bkmkend AAAAAAABPM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV1_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABPN}{\*\bkmkend AAAAAAABPN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV1_NONE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABPO}{\*\bkmkend AAAAAAABPO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV1_ACTIVE}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABPP}{\*\bkmkend AAAAAAABPP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV0_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAABPQ}{\*\bkmkend AAAAAAABPQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV0_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAABPR}{\*\bkmkend AAAAAAABPR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV0_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABPS}{\*\bkmkend AAAAAAABPS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV0_NONE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABPT}{\*\bkmkend AAAAAAABPT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QUEACTV0_ACTIVE}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABPU}{\*\bkmkend AAAAAAABPU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_COMPACT_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00003F00u){\*\bkmkstart AAAAAAABPV}{\*\bkmkend AAAAAAABPV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_COMPACT_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAABPW}{\*\bkmkend AAAAAAABPW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_COMPACT_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABPX}{\*\bkmkend AAAAAAABPX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_COMPACT_NONE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABPY}{\*\bkmkend AAAAAAABPY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_ACTV_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAABPZ}{\*\bkmkend AAAAAAABPZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_ACTV_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAABQA}{\*\bkmkend AAAAAAABQA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_ACTV_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABQB}{\*\bkmkend AAAAAAABQB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_ACTV_IDLE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABQC}{\*\bkmkend AAAAAAABQC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_ACTV_BUSY}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABQD}{\*\bkmkend AAAAAAABQD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_TRACTV_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAABQE}{\*\bkmkend AAAAAAABQE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_TRACTV_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAABQF}{\*\bkmkend AAAAAAABQF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_TRACTV_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABQG}{\*\bkmkend AAAAAAABQG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_TRACTV_NONE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABQH}{\*\bkmkend AAAAAAABQH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_TRACTV_ACTIVE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABQI}{\*\bkmkend AAAAAAABQI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QEVTACTV_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAABQJ}{\*\bkmkend AAAAAAABQJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QEVTACTV_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABQK}{\*\bkmkend AAAAAAABQK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QEVTACTV_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABQL}{\*\bkmkend AAAAAAABQL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QEVTACTV_NONE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABQM}{\*\bkmkend AAAAAAABQM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_QEVTACTV_ACTIVE}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABQN}{\*\bkmkend AAAAAAABQN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_EVTACTV_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABQO}{\*\bkmkend AAAAAAABQO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_EVTACTV_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABQP}{\*\bkmkend AAAAAAABQP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_EVTACTV_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABQQ}{\*\bkmkend AAAAAAABQQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_EVTACTV_NONE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABQR}{\*\bkmkend AAAAAAABQR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_EVTACTV_ACTIVE}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABQS}{\*\bkmkend AAAAAAABQS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCSTAT_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABQT}{\*\bkmkend AAAAAAABQT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_AETCTL_EN_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x80000000u){\*\bkmkstart AAAAAAABQU}{\*\bkmkend AAAAAAABQU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_AETCTL_EN_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAABQV}{\*\bkmkend AAAAAAABQV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_AETCTL_EN_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABQW}{\*\bkmkend AAAAAAABQW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_AETCTL_EN_DISABLE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABQX}{\*\bkmkend AAAAAAABQX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_AETCTL_EN_ENABLE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABQY}{\*\bkmkend AAAAAAABQY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_AETCTL_ENDINT_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00003F00u){\*\bkmkstart AAAAAAABQZ}{\*\bkmkend AAAAAAABQZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_AETCTL_ENDINT_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAABRA}{\*\bkmkend AAAAAAABRA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_AETCTL_ENDINT_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABRB}{\*\bkmkend AAAAAAABRB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_AETCTL_TYPE_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAABRC}{\*\bkmkend AAAAAAABRC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_AETCTL_TYPE_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAABRD}{\*\bkmkend AAAAAAABRD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_AETCTL_TYPE_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABRE}{\*\bkmkend AAAAAAABRE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_AETCTL_TYPE_DMA}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABRF}{\*\bkmkend AAAAAAABRF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_AETCTL_TYPE_QDMA}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABRG}{\*\bkmkend AAAAAAABRG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_AETCTL_STRTEVT_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000003Fu){\*\bkmkstart AAAAAAABRH}{\*\bkmkend AAAAAAABRH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_AETCTL_STRTEVT_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABRI}{\*\bkmkend AAAAAAABRI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_AETCTL_STRTEVT_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABRJ}{\*\bkmkend AAAAAAABRJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_AETCTL_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABRK}{\*\bkmkend AAAAAAABRK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_AETSTAT_STAT_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABRL}{\*\bkmkend AAAAAAABRL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_AETSTAT_STAT_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABRM}{\*\bkmkend AAAAAAABRM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_AETSTAT_STAT_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABRN}{\*\bkmkend AAAAAAABRN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_AETSTAT_STAT_LOW}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABRO}{\*\bkmkend AAAAAAABRO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_AETSTAT_STAT_HIGH}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABRP}{\*\bkmkend AAAAAAABRP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_AETSTAT_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABRQ}{\*\bkmkend AAAAAAABRQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_AETCMD_CLR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABRR}{\*\bkmkend AAAAAAABRR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_AETCMD_CLR_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABRS}{\*\bkmkend AAAAAAABRS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_AETCMD_CLR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABRT}{\*\bkmkend AAAAAAABRT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_AETCMD_CLR_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABRU}{\*\bkmkend AAAAAAABRU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_AETCMD_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABRV}{\*\bkmkend AAAAAAABRV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPFAR_FADDR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAABRW}{\*\bkmkend AAAAAAABRW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPFAR_FADDR_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABRX}{\*\bkmkend AAAAAAABRX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPFAR_FADDR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABRY}{\*\bkmkend AAAAAAABRY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPFAR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABRZ}{\*\bkmkend AAAAAAABRZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPFSR_FID_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001E00u){\*\bkmkstart AAAAAAABSA}{\*\bkmkend AAAAAAABSA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPFSR_FID_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAABSB}{\*\bkmkend AAAAAAABSB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPFSR_FID_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAABSC}{\*\bkmkend AAAAAAABSC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPFSR_SECE_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAABSD}{\*\bkmkend AAAAAAABSD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPFSR_SECE_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAABSE}{\*\bkmkend AAAAAAABSE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPFSR_SECE_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABSF}{\*\bkmkend AAAAAAABSF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPFSR_SRE_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAABSG}{\*\bkmkend AAAAAAABSG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPFSR_SRE_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAABSH}{\*\bkmkend AAAAAAABSH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPFSR_SRE_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABSI}{\*\bkmkend AAAAAAABSI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPFSR_SWE_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAABSJ}{\*\bkmkend AAAAAAABSJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPFSR_SWE_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAABSK}{\*\bkmkend AAAAAAABSK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPFSR_SWE_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABSL}{\*\bkmkend AAAAAAABSL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPFSR_SXE_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAABSM}{\*\bkmkend AAAAAAABSM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPFSR_SXE_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAABSN}{\*\bkmkend AAAAAAABSN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPFSR_SXE_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABSO}{\*\bkmkend AAAAAAABSO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPFSR_URE_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAABSP}{\*\bkmkend AAAAAAABSP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPFSR_URE_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAABSQ}{\*\bkmkend AAAAAAABSQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPFSR_URE_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABSR}{\*\bkmkend AAAAAAABSR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPFSR_UWE_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAABSS}{\*\bkmkend AAAAAAABSS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPFSR_UWE_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABST}{\*\bkmkend AAAAAAABST} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPFSR_UWE_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABSU}{\*\bkmkend AAAAAAABSU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPFSR_UXE_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABSV}{\*\bkmkend AAAAAAABSV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPFSR_UXE_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABSW}{\*\bkmkend AAAAAAABSW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPFSR_UXE_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABSX}{\*\bkmkend AAAAAAABSX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPFSR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001200u){\*\bkmkstart AAAAAAABSY}{\*\bkmkend AAAAAAABSY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPFCR_MPFCLR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABSZ}{\*\bkmkend AAAAAAABSZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPFCR_MPFCLR_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABTA}{\*\bkmkend AAAAAAABTA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPFCR_MPFCLR_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABTB}{\*\bkmkend AAAAAAABTB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPFCR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABTC}{\*\bkmkend AAAAAAABTC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_AID5_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00008000u){\*\bkmkstart AAAAAAABTD}{\*\bkmkend AAAAAAABTD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_AID5_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAABTE}{\*\bkmkend AAAAAAABTE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_AID5_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABTF}{\*\bkmkend AAAAAAABTF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_AID5_BLOCK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABTG}{\*\bkmkend AAAAAAABTG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_AID5_PERMIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABTH}{\*\bkmkend AAAAAAABTH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_AID4_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00004000u){\*\bkmkstart AAAAAAABTI}{\*\bkmkend AAAAAAABTI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_AID4_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Eu){\*\bkmkstart AAAAAAABTJ}{\*\bkmkend AAAAAAABTJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_AID4_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABTK}{\*\bkmkend AAAAAAABTK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_AID4_BLOCK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABTL}{\*\bkmkend AAAAAAABTL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_AID4_PERMIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABTM}{\*\bkmkend AAAAAAABTM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_AID3_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00002000u){\*\bkmkstart AAAAAAABTN}{\*\bkmkend AAAAAAABTN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_AID3_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Du){\*\bkmkstart AAAAAAABTO}{\*\bkmkend AAAAAAABTO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_AID3_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABTP}{\*\bkmkend AAAAAAABTP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_AID3_BLOCK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABTQ}{\*\bkmkend AAAAAAABTQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_AID3_PERMIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABTR}{\*\bkmkend AAAAAAABTR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_AID2_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001000u){\*\bkmkstart AAAAAAABTS}{\*\bkmkend AAAAAAABTS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_AID2_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAABTT}{\*\bkmkend AAAAAAABTT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_AID2_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABTU}{\*\bkmkend AAAAAAABTU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_AID2_BLOCK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABTV}{\*\bkmkend AAAAAAABTV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_AID2_PERMIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABTW}{\*\bkmkend AAAAAAABTW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_AID1_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAABTX}{\*\bkmkend AAAAAAABTX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_AID1_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAABTY}{\*\bkmkend AAAAAAABTY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_AID1_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABTZ}{\*\bkmkend AAAAAAABTZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_AID1_BLOCK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABUA}{\*\bkmkend AAAAAAABUA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_AID1_PERMIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABUB}{\*\bkmkend AAAAAAABUB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_AID0_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000400u){\*\bkmkstart AAAAAAABUC}{\*\bkmkend AAAAAAABUC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_AID0_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAABUD}{\*\bkmkend AAAAAAABUD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_AID0_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABUE}{\*\bkmkend AAAAAAABUE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_AID0_BLOCK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABUF}{\*\bkmkend AAAAAAABUF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_AID0_PERMIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABUG}{\*\bkmkend AAAAAAABUG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_EXT_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000200u){\*\bkmkstart AAAAAAABUH}{\*\bkmkend AAAAAAABUH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_EXT_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAABUI}{\*\bkmkend AAAAAAABUI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_EXT_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABUJ}{\*\bkmkend AAAAAAABUJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_EXT_BLOCK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABUK}{\*\bkmkend AAAAAAABUK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_EXT_PERMIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABUL}{\*\bkmkend AAAAAAABUL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_LCL_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAABUM}{\*\bkmkend AAAAAAABUM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_LCL_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAABUN}{\*\bkmkend AAAAAAABUN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_LCL_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABUO}{\*\bkmkend AAAAAAABUO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_NS_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAABUP}{\*\bkmkend AAAAAAABUP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_NS_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAABUQ}{\*\bkmkend AAAAAAABUQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_NS_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABUR}{\*\bkmkend AAAAAAABUR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_NS_SECURE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABUS}{\*\bkmkend AAAAAAABUS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_NS_NONSECURE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABUT}{\*\bkmkend AAAAAAABUT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_EMU_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAABUU}{\*\bkmkend AAAAAAABUU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_EMU_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAABUV}{\*\bkmkend AAAAAAABUV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_EMU_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABUW}{\*\bkmkend AAAAAAABUW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_EMU_BLOCK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABUX}{\*\bkmkend AAAAAAABUX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_EMU_PERMIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABUY}{\*\bkmkend AAAAAAABUY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_SR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAABUZ}{\*\bkmkend AAAAAAABUZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_SR_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAABVA}{\*\bkmkend AAAAAAABVA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_SR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABVB}{\*\bkmkend AAAAAAABVB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_SR_BLOCK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABVC}{\*\bkmkend AAAAAAABVC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_SR_PERMIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABVD}{\*\bkmkend AAAAAAABVD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_SW_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAABVE}{\*\bkmkend AAAAAAABVE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_SW_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAABVF}{\*\bkmkend AAAAAAABVF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_SW_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABVG}{\*\bkmkend AAAAAAABVG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_SW_BLOCK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABVH}{\*\bkmkend AAAAAAABVH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_SW_PERMIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABVI}{\*\bkmkend AAAAAAABVI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_SX_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAABVJ}{\*\bkmkend AAAAAAABVJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_SX_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAABVK}{\*\bkmkend AAAAAAABVK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_SX_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABVL}{\*\bkmkend AAAAAAABVL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_SX_BLOCK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABVM}{\*\bkmkend AAAAAAABVM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_SX_PERMIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABVN}{\*\bkmkend AAAAAAABVN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_UR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAABVO}{\*\bkmkend AAAAAAABVO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_UR_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAABVP}{\*\bkmkend AAAAAAABVP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_UR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABVQ}{\*\bkmkend AAAAAAABVQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_UR_BLOCK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABVR}{\*\bkmkend AAAAAAABVR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_UR_PERMIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABVS}{\*\bkmkend AAAAAAABVS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_UW_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAABVT}{\*\bkmkend AAAAAAABVT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_UW_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABVU}{\*\bkmkend AAAAAAABVU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_UW_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABVV}{\*\bkmkend AAAAAAABVV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_UW_BLOCK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABVW}{\*\bkmkend AAAAAAABVW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_UW_PERMIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABVX}{\*\bkmkend AAAAAAABVX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_UX_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABVY}{\*\bkmkend AAAAAAABVY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_UX_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABVZ}{\*\bkmkend AAAAAAABVZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_UX_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABWA}{\*\bkmkend AAAAAAABWA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_UX_BLOCK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABWB}{\*\bkmkend AAAAAAABWB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_UX_PERMIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABWC}{\*\bkmkend AAAAAAABWC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPAG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABWD}{\*\bkmkend AAAAAAABWD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_AID5_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00008000u){\*\bkmkstart AAAAAAABWE}{\*\bkmkend AAAAAAABWE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_AID5_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAABWF}{\*\bkmkend AAAAAAABWF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_AID5_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABWG}{\*\bkmkend AAAAAAABWG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_AID5_BLOCK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABWH}{\*\bkmkend AAAAAAABWH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_AID5_PERMIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABWI}{\*\bkmkend AAAAAAABWI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_AID4_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00004000u){\*\bkmkstart AAAAAAABWJ}{\*\bkmkend AAAAAAABWJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_AID4_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Eu){\*\bkmkstart AAAAAAABWK}{\*\bkmkend AAAAAAABWK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_AID4_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABWL}{\*\bkmkend AAAAAAABWL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_AID4_BLOCK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABWM}{\*\bkmkend AAAAAAABWM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_AID4_PERMIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABWN}{\*\bkmkend AAAAAAABWN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_AID3_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00002000u){\*\bkmkstart AAAAAAABWO}{\*\bkmkend AAAAAAABWO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_AID3_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Du){\*\bkmkstart AAAAAAABWP}{\*\bkmkend AAAAAAABWP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_AID3_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABWQ}{\*\bkmkend AAAAAAABWQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_AID3_BLOCK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABWR}{\*\bkmkend AAAAAAABWR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_AID3_PERMIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABWS}{\*\bkmkend AAAAAAABWS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_AID2_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001000u){\*\bkmkstart AAAAAAABWT}{\*\bkmkend AAAAAAABWT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_AID2_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAABWU}{\*\bkmkend AAAAAAABWU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_AID2_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABWV}{\*\bkmkend AAAAAAABWV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_AID2_BLOCK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABWW}{\*\bkmkend AAAAAAABWW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_AID2_PERMIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABWX}{\*\bkmkend AAAAAAABWX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_AID1_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAABWY}{\*\bkmkend AAAAAAABWY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_AID1_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAABWZ}{\*\bkmkend AAAAAAABWZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_AID1_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABXA}{\*\bkmkend AAAAAAABXA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_AID1_BLOCK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABXB}{\*\bkmkend AAAAAAABXB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_AID1_PERMIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABXC}{\*\bkmkend AAAAAAABXC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_AID0_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000400u){\*\bkmkstart AAAAAAABXD}{\*\bkmkend AAAAAAABXD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_AID0_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAABXE}{\*\bkmkend AAAAAAABXE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_AID0_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABXF}{\*\bkmkend AAAAAAABXF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_AID0_BLOCK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABXG}{\*\bkmkend AAAAAAABXG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_AID0_PERMIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABXH}{\*\bkmkend AAAAAAABXH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_EXT_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000200u){\*\bkmkstart AAAAAAABXI}{\*\bkmkend AAAAAAABXI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_EXT_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAABXJ}{\*\bkmkend AAAAAAABXJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_EXT_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABXK}{\*\bkmkend AAAAAAABXK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_EXT_BLOCK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABXL}{\*\bkmkend AAAAAAABXL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_EXT_PERMIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABXM}{\*\bkmkend AAAAAAABXM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_LCL_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAABXN}{\*\bkmkend AAAAAAABXN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_LCL_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAABXO}{\*\bkmkend AAAAAAABXO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_LCL_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABXP}{\*\bkmkend AAAAAAABXP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_NS_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAABXQ}{\*\bkmkend AAAAAAABXQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_NS_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAABXR}{\*\bkmkend AAAAAAABXR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_NS_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABXS}{\*\bkmkend AAAAAAABXS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_NS_SECURE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABXT}{\*\bkmkend AAAAAAABXT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_NS_NONSECURE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABXU}{\*\bkmkend AAAAAAABXU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_EMU_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAABXV}{\*\bkmkend AAAAAAABXV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_EMU_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAABXW}{\*\bkmkend AAAAAAABXW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_EMU_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABXX}{\*\bkmkend AAAAAAABXX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_EMU_BLOCK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABXY}{\*\bkmkend AAAAAAABXY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_EMU_PERMIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABXZ}{\*\bkmkend AAAAAAABXZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_SR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAABYA}{\*\bkmkend AAAAAAABYA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_SR_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAABYB}{\*\bkmkend AAAAAAABYB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_SR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABYC}{\*\bkmkend AAAAAAABYC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_SR_BLOCK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABYD}{\*\bkmkend AAAAAAABYD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_SR_PERMIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABYE}{\*\bkmkend AAAAAAABYE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_SW_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAABYF}{\*\bkmkend AAAAAAABYF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_SW_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAABYG}{\*\bkmkend AAAAAAABYG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_SW_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABYH}{\*\bkmkend AAAAAAABYH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_SW_BLOCK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABYI}{\*\bkmkend AAAAAAABYI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_SW_PERMIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABYJ}{\*\bkmkend AAAAAAABYJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_SX_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAABYK}{\*\bkmkend AAAAAAABYK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_SX_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAABYL}{\*\bkmkend AAAAAAABYL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_SX_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABYM}{\*\bkmkend AAAAAAABYM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_SX_BLOCK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABYN}{\*\bkmkend AAAAAAABYN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_SX_PERMIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABYO}{\*\bkmkend AAAAAAABYO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_UR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAABYP}{\*\bkmkend AAAAAAABYP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_UR_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAABYQ}{\*\bkmkend AAAAAAABYQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_UR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABYR}{\*\bkmkend AAAAAAABYR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_UR_BLOCK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABYS}{\*\bkmkend AAAAAAABYS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_UR_PERMIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABYT}{\*\bkmkend AAAAAAABYT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_UW_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAABYU}{\*\bkmkend AAAAAAABYU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_UW_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABYV}{\*\bkmkend AAAAAAABYV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_UW_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABYW}{\*\bkmkend AAAAAAABYW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_UW_BLOCK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABYX}{\*\bkmkend AAAAAAABYX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_UW_PERMIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABYY}{\*\bkmkend AAAAAAABYY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_UX_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABYZ}{\*\bkmkend AAAAAAABYZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_UX_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABZA}{\*\bkmkend AAAAAAABZA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_UX_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABZB}{\*\bkmkend AAAAAAABZB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_UX_BLOCK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABZC}{\*\bkmkend AAAAAAABZC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_UX_PERMIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAABZD}{\*\bkmkend AAAAAAABZD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_MPPA_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABZE}{\*\bkmkend AAAAAAABZE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E31_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x80000000u){\*\bkmkstart AAAAAAABZF}{\*\bkmkend AAAAAAABZF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E31_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAABZG}{\*\bkmkend AAAAAAABZG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E31_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABZH}{\*\bkmkend AAAAAAABZH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E30_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x40000000u){\*\bkmkstart AAAAAAABZI}{\*\bkmkend AAAAAAABZI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E30_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Eu){\*\bkmkstart AAAAAAABZJ}{\*\bkmkend AAAAAAABZJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E30_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABZK}{\*\bkmkend AAAAAAABZK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E29_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x20000000u){\*\bkmkstart AAAAAAABZL}{\*\bkmkend AAAAAAABZL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E29_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Du){\*\bkmkstart AAAAAAABZM}{\*\bkmkend AAAAAAABZM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E29_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABZN}{\*\bkmkend AAAAAAABZN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E28_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x10000000u){\*\bkmkstart AAAAAAABZO}{\*\bkmkend AAAAAAABZO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E28_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAABZP}{\*\bkmkend AAAAAAABZP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E28_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABZQ}{\*\bkmkend AAAAAAABZQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E27_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x08000000u){\*\bkmkstart AAAAAAABZR}{\*\bkmkend AAAAAAABZR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E27_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Bu){\*\bkmkstart AAAAAAABZS}{\*\bkmkend AAAAAAABZS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E27_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABZT}{\*\bkmkend AAAAAAABZT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E26_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x04000000u){\*\bkmkstart AAAAAAABZU}{\*\bkmkend AAAAAAABZU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E26_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Au){\*\bkmkstart AAAAAAABZV}{\*\bkmkend AAAAAAABZV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E26_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABZW}{\*\bkmkend AAAAAAABZW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E25_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x02000000u){\*\bkmkstart AAAAAAABZX}{\*\bkmkend AAAAAAABZX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E25_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000019u){\*\bkmkstart AAAAAAABZY}{\*\bkmkend AAAAAAABZY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E25_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAABZZ}{\*\bkmkend AAAAAAABZZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E24_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x01000000u){\*\bkmkstart AAAAAAACAA}{\*\bkmkend AAAAAAACAA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E24_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAACAB}{\*\bkmkend AAAAAAACAB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E24_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACAC}{\*\bkmkend AAAAAAACAC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E23_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00800000u){\*\bkmkstart AAAAAAACAD}{\*\bkmkend AAAAAAACAD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E23_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000017u){\*\bkmkstart AAAAAAACAE}{\*\bkmkend AAAAAAACAE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E23_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACAF}{\*\bkmkend AAAAAAACAF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E22_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAACAG}{\*\bkmkend AAAAAAACAG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E22_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAACAH}{\*\bkmkend AAAAAAACAH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E22_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACAI}{\*\bkmkend AAAAAAACAI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E21_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00200000u){\*\bkmkstart AAAAAAACAJ}{\*\bkmkend AAAAAAACAJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E21_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAACAK}{\*\bkmkend AAAAAAACAK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E21_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACAL}{\*\bkmkend AAAAAAACAL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E20_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAACAM}{\*\bkmkend AAAAAAACAM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E20_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAACAN}{\*\bkmkend AAAAAAACAN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E20_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACAO}{\*\bkmkend AAAAAAACAO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E19_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00080000u){\*\bkmkstart AAAAAAACAP}{\*\bkmkend AAAAAAACAP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E19_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000013u){\*\bkmkstart AAAAAAACAQ}{\*\bkmkend AAAAAAACAQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E19_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACAR}{\*\bkmkend AAAAAAACAR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E18_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00040000u){\*\bkmkstart AAAAAAACAS}{\*\bkmkend AAAAAAACAS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E18_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000012u){\*\bkmkstart AAAAAAACAT}{\*\bkmkend AAAAAAACAT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E18_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACAU}{\*\bkmkend AAAAAAACAU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E17_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00020000u){\*\bkmkstart AAAAAAACAV}{\*\bkmkend AAAAAAACAV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E17_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000011u){\*\bkmkstart AAAAAAACAW}{\*\bkmkend AAAAAAACAW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E17_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACAX}{\*\bkmkend AAAAAAACAX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E16_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAACAY}{\*\bkmkend AAAAAAACAY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E16_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAACAZ}{\*\bkmkend AAAAAAACAZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E16_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACBA}{\*\bkmkend AAAAAAACBA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E15_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00008000u){\*\bkmkstart AAAAAAACBB}{\*\bkmkend AAAAAAACBB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E15_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAACBC}{\*\bkmkend AAAAAAACBC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E15_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACBD}{\*\bkmkend AAAAAAACBD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E14_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00004000u){\*\bkmkstart AAAAAAACBE}{\*\bkmkend AAAAAAACBE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E14_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Eu){\*\bkmkstart AAAAAAACBF}{\*\bkmkend AAAAAAACBF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E14_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACBG}{\*\bkmkend AAAAAAACBG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E13_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00002000u){\*\bkmkstart AAAAAAACBH}{\*\bkmkend AAAAAAACBH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E13_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Du){\*\bkmkstart AAAAAAACBI}{\*\bkmkend AAAAAAACBI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E13_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACBJ}{\*\bkmkend AAAAAAACBJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E12_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001000u){\*\bkmkstart AAAAAAACBK}{\*\bkmkend AAAAAAACBK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E12_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAACBL}{\*\bkmkend AAAAAAACBL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E12_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACBM}{\*\bkmkend AAAAAAACBM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E11_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAACBN}{\*\bkmkend AAAAAAACBN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E11_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAACBO}{\*\bkmkend AAAAAAACBO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E11_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACBP}{\*\bkmkend AAAAAAACBP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E10_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000400u){\*\bkmkstart AAAAAAACBQ}{\*\bkmkend AAAAAAACBQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E10_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAACBR}{\*\bkmkend AAAAAAACBR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E10_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACBS}{\*\bkmkend AAAAAAACBS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E9_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000200u){\*\bkmkstart AAAAAAACBT}{\*\bkmkend AAAAAAACBT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E9_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAACBU}{\*\bkmkend AAAAAAACBU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E9_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACBV}{\*\bkmkend AAAAAAACBV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E8_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAACBW}{\*\bkmkend AAAAAAACBW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E8_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAACBX}{\*\bkmkend AAAAAAACBX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E8_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACBY}{\*\bkmkend AAAAAAACBY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E7_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAACBZ}{\*\bkmkend AAAAAAACBZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E7_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAACCA}{\*\bkmkend AAAAAAACCA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E7_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACCB}{\*\bkmkend AAAAAAACCB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E6_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAACCC}{\*\bkmkend AAAAAAACCC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E6_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAACCD}{\*\bkmkend AAAAAAACCD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E6_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACCE}{\*\bkmkend AAAAAAACCE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E5_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAACCF}{\*\bkmkend AAAAAAACCF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E5_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAACCG}{\*\bkmkend AAAAAAACCG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E5_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACCH}{\*\bkmkend AAAAAAACCH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E4_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAACCI}{\*\bkmkend AAAAAAACCI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E4_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAACCJ}{\*\bkmkend AAAAAAACCJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E4_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACCK}{\*\bkmkend AAAAAAACCK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E3_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAACCL}{\*\bkmkend AAAAAAACCL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E3_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAACCM}{\*\bkmkend AAAAAAACCM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E3_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACCN}{\*\bkmkend AAAAAAACCN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E2_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAACCO}{\*\bkmkend AAAAAAACCO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E2_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAACCP}{\*\bkmkend AAAAAAACCP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E2_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACCQ}{\*\bkmkend AAAAAAACCQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E1_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAACCR}{\*\bkmkend AAAAAAACCR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E1_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACCS}{\*\bkmkend AAAAAAACCS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E1_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACCT}{\*\bkmkend AAAAAAACCT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E0_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACCU}{\*\bkmkend AAAAAAACCU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E0_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACCV}{\*\bkmkend AAAAAAACCV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_E0_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACCW}{\*\bkmkend AAAAAAACCW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E63_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x80000000u){\*\bkmkstart AAAAAAACCY}{\*\bkmkend AAAAAAACCY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E63_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAACCZ}{\*\bkmkend AAAAAAACCZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E63_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACDA}{\*\bkmkend AAAAAAACDA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E62_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x40000000u){\*\bkmkstart AAAAAAACDB}{\*\bkmkend AAAAAAACDB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E62_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Eu){\*\bkmkstart AAAAAAACDC}{\*\bkmkend AAAAAAACDC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E62_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACDD}{\*\bkmkend AAAAAAACDD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E61_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x20000000u){\*\bkmkstart AAAAAAACDE}{\*\bkmkend AAAAAAACDE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E61_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Du){\*\bkmkstart AAAAAAACDF}{\*\bkmkend AAAAAAACDF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E61_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACDG}{\*\bkmkend AAAAAAACDG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E60_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x10000000u){\*\bkmkstart AAAAAAACDH}{\*\bkmkend AAAAAAACDH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E60_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAACDI}{\*\bkmkend AAAAAAACDI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E60_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACDJ}{\*\bkmkend AAAAAAACDJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E59_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x08000000u){\*\bkmkstart AAAAAAACDK}{\*\bkmkend AAAAAAACDK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E59_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Bu){\*\bkmkstart AAAAAAACDL}{\*\bkmkend AAAAAAACDL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E59_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACDM}{\*\bkmkend AAAAAAACDM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E58_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x04000000u){\*\bkmkstart AAAAAAACDN}{\*\bkmkend AAAAAAACDN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E58_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Au){\*\bkmkstart AAAAAAACDO}{\*\bkmkend AAAAAAACDO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E58_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACDP}{\*\bkmkend AAAAAAACDP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E57_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x02000000u){\*\bkmkstart AAAAAAACDQ}{\*\bkmkend AAAAAAACDQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E57_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000019u){\*\bkmkstart AAAAAAACDR}{\*\bkmkend AAAAAAACDR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E57_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACDS}{\*\bkmkend AAAAAAACDS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E56_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x01000000u){\*\bkmkstart AAAAAAACDT}{\*\bkmkend AAAAAAACDT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E56_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAACDU}{\*\bkmkend AAAAAAACDU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E56_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACDV}{\*\bkmkend AAAAAAACDV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E55_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00800000u){\*\bkmkstart AAAAAAACDW}{\*\bkmkend AAAAAAACDW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E55_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000017u){\*\bkmkstart AAAAAAACDX}{\*\bkmkend AAAAAAACDX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E55_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACDY}{\*\bkmkend AAAAAAACDY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E54_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAACDZ}{\*\bkmkend AAAAAAACDZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E54_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAACEA}{\*\bkmkend AAAAAAACEA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E54_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACEB}{\*\bkmkend AAAAAAACEB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E53_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00200000u){\*\bkmkstart AAAAAAACEC}{\*\bkmkend AAAAAAACEC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E53_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAACED}{\*\bkmkend AAAAAAACED} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E53_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACEE}{\*\bkmkend AAAAAAACEE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E52_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAACEF}{\*\bkmkend AAAAAAACEF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E52_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAACEG}{\*\bkmkend AAAAAAACEG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E52_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACEH}{\*\bkmkend AAAAAAACEH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E51_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00080000u){\*\bkmkstart AAAAAAACEI}{\*\bkmkend AAAAAAACEI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E51_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000013u){\*\bkmkstart AAAAAAACEJ}{\*\bkmkend AAAAAAACEJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E51_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACEK}{\*\bkmkend AAAAAAACEK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E50_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00040000u){\*\bkmkstart AAAAAAACEL}{\*\bkmkend AAAAAAACEL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E50_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000012u){\*\bkmkstart AAAAAAACEM}{\*\bkmkend AAAAAAACEM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E50_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACEN}{\*\bkmkend AAAAAAACEN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E49_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00020000u){\*\bkmkstart AAAAAAACEO}{\*\bkmkend AAAAAAACEO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E49_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000011u){\*\bkmkstart AAAAAAACEP}{\*\bkmkend AAAAAAACEP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E49_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACEQ}{\*\bkmkend AAAAAAACEQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E48_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAACER}{\*\bkmkend AAAAAAACER} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E48_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAACES}{\*\bkmkend AAAAAAACES} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E48_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACET}{\*\bkmkend AAAAAAACET} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E47_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00008000u){\*\bkmkstart AAAAAAACEU}{\*\bkmkend AAAAAAACEU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E47_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAACEV}{\*\bkmkend AAAAAAACEV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E47_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACEW}{\*\bkmkend AAAAAAACEW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E46_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00004000u){\*\bkmkstart AAAAAAACEX}{\*\bkmkend AAAAAAACEX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E46_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Eu){\*\bkmkstart AAAAAAACEY}{\*\bkmkend AAAAAAACEY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E46_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACEZ}{\*\bkmkend AAAAAAACEZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E45_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00002000u){\*\bkmkstart AAAAAAACFA}{\*\bkmkend AAAAAAACFA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E45_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Du){\*\bkmkstart AAAAAAACFB}{\*\bkmkend AAAAAAACFB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E45_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACFC}{\*\bkmkend AAAAAAACFC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E44_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001000u){\*\bkmkstart AAAAAAACFD}{\*\bkmkend AAAAAAACFD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E44_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAACFE}{\*\bkmkend AAAAAAACFE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E44_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACFF}{\*\bkmkend AAAAAAACFF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E43_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAACFG}{\*\bkmkend AAAAAAACFG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E43_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAACFH}{\*\bkmkend AAAAAAACFH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E43_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACFI}{\*\bkmkend AAAAAAACFI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E42_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000400u){\*\bkmkstart AAAAAAACFJ}{\*\bkmkend AAAAAAACFJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E42_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAACFK}{\*\bkmkend AAAAAAACFK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E42_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACFL}{\*\bkmkend AAAAAAACFL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E41_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000200u){\*\bkmkstart AAAAAAACFM}{\*\bkmkend AAAAAAACFM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E41_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAACFN}{\*\bkmkend AAAAAAACFN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E41_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACFO}{\*\bkmkend AAAAAAACFO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E40_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAACFP}{\*\bkmkend AAAAAAACFP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E40_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAACFQ}{\*\bkmkend AAAAAAACFQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E40_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACFR}{\*\bkmkend AAAAAAACFR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E39_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAACFS}{\*\bkmkend AAAAAAACFS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E39_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAACFT}{\*\bkmkend AAAAAAACFT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E39_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACFU}{\*\bkmkend AAAAAAACFU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E38_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAACFV}{\*\bkmkend AAAAAAACFV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E38_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAACFW}{\*\bkmkend AAAAAAACFW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E38_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACFX}{\*\bkmkend AAAAAAACFX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E37_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAACFY}{\*\bkmkend AAAAAAACFY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E37_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAACFZ}{\*\bkmkend AAAAAAACFZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E37_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACGA}{\*\bkmkend AAAAAAACGA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E36_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAACGB}{\*\bkmkend AAAAAAACGB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E36_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAACGC}{\*\bkmkend AAAAAAACGC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E36_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACGD}{\*\bkmkend AAAAAAACGD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E35_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAACGE}{\*\bkmkend AAAAAAACGE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E35_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAACGF}{\*\bkmkend AAAAAAACGF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E35_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACGG}{\*\bkmkend AAAAAAACGG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E34_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAACGH}{\*\bkmkend AAAAAAACGH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E34_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAACGI}{\*\bkmkend AAAAAAACGI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E34_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACGJ}{\*\bkmkend AAAAAAACGJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E33_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAACGK}{\*\bkmkend AAAAAAACGK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E33_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACGL}{\*\bkmkend AAAAAAACGL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E33_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACGM}{\*\bkmkend AAAAAAACGM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E32_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACGN}{\*\bkmkend AAAAAAACGN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E32_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACGO}{\*\bkmkend AAAAAAACGO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_E32_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACGP}{\*\bkmkend AAAAAAACGP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E31_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x80000000u){\*\bkmkstart AAAAAAACGR}{\*\bkmkend AAAAAAACGR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E31_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAACGS}{\*\bkmkend AAAAAAACGS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E31_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACGT}{\*\bkmkend AAAAAAACGT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E31_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACGU}{\*\bkmkend AAAAAAACGU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E30_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x40000000u){\*\bkmkstart AAAAAAACGV}{\*\bkmkend AAAAAAACGV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E30_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Eu){\*\bkmkstart AAAAAAACGW}{\*\bkmkend AAAAAAACGW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E30_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACGX}{\*\bkmkend AAAAAAACGX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E30_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACGY}{\*\bkmkend AAAAAAACGY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E29_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x20000000u){\*\bkmkstart AAAAAAACGZ}{\*\bkmkend AAAAAAACGZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E29_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Du){\*\bkmkstart AAAAAAACHA}{\*\bkmkend AAAAAAACHA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E29_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACHB}{\*\bkmkend AAAAAAACHB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E29_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACHC}{\*\bkmkend AAAAAAACHC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E28_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x10000000u){\*\bkmkstart AAAAAAACHD}{\*\bkmkend AAAAAAACHD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E28_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAACHE}{\*\bkmkend AAAAAAACHE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E28_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACHF}{\*\bkmkend AAAAAAACHF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E28_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACHG}{\*\bkmkend AAAAAAACHG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E27_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x08000000u){\*\bkmkstart AAAAAAACHH}{\*\bkmkend AAAAAAACHH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E27_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Bu){\*\bkmkstart AAAAAAACHI}{\*\bkmkend AAAAAAACHI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E27_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACHJ}{\*\bkmkend AAAAAAACHJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E27_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACHK}{\*\bkmkend AAAAAAACHK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E26_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x04000000u){\*\bkmkstart AAAAAAACHL}{\*\bkmkend AAAAAAACHL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E26_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Au){\*\bkmkstart AAAAAAACHM}{\*\bkmkend AAAAAAACHM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E26_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACHN}{\*\bkmkend AAAAAAACHN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E26_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACHO}{\*\bkmkend AAAAAAACHO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E25_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x02000000u){\*\bkmkstart AAAAAAACHP}{\*\bkmkend AAAAAAACHP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E25_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000019u){\*\bkmkstart AAAAAAACHQ}{\*\bkmkend AAAAAAACHQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E25_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACHR}{\*\bkmkend AAAAAAACHR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E25_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACHS}{\*\bkmkend AAAAAAACHS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E24_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x01000000u){\*\bkmkstart AAAAAAACHT}{\*\bkmkend AAAAAAACHT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E24_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAACHU}{\*\bkmkend AAAAAAACHU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E24_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACHV}{\*\bkmkend AAAAAAACHV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E24_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACHW}{\*\bkmkend AAAAAAACHW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E23_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00800000u){\*\bkmkstart AAAAAAACHX}{\*\bkmkend AAAAAAACHX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E23_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000017u){\*\bkmkstart AAAAAAACHY}{\*\bkmkend AAAAAAACHY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E23_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACHZ}{\*\bkmkend AAAAAAACHZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E23_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACIA}{\*\bkmkend AAAAAAACIA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E22_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAACIB}{\*\bkmkend AAAAAAACIB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E22_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAACIC}{\*\bkmkend AAAAAAACIC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E22_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACID}{\*\bkmkend AAAAAAACID} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E22_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACIE}{\*\bkmkend AAAAAAACIE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E21_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00200000u){\*\bkmkstart AAAAAAACIF}{\*\bkmkend AAAAAAACIF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E21_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAACIG}{\*\bkmkend AAAAAAACIG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E21_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACIH}{\*\bkmkend AAAAAAACIH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E21_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACII}{\*\bkmkend AAAAAAACII} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E20_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAACIJ}{\*\bkmkend AAAAAAACIJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E20_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAACIK}{\*\bkmkend AAAAAAACIK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E20_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACIL}{\*\bkmkend AAAAAAACIL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E20_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACIM}{\*\bkmkend AAAAAAACIM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E19_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00080000u){\*\bkmkstart AAAAAAACIN}{\*\bkmkend AAAAAAACIN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E19_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000013u){\*\bkmkstart AAAAAAACIO}{\*\bkmkend AAAAAAACIO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E19_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACIP}{\*\bkmkend AAAAAAACIP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E19_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACIQ}{\*\bkmkend AAAAAAACIQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E18_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00040000u){\*\bkmkstart AAAAAAACIR}{\*\bkmkend AAAAAAACIR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E18_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000012u){\*\bkmkstart AAAAAAACIS}{\*\bkmkend AAAAAAACIS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E18_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACIT}{\*\bkmkend AAAAAAACIT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E18_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACIU}{\*\bkmkend AAAAAAACIU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E17_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00020000u){\*\bkmkstart AAAAAAACIV}{\*\bkmkend AAAAAAACIV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E17_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000011u){\*\bkmkstart AAAAAAACIW}{\*\bkmkend AAAAAAACIW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E17_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACIX}{\*\bkmkend AAAAAAACIX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E17_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACIY}{\*\bkmkend AAAAAAACIY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E16_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAACIZ}{\*\bkmkend AAAAAAACIZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E16_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAACJA}{\*\bkmkend AAAAAAACJA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E16_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACJB}{\*\bkmkend AAAAAAACJB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E16_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACJC}{\*\bkmkend AAAAAAACJC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E15_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00008000u){\*\bkmkstart AAAAAAACJD}{\*\bkmkend AAAAAAACJD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E15_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAACJE}{\*\bkmkend AAAAAAACJE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E15_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACJF}{\*\bkmkend AAAAAAACJF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E15_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACJG}{\*\bkmkend AAAAAAACJG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E14_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00004000u){\*\bkmkstart AAAAAAACJH}{\*\bkmkend AAAAAAACJH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E14_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Eu){\*\bkmkstart AAAAAAACJI}{\*\bkmkend AAAAAAACJI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E14_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACJJ}{\*\bkmkend AAAAAAACJJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E14_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACJK}{\*\bkmkend AAAAAAACJK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E13_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00002000u){\*\bkmkstart AAAAAAACJL}{\*\bkmkend AAAAAAACJL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E13_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Du){\*\bkmkstart AAAAAAACJM}{\*\bkmkend AAAAAAACJM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E13_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACJN}{\*\bkmkend AAAAAAACJN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E13_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACJO}{\*\bkmkend AAAAAAACJO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E12_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001000u){\*\bkmkstart AAAAAAACJP}{\*\bkmkend AAAAAAACJP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E12_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAACJQ}{\*\bkmkend AAAAAAACJQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E12_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACJR}{\*\bkmkend AAAAAAACJR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E12_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACJS}{\*\bkmkend AAAAAAACJS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E11_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAACJT}{\*\bkmkend AAAAAAACJT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E11_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAACJU}{\*\bkmkend AAAAAAACJU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E11_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACJV}{\*\bkmkend AAAAAAACJV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E11_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACJW}{\*\bkmkend AAAAAAACJW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E10_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000400u){\*\bkmkstart AAAAAAACJX}{\*\bkmkend AAAAAAACJX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E10_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAACJY}{\*\bkmkend AAAAAAACJY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E10_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACJZ}{\*\bkmkend AAAAAAACJZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E10_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACKA}{\*\bkmkend AAAAAAACKA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E9_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000200u){\*\bkmkstart AAAAAAACKB}{\*\bkmkend AAAAAAACKB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E9_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAACKC}{\*\bkmkend AAAAAAACKC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E9_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACKD}{\*\bkmkend AAAAAAACKD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E9_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACKE}{\*\bkmkend AAAAAAACKE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E8_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAACKF}{\*\bkmkend AAAAAAACKF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E8_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAACKG}{\*\bkmkend AAAAAAACKG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E8_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACKH}{\*\bkmkend AAAAAAACKH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E8_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACKI}{\*\bkmkend AAAAAAACKI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E7_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAACKJ}{\*\bkmkend AAAAAAACKJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E7_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAACKK}{\*\bkmkend AAAAAAACKK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E7_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACKL}{\*\bkmkend AAAAAAACKL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E7_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACKM}{\*\bkmkend AAAAAAACKM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E6_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAACKN}{\*\bkmkend AAAAAAACKN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E6_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAACKO}{\*\bkmkend AAAAAAACKO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E6_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACKP}{\*\bkmkend AAAAAAACKP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E6_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACKQ}{\*\bkmkend AAAAAAACKQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E5_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAACKR}{\*\bkmkend AAAAAAACKR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E5_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAACKS}{\*\bkmkend AAAAAAACKS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E5_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACKT}{\*\bkmkend AAAAAAACKT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E5_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACKU}{\*\bkmkend AAAAAAACKU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E4_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAACKV}{\*\bkmkend AAAAAAACKV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E4_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAACKW}{\*\bkmkend AAAAAAACKW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E4_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACKX}{\*\bkmkend AAAAAAACKX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E4_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACKY}{\*\bkmkend AAAAAAACKY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E3_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAACKZ}{\*\bkmkend AAAAAAACKZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E3_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAACLA}{\*\bkmkend AAAAAAACLA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E3_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACLB}{\*\bkmkend AAAAAAACLB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E3_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACLC}{\*\bkmkend AAAAAAACLC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E2_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAACLD}{\*\bkmkend AAAAAAACLD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E2_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAACLE}{\*\bkmkend AAAAAAACLE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E2_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACLF}{\*\bkmkend AAAAAAACLF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E2_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACLG}{\*\bkmkend AAAAAAACLG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E1_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAACLH}{\*\bkmkend AAAAAAACLH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E1_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACLI}{\*\bkmkend AAAAAAACLI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E1_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACLJ}{\*\bkmkend AAAAAAACLJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E1_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACLK}{\*\bkmkend AAAAAAACLK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E0_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACLL}{\*\bkmkend AAAAAAACLL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E0_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACLM}{\*\bkmkend AAAAAAACLM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E0_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACLN}{\*\bkmkend AAAAAAACLN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_E0_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACLO}{\*\bkmkend AAAAAAACLO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E63_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x80000000u){\*\bkmkstart AAAAAAACLQ}{\*\bkmkend AAAAAAACLQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E63_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAACLR}{\*\bkmkend AAAAAAACLR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E63_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACLS}{\*\bkmkend AAAAAAACLS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E63_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACLT}{\*\bkmkend AAAAAAACLT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E62_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x40000000u){\*\bkmkstart AAAAAAACLU}{\*\bkmkend AAAAAAACLU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E62_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Eu){\*\bkmkstart AAAAAAACLV}{\*\bkmkend AAAAAAACLV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E62_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACLW}{\*\bkmkend AAAAAAACLW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E62_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACLX}{\*\bkmkend AAAAAAACLX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E61_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x20000000u){\*\bkmkstart AAAAAAACLY}{\*\bkmkend AAAAAAACLY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E61_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Du){\*\bkmkstart AAAAAAACLZ}{\*\bkmkend AAAAAAACLZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E61_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACMA}{\*\bkmkend AAAAAAACMA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E61_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACMB}{\*\bkmkend AAAAAAACMB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E60_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x10000000u){\*\bkmkstart AAAAAAACMC}{\*\bkmkend AAAAAAACMC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E60_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAACMD}{\*\bkmkend AAAAAAACMD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E60_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACME}{\*\bkmkend AAAAAAACME} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E60_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACMF}{\*\bkmkend AAAAAAACMF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E59_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x08000000u){\*\bkmkstart AAAAAAACMG}{\*\bkmkend AAAAAAACMG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E59_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Bu){\*\bkmkstart AAAAAAACMH}{\*\bkmkend AAAAAAACMH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E59_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACMI}{\*\bkmkend AAAAAAACMI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E59_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACMJ}{\*\bkmkend AAAAAAACMJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E58_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x04000000u){\*\bkmkstart AAAAAAACMK}{\*\bkmkend AAAAAAACMK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E58_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Au){\*\bkmkstart AAAAAAACML}{\*\bkmkend AAAAAAACML} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E58_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACMM}{\*\bkmkend AAAAAAACMM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E58_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACMN}{\*\bkmkend AAAAAAACMN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E57_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x02000000u){\*\bkmkstart AAAAAAACMO}{\*\bkmkend AAAAAAACMO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E57_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000019u){\*\bkmkstart AAAAAAACMP}{\*\bkmkend AAAAAAACMP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E57_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACMQ}{\*\bkmkend AAAAAAACMQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E57_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACMR}{\*\bkmkend AAAAAAACMR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E56_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x01000000u){\*\bkmkstart AAAAAAACMS}{\*\bkmkend AAAAAAACMS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E56_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAACMT}{\*\bkmkend AAAAAAACMT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E56_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACMU}{\*\bkmkend AAAAAAACMU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E56_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACMV}{\*\bkmkend AAAAAAACMV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E55_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00800000u){\*\bkmkstart AAAAAAACMW}{\*\bkmkend AAAAAAACMW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E55_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000017u){\*\bkmkstart AAAAAAACMX}{\*\bkmkend AAAAAAACMX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E55_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACMY}{\*\bkmkend AAAAAAACMY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E55_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACMZ}{\*\bkmkend AAAAAAACMZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E54_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAACNA}{\*\bkmkend AAAAAAACNA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E54_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAACNB}{\*\bkmkend AAAAAAACNB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E54_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACNC}{\*\bkmkend AAAAAAACNC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E54_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACND}{\*\bkmkend AAAAAAACND} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E53_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00200000u){\*\bkmkstart AAAAAAACNE}{\*\bkmkend AAAAAAACNE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E53_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAACNF}{\*\bkmkend AAAAAAACNF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E53_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACNG}{\*\bkmkend AAAAAAACNG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E53_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACNH}{\*\bkmkend AAAAAAACNH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E52_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAACNI}{\*\bkmkend AAAAAAACNI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E52_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAACNJ}{\*\bkmkend AAAAAAACNJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E52_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACNK}{\*\bkmkend AAAAAAACNK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E52_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACNL}{\*\bkmkend AAAAAAACNL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E51_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00080000u){\*\bkmkstart AAAAAAACNM}{\*\bkmkend AAAAAAACNM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E51_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000013u){\*\bkmkstart AAAAAAACNN}{\*\bkmkend AAAAAAACNN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E51_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACNO}{\*\bkmkend AAAAAAACNO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E51_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACNP}{\*\bkmkend AAAAAAACNP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E50_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00040000u){\*\bkmkstart AAAAAAACNQ}{\*\bkmkend AAAAAAACNQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E50_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000012u){\*\bkmkstart AAAAAAACNR}{\*\bkmkend AAAAAAACNR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E50_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACNS}{\*\bkmkend AAAAAAACNS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E50_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACNT}{\*\bkmkend AAAAAAACNT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E49_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00020000u){\*\bkmkstart AAAAAAACNU}{\*\bkmkend AAAAAAACNU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E49_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000011u){\*\bkmkstart AAAAAAACNV}{\*\bkmkend AAAAAAACNV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E49_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACNW}{\*\bkmkend AAAAAAACNW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E49_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACNX}{\*\bkmkend AAAAAAACNX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E48_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAACNY}{\*\bkmkend AAAAAAACNY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E48_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAACNZ}{\*\bkmkend AAAAAAACNZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E48_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACOA}{\*\bkmkend AAAAAAACOA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E48_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACOB}{\*\bkmkend AAAAAAACOB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E47_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00008000u){\*\bkmkstart AAAAAAACOC}{\*\bkmkend AAAAAAACOC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E47_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAACOD}{\*\bkmkend AAAAAAACOD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E47_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACOE}{\*\bkmkend AAAAAAACOE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E47_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACOF}{\*\bkmkend AAAAAAACOF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E46_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00004000u){\*\bkmkstart AAAAAAACOG}{\*\bkmkend AAAAAAACOG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E46_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Eu){\*\bkmkstart AAAAAAACOH}{\*\bkmkend AAAAAAACOH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E46_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACOI}{\*\bkmkend AAAAAAACOI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E46_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACOJ}{\*\bkmkend AAAAAAACOJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E45_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00002000u){\*\bkmkstart AAAAAAACOK}{\*\bkmkend AAAAAAACOK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E45_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Du){\*\bkmkstart AAAAAAACOL}{\*\bkmkend AAAAAAACOL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E45_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACOM}{\*\bkmkend AAAAAAACOM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E45_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACON}{\*\bkmkend AAAAAAACON} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E44_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001000u){\*\bkmkstart AAAAAAACOO}{\*\bkmkend AAAAAAACOO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E44_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAACOP}{\*\bkmkend AAAAAAACOP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E44_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACOQ}{\*\bkmkend AAAAAAACOQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E44_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACOR}{\*\bkmkend AAAAAAACOR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E43_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAACOS}{\*\bkmkend AAAAAAACOS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E43_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAACOT}{\*\bkmkend AAAAAAACOT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E43_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACOU}{\*\bkmkend AAAAAAACOU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E43_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACOV}{\*\bkmkend AAAAAAACOV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E42_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000400u){\*\bkmkstart AAAAAAACOW}{\*\bkmkend AAAAAAACOW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E42_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAACOX}{\*\bkmkend AAAAAAACOX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E42_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACOY}{\*\bkmkend AAAAAAACOY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E42_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACOZ}{\*\bkmkend AAAAAAACOZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E41_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000200u){\*\bkmkstart AAAAAAACPA}{\*\bkmkend AAAAAAACPA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E41_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAACPB}{\*\bkmkend AAAAAAACPB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E41_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACPC}{\*\bkmkend AAAAAAACPC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E41_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACPD}{\*\bkmkend AAAAAAACPD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E40_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAACPE}{\*\bkmkend AAAAAAACPE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E40_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAACPF}{\*\bkmkend AAAAAAACPF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E40_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACPG}{\*\bkmkend AAAAAAACPG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E40_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACPH}{\*\bkmkend AAAAAAACPH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E39_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAACPI}{\*\bkmkend AAAAAAACPI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E39_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAACPJ}{\*\bkmkend AAAAAAACPJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E39_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACPK}{\*\bkmkend AAAAAAACPK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E39_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACPL}{\*\bkmkend AAAAAAACPL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E38_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAACPM}{\*\bkmkend AAAAAAACPM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E38_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAACPN}{\*\bkmkend AAAAAAACPN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E38_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACPO}{\*\bkmkend AAAAAAACPO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E38_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACPP}{\*\bkmkend AAAAAAACPP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E37_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAACPQ}{\*\bkmkend AAAAAAACPQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E37_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAACPR}{\*\bkmkend AAAAAAACPR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E37_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACPS}{\*\bkmkend AAAAAAACPS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E37_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACPT}{\*\bkmkend AAAAAAACPT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E36_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAACPU}{\*\bkmkend AAAAAAACPU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E36_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAACPV}{\*\bkmkend AAAAAAACPV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E36_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACPW}{\*\bkmkend AAAAAAACPW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E36_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACPX}{\*\bkmkend AAAAAAACPX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E35_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAACPY}{\*\bkmkend AAAAAAACPY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E35_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAACPZ}{\*\bkmkend AAAAAAACPZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E35_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACQA}{\*\bkmkend AAAAAAACQA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E35_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACQB}{\*\bkmkend AAAAAAACQB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E34_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAACQC}{\*\bkmkend AAAAAAACQC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E34_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAACQD}{\*\bkmkend AAAAAAACQD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E34_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACQE}{\*\bkmkend AAAAAAACQE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E34_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACQF}{\*\bkmkend AAAAAAACQF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E33_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAACQG}{\*\bkmkend AAAAAAACQG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E33_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACQH}{\*\bkmkend AAAAAAACQH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E33_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACQI}{\*\bkmkend AAAAAAACQI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E33_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACQJ}{\*\bkmkend AAAAAAACQJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E32_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACQK}{\*\bkmkend AAAAAAACQK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E32_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACQL}{\*\bkmkend AAAAAAACQL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E32_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACQM}{\*\bkmkend AAAAAAACQM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_E32_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACQN}{\*\bkmkend AAAAAAACQN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E31_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x80000000u){\*\bkmkstart AAAAAAACQP}{\*\bkmkend AAAAAAACQP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E31_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAACQQ}{\*\bkmkend AAAAAAACQQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E31_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACQR}{\*\bkmkend AAAAAAACQR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E31_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACQS}{\*\bkmkend AAAAAAACQS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E30_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x40000000u){\*\bkmkstart AAAAAAACQT}{\*\bkmkend AAAAAAACQT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E30_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Eu){\*\bkmkstart AAAAAAACQU}{\*\bkmkend AAAAAAACQU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E30_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACQV}{\*\bkmkend AAAAAAACQV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E30_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACQW}{\*\bkmkend AAAAAAACQW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E29_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x20000000u){\*\bkmkstart AAAAAAACQX}{\*\bkmkend AAAAAAACQX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E29_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Du){\*\bkmkstart AAAAAAACQY}{\*\bkmkend AAAAAAACQY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E29_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACQZ}{\*\bkmkend AAAAAAACQZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E29_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACRA}{\*\bkmkend AAAAAAACRA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E28_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x10000000u){\*\bkmkstart AAAAAAACRB}{\*\bkmkend AAAAAAACRB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E28_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAACRC}{\*\bkmkend AAAAAAACRC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E28_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACRD}{\*\bkmkend AAAAAAACRD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E28_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACRE}{\*\bkmkend AAAAAAACRE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E27_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x08000000u){\*\bkmkstart AAAAAAACRF}{\*\bkmkend AAAAAAACRF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E27_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Bu){\*\bkmkstart AAAAAAACRG}{\*\bkmkend AAAAAAACRG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E27_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACRH}{\*\bkmkend AAAAAAACRH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E27_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACRI}{\*\bkmkend AAAAAAACRI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E26_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x04000000u){\*\bkmkstart AAAAAAACRJ}{\*\bkmkend AAAAAAACRJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E26_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Au){\*\bkmkstart AAAAAAACRK}{\*\bkmkend AAAAAAACRK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E26_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACRL}{\*\bkmkend AAAAAAACRL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E26_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACRM}{\*\bkmkend AAAAAAACRM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E25_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x02000000u){\*\bkmkstart AAAAAAACRN}{\*\bkmkend AAAAAAACRN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E25_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000019u){\*\bkmkstart AAAAAAACRO}{\*\bkmkend AAAAAAACRO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E25_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACRP}{\*\bkmkend AAAAAAACRP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E25_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACRQ}{\*\bkmkend AAAAAAACRQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E24_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x01000000u){\*\bkmkstart AAAAAAACRR}{\*\bkmkend AAAAAAACRR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E24_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAACRS}{\*\bkmkend AAAAAAACRS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E24_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACRT}{\*\bkmkend AAAAAAACRT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E24_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACRU}{\*\bkmkend AAAAAAACRU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E23_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00800000u){\*\bkmkstart AAAAAAACRV}{\*\bkmkend AAAAAAACRV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E23_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000017u){\*\bkmkstart AAAAAAACRW}{\*\bkmkend AAAAAAACRW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E23_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACRX}{\*\bkmkend AAAAAAACRX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E23_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACRY}{\*\bkmkend AAAAAAACRY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E22_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAACRZ}{\*\bkmkend AAAAAAACRZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E22_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAACSA}{\*\bkmkend AAAAAAACSA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E22_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACSB}{\*\bkmkend AAAAAAACSB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E22_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACSC}{\*\bkmkend AAAAAAACSC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E21_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00200000u){\*\bkmkstart AAAAAAACSD}{\*\bkmkend AAAAAAACSD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E21_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAACSE}{\*\bkmkend AAAAAAACSE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E21_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACSF}{\*\bkmkend AAAAAAACSF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E21_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACSG}{\*\bkmkend AAAAAAACSG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E20_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAACSH}{\*\bkmkend AAAAAAACSH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E20_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAACSI}{\*\bkmkend AAAAAAACSI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E20_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACSJ}{\*\bkmkend AAAAAAACSJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E20_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACSK}{\*\bkmkend AAAAAAACSK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E19_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00080000u){\*\bkmkstart AAAAAAACSL}{\*\bkmkend AAAAAAACSL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E19_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000013u){\*\bkmkstart AAAAAAACSM}{\*\bkmkend AAAAAAACSM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E19_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACSN}{\*\bkmkend AAAAAAACSN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E19_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACSO}{\*\bkmkend AAAAAAACSO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E18_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00040000u){\*\bkmkstart AAAAAAACSP}{\*\bkmkend AAAAAAACSP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E18_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000012u){\*\bkmkstart AAAAAAACSQ}{\*\bkmkend AAAAAAACSQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E18_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACSR}{\*\bkmkend AAAAAAACSR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E18_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACSS}{\*\bkmkend AAAAAAACSS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E17_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00020000u){\*\bkmkstart AAAAAAACST}{\*\bkmkend AAAAAAACST} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E17_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000011u){\*\bkmkstart AAAAAAACSU}{\*\bkmkend AAAAAAACSU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E17_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACSV}{\*\bkmkend AAAAAAACSV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E17_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACSW}{\*\bkmkend AAAAAAACSW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E16_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAACSX}{\*\bkmkend AAAAAAACSX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E16_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAACSY}{\*\bkmkend AAAAAAACSY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E16_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACSZ}{\*\bkmkend AAAAAAACSZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E16_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACTA}{\*\bkmkend AAAAAAACTA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E15_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00008000u){\*\bkmkstart AAAAAAACTB}{\*\bkmkend AAAAAAACTB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E15_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAACTC}{\*\bkmkend AAAAAAACTC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E15_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACTD}{\*\bkmkend AAAAAAACTD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E15_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACTE}{\*\bkmkend AAAAAAACTE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E14_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00004000u){\*\bkmkstart AAAAAAACTF}{\*\bkmkend AAAAAAACTF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E14_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Eu){\*\bkmkstart AAAAAAACTG}{\*\bkmkend AAAAAAACTG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E14_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACTH}{\*\bkmkend AAAAAAACTH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E14_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACTI}{\*\bkmkend AAAAAAACTI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E13_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00002000u){\*\bkmkstart AAAAAAACTJ}{\*\bkmkend AAAAAAACTJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E13_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Du){\*\bkmkstart AAAAAAACTK}{\*\bkmkend AAAAAAACTK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E13_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACTL}{\*\bkmkend AAAAAAACTL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E13_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACTM}{\*\bkmkend AAAAAAACTM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E12_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001000u){\*\bkmkstart AAAAAAACTN}{\*\bkmkend AAAAAAACTN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E12_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAACTO}{\*\bkmkend AAAAAAACTO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E12_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACTP}{\*\bkmkend AAAAAAACTP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E12_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACTQ}{\*\bkmkend AAAAAAACTQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E11_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAACTR}{\*\bkmkend AAAAAAACTR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E11_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAACTS}{\*\bkmkend AAAAAAACTS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E11_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACTT}{\*\bkmkend AAAAAAACTT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E11_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACTU}{\*\bkmkend AAAAAAACTU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E10_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000400u){\*\bkmkstart AAAAAAACTV}{\*\bkmkend AAAAAAACTV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E10_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAACTW}{\*\bkmkend AAAAAAACTW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E10_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACTX}{\*\bkmkend AAAAAAACTX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E10_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACTY}{\*\bkmkend AAAAAAACTY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E9_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000200u){\*\bkmkstart AAAAAAACTZ}{\*\bkmkend AAAAAAACTZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E9_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAACUA}{\*\bkmkend AAAAAAACUA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E9_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACUB}{\*\bkmkend AAAAAAACUB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E9_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACUC}{\*\bkmkend AAAAAAACUC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E8_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAACUD}{\*\bkmkend AAAAAAACUD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E8_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAACUE}{\*\bkmkend AAAAAAACUE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E8_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACUF}{\*\bkmkend AAAAAAACUF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E8_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACUG}{\*\bkmkend AAAAAAACUG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E7_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAACUH}{\*\bkmkend AAAAAAACUH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E7_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAACUI}{\*\bkmkend AAAAAAACUI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E7_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACUJ}{\*\bkmkend AAAAAAACUJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E7_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACUK}{\*\bkmkend AAAAAAACUK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E6_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAACUL}{\*\bkmkend AAAAAAACUL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E6_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAACUM}{\*\bkmkend AAAAAAACUM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E6_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACUN}{\*\bkmkend AAAAAAACUN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E6_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACUO}{\*\bkmkend AAAAAAACUO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E5_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAACUP}{\*\bkmkend AAAAAAACUP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E5_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAACUQ}{\*\bkmkend AAAAAAACUQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E5_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACUR}{\*\bkmkend AAAAAAACUR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E5_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACUS}{\*\bkmkend AAAAAAACUS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E4_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAACUT}{\*\bkmkend AAAAAAACUT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E4_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAACUU}{\*\bkmkend AAAAAAACUU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E4_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACUV}{\*\bkmkend AAAAAAACUV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E4_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACUW}{\*\bkmkend AAAAAAACUW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E3_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAACUX}{\*\bkmkend AAAAAAACUX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E3_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAACUY}{\*\bkmkend AAAAAAACUY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E3_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACUZ}{\*\bkmkend AAAAAAACUZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E3_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACVA}{\*\bkmkend AAAAAAACVA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E2_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAACVB}{\*\bkmkend AAAAAAACVB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E2_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAACVC}{\*\bkmkend AAAAAAACVC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E2_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACVD}{\*\bkmkend AAAAAAACVD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E2_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACVE}{\*\bkmkend AAAAAAACVE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E1_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAACVF}{\*\bkmkend AAAAAAACVF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E1_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACVG}{\*\bkmkend AAAAAAACVG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E1_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACVH}{\*\bkmkend AAAAAAACVH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E1_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACVI}{\*\bkmkend AAAAAAACVI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E0_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACVJ}{\*\bkmkend AAAAAAACVJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E0_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACVK}{\*\bkmkend AAAAAAACVK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E0_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACVL}{\*\bkmkend AAAAAAACVL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_E0_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACVM}{\*\bkmkend AAAAAAACVM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E63_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x80000000u){\*\bkmkstart AAAAAAACVO}{\*\bkmkend AAAAAAACVO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E63_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAACVP}{\*\bkmkend AAAAAAACVP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E63_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACVQ}{\*\bkmkend AAAAAAACVQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E63_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACVR}{\*\bkmkend AAAAAAACVR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E62_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x40000000u){\*\bkmkstart AAAAAAACVS}{\*\bkmkend AAAAAAACVS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E62_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Eu){\*\bkmkstart AAAAAAACVT}{\*\bkmkend AAAAAAACVT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E62_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACVU}{\*\bkmkend AAAAAAACVU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E62_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACVV}{\*\bkmkend AAAAAAACVV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E61_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x20000000u){\*\bkmkstart AAAAAAACVW}{\*\bkmkend AAAAAAACVW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E61_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Du){\*\bkmkstart AAAAAAACVX}{\*\bkmkend AAAAAAACVX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E61_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACVY}{\*\bkmkend AAAAAAACVY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E61_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACVZ}{\*\bkmkend AAAAAAACVZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E60_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x10000000u){\*\bkmkstart AAAAAAACWA}{\*\bkmkend AAAAAAACWA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E60_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAACWB}{\*\bkmkend AAAAAAACWB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E60_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACWC}{\*\bkmkend AAAAAAACWC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E60_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACWD}{\*\bkmkend AAAAAAACWD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E59_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x08000000u){\*\bkmkstart AAAAAAACWE}{\*\bkmkend AAAAAAACWE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E59_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Bu){\*\bkmkstart AAAAAAACWF}{\*\bkmkend AAAAAAACWF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E59_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACWG}{\*\bkmkend AAAAAAACWG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E59_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACWH}{\*\bkmkend AAAAAAACWH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E58_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x04000000u){\*\bkmkstart AAAAAAACWI}{\*\bkmkend AAAAAAACWI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E58_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Au){\*\bkmkstart AAAAAAACWJ}{\*\bkmkend AAAAAAACWJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E58_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACWK}{\*\bkmkend AAAAAAACWK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E58_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACWL}{\*\bkmkend AAAAAAACWL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E57_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x02000000u){\*\bkmkstart AAAAAAACWM}{\*\bkmkend AAAAAAACWM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E57_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000019u){\*\bkmkstart AAAAAAACWN}{\*\bkmkend AAAAAAACWN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E57_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACWO}{\*\bkmkend AAAAAAACWO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E57_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACWP}{\*\bkmkend AAAAAAACWP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E56_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x01000000u){\*\bkmkstart AAAAAAACWQ}{\*\bkmkend AAAAAAACWQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E56_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAACWR}{\*\bkmkend AAAAAAACWR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E56_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACWS}{\*\bkmkend AAAAAAACWS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E56_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACWT}{\*\bkmkend AAAAAAACWT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E55_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00800000u){\*\bkmkstart AAAAAAACWU}{\*\bkmkend AAAAAAACWU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E55_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000017u){\*\bkmkstart AAAAAAACWV}{\*\bkmkend AAAAAAACWV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E55_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACWW}{\*\bkmkend AAAAAAACWW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E55_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACWX}{\*\bkmkend AAAAAAACWX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E54_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAACWY}{\*\bkmkend AAAAAAACWY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E54_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAACWZ}{\*\bkmkend AAAAAAACWZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E54_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACXA}{\*\bkmkend AAAAAAACXA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E54_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACXB}{\*\bkmkend AAAAAAACXB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E53_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00200000u){\*\bkmkstart AAAAAAACXC}{\*\bkmkend AAAAAAACXC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E53_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAACXD}{\*\bkmkend AAAAAAACXD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E53_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACXE}{\*\bkmkend AAAAAAACXE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E53_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACXF}{\*\bkmkend AAAAAAACXF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E52_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAACXG}{\*\bkmkend AAAAAAACXG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E52_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAACXH}{\*\bkmkend AAAAAAACXH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E52_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACXI}{\*\bkmkend AAAAAAACXI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E52_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACXJ}{\*\bkmkend AAAAAAACXJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E51_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00080000u){\*\bkmkstart AAAAAAACXK}{\*\bkmkend AAAAAAACXK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E51_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000013u){\*\bkmkstart AAAAAAACXL}{\*\bkmkend AAAAAAACXL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E51_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACXM}{\*\bkmkend AAAAAAACXM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E51_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACXN}{\*\bkmkend AAAAAAACXN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E50_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00040000u){\*\bkmkstart AAAAAAACXO}{\*\bkmkend AAAAAAACXO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E50_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000012u){\*\bkmkstart AAAAAAACXP}{\*\bkmkend AAAAAAACXP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E50_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACXQ}{\*\bkmkend AAAAAAACXQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E50_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACXR}{\*\bkmkend AAAAAAACXR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E49_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00020000u){\*\bkmkstart AAAAAAACXS}{\*\bkmkend AAAAAAACXS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E49_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000011u){\*\bkmkstart AAAAAAACXT}{\*\bkmkend AAAAAAACXT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E49_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACXU}{\*\bkmkend AAAAAAACXU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E49_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACXV}{\*\bkmkend AAAAAAACXV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E48_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAACXW}{\*\bkmkend AAAAAAACXW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E48_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAACXX}{\*\bkmkend AAAAAAACXX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E48_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACXY}{\*\bkmkend AAAAAAACXY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E48_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACXZ}{\*\bkmkend AAAAAAACXZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E47_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00008000u){\*\bkmkstart AAAAAAACYA}{\*\bkmkend AAAAAAACYA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E47_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAACYB}{\*\bkmkend AAAAAAACYB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E47_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACYC}{\*\bkmkend AAAAAAACYC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E47_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACYD}{\*\bkmkend AAAAAAACYD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E46_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00004000u){\*\bkmkstart AAAAAAACYE}{\*\bkmkend AAAAAAACYE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E46_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Eu){\*\bkmkstart AAAAAAACYF}{\*\bkmkend AAAAAAACYF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E46_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACYG}{\*\bkmkend AAAAAAACYG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E46_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACYH}{\*\bkmkend AAAAAAACYH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E45_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00002000u){\*\bkmkstart AAAAAAACYI}{\*\bkmkend AAAAAAACYI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E45_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Du){\*\bkmkstart AAAAAAACYJ}{\*\bkmkend AAAAAAACYJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E45_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACYK}{\*\bkmkend AAAAAAACYK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E45_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACYL}{\*\bkmkend AAAAAAACYL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E44_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001000u){\*\bkmkstart AAAAAAACYM}{\*\bkmkend AAAAAAACYM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E44_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAACYN}{\*\bkmkend AAAAAAACYN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E44_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACYO}{\*\bkmkend AAAAAAACYO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E44_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACYP}{\*\bkmkend AAAAAAACYP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E43_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAACYQ}{\*\bkmkend AAAAAAACYQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E43_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAACYR}{\*\bkmkend AAAAAAACYR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E43_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACYS}{\*\bkmkend AAAAAAACYS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E43_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACYT}{\*\bkmkend AAAAAAACYT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E42_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000400u){\*\bkmkstart AAAAAAACYU}{\*\bkmkend AAAAAAACYU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E42_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAACYV}{\*\bkmkend AAAAAAACYV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E42_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACYW}{\*\bkmkend AAAAAAACYW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E42_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACYX}{\*\bkmkend AAAAAAACYX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E41_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000200u){\*\bkmkstart AAAAAAACYY}{\*\bkmkend AAAAAAACYY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E41_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAACYZ}{\*\bkmkend AAAAAAACYZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E41_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACZA}{\*\bkmkend AAAAAAACZA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E41_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACZB}{\*\bkmkend AAAAAAACZB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E40_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAACZC}{\*\bkmkend AAAAAAACZC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E40_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAACZD}{\*\bkmkend AAAAAAACZD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E40_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACZE}{\*\bkmkend AAAAAAACZE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E40_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACZF}{\*\bkmkend AAAAAAACZF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E39_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAACZG}{\*\bkmkend AAAAAAACZG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E39_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAACZH}{\*\bkmkend AAAAAAACZH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E39_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACZI}{\*\bkmkend AAAAAAACZI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E39_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACZJ}{\*\bkmkend AAAAAAACZJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E38_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAACZK}{\*\bkmkend AAAAAAACZK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E38_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAACZL}{\*\bkmkend AAAAAAACZL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E38_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACZM}{\*\bkmkend AAAAAAACZM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E38_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACZN}{\*\bkmkend AAAAAAACZN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E37_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAACZO}{\*\bkmkend AAAAAAACZO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E37_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAACZP}{\*\bkmkend AAAAAAACZP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E37_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACZQ}{\*\bkmkend AAAAAAACZQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E37_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACZR}{\*\bkmkend AAAAAAACZR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E36_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAACZS}{\*\bkmkend AAAAAAACZS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E36_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAACZT}{\*\bkmkend AAAAAAACZT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E36_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACZU}{\*\bkmkend AAAAAAACZU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E36_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACZV}{\*\bkmkend AAAAAAACZV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E35_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAACZW}{\*\bkmkend AAAAAAACZW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E35_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAACZX}{\*\bkmkend AAAAAAACZX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E35_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACZY}{\*\bkmkend AAAAAAACZY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E35_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAACZZ}{\*\bkmkend AAAAAAACZZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E34_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAADAA}{\*\bkmkend AAAAAAADAA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E34_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAADAB}{\*\bkmkend AAAAAAADAB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E34_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADAC}{\*\bkmkend AAAAAAADAC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E34_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADAD}{\*\bkmkend AAAAAAADAD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E33_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAADAE}{\*\bkmkend AAAAAAADAE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E33_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADAF}{\*\bkmkend AAAAAAADAF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E33_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADAG}{\*\bkmkend AAAAAAADAG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E33_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADAH}{\*\bkmkend AAAAAAADAH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E32_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADAI}{\*\bkmkend AAAAAAADAI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E32_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADAJ}{\*\bkmkend AAAAAAADAJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E32_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADAK}{\*\bkmkend AAAAAAADAK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_E32_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADAL}{\*\bkmkend AAAAAAADAL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E31_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x80000000u){\*\bkmkstart AAAAAAADAN}{\*\bkmkend AAAAAAADAN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E31_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAADAO}{\*\bkmkend AAAAAAADAO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E31_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADAP}{\*\bkmkend AAAAAAADAP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E30_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x40000000u){\*\bkmkstart AAAAAAADAQ}{\*\bkmkend AAAAAAADAQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E30_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Eu){\*\bkmkstart AAAAAAADAR}{\*\bkmkend AAAAAAADAR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E30_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADAS}{\*\bkmkend AAAAAAADAS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E29_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x20000000u){\*\bkmkstart AAAAAAADAT}{\*\bkmkend AAAAAAADAT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E29_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Du){\*\bkmkstart AAAAAAADAU}{\*\bkmkend AAAAAAADAU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E29_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADAV}{\*\bkmkend AAAAAAADAV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E28_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x10000000u){\*\bkmkstart AAAAAAADAW}{\*\bkmkend AAAAAAADAW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E28_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAADAX}{\*\bkmkend AAAAAAADAX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E28_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADAY}{\*\bkmkend AAAAAAADAY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E27_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x08000000u){\*\bkmkstart AAAAAAADAZ}{\*\bkmkend AAAAAAADAZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E27_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Bu){\*\bkmkstart AAAAAAADBA}{\*\bkmkend AAAAAAADBA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E27_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADBB}{\*\bkmkend AAAAAAADBB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E26_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x04000000u){\*\bkmkstart AAAAAAADBC}{\*\bkmkend AAAAAAADBC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E26_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Au){\*\bkmkstart AAAAAAADBD}{\*\bkmkend AAAAAAADBD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E26_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADBE}{\*\bkmkend AAAAAAADBE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E25_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x02000000u){\*\bkmkstart AAAAAAADBF}{\*\bkmkend AAAAAAADBF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E25_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000019u){\*\bkmkstart AAAAAAADBG}{\*\bkmkend AAAAAAADBG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E25_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADBH}{\*\bkmkend AAAAAAADBH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E24_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x01000000u){\*\bkmkstart AAAAAAADBI}{\*\bkmkend AAAAAAADBI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E24_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAADBJ}{\*\bkmkend AAAAAAADBJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E24_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADBK}{\*\bkmkend AAAAAAADBK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E23_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00800000u){\*\bkmkstart AAAAAAADBL}{\*\bkmkend AAAAAAADBL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E23_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000017u){\*\bkmkstart AAAAAAADBM}{\*\bkmkend AAAAAAADBM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E23_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADBN}{\*\bkmkend AAAAAAADBN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E22_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAADBO}{\*\bkmkend AAAAAAADBO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E22_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAADBP}{\*\bkmkend AAAAAAADBP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E22_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADBQ}{\*\bkmkend AAAAAAADBQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E21_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00200000u){\*\bkmkstart AAAAAAADBR}{\*\bkmkend AAAAAAADBR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E21_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAADBS}{\*\bkmkend AAAAAAADBS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E21_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADBT}{\*\bkmkend AAAAAAADBT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E20_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAADBU}{\*\bkmkend AAAAAAADBU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E20_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAADBV}{\*\bkmkend AAAAAAADBV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E20_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADBW}{\*\bkmkend AAAAAAADBW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E19_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00080000u){\*\bkmkstart AAAAAAADBX}{\*\bkmkend AAAAAAADBX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E19_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000013u){\*\bkmkstart AAAAAAADBY}{\*\bkmkend AAAAAAADBY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E19_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADBZ}{\*\bkmkend AAAAAAADBZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E18_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00040000u){\*\bkmkstart AAAAAAADCA}{\*\bkmkend AAAAAAADCA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E18_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000012u){\*\bkmkstart AAAAAAADCB}{\*\bkmkend AAAAAAADCB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E18_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADCC}{\*\bkmkend AAAAAAADCC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E17_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00020000u){\*\bkmkstart AAAAAAADCD}{\*\bkmkend AAAAAAADCD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E17_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000011u){\*\bkmkstart AAAAAAADCE}{\*\bkmkend AAAAAAADCE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E17_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADCF}{\*\bkmkend AAAAAAADCF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E16_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAADCG}{\*\bkmkend AAAAAAADCG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E16_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAADCH}{\*\bkmkend AAAAAAADCH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E16_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADCI}{\*\bkmkend AAAAAAADCI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E15_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00008000u){\*\bkmkstart AAAAAAADCJ}{\*\bkmkend AAAAAAADCJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E15_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAADCK}{\*\bkmkend AAAAAAADCK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E15_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADCL}{\*\bkmkend AAAAAAADCL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E14_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00004000u){\*\bkmkstart AAAAAAADCM}{\*\bkmkend AAAAAAADCM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E14_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Eu){\*\bkmkstart AAAAAAADCN}{\*\bkmkend AAAAAAADCN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E14_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADCO}{\*\bkmkend AAAAAAADCO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E13_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00002000u){\*\bkmkstart AAAAAAADCP}{\*\bkmkend AAAAAAADCP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E13_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Du){\*\bkmkstart AAAAAAADCQ}{\*\bkmkend AAAAAAADCQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E13_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADCR}{\*\bkmkend AAAAAAADCR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E12_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001000u){\*\bkmkstart AAAAAAADCS}{\*\bkmkend AAAAAAADCS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E12_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAADCT}{\*\bkmkend AAAAAAADCT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E12_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADCU}{\*\bkmkend AAAAAAADCU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E11_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAADCV}{\*\bkmkend AAAAAAADCV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E11_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAADCW}{\*\bkmkend AAAAAAADCW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E11_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADCX}{\*\bkmkend AAAAAAADCX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E10_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000400u){\*\bkmkstart AAAAAAADCY}{\*\bkmkend AAAAAAADCY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E10_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAADCZ}{\*\bkmkend AAAAAAADCZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E10_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADDA}{\*\bkmkend AAAAAAADDA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E9_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000200u){\*\bkmkstart AAAAAAADDB}{\*\bkmkend AAAAAAADDB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E9_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAADDC}{\*\bkmkend AAAAAAADDC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E9_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADDD}{\*\bkmkend AAAAAAADDD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E8_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAADDE}{\*\bkmkend AAAAAAADDE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E8_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAADDF}{\*\bkmkend AAAAAAADDF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E8_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADDG}{\*\bkmkend AAAAAAADDG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E7_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAADDH}{\*\bkmkend AAAAAAADDH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E7_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAADDI}{\*\bkmkend AAAAAAADDI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E7_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADDJ}{\*\bkmkend AAAAAAADDJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E6_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAADDK}{\*\bkmkend AAAAAAADDK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E6_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAADDL}{\*\bkmkend AAAAAAADDL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E6_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADDM}{\*\bkmkend AAAAAAADDM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E5_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAADDN}{\*\bkmkend AAAAAAADDN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E5_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAADDO}{\*\bkmkend AAAAAAADDO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E5_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADDP}{\*\bkmkend AAAAAAADDP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E4_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAADDQ}{\*\bkmkend AAAAAAADDQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E4_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAADDR}{\*\bkmkend AAAAAAADDR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E4_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADDS}{\*\bkmkend AAAAAAADDS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E3_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAADDT}{\*\bkmkend AAAAAAADDT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E3_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAADDU}{\*\bkmkend AAAAAAADDU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E3_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADDV}{\*\bkmkend AAAAAAADDV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E2_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAADDW}{\*\bkmkend AAAAAAADDW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E2_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAADDX}{\*\bkmkend AAAAAAADDX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E2_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADDY}{\*\bkmkend AAAAAAADDY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E1_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAADDZ}{\*\bkmkend AAAAAAADDZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E1_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADEA}{\*\bkmkend AAAAAAADEA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E1_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADEB}{\*\bkmkend AAAAAAADEB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E0_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADEC}{\*\bkmkend AAAAAAADEC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E0_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADED}{\*\bkmkend AAAAAAADED} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_E0_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADEE}{\*\bkmkend AAAAAAADEE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E63_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x80000000u){\*\bkmkstart AAAAAAADEG}{\*\bkmkend AAAAAAADEG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E63_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAADEH}{\*\bkmkend AAAAAAADEH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E63_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADEI}{\*\bkmkend AAAAAAADEI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E62_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x40000000u){\*\bkmkstart AAAAAAADEJ}{\*\bkmkend AAAAAAADEJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E62_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Eu){\*\bkmkstart AAAAAAADEK}{\*\bkmkend AAAAAAADEK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E62_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADEL}{\*\bkmkend AAAAAAADEL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E61_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x20000000u){\*\bkmkstart AAAAAAADEM}{\*\bkmkend AAAAAAADEM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E61_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Du){\*\bkmkstart AAAAAAADEN}{\*\bkmkend AAAAAAADEN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E61_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADEO}{\*\bkmkend AAAAAAADEO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E60_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x10000000u){\*\bkmkstart AAAAAAADEP}{\*\bkmkend AAAAAAADEP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E60_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAADEQ}{\*\bkmkend AAAAAAADEQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E60_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADER}{\*\bkmkend AAAAAAADER} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E59_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x08000000u){\*\bkmkstart AAAAAAADES}{\*\bkmkend AAAAAAADES} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E59_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Bu){\*\bkmkstart AAAAAAADET}{\*\bkmkend AAAAAAADET} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E59_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADEU}{\*\bkmkend AAAAAAADEU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E58_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x04000000u){\*\bkmkstart AAAAAAADEV}{\*\bkmkend AAAAAAADEV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E58_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Au){\*\bkmkstart AAAAAAADEW}{\*\bkmkend AAAAAAADEW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E58_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADEX}{\*\bkmkend AAAAAAADEX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E57_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x02000000u){\*\bkmkstart AAAAAAADEY}{\*\bkmkend AAAAAAADEY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E57_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000019u){\*\bkmkstart AAAAAAADEZ}{\*\bkmkend AAAAAAADEZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E57_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADFA}{\*\bkmkend AAAAAAADFA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E56_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x01000000u){\*\bkmkstart AAAAAAADFB}{\*\bkmkend AAAAAAADFB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E56_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAADFC}{\*\bkmkend AAAAAAADFC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E56_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADFD}{\*\bkmkend AAAAAAADFD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E55_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00800000u){\*\bkmkstart AAAAAAADFE}{\*\bkmkend AAAAAAADFE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E55_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000017u){\*\bkmkstart AAAAAAADFF}{\*\bkmkend AAAAAAADFF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E55_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADFG}{\*\bkmkend AAAAAAADFG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E54_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAADFH}{\*\bkmkend AAAAAAADFH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E54_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAADFI}{\*\bkmkend AAAAAAADFI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E54_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADFJ}{\*\bkmkend AAAAAAADFJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E53_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00200000u){\*\bkmkstart AAAAAAADFK}{\*\bkmkend AAAAAAADFK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E53_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAADFL}{\*\bkmkend AAAAAAADFL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E53_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADFM}{\*\bkmkend AAAAAAADFM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E52_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAADFN}{\*\bkmkend AAAAAAADFN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E52_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAADFO}{\*\bkmkend AAAAAAADFO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E52_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADFP}{\*\bkmkend AAAAAAADFP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E51_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00080000u){\*\bkmkstart AAAAAAADFQ}{\*\bkmkend AAAAAAADFQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E51_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000013u){\*\bkmkstart AAAAAAADFR}{\*\bkmkend AAAAAAADFR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E51_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADFS}{\*\bkmkend AAAAAAADFS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E50_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00040000u){\*\bkmkstart AAAAAAADFT}{\*\bkmkend AAAAAAADFT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E50_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000012u){\*\bkmkstart AAAAAAADFU}{\*\bkmkend AAAAAAADFU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E50_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADFV}{\*\bkmkend AAAAAAADFV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E49_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00020000u){\*\bkmkstart AAAAAAADFW}{\*\bkmkend AAAAAAADFW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E49_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000011u){\*\bkmkstart AAAAAAADFX}{\*\bkmkend AAAAAAADFX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E49_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADFY}{\*\bkmkend AAAAAAADFY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E48_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAADFZ}{\*\bkmkend AAAAAAADFZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E48_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAADGA}{\*\bkmkend AAAAAAADGA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E48_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADGB}{\*\bkmkend AAAAAAADGB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E47_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00008000u){\*\bkmkstart AAAAAAADGC}{\*\bkmkend AAAAAAADGC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E47_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAADGD}{\*\bkmkend AAAAAAADGD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E47_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADGE}{\*\bkmkend AAAAAAADGE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E46_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00004000u){\*\bkmkstart AAAAAAADGF}{\*\bkmkend AAAAAAADGF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E46_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Eu){\*\bkmkstart AAAAAAADGG}{\*\bkmkend AAAAAAADGG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E46_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADGH}{\*\bkmkend AAAAAAADGH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E45_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00002000u){\*\bkmkstart AAAAAAADGI}{\*\bkmkend AAAAAAADGI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E45_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Du){\*\bkmkstart AAAAAAADGJ}{\*\bkmkend AAAAAAADGJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E45_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADGK}{\*\bkmkend AAAAAAADGK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E44_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001000u){\*\bkmkstart AAAAAAADGL}{\*\bkmkend AAAAAAADGL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E44_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAADGM}{\*\bkmkend AAAAAAADGM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E44_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADGN}{\*\bkmkend AAAAAAADGN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E43_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAADGO}{\*\bkmkend AAAAAAADGO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E43_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAADGP}{\*\bkmkend AAAAAAADGP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E43_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADGQ}{\*\bkmkend AAAAAAADGQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E42_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000400u){\*\bkmkstart AAAAAAADGR}{\*\bkmkend AAAAAAADGR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E42_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAADGS}{\*\bkmkend AAAAAAADGS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E42_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADGT}{\*\bkmkend AAAAAAADGT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E41_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000200u){\*\bkmkstart AAAAAAADGU}{\*\bkmkend AAAAAAADGU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E41_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAADGV}{\*\bkmkend AAAAAAADGV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E41_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADGW}{\*\bkmkend AAAAAAADGW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E40_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAADGX}{\*\bkmkend AAAAAAADGX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E40_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAADGY}{\*\bkmkend AAAAAAADGY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E40_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADGZ}{\*\bkmkend AAAAAAADGZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E39_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAADHA}{\*\bkmkend AAAAAAADHA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E39_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAADHB}{\*\bkmkend AAAAAAADHB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E39_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADHC}{\*\bkmkend AAAAAAADHC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E38_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAADHD}{\*\bkmkend AAAAAAADHD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E38_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAADHE}{\*\bkmkend AAAAAAADHE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E38_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADHF}{\*\bkmkend AAAAAAADHF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E37_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAADHG}{\*\bkmkend AAAAAAADHG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E37_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAADHH}{\*\bkmkend AAAAAAADHH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E37_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADHI}{\*\bkmkend AAAAAAADHI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E36_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAADHJ}{\*\bkmkend AAAAAAADHJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E36_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAADHK}{\*\bkmkend AAAAAAADHK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E36_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADHL}{\*\bkmkend AAAAAAADHL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E35_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAADHM}{\*\bkmkend AAAAAAADHM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E35_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAADHN}{\*\bkmkend AAAAAAADHN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E35_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADHO}{\*\bkmkend AAAAAAADHO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E34_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAADHP}{\*\bkmkend AAAAAAADHP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E34_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAADHQ}{\*\bkmkend AAAAAAADHQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E34_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADHR}{\*\bkmkend AAAAAAADHR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E33_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAADHS}{\*\bkmkend AAAAAAADHS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E33_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADHT}{\*\bkmkend AAAAAAADHT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E33_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADHU}{\*\bkmkend AAAAAAADHU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E32_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADHV}{\*\bkmkend AAAAAAADHV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E32_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADHW}{\*\bkmkend AAAAAAADHW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_E32_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADHX}{\*\bkmkend AAAAAAADHX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E31_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x80000000u){\*\bkmkstart AAAAAAADHZ}{\*\bkmkend AAAAAAADHZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E31_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAADIA}{\*\bkmkend AAAAAAADIA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E31_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADIB}{\*\bkmkend AAAAAAADIB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E31_}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADIC}{\*\bkmkend AAAAAAADIC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E30_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x40000000u){\*\bkmkstart AAAAAAADID}{\*\bkmkend AAAAAAADID} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E30_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Eu){\*\bkmkstart AAAAAAADIE}{\*\bkmkend AAAAAAADIE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E30_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADIF}{\*\bkmkend AAAAAAADIF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E29_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x20000000u){\*\bkmkstart AAAAAAADIG}{\*\bkmkend AAAAAAADIG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E29_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Du){\*\bkmkstart AAAAAAADIH}{\*\bkmkend AAAAAAADIH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E29_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADII}{\*\bkmkend AAAAAAADII} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E28_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x10000000u){\*\bkmkstart AAAAAAADIJ}{\*\bkmkend AAAAAAADIJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E28_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAADIK}{\*\bkmkend AAAAAAADIK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E28_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADIL}{\*\bkmkend AAAAAAADIL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E27_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x08000000u){\*\bkmkstart AAAAAAADIM}{\*\bkmkend AAAAAAADIM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E27_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Bu){\*\bkmkstart AAAAAAADIN}{\*\bkmkend AAAAAAADIN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E27_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADIO}{\*\bkmkend AAAAAAADIO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E26_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x04000000u){\*\bkmkstart AAAAAAADIP}{\*\bkmkend AAAAAAADIP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E26_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Au){\*\bkmkstart AAAAAAADIQ}{\*\bkmkend AAAAAAADIQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E26_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADIR}{\*\bkmkend AAAAAAADIR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E25_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x02000000u){\*\bkmkstart AAAAAAADIS}{\*\bkmkend AAAAAAADIS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E25_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000019u){\*\bkmkstart AAAAAAADIT}{\*\bkmkend AAAAAAADIT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E25_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADIU}{\*\bkmkend AAAAAAADIU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E24_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x01000000u){\*\bkmkstart AAAAAAADIV}{\*\bkmkend AAAAAAADIV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E24_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAADIW}{\*\bkmkend AAAAAAADIW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E24_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADIX}{\*\bkmkend AAAAAAADIX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E23_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00800000u){\*\bkmkstart AAAAAAADIY}{\*\bkmkend AAAAAAADIY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E23_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000017u){\*\bkmkstart AAAAAAADIZ}{\*\bkmkend AAAAAAADIZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E23_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADJA}{\*\bkmkend AAAAAAADJA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E22_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAADJB}{\*\bkmkend AAAAAAADJB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E22_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAADJC}{\*\bkmkend AAAAAAADJC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E22_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADJD}{\*\bkmkend AAAAAAADJD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E21_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00200000u){\*\bkmkstart AAAAAAADJE}{\*\bkmkend AAAAAAADJE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E21_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAADJF}{\*\bkmkend AAAAAAADJF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E21_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADJG}{\*\bkmkend AAAAAAADJG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E20_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAADJH}{\*\bkmkend AAAAAAADJH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E20_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAADJI}{\*\bkmkend AAAAAAADJI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E20_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADJJ}{\*\bkmkend AAAAAAADJJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E19_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00080000u){\*\bkmkstart AAAAAAADJK}{\*\bkmkend AAAAAAADJK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E19_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000013u){\*\bkmkstart AAAAAAADJL}{\*\bkmkend AAAAAAADJL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E19_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADJM}{\*\bkmkend AAAAAAADJM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E18_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00040000u){\*\bkmkstart AAAAAAADJN}{\*\bkmkend AAAAAAADJN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E18_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000012u){\*\bkmkstart AAAAAAADJO}{\*\bkmkend AAAAAAADJO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E18_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADJP}{\*\bkmkend AAAAAAADJP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E17_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00020000u){\*\bkmkstart AAAAAAADJQ}{\*\bkmkend AAAAAAADJQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E17_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000011u){\*\bkmkstart AAAAAAADJR}{\*\bkmkend AAAAAAADJR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E17_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADJS}{\*\bkmkend AAAAAAADJS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E16_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAADJT}{\*\bkmkend AAAAAAADJT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E16_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAADJU}{\*\bkmkend AAAAAAADJU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E16_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADJV}{\*\bkmkend AAAAAAADJV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E15_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00008000u){\*\bkmkstart AAAAAAADJW}{\*\bkmkend AAAAAAADJW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E15_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAADJX}{\*\bkmkend AAAAAAADJX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E15_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADJY}{\*\bkmkend AAAAAAADJY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E14_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00004000u){\*\bkmkstart AAAAAAADJZ}{\*\bkmkend AAAAAAADJZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E14_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Eu){\*\bkmkstart AAAAAAADKA}{\*\bkmkend AAAAAAADKA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E14_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADKB}{\*\bkmkend AAAAAAADKB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E13_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00002000u){\*\bkmkstart AAAAAAADKC}{\*\bkmkend AAAAAAADKC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E13_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Du){\*\bkmkstart AAAAAAADKD}{\*\bkmkend AAAAAAADKD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E13_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADKE}{\*\bkmkend AAAAAAADKE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E12_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001000u){\*\bkmkstart AAAAAAADKF}{\*\bkmkend AAAAAAADKF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E12_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAADKG}{\*\bkmkend AAAAAAADKG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E12_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADKH}{\*\bkmkend AAAAAAADKH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E11_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAADKI}{\*\bkmkend AAAAAAADKI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E11_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAADKJ}{\*\bkmkend AAAAAAADKJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E11_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADKK}{\*\bkmkend AAAAAAADKK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E10_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000400u){\*\bkmkstart AAAAAAADKL}{\*\bkmkend AAAAAAADKL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E10_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAADKM}{\*\bkmkend AAAAAAADKM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E10_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADKN}{\*\bkmkend AAAAAAADKN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E9_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000200u){\*\bkmkstart AAAAAAADKO}{\*\bkmkend AAAAAAADKO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E9_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAADKP}{\*\bkmkend AAAAAAADKP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E9_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADKQ}{\*\bkmkend AAAAAAADKQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E8_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAADKR}{\*\bkmkend AAAAAAADKR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E8_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAADKS}{\*\bkmkend AAAAAAADKS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E8_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADKT}{\*\bkmkend AAAAAAADKT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E7_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAADKU}{\*\bkmkend AAAAAAADKU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E7_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAADKV}{\*\bkmkend AAAAAAADKV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E7_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADKW}{\*\bkmkend AAAAAAADKW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E6_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAADKX}{\*\bkmkend AAAAAAADKX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E6_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAADKY}{\*\bkmkend AAAAAAADKY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E6_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADKZ}{\*\bkmkend AAAAAAADKZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E5_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAADLA}{\*\bkmkend AAAAAAADLA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E5_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAADLB}{\*\bkmkend AAAAAAADLB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E5_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADLC}{\*\bkmkend AAAAAAADLC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E4_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAADLD}{\*\bkmkend AAAAAAADLD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E4_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAADLE}{\*\bkmkend AAAAAAADLE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E4_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADLF}{\*\bkmkend AAAAAAADLF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E3_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAADLG}{\*\bkmkend AAAAAAADLG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E3_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAADLH}{\*\bkmkend AAAAAAADLH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E3_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADLI}{\*\bkmkend AAAAAAADLI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E2_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAADLJ}{\*\bkmkend AAAAAAADLJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E2_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAADLK}{\*\bkmkend AAAAAAADLK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E2_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADLL}{\*\bkmkend AAAAAAADLL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E1_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAADLM}{\*\bkmkend AAAAAAADLM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E1_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADLN}{\*\bkmkend AAAAAAADLN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E1_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADLO}{\*\bkmkend AAAAAAADLO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E0_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADLP}{\*\bkmkend AAAAAAADLP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E0_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADLQ}{\*\bkmkend AAAAAAADLQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_E0_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADLR}{\*\bkmkend AAAAAAADLR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E63_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x80000000u){\*\bkmkstart AAAAAAADLT}{\*\bkmkend AAAAAAADLT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E63_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAADLU}{\*\bkmkend AAAAAAADLU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E63_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADLV}{\*\bkmkend AAAAAAADLV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E62_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x40000000u){\*\bkmkstart AAAAAAADLW}{\*\bkmkend AAAAAAADLW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E62_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Eu){\*\bkmkstart AAAAAAADLX}{\*\bkmkend AAAAAAADLX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E62_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADLY}{\*\bkmkend AAAAAAADLY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E61_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x20000000u){\*\bkmkstart AAAAAAADLZ}{\*\bkmkend AAAAAAADLZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E61_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Du){\*\bkmkstart AAAAAAADMA}{\*\bkmkend AAAAAAADMA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E61_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADMB}{\*\bkmkend AAAAAAADMB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E60_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x10000000u){\*\bkmkstart AAAAAAADMC}{\*\bkmkend AAAAAAADMC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E60_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAADMD}{\*\bkmkend AAAAAAADMD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E60_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADME}{\*\bkmkend AAAAAAADME} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E59_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x08000000u){\*\bkmkstart AAAAAAADMF}{\*\bkmkend AAAAAAADMF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E59_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Bu){\*\bkmkstart AAAAAAADMG}{\*\bkmkend AAAAAAADMG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E59_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADMH}{\*\bkmkend AAAAAAADMH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E58_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x04000000u){\*\bkmkstart AAAAAAADMI}{\*\bkmkend AAAAAAADMI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E58_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Au){\*\bkmkstart AAAAAAADMJ}{\*\bkmkend AAAAAAADMJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E58_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADMK}{\*\bkmkend AAAAAAADMK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E57_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x02000000u){\*\bkmkstart AAAAAAADML}{\*\bkmkend AAAAAAADML} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E57_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000019u){\*\bkmkstart AAAAAAADMM}{\*\bkmkend AAAAAAADMM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E57_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADMN}{\*\bkmkend AAAAAAADMN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E56_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x01000000u){\*\bkmkstart AAAAAAADMO}{\*\bkmkend AAAAAAADMO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E56_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAADMP}{\*\bkmkend AAAAAAADMP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E56_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADMQ}{\*\bkmkend AAAAAAADMQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E55_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00800000u){\*\bkmkstart AAAAAAADMR}{\*\bkmkend AAAAAAADMR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E55_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000017u){\*\bkmkstart AAAAAAADMS}{\*\bkmkend AAAAAAADMS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E55_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADMT}{\*\bkmkend AAAAAAADMT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E54_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAADMU}{\*\bkmkend AAAAAAADMU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E54_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAADMV}{\*\bkmkend AAAAAAADMV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E54_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADMW}{\*\bkmkend AAAAAAADMW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E53_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00200000u){\*\bkmkstart AAAAAAADMX}{\*\bkmkend AAAAAAADMX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E53_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAADMY}{\*\bkmkend AAAAAAADMY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E53_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADMZ}{\*\bkmkend AAAAAAADMZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E52_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAADNA}{\*\bkmkend AAAAAAADNA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E52_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAADNB}{\*\bkmkend AAAAAAADNB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E52_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADNC}{\*\bkmkend AAAAAAADNC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E51_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00080000u){\*\bkmkstart AAAAAAADND}{\*\bkmkend AAAAAAADND} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E51_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000013u){\*\bkmkstart AAAAAAADNE}{\*\bkmkend AAAAAAADNE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E51_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADNF}{\*\bkmkend AAAAAAADNF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E50_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00040000u){\*\bkmkstart AAAAAAADNG}{\*\bkmkend AAAAAAADNG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E50_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000012u){\*\bkmkstart AAAAAAADNH}{\*\bkmkend AAAAAAADNH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E50_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADNI}{\*\bkmkend AAAAAAADNI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E49_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00020000u){\*\bkmkstart AAAAAAADNJ}{\*\bkmkend AAAAAAADNJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E49_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000011u){\*\bkmkstart AAAAAAADNK}{\*\bkmkend AAAAAAADNK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E49_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADNL}{\*\bkmkend AAAAAAADNL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E48_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAADNM}{\*\bkmkend AAAAAAADNM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E48_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAADNN}{\*\bkmkend AAAAAAADNN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E48_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADNO}{\*\bkmkend AAAAAAADNO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E47_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00008000u){\*\bkmkstart AAAAAAADNP}{\*\bkmkend AAAAAAADNP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E47_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAADNQ}{\*\bkmkend AAAAAAADNQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E47_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADNR}{\*\bkmkend AAAAAAADNR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E46_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00004000u){\*\bkmkstart AAAAAAADNS}{\*\bkmkend AAAAAAADNS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E46_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Eu){\*\bkmkstart AAAAAAADNT}{\*\bkmkend AAAAAAADNT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E46_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADNU}{\*\bkmkend AAAAAAADNU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E45_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00002000u){\*\bkmkstart AAAAAAADNV}{\*\bkmkend AAAAAAADNV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E45_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Du){\*\bkmkstart AAAAAAADNW}{\*\bkmkend AAAAAAADNW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E45_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADNX}{\*\bkmkend AAAAAAADNX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E44_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001000u){\*\bkmkstart AAAAAAADNY}{\*\bkmkend AAAAAAADNY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E44_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAADNZ}{\*\bkmkend AAAAAAADNZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E44_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADOA}{\*\bkmkend AAAAAAADOA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E43_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAADOB}{\*\bkmkend AAAAAAADOB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E43_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAADOC}{\*\bkmkend AAAAAAADOC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E43_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADOD}{\*\bkmkend AAAAAAADOD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E42_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000400u){\*\bkmkstart AAAAAAADOE}{\*\bkmkend AAAAAAADOE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E42_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAADOF}{\*\bkmkend AAAAAAADOF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E42_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADOG}{\*\bkmkend AAAAAAADOG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E41_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000200u){\*\bkmkstart AAAAAAADOH}{\*\bkmkend AAAAAAADOH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E41_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAADOI}{\*\bkmkend AAAAAAADOI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E41_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADOJ}{\*\bkmkend AAAAAAADOJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E40_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAADOK}{\*\bkmkend AAAAAAADOK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E40_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAADOL}{\*\bkmkend AAAAAAADOL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E40_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADOM}{\*\bkmkend AAAAAAADOM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E39_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAADON}{\*\bkmkend AAAAAAADON} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E39_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAADOO}{\*\bkmkend AAAAAAADOO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E39_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADOP}{\*\bkmkend AAAAAAADOP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E38_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAADOQ}{\*\bkmkend AAAAAAADOQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E38_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAADOR}{\*\bkmkend AAAAAAADOR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E38_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADOS}{\*\bkmkend AAAAAAADOS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E37_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAADOT}{\*\bkmkend AAAAAAADOT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E37_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAADOU}{\*\bkmkend AAAAAAADOU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E37_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADOV}{\*\bkmkend AAAAAAADOV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E36_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAADOW}{\*\bkmkend AAAAAAADOW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E36_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAADOX}{\*\bkmkend AAAAAAADOX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E36_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADOY}{\*\bkmkend AAAAAAADOY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E35_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAADOZ}{\*\bkmkend AAAAAAADOZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E35_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAADPA}{\*\bkmkend AAAAAAADPA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E35_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADPB}{\*\bkmkend AAAAAAADPB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E34_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAADPC}{\*\bkmkend AAAAAAADPC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E34_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAADPD}{\*\bkmkend AAAAAAADPD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E34_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADPE}{\*\bkmkend AAAAAAADPE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E33_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAADPF}{\*\bkmkend AAAAAAADPF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E33_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADPG}{\*\bkmkend AAAAAAADPG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E33_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADPH}{\*\bkmkend AAAAAAADPH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E32_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADPI}{\*\bkmkend AAAAAAADPI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E32_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADPJ}{\*\bkmkend AAAAAAADPJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_E32_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADPK}{\*\bkmkend AAAAAAADPK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E31_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x80000000u){\*\bkmkstart AAAAAAADPM}{\*\bkmkend AAAAAAADPM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E31_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAADPN}{\*\bkmkend AAAAAAADPN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E31_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADPO}{\*\bkmkend AAAAAAADPO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E31_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADPP}{\*\bkmkend AAAAAAADPP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E30_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x40000000u){\*\bkmkstart AAAAAAADPQ}{\*\bkmkend AAAAAAADPQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E30_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Eu){\*\bkmkstart AAAAAAADPR}{\*\bkmkend AAAAAAADPR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E30_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADPS}{\*\bkmkend AAAAAAADPS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E30_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADPT}{\*\bkmkend AAAAAAADPT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E29_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x20000000u){\*\bkmkstart AAAAAAADPU}{\*\bkmkend AAAAAAADPU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E29_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Du){\*\bkmkstart AAAAAAADPV}{\*\bkmkend AAAAAAADPV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E29_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADPW}{\*\bkmkend AAAAAAADPW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E29_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADPX}{\*\bkmkend AAAAAAADPX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E28_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x10000000u){\*\bkmkstart AAAAAAADPY}{\*\bkmkend AAAAAAADPY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E28_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAADPZ}{\*\bkmkend AAAAAAADPZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E28_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADQA}{\*\bkmkend AAAAAAADQA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E28_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADQB}{\*\bkmkend AAAAAAADQB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E27_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x08000000u){\*\bkmkstart AAAAAAADQC}{\*\bkmkend AAAAAAADQC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E27_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Bu){\*\bkmkstart AAAAAAADQD}{\*\bkmkend AAAAAAADQD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E27_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADQE}{\*\bkmkend AAAAAAADQE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E27_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADQF}{\*\bkmkend AAAAAAADQF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E26_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x04000000u){\*\bkmkstart AAAAAAADQG}{\*\bkmkend AAAAAAADQG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E26_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Au){\*\bkmkstart AAAAAAADQH}{\*\bkmkend AAAAAAADQH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E26_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADQI}{\*\bkmkend AAAAAAADQI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E26_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADQJ}{\*\bkmkend AAAAAAADQJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E25_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x02000000u){\*\bkmkstart AAAAAAADQK}{\*\bkmkend AAAAAAADQK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E25_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000019u){\*\bkmkstart AAAAAAADQL}{\*\bkmkend AAAAAAADQL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E25_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADQM}{\*\bkmkend AAAAAAADQM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E25_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADQN}{\*\bkmkend AAAAAAADQN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E24_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x01000000u){\*\bkmkstart AAAAAAADQO}{\*\bkmkend AAAAAAADQO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E24_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAADQP}{\*\bkmkend AAAAAAADQP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E24_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADQQ}{\*\bkmkend AAAAAAADQQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E24_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADQR}{\*\bkmkend AAAAAAADQR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E23_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00800000u){\*\bkmkstart AAAAAAADQS}{\*\bkmkend AAAAAAADQS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E23_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000017u){\*\bkmkstart AAAAAAADQT}{\*\bkmkend AAAAAAADQT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E23_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADQU}{\*\bkmkend AAAAAAADQU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E23_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADQV}{\*\bkmkend AAAAAAADQV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E22_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAADQW}{\*\bkmkend AAAAAAADQW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E22_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAADQX}{\*\bkmkend AAAAAAADQX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E22_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADQY}{\*\bkmkend AAAAAAADQY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E22_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADQZ}{\*\bkmkend AAAAAAADQZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E21_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00200000u){\*\bkmkstart AAAAAAADRA}{\*\bkmkend AAAAAAADRA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E21_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAADRB}{\*\bkmkend AAAAAAADRB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E21_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADRC}{\*\bkmkend AAAAAAADRC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E21_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADRD}{\*\bkmkend AAAAAAADRD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E20_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAADRE}{\*\bkmkend AAAAAAADRE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E20_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAADRF}{\*\bkmkend AAAAAAADRF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E20_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADRG}{\*\bkmkend AAAAAAADRG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E20_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADRH}{\*\bkmkend AAAAAAADRH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E19_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00080000u){\*\bkmkstart AAAAAAADRI}{\*\bkmkend AAAAAAADRI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E19_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000013u){\*\bkmkstart AAAAAAADRJ}{\*\bkmkend AAAAAAADRJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E19_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADRK}{\*\bkmkend AAAAAAADRK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E19_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADRL}{\*\bkmkend AAAAAAADRL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E18_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00040000u){\*\bkmkstart AAAAAAADRM}{\*\bkmkend AAAAAAADRM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E18_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000012u){\*\bkmkstart AAAAAAADRN}{\*\bkmkend AAAAAAADRN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E18_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADRO}{\*\bkmkend AAAAAAADRO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E18_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADRP}{\*\bkmkend AAAAAAADRP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E17_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00020000u){\*\bkmkstart AAAAAAADRQ}{\*\bkmkend AAAAAAADRQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E17_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000011u){\*\bkmkstart AAAAAAADRR}{\*\bkmkend AAAAAAADRR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E17_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADRS}{\*\bkmkend AAAAAAADRS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E17_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADRT}{\*\bkmkend AAAAAAADRT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E16_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAADRU}{\*\bkmkend AAAAAAADRU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E16_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAADRV}{\*\bkmkend AAAAAAADRV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E16_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADRW}{\*\bkmkend AAAAAAADRW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E16_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADRX}{\*\bkmkend AAAAAAADRX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E15_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00008000u){\*\bkmkstart AAAAAAADRY}{\*\bkmkend AAAAAAADRY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E15_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAADRZ}{\*\bkmkend AAAAAAADRZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E15_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADSA}{\*\bkmkend AAAAAAADSA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E15_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADSB}{\*\bkmkend AAAAAAADSB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E14_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00004000u){\*\bkmkstart AAAAAAADSC}{\*\bkmkend AAAAAAADSC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E14_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Eu){\*\bkmkstart AAAAAAADSD}{\*\bkmkend AAAAAAADSD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E14_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADSE}{\*\bkmkend AAAAAAADSE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E14_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADSF}{\*\bkmkend AAAAAAADSF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E13_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00002000u){\*\bkmkstart AAAAAAADSG}{\*\bkmkend AAAAAAADSG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E13_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Du){\*\bkmkstart AAAAAAADSH}{\*\bkmkend AAAAAAADSH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E13_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADSI}{\*\bkmkend AAAAAAADSI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E13_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADSJ}{\*\bkmkend AAAAAAADSJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E12_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001000u){\*\bkmkstart AAAAAAADSK}{\*\bkmkend AAAAAAADSK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E12_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAADSL}{\*\bkmkend AAAAAAADSL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E12_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADSM}{\*\bkmkend AAAAAAADSM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E12_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADSN}{\*\bkmkend AAAAAAADSN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E11_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAADSO}{\*\bkmkend AAAAAAADSO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E11_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAADSP}{\*\bkmkend AAAAAAADSP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E11_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADSQ}{\*\bkmkend AAAAAAADSQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E11_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADSR}{\*\bkmkend AAAAAAADSR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E10_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000400u){\*\bkmkstart AAAAAAADSS}{\*\bkmkend AAAAAAADSS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E10_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAADST}{\*\bkmkend AAAAAAADST} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E10_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADSU}{\*\bkmkend AAAAAAADSU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E10_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADSV}{\*\bkmkend AAAAAAADSV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E9_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000200u){\*\bkmkstart AAAAAAADSW}{\*\bkmkend AAAAAAADSW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E9_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAADSX}{\*\bkmkend AAAAAAADSX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E9_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADSY}{\*\bkmkend AAAAAAADSY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E9_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADSZ}{\*\bkmkend AAAAAAADSZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E8_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAADTA}{\*\bkmkend AAAAAAADTA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E8_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAADTB}{\*\bkmkend AAAAAAADTB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E8_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADTC}{\*\bkmkend AAAAAAADTC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E8_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADTD}{\*\bkmkend AAAAAAADTD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E7_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAADTE}{\*\bkmkend AAAAAAADTE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E7_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAADTF}{\*\bkmkend AAAAAAADTF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E7_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADTG}{\*\bkmkend AAAAAAADTG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E7_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADTH}{\*\bkmkend AAAAAAADTH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E6_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAADTI}{\*\bkmkend AAAAAAADTI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E6_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAADTJ}{\*\bkmkend AAAAAAADTJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E6_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADTK}{\*\bkmkend AAAAAAADTK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E6_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADTL}{\*\bkmkend AAAAAAADTL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E5_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAADTM}{\*\bkmkend AAAAAAADTM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E5_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAADTN}{\*\bkmkend AAAAAAADTN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E5_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADTO}{\*\bkmkend AAAAAAADTO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E5_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADTP}{\*\bkmkend AAAAAAADTP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E4_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAADTQ}{\*\bkmkend AAAAAAADTQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E4_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAADTR}{\*\bkmkend AAAAAAADTR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E4_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADTS}{\*\bkmkend AAAAAAADTS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E4_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADTT}{\*\bkmkend AAAAAAADTT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E3_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAADTU}{\*\bkmkend AAAAAAADTU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E3_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAADTV}{\*\bkmkend AAAAAAADTV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E3_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADTW}{\*\bkmkend AAAAAAADTW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E3_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADTX}{\*\bkmkend AAAAAAADTX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E2_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAADTY}{\*\bkmkend AAAAAAADTY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E2_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAADTZ}{\*\bkmkend AAAAAAADTZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E2_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADUA}{\*\bkmkend AAAAAAADUA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E2_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADUB}{\*\bkmkend AAAAAAADUB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E1_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAADUC}{\*\bkmkend AAAAAAADUC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E1_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADUD}{\*\bkmkend AAAAAAADUD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E1_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADUE}{\*\bkmkend AAAAAAADUE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E1_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADUF}{\*\bkmkend AAAAAAADUF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E0_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADUG}{\*\bkmkend AAAAAAADUG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E0_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADUH}{\*\bkmkend AAAAAAADUH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E0_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADUI}{\*\bkmkend AAAAAAADUI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_E0_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADUJ}{\*\bkmkend AAAAAAADUJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E63_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x80000000u){\*\bkmkstart AAAAAAADUL}{\*\bkmkend AAAAAAADUL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E63_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAADUM}{\*\bkmkend AAAAAAADUM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E63_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADUN}{\*\bkmkend AAAAAAADUN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E63_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADUO}{\*\bkmkend AAAAAAADUO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E62_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x40000000u){\*\bkmkstart AAAAAAADUP}{\*\bkmkend AAAAAAADUP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E62_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Eu){\*\bkmkstart AAAAAAADUQ}{\*\bkmkend AAAAAAADUQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E62_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADUR}{\*\bkmkend AAAAAAADUR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E62_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADUS}{\*\bkmkend AAAAAAADUS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E61_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x20000000u){\*\bkmkstart AAAAAAADUT}{\*\bkmkend AAAAAAADUT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E61_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Du){\*\bkmkstart AAAAAAADUU}{\*\bkmkend AAAAAAADUU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E61_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADUV}{\*\bkmkend AAAAAAADUV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E61_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADUW}{\*\bkmkend AAAAAAADUW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E60_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x10000000u){\*\bkmkstart AAAAAAADUX}{\*\bkmkend AAAAAAADUX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E60_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAADUY}{\*\bkmkend AAAAAAADUY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E60_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADUZ}{\*\bkmkend AAAAAAADUZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E60_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADVA}{\*\bkmkend AAAAAAADVA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E59_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x08000000u){\*\bkmkstart AAAAAAADVB}{\*\bkmkend AAAAAAADVB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E59_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Bu){\*\bkmkstart AAAAAAADVC}{\*\bkmkend AAAAAAADVC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E59_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADVD}{\*\bkmkend AAAAAAADVD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E59_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADVE}{\*\bkmkend AAAAAAADVE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E58_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x04000000u){\*\bkmkstart AAAAAAADVF}{\*\bkmkend AAAAAAADVF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E58_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Au){\*\bkmkstart AAAAAAADVG}{\*\bkmkend AAAAAAADVG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E58_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADVH}{\*\bkmkend AAAAAAADVH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E58_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADVI}{\*\bkmkend AAAAAAADVI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E57_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x02000000u){\*\bkmkstart AAAAAAADVJ}{\*\bkmkend AAAAAAADVJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E57_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000019u){\*\bkmkstart AAAAAAADVK}{\*\bkmkend AAAAAAADVK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E57_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADVL}{\*\bkmkend AAAAAAADVL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E57_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADVM}{\*\bkmkend AAAAAAADVM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E56_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x01000000u){\*\bkmkstart AAAAAAADVN}{\*\bkmkend AAAAAAADVN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E56_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAADVO}{\*\bkmkend AAAAAAADVO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E56_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADVP}{\*\bkmkend AAAAAAADVP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E56_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADVQ}{\*\bkmkend AAAAAAADVQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E55_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00800000u){\*\bkmkstart AAAAAAADVR}{\*\bkmkend AAAAAAADVR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E55_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000017u){\*\bkmkstart AAAAAAADVS}{\*\bkmkend AAAAAAADVS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E55_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADVT}{\*\bkmkend AAAAAAADVT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E55_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADVU}{\*\bkmkend AAAAAAADVU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E54_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAADVV}{\*\bkmkend AAAAAAADVV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E54_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAADVW}{\*\bkmkend AAAAAAADVW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E54_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADVX}{\*\bkmkend AAAAAAADVX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E54_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADVY}{\*\bkmkend AAAAAAADVY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E53_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00200000u){\*\bkmkstart AAAAAAADVZ}{\*\bkmkend AAAAAAADVZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E53_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAADWA}{\*\bkmkend AAAAAAADWA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E53_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADWB}{\*\bkmkend AAAAAAADWB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E53_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADWC}{\*\bkmkend AAAAAAADWC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E52_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAADWD}{\*\bkmkend AAAAAAADWD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E52_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAADWE}{\*\bkmkend AAAAAAADWE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E52_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADWF}{\*\bkmkend AAAAAAADWF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E52_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADWG}{\*\bkmkend AAAAAAADWG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E51_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00080000u){\*\bkmkstart AAAAAAADWH}{\*\bkmkend AAAAAAADWH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E51_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000013u){\*\bkmkstart AAAAAAADWI}{\*\bkmkend AAAAAAADWI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E51_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADWJ}{\*\bkmkend AAAAAAADWJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E51_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADWK}{\*\bkmkend AAAAAAADWK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E50_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00040000u){\*\bkmkstart AAAAAAADWL}{\*\bkmkend AAAAAAADWL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E50_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000012u){\*\bkmkstart AAAAAAADWM}{\*\bkmkend AAAAAAADWM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E50_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADWN}{\*\bkmkend AAAAAAADWN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E50_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADWO}{\*\bkmkend AAAAAAADWO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E49_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00020000u){\*\bkmkstart AAAAAAADWP}{\*\bkmkend AAAAAAADWP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E49_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000011u){\*\bkmkstart AAAAAAADWQ}{\*\bkmkend AAAAAAADWQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E49_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADWR}{\*\bkmkend AAAAAAADWR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E49_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADWS}{\*\bkmkend AAAAAAADWS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E48_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAADWT}{\*\bkmkend AAAAAAADWT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E48_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAADWU}{\*\bkmkend AAAAAAADWU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E48_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADWV}{\*\bkmkend AAAAAAADWV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E48_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADWW}{\*\bkmkend AAAAAAADWW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E47_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00008000u){\*\bkmkstart AAAAAAADWX}{\*\bkmkend AAAAAAADWX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E47_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAADWY}{\*\bkmkend AAAAAAADWY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E47_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADWZ}{\*\bkmkend AAAAAAADWZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E47_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADXA}{\*\bkmkend AAAAAAADXA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E46_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00004000u){\*\bkmkstart AAAAAAADXB}{\*\bkmkend AAAAAAADXB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E46_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Eu){\*\bkmkstart AAAAAAADXC}{\*\bkmkend AAAAAAADXC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E46_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADXD}{\*\bkmkend AAAAAAADXD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E46_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADXE}{\*\bkmkend AAAAAAADXE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E45_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00002000u){\*\bkmkstart AAAAAAADXF}{\*\bkmkend AAAAAAADXF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E45_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Du){\*\bkmkstart AAAAAAADXG}{\*\bkmkend AAAAAAADXG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E45_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADXH}{\*\bkmkend AAAAAAADXH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E45_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADXI}{\*\bkmkend AAAAAAADXI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E44_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001000u){\*\bkmkstart AAAAAAADXJ}{\*\bkmkend AAAAAAADXJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E44_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAADXK}{\*\bkmkend AAAAAAADXK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E44_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADXL}{\*\bkmkend AAAAAAADXL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E44_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADXM}{\*\bkmkend AAAAAAADXM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E43_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAADXN}{\*\bkmkend AAAAAAADXN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E43_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAADXO}{\*\bkmkend AAAAAAADXO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E43_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADXP}{\*\bkmkend AAAAAAADXP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E43_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADXQ}{\*\bkmkend AAAAAAADXQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E42_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000400u){\*\bkmkstart AAAAAAADXR}{\*\bkmkend AAAAAAADXR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E42_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAADXS}{\*\bkmkend AAAAAAADXS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E42_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADXT}{\*\bkmkend AAAAAAADXT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E42_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADXU}{\*\bkmkend AAAAAAADXU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E41_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000200u){\*\bkmkstart AAAAAAADXV}{\*\bkmkend AAAAAAADXV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E41_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAADXW}{\*\bkmkend AAAAAAADXW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E41_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADXX}{\*\bkmkend AAAAAAADXX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E41_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADXY}{\*\bkmkend AAAAAAADXY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E40_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAADXZ}{\*\bkmkend AAAAAAADXZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E40_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAADYA}{\*\bkmkend AAAAAAADYA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E40_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADYB}{\*\bkmkend AAAAAAADYB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E40_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADYC}{\*\bkmkend AAAAAAADYC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E39_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAADYD}{\*\bkmkend AAAAAAADYD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E39_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAADYE}{\*\bkmkend AAAAAAADYE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E39_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADYF}{\*\bkmkend AAAAAAADYF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E39_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADYG}{\*\bkmkend AAAAAAADYG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E38_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAADYH}{\*\bkmkend AAAAAAADYH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E38_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAADYI}{\*\bkmkend AAAAAAADYI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E38_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADYJ}{\*\bkmkend AAAAAAADYJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E38_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADYK}{\*\bkmkend AAAAAAADYK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E37_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAADYL}{\*\bkmkend AAAAAAADYL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E37_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAADYM}{\*\bkmkend AAAAAAADYM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E37_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADYN}{\*\bkmkend AAAAAAADYN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E37_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADYO}{\*\bkmkend AAAAAAADYO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E36_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAADYP}{\*\bkmkend AAAAAAADYP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E36_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAADYQ}{\*\bkmkend AAAAAAADYQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E36_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADYR}{\*\bkmkend AAAAAAADYR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E36_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADYS}{\*\bkmkend AAAAAAADYS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E35_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAADYT}{\*\bkmkend AAAAAAADYT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E35_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAADYU}{\*\bkmkend AAAAAAADYU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E35_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADYV}{\*\bkmkend AAAAAAADYV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E35_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADYW}{\*\bkmkend AAAAAAADYW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E34_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAADYX}{\*\bkmkend AAAAAAADYX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E34_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAADYY}{\*\bkmkend AAAAAAADYY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E34_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADYZ}{\*\bkmkend AAAAAAADYZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E34_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADZA}{\*\bkmkend AAAAAAADZA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E33_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAADZB}{\*\bkmkend AAAAAAADZB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E33_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADZC}{\*\bkmkend AAAAAAADZC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E33_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADZD}{\*\bkmkend AAAAAAADZD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E33_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADZE}{\*\bkmkend AAAAAAADZE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E32_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADZF}{\*\bkmkend AAAAAAADZF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E32_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADZG}{\*\bkmkend AAAAAAADZG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E32_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADZH}{\*\bkmkend AAAAAAADZH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_E32_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADZI}{\*\bkmkend AAAAAAADZI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E31_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x80000000u){\*\bkmkstart AAAAAAADZK}{\*\bkmkend AAAAAAADZK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E31_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAADZL}{\*\bkmkend AAAAAAADZL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E31_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADZM}{\*\bkmkend AAAAAAADZM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E31_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADZN}{\*\bkmkend AAAAAAADZN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E30_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x40000000u){\*\bkmkstart AAAAAAADZO}{\*\bkmkend AAAAAAADZO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E30_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Eu){\*\bkmkstart AAAAAAADZP}{\*\bkmkend AAAAAAADZP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E30_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADZQ}{\*\bkmkend AAAAAAADZQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E30_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADZR}{\*\bkmkend AAAAAAADZR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E29_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x20000000u){\*\bkmkstart AAAAAAADZS}{\*\bkmkend AAAAAAADZS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E29_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Du){\*\bkmkstart AAAAAAADZT}{\*\bkmkend AAAAAAADZT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E29_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADZU}{\*\bkmkend AAAAAAADZU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E29_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADZV}{\*\bkmkend AAAAAAADZV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E28_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x10000000u){\*\bkmkstart AAAAAAADZW}{\*\bkmkend AAAAAAADZW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E28_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAADZX}{\*\bkmkend AAAAAAADZX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E28_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADZY}{\*\bkmkend AAAAAAADZY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E28_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAADZZ}{\*\bkmkend AAAAAAADZZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E27_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x08000000u){\*\bkmkstart AAAAAAAEAA}{\*\bkmkend AAAAAAAEAA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E27_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Bu){\*\bkmkstart AAAAAAAEAB}{\*\bkmkend AAAAAAAEAB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E27_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEAC}{\*\bkmkend AAAAAAAEAC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E27_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEAD}{\*\bkmkend AAAAAAAEAD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E26_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x04000000u){\*\bkmkstart AAAAAAAEAE}{\*\bkmkend AAAAAAAEAE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E26_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Au){\*\bkmkstart AAAAAAAEAF}{\*\bkmkend AAAAAAAEAF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E26_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEAG}{\*\bkmkend AAAAAAAEAG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E26_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEAH}{\*\bkmkend AAAAAAAEAH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E25_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x02000000u){\*\bkmkstart AAAAAAAEAI}{\*\bkmkend AAAAAAAEAI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E25_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000019u){\*\bkmkstart AAAAAAAEAJ}{\*\bkmkend AAAAAAAEAJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E25_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEAK}{\*\bkmkend AAAAAAAEAK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E25_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEAL}{\*\bkmkend AAAAAAAEAL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E24_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x01000000u){\*\bkmkstart AAAAAAAEAM}{\*\bkmkend AAAAAAAEAM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E24_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAAEAN}{\*\bkmkend AAAAAAAEAN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E24_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEAO}{\*\bkmkend AAAAAAAEAO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E24_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEAP}{\*\bkmkend AAAAAAAEAP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E23_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00800000u){\*\bkmkstart AAAAAAAEAQ}{\*\bkmkend AAAAAAAEAQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E23_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000017u){\*\bkmkstart AAAAAAAEAR}{\*\bkmkend AAAAAAAEAR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E23_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEAS}{\*\bkmkend AAAAAAAEAS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E23_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEAT}{\*\bkmkend AAAAAAAEAT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E22_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAAEAU}{\*\bkmkend AAAAAAAEAU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E22_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAAEAV}{\*\bkmkend AAAAAAAEAV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E22_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEAW}{\*\bkmkend AAAAAAAEAW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E22_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEAX}{\*\bkmkend AAAAAAAEAX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E21_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00200000u){\*\bkmkstart AAAAAAAEAY}{\*\bkmkend AAAAAAAEAY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E21_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAAEAZ}{\*\bkmkend AAAAAAAEAZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E21_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEBA}{\*\bkmkend AAAAAAAEBA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E21_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEBB}{\*\bkmkend AAAAAAAEBB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E20_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAAEBC}{\*\bkmkend AAAAAAAEBC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E20_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAAEBD}{\*\bkmkend AAAAAAAEBD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E20_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEBE}{\*\bkmkend AAAAAAAEBE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E20_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEBF}{\*\bkmkend AAAAAAAEBF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E19_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00080000u){\*\bkmkstart AAAAAAAEBG}{\*\bkmkend AAAAAAAEBG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E19_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000013u){\*\bkmkstart AAAAAAAEBH}{\*\bkmkend AAAAAAAEBH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E19_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEBI}{\*\bkmkend AAAAAAAEBI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E19_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEBJ}{\*\bkmkend AAAAAAAEBJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E18_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00040000u){\*\bkmkstart AAAAAAAEBK}{\*\bkmkend AAAAAAAEBK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E18_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000012u){\*\bkmkstart AAAAAAAEBL}{\*\bkmkend AAAAAAAEBL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E18_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEBM}{\*\bkmkend AAAAAAAEBM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E18_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEBN}{\*\bkmkend AAAAAAAEBN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E17_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00020000u){\*\bkmkstart AAAAAAAEBO}{\*\bkmkend AAAAAAAEBO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E17_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000011u){\*\bkmkstart AAAAAAAEBP}{\*\bkmkend AAAAAAAEBP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E17_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEBQ}{\*\bkmkend AAAAAAAEBQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E17_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEBR}{\*\bkmkend AAAAAAAEBR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E16_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAAEBS}{\*\bkmkend AAAAAAAEBS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E16_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAEBT}{\*\bkmkend AAAAAAAEBT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E16_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEBU}{\*\bkmkend AAAAAAAEBU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E16_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEBV}{\*\bkmkend AAAAAAAEBV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E15_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00008000u){\*\bkmkstart AAAAAAAEBW}{\*\bkmkend AAAAAAAEBW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E15_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAAEBX}{\*\bkmkend AAAAAAAEBX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E15_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEBY}{\*\bkmkend AAAAAAAEBY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E15_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEBZ}{\*\bkmkend AAAAAAAEBZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E14_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00004000u){\*\bkmkstart AAAAAAAECA}{\*\bkmkend AAAAAAAECA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E14_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Eu){\*\bkmkstart AAAAAAAECB}{\*\bkmkend AAAAAAAECB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E14_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAECC}{\*\bkmkend AAAAAAAECC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E14_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAECD}{\*\bkmkend AAAAAAAECD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E13_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00002000u){\*\bkmkstart AAAAAAAECE}{\*\bkmkend AAAAAAAECE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E13_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Du){\*\bkmkstart AAAAAAAECF}{\*\bkmkend AAAAAAAECF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E13_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAECG}{\*\bkmkend AAAAAAAECG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E13_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAECH}{\*\bkmkend AAAAAAAECH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E12_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001000u){\*\bkmkstart AAAAAAAECI}{\*\bkmkend AAAAAAAECI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E12_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAAECJ}{\*\bkmkend AAAAAAAECJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E12_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAECK}{\*\bkmkend AAAAAAAECK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E12_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAECL}{\*\bkmkend AAAAAAAECL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E11_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAAECM}{\*\bkmkend AAAAAAAECM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E11_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAAECN}{\*\bkmkend AAAAAAAECN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E11_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAECO}{\*\bkmkend AAAAAAAECO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E11_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAECP}{\*\bkmkend AAAAAAAECP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E10_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000400u){\*\bkmkstart AAAAAAAECQ}{\*\bkmkend AAAAAAAECQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E10_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAAECR}{\*\bkmkend AAAAAAAECR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E10_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAECS}{\*\bkmkend AAAAAAAECS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E10_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAECT}{\*\bkmkend AAAAAAAECT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E9_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000200u){\*\bkmkstart AAAAAAAECU}{\*\bkmkend AAAAAAAECU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E9_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAAECV}{\*\bkmkend AAAAAAAECV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E9_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAECW}{\*\bkmkend AAAAAAAECW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E9_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAECX}{\*\bkmkend AAAAAAAECX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E8_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAAECY}{\*\bkmkend AAAAAAAECY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E8_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAECZ}{\*\bkmkend AAAAAAAECZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E8_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEDA}{\*\bkmkend AAAAAAAEDA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E8_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEDB}{\*\bkmkend AAAAAAAEDB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E7_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAAEDC}{\*\bkmkend AAAAAAAEDC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E7_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAEDD}{\*\bkmkend AAAAAAAEDD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E7_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEDE}{\*\bkmkend AAAAAAAEDE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E7_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEDF}{\*\bkmkend AAAAAAAEDF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E6_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAAEDG}{\*\bkmkend AAAAAAAEDG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E6_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAAEDH}{\*\bkmkend AAAAAAAEDH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E6_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEDI}{\*\bkmkend AAAAAAAEDI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E6_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEDJ}{\*\bkmkend AAAAAAAEDJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E5_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAAEDK}{\*\bkmkend AAAAAAAEDK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E5_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAAEDL}{\*\bkmkend AAAAAAAEDL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E5_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEDM}{\*\bkmkend AAAAAAAEDM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E5_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEDN}{\*\bkmkend AAAAAAAEDN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E4_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAEDO}{\*\bkmkend AAAAAAAEDO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E4_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAEDP}{\*\bkmkend AAAAAAAEDP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E4_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEDQ}{\*\bkmkend AAAAAAAEDQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E4_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEDR}{\*\bkmkend AAAAAAAEDR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E3_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAEDS}{\*\bkmkend AAAAAAAEDS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E3_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAEDT}{\*\bkmkend AAAAAAAEDT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E3_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEDU}{\*\bkmkend AAAAAAAEDU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E3_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEDV}{\*\bkmkend AAAAAAAEDV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E2_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAEDW}{\*\bkmkend AAAAAAAEDW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E2_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAEDX}{\*\bkmkend AAAAAAAEDX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E2_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEDY}{\*\bkmkend AAAAAAAEDY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E2_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEDZ}{\*\bkmkend AAAAAAAEDZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E1_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAEEA}{\*\bkmkend AAAAAAAEEA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E1_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEEB}{\*\bkmkend AAAAAAAEEB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E1_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEEC}{\*\bkmkend AAAAAAAEEC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E1_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEED}{\*\bkmkend AAAAAAAEED} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E0_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEEE}{\*\bkmkend AAAAAAAEEE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E0_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEEF}{\*\bkmkend AAAAAAAEEF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E0_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEEG}{\*\bkmkend AAAAAAAEEG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_E0_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEEH}{\*\bkmkend AAAAAAAEEH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E63_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x80000000u){\*\bkmkstart AAAAAAAEEJ}{\*\bkmkend AAAAAAAEEJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E63_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAAEEK}{\*\bkmkend AAAAAAAEEK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E63_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEEL}{\*\bkmkend AAAAAAAEEL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E63_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEEM}{\*\bkmkend AAAAAAAEEM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E62_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x40000000u){\*\bkmkstart AAAAAAAEEN}{\*\bkmkend AAAAAAAEEN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E62_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Eu){\*\bkmkstart AAAAAAAEEO}{\*\bkmkend AAAAAAAEEO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E62_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEEP}{\*\bkmkend AAAAAAAEEP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E62_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEEQ}{\*\bkmkend AAAAAAAEEQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E61_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x20000000u){\*\bkmkstart AAAAAAAEER}{\*\bkmkend AAAAAAAEER} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E61_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Du){\*\bkmkstart AAAAAAAEES}{\*\bkmkend AAAAAAAEES} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E61_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEET}{\*\bkmkend AAAAAAAEET} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E61_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEEU}{\*\bkmkend AAAAAAAEEU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E60_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x10000000u){\*\bkmkstart AAAAAAAEEV}{\*\bkmkend AAAAAAAEEV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E60_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAAEEW}{\*\bkmkend AAAAAAAEEW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E60_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEEX}{\*\bkmkend AAAAAAAEEX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E60_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEEY}{\*\bkmkend AAAAAAAEEY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E59_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x08000000u){\*\bkmkstart AAAAAAAEEZ}{\*\bkmkend AAAAAAAEEZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E59_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Bu){\*\bkmkstart AAAAAAAEFA}{\*\bkmkend AAAAAAAEFA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E59_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEFB}{\*\bkmkend AAAAAAAEFB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E59_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEFC}{\*\bkmkend AAAAAAAEFC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E58_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x04000000u){\*\bkmkstart AAAAAAAEFD}{\*\bkmkend AAAAAAAEFD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E58_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Au){\*\bkmkstart AAAAAAAEFE}{\*\bkmkend AAAAAAAEFE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E58_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEFF}{\*\bkmkend AAAAAAAEFF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E58_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEFG}{\*\bkmkend AAAAAAAEFG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E57_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x02000000u){\*\bkmkstart AAAAAAAEFH}{\*\bkmkend AAAAAAAEFH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E57_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000019u){\*\bkmkstart AAAAAAAEFI}{\*\bkmkend AAAAAAAEFI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E57_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEFJ}{\*\bkmkend AAAAAAAEFJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E57_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEFK}{\*\bkmkend AAAAAAAEFK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E56_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x01000000u){\*\bkmkstart AAAAAAAEFL}{\*\bkmkend AAAAAAAEFL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E56_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAAEFM}{\*\bkmkend AAAAAAAEFM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E56_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEFN}{\*\bkmkend AAAAAAAEFN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E56_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEFO}{\*\bkmkend AAAAAAAEFO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E55_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00800000u){\*\bkmkstart AAAAAAAEFP}{\*\bkmkend AAAAAAAEFP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E55_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000017u){\*\bkmkstart AAAAAAAEFQ}{\*\bkmkend AAAAAAAEFQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E55_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEFR}{\*\bkmkend AAAAAAAEFR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E55_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEFS}{\*\bkmkend AAAAAAAEFS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E54_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAAEFT}{\*\bkmkend AAAAAAAEFT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E54_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAAEFU}{\*\bkmkend AAAAAAAEFU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E54_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEFV}{\*\bkmkend AAAAAAAEFV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E54_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEFW}{\*\bkmkend AAAAAAAEFW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E53_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00200000u){\*\bkmkstart AAAAAAAEFX}{\*\bkmkend AAAAAAAEFX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E53_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAAEFY}{\*\bkmkend AAAAAAAEFY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E53_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEFZ}{\*\bkmkend AAAAAAAEFZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E53_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEGA}{\*\bkmkend AAAAAAAEGA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E52_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAAEGB}{\*\bkmkend AAAAAAAEGB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E52_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAAEGC}{\*\bkmkend AAAAAAAEGC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E52_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEGD}{\*\bkmkend AAAAAAAEGD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E52_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEGE}{\*\bkmkend AAAAAAAEGE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E51_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00080000u){\*\bkmkstart AAAAAAAEGF}{\*\bkmkend AAAAAAAEGF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E51_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000013u){\*\bkmkstart AAAAAAAEGG}{\*\bkmkend AAAAAAAEGG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E51_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEGH}{\*\bkmkend AAAAAAAEGH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E51_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEGI}{\*\bkmkend AAAAAAAEGI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E50_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00040000u){\*\bkmkstart AAAAAAAEGJ}{\*\bkmkend AAAAAAAEGJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E50_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000012u){\*\bkmkstart AAAAAAAEGK}{\*\bkmkend AAAAAAAEGK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E50_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEGL}{\*\bkmkend AAAAAAAEGL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E50_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEGM}{\*\bkmkend AAAAAAAEGM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E49_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00020000u){\*\bkmkstart AAAAAAAEGN}{\*\bkmkend AAAAAAAEGN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E49_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000011u){\*\bkmkstart AAAAAAAEGO}{\*\bkmkend AAAAAAAEGO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E49_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEGP}{\*\bkmkend AAAAAAAEGP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E49_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEGQ}{\*\bkmkend AAAAAAAEGQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E48_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAAEGR}{\*\bkmkend AAAAAAAEGR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E48_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAEGS}{\*\bkmkend AAAAAAAEGS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E48_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEGT}{\*\bkmkend AAAAAAAEGT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E48_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEGU}{\*\bkmkend AAAAAAAEGU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E47_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00008000u){\*\bkmkstart AAAAAAAEGV}{\*\bkmkend AAAAAAAEGV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E47_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAAEGW}{\*\bkmkend AAAAAAAEGW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E47_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEGX}{\*\bkmkend AAAAAAAEGX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E47_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEGY}{\*\bkmkend AAAAAAAEGY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E46_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00004000u){\*\bkmkstart AAAAAAAEGZ}{\*\bkmkend AAAAAAAEGZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E46_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Eu){\*\bkmkstart AAAAAAAEHA}{\*\bkmkend AAAAAAAEHA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E46_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEHB}{\*\bkmkend AAAAAAAEHB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E46_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEHC}{\*\bkmkend AAAAAAAEHC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E45_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00002000u){\*\bkmkstart AAAAAAAEHD}{\*\bkmkend AAAAAAAEHD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E45_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Du){\*\bkmkstart AAAAAAAEHE}{\*\bkmkend AAAAAAAEHE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E45_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEHF}{\*\bkmkend AAAAAAAEHF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E45_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEHG}{\*\bkmkend AAAAAAAEHG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E44_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001000u){\*\bkmkstart AAAAAAAEHH}{\*\bkmkend AAAAAAAEHH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E44_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAAEHI}{\*\bkmkend AAAAAAAEHI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E44_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEHJ}{\*\bkmkend AAAAAAAEHJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E44_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEHK}{\*\bkmkend AAAAAAAEHK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E43_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAAEHL}{\*\bkmkend AAAAAAAEHL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E43_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAAEHM}{\*\bkmkend AAAAAAAEHM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E43_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEHN}{\*\bkmkend AAAAAAAEHN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E43_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEHO}{\*\bkmkend AAAAAAAEHO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E42_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000400u){\*\bkmkstart AAAAAAAEHP}{\*\bkmkend AAAAAAAEHP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E42_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAAEHQ}{\*\bkmkend AAAAAAAEHQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E42_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEHR}{\*\bkmkend AAAAAAAEHR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E42_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEHS}{\*\bkmkend AAAAAAAEHS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E41_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000200u){\*\bkmkstart AAAAAAAEHT}{\*\bkmkend AAAAAAAEHT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E41_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAAEHU}{\*\bkmkend AAAAAAAEHU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E41_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEHV}{\*\bkmkend AAAAAAAEHV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E41_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEHW}{\*\bkmkend AAAAAAAEHW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E40_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAAEHX}{\*\bkmkend AAAAAAAEHX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E40_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAEHY}{\*\bkmkend AAAAAAAEHY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E40_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEHZ}{\*\bkmkend AAAAAAAEHZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E40_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEIA}{\*\bkmkend AAAAAAAEIA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E39_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAAEIB}{\*\bkmkend AAAAAAAEIB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E39_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAEIC}{\*\bkmkend AAAAAAAEIC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E39_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEID}{\*\bkmkend AAAAAAAEID} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E39_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEIE}{\*\bkmkend AAAAAAAEIE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E38_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAAEIF}{\*\bkmkend AAAAAAAEIF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E38_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAAEIG}{\*\bkmkend AAAAAAAEIG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E38_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEIH}{\*\bkmkend AAAAAAAEIH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E38_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEII}{\*\bkmkend AAAAAAAEII} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E37_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAAEIJ}{\*\bkmkend AAAAAAAEIJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E37_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAAEIK}{\*\bkmkend AAAAAAAEIK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E37_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEIL}{\*\bkmkend AAAAAAAEIL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E37_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEIM}{\*\bkmkend AAAAAAAEIM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E36_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAEIN}{\*\bkmkend AAAAAAAEIN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E36_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAEIO}{\*\bkmkend AAAAAAAEIO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E36_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEIP}{\*\bkmkend AAAAAAAEIP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E36_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEIQ}{\*\bkmkend AAAAAAAEIQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E35_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAEIR}{\*\bkmkend AAAAAAAEIR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E35_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAEIS}{\*\bkmkend AAAAAAAEIS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E35_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEIT}{\*\bkmkend AAAAAAAEIT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E35_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEIU}{\*\bkmkend AAAAAAAEIU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E34_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAEIV}{\*\bkmkend AAAAAAAEIV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E34_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAEIW}{\*\bkmkend AAAAAAAEIW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E34_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEIX}{\*\bkmkend AAAAAAAEIX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E34_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEIY}{\*\bkmkend AAAAAAAEIY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E33_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAEIZ}{\*\bkmkend AAAAAAAEIZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E33_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEJA}{\*\bkmkend AAAAAAAEJA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E33_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEJB}{\*\bkmkend AAAAAAAEJB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E33_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEJC}{\*\bkmkend AAAAAAAEJC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E32_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEJD}{\*\bkmkend AAAAAAAEJD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E32_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEJE}{\*\bkmkend AAAAAAAEJE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E32_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEJF}{\*\bkmkend AAAAAAAEJF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_E32_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEJG}{\*\bkmkend AAAAAAAEJG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E31_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x80000000u){\*\bkmkstart AAAAAAAEJI}{\*\bkmkend AAAAAAAEJI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E31_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAAEJJ}{\*\bkmkend AAAAAAAEJJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E31_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEJK}{\*\bkmkend AAAAAAAEJK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E30_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x40000000u){\*\bkmkstart AAAAAAAEJL}{\*\bkmkend AAAAAAAEJL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E30_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Eu){\*\bkmkstart AAAAAAAEJM}{\*\bkmkend AAAAAAAEJM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E30_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEJN}{\*\bkmkend AAAAAAAEJN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E29_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x20000000u){\*\bkmkstart AAAAAAAEJO}{\*\bkmkend AAAAAAAEJO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E29_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Du){\*\bkmkstart AAAAAAAEJP}{\*\bkmkend AAAAAAAEJP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E29_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEJQ}{\*\bkmkend AAAAAAAEJQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E28_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x10000000u){\*\bkmkstart AAAAAAAEJR}{\*\bkmkend AAAAAAAEJR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E28_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAAEJS}{\*\bkmkend AAAAAAAEJS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E28_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEJT}{\*\bkmkend AAAAAAAEJT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E27_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x08000000u){\*\bkmkstart AAAAAAAEJU}{\*\bkmkend AAAAAAAEJU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E27_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Bu){\*\bkmkstart AAAAAAAEJV}{\*\bkmkend AAAAAAAEJV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E27_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEJW}{\*\bkmkend AAAAAAAEJW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E26_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x04000000u){\*\bkmkstart AAAAAAAEJX}{\*\bkmkend AAAAAAAEJX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E26_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Au){\*\bkmkstart AAAAAAAEJY}{\*\bkmkend AAAAAAAEJY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E26_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEJZ}{\*\bkmkend AAAAAAAEJZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E25_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x02000000u){\*\bkmkstart AAAAAAAEKA}{\*\bkmkend AAAAAAAEKA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E25_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000019u){\*\bkmkstart AAAAAAAEKB}{\*\bkmkend AAAAAAAEKB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E25_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEKC}{\*\bkmkend AAAAAAAEKC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E24_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x01000000u){\*\bkmkstart AAAAAAAEKD}{\*\bkmkend AAAAAAAEKD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E24_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAAEKE}{\*\bkmkend AAAAAAAEKE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E24_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEKF}{\*\bkmkend AAAAAAAEKF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E23_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00800000u){\*\bkmkstart AAAAAAAEKG}{\*\bkmkend AAAAAAAEKG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E23_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000017u){\*\bkmkstart AAAAAAAEKH}{\*\bkmkend AAAAAAAEKH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E23_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEKI}{\*\bkmkend AAAAAAAEKI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E22_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAAEKJ}{\*\bkmkend AAAAAAAEKJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E22_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAAEKK}{\*\bkmkend AAAAAAAEKK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E22_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEKL}{\*\bkmkend AAAAAAAEKL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E21_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00200000u){\*\bkmkstart AAAAAAAEKM}{\*\bkmkend AAAAAAAEKM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E21_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAAEKN}{\*\bkmkend AAAAAAAEKN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E21_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEKO}{\*\bkmkend AAAAAAAEKO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E20_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAAEKP}{\*\bkmkend AAAAAAAEKP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E20_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAAEKQ}{\*\bkmkend AAAAAAAEKQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E20_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEKR}{\*\bkmkend AAAAAAAEKR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E19_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00080000u){\*\bkmkstart AAAAAAAEKS}{\*\bkmkend AAAAAAAEKS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E19_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000013u){\*\bkmkstart AAAAAAAEKT}{\*\bkmkend AAAAAAAEKT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E19_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEKU}{\*\bkmkend AAAAAAAEKU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E18_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00040000u){\*\bkmkstart AAAAAAAEKV}{\*\bkmkend AAAAAAAEKV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E18_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000012u){\*\bkmkstart AAAAAAAEKW}{\*\bkmkend AAAAAAAEKW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E18_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEKX}{\*\bkmkend AAAAAAAEKX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E17_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00020000u){\*\bkmkstart AAAAAAAEKY}{\*\bkmkend AAAAAAAEKY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E17_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000011u){\*\bkmkstart AAAAAAAEKZ}{\*\bkmkend AAAAAAAEKZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E17_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAELA}{\*\bkmkend AAAAAAAELA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E16_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAAELB}{\*\bkmkend AAAAAAAELB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E16_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAELC}{\*\bkmkend AAAAAAAELC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E16_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAELD}{\*\bkmkend AAAAAAAELD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E15_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00008000u){\*\bkmkstart AAAAAAAELE}{\*\bkmkend AAAAAAAELE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E15_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAAELF}{\*\bkmkend AAAAAAAELF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E15_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAELG}{\*\bkmkend AAAAAAAELG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E14_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00004000u){\*\bkmkstart AAAAAAAELH}{\*\bkmkend AAAAAAAELH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E14_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Eu){\*\bkmkstart AAAAAAAELI}{\*\bkmkend AAAAAAAELI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E14_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAELJ}{\*\bkmkend AAAAAAAELJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E13_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00002000u){\*\bkmkstart AAAAAAAELK}{\*\bkmkend AAAAAAAELK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E13_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Du){\*\bkmkstart AAAAAAAELL}{\*\bkmkend AAAAAAAELL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E13_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAELM}{\*\bkmkend AAAAAAAELM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E12_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001000u){\*\bkmkstart AAAAAAAELN}{\*\bkmkend AAAAAAAELN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E12_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAAELO}{\*\bkmkend AAAAAAAELO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E12_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAELP}{\*\bkmkend AAAAAAAELP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E11_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAAELQ}{\*\bkmkend AAAAAAAELQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E11_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAAELR}{\*\bkmkend AAAAAAAELR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E11_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAELS}{\*\bkmkend AAAAAAAELS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E10_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000400u){\*\bkmkstart AAAAAAAELT}{\*\bkmkend AAAAAAAELT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E10_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAAELU}{\*\bkmkend AAAAAAAELU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E10_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAELV}{\*\bkmkend AAAAAAAELV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E9_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000200u){\*\bkmkstart AAAAAAAELW}{\*\bkmkend AAAAAAAELW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E9_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAAELX}{\*\bkmkend AAAAAAAELX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E9_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAELY}{\*\bkmkend AAAAAAAELY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E8_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAAELZ}{\*\bkmkend AAAAAAAELZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E8_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAEMA}{\*\bkmkend AAAAAAAEMA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E8_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEMB}{\*\bkmkend AAAAAAAEMB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E7_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAAEMC}{\*\bkmkend AAAAAAAEMC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E7_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAEMD}{\*\bkmkend AAAAAAAEMD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E7_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEME}{\*\bkmkend AAAAAAAEME} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E6_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAAEMF}{\*\bkmkend AAAAAAAEMF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E6_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAAEMG}{\*\bkmkend AAAAAAAEMG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E6_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEMH}{\*\bkmkend AAAAAAAEMH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E5_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAAEMI}{\*\bkmkend AAAAAAAEMI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E5_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAAEMJ}{\*\bkmkend AAAAAAAEMJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E5_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEMK}{\*\bkmkend AAAAAAAEMK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E4_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAEML}{\*\bkmkend AAAAAAAEML} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E4_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAEMM}{\*\bkmkend AAAAAAAEMM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E4_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEMN}{\*\bkmkend AAAAAAAEMN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E3_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAEMO}{\*\bkmkend AAAAAAAEMO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E3_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAEMP}{\*\bkmkend AAAAAAAEMP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E3_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEMQ}{\*\bkmkend AAAAAAAEMQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E2_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAEMR}{\*\bkmkend AAAAAAAEMR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E2_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAEMS}{\*\bkmkend AAAAAAAEMS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E2_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEMT}{\*\bkmkend AAAAAAAEMT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E1_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAEMU}{\*\bkmkend AAAAAAAEMU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E1_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEMV}{\*\bkmkend AAAAAAAEMV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E1_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEMW}{\*\bkmkend AAAAAAAEMW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E0_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEMX}{\*\bkmkend AAAAAAAEMX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E0_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEMY}{\*\bkmkend AAAAAAAEMY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_E0_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEMZ}{\*\bkmkend AAAAAAAEMZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E63_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x80000000u){\*\bkmkstart AAAAAAAENB}{\*\bkmkend AAAAAAAENB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E63_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAAENC}{\*\bkmkend AAAAAAAENC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E63_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEND}{\*\bkmkend AAAAAAAEND} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E62_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x40000000u){\*\bkmkstart AAAAAAAENE}{\*\bkmkend AAAAAAAENE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E62_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Eu){\*\bkmkstart AAAAAAAENF}{\*\bkmkend AAAAAAAENF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E62_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAENG}{\*\bkmkend AAAAAAAENG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E61_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x20000000u){\*\bkmkstart AAAAAAAENH}{\*\bkmkend AAAAAAAENH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E61_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Du){\*\bkmkstart AAAAAAAENI}{\*\bkmkend AAAAAAAENI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E61_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAENJ}{\*\bkmkend AAAAAAAENJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E60_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x10000000u){\*\bkmkstart AAAAAAAENK}{\*\bkmkend AAAAAAAENK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E60_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAAENL}{\*\bkmkend AAAAAAAENL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E60_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAENM}{\*\bkmkend AAAAAAAENM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E59_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x08000000u){\*\bkmkstart AAAAAAAENN}{\*\bkmkend AAAAAAAENN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E59_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Bu){\*\bkmkstart AAAAAAAENO}{\*\bkmkend AAAAAAAENO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E59_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAENP}{\*\bkmkend AAAAAAAENP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E58_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x04000000u){\*\bkmkstart AAAAAAAENQ}{\*\bkmkend AAAAAAAENQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E58_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Au){\*\bkmkstart AAAAAAAENR}{\*\bkmkend AAAAAAAENR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E58_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAENS}{\*\bkmkend AAAAAAAENS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E57_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x02000000u){\*\bkmkstart AAAAAAAENT}{\*\bkmkend AAAAAAAENT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E57_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000019u){\*\bkmkstart AAAAAAAENU}{\*\bkmkend AAAAAAAENU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E57_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAENV}{\*\bkmkend AAAAAAAENV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E56_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x01000000u){\*\bkmkstart AAAAAAAENW}{\*\bkmkend AAAAAAAENW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E56_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAAENX}{\*\bkmkend AAAAAAAENX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E56_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAENY}{\*\bkmkend AAAAAAAENY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E55_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00800000u){\*\bkmkstart AAAAAAAENZ}{\*\bkmkend AAAAAAAENZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E55_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000017u){\*\bkmkstart AAAAAAAEOA}{\*\bkmkend AAAAAAAEOA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E55_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEOB}{\*\bkmkend AAAAAAAEOB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E54_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAAEOC}{\*\bkmkend AAAAAAAEOC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E54_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAAEOD}{\*\bkmkend AAAAAAAEOD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E54_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEOE}{\*\bkmkend AAAAAAAEOE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E53_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00200000u){\*\bkmkstart AAAAAAAEOF}{\*\bkmkend AAAAAAAEOF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E53_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAAEOG}{\*\bkmkend AAAAAAAEOG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E53_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEOH}{\*\bkmkend AAAAAAAEOH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E52_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAAEOI}{\*\bkmkend AAAAAAAEOI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E52_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAAEOJ}{\*\bkmkend AAAAAAAEOJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E52_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEOK}{\*\bkmkend AAAAAAAEOK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E51_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00080000u){\*\bkmkstart AAAAAAAEOL}{\*\bkmkend AAAAAAAEOL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E51_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000013u){\*\bkmkstart AAAAAAAEOM}{\*\bkmkend AAAAAAAEOM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E51_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEON}{\*\bkmkend AAAAAAAEON} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E50_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00040000u){\*\bkmkstart AAAAAAAEOO}{\*\bkmkend AAAAAAAEOO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E50_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000012u){\*\bkmkstart AAAAAAAEOP}{\*\bkmkend AAAAAAAEOP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E50_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEOQ}{\*\bkmkend AAAAAAAEOQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E49_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00020000u){\*\bkmkstart AAAAAAAEOR}{\*\bkmkend AAAAAAAEOR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E49_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000011u){\*\bkmkstart AAAAAAAEOS}{\*\bkmkend AAAAAAAEOS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E49_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEOT}{\*\bkmkend AAAAAAAEOT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E48_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAAEOU}{\*\bkmkend AAAAAAAEOU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E48_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAEOV}{\*\bkmkend AAAAAAAEOV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E48_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEOW}{\*\bkmkend AAAAAAAEOW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E47_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00008000u){\*\bkmkstart AAAAAAAEOX}{\*\bkmkend AAAAAAAEOX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E47_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAAEOY}{\*\bkmkend AAAAAAAEOY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E47_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEOZ}{\*\bkmkend AAAAAAAEOZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E46_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00004000u){\*\bkmkstart AAAAAAAEPA}{\*\bkmkend AAAAAAAEPA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E46_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Eu){\*\bkmkstart AAAAAAAEPB}{\*\bkmkend AAAAAAAEPB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E46_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEPC}{\*\bkmkend AAAAAAAEPC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E45_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00002000u){\*\bkmkstart AAAAAAAEPD}{\*\bkmkend AAAAAAAEPD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E45_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Du){\*\bkmkstart AAAAAAAEPE}{\*\bkmkend AAAAAAAEPE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E45_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEPF}{\*\bkmkend AAAAAAAEPF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E44_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001000u){\*\bkmkstart AAAAAAAEPG}{\*\bkmkend AAAAAAAEPG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E44_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAAEPH}{\*\bkmkend AAAAAAAEPH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E44_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEPI}{\*\bkmkend AAAAAAAEPI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E43_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAAEPJ}{\*\bkmkend AAAAAAAEPJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E43_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAAEPK}{\*\bkmkend AAAAAAAEPK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E43_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEPL}{\*\bkmkend AAAAAAAEPL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E42_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000400u){\*\bkmkstart AAAAAAAEPM}{\*\bkmkend AAAAAAAEPM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E42_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAAEPN}{\*\bkmkend AAAAAAAEPN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E42_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEPO}{\*\bkmkend AAAAAAAEPO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E41_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000200u){\*\bkmkstart AAAAAAAEPP}{\*\bkmkend AAAAAAAEPP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E41_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAAEPQ}{\*\bkmkend AAAAAAAEPQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E41_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEPR}{\*\bkmkend AAAAAAAEPR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E40_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAAEPS}{\*\bkmkend AAAAAAAEPS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E40_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAEPT}{\*\bkmkend AAAAAAAEPT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E40_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEPU}{\*\bkmkend AAAAAAAEPU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E39_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAAEPV}{\*\bkmkend AAAAAAAEPV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E39_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAEPW}{\*\bkmkend AAAAAAAEPW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E39_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEPX}{\*\bkmkend AAAAAAAEPX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E38_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAAEPY}{\*\bkmkend AAAAAAAEPY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E38_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAAEPZ}{\*\bkmkend AAAAAAAEPZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E38_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEQA}{\*\bkmkend AAAAAAAEQA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E37_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAAEQB}{\*\bkmkend AAAAAAAEQB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E37_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAAEQC}{\*\bkmkend AAAAAAAEQC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E37_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEQD}{\*\bkmkend AAAAAAAEQD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E36_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAEQE}{\*\bkmkend AAAAAAAEQE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E36_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAEQF}{\*\bkmkend AAAAAAAEQF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E36_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEQG}{\*\bkmkend AAAAAAAEQG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E35_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAEQH}{\*\bkmkend AAAAAAAEQH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E35_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAEQI}{\*\bkmkend AAAAAAAEQI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E35_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEQJ}{\*\bkmkend AAAAAAAEQJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E34_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAEQK}{\*\bkmkend AAAAAAAEQK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E34_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAEQL}{\*\bkmkend AAAAAAAEQL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E34_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEQM}{\*\bkmkend AAAAAAAEQM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E33_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAEQN}{\*\bkmkend AAAAAAAEQN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E33_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEQO}{\*\bkmkend AAAAAAAEQO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E33_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEQP}{\*\bkmkend AAAAAAAEQP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E32_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEQQ}{\*\bkmkend AAAAAAAEQQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E32_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEQR}{\*\bkmkend AAAAAAAEQR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_E32_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEQS}{\*\bkmkend AAAAAAAEQS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E31_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x80000000u){\*\bkmkstart AAAAAAAEQU}{\*\bkmkend AAAAAAAEQU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E31_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAAEQV}{\*\bkmkend AAAAAAAEQV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E31_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEQW}{\*\bkmkend AAAAAAAEQW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E31_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEQX}{\*\bkmkend AAAAAAAEQX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E30_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x40000000u){\*\bkmkstart AAAAAAAEQY}{\*\bkmkend AAAAAAAEQY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E30_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Eu){\*\bkmkstart AAAAAAAEQZ}{\*\bkmkend AAAAAAAEQZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E30_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAERA}{\*\bkmkend AAAAAAAERA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E30_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAERB}{\*\bkmkend AAAAAAAERB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E29_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x20000000u){\*\bkmkstart AAAAAAAERC}{\*\bkmkend AAAAAAAERC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E29_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Du){\*\bkmkstart AAAAAAAERD}{\*\bkmkend AAAAAAAERD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E29_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAERE}{\*\bkmkend AAAAAAAERE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E29_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAERF}{\*\bkmkend AAAAAAAERF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E28_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x10000000u){\*\bkmkstart AAAAAAAERG}{\*\bkmkend AAAAAAAERG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E28_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAAERH}{\*\bkmkend AAAAAAAERH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E28_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAERI}{\*\bkmkend AAAAAAAERI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E28_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAERJ}{\*\bkmkend AAAAAAAERJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E27_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x08000000u){\*\bkmkstart AAAAAAAERK}{\*\bkmkend AAAAAAAERK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E27_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Bu){\*\bkmkstart AAAAAAAERL}{\*\bkmkend AAAAAAAERL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E27_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAERM}{\*\bkmkend AAAAAAAERM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E27_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAERN}{\*\bkmkend AAAAAAAERN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E26_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x04000000u){\*\bkmkstart AAAAAAAERO}{\*\bkmkend AAAAAAAERO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E26_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Au){\*\bkmkstart AAAAAAAERP}{\*\bkmkend AAAAAAAERP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E26_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAERQ}{\*\bkmkend AAAAAAAERQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E26_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAERR}{\*\bkmkend AAAAAAAERR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E25_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x02000000u){\*\bkmkstart AAAAAAAERS}{\*\bkmkend AAAAAAAERS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E25_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000019u){\*\bkmkstart AAAAAAAERT}{\*\bkmkend AAAAAAAERT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E25_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAERU}{\*\bkmkend AAAAAAAERU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E25_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAERV}{\*\bkmkend AAAAAAAERV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E24_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x01000000u){\*\bkmkstart AAAAAAAERW}{\*\bkmkend AAAAAAAERW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E24_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAAERX}{\*\bkmkend AAAAAAAERX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E24_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAERY}{\*\bkmkend AAAAAAAERY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E24_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAERZ}{\*\bkmkend AAAAAAAERZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E23_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00800000u){\*\bkmkstart AAAAAAAESA}{\*\bkmkend AAAAAAAESA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E23_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000017u){\*\bkmkstart AAAAAAAESB}{\*\bkmkend AAAAAAAESB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E23_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAESC}{\*\bkmkend AAAAAAAESC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E23_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAESD}{\*\bkmkend AAAAAAAESD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E22_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAAESE}{\*\bkmkend AAAAAAAESE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E22_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAAESF}{\*\bkmkend AAAAAAAESF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E22_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAESG}{\*\bkmkend AAAAAAAESG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E22_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAESH}{\*\bkmkend AAAAAAAESH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E21_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00200000u){\*\bkmkstart AAAAAAAESI}{\*\bkmkend AAAAAAAESI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E21_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAAESJ}{\*\bkmkend AAAAAAAESJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E21_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAESK}{\*\bkmkend AAAAAAAESK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E21_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAESL}{\*\bkmkend AAAAAAAESL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E20_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAAESM}{\*\bkmkend AAAAAAAESM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E20_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAAESN}{\*\bkmkend AAAAAAAESN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E20_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAESO}{\*\bkmkend AAAAAAAESO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E20_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAESP}{\*\bkmkend AAAAAAAESP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E19_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00080000u){\*\bkmkstart AAAAAAAESQ}{\*\bkmkend AAAAAAAESQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E19_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000013u){\*\bkmkstart AAAAAAAESR}{\*\bkmkend AAAAAAAESR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E19_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAESS}{\*\bkmkend AAAAAAAESS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E19_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEST}{\*\bkmkend AAAAAAAEST} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E18_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00040000u){\*\bkmkstart AAAAAAAESU}{\*\bkmkend AAAAAAAESU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E18_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000012u){\*\bkmkstart AAAAAAAESV}{\*\bkmkend AAAAAAAESV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E18_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAESW}{\*\bkmkend AAAAAAAESW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E18_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAESX}{\*\bkmkend AAAAAAAESX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E17_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00020000u){\*\bkmkstart AAAAAAAESY}{\*\bkmkend AAAAAAAESY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E17_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000011u){\*\bkmkstart AAAAAAAESZ}{\*\bkmkend AAAAAAAESZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E17_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAETA}{\*\bkmkend AAAAAAAETA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E17_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAETB}{\*\bkmkend AAAAAAAETB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E16_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAAETC}{\*\bkmkend AAAAAAAETC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E16_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAETD}{\*\bkmkend AAAAAAAETD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E16_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAETE}{\*\bkmkend AAAAAAAETE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E16_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAETF}{\*\bkmkend AAAAAAAETF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E15_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00008000u){\*\bkmkstart AAAAAAAETG}{\*\bkmkend AAAAAAAETG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E15_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAAETH}{\*\bkmkend AAAAAAAETH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E15_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAETI}{\*\bkmkend AAAAAAAETI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E15_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAETJ}{\*\bkmkend AAAAAAAETJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E14_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00004000u){\*\bkmkstart AAAAAAAETK}{\*\bkmkend AAAAAAAETK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E14_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Eu){\*\bkmkstart AAAAAAAETL}{\*\bkmkend AAAAAAAETL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E14_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAETM}{\*\bkmkend AAAAAAAETM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E14_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAETN}{\*\bkmkend AAAAAAAETN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E13_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00002000u){\*\bkmkstart AAAAAAAETO}{\*\bkmkend AAAAAAAETO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E13_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Du){\*\bkmkstart AAAAAAAETP}{\*\bkmkend AAAAAAAETP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E13_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAETQ}{\*\bkmkend AAAAAAAETQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E13_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAETR}{\*\bkmkend AAAAAAAETR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E12_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001000u){\*\bkmkstart AAAAAAAETS}{\*\bkmkend AAAAAAAETS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E12_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAAETT}{\*\bkmkend AAAAAAAETT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E12_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAETU}{\*\bkmkend AAAAAAAETU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E12_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAETV}{\*\bkmkend AAAAAAAETV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E11_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAAETW}{\*\bkmkend AAAAAAAETW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E11_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAAETX}{\*\bkmkend AAAAAAAETX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E11_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAETY}{\*\bkmkend AAAAAAAETY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E11_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAETZ}{\*\bkmkend AAAAAAAETZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E10_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000400u){\*\bkmkstart AAAAAAAEUA}{\*\bkmkend AAAAAAAEUA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E10_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAAEUB}{\*\bkmkend AAAAAAAEUB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E10_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEUC}{\*\bkmkend AAAAAAAEUC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E10_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEUD}{\*\bkmkend AAAAAAAEUD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E9_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000200u){\*\bkmkstart AAAAAAAEUE}{\*\bkmkend AAAAAAAEUE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E9_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAAEUF}{\*\bkmkend AAAAAAAEUF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E9_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEUG}{\*\bkmkend AAAAAAAEUG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E9_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEUH}{\*\bkmkend AAAAAAAEUH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E8_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAAEUI}{\*\bkmkend AAAAAAAEUI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E8_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAEUJ}{\*\bkmkend AAAAAAAEUJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E8_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEUK}{\*\bkmkend AAAAAAAEUK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E8_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEUL}{\*\bkmkend AAAAAAAEUL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E7_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAAEUM}{\*\bkmkend AAAAAAAEUM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E7_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAEUN}{\*\bkmkend AAAAAAAEUN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E7_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEUO}{\*\bkmkend AAAAAAAEUO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E7_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEUP}{\*\bkmkend AAAAAAAEUP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E6_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAAEUQ}{\*\bkmkend AAAAAAAEUQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E6_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAAEUR}{\*\bkmkend AAAAAAAEUR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E6_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEUS}{\*\bkmkend AAAAAAAEUS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E6_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEUT}{\*\bkmkend AAAAAAAEUT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E5_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAAEUU}{\*\bkmkend AAAAAAAEUU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E5_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAAEUV}{\*\bkmkend AAAAAAAEUV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E5_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEUW}{\*\bkmkend AAAAAAAEUW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E5_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEUX}{\*\bkmkend AAAAAAAEUX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E4_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAEUY}{\*\bkmkend AAAAAAAEUY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E4_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAEUZ}{\*\bkmkend AAAAAAAEUZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E4_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEVA}{\*\bkmkend AAAAAAAEVA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E4_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEVB}{\*\bkmkend AAAAAAAEVB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E3_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAEVC}{\*\bkmkend AAAAAAAEVC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E3_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAEVD}{\*\bkmkend AAAAAAAEVD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E3_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEVE}{\*\bkmkend AAAAAAAEVE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E3_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEVF}{\*\bkmkend AAAAAAAEVF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E2_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAEVG}{\*\bkmkend AAAAAAAEVG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E2_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAEVH}{\*\bkmkend AAAAAAAEVH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E2_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEVI}{\*\bkmkend AAAAAAAEVI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E2_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEVJ}{\*\bkmkend AAAAAAAEVJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E1_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAEVK}{\*\bkmkend AAAAAAAEVK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E1_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEVL}{\*\bkmkend AAAAAAAEVL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E1_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEVM}{\*\bkmkend AAAAAAAEVM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E1_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEVN}{\*\bkmkend AAAAAAAEVN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E0_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEVO}{\*\bkmkend AAAAAAAEVO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E0_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEVP}{\*\bkmkend AAAAAAAEVP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E0_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEVQ}{\*\bkmkend AAAAAAAEVQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_E0_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEVR}{\*\bkmkend AAAAAAAEVR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E63_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x80000000u){\*\bkmkstart AAAAAAAEVT}{\*\bkmkend AAAAAAAEVT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E63_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAAEVU}{\*\bkmkend AAAAAAAEVU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E63_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEVV}{\*\bkmkend AAAAAAAEVV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E63_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEVW}{\*\bkmkend AAAAAAAEVW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E62_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x40000000u){\*\bkmkstart AAAAAAAEVX}{\*\bkmkend AAAAAAAEVX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E62_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Eu){\*\bkmkstart AAAAAAAEVY}{\*\bkmkend AAAAAAAEVY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E62_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEVZ}{\*\bkmkend AAAAAAAEVZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E62_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEWA}{\*\bkmkend AAAAAAAEWA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E61_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x20000000u){\*\bkmkstart AAAAAAAEWB}{\*\bkmkend AAAAAAAEWB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E61_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Du){\*\bkmkstart AAAAAAAEWC}{\*\bkmkend AAAAAAAEWC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E61_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEWD}{\*\bkmkend AAAAAAAEWD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E61_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEWE}{\*\bkmkend AAAAAAAEWE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E60_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x10000000u){\*\bkmkstart AAAAAAAEWF}{\*\bkmkend AAAAAAAEWF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E60_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAAEWG}{\*\bkmkend AAAAAAAEWG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E60_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEWH}{\*\bkmkend AAAAAAAEWH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E60_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEWI}{\*\bkmkend AAAAAAAEWI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E59_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x08000000u){\*\bkmkstart AAAAAAAEWJ}{\*\bkmkend AAAAAAAEWJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E59_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Bu){\*\bkmkstart AAAAAAAEWK}{\*\bkmkend AAAAAAAEWK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E59_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEWL}{\*\bkmkend AAAAAAAEWL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E59_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEWM}{\*\bkmkend AAAAAAAEWM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E58_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x04000000u){\*\bkmkstart AAAAAAAEWN}{\*\bkmkend AAAAAAAEWN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E58_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Au){\*\bkmkstart AAAAAAAEWO}{\*\bkmkend AAAAAAAEWO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E58_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEWP}{\*\bkmkend AAAAAAAEWP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E58_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEWQ}{\*\bkmkend AAAAAAAEWQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E57_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x02000000u){\*\bkmkstart AAAAAAAEWR}{\*\bkmkend AAAAAAAEWR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E57_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000019u){\*\bkmkstart AAAAAAAEWS}{\*\bkmkend AAAAAAAEWS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E57_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEWT}{\*\bkmkend AAAAAAAEWT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E57_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEWU}{\*\bkmkend AAAAAAAEWU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E56_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x01000000u){\*\bkmkstart AAAAAAAEWV}{\*\bkmkend AAAAAAAEWV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E56_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAAEWW}{\*\bkmkend AAAAAAAEWW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E56_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEWX}{\*\bkmkend AAAAAAAEWX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E56_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEWY}{\*\bkmkend AAAAAAAEWY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E55_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00800000u){\*\bkmkstart AAAAAAAEWZ}{\*\bkmkend AAAAAAAEWZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E55_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000017u){\*\bkmkstart AAAAAAAEXA}{\*\bkmkend AAAAAAAEXA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E55_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEXB}{\*\bkmkend AAAAAAAEXB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E55_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEXC}{\*\bkmkend AAAAAAAEXC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E54_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAAEXD}{\*\bkmkend AAAAAAAEXD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E54_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAAEXE}{\*\bkmkend AAAAAAAEXE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E54_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEXF}{\*\bkmkend AAAAAAAEXF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E54_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEXG}{\*\bkmkend AAAAAAAEXG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E53_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00200000u){\*\bkmkstart AAAAAAAEXH}{\*\bkmkend AAAAAAAEXH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E53_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAAEXI}{\*\bkmkend AAAAAAAEXI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E53_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEXJ}{\*\bkmkend AAAAAAAEXJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E53_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEXK}{\*\bkmkend AAAAAAAEXK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E52_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAAEXL}{\*\bkmkend AAAAAAAEXL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E52_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAAEXM}{\*\bkmkend AAAAAAAEXM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E52_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEXN}{\*\bkmkend AAAAAAAEXN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E52_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEXO}{\*\bkmkend AAAAAAAEXO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E51_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00080000u){\*\bkmkstart AAAAAAAEXP}{\*\bkmkend AAAAAAAEXP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E51_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000013u){\*\bkmkstart AAAAAAAEXQ}{\*\bkmkend AAAAAAAEXQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E51_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEXR}{\*\bkmkend AAAAAAAEXR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E51_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEXS}{\*\bkmkend AAAAAAAEXS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E50_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00040000u){\*\bkmkstart AAAAAAAEXT}{\*\bkmkend AAAAAAAEXT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E50_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000012u){\*\bkmkstart AAAAAAAEXU}{\*\bkmkend AAAAAAAEXU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E50_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEXV}{\*\bkmkend AAAAAAAEXV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E50_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEXW}{\*\bkmkend AAAAAAAEXW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E49_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00020000u){\*\bkmkstart AAAAAAAEXX}{\*\bkmkend AAAAAAAEXX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E49_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000011u){\*\bkmkstart AAAAAAAEXY}{\*\bkmkend AAAAAAAEXY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E49_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEXZ}{\*\bkmkend AAAAAAAEXZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E49_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEYA}{\*\bkmkend AAAAAAAEYA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E48_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAAEYB}{\*\bkmkend AAAAAAAEYB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E48_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAEYC}{\*\bkmkend AAAAAAAEYC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E48_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEYD}{\*\bkmkend AAAAAAAEYD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E48_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEYE}{\*\bkmkend AAAAAAAEYE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E47_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00008000u){\*\bkmkstart AAAAAAAEYF}{\*\bkmkend AAAAAAAEYF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E47_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAAEYG}{\*\bkmkend AAAAAAAEYG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E47_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEYH}{\*\bkmkend AAAAAAAEYH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E47_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEYI}{\*\bkmkend AAAAAAAEYI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E46_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00004000u){\*\bkmkstart AAAAAAAEYJ}{\*\bkmkend AAAAAAAEYJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E46_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Eu){\*\bkmkstart AAAAAAAEYK}{\*\bkmkend AAAAAAAEYK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E46_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEYL}{\*\bkmkend AAAAAAAEYL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E46_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEYM}{\*\bkmkend AAAAAAAEYM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E45_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00002000u){\*\bkmkstart AAAAAAAEYN}{\*\bkmkend AAAAAAAEYN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E45_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Du){\*\bkmkstart AAAAAAAEYO}{\*\bkmkend AAAAAAAEYO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E45_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEYP}{\*\bkmkend AAAAAAAEYP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E45_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEYQ}{\*\bkmkend AAAAAAAEYQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E44_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001000u){\*\bkmkstart AAAAAAAEYR}{\*\bkmkend AAAAAAAEYR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E44_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAAEYS}{\*\bkmkend AAAAAAAEYS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E44_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEYT}{\*\bkmkend AAAAAAAEYT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E44_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEYU}{\*\bkmkend AAAAAAAEYU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E43_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAAEYV}{\*\bkmkend AAAAAAAEYV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E43_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAAEYW}{\*\bkmkend AAAAAAAEYW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E43_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEYX}{\*\bkmkend AAAAAAAEYX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E43_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEYY}{\*\bkmkend AAAAAAAEYY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E42_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000400u){\*\bkmkstart AAAAAAAEYZ}{\*\bkmkend AAAAAAAEYZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E42_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAAEZA}{\*\bkmkend AAAAAAAEZA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E42_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEZB}{\*\bkmkend AAAAAAAEZB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E42_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEZC}{\*\bkmkend AAAAAAAEZC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E41_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000200u){\*\bkmkstart AAAAAAAEZD}{\*\bkmkend AAAAAAAEZD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E41_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAAEZE}{\*\bkmkend AAAAAAAEZE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E41_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEZF}{\*\bkmkend AAAAAAAEZF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E41_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEZG}{\*\bkmkend AAAAAAAEZG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E40_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAAEZH}{\*\bkmkend AAAAAAAEZH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E40_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAEZI}{\*\bkmkend AAAAAAAEZI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E40_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEZJ}{\*\bkmkend AAAAAAAEZJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E40_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEZK}{\*\bkmkend AAAAAAAEZK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E39_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAAEZL}{\*\bkmkend AAAAAAAEZL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E39_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAEZM}{\*\bkmkend AAAAAAAEZM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E39_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEZN}{\*\bkmkend AAAAAAAEZN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E39_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEZO}{\*\bkmkend AAAAAAAEZO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E38_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAAEZP}{\*\bkmkend AAAAAAAEZP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E38_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAAEZQ}{\*\bkmkend AAAAAAAEZQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E38_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEZR}{\*\bkmkend AAAAAAAEZR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E38_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEZS}{\*\bkmkend AAAAAAAEZS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E37_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAAEZT}{\*\bkmkend AAAAAAAEZT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E37_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAAEZU}{\*\bkmkend AAAAAAAEZU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E37_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEZV}{\*\bkmkend AAAAAAAEZV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E37_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAEZW}{\*\bkmkend AAAAAAAEZW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E36_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAEZX}{\*\bkmkend AAAAAAAEZX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E36_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAEZY}{\*\bkmkend AAAAAAAEZY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E36_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEZZ}{\*\bkmkend AAAAAAAEZZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E36_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFAA}{\*\bkmkend AAAAAAAFAA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E35_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAFAB}{\*\bkmkend AAAAAAAFAB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E35_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAFAC}{\*\bkmkend AAAAAAAFAC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E35_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFAD}{\*\bkmkend AAAAAAAFAD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E35_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFAE}{\*\bkmkend AAAAAAAFAE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E34_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAFAF}{\*\bkmkend AAAAAAAFAF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E34_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAFAG}{\*\bkmkend AAAAAAAFAG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E34_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFAH}{\*\bkmkend AAAAAAAFAH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E34_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFAI}{\*\bkmkend AAAAAAAFAI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E33_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAFAJ}{\*\bkmkend AAAAAAAFAJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E33_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFAK}{\*\bkmkend AAAAAAAFAK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E33_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFAL}{\*\bkmkend AAAAAAAFAL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E33_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFAM}{\*\bkmkend AAAAAAAFAM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E32_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFAN}{\*\bkmkend AAAAAAAFAN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E32_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFAO}{\*\bkmkend AAAAAAAFAO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E32_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFAP}{\*\bkmkend AAAAAAAFAP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_E32_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFAQ}{\*\bkmkend AAAAAAAFAQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I31_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x80000000u){\*\bkmkstart AAAAAAAFAS}{\*\bkmkend AAAAAAAFAS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I31_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAAFAT}{\*\bkmkend AAAAAAAFAT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I31_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFAU}{\*\bkmkend AAAAAAAFAU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I30_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x40000000u){\*\bkmkstart AAAAAAAFAV}{\*\bkmkend AAAAAAAFAV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I30_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Eu){\*\bkmkstart AAAAAAAFAW}{\*\bkmkend AAAAAAAFAW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I30_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFAX}{\*\bkmkend AAAAAAAFAX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I29_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x20000000u){\*\bkmkstart AAAAAAAFAY}{\*\bkmkend AAAAAAAFAY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I29_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Du){\*\bkmkstart AAAAAAAFAZ}{\*\bkmkend AAAAAAAFAZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I29_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFBA}{\*\bkmkend AAAAAAAFBA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I28_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x10000000u){\*\bkmkstart AAAAAAAFBB}{\*\bkmkend AAAAAAAFBB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I28_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAAFBC}{\*\bkmkend AAAAAAAFBC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I28_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFBD}{\*\bkmkend AAAAAAAFBD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I27_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x08000000u){\*\bkmkstart AAAAAAAFBE}{\*\bkmkend AAAAAAAFBE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I27_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Bu){\*\bkmkstart AAAAAAAFBF}{\*\bkmkend AAAAAAAFBF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I27_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFBG}{\*\bkmkend AAAAAAAFBG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I26_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x04000000u){\*\bkmkstart AAAAAAAFBH}{\*\bkmkend AAAAAAAFBH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I26_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Au){\*\bkmkstart AAAAAAAFBI}{\*\bkmkend AAAAAAAFBI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I26_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFBJ}{\*\bkmkend AAAAAAAFBJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I25_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x02000000u){\*\bkmkstart AAAAAAAFBK}{\*\bkmkend AAAAAAAFBK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I25_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000019u){\*\bkmkstart AAAAAAAFBL}{\*\bkmkend AAAAAAAFBL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I25_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFBM}{\*\bkmkend AAAAAAAFBM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I24_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x01000000u){\*\bkmkstart AAAAAAAFBN}{\*\bkmkend AAAAAAAFBN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I24_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAAFBO}{\*\bkmkend AAAAAAAFBO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I24_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFBP}{\*\bkmkend AAAAAAAFBP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I23_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00800000u){\*\bkmkstart AAAAAAAFBQ}{\*\bkmkend AAAAAAAFBQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I23_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000017u){\*\bkmkstart AAAAAAAFBR}{\*\bkmkend AAAAAAAFBR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I23_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFBS}{\*\bkmkend AAAAAAAFBS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I22_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAAFBT}{\*\bkmkend AAAAAAAFBT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I22_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAAFBU}{\*\bkmkend AAAAAAAFBU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I22_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFBV}{\*\bkmkend AAAAAAAFBV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I21_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00200000u){\*\bkmkstart AAAAAAAFBW}{\*\bkmkend AAAAAAAFBW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I21_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAAFBX}{\*\bkmkend AAAAAAAFBX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I21_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFBY}{\*\bkmkend AAAAAAAFBY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I20_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAAFBZ}{\*\bkmkend AAAAAAAFBZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I20_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAAFCA}{\*\bkmkend AAAAAAAFCA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I20_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFCB}{\*\bkmkend AAAAAAAFCB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I19_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00080000u){\*\bkmkstart AAAAAAAFCC}{\*\bkmkend AAAAAAAFCC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I19_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000013u){\*\bkmkstart AAAAAAAFCD}{\*\bkmkend AAAAAAAFCD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I19_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFCE}{\*\bkmkend AAAAAAAFCE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I18_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00040000u){\*\bkmkstart AAAAAAAFCF}{\*\bkmkend AAAAAAAFCF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I18_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000012u){\*\bkmkstart AAAAAAAFCG}{\*\bkmkend AAAAAAAFCG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I18_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFCH}{\*\bkmkend AAAAAAAFCH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I17_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00020000u){\*\bkmkstart AAAAAAAFCI}{\*\bkmkend AAAAAAAFCI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I17_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000011u){\*\bkmkstart AAAAAAAFCJ}{\*\bkmkend AAAAAAAFCJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I17_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFCK}{\*\bkmkend AAAAAAAFCK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I16_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAAFCL}{\*\bkmkend AAAAAAAFCL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I16_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAFCM}{\*\bkmkend AAAAAAAFCM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I16_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFCN}{\*\bkmkend AAAAAAAFCN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I15_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00008000u){\*\bkmkstart AAAAAAAFCO}{\*\bkmkend AAAAAAAFCO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I15_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAAFCP}{\*\bkmkend AAAAAAAFCP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I15_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFCQ}{\*\bkmkend AAAAAAAFCQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I14_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00004000u){\*\bkmkstart AAAAAAAFCR}{\*\bkmkend AAAAAAAFCR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I14_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Eu){\*\bkmkstart AAAAAAAFCS}{\*\bkmkend AAAAAAAFCS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I14_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFCT}{\*\bkmkend AAAAAAAFCT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I13_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00002000u){\*\bkmkstart AAAAAAAFCU}{\*\bkmkend AAAAAAAFCU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I13_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Du){\*\bkmkstart AAAAAAAFCV}{\*\bkmkend AAAAAAAFCV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I13_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFCW}{\*\bkmkend AAAAAAAFCW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I12_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001000u){\*\bkmkstart AAAAAAAFCX}{\*\bkmkend AAAAAAAFCX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I12_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAAFCY}{\*\bkmkend AAAAAAAFCY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I12_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFCZ}{\*\bkmkend AAAAAAAFCZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I11_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAAFDA}{\*\bkmkend AAAAAAAFDA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I11_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAAFDB}{\*\bkmkend AAAAAAAFDB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I11_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFDC}{\*\bkmkend AAAAAAAFDC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I10_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000400u){\*\bkmkstart AAAAAAAFDD}{\*\bkmkend AAAAAAAFDD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I10_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAAFDE}{\*\bkmkend AAAAAAAFDE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I10_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFDF}{\*\bkmkend AAAAAAAFDF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I9_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000200u){\*\bkmkstart AAAAAAAFDG}{\*\bkmkend AAAAAAAFDG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I9_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAAFDH}{\*\bkmkend AAAAAAAFDH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I9_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFDI}{\*\bkmkend AAAAAAAFDI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I8_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAAFDJ}{\*\bkmkend AAAAAAAFDJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I8_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAFDK}{\*\bkmkend AAAAAAAFDK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I8_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFDL}{\*\bkmkend AAAAAAAFDL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I7_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAAFDM}{\*\bkmkend AAAAAAAFDM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I7_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAFDN}{\*\bkmkend AAAAAAAFDN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I7_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFDO}{\*\bkmkend AAAAAAAFDO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I6_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAAFDP}{\*\bkmkend AAAAAAAFDP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I6_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAAFDQ}{\*\bkmkend AAAAAAAFDQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I6_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFDR}{\*\bkmkend AAAAAAAFDR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I5_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAAFDS}{\*\bkmkend AAAAAAAFDS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I5_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAAFDT}{\*\bkmkend AAAAAAAFDT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I5_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFDU}{\*\bkmkend AAAAAAAFDU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I4_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAFDV}{\*\bkmkend AAAAAAAFDV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I4_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAFDW}{\*\bkmkend AAAAAAAFDW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I4_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFDX}{\*\bkmkend AAAAAAAFDX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I3_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAFDY}{\*\bkmkend AAAAAAAFDY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I3_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAFDZ}{\*\bkmkend AAAAAAAFDZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I3_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFEA}{\*\bkmkend AAAAAAAFEA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I2_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAFEB}{\*\bkmkend AAAAAAAFEB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I2_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAFEC}{\*\bkmkend AAAAAAAFEC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I2_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFED}{\*\bkmkend AAAAAAAFED} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I1_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAFEE}{\*\bkmkend AAAAAAAFEE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I1_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFEF}{\*\bkmkend AAAAAAAFEF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I1_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFEG}{\*\bkmkend AAAAAAAFEG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I0_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFEH}{\*\bkmkend AAAAAAAFEH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I0_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFEI}{\*\bkmkend AAAAAAAFEI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_I0_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFEJ}{\*\bkmkend AAAAAAAFEJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I63_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x80000000u){\*\bkmkstart AAAAAAAFEL}{\*\bkmkend AAAAAAAFEL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I63_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAAFEM}{\*\bkmkend AAAAAAAFEM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I63_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFEN}{\*\bkmkend AAAAAAAFEN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I62_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x40000000u){\*\bkmkstart AAAAAAAFEO}{\*\bkmkend AAAAAAAFEO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I62_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Eu){\*\bkmkstart AAAAAAAFEP}{\*\bkmkend AAAAAAAFEP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I62_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFEQ}{\*\bkmkend AAAAAAAFEQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I61_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x20000000u){\*\bkmkstart AAAAAAAFER}{\*\bkmkend AAAAAAAFER} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I61_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Du){\*\bkmkstart AAAAAAAFES}{\*\bkmkend AAAAAAAFES} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I61_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFET}{\*\bkmkend AAAAAAAFET} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I60_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x10000000u){\*\bkmkstart AAAAAAAFEU}{\*\bkmkend AAAAAAAFEU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I60_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAAFEV}{\*\bkmkend AAAAAAAFEV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I60_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFEW}{\*\bkmkend AAAAAAAFEW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I59_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x08000000u){\*\bkmkstart AAAAAAAFEX}{\*\bkmkend AAAAAAAFEX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I59_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Bu){\*\bkmkstart AAAAAAAFEY}{\*\bkmkend AAAAAAAFEY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I59_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFEZ}{\*\bkmkend AAAAAAAFEZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I58_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x04000000u){\*\bkmkstart AAAAAAAFFA}{\*\bkmkend AAAAAAAFFA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I58_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Au){\*\bkmkstart AAAAAAAFFB}{\*\bkmkend AAAAAAAFFB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I58_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFFC}{\*\bkmkend AAAAAAAFFC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I57_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x02000000u){\*\bkmkstart AAAAAAAFFD}{\*\bkmkend AAAAAAAFFD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I57_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000019u){\*\bkmkstart AAAAAAAFFE}{\*\bkmkend AAAAAAAFFE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I57_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFFF}{\*\bkmkend AAAAAAAFFF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I56_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x01000000u){\*\bkmkstart AAAAAAAFFG}{\*\bkmkend AAAAAAAFFG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I56_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAAFFH}{\*\bkmkend AAAAAAAFFH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I56_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFFI}{\*\bkmkend AAAAAAAFFI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I55_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00800000u){\*\bkmkstart AAAAAAAFFJ}{\*\bkmkend AAAAAAAFFJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I55_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000017u){\*\bkmkstart AAAAAAAFFK}{\*\bkmkend AAAAAAAFFK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I55_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFFL}{\*\bkmkend AAAAAAAFFL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I54_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAAFFM}{\*\bkmkend AAAAAAAFFM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I54_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAAFFN}{\*\bkmkend AAAAAAAFFN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I54_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFFO}{\*\bkmkend AAAAAAAFFO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I53_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00200000u){\*\bkmkstart AAAAAAAFFP}{\*\bkmkend AAAAAAAFFP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I53_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAAFFQ}{\*\bkmkend AAAAAAAFFQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I53_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFFR}{\*\bkmkend AAAAAAAFFR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I52_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAAFFS}{\*\bkmkend AAAAAAAFFS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I52_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAAFFT}{\*\bkmkend AAAAAAAFFT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I52_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFFU}{\*\bkmkend AAAAAAAFFU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I51_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00080000u){\*\bkmkstart AAAAAAAFFV}{\*\bkmkend AAAAAAAFFV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I51_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000013u){\*\bkmkstart AAAAAAAFFW}{\*\bkmkend AAAAAAAFFW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I51_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFFX}{\*\bkmkend AAAAAAAFFX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I50_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00040000u){\*\bkmkstart AAAAAAAFFY}{\*\bkmkend AAAAAAAFFY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I50_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000012u){\*\bkmkstart AAAAAAAFFZ}{\*\bkmkend AAAAAAAFFZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I50_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFGA}{\*\bkmkend AAAAAAAFGA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I49_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00020000u){\*\bkmkstart AAAAAAAFGB}{\*\bkmkend AAAAAAAFGB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I49_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000011u){\*\bkmkstart AAAAAAAFGC}{\*\bkmkend AAAAAAAFGC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I49_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFGD}{\*\bkmkend AAAAAAAFGD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I48_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAAFGE}{\*\bkmkend AAAAAAAFGE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I48_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAFGF}{\*\bkmkend AAAAAAAFGF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I48_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFGG}{\*\bkmkend AAAAAAAFGG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I47_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00008000u){\*\bkmkstart AAAAAAAFGH}{\*\bkmkend AAAAAAAFGH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I47_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAAFGI}{\*\bkmkend AAAAAAAFGI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I47_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFGJ}{\*\bkmkend AAAAAAAFGJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I46_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00004000u){\*\bkmkstart AAAAAAAFGK}{\*\bkmkend AAAAAAAFGK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I46_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Eu){\*\bkmkstart AAAAAAAFGL}{\*\bkmkend AAAAAAAFGL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I46_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFGM}{\*\bkmkend AAAAAAAFGM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I45_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00002000u){\*\bkmkstart AAAAAAAFGN}{\*\bkmkend AAAAAAAFGN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I45_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Du){\*\bkmkstart AAAAAAAFGO}{\*\bkmkend AAAAAAAFGO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I45_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFGP}{\*\bkmkend AAAAAAAFGP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I44_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001000u){\*\bkmkstart AAAAAAAFGQ}{\*\bkmkend AAAAAAAFGQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I44_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAAFGR}{\*\bkmkend AAAAAAAFGR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I44_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFGS}{\*\bkmkend AAAAAAAFGS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I43_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAAFGT}{\*\bkmkend AAAAAAAFGT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I43_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAAFGU}{\*\bkmkend AAAAAAAFGU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I43_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFGV}{\*\bkmkend AAAAAAAFGV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I42_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000400u){\*\bkmkstart AAAAAAAFGW}{\*\bkmkend AAAAAAAFGW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I42_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAAFGX}{\*\bkmkend AAAAAAAFGX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I42_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFGY}{\*\bkmkend AAAAAAAFGY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I41_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000200u){\*\bkmkstart AAAAAAAFGZ}{\*\bkmkend AAAAAAAFGZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I41_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAAFHA}{\*\bkmkend AAAAAAAFHA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I41_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFHB}{\*\bkmkend AAAAAAAFHB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I40_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAAFHC}{\*\bkmkend AAAAAAAFHC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I40_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAFHD}{\*\bkmkend AAAAAAAFHD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I40_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFHE}{\*\bkmkend AAAAAAAFHE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I39_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAAFHF}{\*\bkmkend AAAAAAAFHF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I39_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAFHG}{\*\bkmkend AAAAAAAFHG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I39_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFHH}{\*\bkmkend AAAAAAAFHH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I38_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAAFHI}{\*\bkmkend AAAAAAAFHI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I38_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAAFHJ}{\*\bkmkend AAAAAAAFHJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I38_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFHK}{\*\bkmkend AAAAAAAFHK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I37_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAAFHL}{\*\bkmkend AAAAAAAFHL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I37_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAAFHM}{\*\bkmkend AAAAAAAFHM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I37_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFHN}{\*\bkmkend AAAAAAAFHN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I36_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAFHO}{\*\bkmkend AAAAAAAFHO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I36_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAFHP}{\*\bkmkend AAAAAAAFHP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I36_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFHQ}{\*\bkmkend AAAAAAAFHQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I35_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAFHR}{\*\bkmkend AAAAAAAFHR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I35_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAFHS}{\*\bkmkend AAAAAAAFHS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I35_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFHT}{\*\bkmkend AAAAAAAFHT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I34_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAFHU}{\*\bkmkend AAAAAAAFHU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I34_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAFHV}{\*\bkmkend AAAAAAAFHV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I34_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFHW}{\*\bkmkend AAAAAAAFHW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I33_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAFHX}{\*\bkmkend AAAAAAAFHX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I33_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFHY}{\*\bkmkend AAAAAAAFHY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I33_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFHZ}{\*\bkmkend AAAAAAAFHZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I32_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFIA}{\*\bkmkend AAAAAAAFIA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I32_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFIB}{\*\bkmkend AAAAAAAFIB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_I32_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFIC}{\*\bkmkend AAAAAAAFIC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I31_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x80000000u){\*\bkmkstart AAAAAAAFIE}{\*\bkmkend AAAAAAAFIE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I31_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAAFIF}{\*\bkmkend AAAAAAAFIF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I31_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFIG}{\*\bkmkend AAAAAAAFIG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I31_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFIH}{\*\bkmkend AAAAAAAFIH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I30_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x40000000u){\*\bkmkstart AAAAAAAFII}{\*\bkmkend AAAAAAAFII} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I30_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Eu){\*\bkmkstart AAAAAAAFIJ}{\*\bkmkend AAAAAAAFIJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I30_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFIK}{\*\bkmkend AAAAAAAFIK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I30_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFIL}{\*\bkmkend AAAAAAAFIL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I29_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x20000000u){\*\bkmkstart AAAAAAAFIM}{\*\bkmkend AAAAAAAFIM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I29_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Du){\*\bkmkstart AAAAAAAFIN}{\*\bkmkend AAAAAAAFIN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I29_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFIO}{\*\bkmkend AAAAAAAFIO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I29_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFIP}{\*\bkmkend AAAAAAAFIP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I28_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x10000000u){\*\bkmkstart AAAAAAAFIQ}{\*\bkmkend AAAAAAAFIQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I28_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAAFIR}{\*\bkmkend AAAAAAAFIR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I28_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFIS}{\*\bkmkend AAAAAAAFIS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I28_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFIT}{\*\bkmkend AAAAAAAFIT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I27_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x08000000u){\*\bkmkstart AAAAAAAFIU}{\*\bkmkend AAAAAAAFIU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I27_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Bu){\*\bkmkstart AAAAAAAFIV}{\*\bkmkend AAAAAAAFIV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I27_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFIW}{\*\bkmkend AAAAAAAFIW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I27_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFIX}{\*\bkmkend AAAAAAAFIX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I26_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x04000000u){\*\bkmkstart AAAAAAAFIY}{\*\bkmkend AAAAAAAFIY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I26_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Au){\*\bkmkstart AAAAAAAFIZ}{\*\bkmkend AAAAAAAFIZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I26_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFJA}{\*\bkmkend AAAAAAAFJA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I26_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFJB}{\*\bkmkend AAAAAAAFJB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I25_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x02000000u){\*\bkmkstart AAAAAAAFJC}{\*\bkmkend AAAAAAAFJC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I25_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000019u){\*\bkmkstart AAAAAAAFJD}{\*\bkmkend AAAAAAAFJD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I25_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFJE}{\*\bkmkend AAAAAAAFJE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I25_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFJF}{\*\bkmkend AAAAAAAFJF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I24_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x01000000u){\*\bkmkstart AAAAAAAFJG}{\*\bkmkend AAAAAAAFJG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I24_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAAFJH}{\*\bkmkend AAAAAAAFJH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I24_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFJI}{\*\bkmkend AAAAAAAFJI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I24_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFJJ}{\*\bkmkend AAAAAAAFJJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I23_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00800000u){\*\bkmkstart AAAAAAAFJK}{\*\bkmkend AAAAAAAFJK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I23_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000017u){\*\bkmkstart AAAAAAAFJL}{\*\bkmkend AAAAAAAFJL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I23_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFJM}{\*\bkmkend AAAAAAAFJM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I23_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFJN}{\*\bkmkend AAAAAAAFJN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I22_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAAFJO}{\*\bkmkend AAAAAAAFJO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I22_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAAFJP}{\*\bkmkend AAAAAAAFJP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I22_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFJQ}{\*\bkmkend AAAAAAAFJQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I22_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFJR}{\*\bkmkend AAAAAAAFJR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I21_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00200000u){\*\bkmkstart AAAAAAAFJS}{\*\bkmkend AAAAAAAFJS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I21_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAAFJT}{\*\bkmkend AAAAAAAFJT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I21_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFJU}{\*\bkmkend AAAAAAAFJU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I21_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFJV}{\*\bkmkend AAAAAAAFJV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I20_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAAFJW}{\*\bkmkend AAAAAAAFJW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I20_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAAFJX}{\*\bkmkend AAAAAAAFJX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I20_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFJY}{\*\bkmkend AAAAAAAFJY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I20_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFJZ}{\*\bkmkend AAAAAAAFJZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I19_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00080000u){\*\bkmkstart AAAAAAAFKA}{\*\bkmkend AAAAAAAFKA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I19_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000013u){\*\bkmkstart AAAAAAAFKB}{\*\bkmkend AAAAAAAFKB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I19_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFKC}{\*\bkmkend AAAAAAAFKC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I19_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFKD}{\*\bkmkend AAAAAAAFKD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I18_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00040000u){\*\bkmkstart AAAAAAAFKE}{\*\bkmkend AAAAAAAFKE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I18_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000012u){\*\bkmkstart AAAAAAAFKF}{\*\bkmkend AAAAAAAFKF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I18_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFKG}{\*\bkmkend AAAAAAAFKG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I18_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFKH}{\*\bkmkend AAAAAAAFKH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I17_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00020000u){\*\bkmkstart AAAAAAAFKI}{\*\bkmkend AAAAAAAFKI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I17_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000011u){\*\bkmkstart AAAAAAAFKJ}{\*\bkmkend AAAAAAAFKJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I17_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFKK}{\*\bkmkend AAAAAAAFKK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I17_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFKL}{\*\bkmkend AAAAAAAFKL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I16_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAAFKM}{\*\bkmkend AAAAAAAFKM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I16_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAFKN}{\*\bkmkend AAAAAAAFKN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I16_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFKO}{\*\bkmkend AAAAAAAFKO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I16_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFKP}{\*\bkmkend AAAAAAAFKP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I15_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00008000u){\*\bkmkstart AAAAAAAFKQ}{\*\bkmkend AAAAAAAFKQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I15_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAAFKR}{\*\bkmkend AAAAAAAFKR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I15_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFKS}{\*\bkmkend AAAAAAAFKS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I15_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFKT}{\*\bkmkend AAAAAAAFKT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I14_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00004000u){\*\bkmkstart AAAAAAAFKU}{\*\bkmkend AAAAAAAFKU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I14_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Eu){\*\bkmkstart AAAAAAAFKV}{\*\bkmkend AAAAAAAFKV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I14_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFKW}{\*\bkmkend AAAAAAAFKW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I14_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFKX}{\*\bkmkend AAAAAAAFKX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I13_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00002000u){\*\bkmkstart AAAAAAAFKY}{\*\bkmkend AAAAAAAFKY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I13_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Du){\*\bkmkstart AAAAAAAFKZ}{\*\bkmkend AAAAAAAFKZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I13_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFLA}{\*\bkmkend AAAAAAAFLA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I13_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFLB}{\*\bkmkend AAAAAAAFLB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I12_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001000u){\*\bkmkstart AAAAAAAFLC}{\*\bkmkend AAAAAAAFLC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I12_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAAFLD}{\*\bkmkend AAAAAAAFLD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I12_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFLE}{\*\bkmkend AAAAAAAFLE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I12_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFLF}{\*\bkmkend AAAAAAAFLF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I11_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAAFLG}{\*\bkmkend AAAAAAAFLG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I11_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAAFLH}{\*\bkmkend AAAAAAAFLH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I11_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFLI}{\*\bkmkend AAAAAAAFLI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I11_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFLJ}{\*\bkmkend AAAAAAAFLJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I10_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000400u){\*\bkmkstart AAAAAAAFLK}{\*\bkmkend AAAAAAAFLK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I10_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAAFLL}{\*\bkmkend AAAAAAAFLL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I10_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFLM}{\*\bkmkend AAAAAAAFLM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I10_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFLN}{\*\bkmkend AAAAAAAFLN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I9_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000200u){\*\bkmkstart AAAAAAAFLO}{\*\bkmkend AAAAAAAFLO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I9_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAAFLP}{\*\bkmkend AAAAAAAFLP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I9_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFLQ}{\*\bkmkend AAAAAAAFLQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I9_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFLR}{\*\bkmkend AAAAAAAFLR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I8_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAAFLS}{\*\bkmkend AAAAAAAFLS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I8_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAFLT}{\*\bkmkend AAAAAAAFLT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I8_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFLU}{\*\bkmkend AAAAAAAFLU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I8_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFLV}{\*\bkmkend AAAAAAAFLV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I7_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAAFLW}{\*\bkmkend AAAAAAAFLW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I7_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAFLX}{\*\bkmkend AAAAAAAFLX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I7_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFLY}{\*\bkmkend AAAAAAAFLY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I7_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFLZ}{\*\bkmkend AAAAAAAFLZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I6_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAAFMA}{\*\bkmkend AAAAAAAFMA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I6_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAAFMB}{\*\bkmkend AAAAAAAFMB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I6_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFMC}{\*\bkmkend AAAAAAAFMC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I6_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFMD}{\*\bkmkend AAAAAAAFMD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I5_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAAFME}{\*\bkmkend AAAAAAAFME} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I5_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAAFMF}{\*\bkmkend AAAAAAAFMF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I5_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFMG}{\*\bkmkend AAAAAAAFMG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I5_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFMH}{\*\bkmkend AAAAAAAFMH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I4_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAFMI}{\*\bkmkend AAAAAAAFMI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I4_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAFMJ}{\*\bkmkend AAAAAAAFMJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I4_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFMK}{\*\bkmkend AAAAAAAFMK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I4_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFML}{\*\bkmkend AAAAAAAFML} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I3_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAFMM}{\*\bkmkend AAAAAAAFMM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I3_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAFMN}{\*\bkmkend AAAAAAAFMN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I3_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFMO}{\*\bkmkend AAAAAAAFMO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I3_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFMP}{\*\bkmkend AAAAAAAFMP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I2_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAFMQ}{\*\bkmkend AAAAAAAFMQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I2_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAFMR}{\*\bkmkend AAAAAAAFMR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I2_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFMS}{\*\bkmkend AAAAAAAFMS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I2_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFMT}{\*\bkmkend AAAAAAAFMT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I1_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAFMU}{\*\bkmkend AAAAAAAFMU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I1_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFMV}{\*\bkmkend AAAAAAAFMV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I1_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFMW}{\*\bkmkend AAAAAAAFMW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I1_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFMX}{\*\bkmkend AAAAAAAFMX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I0_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFMY}{\*\bkmkend AAAAAAAFMY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I0_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFMZ}{\*\bkmkend AAAAAAAFMZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I0_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFNA}{\*\bkmkend AAAAAAAFNA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_I0_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFNB}{\*\bkmkend AAAAAAAFNB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I63_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x80000000u){\*\bkmkstart AAAAAAAFND}{\*\bkmkend AAAAAAAFND} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I63_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAAFNE}{\*\bkmkend AAAAAAAFNE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I63_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFNF}{\*\bkmkend AAAAAAAFNF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I63_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFNG}{\*\bkmkend AAAAAAAFNG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I62_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x40000000u){\*\bkmkstart AAAAAAAFNH}{\*\bkmkend AAAAAAAFNH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I62_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Eu){\*\bkmkstart AAAAAAAFNI}{\*\bkmkend AAAAAAAFNI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I62_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFNJ}{\*\bkmkend AAAAAAAFNJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I62_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFNK}{\*\bkmkend AAAAAAAFNK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I61_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x20000000u){\*\bkmkstart AAAAAAAFNL}{\*\bkmkend AAAAAAAFNL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I61_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Du){\*\bkmkstart AAAAAAAFNM}{\*\bkmkend AAAAAAAFNM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I61_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFNN}{\*\bkmkend AAAAAAAFNN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I61_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFNO}{\*\bkmkend AAAAAAAFNO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I60_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x10000000u){\*\bkmkstart AAAAAAAFNP}{\*\bkmkend AAAAAAAFNP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I60_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAAFNQ}{\*\bkmkend AAAAAAAFNQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I60_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFNR}{\*\bkmkend AAAAAAAFNR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I60_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFNS}{\*\bkmkend AAAAAAAFNS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I59_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x08000000u){\*\bkmkstart AAAAAAAFNT}{\*\bkmkend AAAAAAAFNT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I59_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Bu){\*\bkmkstart AAAAAAAFNU}{\*\bkmkend AAAAAAAFNU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I59_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFNV}{\*\bkmkend AAAAAAAFNV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I59_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFNW}{\*\bkmkend AAAAAAAFNW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I58_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x04000000u){\*\bkmkstart AAAAAAAFNX}{\*\bkmkend AAAAAAAFNX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I58_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Au){\*\bkmkstart AAAAAAAFNY}{\*\bkmkend AAAAAAAFNY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I58_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFNZ}{\*\bkmkend AAAAAAAFNZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I58_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFOA}{\*\bkmkend AAAAAAAFOA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I57_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x02000000u){\*\bkmkstart AAAAAAAFOB}{\*\bkmkend AAAAAAAFOB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I57_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000019u){\*\bkmkstart AAAAAAAFOC}{\*\bkmkend AAAAAAAFOC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I57_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFOD}{\*\bkmkend AAAAAAAFOD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I57_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFOE}{\*\bkmkend AAAAAAAFOE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I56_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x01000000u){\*\bkmkstart AAAAAAAFOF}{\*\bkmkend AAAAAAAFOF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I56_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAAFOG}{\*\bkmkend AAAAAAAFOG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I56_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFOH}{\*\bkmkend AAAAAAAFOH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I56_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFOI}{\*\bkmkend AAAAAAAFOI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I55_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00800000u){\*\bkmkstart AAAAAAAFOJ}{\*\bkmkend AAAAAAAFOJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I55_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000017u){\*\bkmkstart AAAAAAAFOK}{\*\bkmkend AAAAAAAFOK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I55_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFOL}{\*\bkmkend AAAAAAAFOL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I55_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFOM}{\*\bkmkend AAAAAAAFOM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I54_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAAFON}{\*\bkmkend AAAAAAAFON} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I54_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAAFOO}{\*\bkmkend AAAAAAAFOO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I54_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFOP}{\*\bkmkend AAAAAAAFOP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I54_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFOQ}{\*\bkmkend AAAAAAAFOQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I53_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00200000u){\*\bkmkstart AAAAAAAFOR}{\*\bkmkend AAAAAAAFOR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I53_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAAFOS}{\*\bkmkend AAAAAAAFOS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I53_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFOT}{\*\bkmkend AAAAAAAFOT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I53_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFOU}{\*\bkmkend AAAAAAAFOU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I52_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAAFOV}{\*\bkmkend AAAAAAAFOV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I52_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAAFOW}{\*\bkmkend AAAAAAAFOW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I52_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFOX}{\*\bkmkend AAAAAAAFOX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I52_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFOY}{\*\bkmkend AAAAAAAFOY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I51_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00080000u){\*\bkmkstart AAAAAAAFOZ}{\*\bkmkend AAAAAAAFOZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I51_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000013u){\*\bkmkstart AAAAAAAFPA}{\*\bkmkend AAAAAAAFPA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I51_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFPB}{\*\bkmkend AAAAAAAFPB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I51_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFPC}{\*\bkmkend AAAAAAAFPC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I50_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00040000u){\*\bkmkstart AAAAAAAFPD}{\*\bkmkend AAAAAAAFPD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I50_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000012u){\*\bkmkstart AAAAAAAFPE}{\*\bkmkend AAAAAAAFPE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I50_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFPF}{\*\bkmkend AAAAAAAFPF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I50_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFPG}{\*\bkmkend AAAAAAAFPG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I49_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00020000u){\*\bkmkstart AAAAAAAFPH}{\*\bkmkend AAAAAAAFPH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I49_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000011u){\*\bkmkstart AAAAAAAFPI}{\*\bkmkend AAAAAAAFPI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I49_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFPJ}{\*\bkmkend AAAAAAAFPJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I49_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFPK}{\*\bkmkend AAAAAAAFPK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I48_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAAFPL}{\*\bkmkend AAAAAAAFPL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I48_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAFPM}{\*\bkmkend AAAAAAAFPM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I48_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFPN}{\*\bkmkend AAAAAAAFPN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I48_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFPO}{\*\bkmkend AAAAAAAFPO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I47_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00008000u){\*\bkmkstart AAAAAAAFPP}{\*\bkmkend AAAAAAAFPP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I47_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAAFPQ}{\*\bkmkend AAAAAAAFPQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I47_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFPR}{\*\bkmkend AAAAAAAFPR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I47_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFPS}{\*\bkmkend AAAAAAAFPS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I46_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00004000u){\*\bkmkstart AAAAAAAFPT}{\*\bkmkend AAAAAAAFPT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I46_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Eu){\*\bkmkstart AAAAAAAFPU}{\*\bkmkend AAAAAAAFPU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I46_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFPV}{\*\bkmkend AAAAAAAFPV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I46_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFPW}{\*\bkmkend AAAAAAAFPW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I45_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00002000u){\*\bkmkstart AAAAAAAFPX}{\*\bkmkend AAAAAAAFPX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I45_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Du){\*\bkmkstart AAAAAAAFPY}{\*\bkmkend AAAAAAAFPY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I45_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFPZ}{\*\bkmkend AAAAAAAFPZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I45_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFQA}{\*\bkmkend AAAAAAAFQA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I44_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001000u){\*\bkmkstart AAAAAAAFQB}{\*\bkmkend AAAAAAAFQB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I44_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAAFQC}{\*\bkmkend AAAAAAAFQC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I44_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFQD}{\*\bkmkend AAAAAAAFQD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I44_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFQE}{\*\bkmkend AAAAAAAFQE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I43_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAAFQF}{\*\bkmkend AAAAAAAFQF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I43_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAAFQG}{\*\bkmkend AAAAAAAFQG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I43_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFQH}{\*\bkmkend AAAAAAAFQH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I43_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFQI}{\*\bkmkend AAAAAAAFQI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I42_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000400u){\*\bkmkstart AAAAAAAFQJ}{\*\bkmkend AAAAAAAFQJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I42_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAAFQK}{\*\bkmkend AAAAAAAFQK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I42_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFQL}{\*\bkmkend AAAAAAAFQL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I42_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFQM}{\*\bkmkend AAAAAAAFQM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I41_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000200u){\*\bkmkstart AAAAAAAFQN}{\*\bkmkend AAAAAAAFQN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I41_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAAFQO}{\*\bkmkend AAAAAAAFQO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I41_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFQP}{\*\bkmkend AAAAAAAFQP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I41_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFQQ}{\*\bkmkend AAAAAAAFQQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I40_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAAFQR}{\*\bkmkend AAAAAAAFQR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I40_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAFQS}{\*\bkmkend AAAAAAAFQS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I40_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFQT}{\*\bkmkend AAAAAAAFQT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I40_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFQU}{\*\bkmkend AAAAAAAFQU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I39_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAAFQV}{\*\bkmkend AAAAAAAFQV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I39_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAFQW}{\*\bkmkend AAAAAAAFQW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I39_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFQX}{\*\bkmkend AAAAAAAFQX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I39_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFQY}{\*\bkmkend AAAAAAAFQY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I38_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAAFQZ}{\*\bkmkend AAAAAAAFQZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I38_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAAFRA}{\*\bkmkend AAAAAAAFRA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I38_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFRB}{\*\bkmkend AAAAAAAFRB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I38_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFRC}{\*\bkmkend AAAAAAAFRC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I37_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAAFRD}{\*\bkmkend AAAAAAAFRD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I37_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAAFRE}{\*\bkmkend AAAAAAAFRE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I37_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFRF}{\*\bkmkend AAAAAAAFRF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I37_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFRG}{\*\bkmkend AAAAAAAFRG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I36_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAFRH}{\*\bkmkend AAAAAAAFRH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I36_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAFRI}{\*\bkmkend AAAAAAAFRI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I36_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFRJ}{\*\bkmkend AAAAAAAFRJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I36_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFRK}{\*\bkmkend AAAAAAAFRK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I35_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAFRL}{\*\bkmkend AAAAAAAFRL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I35_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAFRM}{\*\bkmkend AAAAAAAFRM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I35_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFRN}{\*\bkmkend AAAAAAAFRN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I35_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFRO}{\*\bkmkend AAAAAAAFRO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I34_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAFRP}{\*\bkmkend AAAAAAAFRP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I34_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAFRQ}{\*\bkmkend AAAAAAAFRQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I34_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFRR}{\*\bkmkend AAAAAAAFRR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I34_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFRS}{\*\bkmkend AAAAAAAFRS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I33_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAFRT}{\*\bkmkend AAAAAAAFRT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I33_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFRU}{\*\bkmkend AAAAAAAFRU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I33_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFRV}{\*\bkmkend AAAAAAAFRV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I33_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFRW}{\*\bkmkend AAAAAAAFRW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I32_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFRX}{\*\bkmkend AAAAAAAFRX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I32_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFRY}{\*\bkmkend AAAAAAAFRY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I32_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFRZ}{\*\bkmkend AAAAAAAFRZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_I32_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFSA}{\*\bkmkend AAAAAAAFSA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I31_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x80000000u){\*\bkmkstart AAAAAAAFSC}{\*\bkmkend AAAAAAAFSC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I31_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAAFSD}{\*\bkmkend AAAAAAAFSD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I31_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFSE}{\*\bkmkend AAAAAAAFSE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I31_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFSF}{\*\bkmkend AAAAAAAFSF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I30_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x40000000u){\*\bkmkstart AAAAAAAFSG}{\*\bkmkend AAAAAAAFSG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I30_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Eu){\*\bkmkstart AAAAAAAFSH}{\*\bkmkend AAAAAAAFSH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I30_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFSI}{\*\bkmkend AAAAAAAFSI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I30_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFSJ}{\*\bkmkend AAAAAAAFSJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I29_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x20000000u){\*\bkmkstart AAAAAAAFSK}{\*\bkmkend AAAAAAAFSK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I29_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Du){\*\bkmkstart AAAAAAAFSL}{\*\bkmkend AAAAAAAFSL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I29_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFSM}{\*\bkmkend AAAAAAAFSM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I29_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFSN}{\*\bkmkend AAAAAAAFSN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I28_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x10000000u){\*\bkmkstart AAAAAAAFSO}{\*\bkmkend AAAAAAAFSO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I28_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAAFSP}{\*\bkmkend AAAAAAAFSP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I28_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFSQ}{\*\bkmkend AAAAAAAFSQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I28_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFSR}{\*\bkmkend AAAAAAAFSR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I27_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x08000000u){\*\bkmkstart AAAAAAAFSS}{\*\bkmkend AAAAAAAFSS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I27_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Bu){\*\bkmkstart AAAAAAAFST}{\*\bkmkend AAAAAAAFST} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I27_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFSU}{\*\bkmkend AAAAAAAFSU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I27_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFSV}{\*\bkmkend AAAAAAAFSV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I26_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x04000000u){\*\bkmkstart AAAAAAAFSW}{\*\bkmkend AAAAAAAFSW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I26_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Au){\*\bkmkstart AAAAAAAFSX}{\*\bkmkend AAAAAAAFSX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I26_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFSY}{\*\bkmkend AAAAAAAFSY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I26_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFSZ}{\*\bkmkend AAAAAAAFSZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I25_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x02000000u){\*\bkmkstart AAAAAAAFTA}{\*\bkmkend AAAAAAAFTA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I25_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000019u){\*\bkmkstart AAAAAAAFTB}{\*\bkmkend AAAAAAAFTB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I25_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFTC}{\*\bkmkend AAAAAAAFTC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I25_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFTD}{\*\bkmkend AAAAAAAFTD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I24_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x01000000u){\*\bkmkstart AAAAAAAFTE}{\*\bkmkend AAAAAAAFTE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I24_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAAFTF}{\*\bkmkend AAAAAAAFTF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I24_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFTG}{\*\bkmkend AAAAAAAFTG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I24_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFTH}{\*\bkmkend AAAAAAAFTH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I23_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00800000u){\*\bkmkstart AAAAAAAFTI}{\*\bkmkend AAAAAAAFTI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I23_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000017u){\*\bkmkstart AAAAAAAFTJ}{\*\bkmkend AAAAAAAFTJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I23_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFTK}{\*\bkmkend AAAAAAAFTK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I23_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFTL}{\*\bkmkend AAAAAAAFTL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I22_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAAFTM}{\*\bkmkend AAAAAAAFTM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I22_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAAFTN}{\*\bkmkend AAAAAAAFTN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I22_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFTO}{\*\bkmkend AAAAAAAFTO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I22_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFTP}{\*\bkmkend AAAAAAAFTP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I21_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00200000u){\*\bkmkstart AAAAAAAFTQ}{\*\bkmkend AAAAAAAFTQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I21_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAAFTR}{\*\bkmkend AAAAAAAFTR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I21_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFTS}{\*\bkmkend AAAAAAAFTS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I21_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFTT}{\*\bkmkend AAAAAAAFTT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I20_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAAFTU}{\*\bkmkend AAAAAAAFTU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I20_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAAFTV}{\*\bkmkend AAAAAAAFTV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I20_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFTW}{\*\bkmkend AAAAAAAFTW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I20_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFTX}{\*\bkmkend AAAAAAAFTX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I19_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00080000u){\*\bkmkstart AAAAAAAFTY}{\*\bkmkend AAAAAAAFTY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I19_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000013u){\*\bkmkstart AAAAAAAFTZ}{\*\bkmkend AAAAAAAFTZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I19_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFUA}{\*\bkmkend AAAAAAAFUA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I19_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFUB}{\*\bkmkend AAAAAAAFUB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I18_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00040000u){\*\bkmkstart AAAAAAAFUC}{\*\bkmkend AAAAAAAFUC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I18_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000012u){\*\bkmkstart AAAAAAAFUD}{\*\bkmkend AAAAAAAFUD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I18_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFUE}{\*\bkmkend AAAAAAAFUE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I18_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFUF}{\*\bkmkend AAAAAAAFUF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I17_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00020000u){\*\bkmkstart AAAAAAAFUG}{\*\bkmkend AAAAAAAFUG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I17_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000011u){\*\bkmkstart AAAAAAAFUH}{\*\bkmkend AAAAAAAFUH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I17_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFUI}{\*\bkmkend AAAAAAAFUI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I17_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFUJ}{\*\bkmkend AAAAAAAFUJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I16_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAAFUK}{\*\bkmkend AAAAAAAFUK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I16_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAFUL}{\*\bkmkend AAAAAAAFUL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I16_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFUM}{\*\bkmkend AAAAAAAFUM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I16_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFUN}{\*\bkmkend AAAAAAAFUN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I15_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00008000u){\*\bkmkstart AAAAAAAFUO}{\*\bkmkend AAAAAAAFUO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I15_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAAFUP}{\*\bkmkend AAAAAAAFUP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I15_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFUQ}{\*\bkmkend AAAAAAAFUQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I15_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFUR}{\*\bkmkend AAAAAAAFUR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I14_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00004000u){\*\bkmkstart AAAAAAAFUS}{\*\bkmkend AAAAAAAFUS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I14_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Eu){\*\bkmkstart AAAAAAAFUT}{\*\bkmkend AAAAAAAFUT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I14_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFUU}{\*\bkmkend AAAAAAAFUU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I14_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFUV}{\*\bkmkend AAAAAAAFUV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I13_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00002000u){\*\bkmkstart AAAAAAAFUW}{\*\bkmkend AAAAAAAFUW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I13_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Du){\*\bkmkstart AAAAAAAFUX}{\*\bkmkend AAAAAAAFUX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I13_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFUY}{\*\bkmkend AAAAAAAFUY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I13_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFUZ}{\*\bkmkend AAAAAAAFUZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I12_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001000u){\*\bkmkstart AAAAAAAFVA}{\*\bkmkend AAAAAAAFVA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I12_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAAFVB}{\*\bkmkend AAAAAAAFVB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I12_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFVC}{\*\bkmkend AAAAAAAFVC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I12_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFVD}{\*\bkmkend AAAAAAAFVD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I11_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAAFVE}{\*\bkmkend AAAAAAAFVE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I11_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAAFVF}{\*\bkmkend AAAAAAAFVF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I11_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFVG}{\*\bkmkend AAAAAAAFVG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I11_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFVH}{\*\bkmkend AAAAAAAFVH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I10_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000400u){\*\bkmkstart AAAAAAAFVI}{\*\bkmkend AAAAAAAFVI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I10_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAAFVJ}{\*\bkmkend AAAAAAAFVJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I10_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFVK}{\*\bkmkend AAAAAAAFVK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I10_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFVL}{\*\bkmkend AAAAAAAFVL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I9_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000200u){\*\bkmkstart AAAAAAAFVM}{\*\bkmkend AAAAAAAFVM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I9_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAAFVN}{\*\bkmkend AAAAAAAFVN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I9_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFVO}{\*\bkmkend AAAAAAAFVO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I9_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFVP}{\*\bkmkend AAAAAAAFVP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I8_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAAFVQ}{\*\bkmkend AAAAAAAFVQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I8_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAFVR}{\*\bkmkend AAAAAAAFVR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I8_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFVS}{\*\bkmkend AAAAAAAFVS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I8_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFVT}{\*\bkmkend AAAAAAAFVT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I7_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAAFVU}{\*\bkmkend AAAAAAAFVU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I7_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAFVV}{\*\bkmkend AAAAAAAFVV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I7_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFVW}{\*\bkmkend AAAAAAAFVW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I7_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFVX}{\*\bkmkend AAAAAAAFVX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I6_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAAFVY}{\*\bkmkend AAAAAAAFVY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I6_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAAFVZ}{\*\bkmkend AAAAAAAFVZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I6_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFWA}{\*\bkmkend AAAAAAAFWA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I6_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFWB}{\*\bkmkend AAAAAAAFWB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I5_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAAFWC}{\*\bkmkend AAAAAAAFWC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I5_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAAFWD}{\*\bkmkend AAAAAAAFWD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I5_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFWE}{\*\bkmkend AAAAAAAFWE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I5_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFWF}{\*\bkmkend AAAAAAAFWF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I4_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAFWG}{\*\bkmkend AAAAAAAFWG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I4_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAFWH}{\*\bkmkend AAAAAAAFWH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I4_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFWI}{\*\bkmkend AAAAAAAFWI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I4_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFWJ}{\*\bkmkend AAAAAAAFWJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I3_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAFWK}{\*\bkmkend AAAAAAAFWK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I3_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAFWL}{\*\bkmkend AAAAAAAFWL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I3_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFWM}{\*\bkmkend AAAAAAAFWM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I3_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFWN}{\*\bkmkend AAAAAAAFWN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I2_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAFWO}{\*\bkmkend AAAAAAAFWO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I2_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAFWP}{\*\bkmkend AAAAAAAFWP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I2_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFWQ}{\*\bkmkend AAAAAAAFWQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I2_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFWR}{\*\bkmkend AAAAAAAFWR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I1_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAFWS}{\*\bkmkend AAAAAAAFWS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I1_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFWT}{\*\bkmkend AAAAAAAFWT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I1_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFWU}{\*\bkmkend AAAAAAAFWU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I1_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFWV}{\*\bkmkend AAAAAAAFWV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I0_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFWW}{\*\bkmkend AAAAAAAFWW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I0_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFWX}{\*\bkmkend AAAAAAAFWX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I0_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFWY}{\*\bkmkend AAAAAAAFWY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_I0_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFWZ}{\*\bkmkend AAAAAAAFWZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I63_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x80000000u){\*\bkmkstart AAAAAAAFXB}{\*\bkmkend AAAAAAAFXB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I63_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAAFXC}{\*\bkmkend AAAAAAAFXC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I63_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFXD}{\*\bkmkend AAAAAAAFXD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I63_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFXE}{\*\bkmkend AAAAAAAFXE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I62_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x40000000u){\*\bkmkstart AAAAAAAFXF}{\*\bkmkend AAAAAAAFXF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I62_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Eu){\*\bkmkstart AAAAAAAFXG}{\*\bkmkend AAAAAAAFXG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I62_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFXH}{\*\bkmkend AAAAAAAFXH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I62_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFXI}{\*\bkmkend AAAAAAAFXI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I61_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x20000000u){\*\bkmkstart AAAAAAAFXJ}{\*\bkmkend AAAAAAAFXJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I61_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Du){\*\bkmkstart AAAAAAAFXK}{\*\bkmkend AAAAAAAFXK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I61_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFXL}{\*\bkmkend AAAAAAAFXL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I61_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFXM}{\*\bkmkend AAAAAAAFXM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I60_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x10000000u){\*\bkmkstart AAAAAAAFXN}{\*\bkmkend AAAAAAAFXN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I60_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAAFXO}{\*\bkmkend AAAAAAAFXO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I60_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFXP}{\*\bkmkend AAAAAAAFXP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I60_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFXQ}{\*\bkmkend AAAAAAAFXQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I59_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x08000000u){\*\bkmkstart AAAAAAAFXR}{\*\bkmkend AAAAAAAFXR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I59_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Bu){\*\bkmkstart AAAAAAAFXS}{\*\bkmkend AAAAAAAFXS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I59_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFXT}{\*\bkmkend AAAAAAAFXT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I59_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFXU}{\*\bkmkend AAAAAAAFXU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I58_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x04000000u){\*\bkmkstart AAAAAAAFXV}{\*\bkmkend AAAAAAAFXV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I58_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Au){\*\bkmkstart AAAAAAAFXW}{\*\bkmkend AAAAAAAFXW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I58_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFXX}{\*\bkmkend AAAAAAAFXX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I58_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFXY}{\*\bkmkend AAAAAAAFXY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I57_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x02000000u){\*\bkmkstart AAAAAAAFXZ}{\*\bkmkend AAAAAAAFXZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I57_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000019u){\*\bkmkstart AAAAAAAFYA}{\*\bkmkend AAAAAAAFYA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I57_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFYB}{\*\bkmkend AAAAAAAFYB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I57_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFYC}{\*\bkmkend AAAAAAAFYC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I56_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x01000000u){\*\bkmkstart AAAAAAAFYD}{\*\bkmkend AAAAAAAFYD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I56_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAAFYE}{\*\bkmkend AAAAAAAFYE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I56_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFYF}{\*\bkmkend AAAAAAAFYF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I56_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFYG}{\*\bkmkend AAAAAAAFYG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I55_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00800000u){\*\bkmkstart AAAAAAAFYH}{\*\bkmkend AAAAAAAFYH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I55_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000017u){\*\bkmkstart AAAAAAAFYI}{\*\bkmkend AAAAAAAFYI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I55_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFYJ}{\*\bkmkend AAAAAAAFYJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I55_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFYK}{\*\bkmkend AAAAAAAFYK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I54_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAAFYL}{\*\bkmkend AAAAAAAFYL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I54_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAAFYM}{\*\bkmkend AAAAAAAFYM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I54_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFYN}{\*\bkmkend AAAAAAAFYN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I54_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFYO}{\*\bkmkend AAAAAAAFYO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I53_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00200000u){\*\bkmkstart AAAAAAAFYP}{\*\bkmkend AAAAAAAFYP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I53_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAAFYQ}{\*\bkmkend AAAAAAAFYQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I53_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFYR}{\*\bkmkend AAAAAAAFYR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I53_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFYS}{\*\bkmkend AAAAAAAFYS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I52_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAAFYT}{\*\bkmkend AAAAAAAFYT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I52_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAAFYU}{\*\bkmkend AAAAAAAFYU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I52_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFYV}{\*\bkmkend AAAAAAAFYV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I52_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFYW}{\*\bkmkend AAAAAAAFYW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I51_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00080000u){\*\bkmkstart AAAAAAAFYX}{\*\bkmkend AAAAAAAFYX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I51_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000013u){\*\bkmkstart AAAAAAAFYY}{\*\bkmkend AAAAAAAFYY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I51_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFYZ}{\*\bkmkend AAAAAAAFYZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I51_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFZA}{\*\bkmkend AAAAAAAFZA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I50_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00040000u){\*\bkmkstart AAAAAAAFZB}{\*\bkmkend AAAAAAAFZB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I50_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000012u){\*\bkmkstart AAAAAAAFZC}{\*\bkmkend AAAAAAAFZC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I50_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFZD}{\*\bkmkend AAAAAAAFZD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I50_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFZE}{\*\bkmkend AAAAAAAFZE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I49_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00020000u){\*\bkmkstart AAAAAAAFZF}{\*\bkmkend AAAAAAAFZF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I49_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000011u){\*\bkmkstart AAAAAAAFZG}{\*\bkmkend AAAAAAAFZG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I49_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFZH}{\*\bkmkend AAAAAAAFZH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I49_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFZI}{\*\bkmkend AAAAAAAFZI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I48_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAAFZJ}{\*\bkmkend AAAAAAAFZJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I48_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAFZK}{\*\bkmkend AAAAAAAFZK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I48_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFZL}{\*\bkmkend AAAAAAAFZL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I48_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFZM}{\*\bkmkend AAAAAAAFZM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I47_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00008000u){\*\bkmkstart AAAAAAAFZN}{\*\bkmkend AAAAAAAFZN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I47_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAAFZO}{\*\bkmkend AAAAAAAFZO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I47_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFZP}{\*\bkmkend AAAAAAAFZP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I47_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFZQ}{\*\bkmkend AAAAAAAFZQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I46_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00004000u){\*\bkmkstart AAAAAAAFZR}{\*\bkmkend AAAAAAAFZR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I46_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Eu){\*\bkmkstart AAAAAAAFZS}{\*\bkmkend AAAAAAAFZS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I46_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFZT}{\*\bkmkend AAAAAAAFZT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I46_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFZU}{\*\bkmkend AAAAAAAFZU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I45_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00002000u){\*\bkmkstart AAAAAAAFZV}{\*\bkmkend AAAAAAAFZV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I45_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Du){\*\bkmkstart AAAAAAAFZW}{\*\bkmkend AAAAAAAFZW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I45_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFZX}{\*\bkmkend AAAAAAAFZX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I45_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAFZY}{\*\bkmkend AAAAAAAFZY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I44_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001000u){\*\bkmkstart AAAAAAAFZZ}{\*\bkmkend AAAAAAAFZZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I44_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAAGAA}{\*\bkmkend AAAAAAAGAA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I44_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGAB}{\*\bkmkend AAAAAAAGAB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I44_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGAC}{\*\bkmkend AAAAAAAGAC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I43_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAAGAD}{\*\bkmkend AAAAAAAGAD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I43_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAAGAE}{\*\bkmkend AAAAAAAGAE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I43_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGAF}{\*\bkmkend AAAAAAAGAF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I43_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGAG}{\*\bkmkend AAAAAAAGAG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I42_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000400u){\*\bkmkstart AAAAAAAGAH}{\*\bkmkend AAAAAAAGAH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I42_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAAGAI}{\*\bkmkend AAAAAAAGAI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I42_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGAJ}{\*\bkmkend AAAAAAAGAJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I42_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGAK}{\*\bkmkend AAAAAAAGAK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I41_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000200u){\*\bkmkstart AAAAAAAGAL}{\*\bkmkend AAAAAAAGAL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I41_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAAGAM}{\*\bkmkend AAAAAAAGAM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I41_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGAN}{\*\bkmkend AAAAAAAGAN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I41_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGAO}{\*\bkmkend AAAAAAAGAO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I40_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAAGAP}{\*\bkmkend AAAAAAAGAP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I40_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAGAQ}{\*\bkmkend AAAAAAAGAQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I40_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGAR}{\*\bkmkend AAAAAAAGAR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I40_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGAS}{\*\bkmkend AAAAAAAGAS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I39_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAAGAT}{\*\bkmkend AAAAAAAGAT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I39_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAGAU}{\*\bkmkend AAAAAAAGAU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I39_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGAV}{\*\bkmkend AAAAAAAGAV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I39_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGAW}{\*\bkmkend AAAAAAAGAW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I38_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAAGAX}{\*\bkmkend AAAAAAAGAX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I38_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAAGAY}{\*\bkmkend AAAAAAAGAY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I38_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGAZ}{\*\bkmkend AAAAAAAGAZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I38_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGBA}{\*\bkmkend AAAAAAAGBA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I37_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAAGBB}{\*\bkmkend AAAAAAAGBB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I37_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAAGBC}{\*\bkmkend AAAAAAAGBC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I37_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGBD}{\*\bkmkend AAAAAAAGBD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I37_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGBE}{\*\bkmkend AAAAAAAGBE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I36_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAGBF}{\*\bkmkend AAAAAAAGBF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I36_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAGBG}{\*\bkmkend AAAAAAAGBG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I36_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGBH}{\*\bkmkend AAAAAAAGBH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I36_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGBI}{\*\bkmkend AAAAAAAGBI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I35_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAGBJ}{\*\bkmkend AAAAAAAGBJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I35_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAGBK}{\*\bkmkend AAAAAAAGBK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I35_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGBL}{\*\bkmkend AAAAAAAGBL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I35_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGBM}{\*\bkmkend AAAAAAAGBM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I34_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAGBN}{\*\bkmkend AAAAAAAGBN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I34_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAGBO}{\*\bkmkend AAAAAAAGBO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I34_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGBP}{\*\bkmkend AAAAAAAGBP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I34_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGBQ}{\*\bkmkend AAAAAAAGBQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I33_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAGBR}{\*\bkmkend AAAAAAAGBR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I33_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGBS}{\*\bkmkend AAAAAAAGBS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I33_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGBT}{\*\bkmkend AAAAAAAGBT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I33_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGBU}{\*\bkmkend AAAAAAAGBU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I32_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGBV}{\*\bkmkend AAAAAAAGBV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I32_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGBW}{\*\bkmkend AAAAAAAGBW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I32_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGBX}{\*\bkmkend AAAAAAAGBX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_I32_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGBY}{\*\bkmkend AAAAAAAGBY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I31_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x80000000u){\*\bkmkstart AAAAAAAGCA}{\*\bkmkend AAAAAAAGCA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I31_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAAGCB}{\*\bkmkend AAAAAAAGCB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I31_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGCC}{\*\bkmkend AAAAAAAGCC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I30_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x40000000u){\*\bkmkstart AAAAAAAGCD}{\*\bkmkend AAAAAAAGCD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I30_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Eu){\*\bkmkstart AAAAAAAGCE}{\*\bkmkend AAAAAAAGCE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I30_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGCF}{\*\bkmkend AAAAAAAGCF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I29_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x20000000u){\*\bkmkstart AAAAAAAGCG}{\*\bkmkend AAAAAAAGCG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I29_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Du){\*\bkmkstart AAAAAAAGCH}{\*\bkmkend AAAAAAAGCH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I29_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGCI}{\*\bkmkend AAAAAAAGCI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I28_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x10000000u){\*\bkmkstart AAAAAAAGCJ}{\*\bkmkend AAAAAAAGCJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I28_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAAGCK}{\*\bkmkend AAAAAAAGCK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I28_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGCL}{\*\bkmkend AAAAAAAGCL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I27_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x08000000u){\*\bkmkstart AAAAAAAGCM}{\*\bkmkend AAAAAAAGCM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I27_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Bu){\*\bkmkstart AAAAAAAGCN}{\*\bkmkend AAAAAAAGCN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I27_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGCO}{\*\bkmkend AAAAAAAGCO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I26_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x04000000u){\*\bkmkstart AAAAAAAGCP}{\*\bkmkend AAAAAAAGCP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I26_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Au){\*\bkmkstart AAAAAAAGCQ}{\*\bkmkend AAAAAAAGCQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I26_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGCR}{\*\bkmkend AAAAAAAGCR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I25_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x02000000u){\*\bkmkstart AAAAAAAGCS}{\*\bkmkend AAAAAAAGCS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I25_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000019u){\*\bkmkstart AAAAAAAGCT}{\*\bkmkend AAAAAAAGCT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I25_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGCU}{\*\bkmkend AAAAAAAGCU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I24_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x01000000u){\*\bkmkstart AAAAAAAGCV}{\*\bkmkend AAAAAAAGCV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I24_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAAGCW}{\*\bkmkend AAAAAAAGCW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I24_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGCX}{\*\bkmkend AAAAAAAGCX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I23_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00800000u){\*\bkmkstart AAAAAAAGCY}{\*\bkmkend AAAAAAAGCY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I23_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000017u){\*\bkmkstart AAAAAAAGCZ}{\*\bkmkend AAAAAAAGCZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I23_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGDA}{\*\bkmkend AAAAAAAGDA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I22_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAAGDB}{\*\bkmkend AAAAAAAGDB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I22_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAAGDC}{\*\bkmkend AAAAAAAGDC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I22_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGDD}{\*\bkmkend AAAAAAAGDD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I21_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00200000u){\*\bkmkstart AAAAAAAGDE}{\*\bkmkend AAAAAAAGDE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I21_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAAGDF}{\*\bkmkend AAAAAAAGDF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I21_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGDG}{\*\bkmkend AAAAAAAGDG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I20_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAAGDH}{\*\bkmkend AAAAAAAGDH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I20_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAAGDI}{\*\bkmkend AAAAAAAGDI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I20_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGDJ}{\*\bkmkend AAAAAAAGDJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I19_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00080000u){\*\bkmkstart AAAAAAAGDK}{\*\bkmkend AAAAAAAGDK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I19_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000013u){\*\bkmkstart AAAAAAAGDL}{\*\bkmkend AAAAAAAGDL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I19_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGDM}{\*\bkmkend AAAAAAAGDM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I18_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00040000u){\*\bkmkstart AAAAAAAGDN}{\*\bkmkend AAAAAAAGDN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I18_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000012u){\*\bkmkstart AAAAAAAGDO}{\*\bkmkend AAAAAAAGDO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I18_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGDP}{\*\bkmkend AAAAAAAGDP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I17_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00020000u){\*\bkmkstart AAAAAAAGDQ}{\*\bkmkend AAAAAAAGDQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I17_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000011u){\*\bkmkstart AAAAAAAGDR}{\*\bkmkend AAAAAAAGDR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I17_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGDS}{\*\bkmkend AAAAAAAGDS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I16_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAAGDT}{\*\bkmkend AAAAAAAGDT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I16_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAGDU}{\*\bkmkend AAAAAAAGDU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I16_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGDV}{\*\bkmkend AAAAAAAGDV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I15_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00008000u){\*\bkmkstart AAAAAAAGDW}{\*\bkmkend AAAAAAAGDW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I15_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAAGDX}{\*\bkmkend AAAAAAAGDX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I15_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGDY}{\*\bkmkend AAAAAAAGDY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I14_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00004000u){\*\bkmkstart AAAAAAAGDZ}{\*\bkmkend AAAAAAAGDZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I14_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Eu){\*\bkmkstart AAAAAAAGEA}{\*\bkmkend AAAAAAAGEA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I14_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGEB}{\*\bkmkend AAAAAAAGEB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I13_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00002000u){\*\bkmkstart AAAAAAAGEC}{\*\bkmkend AAAAAAAGEC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I13_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Du){\*\bkmkstart AAAAAAAGED}{\*\bkmkend AAAAAAAGED} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I13_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGEE}{\*\bkmkend AAAAAAAGEE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I12_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001000u){\*\bkmkstart AAAAAAAGEF}{\*\bkmkend AAAAAAAGEF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I12_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAAGEG}{\*\bkmkend AAAAAAAGEG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I12_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGEH}{\*\bkmkend AAAAAAAGEH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I11_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAAGEI}{\*\bkmkend AAAAAAAGEI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I11_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAAGEJ}{\*\bkmkend AAAAAAAGEJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I11_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGEK}{\*\bkmkend AAAAAAAGEK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I10_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000400u){\*\bkmkstart AAAAAAAGEL}{\*\bkmkend AAAAAAAGEL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I10_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAAGEM}{\*\bkmkend AAAAAAAGEM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I10_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGEN}{\*\bkmkend AAAAAAAGEN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I9_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000200u){\*\bkmkstart AAAAAAAGEO}{\*\bkmkend AAAAAAAGEO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I9_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAAGEP}{\*\bkmkend AAAAAAAGEP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I9_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGEQ}{\*\bkmkend AAAAAAAGEQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I8_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAAGER}{\*\bkmkend AAAAAAAGER} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I8_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAGES}{\*\bkmkend AAAAAAAGES} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I8_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGET}{\*\bkmkend AAAAAAAGET} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I7_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAAGEU}{\*\bkmkend AAAAAAAGEU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I7_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAGEV}{\*\bkmkend AAAAAAAGEV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I7_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGEW}{\*\bkmkend AAAAAAAGEW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I6_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAAGEX}{\*\bkmkend AAAAAAAGEX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I6_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAAGEY}{\*\bkmkend AAAAAAAGEY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I6_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGEZ}{\*\bkmkend AAAAAAAGEZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I5_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAAGFA}{\*\bkmkend AAAAAAAGFA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I5_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAAGFB}{\*\bkmkend AAAAAAAGFB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I5_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGFC}{\*\bkmkend AAAAAAAGFC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I4_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAGFD}{\*\bkmkend AAAAAAAGFD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I4_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAGFE}{\*\bkmkend AAAAAAAGFE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I4_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGFF}{\*\bkmkend AAAAAAAGFF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I3_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAGFG}{\*\bkmkend AAAAAAAGFG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I3_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAGFH}{\*\bkmkend AAAAAAAGFH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I3_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGFI}{\*\bkmkend AAAAAAAGFI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I2_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAGFJ}{\*\bkmkend AAAAAAAGFJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I2_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAGFK}{\*\bkmkend AAAAAAAGFK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I2_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGFL}{\*\bkmkend AAAAAAAGFL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I1_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAGFM}{\*\bkmkend AAAAAAAGFM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I1_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGFN}{\*\bkmkend AAAAAAAGFN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I1_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGFO}{\*\bkmkend AAAAAAAGFO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I0_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGFP}{\*\bkmkend AAAAAAAGFP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I0_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGFQ}{\*\bkmkend AAAAAAAGFQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_I0_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGFR}{\*\bkmkend AAAAAAAGFR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I63_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x80000000u){\*\bkmkstart AAAAAAAGFT}{\*\bkmkend AAAAAAAGFT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I63_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAAGFU}{\*\bkmkend AAAAAAAGFU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I63_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGFV}{\*\bkmkend AAAAAAAGFV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I62_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x40000000u){\*\bkmkstart AAAAAAAGFW}{\*\bkmkend AAAAAAAGFW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I62_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Eu){\*\bkmkstart AAAAAAAGFX}{\*\bkmkend AAAAAAAGFX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I62_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGFY}{\*\bkmkend AAAAAAAGFY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I61_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x20000000u){\*\bkmkstart AAAAAAAGFZ}{\*\bkmkend AAAAAAAGFZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I61_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Du){\*\bkmkstart AAAAAAAGGA}{\*\bkmkend AAAAAAAGGA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I61_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGGB}{\*\bkmkend AAAAAAAGGB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I60_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x10000000u){\*\bkmkstart AAAAAAAGGC}{\*\bkmkend AAAAAAAGGC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I60_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAAGGD}{\*\bkmkend AAAAAAAGGD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I60_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGGE}{\*\bkmkend AAAAAAAGGE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I59_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x08000000u){\*\bkmkstart AAAAAAAGGF}{\*\bkmkend AAAAAAAGGF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I59_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Bu){\*\bkmkstart AAAAAAAGGG}{\*\bkmkend AAAAAAAGGG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I59_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGGH}{\*\bkmkend AAAAAAAGGH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I58_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x04000000u){\*\bkmkstart AAAAAAAGGI}{\*\bkmkend AAAAAAAGGI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I58_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Au){\*\bkmkstart AAAAAAAGGJ}{\*\bkmkend AAAAAAAGGJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I58_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGGK}{\*\bkmkend AAAAAAAGGK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I57_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x02000000u){\*\bkmkstart AAAAAAAGGL}{\*\bkmkend AAAAAAAGGL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I57_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000019u){\*\bkmkstart AAAAAAAGGM}{\*\bkmkend AAAAAAAGGM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I57_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGGN}{\*\bkmkend AAAAAAAGGN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I56_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x01000000u){\*\bkmkstart AAAAAAAGGO}{\*\bkmkend AAAAAAAGGO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I56_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAAGGP}{\*\bkmkend AAAAAAAGGP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I56_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGGQ}{\*\bkmkend AAAAAAAGGQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I55_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00800000u){\*\bkmkstart AAAAAAAGGR}{\*\bkmkend AAAAAAAGGR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I55_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000017u){\*\bkmkstart AAAAAAAGGS}{\*\bkmkend AAAAAAAGGS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I55_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGGT}{\*\bkmkend AAAAAAAGGT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I54_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAAGGU}{\*\bkmkend AAAAAAAGGU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I54_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAAGGV}{\*\bkmkend AAAAAAAGGV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I54_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGGW}{\*\bkmkend AAAAAAAGGW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I53_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00200000u){\*\bkmkstart AAAAAAAGGX}{\*\bkmkend AAAAAAAGGX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I53_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAAGGY}{\*\bkmkend AAAAAAAGGY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I53_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGGZ}{\*\bkmkend AAAAAAAGGZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I52_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAAGHA}{\*\bkmkend AAAAAAAGHA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I52_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAAGHB}{\*\bkmkend AAAAAAAGHB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I52_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGHC}{\*\bkmkend AAAAAAAGHC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I51_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00080000u){\*\bkmkstart AAAAAAAGHD}{\*\bkmkend AAAAAAAGHD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I51_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000013u){\*\bkmkstart AAAAAAAGHE}{\*\bkmkend AAAAAAAGHE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I51_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGHF}{\*\bkmkend AAAAAAAGHF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I50_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00040000u){\*\bkmkstart AAAAAAAGHG}{\*\bkmkend AAAAAAAGHG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I50_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000012u){\*\bkmkstart AAAAAAAGHH}{\*\bkmkend AAAAAAAGHH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I50_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGHI}{\*\bkmkend AAAAAAAGHI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I49_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00020000u){\*\bkmkstart AAAAAAAGHJ}{\*\bkmkend AAAAAAAGHJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I49_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000011u){\*\bkmkstart AAAAAAAGHK}{\*\bkmkend AAAAAAAGHK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I49_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGHL}{\*\bkmkend AAAAAAAGHL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I48_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAAGHM}{\*\bkmkend AAAAAAAGHM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I48_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAGHN}{\*\bkmkend AAAAAAAGHN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I48_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGHO}{\*\bkmkend AAAAAAAGHO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I47_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00008000u){\*\bkmkstart AAAAAAAGHP}{\*\bkmkend AAAAAAAGHP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I47_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAAGHQ}{\*\bkmkend AAAAAAAGHQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I47_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGHR}{\*\bkmkend AAAAAAAGHR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I46_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00004000u){\*\bkmkstart AAAAAAAGHS}{\*\bkmkend AAAAAAAGHS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I46_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Eu){\*\bkmkstart AAAAAAAGHT}{\*\bkmkend AAAAAAAGHT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I46_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGHU}{\*\bkmkend AAAAAAAGHU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I45_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00002000u){\*\bkmkstart AAAAAAAGHV}{\*\bkmkend AAAAAAAGHV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I45_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Du){\*\bkmkstart AAAAAAAGHW}{\*\bkmkend AAAAAAAGHW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I45_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGHX}{\*\bkmkend AAAAAAAGHX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I44_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001000u){\*\bkmkstart AAAAAAAGHY}{\*\bkmkend AAAAAAAGHY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I44_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAAGHZ}{\*\bkmkend AAAAAAAGHZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I44_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGIA}{\*\bkmkend AAAAAAAGIA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I43_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAAGIB}{\*\bkmkend AAAAAAAGIB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I43_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAAGIC}{\*\bkmkend AAAAAAAGIC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I43_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGID}{\*\bkmkend AAAAAAAGID} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I42_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000400u){\*\bkmkstart AAAAAAAGIE}{\*\bkmkend AAAAAAAGIE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I42_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAAGIF}{\*\bkmkend AAAAAAAGIF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I42_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGIG}{\*\bkmkend AAAAAAAGIG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I41_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000200u){\*\bkmkstart AAAAAAAGIH}{\*\bkmkend AAAAAAAGIH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I41_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAAGII}{\*\bkmkend AAAAAAAGII} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I41_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGIJ}{\*\bkmkend AAAAAAAGIJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I40_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAAGIK}{\*\bkmkend AAAAAAAGIK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I40_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAGIL}{\*\bkmkend AAAAAAAGIL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I40_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGIM}{\*\bkmkend AAAAAAAGIM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I39_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAAGIN}{\*\bkmkend AAAAAAAGIN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I39_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAGIO}{\*\bkmkend AAAAAAAGIO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I39_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGIP}{\*\bkmkend AAAAAAAGIP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I38_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAAGIQ}{\*\bkmkend AAAAAAAGIQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I38_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAAGIR}{\*\bkmkend AAAAAAAGIR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I38_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGIS}{\*\bkmkend AAAAAAAGIS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I37_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAAGIT}{\*\bkmkend AAAAAAAGIT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I37_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAAGIU}{\*\bkmkend AAAAAAAGIU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I37_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGIV}{\*\bkmkend AAAAAAAGIV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I36_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAGIW}{\*\bkmkend AAAAAAAGIW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I36_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAGIX}{\*\bkmkend AAAAAAAGIX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I36_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGIY}{\*\bkmkend AAAAAAAGIY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I35_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAGIZ}{\*\bkmkend AAAAAAAGIZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I35_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAGJA}{\*\bkmkend AAAAAAAGJA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I35_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGJB}{\*\bkmkend AAAAAAAGJB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I34_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAGJC}{\*\bkmkend AAAAAAAGJC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I34_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAGJD}{\*\bkmkend AAAAAAAGJD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I34_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGJE}{\*\bkmkend AAAAAAAGJE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I33_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAGJF}{\*\bkmkend AAAAAAAGJF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I33_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGJG}{\*\bkmkend AAAAAAAGJG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I33_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGJH}{\*\bkmkend AAAAAAAGJH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I32_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGJI}{\*\bkmkend AAAAAAAGJI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I32_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGJJ}{\*\bkmkend AAAAAAAGJJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_I32_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGJK}{\*\bkmkend AAAAAAAGJK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I31_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x80000000u){\*\bkmkstart AAAAAAAGJM}{\*\bkmkend AAAAAAAGJM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I31_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAAGJN}{\*\bkmkend AAAAAAAGJN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I31_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGJO}{\*\bkmkend AAAAAAAGJO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I31_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGJP}{\*\bkmkend AAAAAAAGJP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I30_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x40000000u){\*\bkmkstart AAAAAAAGJQ}{\*\bkmkend AAAAAAAGJQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I30_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Eu){\*\bkmkstart AAAAAAAGJR}{\*\bkmkend AAAAAAAGJR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I30_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGJS}{\*\bkmkend AAAAAAAGJS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I30_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGJT}{\*\bkmkend AAAAAAAGJT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I29_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x20000000u){\*\bkmkstart AAAAAAAGJU}{\*\bkmkend AAAAAAAGJU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I29_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Du){\*\bkmkstart AAAAAAAGJV}{\*\bkmkend AAAAAAAGJV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I29_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGJW}{\*\bkmkend AAAAAAAGJW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I29_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGJX}{\*\bkmkend AAAAAAAGJX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I28_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x10000000u){\*\bkmkstart AAAAAAAGJY}{\*\bkmkend AAAAAAAGJY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I28_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAAGJZ}{\*\bkmkend AAAAAAAGJZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I28_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGKA}{\*\bkmkend AAAAAAAGKA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I28_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGKB}{\*\bkmkend AAAAAAAGKB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I27_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x08000000u){\*\bkmkstart AAAAAAAGKC}{\*\bkmkend AAAAAAAGKC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I27_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Bu){\*\bkmkstart AAAAAAAGKD}{\*\bkmkend AAAAAAAGKD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I27_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGKE}{\*\bkmkend AAAAAAAGKE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I27_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGKF}{\*\bkmkend AAAAAAAGKF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I26_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x04000000u){\*\bkmkstart AAAAAAAGKG}{\*\bkmkend AAAAAAAGKG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I26_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Au){\*\bkmkstart AAAAAAAGKH}{\*\bkmkend AAAAAAAGKH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I26_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGKI}{\*\bkmkend AAAAAAAGKI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I26_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGKJ}{\*\bkmkend AAAAAAAGKJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I25_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x02000000u){\*\bkmkstart AAAAAAAGKK}{\*\bkmkend AAAAAAAGKK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I25_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000019u){\*\bkmkstart AAAAAAAGKL}{\*\bkmkend AAAAAAAGKL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I25_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGKM}{\*\bkmkend AAAAAAAGKM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I25_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGKN}{\*\bkmkend AAAAAAAGKN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I24_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x01000000u){\*\bkmkstart AAAAAAAGKO}{\*\bkmkend AAAAAAAGKO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I24_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAAGKP}{\*\bkmkend AAAAAAAGKP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I24_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGKQ}{\*\bkmkend AAAAAAAGKQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I24_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGKR}{\*\bkmkend AAAAAAAGKR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I23_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00800000u){\*\bkmkstart AAAAAAAGKS}{\*\bkmkend AAAAAAAGKS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I23_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000017u){\*\bkmkstart AAAAAAAGKT}{\*\bkmkend AAAAAAAGKT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I23_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGKU}{\*\bkmkend AAAAAAAGKU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I23_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGKV}{\*\bkmkend AAAAAAAGKV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I22_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAAGKW}{\*\bkmkend AAAAAAAGKW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I22_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAAGKX}{\*\bkmkend AAAAAAAGKX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I22_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGKY}{\*\bkmkend AAAAAAAGKY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I22_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGKZ}{\*\bkmkend AAAAAAAGKZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I21_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00200000u){\*\bkmkstart AAAAAAAGLA}{\*\bkmkend AAAAAAAGLA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I21_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAAGLB}{\*\bkmkend AAAAAAAGLB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I21_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGLC}{\*\bkmkend AAAAAAAGLC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I21_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGLD}{\*\bkmkend AAAAAAAGLD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I20_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAAGLE}{\*\bkmkend AAAAAAAGLE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I20_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAAGLF}{\*\bkmkend AAAAAAAGLF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I20_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGLG}{\*\bkmkend AAAAAAAGLG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I20_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGLH}{\*\bkmkend AAAAAAAGLH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I19_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00080000u){\*\bkmkstart AAAAAAAGLI}{\*\bkmkend AAAAAAAGLI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I19_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000013u){\*\bkmkstart AAAAAAAGLJ}{\*\bkmkend AAAAAAAGLJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I19_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGLK}{\*\bkmkend AAAAAAAGLK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I19_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGLL}{\*\bkmkend AAAAAAAGLL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I18_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00040000u){\*\bkmkstart AAAAAAAGLM}{\*\bkmkend AAAAAAAGLM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I18_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000012u){\*\bkmkstart AAAAAAAGLN}{\*\bkmkend AAAAAAAGLN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I18_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGLO}{\*\bkmkend AAAAAAAGLO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I18_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGLP}{\*\bkmkend AAAAAAAGLP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I17_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00020000u){\*\bkmkstart AAAAAAAGLQ}{\*\bkmkend AAAAAAAGLQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I17_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000011u){\*\bkmkstart AAAAAAAGLR}{\*\bkmkend AAAAAAAGLR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I17_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGLS}{\*\bkmkend AAAAAAAGLS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I17_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGLT}{\*\bkmkend AAAAAAAGLT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I16_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAAGLU}{\*\bkmkend AAAAAAAGLU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I16_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAGLV}{\*\bkmkend AAAAAAAGLV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I16_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGLW}{\*\bkmkend AAAAAAAGLW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I16_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGLX}{\*\bkmkend AAAAAAAGLX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I15_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00008000u){\*\bkmkstart AAAAAAAGLY}{\*\bkmkend AAAAAAAGLY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I15_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAAGLZ}{\*\bkmkend AAAAAAAGLZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I15_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGMA}{\*\bkmkend AAAAAAAGMA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I15_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGMB}{\*\bkmkend AAAAAAAGMB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I14_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00004000u){\*\bkmkstart AAAAAAAGMC}{\*\bkmkend AAAAAAAGMC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I14_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Eu){\*\bkmkstart AAAAAAAGMD}{\*\bkmkend AAAAAAAGMD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I14_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGME}{\*\bkmkend AAAAAAAGME} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I14_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGMF}{\*\bkmkend AAAAAAAGMF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I13_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00002000u){\*\bkmkstart AAAAAAAGMG}{\*\bkmkend AAAAAAAGMG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I13_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Du){\*\bkmkstart AAAAAAAGMH}{\*\bkmkend AAAAAAAGMH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I13_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGMI}{\*\bkmkend AAAAAAAGMI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I13_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGMJ}{\*\bkmkend AAAAAAAGMJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I12_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001000u){\*\bkmkstart AAAAAAAGMK}{\*\bkmkend AAAAAAAGMK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I12_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAAGML}{\*\bkmkend AAAAAAAGML} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I12_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGMM}{\*\bkmkend AAAAAAAGMM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I12_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGMN}{\*\bkmkend AAAAAAAGMN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I11_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAAGMO}{\*\bkmkend AAAAAAAGMO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I11_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAAGMP}{\*\bkmkend AAAAAAAGMP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I11_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGMQ}{\*\bkmkend AAAAAAAGMQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I11_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGMR}{\*\bkmkend AAAAAAAGMR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I10_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000400u){\*\bkmkstart AAAAAAAGMS}{\*\bkmkend AAAAAAAGMS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I10_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAAGMT}{\*\bkmkend AAAAAAAGMT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I10_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGMU}{\*\bkmkend AAAAAAAGMU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I10_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGMV}{\*\bkmkend AAAAAAAGMV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I9_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000200u){\*\bkmkstart AAAAAAAGMW}{\*\bkmkend AAAAAAAGMW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I9_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAAGMX}{\*\bkmkend AAAAAAAGMX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I9_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGMY}{\*\bkmkend AAAAAAAGMY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I9_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGMZ}{\*\bkmkend AAAAAAAGMZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I8_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAAGNA}{\*\bkmkend AAAAAAAGNA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I8_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAGNB}{\*\bkmkend AAAAAAAGNB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I8_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGNC}{\*\bkmkend AAAAAAAGNC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I8_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGND}{\*\bkmkend AAAAAAAGND} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I7_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAAGNE}{\*\bkmkend AAAAAAAGNE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I7_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAGNF}{\*\bkmkend AAAAAAAGNF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I7_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGNG}{\*\bkmkend AAAAAAAGNG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I7_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGNH}{\*\bkmkend AAAAAAAGNH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I6_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAAGNI}{\*\bkmkend AAAAAAAGNI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I6_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAAGNJ}{\*\bkmkend AAAAAAAGNJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I6_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGNK}{\*\bkmkend AAAAAAAGNK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I6_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGNL}{\*\bkmkend AAAAAAAGNL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I5_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAAGNM}{\*\bkmkend AAAAAAAGNM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I5_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAAGNN}{\*\bkmkend AAAAAAAGNN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I5_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGNO}{\*\bkmkend AAAAAAAGNO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I5_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGNP}{\*\bkmkend AAAAAAAGNP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I4_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAGNQ}{\*\bkmkend AAAAAAAGNQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I4_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAGNR}{\*\bkmkend AAAAAAAGNR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I4_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGNS}{\*\bkmkend AAAAAAAGNS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I4_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGNT}{\*\bkmkend AAAAAAAGNT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I3_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAGNU}{\*\bkmkend AAAAAAAGNU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I3_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAGNV}{\*\bkmkend AAAAAAAGNV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I3_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGNW}{\*\bkmkend AAAAAAAGNW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I3_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGNX}{\*\bkmkend AAAAAAAGNX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I2_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAGNY}{\*\bkmkend AAAAAAAGNY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I2_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAGNZ}{\*\bkmkend AAAAAAAGNZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I2_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGOA}{\*\bkmkend AAAAAAAGOA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I2_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGOB}{\*\bkmkend AAAAAAAGOB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I1_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAGOC}{\*\bkmkend AAAAAAAGOC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I1_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGOD}{\*\bkmkend AAAAAAAGOD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I1_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGOE}{\*\bkmkend AAAAAAAGOE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I1_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGOF}{\*\bkmkend AAAAAAAGOF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I0_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGOG}{\*\bkmkend AAAAAAAGOG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I0_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGOH}{\*\bkmkend AAAAAAAGOH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I0_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGOI}{\*\bkmkend AAAAAAAGOI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_I0_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGOJ}{\*\bkmkend AAAAAAAGOJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I63_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x80000000u){\*\bkmkstart AAAAAAAGOL}{\*\bkmkend AAAAAAAGOL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I63_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAAGOM}{\*\bkmkend AAAAAAAGOM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I63_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGON}{\*\bkmkend AAAAAAAGON} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I63_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGOO}{\*\bkmkend AAAAAAAGOO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I62_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x40000000u){\*\bkmkstart AAAAAAAGOP}{\*\bkmkend AAAAAAAGOP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I62_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Eu){\*\bkmkstart AAAAAAAGOQ}{\*\bkmkend AAAAAAAGOQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I62_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGOR}{\*\bkmkend AAAAAAAGOR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I62_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGOS}{\*\bkmkend AAAAAAAGOS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I61_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x20000000u){\*\bkmkstart AAAAAAAGOT}{\*\bkmkend AAAAAAAGOT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I61_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Du){\*\bkmkstart AAAAAAAGOU}{\*\bkmkend AAAAAAAGOU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I61_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGOV}{\*\bkmkend AAAAAAAGOV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I61_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGOW}{\*\bkmkend AAAAAAAGOW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I60_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x10000000u){\*\bkmkstart AAAAAAAGOX}{\*\bkmkend AAAAAAAGOX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I60_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Cu){\*\bkmkstart AAAAAAAGOY}{\*\bkmkend AAAAAAAGOY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I60_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGOZ}{\*\bkmkend AAAAAAAGOZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I60_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGPA}{\*\bkmkend AAAAAAAGPA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I59_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x08000000u){\*\bkmkstart AAAAAAAGPB}{\*\bkmkend AAAAAAAGPB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I59_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Bu){\*\bkmkstart AAAAAAAGPC}{\*\bkmkend AAAAAAAGPC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I59_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGPD}{\*\bkmkend AAAAAAAGPD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I59_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGPE}{\*\bkmkend AAAAAAAGPE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I58_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x04000000u){\*\bkmkstart AAAAAAAGPF}{\*\bkmkend AAAAAAAGPF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I58_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Au){\*\bkmkstart AAAAAAAGPG}{\*\bkmkend AAAAAAAGPG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I58_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGPH}{\*\bkmkend AAAAAAAGPH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I58_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGPI}{\*\bkmkend AAAAAAAGPI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I57_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x02000000u){\*\bkmkstart AAAAAAAGPJ}{\*\bkmkend AAAAAAAGPJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I57_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000019u){\*\bkmkstart AAAAAAAGPK}{\*\bkmkend AAAAAAAGPK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I57_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGPL}{\*\bkmkend AAAAAAAGPL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I57_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGPM}{\*\bkmkend AAAAAAAGPM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I56_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x01000000u){\*\bkmkstart AAAAAAAGPN}{\*\bkmkend AAAAAAAGPN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I56_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAAGPO}{\*\bkmkend AAAAAAAGPO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I56_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGPP}{\*\bkmkend AAAAAAAGPP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I56_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGPQ}{\*\bkmkend AAAAAAAGPQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I55_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00800000u){\*\bkmkstart AAAAAAAGPR}{\*\bkmkend AAAAAAAGPR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I55_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000017u){\*\bkmkstart AAAAAAAGPS}{\*\bkmkend AAAAAAAGPS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I55_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGPT}{\*\bkmkend AAAAAAAGPT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I55_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGPU}{\*\bkmkend AAAAAAAGPU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I54_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAAGPV}{\*\bkmkend AAAAAAAGPV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I54_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAAGPW}{\*\bkmkend AAAAAAAGPW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I54_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGPX}{\*\bkmkend AAAAAAAGPX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I54_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGPY}{\*\bkmkend AAAAAAAGPY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I53_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00200000u){\*\bkmkstart AAAAAAAGPZ}{\*\bkmkend AAAAAAAGPZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I53_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAAGQA}{\*\bkmkend AAAAAAAGQA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I53_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGQB}{\*\bkmkend AAAAAAAGQB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I53_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGQC}{\*\bkmkend AAAAAAAGQC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I52_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAAGQD}{\*\bkmkend AAAAAAAGQD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I52_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAAGQE}{\*\bkmkend AAAAAAAGQE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I52_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGQF}{\*\bkmkend AAAAAAAGQF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I52_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGQG}{\*\bkmkend AAAAAAAGQG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I51_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00080000u){\*\bkmkstart AAAAAAAGQH}{\*\bkmkend AAAAAAAGQH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I51_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000013u){\*\bkmkstart AAAAAAAGQI}{\*\bkmkend AAAAAAAGQI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I51_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGQJ}{\*\bkmkend AAAAAAAGQJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I51_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGQK}{\*\bkmkend AAAAAAAGQK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I50_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00040000u){\*\bkmkstart AAAAAAAGQL}{\*\bkmkend AAAAAAAGQL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I50_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000012u){\*\bkmkstart AAAAAAAGQM}{\*\bkmkend AAAAAAAGQM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I50_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGQN}{\*\bkmkend AAAAAAAGQN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I50_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGQO}{\*\bkmkend AAAAAAAGQO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I49_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00020000u){\*\bkmkstart AAAAAAAGQP}{\*\bkmkend AAAAAAAGQP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I49_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000011u){\*\bkmkstart AAAAAAAGQQ}{\*\bkmkend AAAAAAAGQQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I49_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGQR}{\*\bkmkend AAAAAAAGQR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I49_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGQS}{\*\bkmkend AAAAAAAGQS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I48_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAAGQT}{\*\bkmkend AAAAAAAGQT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I48_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAGQU}{\*\bkmkend AAAAAAAGQU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I48_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGQV}{\*\bkmkend AAAAAAAGQV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I48_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGQW}{\*\bkmkend AAAAAAAGQW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I47_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00008000u){\*\bkmkstart AAAAAAAGQX}{\*\bkmkend AAAAAAAGQX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I47_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAAGQY}{\*\bkmkend AAAAAAAGQY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I47_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGQZ}{\*\bkmkend AAAAAAAGQZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I47_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGRA}{\*\bkmkend AAAAAAAGRA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I46_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00004000u){\*\bkmkstart AAAAAAAGRB}{\*\bkmkend AAAAAAAGRB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I46_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Eu){\*\bkmkstart AAAAAAAGRC}{\*\bkmkend AAAAAAAGRC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I46_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGRD}{\*\bkmkend AAAAAAAGRD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I46_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGRE}{\*\bkmkend AAAAAAAGRE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I45_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00002000u){\*\bkmkstart AAAAAAAGRF}{\*\bkmkend AAAAAAAGRF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I45_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Du){\*\bkmkstart AAAAAAAGRG}{\*\bkmkend AAAAAAAGRG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I45_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGRH}{\*\bkmkend AAAAAAAGRH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I45_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGRI}{\*\bkmkend AAAAAAAGRI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I44_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00001000u){\*\bkmkstart AAAAAAAGRJ}{\*\bkmkend AAAAAAAGRJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I44_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAAGRK}{\*\bkmkend AAAAAAAGRK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I44_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGRL}{\*\bkmkend AAAAAAAGRL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I44_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGRM}{\*\bkmkend AAAAAAAGRM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I43_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAAGRN}{\*\bkmkend AAAAAAAGRN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I43_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAAGRO}{\*\bkmkend AAAAAAAGRO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I43_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGRP}{\*\bkmkend AAAAAAAGRP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I43_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGRQ}{\*\bkmkend AAAAAAAGRQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I42_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000400u){\*\bkmkstart AAAAAAAGRR}{\*\bkmkend AAAAAAAGRR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I42_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAAGRS}{\*\bkmkend AAAAAAAGRS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I42_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGRT}{\*\bkmkend AAAAAAAGRT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I42_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGRU}{\*\bkmkend AAAAAAAGRU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I41_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000200u){\*\bkmkstart AAAAAAAGRV}{\*\bkmkend AAAAAAAGRV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I41_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAAGRW}{\*\bkmkend AAAAAAAGRW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I41_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGRX}{\*\bkmkend AAAAAAAGRX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I41_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGRY}{\*\bkmkend AAAAAAAGRY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I40_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAAGRZ}{\*\bkmkend AAAAAAAGRZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I40_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAGSA}{\*\bkmkend AAAAAAAGSA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I40_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGSB}{\*\bkmkend AAAAAAAGSB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I40_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGSC}{\*\bkmkend AAAAAAAGSC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I39_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAAGSD}{\*\bkmkend AAAAAAAGSD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I39_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAGSE}{\*\bkmkend AAAAAAAGSE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I39_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGSF}{\*\bkmkend AAAAAAAGSF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I39_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGSG}{\*\bkmkend AAAAAAAGSG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I38_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAAGSH}{\*\bkmkend AAAAAAAGSH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I38_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAAGSI}{\*\bkmkend AAAAAAAGSI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I38_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGSJ}{\*\bkmkend AAAAAAAGSJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I38_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGSK}{\*\bkmkend AAAAAAAGSK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I37_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAAGSL}{\*\bkmkend AAAAAAAGSL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I37_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAAGSM}{\*\bkmkend AAAAAAAGSM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I37_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGSN}{\*\bkmkend AAAAAAAGSN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I37_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGSO}{\*\bkmkend AAAAAAAGSO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I36_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAGSP}{\*\bkmkend AAAAAAAGSP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I36_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAGSQ}{\*\bkmkend AAAAAAAGSQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I36_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGSR}{\*\bkmkend AAAAAAAGSR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I36_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGSS}{\*\bkmkend AAAAAAAGSS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I35_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAGST}{\*\bkmkend AAAAAAAGST} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I35_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAGSU}{\*\bkmkend AAAAAAAGSU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I35_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGSV}{\*\bkmkend AAAAAAAGSV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I35_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGSW}{\*\bkmkend AAAAAAAGSW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I34_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAGSX}{\*\bkmkend AAAAAAAGSX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I34_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAGSY}{\*\bkmkend AAAAAAAGSY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I34_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGSZ}{\*\bkmkend AAAAAAAGSZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I34_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGTA}{\*\bkmkend AAAAAAAGTA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I33_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAGTB}{\*\bkmkend AAAAAAAGTB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I33_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGTC}{\*\bkmkend AAAAAAAGTC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I33_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGTD}{\*\bkmkend AAAAAAAGTD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I33_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGTE}{\*\bkmkend AAAAAAAGTE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I32_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGTF}{\*\bkmkend AAAAAAAGTF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I32_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGTG}{\*\bkmkend AAAAAAAGTG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I32_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGTH}{\*\bkmkend AAAAAAAGTH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_I32_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGTI}{\*\bkmkend AAAAAAAGTI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IEVAL_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAGTK}{\*\bkmkend AAAAAAAGTK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IEVAL_SET_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGTL}{\*\bkmkend AAAAAAAGTL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IEVAL_SET_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGTM}{\*\bkmkend AAAAAAAGTM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IEVAL_SET_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGTN}{\*\bkmkend AAAAAAAGTN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IEVAL_EVAL_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGTO}{\*\bkmkend AAAAAAAGTO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IEVAL_EVAL_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGTP}{\*\bkmkend AAAAAAAGTP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IEVAL_EVAL_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGTQ}{\*\bkmkend AAAAAAAGTQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IEVAL_EVAL_EVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGTR}{\*\bkmkend AAAAAAAGTR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IEVAL_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QER_E7_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAAGTT}{\*\bkmkend AAAAAAAGTT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QER_E7_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAGTU}{\*\bkmkend AAAAAAAGTU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QER_E7_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGTV}{\*\bkmkend AAAAAAAGTV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QER_E6_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAAGTW}{\*\bkmkend AAAAAAAGTW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QER_E6_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAAGTX}{\*\bkmkend AAAAAAAGTX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QER_E6_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGTY}{\*\bkmkend AAAAAAAGTY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QER_E5_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAAGTZ}{\*\bkmkend AAAAAAAGTZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QER_E5_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAAGUA}{\*\bkmkend AAAAAAAGUA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QER_E5_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGUB}{\*\bkmkend AAAAAAAGUB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QER_E4_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAGUC}{\*\bkmkend AAAAAAAGUC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QER_E4_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAGUD}{\*\bkmkend AAAAAAAGUD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QER_E4_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGUE}{\*\bkmkend AAAAAAAGUE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QER_E3_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAGUF}{\*\bkmkend AAAAAAAGUF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QER_E3_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAGUG}{\*\bkmkend AAAAAAAGUG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QER_E3_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGUH}{\*\bkmkend AAAAAAAGUH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QER_E2_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAGUI}{\*\bkmkend AAAAAAAGUI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QER_E2_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAGUJ}{\*\bkmkend AAAAAAAGUJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QER_E2_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGUK}{\*\bkmkend AAAAAAAGUK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QER_E1_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAGUL}{\*\bkmkend AAAAAAAGUL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QER_E1_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGUM}{\*\bkmkend AAAAAAAGUM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QER_E1_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGUN}{\*\bkmkend AAAAAAAGUN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QER_E0_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGUO}{\*\bkmkend AAAAAAAGUO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QER_E0_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGUP}{\*\bkmkend AAAAAAAGUP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QER_E0_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGUQ}{\*\bkmkend AAAAAAAGUQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QER_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEER_E7_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAAGUS}{\*\bkmkend AAAAAAAGUS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEER_E7_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAGUT}{\*\bkmkend AAAAAAAGUT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEER_E7_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGUU}{\*\bkmkend AAAAAAAGUU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEER_E6_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAAGUV}{\*\bkmkend AAAAAAAGUV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEER_E6_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAAGUW}{\*\bkmkend AAAAAAAGUW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEER_E6_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGUX}{\*\bkmkend AAAAAAAGUX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEER_E5_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAAGUY}{\*\bkmkend AAAAAAAGUY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEER_E5_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAAGUZ}{\*\bkmkend AAAAAAAGUZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEER_E5_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGVA}{\*\bkmkend AAAAAAAGVA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEER_E4_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAGVB}{\*\bkmkend AAAAAAAGVB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEER_E4_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAGVC}{\*\bkmkend AAAAAAAGVC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEER_E4_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGVD}{\*\bkmkend AAAAAAAGVD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEER_E3_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAGVE}{\*\bkmkend AAAAAAAGVE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEER_E3_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAGVF}{\*\bkmkend AAAAAAAGVF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEER_E3_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGVG}{\*\bkmkend AAAAAAAGVG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEER_E2_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAGVH}{\*\bkmkend AAAAAAAGVH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEER_E2_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAGVI}{\*\bkmkend AAAAAAAGVI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEER_E2_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGVJ}{\*\bkmkend AAAAAAAGVJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEER_E1_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAGVK}{\*\bkmkend AAAAAAAGVK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEER_E1_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGVL}{\*\bkmkend AAAAAAAGVL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEER_E1_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGVM}{\*\bkmkend AAAAAAAGVM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEER_E0_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGVN}{\*\bkmkend AAAAAAAGVN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEER_E0_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGVO}{\*\bkmkend AAAAAAAGVO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEER_E0_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGVP}{\*\bkmkend AAAAAAAGVP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEER_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_E7_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAAGVR}{\*\bkmkend AAAAAAAGVR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_E7_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAGVS}{\*\bkmkend AAAAAAAGVS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_E7_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGVT}{\*\bkmkend AAAAAAAGVT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_E7_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGVU}{\*\bkmkend AAAAAAAGVU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_E6_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAAGVV}{\*\bkmkend AAAAAAAGVV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_E6_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAAGVW}{\*\bkmkend AAAAAAAGVW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_E6_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGVX}{\*\bkmkend AAAAAAAGVX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_E6_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGVY}{\*\bkmkend AAAAAAAGVY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_E5_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAAGVZ}{\*\bkmkend AAAAAAAGVZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_E5_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAAGWA}{\*\bkmkend AAAAAAAGWA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_E5_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGWB}{\*\bkmkend AAAAAAAGWB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_E5_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGWC}{\*\bkmkend AAAAAAAGWC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_E4_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAGWD}{\*\bkmkend AAAAAAAGWD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_E4_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAGWE}{\*\bkmkend AAAAAAAGWE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_E4_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGWF}{\*\bkmkend AAAAAAAGWF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_E4_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGWG}{\*\bkmkend AAAAAAAGWG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_E3_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAGWH}{\*\bkmkend AAAAAAAGWH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_E3_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAGWI}{\*\bkmkend AAAAAAAGWI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_E3_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGWJ}{\*\bkmkend AAAAAAAGWJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_E3_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGWK}{\*\bkmkend AAAAAAAGWK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_E2_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAGWL}{\*\bkmkend AAAAAAAGWL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_E2_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAGWM}{\*\bkmkend AAAAAAAGWM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_E2_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGWN}{\*\bkmkend AAAAAAAGWN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_E2_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGWO}{\*\bkmkend AAAAAAAGWO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_E1_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAGWP}{\*\bkmkend AAAAAAAGWP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_E1_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGWQ}{\*\bkmkend AAAAAAAGWQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_E1_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGWR}{\*\bkmkend AAAAAAAGWR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_E1_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGWS}{\*\bkmkend AAAAAAAGWS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_E0_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGWT}{\*\bkmkend AAAAAAAGWT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_E0_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGWU}{\*\bkmkend AAAAAAAGWU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_E0_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGWV}{\*\bkmkend AAAAAAAGWV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_E0_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGWW}{\*\bkmkend AAAAAAAGWW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_E7_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAAGWY}{\*\bkmkend AAAAAAAGWY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_E7_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAGWZ}{\*\bkmkend AAAAAAAGWZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_E7_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGXA}{\*\bkmkend AAAAAAAGXA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_E7_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGXB}{\*\bkmkend AAAAAAAGXB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_E6_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAAGXC}{\*\bkmkend AAAAAAAGXC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_E6_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAAGXD}{\*\bkmkend AAAAAAAGXD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_E6_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGXE}{\*\bkmkend AAAAAAAGXE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_E6_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGXF}{\*\bkmkend AAAAAAAGXF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_E5_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAAGXG}{\*\bkmkend AAAAAAAGXG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_E5_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAAGXH}{\*\bkmkend AAAAAAAGXH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_E5_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGXI}{\*\bkmkend AAAAAAAGXI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_E5_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGXJ}{\*\bkmkend AAAAAAAGXJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_E4_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAGXK}{\*\bkmkend AAAAAAAGXK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_E4_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAGXL}{\*\bkmkend AAAAAAAGXL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_E4_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGXM}{\*\bkmkend AAAAAAAGXM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_E4_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGXN}{\*\bkmkend AAAAAAAGXN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_E3_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAGXO}{\*\bkmkend AAAAAAAGXO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_E3_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAGXP}{\*\bkmkend AAAAAAAGXP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_E3_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGXQ}{\*\bkmkend AAAAAAAGXQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_E3_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGXR}{\*\bkmkend AAAAAAAGXR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_E2_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAGXS}{\*\bkmkend AAAAAAAGXS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_E2_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAGXT}{\*\bkmkend AAAAAAAGXT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_E2_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGXU}{\*\bkmkend AAAAAAAGXU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_E2_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGXV}{\*\bkmkend AAAAAAAGXV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_E1_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAGXW}{\*\bkmkend AAAAAAAGXW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_E1_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGXX}{\*\bkmkend AAAAAAAGXX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_E1_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGXY}{\*\bkmkend AAAAAAAGXY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_E1_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGXZ}{\*\bkmkend AAAAAAAGXZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_E0_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGYA}{\*\bkmkend AAAAAAAGYA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_E0_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGYB}{\*\bkmkend AAAAAAAGYB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_E0_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGYC}{\*\bkmkend AAAAAAAGYC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_E0_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGYD}{\*\bkmkend AAAAAAAGYD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSER_E7_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAAGYF}{\*\bkmkend AAAAAAAGYF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSER_E7_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAGYG}{\*\bkmkend AAAAAAAGYG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSER_E7_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGYH}{\*\bkmkend AAAAAAAGYH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSER_E6_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAAGYI}{\*\bkmkend AAAAAAAGYI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSER_E6_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAAGYJ}{\*\bkmkend AAAAAAAGYJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSER_E6_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGYK}{\*\bkmkend AAAAAAAGYK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSER_E5_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAAGYL}{\*\bkmkend AAAAAAAGYL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSER_E5_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAAGYM}{\*\bkmkend AAAAAAAGYM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSER_E5_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGYN}{\*\bkmkend AAAAAAAGYN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSER_E4_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAGYO}{\*\bkmkend AAAAAAAGYO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSER_E4_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAGYP}{\*\bkmkend AAAAAAAGYP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSER_E4_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGYQ}{\*\bkmkend AAAAAAAGYQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSER_E3_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAGYR}{\*\bkmkend AAAAAAAGYR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSER_E3_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAGYS}{\*\bkmkend AAAAAAAGYS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSER_E3_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGYT}{\*\bkmkend AAAAAAAGYT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSER_E2_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAGYU}{\*\bkmkend AAAAAAAGYU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSER_E2_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAGYV}{\*\bkmkend AAAAAAAGYV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSER_E2_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGYW}{\*\bkmkend AAAAAAAGYW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSER_E1_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAGYX}{\*\bkmkend AAAAAAAGYX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSER_E1_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGYY}{\*\bkmkend AAAAAAAGYY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSER_E1_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGYZ}{\*\bkmkend AAAAAAAGYZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSER_E0_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGZA}{\*\bkmkend AAAAAAAGZA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSER_E0_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGZB}{\*\bkmkend AAAAAAAGZB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSER_E0_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGZC}{\*\bkmkend AAAAAAAGZC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSER_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_E7_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000080u){\*\bkmkstart AAAAAAAGZE}{\*\bkmkend AAAAAAAGZE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_E7_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAGZF}{\*\bkmkend AAAAAAAGZF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_E7_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGZG}{\*\bkmkend AAAAAAAGZG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_E7_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGZH}{\*\bkmkend AAAAAAAGZH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_E6_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000040u){\*\bkmkstart AAAAAAAGZI}{\*\bkmkend AAAAAAAGZI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_E6_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAAGZJ}{\*\bkmkend AAAAAAAGZJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_E6_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGZK}{\*\bkmkend AAAAAAAGZK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_E6_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGZL}{\*\bkmkend AAAAAAAGZL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_E5_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000020u){\*\bkmkstart AAAAAAAGZM}{\*\bkmkend AAAAAAAGZM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_E5_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAAGZN}{\*\bkmkend AAAAAAAGZN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_E5_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGZO}{\*\bkmkend AAAAAAAGZO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_E5_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGZP}{\*\bkmkend AAAAAAAGZP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_E4_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAGZQ}{\*\bkmkend AAAAAAAGZQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_E4_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAGZR}{\*\bkmkend AAAAAAAGZR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_E4_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGZS}{\*\bkmkend AAAAAAAGZS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_E4_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGZT}{\*\bkmkend AAAAAAAGZT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_E3_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAGZU}{\*\bkmkend AAAAAAAGZU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_E3_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAGZV}{\*\bkmkend AAAAAAAGZV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_E3_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGZW}{\*\bkmkend AAAAAAAGZW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_E3_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAGZX}{\*\bkmkend AAAAAAAGZX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_E2_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAGZY}{\*\bkmkend AAAAAAAGZY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_E2_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAGZZ}{\*\bkmkend AAAAAAAGZZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_E2_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHAA}{\*\bkmkend AAAAAAAHAA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_E2_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHAB}{\*\bkmkend AAAAAAAHAB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_E1_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAHAC}{\*\bkmkend AAAAAAAHAC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_E1_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHAD}{\*\bkmkend AAAAAAAHAD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_E1_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHAE}{\*\bkmkend AAAAAAAHAE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_E1_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHAF}{\*\bkmkend AAAAAAAHAF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_E0_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHAG}{\*\bkmkend AAAAAAAHAG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_E0_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHAH}{\*\bkmkend AAAAAAAHAH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_E0_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHAI}{\*\bkmkend AAAAAAAHAI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_E0_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHAJ}{\*\bkmkend AAAAAAAHAJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_PRIV_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x80000000u){\*\bkmkstart AAAAAAAHAL}{\*\bkmkend AAAAAAAHAL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_PRIV_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Fu){\*\bkmkstart AAAAAAAHAM}{\*\bkmkend AAAAAAAHAM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_PRIV_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHAN}{\*\bkmkend AAAAAAAHAN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_PRIV_USER}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHAO}{\*\bkmkend AAAAAAAHAO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_PRIV_SUPERVISOR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHAP}{\*\bkmkend AAAAAAAHAP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_SECURE_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x40000000u){\*\bkmkstart AAAAAAAHAQ}{\*\bkmkend AAAAAAAHAQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_SECURE_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000001Eu){\*\bkmkstart AAAAAAAHAR}{\*\bkmkend AAAAAAAHAR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_SECURE_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHAS}{\*\bkmkend AAAAAAAHAS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_SECURE_SECURE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHAT}{\*\bkmkend AAAAAAAHAT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_SECURE_NONSECURE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHAU}{\*\bkmkend AAAAAAAHAU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_PRIVID_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0F000000u){\*\bkmkstart AAAAAAAHAV}{\*\bkmkend AAAAAAAHAV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_PRIVID_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000018u){\*\bkmkstart AAAAAAAHAW}{\*\bkmkend AAAAAAAHAW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_PRIVID_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHAX}{\*\bkmkend AAAAAAAHAX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_ITCCHEN_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00800000u){\*\bkmkstart AAAAAAAHAY}{\*\bkmkend AAAAAAAHAY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_ITCCHEN_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000017u){\*\bkmkstart AAAAAAAHAZ}{\*\bkmkend AAAAAAAHAZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_ITCCHEN_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHBA}{\*\bkmkend AAAAAAAHBA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_ITCCHEN_DISABLE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHBB}{\*\bkmkend AAAAAAAHBB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_ITCCHEN_ENABLE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHBC}{\*\bkmkend AAAAAAAHBC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_TCCHEN_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAAHBD}{\*\bkmkend AAAAAAAHBD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_TCCHEN_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAAHBE}{\*\bkmkend AAAAAAAHBE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_TCCHEN_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHBF}{\*\bkmkend AAAAAAAHBF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_TCCHEN_DISABLE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHBG}{\*\bkmkend AAAAAAAHBG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_TCCHEN_ENABLE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHBH}{\*\bkmkend AAAAAAAHBH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_ITCINTEN_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00200000u){\*\bkmkstart AAAAAAAHBI}{\*\bkmkend AAAAAAAHBI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_ITCINTEN_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000015u){\*\bkmkstart AAAAAAAHBJ}{\*\bkmkend AAAAAAAHBJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_ITCINTEN_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHBK}{\*\bkmkend AAAAAAAHBK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_ITCINTEN_DISABLE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHBL}{\*\bkmkend AAAAAAAHBL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_ITCINTEN_ENABLE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHBM}{\*\bkmkend AAAAAAAHBM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_TCINTEN_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAAHBN}{\*\bkmkend AAAAAAAHBN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_TCINTEN_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAAHBO}{\*\bkmkend AAAAAAAHBO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_TCINTEN_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHBP}{\*\bkmkend AAAAAAAHBP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_TCINTEN_DISABLE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHBQ}{\*\bkmkend AAAAAAAHBQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_TCINTEN_ENABLE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHBR}{\*\bkmkend AAAAAAAHBR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_WIMODE_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00080000u){\*\bkmkstart AAAAAAAHBS}{\*\bkmkend AAAAAAAHBS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_WIMODE_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000013u){\*\bkmkstart AAAAAAAHBT}{\*\bkmkend AAAAAAAHBT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_WIMODE_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHBU}{\*\bkmkend AAAAAAAHBU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_WIMODE_NORMAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHBV}{\*\bkmkend AAAAAAAHBV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_WIMODE_WI}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHBW}{\*\bkmkend AAAAAAAHBW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_TCC_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0003F000u){\*\bkmkstart AAAAAAAHBX}{\*\bkmkend AAAAAAAHBX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_TCC_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAAHBY}{\*\bkmkend AAAAAAAHBY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_TCC_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHBZ}{\*\bkmkend AAAAAAAHBZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_TCCMODE_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000800u){\*\bkmkstart AAAAAAAHCA}{\*\bkmkend AAAAAAAHCA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_TCCMODE_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAAHCB}{\*\bkmkend AAAAAAAHCB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_TCCMODE_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHCC}{\*\bkmkend AAAAAAAHCC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_TCCMODE_NORMAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHCD}{\*\bkmkend AAAAAAAHCD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_TCCMODE_EARLY}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHCE}{\*\bkmkend AAAAAAAHCE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_FWID_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000700u){\*\bkmkstart AAAAAAAHCF}{\*\bkmkend AAAAAAAHCF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_FWID_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAHCG}{\*\bkmkend AAAAAAAHCG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_FWID_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHCH}{\*\bkmkend AAAAAAAHCH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_FWID_8}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHCI}{\*\bkmkend AAAAAAAHCI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_FWID_16}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHCJ}{\*\bkmkend AAAAAAAHCJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_FWID_32}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAHCK}{\*\bkmkend AAAAAAAHCK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_FWID_64}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAHCL}{\*\bkmkend AAAAAAAHCL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_FWID_128}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAHCM}{\*\bkmkend AAAAAAAHCM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_FWID_256}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAAHCN}{\*\bkmkend AAAAAAAHCN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_STATIC_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAHCO}{\*\bkmkend AAAAAAAHCO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_STATIC_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAHCP}{\*\bkmkend AAAAAAAHCP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_STATIC_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHCQ}{\*\bkmkend AAAAAAAHCQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_STATIC_NORMAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHCR}{\*\bkmkend AAAAAAAHCR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_STATIC_STATIC}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHCS}{\*\bkmkend AAAAAAAHCS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_SYNCDIM_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAHCT}{\*\bkmkend AAAAAAAHCT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_SYNCDIM_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAHCU}{\*\bkmkend AAAAAAAHCU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_SYNCDIM_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHCV}{\*\bkmkend AAAAAAAHCV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_SYNCDIM_ASYNC}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHCW}{\*\bkmkend AAAAAAAHCW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_SYNCDIM_ABSYNC}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHCX}{\*\bkmkend AAAAAAAHCX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_DAM_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAHCY}{\*\bkmkend AAAAAAAHCY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_DAM_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHCZ}{\*\bkmkend AAAAAAAHCZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_DAM_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHDA}{\*\bkmkend AAAAAAAHDA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_DAM_INCR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHDB}{\*\bkmkend AAAAAAAHDB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_DAM_FIFO}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHDC}{\*\bkmkend AAAAAAAHDC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_SAM_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHDD}{\*\bkmkend AAAAAAAHDD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_SAM_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHDE}{\*\bkmkend AAAAAAAHDE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_SAM_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHDF}{\*\bkmkend AAAAAAAHDF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_SAM_INCR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHDG}{\*\bkmkend AAAAAAAHDG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_SAM_FIFO}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHDH}{\*\bkmkend AAAAAAAHDH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_OPT_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHDI}{\*\bkmkend AAAAAAAHDI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SRC_SRC_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHDJ}{\*\bkmkend AAAAAAAHDJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SRC_SRC_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHDK}{\*\bkmkend AAAAAAAHDK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SRC_SRC_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHDL}{\*\bkmkend AAAAAAAHDL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SRC_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHDM}{\*\bkmkend AAAAAAAHDM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_A_B_CNT_BCNT_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFF0000u){\*\bkmkstart AAAAAAAHDN}{\*\bkmkend AAAAAAAHDN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_A_B_CNT_BCNT_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAHDO}{\*\bkmkend AAAAAAAHDO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_A_B_CNT_BCNT_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHDP}{\*\bkmkend AAAAAAAHDP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_A_B_CNT_ACNT_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000FFFFu){\*\bkmkstart AAAAAAAHDQ}{\*\bkmkend AAAAAAAHDQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_A_B_CNT_ACNT_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHDR}{\*\bkmkend AAAAAAAHDR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_A_B_CNT_ACNT_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHDS}{\*\bkmkend AAAAAAAHDS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_A_B_CNT_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHDT}{\*\bkmkend AAAAAAAHDT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DST_DST_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHDU}{\*\bkmkend AAAAAAAHDU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DST_DST_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHDV}{\*\bkmkend AAAAAAAHDV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DST_DST_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHDW}{\*\bkmkend AAAAAAAHDW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_DST_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHDX}{\*\bkmkend AAAAAAAHDX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SRC_DST_BIDX_DSTBIDX_MASK}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0xFFFF0000u){\*\bkmkstart AAAAAAAHDY}{\*\bkmkend AAAAAAAHDY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SRC_DST_BIDX_DSTBIDX_SHIFT}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAHDZ}{\*\bkmkend AAAAAAAHDZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SRC_DST_BIDX_DSTBIDX_RESETVAL}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHEA}{\*\bkmkend AAAAAAAHEA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SRC_DST_BIDX_SRCBIDX_MASK}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x0000FFFFu){\*\bkmkstart AAAAAAAHEB}{\*\bkmkend AAAAAAAHEB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SRC_DST_BIDX_SRCBIDX_SHIFT}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHEC}{\*\bkmkend AAAAAAAHEC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SRC_DST_BIDX_SRCBIDX_RESETVAL}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHED}{\*\bkmkend AAAAAAAHED} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SRC_DST_BIDX_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHEE}{\*\bkmkend AAAAAAAHEE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_LINK_BCNTRLD_BCNTRLD_MASK}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0xFFFF0000u){\*\bkmkstart AAAAAAAHEF}{\*\bkmkend AAAAAAAHEF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_LINK_BCNTRLD_BCNTRLD_SHIFT}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAHEG}{\*\bkmkend AAAAAAAHEG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_LINK_BCNTRLD_BCNTRLD_RESETVAL}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHEH}{\*\bkmkend AAAAAAAHEH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_LINK_BCNTRLD_LINK_MASK}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x0000FFFFu){\*\bkmkstart AAAAAAAHEI}{\*\bkmkend AAAAAAAHEI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_LINK_BCNTRLD_LINK_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHEJ}{\*\bkmkend AAAAAAAHEJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_LINK_BCNTRLD_LINK_RESETVAL}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHEK}{\*\bkmkend AAAAAAAHEK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_LINK_BCNTRLD_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHEL}{\*\bkmkend AAAAAAAHEL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SRC_DST_CIDX_DSTCIDX_MASK}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0xFFFF0000u){\*\bkmkstart AAAAAAAHEM}{\*\bkmkend AAAAAAAHEM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SRC_DST_CIDX_DSTCIDX_SHIFT}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAHEN}{\*\bkmkend AAAAAAAHEN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SRC_DST_CIDX_DSTCIDX_RESETVAL}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHEO}{\*\bkmkend AAAAAAAHEO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SRC_DST_CIDX_SRCCIDX_MASK}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x0000FFFFu){\*\bkmkstart AAAAAAAHEP}{\*\bkmkend AAAAAAAHEP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SRC_DST_CIDX_SRCCIDX_SHIFT}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHEQ}{\*\bkmkend AAAAAAAHEQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SRC_DST_CIDX_SRCCIDX_RESETVAL}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHER}{\*\bkmkend AAAAAAAHER} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SRC_DST_CIDX_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHES}{\*\bkmkend AAAAAAAHES} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCNT_CCNT_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000FFFFu){\*\bkmkstart AAAAAAAHET}{\*\bkmkend AAAAAAAHET} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCNT_CCNT_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHEU}{\*\bkmkend AAAAAAAHEU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCNT_CCNT_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHEV}{\*\bkmkend AAAAAAAHEV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CCNT_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHEW}{\*\bkmkend AAAAAAAHEW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_REG_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHEX}{\*\bkmkend AAAAAAAHEX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_REG_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHEY}{\*\bkmkend AAAAAAAHEY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_REG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHEZ}{\*\bkmkend AAAAAAAHEZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ER_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACCX}{\*\bkmkend AAAAAAACCX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_REG_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHFA}{\*\bkmkend AAAAAAAHFA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_REG_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHFB}{\*\bkmkend AAAAAAAHFB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_REG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHFC}{\*\bkmkend AAAAAAAHFC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ERH_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACGQ}{\*\bkmkend AAAAAAACGQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_REG_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHFD}{\*\bkmkend AAAAAAAHFD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_REG_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHFE}{\*\bkmkend AAAAAAAHFE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_REG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHFF}{\*\bkmkend AAAAAAAHFF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACLP}{\*\bkmkend AAAAAAACLP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_REG_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHFG}{\*\bkmkend AAAAAAAHFG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_REG_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHFH}{\*\bkmkend AAAAAAAHFH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_REG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHFI}{\*\bkmkend AAAAAAAHFI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ECRH_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACQO}{\*\bkmkend AAAAAAACQO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_REG_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHFJ}{\*\bkmkend AAAAAAAHFJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_REG_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHFK}{\*\bkmkend AAAAAAAHFK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_REG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHFL}{\*\bkmkend AAAAAAAHFL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAACVN}{\*\bkmkend AAAAAAACVN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_REG_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHFM}{\*\bkmkend AAAAAAAHFM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_REG_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHFN}{\*\bkmkend AAAAAAAHFN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_REG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHFO}{\*\bkmkend AAAAAAAHFO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ESRH_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADAM}{\*\bkmkend AAAAAAADAM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_REG_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHFP}{\*\bkmkend AAAAAAAHFP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_REG_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHFQ}{\*\bkmkend AAAAAAAHFQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_REG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHFR}{\*\bkmkend AAAAAAAHFR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CER_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADEF}{\*\bkmkend AAAAAAADEF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_REG_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHFS}{\*\bkmkend AAAAAAAHFS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_REG_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHFT}{\*\bkmkend AAAAAAAHFT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_REG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHFU}{\*\bkmkend AAAAAAAHFU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_CERH_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADHY}{\*\bkmkend AAAAAAADHY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_REG_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHFV}{\*\bkmkend AAAAAAAHFV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_REG_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHFW}{\*\bkmkend AAAAAAAHFW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_REG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHFX}{\*\bkmkend AAAAAAAHFX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EER_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADLS}{\*\bkmkend AAAAAAADLS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_REG_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHFY}{\*\bkmkend AAAAAAAHFY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_REG_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHFZ}{\*\bkmkend AAAAAAAHFZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_REG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHGA}{\*\bkmkend AAAAAAAHGA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EERH_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADPL}{\*\bkmkend AAAAAAADPL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_REG_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHGB}{\*\bkmkend AAAAAAAHGB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_REG_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHGC}{\*\bkmkend AAAAAAAHGC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_REG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHGD}{\*\bkmkend AAAAAAAHGD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADUK}{\*\bkmkend AAAAAAADUK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_REG_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHGE}{\*\bkmkend AAAAAAAHGE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_REG_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHGF}{\*\bkmkend AAAAAAAHGF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_REG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHGG}{\*\bkmkend AAAAAAAHGG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EECRH_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAADZJ}{\*\bkmkend AAAAAAADZJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_REG_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHGH}{\*\bkmkend AAAAAAAHGH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_REG_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHGI}{\*\bkmkend AAAAAAAHGI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_REG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHGJ}{\*\bkmkend AAAAAAAHGJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEEI}{\*\bkmkend AAAAAAAEEI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_REG_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHGK}{\*\bkmkend AAAAAAAHGK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_REG_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHGL}{\*\bkmkend AAAAAAAHGL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_REG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHGM}{\*\bkmkend AAAAAAAHGM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_EESRH_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEJH}{\*\bkmkend AAAAAAAEJH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_REG_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHGN}{\*\bkmkend AAAAAAAHGN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_REG_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHGO}{\*\bkmkend AAAAAAAHGO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_REG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHGP}{\*\bkmkend AAAAAAAHGP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SER_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAENA}{\*\bkmkend AAAAAAAENA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_REG_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHGQ}{\*\bkmkend AAAAAAAHGQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_REG_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHGR}{\*\bkmkend AAAAAAAHGR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_REG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHGS}{\*\bkmkend AAAAAAAHGS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SERH_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEQT}{\*\bkmkend AAAAAAAEQT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_REG_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHGT}{\*\bkmkend AAAAAAAHGT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_REG_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHGU}{\*\bkmkend AAAAAAAHGU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_REG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHGV}{\*\bkmkend AAAAAAAHGV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAEVS}{\*\bkmkend AAAAAAAEVS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_REG_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHGW}{\*\bkmkend AAAAAAAHGW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_REG_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHGX}{\*\bkmkend AAAAAAAHGX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_REG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHGY}{\*\bkmkend AAAAAAAHGY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_SECRH_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFAR}{\*\bkmkend AAAAAAAFAR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_REG_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHGZ}{\*\bkmkend AAAAAAAHGZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_REG_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHHA}{\*\bkmkend AAAAAAAHHA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_REG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHHB}{\*\bkmkend AAAAAAAHHB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IER_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFEK}{\*\bkmkend AAAAAAAFEK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_REG_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHHC}{\*\bkmkend AAAAAAAHHC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_REG_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHHD}{\*\bkmkend AAAAAAAHHD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_REG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHHE}{\*\bkmkend AAAAAAAHHE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IERH_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFID}{\*\bkmkend AAAAAAAFID} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_REG_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHHF}{\*\bkmkend AAAAAAAHHF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_REG_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHHG}{\*\bkmkend AAAAAAAHHG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_REG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHHH}{\*\bkmkend AAAAAAAHHH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFNC}{\*\bkmkend AAAAAAAFNC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_REG_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHHI}{\*\bkmkend AAAAAAAHHI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_REG_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHHJ}{\*\bkmkend AAAAAAAHHJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_REG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHHK}{\*\bkmkend AAAAAAAHHK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IECRH_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFSB}{\*\bkmkend AAAAAAAFSB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_REG_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHHL}{\*\bkmkend AAAAAAAHHL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_REG_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHHM}{\*\bkmkend AAAAAAAHHM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_REG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHHN}{\*\bkmkend AAAAAAAHHN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAFXA}{\*\bkmkend AAAAAAAFXA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_REG_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHHO}{\*\bkmkend AAAAAAAHHO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_REG_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHHP}{\*\bkmkend AAAAAAAHHP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_REG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHHQ}{\*\bkmkend AAAAAAAHHQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IESRH_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGBZ}{\*\bkmkend AAAAAAAGBZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_REG_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHHR}{\*\bkmkend AAAAAAAHHR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_REG_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHHS}{\*\bkmkend AAAAAAAHHS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_REG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHHT}{\*\bkmkend AAAAAAAHHT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGFS}{\*\bkmkend AAAAAAAGFS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_REG_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHHU}{\*\bkmkend AAAAAAAHHU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_REG_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHHV}{\*\bkmkend AAAAAAAHHV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_REG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHHW}{\*\bkmkend AAAAAAAHHW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IPRH_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGJL}{\*\bkmkend AAAAAAAGJL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_REG_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHHX}{\*\bkmkend AAAAAAAHHX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_REG_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHHY}{\*\bkmkend AAAAAAAHHY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_REG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHHZ}{\*\bkmkend AAAAAAAHHZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGOK}{\*\bkmkend AAAAAAAGOK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_REG_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHIA}{\*\bkmkend AAAAAAAHIA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_REG_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHIB}{\*\bkmkend AAAAAAAHIB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_REG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHIC}{\*\bkmkend AAAAAAAHIC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ICRH_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGTJ}{\*\bkmkend AAAAAAAGTJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IEVAL_REG_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHID}{\*\bkmkend AAAAAAAHID} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IEVAL_REG_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHIE}{\*\bkmkend AAAAAAAHIE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IEVAL_REG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHIF}{\*\bkmkend AAAAAAAHIF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_IEVAL_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGTS}{\*\bkmkend AAAAAAAGTS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QER_REG_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHIG}{\*\bkmkend AAAAAAAHIG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QER_REG_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHIH}{\*\bkmkend AAAAAAAHIH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QER_REG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHII}{\*\bkmkend AAAAAAAHII} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QER_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGUR}{\*\bkmkend AAAAAAAGUR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEER_REG_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHIJ}{\*\bkmkend AAAAAAAHIJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEER_REG_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHIK}{\*\bkmkend AAAAAAAHIK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEER_REG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHIL}{\*\bkmkend AAAAAAAHIL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEER_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGVQ}{\*\bkmkend AAAAAAAGVQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_REG_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHIM}{\*\bkmkend AAAAAAAHIM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_REG_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHIN}{\*\bkmkend AAAAAAAHIN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_REG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHIO}{\*\bkmkend AAAAAAAHIO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEECR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGWX}{\*\bkmkend AAAAAAAGWX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_REG_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHIP}{\*\bkmkend AAAAAAAHIP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_REG_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHIQ}{\*\bkmkend AAAAAAAHIQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_REG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHIR}{\*\bkmkend AAAAAAAHIR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QEESR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGYE}{\*\bkmkend AAAAAAAGYE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSER_REG_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHIS}{\*\bkmkend AAAAAAAHIS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSER_REG_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHIT}{\*\bkmkend AAAAAAAHIT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSER_REG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHIU}{\*\bkmkend AAAAAAAHIU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSER_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAGZD}{\*\bkmkend AAAAAAAGZD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_REG_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHIV}{\*\bkmkend AAAAAAAHIV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_REG_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHIW}{\*\bkmkend AAAAAAAHIW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_REG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHIX}{\*\bkmkend AAAAAAAHIX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_QSECR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHAK}{\*\bkmkend AAAAAAAHAK} +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Typedefs +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +typedef volatile EDMA3_CCRL_ShadowRegs * }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_ShadowRegsOvly}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAHIY}{\*\bkmkend AAAAAAAHIY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 typedef volatile EDMA3_CCRL_ParamentryRegs * }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_CCRL_ParamentryRegsOvly}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAHIZ}{\*\bkmkend AAAAAAAHIZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 typedef volatile EDMA3_CCRL_Regs * }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_CCRL_RegsOvly}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAHJA}{\*\bkmkend AAAAAAAHJA} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 EDMA3 Channel Controller Register Desciption. +\par This file contains the register layer for the EDMA3 Channel Controller. +\par (C) Copyright 2006, Texas Instruments, Inc +\par }\pard\plain \ltrpar\s5\qj \li0\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Version: +\par }\pard\plain \ltrpar\s43\ql \li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 1.0 Anuj Aggarwal - Created +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 +\ltrch\fcs0 \fs24\insrsid7370340 +\par \sect }\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 +\ltrch\fcs0 \b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_rl_tc.h File Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc { +\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \tcl2{\*\bkmkstart _Toc211937581}edma3_rl_tc.h{\*\bkmkend _Toc211937581}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn +\pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 edma3_rl_tc.h}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAHJB}{\*\bkmkend AAAAAAAHJB}EDMA3 Transfer Controller Register Desciption. +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Data Structures +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DfiregRegs}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 struct }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_Regs}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Defines +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define } +{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_REV_TYPE_MASK}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00FF0000u){\*\bkmkstart AAAAAAAHJC}{\*\bkmkend AAAAAAAHJC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_REV_TYPE_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAHJD}{\*\bkmkend AAAAAAAHJD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_REV_TYPE_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000006u){\*\bkmkstart AAAAAAAHJE}{\*\bkmkend AAAAAAAHJE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_REV_CLASS_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000FF00u){\*\bkmkstart AAAAAAAHJF}{\*\bkmkend AAAAAAAHJF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_REV_CLASS_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAHJG}{\*\bkmkend AAAAAAAHJG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_REV_CLASS_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAHJH}{\*\bkmkend AAAAAAAHJH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_REV_REV_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x000000FFu){\*\bkmkstart AAAAAAAHJI}{\*\bkmkend AAAAAAAHJI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_REV_REV_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHJJ}{\*\bkmkend AAAAAAAHJJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_REV_REV_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHJK}{\*\bkmkend AAAAAAAHJK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_REV_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00060401u){\*\bkmkstart AAAAAAAHJL}{\*\bkmkend AAAAAAAHJL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCCFG_DREGDEPTH_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000300u){\*\bkmkstart AAAAAAAHJM}{\*\bkmkend AAAAAAAHJM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCCFG_DREGDEPTH_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAHJN}{\*\bkmkend AAAAAAAHJN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCCFG_DREGDEPTH_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHJO}{\*\bkmkend AAAAAAAHJO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCCFG_DREGDEPTH_1ENTRY}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHJP}{\*\bkmkend AAAAAAAHJP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCCFG_DREGDEPTH_2ENTRY}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHJQ}{\*\bkmkend AAAAAAAHJQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCCFG_DREGDEPTH_4ENTRY}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAHJR}{\*\bkmkend AAAAAAAHJR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCCFG_BUSWIDTH_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000030u){\*\bkmkstart AAAAAAAHJS}{\*\bkmkend AAAAAAAHJS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCCFG_BUSWIDTH_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAHJT}{\*\bkmkend AAAAAAAHJT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCCFG_BUSWIDTH_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHJU}{\*\bkmkend AAAAAAAHJU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCCFG_BUSWIDTH_32BIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHJV}{\*\bkmkend AAAAAAAHJV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCCFG_BUSWIDTH_64BIY}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHJW}{\*\bkmkend AAAAAAAHJW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCCFG_BUSWIDTH_128BIT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAHJX}{\*\bkmkend AAAAAAAHJX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCCFG_FIFOSIZE_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAHJY}{\*\bkmkend AAAAAAAHJY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCCFG_FIFOSIZE_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHJZ}{\*\bkmkend AAAAAAAHJZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCCFG_FIFOSIZE_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHKA}{\*\bkmkend AAAAAAAHKA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCCFG_FIFOSIZE_32BYTE}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHKB}{\*\bkmkend AAAAAAAHKB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCCFG_FIFOSIZE_64BYTE}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHKC}{\*\bkmkend AAAAAAAHKC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCCFG_FIFOSIZE_128BYTE}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAHKD}{\*\bkmkend AAAAAAAHKD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCCFG_FIFOSIZE_256BYTE}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAHKE}{\*\bkmkend AAAAAAAHKE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCCFG_FIFOSIZE_512BYTE}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAHKF}{\*\bkmkend AAAAAAAHKF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCCFG_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHKG}{\*\bkmkend AAAAAAAHKG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCSTAT_DFSTRT_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00003000u){\*\bkmkstart AAAAAAAHKH}{\*\bkmkend AAAAAAAHKH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCSTAT_DFSTRT_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAAHKI}{\*\bkmkend AAAAAAAHKI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCSTAT_DFSTRT_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHKJ}{\*\bkmkend AAAAAAAHKJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCSTAT_ATCV_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAAHKK}{\*\bkmkend AAAAAAAHKK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCSTAT_ATCV_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAHKL}{\*\bkmkend AAAAAAAHKL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCSTAT_ATCV_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHKM}{\*\bkmkend AAAAAAAHKM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCSTAT_ATCV_IDLE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHKN}{\*\bkmkend AAAAAAAHKN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCSTAT_ATCV_BUSY}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHKO}{\*\bkmkend AAAAAAAHKO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCSTAT_DSTACT_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000070u){\*\bkmkstart AAAAAAAHKP}{\*\bkmkend AAAAAAAHKP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCSTAT_DSTACT_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAHKQ}{\*\bkmkend AAAAAAAHKQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCSTAT_DSTACT_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHKR}{\*\bkmkend AAAAAAAHKR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCSTAT_DSTACT_EMPTY}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHKS}{\*\bkmkend AAAAAAAHKS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCSTAT_DSTACT_1TR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHKT}{\*\bkmkend AAAAAAAHKT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCSTAT_DSTACT_2TR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAHKU}{\*\bkmkend AAAAAAAHKU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCSTAT_DSTACT_3TR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAHKV}{\*\bkmkend AAAAAAAHKV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCSTAT_DSTACT_4TR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAHKW}{\*\bkmkend AAAAAAAHKW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCSTAT_WSACTV_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAHKX}{\*\bkmkend AAAAAAAHKX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCSTAT_WSACTV_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAHKY}{\*\bkmkend AAAAAAAHKY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCSTAT_WSACTV_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHKZ}{\*\bkmkend AAAAAAAHKZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCSTAT_WSACTV_NONE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHLA}{\*\bkmkend AAAAAAAHLA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCSTAT_WSACTV_PEND}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHLB}{\*\bkmkend AAAAAAAHLB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCSTAT_SRCACTV_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAHLC}{\*\bkmkend AAAAAAAHLC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCSTAT_SRCACTV_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHLD}{\*\bkmkend AAAAAAAHLD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCSTAT_SRCACTV_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHLE}{\*\bkmkend AAAAAAAHLE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCSTAT_SRCACTV_IDLE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHLF}{\*\bkmkend AAAAAAAHLF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCSTAT_SRCACTV_BUSY}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHLG}{\*\bkmkend AAAAAAAHLG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCSTAT_PROGBUSY_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHLH}{\*\bkmkend AAAAAAAHLH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCSTAT_PROGBUSY_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHLI}{\*\bkmkend AAAAAAAHLI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCSTAT_PROGBUSY_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHLJ}{\*\bkmkend AAAAAAAHLJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCSTAT_PROGBUSY_IDLE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHLK}{\*\bkmkend AAAAAAAHLK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCSTAT_PROGBUSY_BUSY}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHLL}{\*\bkmkend AAAAAAAHLL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_TCSTAT_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHLM}{\*\bkmkend AAAAAAAHLM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTSTAT_TRDONE_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAHLN}{\*\bkmkend AAAAAAAHLN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTSTAT_TRDONE_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHLO}{\*\bkmkend AAAAAAAHLO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTSTAT_TRDONE_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHLP}{\*\bkmkend AAAAAAAHLP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTSTAT_TRDONE_NONE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHLQ}{\*\bkmkend AAAAAAAHLQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTSTAT_TRDONE_DONE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHLR}{\*\bkmkend AAAAAAAHLR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTSTAT_PROGEMPTY_MASK}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHLS}{\*\bkmkend AAAAAAAHLS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTSTAT_PROGEMPTY_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHLT}{\*\bkmkend AAAAAAAHLT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTSTAT_PROGEMPTY_RESETVAL}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHLU}{\*\bkmkend AAAAAAAHLU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTSTAT_PROGEMPTY_NONE}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHLV}{\*\bkmkend AAAAAAAHLV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTSTAT_PROGEMPTY_EMPTY}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHLW}{\*\bkmkend AAAAAAAHLW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTSTAT_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHLX}{\*\bkmkend AAAAAAAHLX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTEN_TRDONE_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAHLY}{\*\bkmkend AAAAAAAHLY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTEN_TRDONE_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHLZ}{\*\bkmkend AAAAAAAHLZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTEN_TRDONE_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHMA}{\*\bkmkend AAAAAAAHMA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTEN_TRDONE_DISABLE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHMB}{\*\bkmkend AAAAAAAHMB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTEN_TRDONE_ENABLE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHMC}{\*\bkmkend AAAAAAAHMC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTEN_PROGEMPTY_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHMD}{\*\bkmkend AAAAAAAHMD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTEN_PROGEMPTY_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHME}{\*\bkmkend AAAAAAAHME} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTEN_PROGEMPTY_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHMF}{\*\bkmkend AAAAAAAHMF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTEN_PROGEMPTY_DISABLE}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHMG}{\*\bkmkend AAAAAAAHMG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTEN_PROGEMPTY_ENABLE}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHMH}{\*\bkmkend AAAAAAAHMH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTEN_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHMI}{\*\bkmkend AAAAAAAHMI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTCLR_TRDONE_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAHMJ}{\*\bkmkend AAAAAAAHMJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTCLR_TRDONE_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHMK}{\*\bkmkend AAAAAAAHMK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTCLR_TRDONE_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHML}{\*\bkmkend AAAAAAAHML} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTCLR_TRDONE_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHMM}{\*\bkmkend AAAAAAAHMM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTCLR_PROGEMPTY_MASK}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHMN}{\*\bkmkend AAAAAAAHMN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTCLR_PROGEMPTY_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHMO}{\*\bkmkend AAAAAAAHMO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTCLR_PROGEMPTY_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHMP}{\*\bkmkend AAAAAAAHMP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTCLR_PROGEMPTY_CLEAR}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHMQ}{\*\bkmkend AAAAAAAHMQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTCLR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHMR}{\*\bkmkend AAAAAAAHMR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTCMD_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAHMS}{\*\bkmkend AAAAAAAHMS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTCMD_SET_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHMT}{\*\bkmkend AAAAAAAHMT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTCMD_SET_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHMU}{\*\bkmkend AAAAAAAHMU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTCMD_SET_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHMV}{\*\bkmkend AAAAAAAHMV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTCMD_EVAL_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHMW}{\*\bkmkend AAAAAAAHMW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTCMD_EVAL_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHMX}{\*\bkmkend AAAAAAAHMX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTCMD_EVAL_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHMY}{\*\bkmkend AAAAAAAHMY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTCMD_EVAL_EVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHMZ}{\*\bkmkend AAAAAAAHMZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_INTCMD_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHNA}{\*\bkmkend AAAAAAAHNA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRSTAT_MMRAERR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAHNB}{\*\bkmkend AAAAAAAHNB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRSTAT_MMRAERR_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAHNC}{\*\bkmkend AAAAAAAHNC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRSTAT_MMRAERR_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHND}{\*\bkmkend AAAAAAAHND} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRSTAT_MMRAERR_NONE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHNE}{\*\bkmkend AAAAAAAHNE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRSTAT_MMRAERR_ERROR}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHNF}{\*\bkmkend AAAAAAAHNF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRSTAT_TRERR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAHNG}{\*\bkmkend AAAAAAAHNG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRSTAT_TRERR_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAHNH}{\*\bkmkend AAAAAAAHNH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRSTAT_TRERR_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHNI}{\*\bkmkend AAAAAAAHNI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRSTAT_TRERR_NONE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHNJ}{\*\bkmkend AAAAAAAHNJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRSTAT_TRERR_ERROR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHNK}{\*\bkmkend AAAAAAAHNK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRSTAT_BUSERR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHNL}{\*\bkmkend AAAAAAAHNL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRSTAT_BUSERR_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHNM}{\*\bkmkend AAAAAAAHNM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRSTAT_BUSERR_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHNN}{\*\bkmkend AAAAAAAHNN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRSTAT_BUSERR_NONE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHNO}{\*\bkmkend AAAAAAAHNO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRSTAT_BUSERR_ERROR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHNP}{\*\bkmkend AAAAAAAHNP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRSTAT_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHNQ}{\*\bkmkend AAAAAAAHNQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERREN_MMRAERR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAHNR}{\*\bkmkend AAAAAAAHNR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERREN_MMRAERR_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAHNS}{\*\bkmkend AAAAAAAHNS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERREN_MMRAERR_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHNT}{\*\bkmkend AAAAAAAHNT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERREN_MMRAERR_ENABLE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHNU}{\*\bkmkend AAAAAAAHNU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERREN_MMRAERR_DISABLE}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHNV}{\*\bkmkend AAAAAAAHNV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERREN_TRERR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAHNW}{\*\bkmkend AAAAAAAHNW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERREN_TRERR_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAHNX}{\*\bkmkend AAAAAAAHNX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERREN_TRERR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHNY}{\*\bkmkend AAAAAAAHNY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERREN_TRERR_ENABLE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHNZ}{\*\bkmkend AAAAAAAHNZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERREN_TRERR_DISABLE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHOA}{\*\bkmkend AAAAAAAHOA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERREN_BUSERR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHOB}{\*\bkmkend AAAAAAAHOB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERREN_BUSERR_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHOC}{\*\bkmkend AAAAAAAHOC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERREN_BUSERR_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHOD}{\*\bkmkend AAAAAAAHOD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERREN_BUSERR_ENABLE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHOE}{\*\bkmkend AAAAAAAHOE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERREN_BUSERR_DISABLE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHOF}{\*\bkmkend AAAAAAAHOF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERREN_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHOG}{\*\bkmkend AAAAAAAHOG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRCLR_MMRAERR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAHOH}{\*\bkmkend AAAAAAAHOH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRCLR_MMRAERR_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAHOI}{\*\bkmkend AAAAAAAHOI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRCLR_MMRAERR_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHOJ}{\*\bkmkend AAAAAAAHOJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRCLR_MMRAERR_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHOK}{\*\bkmkend AAAAAAAHOK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRCLR_TRERR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAHOL}{\*\bkmkend AAAAAAAHOL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRCLR_TRERR_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAHOM}{\*\bkmkend AAAAAAAHOM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRCLR_TRERR_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHON}{\*\bkmkend AAAAAAAHON} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRCLR_TRERR_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHOO}{\*\bkmkend AAAAAAAHOO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRCLR_BUSERR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHOP}{\*\bkmkend AAAAAAAHOP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRCLR_BUSERR_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHOQ}{\*\bkmkend AAAAAAAHOQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRCLR_BUSERR_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHOR}{\*\bkmkend AAAAAAAHOR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRCLR_BUSERR_CLEAR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHOS}{\*\bkmkend AAAAAAAHOS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRCLR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHOT}{\*\bkmkend AAAAAAAHOT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRDET_TCCHEN_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00020000u){\*\bkmkstart AAAAAAAHOU}{\*\bkmkend AAAAAAAHOU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRDET_TCCHEN_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000011u){\*\bkmkstart AAAAAAAHOV}{\*\bkmkend AAAAAAAHOV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRDET_TCCHEN_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHOW}{\*\bkmkend AAAAAAAHOW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRDET_TCINTEN_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00010000u){\*\bkmkstart AAAAAAAHOX}{\*\bkmkend AAAAAAAHOX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRDET_TCINTEN_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAHOY}{\*\bkmkend AAAAAAAHOY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRDET_TCINTEN_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHOZ}{\*\bkmkend AAAAAAAHOZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRDET_TCC_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00003F00u){\*\bkmkstart AAAAAAAHPA}{\*\bkmkend AAAAAAAHPA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRDET_TCC_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAHPB}{\*\bkmkend AAAAAAAHPB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRDET_TCC_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHPC}{\*\bkmkend AAAAAAAHPC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRDET_STAT_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAAHPD}{\*\bkmkend AAAAAAAHPD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRDET_STAT_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHPE}{\*\bkmkend AAAAAAAHPE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRDET_STAT_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHPF}{\*\bkmkend AAAAAAAHPF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRDET_STAT_NONE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHPG}{\*\bkmkend AAAAAAAHPG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRDET_STAT_READ_ADDRESS}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHPH}{\*\bkmkend AAAAAAAHPH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRDET_STAT_READ_PRIVILEGE}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAHPI}{\*\bkmkend AAAAAAAHPI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRDET_STAT_READ_TIMEOUT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAHPJ}{\*\bkmkend AAAAAAAHPJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRDET_STAT_READ_DATA}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAHPK}{\*\bkmkend AAAAAAAHPK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRDET_STAT_READ_EXCLUSIVE}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAHPL}{\*\bkmkend AAAAAAAHPL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRDET_STAT_WRITE_ADDRESS}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000009u){\*\bkmkstart AAAAAAAHPM}{\*\bkmkend AAAAAAAHPM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRDET_STAT_WRITE_PRIVILEGE}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0x0000000Au){\*\bkmkstart AAAAAAAHPN}{\*\bkmkend AAAAAAAHPN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRDET_STAT_WRITE_TIMEOUT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x0000000Bu){\*\bkmkstart AAAAAAAHPO}{\*\bkmkend AAAAAAAHPO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRDET_STAT_WRITE_DATA}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAAHPP}{\*\bkmkend AAAAAAAHPP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRDET_STAT_WRITE_EXCLUSIVE}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAAHPQ}{\*\bkmkend AAAAAAAHPQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRDET_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHPR}{\*\bkmkend AAAAAAAHPR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRCMD_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAHPS}{\*\bkmkend AAAAAAAHPS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRCMD_SET_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHPT}{\*\bkmkend AAAAAAAHPT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRCMD_SET_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHPU}{\*\bkmkend AAAAAAAHPU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRCMD_SET_SET}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHPV}{\*\bkmkend AAAAAAAHPV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRCMD_EVAL_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHPW}{\*\bkmkend AAAAAAAHPW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRCMD_EVAL_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHPX}{\*\bkmkend AAAAAAAHPX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRCMD_EVAL_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHPY}{\*\bkmkend AAAAAAAHPY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRCMD_EVAL_EVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHPZ}{\*\bkmkend AAAAAAAHPZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_ERRCMD_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHQA}{\*\bkmkend AAAAAAAHQA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_RDRATE_RDRATE_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000007u){\*\bkmkstart AAAAAAAHQB}{\*\bkmkend AAAAAAAHQB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_RDRATE_RDRATE_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHQC}{\*\bkmkend AAAAAAAHQC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_RDRATE_RDRATE_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHQD}{\*\bkmkend AAAAAAAHQD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_RDRATE_RDRATE_AFAP}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHQE}{\*\bkmkend AAAAAAAHQE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_RDRATE_RDRATE_4CYCLE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHQF}{\*\bkmkend AAAAAAAHQF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_RDRATE_RDRATE_8CYCLE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAHQG}{\*\bkmkend AAAAAAAHQG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_RDRATE_RDRATE_16CYCLE}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAHQH}{\*\bkmkend AAAAAAAHQH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_RDRATE_RDRATE_32CYCLE}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAHQI}{\*\bkmkend AAAAAAAHQI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_RDRATE_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHQJ}{\*\bkmkend AAAAAAAHQJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_POPT_TCCHEN_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAAHQK}{\*\bkmkend AAAAAAAHQK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_POPT_TCCHEN_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAAHQL}{\*\bkmkend AAAAAAAHQL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_POPT_TCCHEN_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHQM}{\*\bkmkend AAAAAAAHQM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_POPT_TCCHEN_DISABLE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHQN}{\*\bkmkend AAAAAAAHQN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_POPT_TCCHEN_ENABLE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHQO}{\*\bkmkend AAAAAAAHQO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_POPT_TCINTEN_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAAHQP}{\*\bkmkend AAAAAAAHQP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_POPT_TCINTEN_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAAHQQ}{\*\bkmkend AAAAAAAHQQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_POPT_TCINTEN_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHQR}{\*\bkmkend AAAAAAAHQR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_POPT_TCINTEN_DISABLE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHQS}{\*\bkmkend AAAAAAAHQS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_POPT_TCINTEN_ENABLE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHQT}{\*\bkmkend AAAAAAAHQT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_POPT_TCC_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0003F000u){\*\bkmkstart AAAAAAAHQU}{\*\bkmkend AAAAAAAHQU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_POPT_TCC_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAAHQV}{\*\bkmkend AAAAAAAHQV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_POPT_TCC_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHQW}{\*\bkmkend AAAAAAAHQW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_POPT_FWID_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000700u){\*\bkmkstart AAAAAAAHQX}{\*\bkmkend AAAAAAAHQX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_POPT_FWID_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAHQY}{\*\bkmkend AAAAAAAHQY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_POPT_FWID_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHQZ}{\*\bkmkend AAAAAAAHQZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_POPT_FWID_8BIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHRA}{\*\bkmkend AAAAAAAHRA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_POPT_FWID_16BIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHRB}{\*\bkmkend AAAAAAAHRB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_POPT_FWID_32BIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAHRC}{\*\bkmkend AAAAAAAHRC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_POPT_FWID_64BIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAHRD}{\*\bkmkend AAAAAAAHRD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_POPT_FWID_128BIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAHRE}{\*\bkmkend AAAAAAAHRE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_POPT_FWID_256BIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAAHRF}{\*\bkmkend AAAAAAAHRF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_POPT_PRI_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000070u){\*\bkmkstart AAAAAAAHRG}{\*\bkmkend AAAAAAAHRG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_POPT_PRI_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAHRH}{\*\bkmkend AAAAAAAHRH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_POPT_PRI_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHRI}{\*\bkmkend AAAAAAAHRI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_POPT_DAM_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAHRJ}{\*\bkmkend AAAAAAAHRJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_POPT_DAM_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHRK}{\*\bkmkend AAAAAAAHRK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_POPT_DAM_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHRL}{\*\bkmkend AAAAAAAHRL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_POPT_DAM_INCR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHRM}{\*\bkmkend AAAAAAAHRM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_POPT_DAM_FIFO}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHRN}{\*\bkmkend AAAAAAAHRN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_POPT_SAM_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHRO}{\*\bkmkend AAAAAAAHRO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_POPT_SAM_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHRP}{\*\bkmkend AAAAAAAHRP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_POPT_SAM_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHRQ}{\*\bkmkend AAAAAAAHRQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_POPT_SAM_INCR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHRR}{\*\bkmkend AAAAAAAHRR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_POPT_SAM_FIFO}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHRS}{\*\bkmkend AAAAAAAHRS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_POPT_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHRT}{\*\bkmkend AAAAAAAHRT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_PSRC_SADDR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHRU}{\*\bkmkend AAAAAAAHRU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_PSRC_SADDR_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHRV}{\*\bkmkend AAAAAAAHRV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_PSRC_SADDR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHRW}{\*\bkmkend AAAAAAAHRW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_PSRC_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHRX}{\*\bkmkend AAAAAAAHRX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_PCNT_BCNT_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFF0000u){\*\bkmkstart AAAAAAAHRY}{\*\bkmkend AAAAAAAHRY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_PCNT_BCNT_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAHRZ}{\*\bkmkend AAAAAAAHRZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_PCNT_BCNT_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHSA}{\*\bkmkend AAAAAAAHSA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_PCNT_ACNT_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000FFFFu){\*\bkmkstart AAAAAAAHSB}{\*\bkmkend AAAAAAAHSB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_PCNT_ACNT_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHSC}{\*\bkmkend AAAAAAAHSC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_PCNT_ACNT_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHSD}{\*\bkmkend AAAAAAAHSD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_PCNT_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHSE}{\*\bkmkend AAAAAAAHSE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_PDST_DADDR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHSF}{\*\bkmkend AAAAAAAHSF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_PDST_DADDR_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHSG}{\*\bkmkend AAAAAAAHSG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_PDST_DADDR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHSH}{\*\bkmkend AAAAAAAHSH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_PDST_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHSI}{\*\bkmkend AAAAAAAHSI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_PBIDX_DBIDX_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFF0000u){\*\bkmkstart AAAAAAAHSJ}{\*\bkmkend AAAAAAAHSJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_PBIDX_DBIDX_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAHSK}{\*\bkmkend AAAAAAAHSK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_PBIDX_DBIDX_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHSL}{\*\bkmkend AAAAAAAHSL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_PBIDX_SBIDX_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000FFFFu){\*\bkmkstart AAAAAAAHSM}{\*\bkmkend AAAAAAAHSM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_PBIDX_SBIDX_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHSN}{\*\bkmkend AAAAAAAHSN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_PBIDX_SBIDX_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHSO}{\*\bkmkend AAAAAAAHSO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_PBIDX_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHSP}{\*\bkmkend AAAAAAAHSP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_PMPPRXY_PRIV_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAAHSQ}{\*\bkmkend AAAAAAAHSQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_PMPPRXY_PRIV_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAHSR}{\*\bkmkend AAAAAAAHSR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_PMPPRXY_PRIV_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHSS}{\*\bkmkend AAAAAAAHSS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_PMPPRXY_PRIV_USER}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHST}{\*\bkmkend AAAAAAAHST} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_PMPPRXY_PRIV_SUPERVISOR}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHSU}{\*\bkmkend AAAAAAAHSU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_PMPPRXY_PRIVID_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAAHSV}{\*\bkmkend AAAAAAAHSV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_PMPPRXY_PRIVID_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHSW}{\*\bkmkend AAAAAAAHSW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_PMPPRXY_PRIVID_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHSX}{\*\bkmkend AAAAAAAHSX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_PMPPRXY_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHSY}{\*\bkmkend AAAAAAAHSY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAOPT_TCCHEN_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAAHSZ}{\*\bkmkend AAAAAAAHSZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAOPT_TCCHEN_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAAHTA}{\*\bkmkend AAAAAAAHTA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAOPT_TCCHEN_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHTB}{\*\bkmkend AAAAAAAHTB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAOPT_TCCHEN_DISABLE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHTC}{\*\bkmkend AAAAAAAHTC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAOPT_TCCHEN_ENABLE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHTD}{\*\bkmkend AAAAAAAHTD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAOPT_TCINTEN_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAAHTE}{\*\bkmkend AAAAAAAHTE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAOPT_TCINTEN_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAAHTF}{\*\bkmkend AAAAAAAHTF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAOPT_TCINTEN_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHTG}{\*\bkmkend AAAAAAAHTG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAOPT_TCINTEN_DISABLE}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHTH}{\*\bkmkend AAAAAAAHTH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAOPT_TCINTEN_ENABLE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHTI}{\*\bkmkend AAAAAAAHTI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAOPT_TCC_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0003F000u){\*\bkmkstart AAAAAAAHTJ}{\*\bkmkend AAAAAAAHTJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAOPT_TCC_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAAHTK}{\*\bkmkend AAAAAAAHTK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAOPT_TCC_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHTL}{\*\bkmkend AAAAAAAHTL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAOPT_FWID_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000700u){\*\bkmkstart AAAAAAAHTM}{\*\bkmkend AAAAAAAHTM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAOPT_FWID_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAHTN}{\*\bkmkend AAAAAAAHTN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAOPT_FWID_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHTO}{\*\bkmkend AAAAAAAHTO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAOPT_FWID_8BIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHTP}{\*\bkmkend AAAAAAAHTP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAOPT_FWID_16BIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHTQ}{\*\bkmkend AAAAAAAHTQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAOPT_FWID_32BIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAHTR}{\*\bkmkend AAAAAAAHTR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAOPT_FWID_64BIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAHTS}{\*\bkmkend AAAAAAAHTS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAOPT_FWID_128BIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAHTT}{\*\bkmkend AAAAAAAHTT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAOPT_FWID_256BIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAAHTU}{\*\bkmkend AAAAAAAHTU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAOPT_PRI_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000070u){\*\bkmkstart AAAAAAAHTV}{\*\bkmkend AAAAAAAHTV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAOPT_PRI_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAHTW}{\*\bkmkend AAAAAAAHTW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAOPT_PRI_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHTX}{\*\bkmkend AAAAAAAHTX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAOPT_DAM_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAHTY}{\*\bkmkend AAAAAAAHTY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAOPT_DAM_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHTZ}{\*\bkmkend AAAAAAAHTZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAOPT_DAM_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHUA}{\*\bkmkend AAAAAAAHUA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAOPT_DAM_INCR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHUB}{\*\bkmkend AAAAAAAHUB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAOPT_DAM_FIFO}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHUC}{\*\bkmkend AAAAAAAHUC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAOPT_SAM_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHUD}{\*\bkmkend AAAAAAAHUD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAOPT_SAM_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHUE}{\*\bkmkend AAAAAAAHUE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAOPT_SAM_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHUF}{\*\bkmkend AAAAAAAHUF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAOPT_SAM_INCR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHUG}{\*\bkmkend AAAAAAAHUG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAOPT_SAM_FIFO}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHUH}{\*\bkmkend AAAAAAAHUH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAOPT_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHUI}{\*\bkmkend AAAAAAAHUI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SASRC_SADDR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHUJ}{\*\bkmkend AAAAAAAHUJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SASRC_SADDR_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHUK}{\*\bkmkend AAAAAAAHUK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SASRC_SADDR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHUL}{\*\bkmkend AAAAAAAHUL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SASRC_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHUM}{\*\bkmkend AAAAAAAHUM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SACNT_BCNT_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFF0000u){\*\bkmkstart AAAAAAAHUN}{\*\bkmkend AAAAAAAHUN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SACNT_BCNT_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAHUO}{\*\bkmkend AAAAAAAHUO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SACNT_BCNT_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHUP}{\*\bkmkend AAAAAAAHUP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SACNT_ACNT_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000FFFFu){\*\bkmkstart AAAAAAAHUQ}{\*\bkmkend AAAAAAAHUQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SACNT_ACNT_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHUR}{\*\bkmkend AAAAAAAHUR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SACNT_ACNT_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHUS}{\*\bkmkend AAAAAAAHUS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SACNT_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHUT}{\*\bkmkend AAAAAAAHUT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SADST_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHUU}{\*\bkmkend AAAAAAAHUU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SABIDX_DBIDX_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFF0000u){\*\bkmkstart AAAAAAAHUV}{\*\bkmkend AAAAAAAHUV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SABIDX_DBIDX_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAHUW}{\*\bkmkend AAAAAAAHUW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SABIDX_DBIDX_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHUX}{\*\bkmkend AAAAAAAHUX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SABIDX_SBIDX_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000FFFFu){\*\bkmkstart AAAAAAAHUY}{\*\bkmkend AAAAAAAHUY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SABIDX_SBIDX_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHUZ}{\*\bkmkend AAAAAAAHUZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SABIDX_SBIDX_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHVA}{\*\bkmkend AAAAAAAHVA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SABIDX_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHVB}{\*\bkmkend AAAAAAAHVB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAMPPRXY_PRIV_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAAHVC}{\*\bkmkend AAAAAAAHVC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAMPPRXY_PRIV_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAHVD}{\*\bkmkend AAAAAAAHVD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAMPPRXY_PRIV_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHVE}{\*\bkmkend AAAAAAAHVE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAMPPRXY_PRIV_USER}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHVF}{\*\bkmkend AAAAAAAHVF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAMPPRXY_PRIV_SUPERVISOR}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHVG}{\*\bkmkend AAAAAAAHVG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAMPPRXY_PRIVID_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAAHVH}{\*\bkmkend AAAAAAAHVH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAMPPRXY_PRIVID_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHVI}{\*\bkmkend AAAAAAAHVI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAMPPRXY_PRIVID_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHVJ}{\*\bkmkend AAAAAAAHVJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SAMPPRXY_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHVK}{\*\bkmkend AAAAAAAHVK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SACNTRLD_ACNTRLD_MASK}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x0000FFFFu){\*\bkmkstart AAAAAAAHVL}{\*\bkmkend AAAAAAAHVL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SACNTRLD_ACNTRLD_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHVM}{\*\bkmkend AAAAAAAHVM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SACNTRLD_ACNTRLD_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHVN}{\*\bkmkend AAAAAAAHVN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SACNTRLD_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHVO}{\*\bkmkend AAAAAAAHVO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SASRCBREF_SADDRBREFG_MASK}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHVP}{\*\bkmkend AAAAAAAHVP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SASRCBREF_SADDRBREFG_SHIFT}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHVQ}{\*\bkmkend AAAAAAAHVQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SASRCBREF_SADDRBREFG_RESETVAL}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHVR}{\*\bkmkend AAAAAAAHVR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SASRCBREF_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHVS}{\*\bkmkend AAAAAAAHVS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_SADSTBREF_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHVT}{\*\bkmkend AAAAAAAHVT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFCNTRLD_ACNTRLD_MASK}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x0000FFFFu){\*\bkmkstart AAAAAAAHVU}{\*\bkmkend AAAAAAAHVU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFCNTRLD_ACNTRLD_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHVV}{\*\bkmkend AAAAAAAHVV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFCNTRLD_ACNTRLD_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHVW}{\*\bkmkend AAAAAAAHVW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFCNTRLD_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHVX}{\*\bkmkend AAAAAAAHVX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFSRCBREF_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHVY}{\*\bkmkend AAAAAAAHVY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFDSTBREF_DADDRBREF_MASK}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHVZ}{\*\bkmkend AAAAAAAHVZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFDSTBREF_DADDRBREF_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHWA}{\*\bkmkend AAAAAAAHWA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFDSTBREF_DADDRBREF_RESETVAL}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHWB}{\*\bkmkend AAAAAAAHWB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFDSTBREF_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHWC}{\*\bkmkend AAAAAAAHWC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFOPT_TCCHEN_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00400000u){\*\bkmkstart AAAAAAAHWD}{\*\bkmkend AAAAAAAHWD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFOPT_TCCHEN_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000016u){\*\bkmkstart AAAAAAAHWE}{\*\bkmkend AAAAAAAHWE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFOPT_TCCHEN_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHWF}{\*\bkmkend AAAAAAAHWF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFOPT_TCCHEN_DISABLE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHWG}{\*\bkmkend AAAAAAAHWG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFOPT_TCCHEN_ENABLE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHWH}{\*\bkmkend AAAAAAAHWH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFOPT_TCINTEN_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00100000u){\*\bkmkstart AAAAAAAHWI}{\*\bkmkend AAAAAAAHWI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFOPT_TCINTEN_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000014u){\*\bkmkstart AAAAAAAHWJ}{\*\bkmkend AAAAAAAHWJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFOPT_TCINTEN_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHWK}{\*\bkmkend AAAAAAAHWK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFOPT_TCINTEN_DISABLE}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHWL}{\*\bkmkend AAAAAAAHWL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFOPT_TCINTEN_ENABLE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHWM}{\*\bkmkend AAAAAAAHWM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFOPT_TCC_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0003F000u){\*\bkmkstart AAAAAAAHWN}{\*\bkmkend AAAAAAAHWN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFOPT_TCC_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Cu){\*\bkmkstart AAAAAAAHWO}{\*\bkmkend AAAAAAAHWO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFOPT_TCC_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHWP}{\*\bkmkend AAAAAAAHWP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFOPT_FWID_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000700u){\*\bkmkstart AAAAAAAHWQ}{\*\bkmkend AAAAAAAHWQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFOPT_FWID_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAHWR}{\*\bkmkend AAAAAAAHWR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFOPT_FWID_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHWS}{\*\bkmkend AAAAAAAHWS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFOPT_FWID_8BIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHWT}{\*\bkmkend AAAAAAAHWT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFOPT_FWID_16BIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHWU}{\*\bkmkend AAAAAAAHWU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFOPT_FWID_32BIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAHWV}{\*\bkmkend AAAAAAAHWV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFOPT_FWID_64BIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000003u){\*\bkmkstart AAAAAAAHWW}{\*\bkmkend AAAAAAAHWW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFOPT_FWID_128BIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAHWX}{\*\bkmkend AAAAAAAHWX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFOPT_FWID_256BIT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000005u){\*\bkmkstart AAAAAAAHWY}{\*\bkmkend AAAAAAAHWY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFOPT_PRI_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000070u){\*\bkmkstart AAAAAAAHWZ}{\*\bkmkend AAAAAAAHWZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFOPT_PRI_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000004u){\*\bkmkstart AAAAAAAHXA}{\*\bkmkend AAAAAAAHXA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFOPT_PRI_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHXB}{\*\bkmkend AAAAAAAHXB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFOPT_DAM_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000002u){\*\bkmkstart AAAAAAAHXC}{\*\bkmkend AAAAAAAHXC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFOPT_DAM_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHXD}{\*\bkmkend AAAAAAAHXD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFOPT_DAM_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHXE}{\*\bkmkend AAAAAAAHXE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFOPT_DAM_INCR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHXF}{\*\bkmkend AAAAAAAHXF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFOPT_DAM_FIFO}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHXG}{\*\bkmkend AAAAAAAHXG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFOPT_SAM_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHXH}{\*\bkmkend AAAAAAAHXH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFOPT_SAM_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHXI}{\*\bkmkend AAAAAAAHXI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFOPT_SAM_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHXJ}{\*\bkmkend AAAAAAAHXJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFOPT_SAM_INCR}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHXK}{\*\bkmkend AAAAAAAHXK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFOPT_SAM_FIFO}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHXL}{\*\bkmkend AAAAAAAHXL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFOPT_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHXM}{\*\bkmkend AAAAAAAHXM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFSRC_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHXN}{\*\bkmkend AAAAAAAHXN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFCNT_BCNT_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFF0000u){\*\bkmkstart AAAAAAAHXO}{\*\bkmkend AAAAAAAHXO} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFCNT_BCNT_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAHXP}{\*\bkmkend AAAAAAAHXP} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFCNT_BCNT_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHXQ}{\*\bkmkend AAAAAAAHXQ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFCNT_ACNT_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000FFFFu){\*\bkmkstart AAAAAAAHXR}{\*\bkmkend AAAAAAAHXR} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFCNT_ACNT_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHXS}{\*\bkmkend AAAAAAAHXS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFCNT_ACNT_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHXT}{\*\bkmkend AAAAAAAHXT} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFCNT_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHXU}{\*\bkmkend AAAAAAAHXU} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFDST_DADDR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu){\*\bkmkstart AAAAAAAHXV}{\*\bkmkend AAAAAAAHXV} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFDST_DADDR_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHXW}{\*\bkmkend AAAAAAAHXW} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFDST_DADDR_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHXX}{\*\bkmkend AAAAAAAHXX} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFDST_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHXY}{\*\bkmkend AAAAAAAHXY} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFBIDX_DBIDX_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0xFFFF0000u){\*\bkmkstart AAAAAAAHXZ}{\*\bkmkend AAAAAAAHXZ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFBIDX_DBIDX_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000010u){\*\bkmkstart AAAAAAAHYA}{\*\bkmkend AAAAAAAHYA} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFBIDX_DBIDX_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHYB}{\*\bkmkend AAAAAAAHYB} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFBIDX_SBIDX_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000FFFFu){\*\bkmkstart AAAAAAAHYC}{\*\bkmkend AAAAAAAHYC} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFBIDX_SBIDX_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHYD}{\*\bkmkend AAAAAAAHYD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFBIDX_SBIDX_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHYE}{\*\bkmkend AAAAAAAHYE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFBIDX_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHYF}{\*\bkmkend AAAAAAAHYF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFMPPRXY_PRIV_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000100u){\*\bkmkstart AAAAAAAHYG}{\*\bkmkend AAAAAAAHYG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFMPPRXY_PRIV_SHIFT}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000008u){\*\bkmkstart AAAAAAAHYH}{\*\bkmkend AAAAAAAHYH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFMPPRXY_PRIV_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHYI}{\*\bkmkend AAAAAAAHYI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFMPPRXY_PRIV_USER}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHYJ}{\*\bkmkend AAAAAAAHYJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFMPPRXY_PRIV_SUPERVISOR}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000001u){\*\bkmkstart AAAAAAAHYK}{\*\bkmkend AAAAAAAHYK} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFMPPRXY_PRIVID_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x0000000Fu){\*\bkmkstart AAAAAAAHYL}{\*\bkmkend AAAAAAAHYL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFMPPRXY_PRIVID_SHIFT}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHYM}{\*\bkmkend AAAAAAAHYM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFMPPRXY_PRIVID_RESETVAL}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHYN}{\*\bkmkend AAAAAAAHYN} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_TCRL_DFMPPRXY_RESETVAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (0x00000000u){\*\bkmkstart AAAAAAAHYO}{\*\bkmkend AAAAAAAHYO} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 EDMA3 Transfer Controller Register Desciption. +\par This file contains the register layer for the EDMA3 Transfer Controller. +\par (C) Copyright 2006, Texas Instruments, Inc +\par }\pard\plain \ltrpar\s5\qj \li0\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Version: +\par }\pard\plain \ltrpar\s43\ql \li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 1.0 Anuj Aggarwal - Created +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 +\ltrch\fcs0 \fs24\insrsid7370340 +\par \sect }\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 +\ltrch\fcs0 \b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_rm.h File Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc { +\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \tcl2{\*\bkmkstart _Toc211937582}edma3_rm.h{\*\bkmkend _Toc211937582}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn +\pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 edma3_rm.h}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAHYP}{\*\bkmkend AAAAAAAHYP}EDMA3 Controller Resource Manager Interface. +\par }\pard\plain \ltrpar\s18\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af2 +\ltrch\fcs0 \f2\insrsid7370340 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Data Structures +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_GblErrCallbackParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Global Error Callback parameters. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Handle to a Resource. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_GblConfigParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_InstanceInitConfig}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Init-time Region Specific Configuration structure for EDMA3 RM, to provide region specific Information. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Param}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Used to Initialize the Resource Manager Instance. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_MiscParam}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Used to specify the miscellaneous options during Resource Manager Initialization. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ParamentryRegs}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 EDMA3 PaRAM Set. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_PaRAMRegs}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 EDMA3 PaRAM Set in User Configurable format. +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Defines +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define } +{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_RES_ANY}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (1010u){\*\bkmkstart AAAAAAAHYQ}{\*\bkmkend AAAAAAAHYQ} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Used to specify any available Resource Id (}{\rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\insrsid7370340 EDMA3_RM_ResDesc.resId}{\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 ). +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define } +{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_BASE}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (-155) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_OBJ_NOT_DELETED}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (EDMA3_RM_E_BASE) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_OBJ_NOT_CLOSED}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (EDMA3_RM_E_BASE-1) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_OBJ_NOT_OPENED}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (EDMA3_RM_E_BASE-2) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_INVALID_PARAM}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (EDMA3_RM_E_BASE-3) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_RES_ALREADY_FREE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (EDMA3_RM_E_BASE-4) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_RES_NOT_OWNED}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (EDMA3_RM_E_BASE-5) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (EDMA3_RM_E_BASE-6) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_ALL_RES_NOT_AVAILABLE}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (EDMA3_RM_E_BASE-7) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_INVALID_STATE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (EDMA3_RM_E_BASE-8) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_MAX_RM_INST_OPENED}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (EDMA3_RM_E_BASE-9) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_RM_MASTER_ALREADY_EXISTS}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (EDMA3_RM_E_BASE-10) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (EDMA3_RM_E_BASE-11) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_SEMAPHORE}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (EDMA3_RM_E_BASE-12) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_FEATURE_UNSUPPORTED}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (EDMA3_RM_E_BASE-13) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_RES_NOT_ALLOCATED}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (EDMA3_RM_E_BASE-14) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_DMA_CHANNEL_ANY}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (1011u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_QDMA_CHANNEL_ANY}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (1012u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_TCC_ANY}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ (1013u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_PARAM_ANY}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 \~ (1014u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_CH_NO_PARAM_MAP}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (1015u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_CH_NO_TCC_MAP}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (1016u) +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Typedefs +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +typedef void(* }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_GblErrCallback}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 )(}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_GlobalError}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 deviceStatus, unsigned int instanceId, void *gblerrData) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Global Error callback - caters to module events like bus error etc which are not channel specific. Runs in ISR context. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +typedef void(* }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_TccCallback}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 )(unsigned int tcc, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_TccStatus}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 status, void *appData) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 TCC callback - caters to channel-specific events like "Event Miss Error" or "Transfer Complete". Runs in ISR context. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +typedef unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_RegionId}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 EDMA3 Region Id. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +typedef unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_EventQueue}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 EDMA3 Event Queue assignment. +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Enumerations +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_TccStatus}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_XFER_COMPLETE}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 1, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_CC_DMA_EVT_MISS}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 2, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_CC_QDMA_EVT_MISS}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 = 3 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 This enum defines the channel specific status codes of an EDMA3 transfer. It is returned while calling the channel specific callback function to tell the status. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_GlobalError}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_CC_QUE_THRES_EXCEED}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 + = 1, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_CC_TCC}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 2, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_TC_MEM_LOCATION_READ_ERROR}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 = 3, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_TC_MEM_LOCATION_WRITE_ERROR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 4, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_TC_INVALID_ADDR}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 5, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_E_TC_TR_ERROR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 6 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 This enum defines the global (not specific to any channel) error codes of completion of an EDMA3 transfer. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResType}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_RES_DMA_CHANNEL}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 1, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_RES_QDMA_CHANNEL}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 2, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_RES_TCC}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 3, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_RES_PARAM_SET}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 4 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 EDMA3 Resource Type. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_0}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 + = 0, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_1}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_2}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_3}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_4}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_5}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_6}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_7}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_8}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_9}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_10 +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_11}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_HW_CHANNEL_EVENT_12}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_13}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_14}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_15}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_16}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_17}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 +\ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_18}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_19}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_20}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_21}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_22}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_23}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_24}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_25}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_26}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_27}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_28}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_29}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_30}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_HW_CHANNEL_EVENT_31}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_32}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_33}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_34}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_35}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_36}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 +\ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_37}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_38}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_39}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_40}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_41}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_42}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_43}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_44}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_45}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_46}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_47}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_48}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_49}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_HW_CHANNEL_EVENT_50}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_51}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_52}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_53}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_54}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_55}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 +\ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_56}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_57}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_58}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_59}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_60}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_61}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_62}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_63}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 DMA Channels assigned to different Hardware Events. They should be used while requesting a specific DMA channel. One possible usage is to maintain a SoC specific file, which will cont +ain the mapping of these hardware events to the respective peripherals for better understanding and lesser probability of errors. Also, if any event associated with a particular peripheral gets changed, only that SoC specific file needs to be changed. + +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_QdmaTrigWord}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_QDMA_TRIG_OPT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 0, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_QDMA_TRIG_SRC}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 1, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_QDMA_TRIG_ACNT_BCNT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 + = 2, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_QDMA_TRIG_DST}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 3, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_QDMA_TRIG_SRC_DST_BIDX}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 = 4, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_QDMA_TRIG_LINK_BCNTRLD}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 5, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_QDMA_TRIG_SRC_DST_CIDX}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 6, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_QDMA_TRIG_CCNT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 7, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_QDMA_TRIG_DEFAULT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 7 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 QDMA Trigger Word. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Cntrlr_PhyAddr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_CC_PHY_ADDR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 0, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_TC0_PHY_ADDR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_TC1_PHY_ADDR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_TC2_PHY_ADDR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_TC3_PHY_ADDR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_TC4_PHY_ADDR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_TC5_PHY_ADDR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_TC6_PHY_ADDR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_TC7_PHY_ADDR}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 CC/TC Physical Address. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_IoctlCmd}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_IOCTL_MIN_IOCTL}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 0, }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_IOCTL_SET_PARAM_CLEAR_OPTION}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_IOCTL_GET_PARAM_CLEAR_OPTION}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_IOCTL_SET_GBL_REG_MODIFY_OPTION}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_IOCTL_GET_GBL_REG_MODIFY_OPTION}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 , }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_IOCTL_MAX_IOCTL}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 EDMA3 Resource Manager IOCTL commands. +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Functions +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_registerTccCb}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *channelObj, unsigned int tcc, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 EDMA3_RM_TccCallback}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 tccCb, void *cbData) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Register Interrupt / Completion Handler for a given TCC. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_unregisterTccCb}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *channelObj) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Unregister the previously registered callback function against a DMA/QDMA channel. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_create}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (unsigned int phyCtrllerInstId, const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 EDMA3_RM_GblConfigParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *gblCfgParams, const void *miscParam) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Create EDMA3 Resource Manager Object. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_delete}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (unsigned int phyCtrllerInstId, const void *param) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Delete EDMA3 Resource Manager Object. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Handle}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_open}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (unsigned int phyCtrllerInstId, const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 EDMA3_RM_Param}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *initParam, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *errorCode) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Open EDMA3 Resource Manager Instance. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_close}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, const void *param) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Close EDMA3 Resource Manager Instance. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_allocResource}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *resObj) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 This API is used to allocate specified EDMA3 Resources like DMA/QDMA channel, PaRAM Set or TCC. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_freeResource}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *resObj) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 This API is used to free previously allocated EDMA3 Resources like DMA/QDMA channel, PaRAM Set or TCC. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_allocContiguousResource}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Handle}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *firstResIdObj, unsigned int numResources) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Allocate a contiguous region of specified EDMA3 Resource like DMA channel, QDMA channel, PaRAM Set or TCC. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_freeContiguousResource}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Handle}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *firstResIdObj, unsigned int numResources) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Free a contiguous region of specified EDMA3 Resource like DMA channel, QDMA channel, PaRAM Set or TCC, previously allocated. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_allocLogicalChannel}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Handle}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *lChObj, unsigned int *pParam, unsigned int *pTcc) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Request a DMA/QDMA/Link channel. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_freeLogicalChannel}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Handle}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *lChObj) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 This API is used to free the specified channel (DMA/QDMA/Link) and its associated resources (PaRAM Set, TCC etc). +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_mapEdmaChannel}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle} +{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, unsigned int channelId, unsigned int paRAMId) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Bind the resources DMA Channel and PaRAM Set. Both the DMA channel and the PaRAM set should be previously allocated. If they are not, this API will result in error. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_mapQdmaChannel}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle} +{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, unsigned int channelId, unsigned int paRAMId, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_QdmaTrigWord}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 trigWord) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Bind the resources QDMA Channel and PaRAM Set. Also, Set the trigger word fo +r the QDMA channel. Both the QDMA channel and the PaRAM set should be previously allocated. If they are not, this API will result in error. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_setCCRegister}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, unsigned int regOffset, unsigned int newRegValue) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Set the Channel Controller (CC) Register value. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_getCCRegister}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, unsigned int regOffset, unsigned int *regValue) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Get the Channel Controller (CC) Register value. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_waitAndClearTcc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, unsigned int tccNo) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Wait for a transfer completion interrupt to occur and clear it. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_checkAndClearTcc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Handle}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, unsigned int tccNo, unsigned short *tccStatus) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Returns the status of a previously initiated transfer. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_setPaRAM}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *lChObj, const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_PaRAMRegs}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *newPaRAM) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Copy the user specified PaRAM Set onto the PaRAM Set associated with the logical channel (DMA/QDMA/Link). +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_getPaRAM}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *lChObj, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_PaRAMRegs} +{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *currPaRAM) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Retrieve existing PaRAM set associated with specified logical channel (DMA/QDMA/Link). +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_getPaRAMPhyAddr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *lChObj, unsigned int *paramPhyAddr) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Get the PaRAM Set Physical Address associated with a logical channel. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_getBaseAddress}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle} +{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Cntrlr_PhyAddr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 controllerId, unsigned int *phyAddress) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Get the Channel Controller or Transfer Controller (n) Physical Address. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_getGblConfigParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (unsigned int phyCtrllerInstId, }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_GblConfigParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *gblCfgParams) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Get the SoC specific configuration structure for the EDMA3 Hardware. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_getInstanceInitCfg}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Handle}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_InstanceInitConfig}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *instanceInitConfig) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Get the RM Instance specific configuration structure for different EDMA3 resources' usage (owned resources, reserved resources etc). +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Ioctl}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_IoctlCmd}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 cmd, void *cmdArg, void *param) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 +\i\insrsid7370340 EDMA3 Resource Manager IOCTL. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +EDMA3 Controller Resource Manager Interface. +\par This file contains Application Interface for the EDMA3 Controller Resource Manager. +\par (C) Copyright 2006, Texas Instruments, Inc +\par }\pard\plain \ltrpar\s5\qj \li0\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Version: +\par }\pard\plain \ltrpar\s43\ql \li360\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +0.0.1 Purushotam Kumar - Created 0.1.0 Joseph Fernandez - Made generic +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Added documentation +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Moved SoC specific defines to SoC specific header. 0.2.0 Anuj Aggarwal - Modified it for EDMA3 package +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Added multiple instances capability 0.2.1 Anuj Aggarwal - Modified it for more run time configuration. +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Made EDMA3 package OS independent. 0.2.2 Anuj Aggarwal - Critical section handling code modification. Uses semaphore and interrupts disabling mechanism for resource sharing. 0.3.0 Anuj Aggarwal - Renamed EDMA3_DVR to EDMA3_DRV +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 IPR bit clearing in RM ISR issue fixed. +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Sample application made generic 0.3.1 Anuj Aggarwal - Added DMA/QDMA Channel to TCC mapping, to fix QDMA missed event issue. 0.3.2 Anuj Aggarwal - Added support for POLL mode +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Added a new API to modify the CC Register. 1.0.0 Anuj Aggarwa +l - Fixed resource allocation related bugs. 1.0.0.1 Anuj Aggarwal - Fixed spurious missed event generation related bug. 1.0.0.2 Anuj Aggarwal - Made the EDMA3 package RTSC compliant. 1.0.0.3 Anuj Aggarwal - Changed the directory structure as per RTSC stan +d +ard. 1.01.00.01 Anuj Aggarwal - a) Added new APIs to allocate logical channels b) Created EDMA3 config files for different platforms c) Misc changes 1.02.00.01 Anuj Aggarwal - a) Added DM6467 support b) Fixed some MRs 1.03.00.01 Anuj Aggarwal - a) Added n +on-RTSC PJT files b) IOCTL Interface added. c) Fixed some MRs. 1.04 Anuj Aggarwal - a) Added new IOCTLs and APIs. b) Number of maximum Resource Manager Instances is configurable. c) Header files modified to have extern "C" declarations. +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 +\par \sect }\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_rm_gbl_data.c File Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \tcl2 +{\*\bkmkstart _Toc211937583}edma3_rm_gbl_data.c{\*\bkmkend _Toc211937583}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 +\v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 edma3_rm_gbl_data.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAHYR} +{\*\bkmkend AAAAAAAHYR}Source file for the Resource Manager, for internal data structures. +\par }\pard\plain \ltrpar\s18\ql \li0\ri0\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 +#include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Defines +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define } +{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 MAX_EDMA3_RM_INSTANCES}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (8u) +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Variables +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +const unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_MAX_RM_INSTANCES}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 8u +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_InstanceInitConfig}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid7370340 userInstInitConfigArray}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [EDMA3_MAX_EDMA3_INSTANCES][MAX_EDMA3_RM_INSTANCES] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Region Specific Configuration structure for EDMA3 controller, to provide region specific Information. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Instance}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 resMgrInstanceArray}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [EDMA3_MAX_EDMA3_INSTANCES][MAX_EDMA3_RM_INSTANCES] +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Instance}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 * }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 resMgrInstance}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Instance}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *)}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +resMgrInstanceArray}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_InstanceInitConfig}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 * }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid7370340 userInitConfig}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_InstanceInitConfig}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *)}{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid7370340 userInstInitConfigArray}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Region Specific Configuration structure for EDMA3 controller, to provide region specific Information. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Instance}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 * }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 ptrRMIArray}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Instance}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *)}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 resMgrInstanceArray}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAHYS}{\*\bkmkend AAAAAAAHYS} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_InstanceInitConfig}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 * }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid7370340 ptrInitCfgArray}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_InstanceInitConfig}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *)}{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid7370340 userInstInitConfigArray}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAHYT}{\*\bkmkend AAAAAAAHYT} +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 Source file for the Resource Manager, for internal data structures. +\par (C) Copyright 2006, Texas Instruments, Inc +\par }\pard\plain \ltrpar\s5\qj \li0\ri0\sb90\sa30\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel4\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Version: +\par }\pard\plain \ltrpar\s43\ql \li360\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 0.1.0 Anuj Aggarwal - Created +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Define Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 MAX_EDMA3_RM_INSTANCES\:edma3_rm_gbl_data.c}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 edma3_rm_gbl_data.c\:MAX_EDMA3_RM_INSTANCES}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define MAX_EDMA3_RM_INSTANCES\~ (8u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAHYU}{\*\bkmkend AAAAAAAHYU}Maximum Resource Manager Instances supported by the EDMA3 Package. USE THE SAME VALUE FOR BOTH THE DEFINE AND CONST UNSIGNED INT BELOW. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Variable Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 EDMA3_MAX_RM_INSTANCES\:edma3_rm_gbl_data.c}}}\sectd \linex0\sectdefaultcl\sftnbj +{\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 edma3_rm_gbl_data.c\:EDMA3_MAX_RM_INSTANCES}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +const unsigned int EDMA3_MAX_RM_INSTANCES = 8u +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAHYV}{\*\bkmkend AAAAAAAHYV}Maximum Resource Manager Instances supported by the EDMA3 Package. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Referenced by EDMA3_RM_create(), EDMA3_RM_getInstanceInitCfg(), EDMA3_RM_open(), edma3CCErrHandler(), and edma3TCErrHandler(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 resMgrInstance\:edma3_rm_gbl_data.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_rm_gbl_data.c\:resMgrInstance}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_Instance* resMgrInstance = (EDMA3_RM_Instance *)resMgrInstanceArray +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAHYW}{\*\bkmkend AAAAAAAHYW}Handles of EDMA3 Resource Manager Instances. +\par Used to maintain information of the EDMA3 RM Instances for each HW controller. There could be a maximum of EDMA3_MAX_RM_INSTANCES instances per EDMA3 HW. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 resMgrInstanceArray\:edma3_rm_gbl_data.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_rm_gbl_data.c\:resMgrInstanceArray}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 EDMA3_RM_ +Instance resMgrInstanceArray[EDMA3_MAX_EDMA3_INSTANCES][MAX_EDMA3_RM_INSTANCES] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAHYX}{\*\bkmkend AAAAAAAHYX}Handles of EDMA3 Resource Manager Instances. +\par Used to maintain information of the EDMA3 RM Instances for each HW controller. There could be a maximum of EDMA3_MAX_RM_INSTANCES instances per EDMA3 HW. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 userInitConfig\:edma3_rm_gbl_data.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_rm_gbl_data.c\:userInitConfig}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_InstanceInitConfig* userInitConfig = (EDMA3_RM_InstanceInitConfig *)userInstInitConfigArray +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAHYY}{\*\bkmkend AAAAAAAHYY}Region Specific Configuration structure for EDMA3 controller, to provide region specific Information. +\par This configuration info can also be provided by the user at run-time, while calling EDMA3_RM_open (). If not provided at run-time, this info will be taken from the config file "edma3__cfg.c", for the specified platform. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 userInstInitConfigArray\:edma3_rm_gbl_data.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3_rm_gbl_data.c\:userInstInitConfigArray}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_InstanceInitConfig userInstInitConfigArray[EDMA3_MAX_EDMA3_INSTANCES][MAX_EDMA3_RM_INSTANCES] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAHYZ}{\*\bkmkend AAAAAAAHYZ}Region Specific Configuration structure for EDMA3 controller, to provide region specific Information. +\par This configuration info can also be provided by the user at run-time, while calling EDMA3_RM_open (). If not provided at run-time, this info will be taken from the config file "edma3__cfg.c", for the specified platform. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 +\ltrch\fcs0 \fs24\insrsid7370340 \sect }\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 +\rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.c File Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 +{\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc { +\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \tcl2{\*\bkmkstart _Toc211937584}edma3resmgr.c{\*\bkmkend _Toc211937584}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn +\pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 edma3resmgr.c}}}\sectd +\linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAHZA}{\*\bkmkend AAAAAAAHZA}EDMA3 Controller Resource Manager Interface Implementation. +\par }\pard\plain \ltrpar\s18\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af2 +\ltrch\fcs0 \f2\insrsid7370340 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Defines +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define } +{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_RES_CLEAR_ERROR_STATUS_FOR_ALL_CHANNELS}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (TRUE) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 EDMA3 Resource Manager behaviour of clearing CC ERROR interrupts. This macro controls the driver to enable/disable clearing of error status of all channels. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define } +{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_COMPL_HANDLER_RETRY_COUNT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (10u){\*\bkmkstart AAAAAAAHZB}{\*\bkmkend AAAAAAAHZB} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 EDMA3 Resource Manager retry count to check the pending interrupts inside ISR. This macro controls the driver to check the pending interrupt for 'n' number of times. Minumum value is 1. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define } +{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_CCERR_HANDLER_RETRY_COUNT}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (10u){\*\bkmkstart AAAAAAAHZC}{\*\bkmkend AAAAAAAHZC} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 EDMA3 Resource Manager retry count to check the pending CC Error Interrupt inside ISR This macro controls the driver to check the pending CC Error interrupt for 'n' number of times. Minumum value is 1. + +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Functions +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 void }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 lisrEdma3ComplHandler0}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (unsigned int arg) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 void }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 lisrEdma3CCErrHandler0}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 (unsigned int arg) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 void }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 lisrEdma3TC0ErrHandler0}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 (unsigned int arg) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 void }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 lisrEdma3TC1ErrHandler0}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 (unsigned int arg){\*\bkmkstart AAAAAAAHZD}{\*\bkmkend AAAAAAAHZD} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 void }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 lisrEdma3TC2ErrHandler0}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 (unsigned int arg){\*\bkmkstart AAAAAAAHZE}{\*\bkmkend AAAAAAAHZE} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 void }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 lisrEdma3TC3ErrHandler0}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 (unsigned int arg){\*\bkmkstart AAAAAAAHZF}{\*\bkmkend AAAAAAAHZF} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 void }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 lisrEdma3TC4ErrHandler0}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 (unsigned int arg){\*\bkmkstart AAAAAAAHZG}{\*\bkmkend AAAAAAAHZG} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 void }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 lisrEdma3TC5ErrHandler0}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 (unsigned int arg){\*\bkmkstart AAAAAAAHZH}{\*\bkmkend AAAAAAAHZH} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 void }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 lisrEdma3TC6ErrHandler0}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 (unsigned int arg){\*\bkmkstart AAAAAAAHZI}{\*\bkmkend AAAAAAAHZI} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 void }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 lisrEdma3TC7ErrHandler0}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 (unsigned int arg){\*\bkmkstart AAAAAAAHZJ}{\*\bkmkend AAAAAAAHZJ} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 static void }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 edma3ComplHandler}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 (const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Obj}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *rmObj) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Interrupt handler for successful transfer completion. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +static void }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 edma3CCErrHandler}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Obj}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *rmObj) + +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Interrupt handler for Channel Controller Error. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +static void }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 edma3TCErrHandler}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Obj}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 + *rmObj, unsigned int tcNum) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Interrupt handler for Transfer Controller Error. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 void }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 edma3MemSet}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (void *dst, unsigned char data, unsigned int len) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 void }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 edma3MemCpy}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 (void *dst, const void *src, unsigned int len) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 static void }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 edma3GlobalRegionInit}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 (unsigned int phyCtrllerInstId) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 static void }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 edma3ShadowRegionInit}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 (const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Instance}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *pRMInstance) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 static int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 findBitInWord}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 (int source, unsigned int start, unsigned short bit) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 static int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 findBit}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResType}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 resType, unsigned int start, unsigned int end, unsigned short bit) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 static }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 allocAnyContigRes}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResType}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 + resType, unsigned int numResources, unsigned int *positionRes) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 static }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 gblChngAllocContigRes}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Instance}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 + *rmInstance, const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *firstResIdObj, unsigned int numResources) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 EDMA3_RM_create}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (unsigned int phyCtrllerInstId, const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_GblConfigParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 + *gblCfgParams, const void *miscParam) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Create EDMA3 Resource Manager Object. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_delete}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (unsigned int phyCtrllerInstId, const void *param) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Delete EDMA3 Resource Manager Object. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Handle}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_open}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (unsigned int phyCtrllerInstId, const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 EDMA3_RM_Param}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *initParam, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *errorCode) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Open EDMA3 Resource Manager Instance. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_close}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, const void *param) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Close EDMA3 Resource Manager Instance. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_allocResource}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *resObj) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 This API is used to allocate specified EDMA3 Resources like DMA/QDMA channel, PaRAM Set or TCC. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_freeResource}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *resObj) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 This API is used to free previously allocated EDMA3 Resources like DMA/QDMA channel, PaRAM Set or TCC. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_allocLogicalChannel}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Handle}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *lChObj, unsigned int *pParam, unsigned int *pTcc) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Request a DMA/QDMA/Link channel. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_freeLogicalChannel}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Handle}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *lChObj) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 This API is used to free the specified channel (DMA/QDMA/Link) and its associated resources (PaRAM Set, TCC etc). +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_mapEdmaChannel}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle} +{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, unsigned int channelId, unsigned int paRAMId) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Bind the resources DMA Channel and PaRAM Set. Both the DMA channel and the PaRAM set should be previously allocated. If they are not, this API will result in error. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_mapQdmaChannel}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle} +{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, unsigned int channelId, unsigned int paRAMId, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_QdmaTrigWord}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 trigWord) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 +Bind the resources QDMA Channel and PaRAM Set. Also, Set the trigger word for the QDMA channel. Both the QDMA channel and the PaRAM set should be previously allocated. If they are not, this API will result in error. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 E +DMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_registerTccCb}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *channelObj, unsigned int tcc, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 EDMA3_RM_TccCallback}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 tccCb, void *cbData) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Register Interrupt / Completion Handler for a given TCC. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_unregisterTccCb}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *channelObj) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Unregister the previously registered callback function against a DMA/QDMA channel. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_allocContiguousResource}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Handle}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *firstResIdObj, unsigned int numResources) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Allocate a contiguous region of specified EDMA3 Resource like DMA channel, QDMA channel, PaRAM Set or TCC. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_freeContiguousResource}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Handle}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *firstResIdObj, unsigned int numResources) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Free a contiguous region of specified EDMA3 Resource like DMA channel, QDMA channel, PaRAM Set or TCC, previously allocated. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_setCCRegister}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, unsigned int regOffset, unsigned int newRegValue) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Set the Channel Controller (CC) Register value. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_getCCRegister}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, unsigned int regOffset, unsigned int *regValue) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Get the Channel Controller (CC) Register value. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_waitAndClearTcc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, unsigned int tccNo) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Wait for a transfer completion interrupt to occur and clear it. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_checkAndClearTcc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Handle}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, unsigned int tccNo, unsigned short *tccStatus) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Returns the status of a previously initiated transfer. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_setPaRAM}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *lChObj, const }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_PaRAMRegs}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *newPaRAM) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Copy the user specified PaRAM Set onto the PaRAM Set associated with the logical channel (DMA/QDMA/Link). +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_getPaRAM}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *lChObj, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_PaRAMRegs} +{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *currPaRAM) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Retrieve existing PaRAM set associated with specified logical channel (DMA/QDMA/Link). +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_getPaRAMPhyAddr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle +}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ResDesc}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *lChObj, unsigned int *paramPhyAddr) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Get the PaRAM Set Physical Address associated with a logical channel. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_getBaseAddress}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle} +{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Cntrlr_PhyAddr}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 controllerId, unsigned int *phyAddress) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Get the Channel Controller or Transfer Controller (n) Physical Address. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_getGblConfigParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (unsigned int phyCtrllerInstId, }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_GblConfigParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *gblCfgParams) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Get the SoC specific configuration structure for the EDMA3 Hardware. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_getInstanceInitCfg}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Handle}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_InstanceInitConfig}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 *instanceInitConfig) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Get the RM Instance specific configuration structure for different EDMA3 resources' usage (owned resources, reserved resources etc). +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_Result}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Ioctl}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 (}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Handle}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 hEdmaResMgr, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_IoctlCmd}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 cmd, void *cmdArg, void *param) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 EDMA3 Resource Manager IOCTL. +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Variables +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +const unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_MAX_RM_INSTANCES}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_GblConfigParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid7370340 edma3GblCfgParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [EDMA3_MAX_EDMA3_INSTANCES] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Static Configuration structure for EDMA3 controller, to provide Global SoC specific Information. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_InstanceInitConfig}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 defInstInitConfig}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] +{\*\bkmkstart AAAAAAAHZK}{\*\bkmkend AAAAAAAHZK} +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Default Static Region Specific Configuration structure for EDMA3 controller, to provide region specific Information. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_InstanceInitConfig}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 * }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 userInitConfig}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 Region Specific Configuration structure for EDMA3 controller, to provide region specific Information. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 +EDMA3_RM_InstanceInitConfig}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 * }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 ptrInitCfgArray}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAHZL}{\*\bkmkend AAAAAAAHZL} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Instance}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 * }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 resMgrInstance}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Instance}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 * }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 ptrRMIArray}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAHZM}{\*\bkmkend AAAAAAAHZM} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \ab\af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Obj}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\insrsid7370340 resMgrObj}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [EDMA3_MAX_EDMA3_INSTANCES] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 EDMA3 Resource Manager Objects, tied to each EDMA3 HW Controller. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +static unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 edma3DmaChTccMapping}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [EDMA3_MAX_DMA_CH] +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 static unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 edma3QdmaChTccMapping}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 [EDMA3_MAX_QDMA_CH] +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 static }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_TccCallbackParams}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 edma3IntrParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [EDMA3_MAX_TCC] +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 static }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_RegionId}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 edma3RegionId}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = EDMA3_MAX_REGIONS +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 static unsigned short }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 masterExists}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 = FALSE +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 edma3NumPaRAMSets}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 = EDMA3_MAX_PARAM_SETS +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 static unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 allocatedTCCs}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 [2u] = \{0x0u, 0x0u\} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 static unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 contiguousDmaRes}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 [EDMA3_MAX_DMA_CHAN_DWRDS] = \{0x0u, 0x0u\} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 static unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 contiguousQdmaRes}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 [EDMA3_MAX_QDMA_CHAN_DWRDS] = \{0x0u\} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 static unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 contiguousTccRes}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 [EDMA3_MAX_TCC_DWRDS] = \{0x0u, 0x0u\} +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 static unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 contiguousParamRes}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 [EDMA3_MAX_PARAM_DWRDS] +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 static }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ChBoundResources}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 edma3RmChBoundRes}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_LOGICAL_CH] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ai\af0 \ltrch\fcs0 +\i\insrsid7370340 Resources bound to a Channel. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +EDMA3 Controller Resource Manager Interface Implementation. +\par This file contains Resource Manager Implementation for the EDMA3 Controller. +\par (C) Copyright 2006, Texas Instruments, Inc +\par }\pard\plain \ltrpar\s5\qj \li0\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Version: +\par }\pard\plain \ltrpar\s43\ql \li360\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +0.0.1 Purushotam Kumar - Created 0.1.0 Joseph Fernandez - Made generic +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Added documentation +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Moved SoC specific defines to SoC specific header. 0.2.0 Anuj Aggarwal - Modified it for EDMA3 package +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Added multiple instances capability 0.2.1 Anuj Aggarwal - Modified it for more run time configuration. +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Made EDMA3 package OS independent. 0.2.2 Anuj Aggarwal - Critical section handling code modification. Uses semaphore and interrupts disabling mechanism for resource sharing. 0.3.0 Anuj Aggarwal - Renamed EDMA3_DVR to EDMA3_DRV +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 IPR bit clearing in RM ISR issue fixed. +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Sample application made generic 0.3.1 Anuj Aggarwal - Added DMA/QDMA Channel to TCC mapping, to fix QDMA missed event issue. 0.3.2 Anuj Aggarwal - Added support for POLL mode +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 Added a new API to modify the CC Register. 1.0.0 Anuj Aggarwal - Fixed + resource allocation related bugs. 1.0.0.1 Anuj Aggarwal - Fixed spurious missed event generation related bug. 1.0.0.2 Anuj Aggarwal - Made the EDMA3 package RTSC compliant. 1.0.0.3 Anuj Aggarwal - Changed the directory structure as per RTSC standard. 1.0 +1 +.00.01 Anuj Aggarwal - a) Added new APIs to allocate logical channels b) Created EDMA3 config files for different platforms c) Misc changes 1.02.00.01 Anuj Aggarwal - a) Added DM6467 support b) Fixed some MRs 1.03.00.01 Anuj Aggarwal - a) Added non-RTSC P +JT files b) IOCTL Interface added. c) Fixed some MRs. 1.04 Anuj Aggarwal - a) Added new IOCTLs and APIs. b) Number of maximum Resource Manager Instances is configurable. c) Header files modified to have extern "C" declarations. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Define Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 +\ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_RES_CLEAR_ERROR_STATUS_FOR_ALL_CHANNELS\:edma3resmgr.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 +\ltrch\fcs0 \fs24\insrsid7370340 edma3resmgr.c\:EDMA3_RM_RES_CLEAR_ERROR_STATUS_FOR_ALL_CHANNELS}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 #define EDMA3_RM_RES_CLEAR_ERROR_STATUS_FOR_ALL_CHANNELS\~ (TRUE) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAHZN}{\*\bkmkend AAAAAAAHZN}EDMA3 Resource Manager behaviour of clearing CC ERROR interrupts. This macro controls the driver to enable/disable clearing of error status of all channels. +\par Define NDEBUG to ignore assert(). NDEBUG should be defined before including assert.h header file. On disabling this (with value 0x0), the + channels owned by the region is cleared and its expected that some other entity is responsible for clearing the error status for channels not owned. +\par Its recomended that this flag is a positive value, to ensure that error flags are cleared for all the channels. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 +\b\f1\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Function Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 +\ltrch\fcs0 \fs24\insrsid7370340 allocAnyContigRes\:edma3resmgr.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 edma3resmgr.c\:allocAnyContigRes}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 static EDMA3_RM_Result allocAnyContigRes (EDMA3_RM_ResType }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 resType}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\insrsid7370340 numResources}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , unsigned int * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 positionRes}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 )}{\rtlch\fcs1 \af2 \ltrch\fcs0 +\f2\insrsid7370340 [static]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAHZO}{\*\bkmkend AAAAAAAHZO}If successful, this function returns EDMA3_RM_SOK and the position of first available resource in 'positionRes'. Else returns error. +\par Algorithm used for finding N contiguous resources. In the resources' array, '1' means available and '0' means not-a +vailable. Step a) Find first '1' starting from 'start'. If successful, store it in first_one, else return error. Step b) Find first '0' starting from (first_one+1) to 'end'. If successful, store returned value in next_zero. If '0' could not be located, it + +means all the resources are available. Store 'end' (i.e. the last resource id) in next_zero. Step c) Count the number of contiguous resources available by subtracting first_one from next_zero. Step d) If result < N, do the whole process again untill you r +each end. Else you have found enough resources, return success. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +References EDMA3_MAX_DMA_CH, EDMA3_MAX_QDMA_CH, EDMA3_MAX_TCC, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE, EDMA3_RM_RES_DMA_CHANNEL, EDMA3_RM_RES_PARAM_SET, EDMA3_RM_RES_ +QDMA_CHANNEL, EDMA3_RM_RES_TCC, EDMA3_RM_SOK, edma3NumPaRAMSets, findBit(), and NULL. +\par Referenced by EDMA3_RM_allocContiguousResource(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 edma3CCErrHandler\:edma3resmgr.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.c\:edma3CCErrHandler}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +static void edma3CCErrHandler (const EDMA3_RM_Obj * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 rmObj}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 )}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 [static]}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAHZP}{\*\bkmkend AAAAAAAHZP}Interrupt handler for Channel Controller Error. +\par Interrupt Handler for the Channel Controller Error interrupt +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +This function first disables its own interrupt to make it non- entrant. Later, after calling all the callback functions, it re-enables its own interrupt. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 None. + +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Using the 'index' value (basically the DMA channel), fetch the corresponding TCC value, mapped to this DMA channel. +\par Ensure that the mapped tcc is valid and the call back is not NULL +\par TCC owned and allocated by RM. Write to EMCR to clear the corresponding EMR bits. +\par DMA channel not owned by the RM instance. Check the global error interrupt clearing option. If it is TRUE, clear the error interupt else leave it like that. +\par Using the 'index' value (basically the DMA channel), fetch the corresponding TCC value, mapped to this DMA channel. +\par Ensure that the mapped tcc is valid and the call back is not NULL +\par TCC owned and allocated by RM. Write to EMCR to clear the corresponding EMR bits. +\par DMA channel not owned by the RM instance. Check the global error interrupt clearing option. If it is TRUE, clear the error interupt else leave it like that. +\par TCC NOT owned by RM. Write to EMCRH to clear the corresponding EMRH bits. +\par Using the 'index' value (basically the QDMA channel), fetch the corresponding TCC value, mapped to this QDMA channel. +\par QDMA channel not owned by the RM instance. Check the global error interrupt clearing option. If it is TRUE, clear the error interupt else leave the ISR. +\par Queue threshold error for queue 'evtqueNum' raised. Inform all the RM instances working on this region about the error by calling their global callback functions. +\par Transfer completion code error raised. Inform all the RM instances working on this region about the error by calling their global callback functions. +\par Read the error registers again. If any interrupt is pending, write the EEVAL register. Moreover, according to the global error interrupt clearing option, check either error bits associated with all the DMA/QDMA channel +s (option is SET) OR check error bits associated with owned DMA/QDMA channels. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +References EDMA3_MAX_RM_INSTANCES, EDMA3_MAX_TCC, EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR, EDMA3_RM_CCERR_HANDLER_RETRY_COUNT, EDMA3_RM_E_CC_DMA_EVT_MISS, EDMA3_RM_E_CC_QDMA_EVT_MI +SS, EDMA3_RM_E_CC_QUE_THRES_EXCEED, EDMA3_RM_E_CC_TCC, edma3DmaChTccMapping, edma3OsProtectEntry(), edma3OsProtectExit(), edma3QdmaChTccMapping, edma3RegionId, EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_GblErrCallbackParams::gblerrCb, EDMA3_RM_Param::gblerrCbPa +r +ams, EDMA3_RM_GblErrCallbackParams::gblerrData, EDMA3_RM_GblConfigParams::globalRegs, EDMA3_RM_Instance::initParam, NULL, EDMA3_RM_GblConfigParams::numEvtQueue, EDMA3_RM_Obj::numOpens, EDMA3_RM_InstanceInitConfig::ownDmaChannels, EDMA3_RM_InstanceInitConf +ig::ownQdmaChannels, EDMA3_RM_Obj::phyCtrllerInstId, EDMA3_RM_Param::regionId, EDMA3_RM_Param::rmInstInitConfig, EDMA3_RM_TccCallbackParams::tccCb, and TRUE. +\par Referenced by lisrEdma3CCErrHandler0(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 edma3ComplHandler\:edma3resmgr.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.c\:edma3ComplHandler}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +static void edma3ComplHandler (const EDMA3_RM_Obj * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 rmObj}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 )}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 [static]}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAHZQ}{\*\bkmkend AAAAAAAHZQ}Interrupt handler for successful transfer completion. +\par Interrupt Handler for the Transfer Completion interrupt +\par edma3ComplHandler +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +This function first disables its own interrupt to make it non- entrant. Later, after calling all the callback functions, it re-enables its own interrupt. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 None. + +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Since an interrupt has found, we have to make sure that this interrupt (TCC) belongs to the TCCs allo +cated by us only. It might happen that someone else, who is using EDMA3 also, is the owner of this interrupt channel i.e. the TCC. For this, use the allocatedTCCs[], to check which all interrupt channels are owned by the EDMA3 RM Instances. +\par Choose interrupts coming from our allocated TCCs and MASK remaining ones. +\par If the user has not given any callback function while requesting the TCC, its TCC specific bit in the IPR register will NOT be cleared. +\par Choose interrupts coming from our allocated TCCs and MASK remaining ones. +\par If the user has not given any callback function while requesting the TCC, its TCC specific bit in the IPRH register will NOT be cleared. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +References allocatedTCCs, EDMA3_OS_PROTECT_I +NTERRUPT_XFER_COMPLETION, EDMA3_RM_COMPL_HANDLER_RETRY_COUNT, EDMA3_RM_XFER_COMPLETE, edma3OsProtectEntry(), edma3OsProtectExit(), edma3RegionId, EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_GblConfigParams::globalRegs, NULL, EDMA3_RM_TccCallbackParams::tccCb, an +d TRUE. +\par Referenced by lisrEdma3ComplHandler0(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 edma3GlobalRegionInit\:edma3resmgr.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.c\:edma3GlobalRegionInit}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +static void edma3GlobalRegionInit (unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 phyCtrllerInstId}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 )}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 [static]}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAHZR}{\*\bkmkend AAAAAAAHZR}Initialization of the Global region registers of the EDMA3 Controller +\par Set TC Priority among system-wide bus-masters and Queue Watermark Level +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +References EDMA3_MAX_EDMA3_INSTANCES, EDMA3_RM_QUEPRI_CLR_MASK, EDMA3_RM_QUEPRI_SET_MASK, EDMA3_RM_QUEWMTHR_SET_MASK, EDMA3_RM_SET_ALL_BITS, and NULL. +\par Referenced by EDMA3_RM_create(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 edma3MemCpy\:edma3resmgr.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.c\:edma3MemCpy}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 void edma3MemCpy (void * }{ +\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 dst}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , const void * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 src}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , unsigned int }{\rtlch\fcs1 +\ai\af1 \ltrch\fcs0 \i\insrsid7370340 len}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAHZS}{\*\bkmkend AAAAAAAHZS}Local MemCpy function +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +References NULL. +\par Referenced by EDMA3_RM_create(), EDMA3_RM_getGblConfigParams(), EDMA3_RM_getInstanceInitCfg(), EDMA3_RM_getPaRAM(), EDMA3_RM_open(), and EDMA3_RM_setPaRAM(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 edma3MemSet\:edma3resmgr.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.c\:edma3MemSet}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 void edma3MemSet (void * }{ +\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 dst}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , unsigned char }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 data}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , unsigned int }{\rtlch\fcs1 +\ai\af1 \ltrch\fcs0 \i\insrsid7370340 len}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAHZT}{\*\bkmkend AAAAAAAHZT}Local MemSet function +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +References NULL. +\par Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_close(), EDMA3_RM_create(), EDMA3_RM_delete(), EDMA3_RM_open(), and gblChngAllocContigRes(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 edma3ShadowRegionInit\:edma3resmgr.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.c\:edma3ShadowRegionInit}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +static void edma3ShadowRegionInit (const EDMA3_RM_Instance * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 pRMInstance}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 )}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 [static]}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAHZU}{\*\bkmkend AAAAAAAHZU}Initialization of the Shadow region registers of the EDMA3 Controller +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +References EDMA3_OS_PROTECT_INTERRUPT, edma3OsProtectEntry(), edma3OsProtectExit(), EDMA3_RM_Instance::initParam, NULL, EDMA3_RM_InstanceInitConfig::ownDmaChannels, EDMA3_RM_InstanceInitConfig::ownQdmaChannels, EDMA3_RM_Inst +anceInitConfig::ownTccs, EDMA3_RM_Obj::phyCtrllerInstId, EDMA3_RM_Instance::pResMgrObjHandle, EDMA3_RM_Param::regionId, and EDMA3_RM_Param::rmInstInitConfig. +\par Referenced by EDMA3_RM_open(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 edma3TCErrHandler\:edma3resmgr.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.c\:edma3TCErrHandler}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +static void edma3TCErrHandler (const EDMA3_RM_Obj * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 rmObj}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 tcNum}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 )}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 [static]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAHZV}{\*\bkmkend AAAAAAAHZV}Interrupt handler for Transfer Controller Error. +\par Interrupt Handler for the Transfer Controller Error interrupt +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Note: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +This function first disables its own interrupt to make it non- entrant. Later, after calling all the callback functions, it re-enables its own interrupt. +\par }\pard\plain \ltrpar\s5\qj \li360\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Returns: +\par }\pard\plain \ltrpar\s44\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 None. + +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +EDMA3TC has detected an error at source or destination address. Error information can be read from the error details register (ERRDET). +\par Inform all the RM instances working on this region about the error by calling their global callback functions. +\par Inform all the RM instances working on this region about the error by calling their global callback functions. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +References EDMA3_MAX_RM_INSTANCES, EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR, EDMA3_RM_E_TC_INVALID_ADDR, EDMA3_RM_E_TC_MEM_LOCATION_READ_ERROR, EDMA3_RM_E_TC_MEM_LOCATION_WRITE_ERROR, EDMA3_RM_E_TC_TR_ERROR, edma3OsProtectEntry(), edma3OsProtectExit() +, edma3RegionId, EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_GblErrCallbackParams::gblerrCb, EDMA3_RM_Param::gblerrCbParams, EDMA3_RM_GblErrCallbackParams::gblerrData, EDMA3_RM_Instance::initParam, NULL, EDMA3_RM_Obj::numOpens, EDMA3_RM_Obj::phyCtrllerInstId, ED +MA3_RM_Param::regionId, and EDMA3_RM_GblConfigParams::tcRegs. +\par Referenced by lisrEdma3TC0ErrHandler0(), lisrEdma3TC1ErrHandler0(), lisrEdma3TC2ErrHandler0(), lisrEdma3TC3ErrHandler0(), lisrEdma3TC4ErrHandler0(), lisrEdma3TC5ErrHandler0(), lisrEdma3TC6ErrHandler0(), and lisrEdma3TC7ErrHandler0(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 findBit\:edma3resmgr.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.c\:findBit}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +static int findBit (EDMA3_RM_ResType }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 resType}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 start}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 end}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , unsigned short }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 bit}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 )}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 [static]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAHZW}{\*\bkmkend AAAAAAAHZW}Finds a particular bit ('0' or '1') in the specified resources' array from 'start' to 'end'. If found, returns the position, else return -1. +\par job is to find 'bit' in an array[start_index:end_index] algo used: first search in array[start_index] then search in array[start_index + 1 : end_index - 1] then search in array[end_index] +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +References contiguousDmaRes, contiguousParamRes, contiguousQdmaRes, contiguousTccRes, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_RES_DMA_CHANNEL, EDMA3_RM_RES_PARAM_SET, EDMA3_RM_RES_QDMA_CHANNEL, EDMA3_RM_RES_TCC, EDMA3_RM_SOK, and findBitInWord(). +\par Referenced by allocAnyContigRes(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 findBitInWord\:edma3resmgr.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.c\:findBitInWord}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +static int findBitInWord (int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 source}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 start}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 , unsigned short }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 bit}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 )}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 [static]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAHZX}{\*\bkmkend AAAAAAAHZX}Finds a particular bit ('0' or '1') in the particular word from 'start'. If found, returns the position, else return -1. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by findBit(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 gblChngAllocContigRes\:edma3resmgr.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.c\:gblChngAllocContigRes}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +static EDMA3_RM_Result gblChngAllocContigRes (EDMA3_RM_Instance * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 rmInstance}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , const EDMA3_RM_ResDesc * }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\insrsid7370340 firstResIdObj}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 , unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 numResources}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 )}{\rtlch\fcs1 \af2 \ltrch\fcs0 +\f2\insrsid7370340 [static]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAHZY}{\*\bkmkend AAAAAAAHZY}Starting from 'firstResIdObj', this function makes the next 'numResources' Resources non-available for future. Also, it does some global resisters' setting also. +\par Enable the DMA channel in the DRAE/DRAEH registers also. +\par Enable the QDMA channel in the QRAE register also. +\par Enable the Interrupt channel in the DRAE/DRAEH registers. Also, If the region id coming fro +m this RM instance is same as the Master RM Instance's region id, only then we will be getting the interrupts on the same side. So save the TCC in the allocatedTCCs[] array. +\par Also, make the actual PARAM Set NULL, checking the flag whether it is required or not. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +References allocatedTCCs, EDMA3_RM_Instance::avlblDmaChannels, EDMA3_RM_Instance::avlblPaRAMSets, EDMA3_RM_Instance::avlblQdmaChannels, EDMA3_RM_Instance::avlblTccs, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_RES_DMA_CHANNEL, EDMA3_RM_RES_PARAM_SET, EDMA3_RM +_RES_QDMA_CHANNEL, EDMA3_RM_RES_TCC, EDMA3_RM_SOK, edma3MemSet(), edma3RegionId, EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_GblConfigParams::globalRegs, EDMA3_RM_Instance::initParam, NULL, EDMA3_RM_Instance::paramInitRequired, EDMA3_RM_Instance::pResMgrObjHandl +e, EDMA3_RM_Param::regionId, EDMA3_RM_ResDesc::resId, TRUE, and EDMA3_RM_ResDesc::type. +\par Referenced by EDMA3_RM_allocContiguousResource(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 lisrEdma3CCErrHandler0\:edma3resmgr.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.c\:lisrEdma3CCErrHandler0}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +void lisrEdma3CCErrHandler0 (unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 arg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAHZZ}{\*\bkmkend AAAAAAAHZZ}EDMA3 Instance 0 CC Error Interrupt Service Routine +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 lisrEdma3ComplHandler0\:edma3resmgr.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.c\:lisrEdma3ComplHandler0}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +void lisrEdma3ComplHandler0 (unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 arg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIAA}{\*\bkmkend AAAAAAAIAA}EDMA3 Instance 0 Completion Handler Interrupt Service Routine +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 lisrEdma3TC0ErrHandler0\:edma3resmgr.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.c\:lisrEdma3TC0ErrHandler0}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +void lisrEdma3TC0ErrHandler0 (unsigned int }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid7370340 arg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 ) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIAB}{\*\bkmkend AAAAAAAIAB}EDMA3 Instance 0 TC[0-7] Error Interrupt Service Routines for a maximum of 8 TCs (Transfer Controllers). +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 +\b\f1\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Variable Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 +\ltrch\fcs0 \fs24\insrsid7370340 allocatedTCCs\:edma3resmgr.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 edma3resmgr.c\:allocatedTCCs}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 unsigned int allocatedTCCs[2u] = \{0x0u, 0x0u\}}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 [static]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIAC}{\*\bkmkend AAAAAAAIAC}The list of Interrupt Channels which get allocated while requesting the TCC. It will be used while checking the IPR/IPRH bits in the RM ISR. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_delete(), EDMA3_RM_freeResource(), edma3ComplHandler(), and gblChngAllocContigRes(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 contiguousDmaRes\:edma3resmgr.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.c\:contiguousDmaRes}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +unsigned int contiguousDmaRes[EDMA3_MAX_DMA_CHAN_DWRDS] = \{0x0u, 0x0u\}}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 [static]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIAD}{\*\bkmkend AAAAAAAIAD}Arrays ownDmaChannels[], resvdDmaChannels and avlblDmaChannels will be ANDed and stored in this array. It will be referenced in EDMA3_RM_allocContiguousResource () to look for contiguous resources. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocContiguousResource(), and findBit(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 contiguousParamRes\:edma3resmgr.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.c\:contiguousParamRes}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +unsigned int contiguousParamRes[EDMA3_MAX_PARAM_DWRDS]}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 [static]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIAE}{\*\bkmkend AAAAAAAIAE}Arrays ownDmaChannels[], resvdDmaChannels and avlblDmaChannels will be ANDed and stored in this array. It will be referenced in EDMA3_RM_allocContiguousResource () to look for contiguous resources. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_create(), and findBit(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 contiguousQdmaRes\:edma3resmgr.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.c\:contiguousQdmaRes}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +unsigned int contiguousQdmaRes[EDMA3_MAX_QDMA_CHAN_DWRDS] = \{0x0u\}}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 [static]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIAF}{\*\bkmkend AAAAAAAIAF}Arrays ownDmaChannels[], resvdDmaChannels and avlblDmaChannels will be ANDed and stored in this array. It will be referenced in EDMA3_RM_allocContiguousResource () to look for contiguous resources. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocContiguousResource(), and findBit(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 contiguousTccRes\:edma3resmgr.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.c\:contiguousTccRes}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +unsigned int contiguousTccRes[EDMA3_MAX_TCC_DWRDS] = \{0x0u, 0x0u\}}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 [static]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIAG}{\*\bkmkend AAAAAAAIAG}Arrays ownDmaChannels[], resvdDmaChannels and avlblDmaChannels will be ANDed and stored in this array. It will be referenced in EDMA3_RM_allocContiguousResource () to look for contiguous resources. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocContiguousResource(), and findBit(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 EDMA3_MAX_RM_INSTANCES\:edma3resmgr.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.c\:EDMA3_MAX_RM_INSTANCES}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +const unsigned int EDMA3_MAX_RM_INSTANCES +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIAH}{\*\bkmkend AAAAAAAIAH}Maximum Resource Manager Instances supported by the EDMA3 Package. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_create(), EDMA3_RM_getInstanceInitCfg(), EDMA3_RM_open(), edma3CCErrHandler(), and edma3TCErrHandler(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 edma3DmaChTccMapping\:edma3resmgr.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.c\:edma3DmaChTccMapping}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +unsigned int edma3DmaChTccMapping[EDMA3_MAX_DMA_CH]}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 [static]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIAI}{\*\bkmkend AAAAAAAIAI}Global Arr +ay to store the mapping between DMA channels and Interrupt channels i.e. TCCs. DMA channel X can use any TCC Y. Transfer completion interrupt will occur on the TCC Y (IPR/IPRH Register, bit Y), but error interrupt will occur on DMA channel X (EMR/EMRH reg +ister, bit X). In that scenario, this DMA channel <-> TCC mapping will be used to point to the correct callback function. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_create(), EDMA3_RM_registerTccCb(), EDMA3_RM_unregisterTccCb(), and edma3CCErrHandler(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 edma3GblCfgParams\:edma3resmgr.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.c\:edma3GblCfgParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_GblConfigParams edma3GblCfgParams[EDMA3_MAX_EDMA3_INSTANCES] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIAJ}{\*\bkmkend AAAAAAAIAJ}Static Configuration structure for EDMA3 controller, to provide Global SoC specific Information. +\par This configuration info can also be provided by the user at run-time, while calling EDMA3_RM_create (). If not provided at run-time, this info will be taken from the config file "edma3__cfg.c", for the specified platform. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 edma3IntrParams\:edma3resmgr.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.c\:edma3IntrParams}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_TccCallbackParams edma3IntrParams[EDMA3_MAX_TCC]}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 [static]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIAK}{\*\bkmkend AAAAAAAIAK}Global Array to maintain the Callback details registered against a particular TCC. Used to call the callback functions linked to the particular channel. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 edma3NumPaRAMSets\:edma3resmgr.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.c\:edma3NumPaRAMSets}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +unsigned int edma3NumPaRAMSets = EDMA3_MAX_PARAM_SETS +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIAL}{\*\bkmkend AAAAAAAIAL}Number of PaRAM Sets actually present on the SoC. This will be updated while creating the Resource Manager Object. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by allocAnyContigRes(), EDMA3_RM_allocLogicalChannel(), EDMA3_RM_create(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_getPaRAM(), EDMA3_RM_getPaRAMPhyAddr(), and EDMA3_RM_setPaRAM(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 edma3QdmaChTccMapping\:edma3resmgr.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.c\:edma3QdmaChTccMapping}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +unsigned int edma3QdmaChTccMapping[EDMA3_MAX_QDMA_CH]}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 [static]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIAM}{\*\bkmkend AAAAAAAIAM}Global Array to store the mapping between QDMA channels and Interrupt channels i.e. TCCs. QDMA channel X can use any TC +C Y. Transfer completion interrupt will occur on the TCC Y (IPR/IPRH Register, bit Y), but error interrupt will occur on QDMA channel X (QEMR register, bit X). In that scenario, this QDMA channel <-> TCC mapping will be used to point to the correct callba +ck function. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_create(), EDMA3_RM_registerTccCb(), EDMA3_RM_unregisterTccCb(), and edma3CCErrHandler(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 edma3RegionId\:edma3resmgr.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.c\:edma3RegionId}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_RegionId edma3RegionId = EDMA3_MAX_REGIONS}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 [static]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIAN}{\*\bkmkend AAAAAAAIAN}edma3RegionId will be updated ONCE using the parameter regionId passed to the }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_open()}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 + function, for the Master RM instance (one who configures the Global Registers). This global variable will be used within the Interrupt handlers +to know which shadow region registers to access. All other interrupts coming from other shadow regions will not be handled. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_close(), EDMA3_RM_freeResource(), EDMA3_RM_open(), edma3CCErrHandler(), edma3ComplHandler(), edma3TCErrHandler(), and gblChngAllocContigRes(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 edma3RmChBoundRes\:edma3resmgr.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.c\:edma3RmChBoundRes}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_ChBoundResources edma3RmChBoundRes[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_LOGICAL_CH]}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 [static]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIAO}{\*\bkmkend AAAAAAAIAO}Resources bound to a Channel. +\par When a request for a channel is made, the resources PaRAM Set and TCC get bound to that channel. This information is needed internally by the resource manager, when a request is made to free the channel, to free up the channel-associated resources. + +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 masterExists\:edma3resmgr.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.c\:masterExists}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +unsigned short masterExists = FALSE}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 [static]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIAP}{\*\bkmkend AAAAAAAIAP}masterExists will be updated when the Master RM Instance modifies the Global EDMA3 configuration registers. It is used to prevent any other Master RM Instance creation. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_close(), and EDMA3_RM_open(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 resMgrInstance\:edma3resmgr.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.c\:resMgrInstance}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_Instance* resMgrInstance +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIAQ}{\*\bkmkend AAAAAAAIAQ}Handles of EDMA3 Resource Manager Instances. +\par Used to maintain information of the EDMA3 RM Instances for each HW controller. There could be a maximum of EDMA3_MAX_RM_INSTANCES instances per EDMA3 HW. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 resMgrObj\:edma3resmgr.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 +\b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.c\:resMgrObj}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_Obj resMgrObj[EDMA3_MAX_EDMA3_INSTANCES] +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIAR}{\*\bkmkend AAAAAAAIAR}EDMA3 Resource Manager Objects, tied to each EDMA3 HW Controller. +\par Typically one RM object will cater to one EDMA3 HW controller and will have all the global config information. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 userInitConfig\:edma3resmgr.c}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.c\:userInitConfig}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +EDMA3_RM_InstanceInitConfig* userInitConfig +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIAS}{\*\bkmkend AAAAAAAIAS}Region Specific Configuration structure for EDMA3 controller, to provide region specific Information. +\par This configuration info can also be provided by the user at run-time, while calling EDMA3_RM_open (). If not provided at run-time, this info will be taken from the config file "edma3__cfg.c", for the specified platform. +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \sect +}\sectd \ltrsect\linex0\sectdefaultcl\sftnbj \pard\plain \ltrpar\s2\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel1\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 +\b\f1\fs28\lang1033\langfe1033\kerning28\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.h File Reference +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \tcl2 +{\*\bkmkstart _Toc211937585}edma3resmgr.h{\*\bkmkend _Toc211937585}}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 +\v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 edma3resmgr.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 {\*\bkmkstart AAAAAAAIAT} +{\*\bkmkend AAAAAAAIAT}EDMA3 Resource Manager Internal header file. +\par }\pard\plain \ltrpar\s18\ql \li0\ri0\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 +#include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid7370340 #include }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Data Structures +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Obj}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 EDMA3 Hardware Instance Configuration Structure. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_Instance}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 EDMA3 RM Instance Specific Configuration Structure. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ChBoundResources}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 EDMA3 Channel-Bound resources. +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 struct }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_TccCallbackParams}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 { +\rtlch\fcs1 \ai\af0 \ltrch\fcs0 \i\insrsid7370340 TCC Callback - Caters to channel specific status reporting. +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Defines +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define } +{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_SET_ALL_BITS}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \~ (0xFFFFFFFFu) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_DCH_PARAM_CLR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (~EDMA3_CCRL_DCHMAP_PAENTRY_MASK) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_DCH_PARAM_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 (paRAMId)\~ (((EDMA3_CCRL_DCHMAP_PAENTRY_MASK >> EDMA3_CCRL_DCHMAP_PAENTRY_SHIFT) & (paRAMId)) << EDMA3_CCRL_DCHMAP_PAENTRY_SHIFT) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_QCH_PARAM_CLR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (~EDMA3_CCRL_QCHMAP_PAENTRY_MASK) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_QCH_PARAM_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 (paRAMId)\~ (((EDMA3_CCRL_QCHMAP_PAENTRY_MASK >> EDMA3_CCRL_QCHMAP_PAENTRY_SHIFT) & (paRAMId)) << EDMA3_CCRL_QCHMAP_PAENTRY_SHIFT) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_QCH_TRWORD_CLR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (~EDMA3_CCRL_QCHMAP_TRWORD_MASK) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_QCH_TRWORD_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 (paRAMId)\~ (((EDMA3_CCRL_QCHMAP_TRWORD_MASK >> EDMA3_CCRL_QCHMAP_TRWORD_SHIFT) & (paRAMId)) << EDMA3_CCRL_QCHMAP_TRWORD_SHIFT) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_QUEPRI_CLR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 (queNum)\~ (~(EDMA3_CCRL_QUEPRI_PRIQ0_MASK << ((queNum) * EDMA3_CCRL_QUEPRI_PRIQ1_SHIFT))) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_QUEPRI_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 (queNum, quePri)\~ ((EDMA3_CCRL_QUEPRI_PRIQ0_MASK & (quePri)) << ((queNum) * EDMA3_CCRL_QUEPRI_PRIQ1_SHIFT)) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_QUEWMTHR_CLR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 (queNum)\~ (~(EDMA3_CCRL_QWMTHRA_Q0_MASK << ((queNum) * EDMA3_CCRL_QWMTHRA_Q1_SHIFT))) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_QUEWMTHR_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 (queNum, queThr)\~ ((EDMA3_CCRL_QWMTHRA_Q0_MASK & (queThr)) << ((queNum) * EDMA3_CCRL_QWMTHRA_Q1_SHIFT)) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_OPT_TCC_CLR_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (~EDMA3_CCRL_OPT_TCC_MASK) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_OPT_TCC_SET_MASK}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 (tcc)\~ (((EDMA3_CCRL_OPT_TCC_MASK >> EDMA3_CCRL_OPT_TCC_SHIFT) & (tcc)) << EDMA3_CCRL_OPT_TCC_SHIFT) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD}{\rtlch\fcs1 +\af0 \ltrch\fcs0 \insrsid7370340 \~ (5u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_DMA_CH_MAX_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (EDMA3_MAX_DMA_CH - 1u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_LINK_CH_MIN_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (EDMA3_MAX_DMA_CH) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_LINK_CH_MAX_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS - 1u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_QDMA_CH_MIN_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_QDMA_CH_MAX_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS + EDMA3_MAX_QDMA_CH - 1u) +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 #define }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_LOG_CH_MAX_VAL}{\rtlch\fcs1 \af0 +\ltrch\fcs0 \insrsid7370340 \~ (EDMA3_RM_QDMA_CH_MAX_VAL) +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Enumerations +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 enum }{ +\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_ObjState}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 \{ }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_DELETED}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 0, }{\rtlch\fcs1 +\ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_CREATED}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 1, }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_OPENED}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 2, }{\rtlch\fcs1 \ab\af0 +\ltrch\fcs0 \b\insrsid7370340 EDMA3_RM_CLOSED}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 = 3 \} +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 +\b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Variables +\par {\pntext\pard\plain\ltrpar \s62 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s62\ql \fi-360\li360\ri0\widctlpar\jclisttab\tx360\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls1\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls1\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +unsigned int }{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\insrsid7370340 edma3NumPaRAMSets}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Detailed Description +\par }\pard\plain \ltrpar\s17\qj \li0\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +EDMA3 Resource Manager Internal header file. +\par This file contains implementation specific details used by the RM internally +\par (C) Copyright 2006, Texas Instruments, Inc +\par }\pard\plain \ltrpar\s5\qj \li0\ri0\sb90\sa30\keepn\widctlpar\wrapdefault\faauto\outlinelevel4\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Version: +\par }\pard\plain \ltrpar\s43\ql \li360\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +0.1.0 Joseph Fernandez - Created 0.2.0 Anuj Aggarwal - Modified it for EDMA3 package +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard\plain \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Added multiple instances capability 0.2.1 Anuj Aggarwal - Modified it for more run time configuration. +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Made EDMA3 package OS independent. 0.2.2 Anuj Aggarwal - Critical section handling code modification. Uses semaphore and interrupts disabling mechanism for resource sharing. 0.3.0 Anuj Aggarwal - Renamed EDMA3_DVR to EDMA3_DRV +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 IPR bit clearing in RM ISR issue fixed. +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Sample application made generic 0.3.1 Anuj Aggarwal - Added DMA/QDMA Channel to TCC mapping, to fix QDMA missed event issue. 0.3.2 Anuj Aggarwal - Added support for POLL mode +\par {\pntext\pard\plain\ltrpar \s63 \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f3\fs20 \loch\af3\dbch\af0\hich\f3 \'b7\tab}}\pard \ltrpar\s63\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Added a new API to modify the CC Register. 1.0.0 Anuj Aggarwal - Fixed resource allocation related bugs. 1.0.0.1 Anuj Aggarwal - Fixed spurious missed event generation related bug. 1.0.0.2 Anuj Aggarwal - Made the EDMA3 package RTSC compliant. 1.0.0.3 Anu +j + Aggarwal - Changed the directory structure as per RTSC standard. 1.01.00.01 Anuj Aggarwal - a) Added new APIs to allocate logical channels b) Created EDMA3 config files for different platforms c) Misc changes 1.02.00.01 Anuj Aggarwal - a) Added DM6467 su +p +port b) Fixed some MRs 1.03.00.01 Anuj Aggarwal - a) Added non-RTSC PJT files b) IOCTL Interface added. c) Fixed some MRs. 1.04 Anuj Aggarwal - a) Added new IOCTLs and APIs. b) Number of maximum Resource Manager Instances is configurable. c) Header files +modified to have extern "C" declarations. +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 +\fs24\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Define Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 +\ltrch\fcs0 \fs24\insrsid7370340 EDMA3_RM_DCH_PARAM_CLR_MASK\:edma3resmgr.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 edma3resmgr.h\:EDMA3_RM_DCH_PARAM_CLR_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 +\af1 \ltrch\fcs0 \insrsid7370340 #define EDMA3_RM_DCH_PARAM_CLR_MASK\~ (~EDMA3_CCRL_DCHMAP_PAENTRY_MASK) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIAU}{\*\bkmkend AAAAAAAIAU}DCHMAP-PaRAMEntry bitfield Clear +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocLogicalChannel(), EDMA3_RM_freeLogicalChannel(), and EDMA3_RM_mapEdmaChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 EDMA3_RM_DCH_PARAM_SET_MASK\:edma3resmgr.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.h\:EDMA3_RM_DCH_PARAM_SET_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 #define EDMA3_RM_DCH_PARAM_SET_MASK(paRAMId)\~ (((EDMA3_CCRL_DCHMAP_PAENTRY_MASK >> EDMA3_CCRL_DCHMAP_PAENTRY_SHIFT) & (paRAMId)) << EDMA3_CCRL_DCHMAP_PAENTRY_SHIFT) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIAV}{\*\bkmkend AAAAAAAIAV}DCHMAP-PaRAMEntry bitfield Set +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocLogicalChannel(), and EDMA3_RM_mapEdmaChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 EDMA3_RM_OPT_TCC_CLR_MASK\:edma3resmgr.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.h\:EDMA3_RM_OPT_TCC_CLR_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_RM_OPT_TCC_CLR_MASK\~ (~EDMA3_CCRL_OPT_TCC_MASK) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIAW}{\*\bkmkend AAAAAAAIAW}OPT-TCC bitfield Clear +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocLogicalChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 EDMA3_RM_OPT_TCC_SET_MASK\:edma3resmgr.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.h\:EDMA3_RM_OPT_TCC_SET_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_RM_OPT_TCC_SET_MASK(tcc)\~ (((EDMA3_CCRL_OPT_TCC_MASK >> EDMA3_CCRL_OPT_TCC_SHIFT) & (tcc)) << EDMA3_CCRL_OPT_TCC_SHIFT) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIAX}{\*\bkmkend AAAAAAAIAX}OPT-TCC bitfield Set +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocLogicalChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD\:edma3resmgr.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.h\:EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 #define EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD\~ (5u) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIAY}{\*\bkmkend AAAAAAAIAY}PaRAM Set Entry for Link and B count Reload field +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocLogicalChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 EDMA3_RM_QCH_PARAM_CLR_MASK\:edma3resmgr.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.h\:EDMA3_RM_QCH_PARAM_CLR_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 #define EDMA3_RM_QCH_PARAM_CLR_MASK\~ (~EDMA3_CCRL_QCHMAP_PAENTRY_MASK) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIAZ}{\*\bkmkend AAAAAAAIAZ}QCHMAP-PaRAMEntry bitfield Clear +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocLogicalChannel(), EDMA3_RM_freeLogicalChannel(), and EDMA3_RM_mapQdmaChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 EDMA3_RM_QCH_PARAM_SET_MASK\:edma3resmgr.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.h\:EDMA3_RM_QCH_PARAM_SET_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 #define EDMA3_RM_QCH_PARAM_SET_MASK(paRAMId)\~ (((EDMA3_CCRL_QCHMAP_PAENTRY_MASK >> EDMA3_CCRL_QCHMAP_PAENTRY_SHIFT) & (paRAMId)) << EDMA3_CCRL_QCHMAP_PAENTRY_SHIFT) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIBA}{\*\bkmkend AAAAAAAIBA}QCHMAP-PaRAMEntry bitfield Set +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocLogicalChannel(), and EDMA3_RM_mapQdmaChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 EDMA3_RM_QCH_TRWORD_CLR_MASK\:edma3resmgr.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.h\:EDMA3_RM_QCH_TRWORD_CLR_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 #define EDMA3_RM_QCH_TRWORD_CLR_MASK\~ (~EDMA3_CCRL_QCHMAP_TRWORD_MASK) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIBB}{\*\bkmkend AAAAAAAIBB}QCHMAP-TrigWord bitfield Clear +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocLogicalChannel(), EDMA3_RM_freeLogicalChannel(), and EDMA3_RM_mapQdmaChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 EDMA3_RM_QCH_TRWORD_SET_MASK\:edma3resmgr.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.h\:EDMA3_RM_QCH_TRWORD_SET_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 #define EDMA3_RM_QCH_TRWORD_SET_MASK(paRAMId)\~ (((EDMA3_CCRL_QCHMAP_TRWORD_MASK >> EDMA3_CCRL_QCHMAP_TRWORD_SHIFT) & (paRAMId)) << EDMA3_CCRL_QCHMAP_TRWORD_SHIFT) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIBC}{\*\bkmkend AAAAAAAIBC}QCHMAP-TrigWord bitfield Set +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by EDMA3_RM_allocLogicalChannel(), and EDMA3_RM_mapQdmaChannel(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 EDMA3_RM_QUEPRI_CLR_MASK\:edma3resmgr.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.h\:EDMA3_RM_QUEPRI_CLR_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_RM_QUEPRI_CLR_MASK(queNum)\~ (~(EDMA3_CCRL_QUEPRI_PRIQ0_MASK << ((queNum) * EDMA3_CCRL_QUEPRI_PRIQ1_SHIFT))) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIBD}{\*\bkmkend AAAAAAAIBD}QUEPRI bits Clear +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by edma3GlobalRegionInit(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 EDMA3_RM_QUEPRI_SET_MASK\:edma3resmgr.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.h\:EDMA3_RM_QUEPRI_SET_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_RM_QUEPRI_SET_MASK(queNum, quePri)\~ ((EDMA3_CCRL_QUEPRI_PRIQ0_MASK & (quePri)) << ((queNum) * EDMA3_CCRL_QUEPRI_PRIQ1_SHIFT)) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIBE}{\*\bkmkend AAAAAAAIBE}QUEPRI bits Set +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by edma3GlobalRegionInit(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 EDMA3_RM_QUEWMTHR_CLR_MASK\:edma3resmgr.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.h\:EDMA3_RM_QUEWMTHR_CLR_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 #define EDMA3_RM_QUEWMTHR_CLR_MASK(queNum)\~ (~(EDMA3_CCRL_QWMTHRA_Q0_MASK << ((queNum) * EDMA3_CCRL_QWMTHRA_Q1_SHIFT))) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIBF}{\*\bkmkend AAAAAAAIBF}QUEWMTHR bits Clear +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 EDMA3_RM_QUEWMTHR_SET_MASK\:edma3resmgr.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.h\:EDMA3_RM_QUEWMTHR_SET_MASK}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 #define EDMA3_RM_QUEWMTHR_SET_MASK(queNum, queThr)\~ ((EDMA3_CCRL_QWMTHRA_Q0_MASK & (queThr)) << ((queNum) * EDMA3_CCRL_QWMTHRA_Q1_SHIFT)) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIBG}{\*\bkmkend AAAAAAAIBG}QUEWMTHR bits Set +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by edma3GlobalRegionInit(). +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 +\insrsid7370340 EDMA3_RM_SET_ALL_BITS\:edma3resmgr.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 +\ltrch\fcs0 \b\v\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 edma3resmgr.h\:EDMA3_RM_SET_ALL_BITS}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 +#define EDMA3_RM_SET_ALL_BITS\~ (0xFFFFFFFFu) +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIBH}{\*\bkmkend AAAAAAAIBH}Define for setting all bits of the EDMA3 Controller Registers +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by edma3GlobalRegionInit(). +\par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\brdrb\brdrs\brdrw5\brsp20 \wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 +\b\f1\insrsid7370340 +\par }\pard\plain \ltrpar\s3\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel2\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 Variable Documentation +\par }\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs20\alang1025 \ltrch\fcs0 \b\f1\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 +\ltrch\fcs0 \fs24\insrsid7370340 edma3NumPaRAMSets\:edma3resmgr.h}}}\sectd \linex0\sectdefaultcl\sftnbj {\pard\plain \ltrpar\s4\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel3\adjustright\rin0\lin0\itap0 \rtlch\fcs1 +\ab\af1\afs24\alang1025 \ltrch\fcs0 \b\v\f1\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\xe {\rtlch\fcs1 \af1\afs24 \ltrch\fcs0 \fs24\insrsid7370340 edma3resmgr.h\:edma3NumPaRAMSets}}}\sectd \linex0\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 +\ltrch\fcs0 \insrsid7370340 unsigned int edma3NumPaRAMSets +\par }\pard\plain \ltrpar\s17\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 \fs22\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +{\*\bkmkstart AAAAAAAIBI}{\*\bkmkend AAAAAAAIBI}Include Resource Manager header file Number of PaRAM Sets actually present on the SoC. This will be updated while creating the Resource Manager Object. +\par Number of PaRAM Sets actually present on the SoC. This will be updated while creating the Resource Manager Object. +\par }\pard\plain \ltrpar\s33\qj \li360\ri0\sb30\sa60\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +Referenced by allocAnyContigRes(), EDMA3_RM_allocLogicalChannel(), EDMA3_RM_create(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_getPaRAM(), EDMA3_RM_getPaRAMPhyAddr(), and EDMA3_RM_setPaRAM(). +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 \sect +}\sectd \ltrsect\linex0\sectdefaultcl\sectrsid7370340\sftnbj \pard\plain \ltrpar\s1\ql \li0\ri0\sb240\sa60\keepn\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\af1\afs36\alang1025 \ltrch\fcs0 +\b\f1\fs36\lang1033\langfe1033\kerning36\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7370340 Index +\par }\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\pard\plain \ltrpar +\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs24\alang1025 \ltrch\fcs0 \v\fs24\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\tc {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 {\*\bkmkstart _Toc211937586} +Index{\*\bkmkend _Toc211937586}}}}\sectd \linex0\sectdefaultcl\sectrsid7370340\sftnbj {\field{\*\fldinst {\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\insrsid7370340 INDEX \\c2 \\*MERGEFORMAT}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 +\par }{\rtlch\fcs1 \af0\afs24 \ltrch\fcs0 \fs24\lang1024\langfe1024\noproof\insrsid7370340 \sect }\sectd \ltrsect\sbknone\linex0\cols2\sectdefaultcl\sectrsid7370340\sftnbj \pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar +\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid7370340 A_B_CNT + +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_ParamentryRegs, 68 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 allocAnyContigRes +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3resmgr.c, 203 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 allocatedTCCs +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3resmgr.c, 208 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 avlblDmaChannels +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_Instance, 58 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 avlblPaRAMSets +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_Instance, 58 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 avlblQdmaChannels +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_Instance, 58 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 avlblTccs +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_Instance, 58 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Boundary Values, 49 +\par cbData +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_TccCallbackParams, 73 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 CC_BASE_ADDRESS +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_da830_cfg.c, 84 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 CC_ERROR_INT +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_da830_cfg.c, 84 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 ccError +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_GblConfigParams, 54 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Channel Specific Interface, 7 +\par Completion status, 5 +\par contiguousDmaRes +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3resmgr.c, 208 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 contiguousParamRes +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3resmgr.c, 208 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 contiguousQdmaRes +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3resmgr.c, 208 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 contiguousTccRes +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3resmgr.c, 208 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 DMA_CHANNEL_TO_EVENT_MAPPING_0 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_da830_cfg.c, 84 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 DMA_CHANNEL_TO_EVENT_MAPPING_1 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_da830_cfg.c, 84 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 dmaChannelHwEvtMap +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_GblConfigParams, 55 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 dmaChannelPaRAMMap +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_GblConfigParams, 55 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 dmaChannelTccMap +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_GblConfigParams, 55 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 dmaChPaRAMMapExists +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_GblConfigParams, 53 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3 Interrupt Manager Interface, 5 +\par EDMA3 Resource Manager Usage Guidelines, 15 +\par EDMA3 Resources Management, 24 +\par edma3_common.h, 74 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_DRV_DEBUG, 75 +\par EDMA3_DRV_Handle, 78 +\par EDMA3_DRV_Result, 78 +\par EDMA3_DRV_SOK, 75 +\par EDMA3_MAX_DMA_CH, 75 +\par EDMA3_MAX_DMA_CHAN_DWRDS, 76 +\par EDMA3_MAX_EDMA3_INSTANCES, 76 +\par EDMA3_MAX_EVT_QUE, 76 +\par EDMA3_MAX_LOGICAL_CH, 76 +\par EDMA3_MAX_PARAM_DWRDS, 76 +\par EDMA3_MAX_PARAM_SETS, 76 +\par EDMA3_MAX_QDMA_CH, 76 +\par EDMA3_MAX_QDMA_CHAN_DWRDS, 76 +\par EDMA3_MAX_REGIONS, 76 +\par EDMA3_MAX_TC, 76 +\par EDMA3_MAX_TCC, 77 +\par EDMA3_MAX_TCC_DWRDS, 77 +\par EDMA3_OS_PROTECT_INTERRUPT, 77 +\par EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR, 77 +\par EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR, 77 +\par EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION, 77 +\par EDMA3_OS_PROTECT_SCHEDULER, 77 +\par EDMA3_OS_Sem_Handle, 79 +\par EDMA3_OSSEM_NO_TIMEOUT, 77 +\par EDMA3_RM_DEBUG, 77 +\par EDMA3_RM_Handle, 79 +\par EDMA3_RM_Result, 79 +\par EDMA3_RM_SOK, 77 +\par edma3OsProtectEntry, 79 +\par edma3OsProtectExit, 80 +\par edma3OsSemGive, 80 +\par edma3OsSemTake, 80 +\par FALSE, 78 +\par lisrEdma3CCErrHandler0, 81 +\par lisrEdma3ComplHandler0, 81 +\par lisrEdma3TC0ErrHandler0, 81 +\par lisrEdma3TC1ErrHandler0, 81 +\par lisrEdma3TC2ErrHandler0, 81 +\par lisrEdma3TC3ErrHandler0, 81 +\par lisrEdma3TC4ErrHandler0, 81 +\par lisrEdma3TC5ErrHandler0, 81 +\par lisrEdma3TC6ErrHandler0, 82 +\par lisrEdma3TC7ErrHandler0, 82 +\par NULL, 78 +\par TRUE, 78 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_da830_cfg.c, 83 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 CC_BASE_ADDRESS, 84 +\par CC_ERROR_INT, 84 +\par DMA_CHANNEL_TO_EVENT_MAPPING_0, 84 +\par DMA_CHANNEL_TO_EVENT_MAPPING_1, 84 +\par edma3GblCfgParams, 86 +\par MEM_PROTECTION_EXISTENCE, 85 +\par NUM_DMA_CHANNELS, 85 +\par NUM_EVENT_QUEUE, 85 +\par NUM_PARAM_SETS, 85 +\par NUM_QDMA_CHANNELS, 85 +\par NUM_REGION, 85 +\par NUM_TC, 85 +\par NUM_TCC, 85 +\par TC0_BASE_ADDRESS, 85 +\par TC0_ERROR_INT, 85 +\par TC1_BASE_ADDRESS, 85 +\par TC1_ERROR_INT, 85 +\par TC2_BASE_ADDRESS, 85 +\par TC2_ERROR_INT, 85 +\par TC3_BASE_ADDRESS, 85 +\par TC3_ERROR_INT, 86 +\par TC4_BASE_ADDRESS, 86 +\par TC4_ERROR_INT, 86 +\par TC5_BASE_ADDRESS, 86 +\par TC5_ERROR_INT, 86 +\par TC6_BASE_ADDRESS, 86 +\par TC6_ERROR_INT, 86 +\par TC7_BASE_ADDRESS, 86 +\par TC7_ERROR_INT, 86 +\par XFER_COMPLETION_INT, 86 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_DRV_DEBUG +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 75 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_DRV_Handle +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 78 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_DRV_Result +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 78 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_DRV_SOK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 75 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_log.h, 87 +\par EDMA3_MAX_DMA_CH +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 75 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_MAX_DMA_CHAN_DWRDS +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 76 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_MAX_EDMA3_INSTANCES +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 76 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_MAX_EVT_QUE +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 76 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_MAX_LOGICAL_CH +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 76 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_MAX_PARAM_DWRDS +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 76 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_MAX_PARAM_SETS +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 76 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_MAX_QDMA_CH +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 76 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_MAX_QDMA_CHAN_DWRDS +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 76 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_MAX_REGIONS +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 76 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_MAX_RM_INSTANCES +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_rm_gbl_data.c, 197 +\par edma3resmgr.c, 208 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_MAX_TC +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 76 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_MAX_TCC +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 77 +\par }\pard\plain \ltrpar\s84\ql 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\fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 77 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 77 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 77 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 77 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_OS_PROTECT_SCHEDULER +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 77 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_OS_Sem_Handle +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 79 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_OSSEM_NO_TIMEOUT +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 77 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_rl_cc.h, 88 +\par edma3_rl_tc.h, 182 +\par edma3_rm.h, 191 +\par EDMA3_RM_allocContiguousResource +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 32 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_allocLogicalChannel +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 33 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_allocResource 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\fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_CH_NO_PARAM_MAP +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 27 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_CH_NO_TCC_MAP +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 27 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_ChBoundResources, 51 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 paRAMId, 51 +\par tcc, 51 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_checkAndClearTcc +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 38 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_close +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMMain, 11 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_CLOSED +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgrIntObjMaint, 49 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_Cntrlr_PhyAddr +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 28 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_create +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMMain, 12 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_CREATED +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgrIntObjMaint, 49 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_DCH_PARAM_CLR_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3resmgr.h, 213 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_DCH_PARAM_SET_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3resmgr.h, 213 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_DEBUG +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 77 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_delete +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMMain, 13 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_DELETED +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgrIntObjMaint, 49 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_DMA_CH_MAX_VAL +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMIntBoundVals, 50 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_DMA_CHANNEL_ANY +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 27 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_E_ALL_RES_NOT_AVAILABLE +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMErrCode, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_E_BASE +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMErrCode, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMErrCode, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_E_CC_DMA_EVT_MISS +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMStatus, 7 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_E_CC_QDMA_EVT_MISS +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMStatus, 7 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_E_CC_QUE_THRES_EXCEED +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMStatus, 6 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_E_CC_TCC +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMStatus, 6 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_E_FEATURE_UNSUPPORTED +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMErrCode, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_E_INVALID_PARAM +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMErrCode, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_E_INVALID_STATE +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMErrCode, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_E_MAX_RM_INST_OPENED +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMErrCode, 22 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_E_OBJ_NOT_CLOSED +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMErrCode, 23 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_E_OBJ_NOT_DELETED +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMErrCode, 23 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_E_OBJ_NOT_OPENED +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMErrCode, 23 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_E_RES_ALREADY_FREE +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMErrCode, 23 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_E_RES_NOT_ALLOCATED +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMErrCode, 23 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_E_RES_NOT_OWNED +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMErrCode, 23 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_E_RM_MASTER_ALREADY_EXISTS +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMErrCode, 23 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_E_SEMAPHORE +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMErrCode, 23 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMErrCode, 23 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_E_TC_INVALID_ADDR +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMStatus, 6 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_E_TC_MEM_LOCATION_READ_ERROR +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMStatus, 6 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_E_TC_MEM_LOCATION_WRITE_ERROR +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMStatus, 6 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_E_TC_TR_ERROR +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMStatus, 6 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_EventQueue +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMMain, 11 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_freeContiguousResource +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 39 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_freeLogicalChannel +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 40 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_freeResource +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 40 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_rm_gbl_data.c, 197 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_MAX_RM_INSTANCES, 197 +\par MAX_EDMA3_RM_INSTANCES, 197 +\par resMgrInstance, 198 +\par resMgrInstanceArray, 198 +\par userInitConfig, 198 +\par userInstInitConfigArray, 198 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_GblConfigParams, 52 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 ccError, 54 +\par dmaChannelHwEvtMap, 55 +\par dmaChannelPaRAMMap, 55 +\par dmaChannelTccMap, 55 +\par dmaChPaRAMMapExists, 53 +\par evtQPri, 54 +\par evtQueueWaterMarkLvl, 54 +\par globalRegs, 54 +\par memProtectionExists, 54 +\par numDmaChannels, 53 +\par numEvtQueue, 53 +\par numPaRAMSets, 53 +\par numQdmaChannels, 53 +\par numRegions, 53 +\par numTccs, 53 +\par numTcs, 53 +\par tcDefaultBurstSize, 55 +\par tcError, 54 +\par tcRegs, 54 +\par xferCompleteInt, 54 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_GblErrCallback +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMStatus, 6 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_GblErrCallbackParams, 56 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 gblerrCb, 56 +\par gblerrData, 56 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_getBaseAddress +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 41 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_getCCRegister +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 42 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_getGblConfigParams +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 42 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_getInstanceInitCfg +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 43 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_getPaRAM +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 43 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_getPaRAMPhyAddr +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 43 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_GlobalError +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMStatus, 6 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_Handle +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 79 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 28 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_0 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 28 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_1 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 28 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_10 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_11 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_12 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_13 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_14 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_15 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_16 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_17 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_18 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_19 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_2 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 28 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_20 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_21 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_22 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_23 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_24 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_25 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_26 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_27 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_28 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_29 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_3 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_30 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_31 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_32 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_33 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_34 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_35 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_36 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_37 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_38 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_39 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_4 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_40 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_41 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_42 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_43 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_44 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_45 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_46 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_47 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_48 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_49 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_5 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_50 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_51 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_52 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_53 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_54 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_55 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_56 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_57 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_58 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_59 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_6 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_60 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_61 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_62 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_63 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_7 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_8 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_HW_CHANNEL_EVENT_9 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 29 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_Instance, 57 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 avlblDmaChannels, 58 +\par avlblPaRAMSets, 58 +\par avlblQdmaChannels, 58 +\par avlblTccs, 58 +\par initParam, 57 +\par paramInitRequired, 58 +\par pResMgrObjHandle, 58 +\par regModificationRequired, 59 +\par shadowRegs, 57 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_InstanceInitConfig, 60 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 ownDmaChannels, 61 +\par ownPaRAMSets, 61 +\par ownQdmaChannels, 61 +\par ownTccs, 61 +\par resvdDmaChannels, 62 +\par resvdPaRAMSets, 62 +\par resvdQdmaChannels, 62 +\par resvdTccs, 62 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_Ioctl +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 44 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_IOCTL_GET_GBL_REG_MODIFY_OPTION +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 31 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_IOCTL_GET_PARAM_CLEAR_OPTION +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 31 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_IOCTL_SET_GBL_REG_MODIFY_OPTION +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 31 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_IOCTL_SET_PARAM_CLEAR_OPTION +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_IoctlCmd +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 30 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_LINK_CH_MAX_VAL +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMIntBoundVals, 50 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_LINK_CH_MIN_VAL +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMIntBoundVals, 50 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_LOG_CH_MAX_VAL +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMIntBoundVals, 50 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_mapEdmaChannel +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 45 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_mapQdmaChannel +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 45 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_MiscParam, 63 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 isSlave, 63 +\par param, 63 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_Obj, 64 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 gblCfgParams, 64 +\par numOpens, 64 +\par phyCtrllerInstId, 64 +\par state, 64 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_ObjState +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgrIntObjMaint, 49 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_open +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMMain, 13 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_OPENED +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgrIntObjMaint, 49 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_OPT_TCC_CLR_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3resmgr.h, 213 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_OPT_TCC_SET_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3resmgr.h, 213 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_Param, 66 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 gblerrCbParams, 67 +\par isMaster, 66 +\par regionId, 66 +\par regionInitEnable, 67 +\par rmInstInitConfig, 66 +\par rmSemHandle, 67 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_PARAM_ANY +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr, 27 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3resmgr.h, 213 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_ParamentryRegs, 68 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 A_B_CNT, 68 +\par LINK_BCNTRLD, 69 +\par OPT, 68 +\par SRC_DST_BIDX, 69 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_PaRAMRegs, 70 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 opt, 71 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_QCH_PARAM_CLR_MASK +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 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+\lang1024\langfe1024\noproof\insrsid7370340 edma3resmgr.h, 214 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_QDMA_CH_MAX_VAL +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMIntBoundVals, 50 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 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+\lang1024\langfe1024\noproof\insrsid7370340 edma3MemCpy +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3resmgr.c, 205 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3MemSet +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3resmgr.c, 205 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3NumPaRAMSets +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3resmgr.c, 209 +\par edma3resmgr.h, 214 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3OsProtectEntry +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 79 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3OsProtectExit +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 80 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3OsSemGive +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 80 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3OsSemTake +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 80 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3QdmaChTccMapping +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3resmgr.c, 209 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3RegionId +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3resmgr.c, 209 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgr +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_allocContiguousResource, 32 +\par EDMA3_RM_allocLogicalChannel, 33 +\par EDMA3_RM_allocResource, 37 +\par EDMA3_RM_CC_PHY_ADDR, 28 +\par EDMA3_RM_CH_NO_PARAM_MAP, 27 +\par EDMA3_RM_CH_NO_TCC_MAP, 27 +\par EDMA3_RM_checkAndClearTcc, 38 +\par EDMA3_RM_Cntrlr_PhyAddr, 28 +\par EDMA3_RM_DMA_CHANNEL_ANY, 27 +\par EDMA3_RM_freeContiguousResource, 39 +\par EDMA3_RM_freeLogicalChannel, 40 +\par EDMA3_RM_freeResource, 40 +\par EDMA3_RM_getBaseAddress, 41 +\par EDMA3_RM_getCCRegister, 42 +\par EDMA3_RM_getGblConfigParams, 42 +\par EDMA3_RM_getInstanceInitCfg, 43 +\par EDMA3_RM_getPaRAM, 43 +\par EDMA3_RM_getPaRAMPhyAddr, 43 +\par EDMA3_RM_HW_CHANNEL_EVENT, 28 +\par EDMA3_RM_HW_CHANNEL_EVENT_0, 28 +\par EDMA3_RM_HW_CHANNEL_EVENT_1, 28 +\par EDMA3_RM_HW_CHANNEL_EVENT_10, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_11, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_12, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_13, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_14, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_15, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_16, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_17, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_18, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_19, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_2, 28 +\par EDMA3_RM_HW_CHANNEL_EVENT_20, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_21, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_22, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_23, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_24, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_25, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_26, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_27, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_28, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_29, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_3, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_30, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_31, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_32, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_33, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_34, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_35, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_36, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_37, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_38, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_39, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_4, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_40, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_41, 30 +\par EDMA3_RM_HW_CHANNEL_EVENT_42, 30 +\par EDMA3_RM_HW_CHANNEL_EVENT_43, 30 +\par EDMA3_RM_HW_CHANNEL_EVENT_44, 30 +\par EDMA3_RM_HW_CHANNEL_EVENT_45, 30 +\par EDMA3_RM_HW_CHANNEL_EVENT_46, 30 +\par EDMA3_RM_HW_CHANNEL_EVENT_47, 30 +\par EDMA3_RM_HW_CHANNEL_EVENT_48, 30 +\par EDMA3_RM_HW_CHANNEL_EVENT_49, 30 +\par EDMA3_RM_HW_CHANNEL_EVENT_5, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_50, 30 +\par EDMA3_RM_HW_CHANNEL_EVENT_51, 30 +\par EDMA3_RM_HW_CHANNEL_EVENT_52, 30 +\par EDMA3_RM_HW_CHANNEL_EVENT_53, 30 +\par EDMA3_RM_HW_CHANNEL_EVENT_54, 30 +\par EDMA3_RM_HW_CHANNEL_EVENT_55, 30 +\par EDMA3_RM_HW_CHANNEL_EVENT_56, 30 +\par EDMA3_RM_HW_CHANNEL_EVENT_57, 30 +\par EDMA3_RM_HW_CHANNEL_EVENT_58, 30 +\par EDMA3_RM_HW_CHANNEL_EVENT_59, 30 +\par EDMA3_RM_HW_CHANNEL_EVENT_6, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_60, 30 +\par EDMA3_RM_HW_CHANNEL_EVENT_61, 30 +\par EDMA3_RM_HW_CHANNEL_EVENT_62, 30 +\par EDMA3_RM_HW_CHANNEL_EVENT_63, 30 +\par EDMA3_RM_HW_CHANNEL_EVENT_7, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_8, 29 +\par EDMA3_RM_HW_CHANNEL_EVENT_9, 29 +\par EDMA3_RM_Ioctl, 44 +\par EDMA3_RM_IOCTL_GET_GBL_REG_MODIFY_OPTION, 31 +\par EDMA3_RM_IOCTL_GET_PARAM_CLEAR_OPTION, 31 +\par EDMA3_RM_IOCTL_SET_GBL_REG_MODIFY_OPTION, 31 +\par EDMA3_RM_IOCTL_SET_PARAM_CLEAR_OPTION, 30 +\par EDMA3_RM_IoctlCmd, 30 +\par EDMA3_RM_mapEdmaChannel, 45 +\par EDMA3_RM_mapQdmaChannel, 45 +\par EDMA3_RM_PARAM_ANY, 27 +\par EDMA3_RM_QDMA_CHANNEL_ANY, 27 +\par EDMA3_RM_QDMA_TRIG_ACNT_BCNT, 31 +\par EDMA3_RM_QDMA_TRIG_CCNT, 32 +\par EDMA3_RM_QDMA_TRIG_DEFAULT, 32 +\par EDMA3_RM_QDMA_TRIG_DST, 31 +\par EDMA3_RM_QDMA_TRIG_LINK_BCNTRLD, 31 +\par EDMA3_RM_QDMA_TRIG_OPT, 31 +\par EDMA3_RM_QDMA_TRIG_SRC, 31 +\par EDMA3_RM_QDMA_TRIG_SRC_DST_BIDX, 31 +\par EDMA3_RM_QDMA_TRIG_SRC_DST_CIDX, 31 +\par EDMA3_RM_QdmaTrigWord, 31 +\par EDMA3_RM_setCCRegister, 46 +\par EDMA3_RM_setPaRAM, 46 +\par EDMA3_RM_TC0_PHY_ADDR, 28 +\par EDMA3_RM_TC1_PHY_ADDR, 28 +\par EDMA3_RM_TC2_PHY_ADDR, 28 +\par EDMA3_RM_TC3_PHY_ADDR, 28 +\par EDMA3_RM_TC4_PHY_ADDR, 28 +\par EDMA3_RM_TC5_PHY_ADDR, 28 +\par EDMA3_RM_TC6_PHY_ADDR, 28 +\par EDMA3_RM_TC7_PHY_ADDR, 28 +\par EDMA3_RM_TCC_ANY, 28 +\par EDMA3_RM_waitAndClearTcc, 47 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3resmgr.c, 199 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 allocAnyContigRes, 203 +\par allocatedTCCs, 208 +\par contiguousDmaRes, 208 +\par contiguousParamRes, 208 +\par contiguousQdmaRes, 208 +\par contiguousTccRes, 208 +\par EDMA3_MAX_RM_INSTANCES, 208 +\par EDMA3_RM_RES_CLEAR_ERROR_STATUS_FOR_ALL_CHANNELS, 203 +\par edma3CCErrHandler, 203 +\par edma3ComplHandler, 204 +\par edma3DmaChTccMapping, 208 +\par edma3GblCfgParams, 209 +\par edma3GlobalRegionInit, 205 +\par edma3IntrParams, 209 +\par edma3MemCpy, 205 +\par edma3MemSet, 205 +\par edma3NumPaRAMSets, 209 +\par edma3QdmaChTccMapping, 209 +\par edma3RegionId, 209 +\par edma3RmChBoundRes, 209 +\par edma3ShadowRegionInit, 206 +\par edma3TCErrHandler, 206 +\par findBit, 206 +\par findBitInWord, 207 +\par gblChngAllocContigRes, 207 +\par lisrEdma3CCErrHandler0, 207 +\par lisrEdma3ComplHandler0, 207 +\par lisrEdma3TC0ErrHandler0, 207 +\par masterExists, 210 +\par resMgrInstance, 210 +\par resMgrObj, 210 +\par userInitConfig, 210 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3resmgr.h, 211 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_DCH_PARAM_CLR_MASK, 213 +\par EDMA3_RM_DCH_PARAM_SET_MASK, 213 +\par EDMA3_RM_OPT_TCC_CLR_MASK, 213 +\par EDMA3_RM_OPT_TCC_SET_MASK, 213 +\par EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD, 213 +\par EDMA3_RM_QCH_PARAM_CLR_MASK, 213 +\par EDMA3_RM_QCH_PARAM_SET_MASK, 213 +\par EDMA3_RM_QCH_TRWORD_CLR_MASK, 213 +\par EDMA3_RM_QCH_TRWORD_SET_MASK, 214 +\par EDMA3_RM_QUEPRI_CLR_MASK, 214 +\par EDMA3_RM_QUEPRI_SET_MASK, 214 +\par EDMA3_RM_QUEWMTHR_CLR_MASK, 214 +\par EDMA3_RM_QUEWMTHR_SET_MASK, 214 +\par EDMA3_RM_SET_ALL_BITS, 214 +\par edma3NumPaRAMSets, 214 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResMgrIntObjMaint +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_CLOSED, 49 +\par EDMA3_RM_CREATED, 49 +\par EDMA3_RM_DELETED, 49 +\par EDMA3_RM_ObjState, 49 +\par EDMA3_RM_OPENED, 49 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3ResType +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_RES_DMA_CHANNEL, 10 +\par EDMA3_RM_RES_PARAM_SET, 10 +\par EDMA3_RM_RES_QDMA_CHANNEL, 10 +\par EDMA3_RM_RES_TCC, 10 +\par EDMA3_RM_ResType, 9 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3RmChBoundRes +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3resmgr.c, 209 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMErrCode +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_E_ALL_RES_NOT_AVAILABLE, 22 +\par EDMA3_RM_E_BASE, 22 +\par EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED, 22 +\par EDMA3_RM_E_FEATURE_UNSUPPORTED, 22 +\par EDMA3_RM_E_INVALID_PARAM, 22 +\par EDMA3_RM_E_INVALID_STATE, 22 +\par EDMA3_RM_E_MAX_RM_INST_OPENED, 22 +\par EDMA3_RM_E_OBJ_NOT_CLOSED, 23 +\par EDMA3_RM_E_OBJ_NOT_DELETED, 23 +\par EDMA3_RM_E_OBJ_NOT_OPENED, 23 +\par EDMA3_RM_E_RES_ALREADY_FREE, 23 +\par EDMA3_RM_E_RES_NOT_ALLOCATED, 23 +\par EDMA3_RM_E_RES_NOT_OWNED, 23 +\par EDMA3_RM_E_RM_MASTER_ALREADY_EXISTS, 23 +\par EDMA3_RM_E_SEMAPHORE, 23 +\par EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE, 23 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMIntBoundVals +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_DMA_CH_MAX_VAL, 50 +\par EDMA3_RM_LINK_CH_MAX_VAL, 50 +\par EDMA3_RM_LINK_CH_MIN_VAL, 50 +\par EDMA3_RM_LOG_CH_MAX_VAL, 50 +\par EDMA3_RM_QDMA_CH_MAX_VAL, 50 +\par EDMA3_RM_QDMA_CH_MIN_VAL, 50 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMIntrMgrChannel +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_registerTccCb, 8 +\par EDMA3_RM_TccCallback, 8 +\par EDMA3_RM_unregisterTccCb, 8 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMMain +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_close, 11 +\par EDMA3_RM_create, 12 +\par EDMA3_RM_delete, 13 +\par EDMA3_RM_EventQueue, 11 +\par EDMA3_RM_open, 13 +\par EDMA3_RM_RegionId, 11 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Edma3RMStatus +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_E_CC_DMA_EVT_MISS, 7 +\par EDMA3_RM_E_CC_QDMA_EVT_MISS, 7 +\par EDMA3_RM_E_CC_QUE_THRES_EXCEED, 6 +\par EDMA3_RM_E_CC_TCC, 6 +\par EDMA3_RM_E_TC_INVALID_ADDR, 6 +\par EDMA3_RM_E_TC_MEM_LOCATION_READ_ERROR, 6 +\par EDMA3_RM_E_TC_MEM_LOCATION_WRITE_ERROR, 6 +\par EDMA3_RM_E_TC_TR_ERROR, 6 +\par EDMA3_RM_GblErrCallback, 6 +\par EDMA3_RM_GlobalError, 6 +\par EDMA3_RM_TccStatus, 7 +\par EDMA3_RM_XFER_COMPLETE, 7 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3ShadowRegionInit +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3resmgr.c, 206 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3TCErrHandler +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3resmgr.c, 206 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Error Codes, 15 +\par evtQPri +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_GblConfigParams, 54 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 evtQueueWaterMarkLvl +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_GblConfigParams, 54 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 FALSE +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 78 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 findBit +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3resmgr.c, 206 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 findBitInWord +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3resmgr.c, 207 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 gblCfgParams +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_Obj, 64 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 gblChngAllocContigRes +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3resmgr.c, 207 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 gblerrCb +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_GblErrCallbackParams, 56 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 gblerrCbParams +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_Param, 67 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 gblerrData +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_GblErrCallbackParams, 56 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 globalRegs +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_GblConfigParams, 54 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 initParam +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_Instance, 57 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Instance Wide Interface, 5 +\par Interface Definition for EDMA3 Resource Manager Layer, 10 +\par Internal Interface Definition for Resource Manager, 48 +\par isMaster +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_Param, 66 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 isSlave +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_MiscParam, 63 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 LINK_BCNTRLD +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_ParamentryRegs, 69 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 lisrEdma3CCErrHandler0 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 81 +\par edma3resmgr.c, 207 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 lisrEdma3ComplHandler0 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 81 +\par edma3resmgr.c, 207 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 lisrEdma3TC0ErrHandler0 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 81 +\par edma3resmgr.c, 207 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 lisrEdma3TC1ErrHandler0 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 81 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 lisrEdma3TC2ErrHandler0 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 81 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 lisrEdma3TC3ErrHandler0 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 81 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 lisrEdma3TC4ErrHandler0 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 81 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 lisrEdma3TC5ErrHandler0 +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 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\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3resmgr.c, 210 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 MAX_EDMA3_RM_INSTANCES +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_rm_gbl_data.c, 197 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 MEM_PROTECTION_EXISTENCE +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_da830_cfg.c, 85 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 memProtectionExists +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_GblConfigParams, 54 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 NULL +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_common.h, 78 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 NUM_DMA_CHANNELS +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_da830_cfg.c, 85 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 NUM_EVENT_QUEUE +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_da830_cfg.c, 85 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 NUM_PARAM_SETS +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_da830_cfg.c, 85 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 NUM_QDMA_CHANNELS +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_da830_cfg.c, 85 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 NUM_REGION +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_da830_cfg.c, 85 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 NUM_TC +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_da830_cfg.c, 85 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 NUM_TCC +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_da830_cfg.c, 85 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 numDmaChannels +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_GblConfigParams, 53 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 numEvtQueue +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_GblConfigParams, 53 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 numOpens +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_Obj, 64 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 numPaRAMSets +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_GblConfigParams, 53 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 numQdmaChannels +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_GblConfigParams, 53 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 numRegions +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_GblConfigParams, 53 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 numTccs +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_GblConfigParams, 53 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 numTcs +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_GblConfigParams, 53 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Object Maintenance, 49 +\par opt +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_PaRAMRegs, 71 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 OPT +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_ParamentryRegs, 68 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 ownDmaChannels +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_InstanceInitConfig, 61 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 ownPaRAMSets +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_InstanceInitConfig, 61 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 ownQdmaChannels +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_InstanceInitConfig, 61 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 ownTccs +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_InstanceInitConfig, 61 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 param +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_MiscParam, 63 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 paRAMId +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_ChBoundResources, 51 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 paramInitRequired +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_Instance, 58 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 phyCtrllerInstId +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_Obj, 64 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 pResMgrObjHandle +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_Instance, 58 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 regionId +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_Param, 66 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 regionInitEnable +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_Param, 67 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 regModificationRequired +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_Instance, 59 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 resId +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_ResDesc, 72 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 resMgrInstance +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_rm_gbl_data.c, 198 +\par edma3resmgr.c, 210 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 resMgrInstanceArray +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_rm_gbl_data.c, 198 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 resMgrObj +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3resmgr.c, 210 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 Resource Type, 9 +\par resvdDmaChannels +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_InstanceInitConfig, 62 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 resvdPaRAMSets +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_InstanceInitConfig, 62 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 resvdQdmaChannels +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_InstanceInitConfig, 62 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 resvdTccs +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_InstanceInitConfig, 62 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 rmInstInitConfig +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_Param, 66 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 rmSemHandle +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_Param, 67 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 shadowRegs +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_Instance, 57 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 SRC_DST_BIDX +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_ParamentryRegs, 69 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 state +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 EDMA3_RM_Obj, 64 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 TC0_BASE_ADDRESS +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_da830_cfg.c, 85 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 TC0_ERROR_INT +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_da830_cfg.c, 85 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 TC1_BASE_ADDRESS +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_da830_cfg.c, 85 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 TC1_ERROR_INT +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_da830_cfg.c, 85 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 TC2_BASE_ADDRESS +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_da830_cfg.c, 85 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 TC2_ERROR_INT +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_da830_cfg.c, 85 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 TC3_BASE_ADDRESS +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_da830_cfg.c, 85 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 TC3_ERROR_INT +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_da830_cfg.c, 86 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 TC4_BASE_ADDRESS +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_da830_cfg.c, 86 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 TC4_ERROR_INT +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 edma3_da830_cfg.c, 86 +\par }\pard\plain \ltrpar\s84\ql \fi-200\li200\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 +\lang1024\langfe1024\noproof\insrsid7370340 TC5_BASE_ADDRESS +\par }\pard\plain \ltrpar\s85\ql \fi-200\li400\ri0\widctlpar\tqr\tldot\tx3950\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 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+\fs24\lang1024\langfe1024\noproof\insrsid7370340 \sect }\sectd \ltrsect\sbknone\linex0\sectdefaultcl\sectrsid7370340\sftnbj \pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 +\fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 }}\pard\plain \ltrpar\ql \li0\ri0\nowidctlpar\wrapdefault\faauto\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 \sectd +\sbknone\linex0\sectdefaultcl\sectrsid7370340\sftnbj {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7370340 +\par }} \ No newline at end of file diff --git a/packages/ti/sdo/edma3/rm/docs/html/annotated.html b/packages/ti/sdo/edma3/rm/docs/html/annotated.html new file mode 100644 index 0000000..a28dfd9 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/annotated.html @@ -0,0 +1,45 @@ + + +EDMA3 Resource Manager: Data Structures + + + + + +
+

Data Structures

Here are the data structures with brief descriptions: + + + + + + + + + + + + +
EDMA3_RM_ChBoundResourcesEDMA3 Channel-Bound resources
EDMA3_RM_GblConfigParamsInit-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information
EDMA3_RM_GblErrCallbackParamsGlobal Error Callback parameters
EDMA3_RM_InstanceEDMA3 RM Instance Specific Configuration Structure
EDMA3_RM_InstanceInitConfigInit-time Region Specific Configuration structure for EDMA3 RM, to provide region specific Information
EDMA3_RM_MiscParamUsed to specify the miscellaneous options during Resource Manager Initialization
EDMA3_RM_ObjEDMA3 Hardware Instance Configuration Structure
EDMA3_RM_ParamUsed to Initialize the Resource Manager Instance
EDMA3_RM_ParamentryRegsEDMA3 PaRAM Set
EDMA3_RM_PaRAMRegsEDMA3 PaRAM Set in User Configurable format
EDMA3_RM_ResDescHandle to a Resource
EDMA3_RM_TccCallbackParamsTCC Callback - Caters to channel specific status reporting
+
+
Generated on Thu Oct 16 16:22:42 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/classes.html b/packages/ti/sdo/edma3/rm/docs/html/classes.html new file mode 100644 index 0000000..b8e851d --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/classes.html @@ -0,0 +1,35 @@ + + +EDMA3 Resource Manager: Alphabetical List + + + + + +
+

Data Structure Index

E

+ +
  E  
+		EDMA3_RM_Instance   EDMA3_RM_Obj   EDMA3_RM_PaRAMRegs   
EDMA3_RM_ChBoundResources   EDMA3_RM_InstanceInitConfig   EDMA3_RM_Param   EDMA3_RM_ResDesc   
EDMA3_RM_GblConfigParams   EDMA3_RM_MiscParam   EDMA3_RM_ParamentryRegs   EDMA3_RM_TccCallbackParams   
EDMA3_RM_GblErrCallbackParams   

E

+

+
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Generated on Thu Oct 16 16:21:26 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/edma3__common_8h.html b/packages/ti/sdo/edma3/rm/docs/html/edma3__common_8h.html new file mode 100644 index 0000000..a08a329 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/edma3__common_8h.html @@ -0,0 +1,1030 @@ + + +EDMA3 Resource Manager: edma3_common.h File Reference + + + + + +
+

edma3_common.h File Reference

EDMA3 Common header provides generic defines/typedefs and debugging info. More... +

+ +

+Go to the source code of this file. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Defines

#define EDMA3_RM_DEBUG
#define EDMA3_DRV_DEBUG
#define TRUE   (1u)
#define FALSE   (0u)
#define NULL   0u
#define EDMA3_RM_SOK   (0u)
#define EDMA3_DRV_SOK   (0u)
#define EDMA3_OSSEM_NO_TIMEOUT   (-1)
#define EDMA3_MAX_EDMA3_INSTANCES   (1u)
#define EDMA3_MAX_DMA_CH   (64u)
#define EDMA3_MAX_QDMA_CH   (8u)
#define EDMA3_MAX_PARAM_SETS   (512u)
#define EDMA3_MAX_LOGICAL_CH
#define EDMA3_MAX_TCC   (64u)
#define EDMA3_MAX_EVT_QUE   (8u)
#define EDMA3_MAX_TC   (8u)
#define EDMA3_MAX_REGIONS   (8u)
#define EDMA3_MAX_DMA_CHAN_DWRDS   (EDMA3_MAX_DMA_CH / 32u)
#define EDMA3_MAX_QDMA_CHAN_DWRDS   (1u)
#define EDMA3_MAX_PARAM_DWRDS   (EDMA3_MAX_PARAM_SETS / 32u)
#define EDMA3_MAX_TCC_DWRDS   (EDMA3_MAX_TCC / 32u)
#define EDMA3_OS_PROTECT_INTERRUPT   1
#define EDMA3_OS_PROTECT_SCHEDULER   2
#define EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION   3
#define EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR   4
#define EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR   5

Typedefs

typedef int EDMA3_RM_Result
typedef int EDMA3_DRV_Result
typedef void * EDMA3_RM_Handle
typedef void * EDMA3_DRV_Handle
typedef void * EDMA3_OS_Sem_Handle

Functions

void lisrEdma3ComplHandler0 (unsigned int arg)
void lisrEdma3CCErrHandler0 (unsigned int arg)
void lisrEdma3TC0ErrHandler0 (unsigned int arg)
void lisrEdma3TC1ErrHandler0 (unsigned int arg)
void lisrEdma3TC2ErrHandler0 (unsigned int arg)
void lisrEdma3TC3ErrHandler0 (unsigned int arg)
void lisrEdma3TC4ErrHandler0 (unsigned int arg)
void lisrEdma3TC5ErrHandler0 (unsigned int arg)
void lisrEdma3TC6ErrHandler0 (unsigned int arg)
void lisrEdma3TC7ErrHandler0 (unsigned int arg)
void edma3OsProtectEntry (int level, unsigned int *intState)
 EDMA3 OS Protect Entry.
void edma3OsProtectExit (int level, unsigned int intState)
 EDMA3 OS Protect Exit.
EDMA3_DRV_Result edma3OsSemTake (EDMA3_OS_Sem_Handle hSem, int mSecTimeout)
 EDMA3 OS Semaphore Take.
EDMA3_DRV_Result edma3OsSemGive (EDMA3_OS_Sem_Handle hSem)
 EDMA3 OS Semaphore Give.
+

Detailed Description

+EDMA3 Common header provides generic defines/typedefs and debugging info. +

+This file contains the generic defines and typedefs and the debugging info that are common across interfaces of EDMA Res Mgr and EDMA Driver and visible to the application.

+(C) Copyright 2006, Texas Instruments, Inc

+

Version:
0.2.0 Anuj Aggarwal - Created 0.2.1 Anuj Aggarwal - Modified it for more run time configuration.
    +
  • Made EDMA3 package OS independent. 0.2.2 Anuj Aggarwal - Critical section handling code modification. Uses semaphore and interrupts disabling mechanism for resource sharing. 0.3.0 Anuj Aggarwal - Renamed EDMA3_DVR to EDMA3_DRV
  • IPR bit clearing in RM ISR issue fixed.
  • Sample application made generic 0.3.1 Anuj Aggarwal - Added DMA/QDMA Channel to TCC mapping, to fix QDMA missed event issue. 0.3.2 Anuj Aggarwal - Added support for POLL mode
  • Added a new API to modify the CC Register. 1.0.0 Anuj Aggarwal - Fixed resource allocation related bugs. 1.0.0.1 Anuj Aggarwal - Fixed spurious missed event generation related bug. 1.0.0.2 Anuj Aggarwal - Made the EDMA3 package RTSC compliant. 1.0.0.3 Anuj Aggarwal - Changed the directory structure as per RTSC standard. 1.01.00.01 Anuj Aggarwal - a) Added new APIs to allocate logical channels b) Created EDMA3 config files for different platforms c) Misc changes 1.02.00.01 Anuj Aggarwal - a) Added DM6467 support b) Fixed some MRs 1.03.00.01 Anuj Aggarwal - a) Added non-RTSC PJT files b) IOCTL Interface added. c) Fixed some MRs. 1.04 Anuj Aggarwal - a) Added new IOCTLs and APIs. b) Number of maximum Resource Manager Instances is configurable. c) Header files modified to have extern "C" declarations.
+
+

Define Documentation

+ +
+
+ + + + +
#define EDMA3_DRV_DEBUG
+
+
+ +

+define to enable/disable EDMA3 Driver debug messages +

+

+ +

+
+ + + + +
#define EDMA3_DRV_SOK   (0u)
+
+
+ +

+EDMA3 Driver Result OK +

+

+ +

+
+ + + + +
#define EDMA3_MAX_DMA_CH   (64u)
+
+
+ +

+Maximum DMA channels supported by the EDMA3 Controller +

Referenced by allocAnyContigRes(), and EDMA3_RM_freeLogicalChannel().

+ +
+

+ +

+
+ + + + +
#define EDMA3_MAX_DMA_CHAN_DWRDS   (EDMA3_MAX_DMA_CH / 32u)
+
+
+ +

+Maximum Words (4-bytes region) required for the book-keeping information specific to the maximum possible DMA channels. +

+

+ +

+
+ + + + +
#define EDMA3_MAX_EDMA3_INSTANCES   (1u)
+
+
+ +

+Defines used to support the maximum resources supported by the EDMA3 controller. These are used to allocate the maximum memory for different data structures of the EDMA3 Driver and Resource Manager. Maximum EDMA3 Controllers on the SoC +

Referenced by EDMA3_RM_create(), EDMA3_RM_delete(), EDMA3_RM_getGblConfigParams(), EDMA3_RM_open(), and edma3GlobalRegionInit().

+ +
+

+ +

+
+ + + + +
#define EDMA3_MAX_EVT_QUE   (8u)
+
+
+ +

+Maximum Event Queues supported by the EDMA3 Controller +

+

+ +

+
+ + + + +
#define EDMA3_MAX_LOGICAL_CH
+
+
+ +

+Value:

(EDMA3_MAX_DMA_CH + \
+                                                 EDMA3_MAX_PARAM_SETS + \
+                                                 EDMA3_MAX_QDMA_CH)
+
Maximum Logical channels supported by the EDMA3 Package +

Referenced by EDMA3_RM_create().

+ +
+

+ +

+
+ + + + +
#define EDMA3_MAX_PARAM_DWRDS   (EDMA3_MAX_PARAM_SETS / 32u)
+
+
+ +

+Maximum Words (4-bytes region) required for the book-keeping information specific to the maximum possible PaRAM Sets. +

+

+ +

+
+ + + + +
#define EDMA3_MAX_PARAM_SETS   (512u)
+
+
+ +

+Maximum PaRAM Sets supported by the EDMA3 Controller +

Referenced by EDMA3_RM_allocLogicalChannel().

+ +
+

+ +

+
+ + + + +
#define EDMA3_MAX_QDMA_CH   (8u)
+
+
+ +

+Maximum QDMA channels supported by the EDMA3 Controller +

Referenced by allocAnyContigRes(), EDMA3_RM_allocLogicalChannel(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_getPaRAM(), EDMA3_RM_getPaRAMPhyAddr(), and EDMA3_RM_setPaRAM().

+ +
+

+ +

+
+ + + + +
#define EDMA3_MAX_QDMA_CHAN_DWRDS   (1u)
+
+
+ +

+Maximum Words (4-bytes region) required for the book-keeping information specific to the maximum possible QDMA channels. +

+

+ +

+
+ + + + +
#define EDMA3_MAX_REGIONS   (8u)
+
+
+ +

+Maximum Shadow Regions supported by the EDMA3 Controller +

Referenced by EDMA3_RM_close().

+ +
+

+ +

+
+ + + + +
#define EDMA3_MAX_TC   (8u)
+
+
+ +

+Maximum Transfer Controllers supported by the EDMA3 Controller +

+

+ +

+
+ + + + +
#define EDMA3_MAX_TCC   (64u)
+
+
+ +

+Maximum TCCs (Interrupt Channels) supported by the EDMA3 Controller +

Referenced by allocAnyContigRes(), EDMA3_RM_create(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_unregisterTccCb(), and edma3CCErrHandler().

+ +
+

+ +

+
+ + + + +
#define EDMA3_MAX_TCC_DWRDS   (EDMA3_MAX_TCC / 32u)
+
+
+ +

+Maximum Words (4-bytes region) required for the book-keeping information specific to the maximum possible TCCs. +

+

+ +

+
+ + + + +
#define EDMA3_OS_PROTECT_INTERRUPT   1
+
+
+ +

+Defines for the level of OS protection needed when calling edma3OsProtectEntry() Protection from All Interrupts required +

Referenced by EDMA3_RM_close(), EDMA3_RM_freeResource(), EDMA3_RM_open(), and edma3ShadowRegionInit().

+ +
+

+ +

+
+ + + + +
#define EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR   4
+
+
+ +

+Protection from EDMA3 CC Error Interrupt required +

Referenced by edma3CCErrHandler().

+ +
+

+ +

+
+ + + + +
#define EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR   5
+
+
+ +

+Protection from EDMA3 TC Error Interrupt required +

Referenced by edma3TCErrHandler().

+ +
+

+ +

+
+ + + + +
#define EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION   3
+
+
+ +

+Protection from EDMA3 Transfer Completion Interrupt required +

Referenced by edma3ComplHandler().

+ +
+

+ +

+
+ + + + +
#define EDMA3_OS_PROTECT_SCHEDULER   2
+
+
+ +

+Protection from scheduling required +

+

+ +

+
+ + + + +
#define EDMA3_OSSEM_NO_TIMEOUT   (-1)
+
+
+ +

+Blocking call without timeout +

Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), and EDMA3_RM_setCCRegister().

+ +
+

+ +

+
+ + + + +
#define EDMA3_RM_DEBUG
+
+
+ +

+define to enable/disable Resource Manager debug messages +

+

+ +

+
+ + + + +
#define EDMA3_RM_SOK   (0u)
+
+
+ +

+EDMA3 Resource Manager Result OK +

Referenced by allocAnyContigRes(), EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocLogicalChannel(), EDMA3_RM_allocResource(), EDMA3_RM_checkAndClearTcc(), EDMA3_RM_close(), EDMA3_RM_create(), EDMA3_RM_delete(), EDMA3_RM_freeContiguousResource(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_freeResource(), EDMA3_RM_getBaseAddress(), EDMA3_RM_getCCRegister(), EDMA3_RM_getGblConfigParams(), EDMA3_RM_getInstanceInitCfg(), EDMA3_RM_getPaRAM(), EDMA3_RM_getPaRAMPhyAddr(), EDMA3_RM_Ioctl(), EDMA3_RM_mapEdmaChannel(), EDMA3_RM_mapQdmaChannel(), EDMA3_RM_open(), EDMA3_RM_registerTccCb(), EDMA3_RM_setCCRegister(), EDMA3_RM_setPaRAM(), EDMA3_RM_unregisterTccCb(), EDMA3_RM_waitAndClearTcc(), findBit(), and gblChngAllocContigRes().

+ +
+

+ +

+
+ + + + +
#define FALSE   (0u)
+
+
+ +

+FALSE +

Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_checkAndClearTcc(), EDMA3_RM_close(), EDMA3_RM_create(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_freeResource(), EDMA3_RM_mapEdmaChannel(), EDMA3_RM_mapQdmaChannel(), and EDMA3_RM_waitAndClearTcc().

+ +
+

+ +

+
+ + + + +
#define NULL   0u
+
+
+ +

+Define for NULL values +

Referenced by allocAnyContigRes(), EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocLogicalChannel(), EDMA3_RM_allocResource(), EDMA3_RM_checkAndClearTcc(), EDMA3_RM_close(), EDMA3_RM_create(), EDMA3_RM_delete(), EDMA3_RM_freeContiguousResource(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_freeResource(), EDMA3_RM_getBaseAddress(), EDMA3_RM_getCCRegister(), EDMA3_RM_getGblConfigParams(), EDMA3_RM_getInstanceInitCfg(), EDMA3_RM_getPaRAM(), EDMA3_RM_getPaRAMPhyAddr(), EDMA3_RM_Ioctl(), EDMA3_RM_mapEdmaChannel(), EDMA3_RM_mapQdmaChannel(), EDMA3_RM_open(), EDMA3_RM_registerTccCb(), EDMA3_RM_setCCRegister(), EDMA3_RM_setPaRAM(), EDMA3_RM_unregisterTccCb(), EDMA3_RM_waitAndClearTcc(), edma3CCErrHandler(), edma3ComplHandler(), edma3GlobalRegionInit(), edma3MemCpy(), edma3MemSet(), edma3ShadowRegionInit(), edma3TCErrHandler(), and gblChngAllocContigRes().

+ +
+

+ +

+
+ + + + +
#define TRUE   (1u)
+
+
+ +

+Debug mechanism used for Resource Manager Debug mechanism used for EDMA Driver Defines for boolean variables TRUE +

Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocLogicalChannel(), EDMA3_RM_allocResource(), EDMA3_RM_checkAndClearTcc(), EDMA3_RM_close(), EDMA3_RM_create(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_freeResource(), EDMA3_RM_mapEdmaChannel(), EDMA3_RM_open(), edma3CCErrHandler(), edma3ComplHandler(), and gblChngAllocContigRes().

+ +
+

+

Typedef Documentation

+ +
+
+ + + + +
typedef void* EDMA3_DRV_Handle
+
+
+ +

+EDMA3 Driver Handle. It will be returned from EDMA3_DRV_open() and will be used to call other EDMA3 Driver APIs. +

+

+ +

+
+ + + + +
typedef int EDMA3_DRV_Result
+
+
+ +

+EDMA3_DRV Result - return value of a function +

+

+ +

+
+ + + + +
typedef void* EDMA3_OS_Sem_Handle
+
+
+ +

+OS specific Semaphore Handle. Used to acquire/free the semaphore, used for sharing of resources among multiple users. +

+

+ +

+
+ + + + +
typedef void* EDMA3_RM_Handle
+
+
+ +

+EDMA3 Resource Manager Handle. It will be returned from EDMA3_RM_open() and will be used to call other Resource Manager APIs. +

+

+ +

+
+ + + + +
typedef int EDMA3_RM_Result
+
+
+ +

+EDMA3_RM Result - return value of a function +

+

+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void edma3OsProtectEntry (int  level,
unsigned int *  intState 
)
+
+
+ +

+EDMA3 OS Protect Entry. +

+Critical section entry and exit functions (OS dependent) should be implemented by the application for proper linking with the EDMA3 Driver and/or EDMA3 Resource Manager. Without the definitions being provided, the image wonÂ’t get linked properly.

+It is possible that for some regions of code, user needs ultimate degree of protection where some or all external interrupts are blocked, essentially locking out the CPU exclusively for the critical section of code. On the other hand, user may wish to merely avoid thread or task switch from occuring inside said region of code, but he may wish to entertain ISRs to run if so required.

+Depending on the underlying OS, the number of levels of protection offered may vary. At the least, these basic levels of protection are supported --

    +
  • EDMA3_OS_PROTECT_INTERRUPT - Mask interrupts globally. This has real-time implications and must be used with descretion.
+

+

    +
  • EDMA3_OS_PROTECT_SCHEDULER - Only turns off Kernel scheduler completely, but still allows h/w interrupts from being serviced.
+

+

    +
  • EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION - Mask EDMA3 Transfer Completion Interrupt.
+

+

    +
  • EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR - Mask EDMA3 CC Error Interrupt.
+

+

    +
  • EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR - Mask EDMA3 TC Error Interrupt.
+

+These APIs should be mandatorily implemented ONCE by the global initialization routine or by the user itself. This function saves the current state of protection in 'intState' variable passed by caller, if the protection level is EDMA3_OS_PROTECT_INTERRUPT. It then applies the requested level of protection. For EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION and EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR, variable 'intState' is ignored, and the requested interrupt is disabled. For EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR, '*intState' specifies the Transfer Controller number whose interrupt needs to be disabled.

+

Parameters:
+ + + +
level is numeric identifier of the desired degree of protection.
intState is memory location where current state of protection is saved for future use while restoring it via edma3OsProtectExit() (Only for EDMA3_OS_PROTECT_INTERRUPT protection level).
+
+
Returns:
None
+ +

Referenced by EDMA3_RM_close(), EDMA3_RM_freeResource(), EDMA3_RM_open(), edma3CCErrHandler(), edma3ComplHandler(), edma3ShadowRegionInit(), and edma3TCErrHandler().

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
void edma3OsProtectExit (int  level,
unsigned int  intState 
)
+
+
+ +

+EDMA3 OS Protect Exit. +

+This function undoes the protection enforced to original state as is specified by the variable 'intState' passed, if the protection level is EDMA3_OS_PROTECT_INTERRUPT. For EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION and EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR, variable 'intState' is ignored, and the requested interrupt is enabled. For EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR, 'intState' specifies the Transfer Controller number whose interrupt needs to be enabled.

+

Parameters:
+ + + +
level is numeric identifier of the desired degree of protection.
intState is original state of protection at time when the corresponding edma3OsProtectEntry() was called (Only for EDMA3_OS_PROTECT_INTERRUPT protection level).
+
+
Returns:
None
+ +

Referenced by EDMA3_RM_close(), EDMA3_RM_freeResource(), EDMA3_RM_open(), edma3CCErrHandler(), edma3ComplHandler(), edma3ShadowRegionInit(), and edma3TCErrHandler().

+ +
+

+ +

+
+ + + + + + + + + +
EDMA3_DRV_Result edma3OsSemGive (EDMA3_OS_Sem_Handle  hSem  ) 
+
+
+ +

+EDMA3 OS Semaphore Give. +

+This function gives or relinquishes an already acquired semaphore token

+

Parameters:
+ + +
hSem [IN] is the handle of the specified semaphore
+
+
Returns:
EDMA3_DRV_Result if successful else a suitable error code
+ +

Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), and EDMA3_RM_setCCRegister().

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
EDMA3_DRV_Result edma3OsSemTake (EDMA3_OS_Sem_Handle  hSem,
int  mSecTimeout 
)
+
+
+ +

+EDMA3 OS Semaphore Take. +

+Counting Semaphore related functions (OS dependent) should be implemented by the application for proper linking with the EDMA3 Driver and Resource Manager. The EDMA3 Resource Manager uses these functions for proper sharing of resources (among various users) and assume the implementation of these functions to be provided by the application. Without the definitions being provided, the image wonÂ’t get linked properly. This function takes a semaphore token if available. If a semaphore is unavailable, it blocks currently running thread in wait (for specified duration) for a free semaphore.

+

Parameters:
+ + + +
hSem [IN] is the handle of the specified semaphore
mSecTimeout [IN] is wait time in milliseconds
+
+
Returns:
EDMA3_DRV_Result if successful else a suitable error code
+ +

Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), and EDMA3_RM_setCCRegister().

+ +
+

+ +

+
+ + + + + + + + + +
void lisrEdma3CCErrHandler0 (unsigned int  arg  ) 
+
+
+ +

+EDMA3 CC Error Interrupt Handler ISR Routine +

References edma3CCErrHandler().

+ +
+

+ +

+
+ + + + + + + + + +
void lisrEdma3ComplHandler0 (unsigned int  arg  ) 
+
+
+ +

+EDMA3 ISRs which need to be registered with the underlying OS by the user (Not all TC error ISRs need to be registered, register only for the available Transfer Controllers). EDMA3 Completion Handler ISR Routine +

References edma3ComplHandler().

+ +
+

+ +

+
+ + + + + + + + + +
void lisrEdma3TC0ErrHandler0 (unsigned int  arg  ) 
+
+
+ +

+EDMA3 TC0 Error Interrupt Handler ISR Routine +

References edma3TCErrHandler().

+ +
+

+ +

+
+ + + + + + + + + +
void lisrEdma3TC1ErrHandler0 (unsigned int  arg  ) 
+
+
+ +

+EDMA3 TC1 Error Interrupt Handler ISR Routine +

References edma3TCErrHandler().

+ +
+

+ +

+
+ + + + + + + + + +
void lisrEdma3TC2ErrHandler0 (unsigned int  arg  ) 
+
+
+ +

+EDMA3 TC2 Error Interrupt Handler ISR Routine +

References edma3TCErrHandler().

+ +
+

+ +

+
+ + + + + + + + + +
void lisrEdma3TC3ErrHandler0 (unsigned int  arg  ) 
+
+
+ +

+EDMA3 TC3 Error Interrupt Handler ISR Routine +

References edma3TCErrHandler().

+ +
+

+ +

+
+ + + + + + + + + +
void lisrEdma3TC4ErrHandler0 (unsigned int  arg  ) 
+
+
+ +

+EDMA3 TC4 Error Interrupt Handler ISR Routine +

References edma3TCErrHandler().

+ +
+

+ +

+
+ + + + + + + + + +
void lisrEdma3TC5ErrHandler0 (unsigned int  arg  ) 
+
+
+ +

+EDMA3 TC5 Error Interrupt Handler ISR Routine +

References edma3TCErrHandler().

+ +
+

+ +

+
+ + + + + + + + + +
void lisrEdma3TC6ErrHandler0 (unsigned int  arg  ) 
+
+
+ +

+EDMA3 TC6 Error Interrupt Handler ISR Routine +

References edma3TCErrHandler().

+ +
+

+ +

+
+ + + + + + + + + +
void lisrEdma3TC7ErrHandler0 (unsigned int  arg  ) 
+
+
+ +

+EDMA3 TC7 Error Interrupt Handler ISR Routine +

References edma3TCErrHandler().

+ +
+

+

+
Generated on Thu Oct 16 16:21:27 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/edma3__da830__cfg_8c.html b/packages/ti/sdo/edma3/rm/docs/html/edma3__da830__cfg_8c.html new file mode 100644 index 0000000..811f366 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/edma3__da830__cfg_8c.html @@ -0,0 +1,569 @@ + + +EDMA3 Resource Manager: edma3_da830_cfg.c File Reference + + + + + +
+

edma3_da830_cfg.c File Reference

EDMA3 Driver Adaptation Configuration File (Soc Specific) for DA8xx platform. More... +

+#include <ti/sdo/edma3/rm/edma3_rm.h>
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Defines

#define NUM_DMA_CHANNELS   (32u)
#define NUM_QDMA_CHANNELS   (8u)
#define NUM_TCC   (32u)
#define NUM_PARAM_SETS   (128u)
#define NUM_EVENT_QUEUE   (2u)
#define NUM_TC   (2u)
#define NUM_REGION   (4u)
+#define CHANNEL_MAPPING_EXISTENCE   (0u)
 Channel mapping existence A value of 0 (No channel mapping) implies that there is fixed association for a channel number to a parameter entry number or, in other words, PaRAM entry n corresponds to channel n.
#define MEM_PROTECTION_EXISTENCE   (0u)
#define CC_BASE_ADDRESS   (0x01C00000u)
#define TC0_BASE_ADDRESS   (0x01C08000u)
#define TC1_BASE_ADDRESS   (0x01C08400u)
#define TC2_BASE_ADDRESS   NULL
#define TC3_BASE_ADDRESS   NULL
#define TC4_BASE_ADDRESS   NULL
#define TC5_BASE_ADDRESS   NULL
#define TC6_BASE_ADDRESS   NULL
#define TC7_BASE_ADDRESS   NULL
#define XFER_COMPLETION_INT   (8u)
#define CC_ERROR_INT   (56u)
#define TC0_ERROR_INT   (57u)
#define TC1_ERROR_INT   (58u)
#define TC2_ERROR_INT   (0u)
#define TC3_ERROR_INT   (0u)
#define TC4_ERROR_INT   (0u)
#define TC5_ERROR_INT   (0u)
#define TC6_ERROR_INT   (0u)
#define TC7_ERROR_INT   (0u)
#define DMA_CHANNEL_TO_EVENT_MAPPING_0   (0xCF3FFFFFu)
 Mapping of DMA channels 0-31 to Hardware Events from various peripherals, which use EDMA for data transfer. All channels need not be mapped, some can be free also. 1: Mapped 0: Not mapped.
#define DMA_CHANNEL_TO_EVENT_MAPPING_1   (0x0u)
 Mapping of DMA channels 32-63 to Hardware Events from various peripherals, which use EDMA for data transfer. All channels need not be mapped, some can be free also. 1: Mapped 0: Not mapped.

Variables

EDMA3_RM_GblConfigParams edma3GblCfgParams [EDMA3_MAX_EDMA3_INSTANCES]
 Static Configuration structure for EDMA3 controller, to provide Global SoC specific Information.
+EDMA3_RM_InstanceInitConfig defInstInitConfig [EDMA3_MAX_EDMA3_INSTANCES][NUM_REGION]
 Default Static Region Specific Configuration structure for EDMA3 controller, to provide region specific Information.
+

Detailed Description

+EDMA3 Driver Adaptation Configuration File (Soc Specific) for DA8xx platform. +

+This file contains configuration data for adaptation of EDMA3 RM

+(C) Copyright 2008, Texas Instruments, Inc

+

Version:
0.1 Anuj Aggarwal - Created
+

Define Documentation

+ +
+
+ + + + +
#define CC_BASE_ADDRESS   (0x01C00000u)
+
+
+ +

+Global Register Region of CC Registers +

+

+ +

+
+ + + + +
#define CC_ERROR_INT   (56u)
+
+
+ +

+Interrupt no. for CC Error +

+

+ +

+
+ + + + +
#define DMA_CHANNEL_TO_EVENT_MAPPING_0   (0xCF3FFFFFu)
+
+
+ +

+Mapping of DMA channels 0-31 to Hardware Events from various peripherals, which use EDMA for data transfer. All channels need not be mapped, some can be free also. 1: Mapped 0: Not mapped. +

+This mapping will be used to allocate DMA channels when user passes EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory copy). The same mapping is used to allocate the TCC when user passes EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).

+To allocate more DMA channels or TCCs, one has to modify the event mapping. +

+

+ +

+
+ + + + +
#define DMA_CHANNEL_TO_EVENT_MAPPING_1   (0x0u)
+
+
+ +

+Mapping of DMA channels 32-63 to Hardware Events from various peripherals, which use EDMA for data transfer. All channels need not be mapped, some can be free also. 1: Mapped 0: Not mapped. +

+EDMA channels 22, 23, 28 & 29 which correspond to GPIO bank interrupts will be used for memory-to-memory data transfers, since there are no free dma channels. This mapping will be used to allocate DMA channels when user passes EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory copy). The same mapping is used to allocate the TCC when user passes EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).

+To allocate more DMA channels or TCCs, one has to modify the event mapping. +

+

+ +

+
+ + + + +
#define MEM_PROTECTION_EXISTENCE   (0u)
+
+
+ +

+Existence of memory protection feature +

+

+ +

+
+ + + + +
#define NUM_DMA_CHANNELS   (32u)
+
+
+ +

+Total number of DMA Channels supported by the EDMA3 Controller +

+

+ +

+
+ + + + +
#define NUM_EVENT_QUEUE   (2u)
+
+
+ +

+Total number of Event Queues in the EDMA3 Controller +

+

+ +

+
+ + + + +
#define NUM_PARAM_SETS   (128u)
+
+
+ +

+Total number of PaRAM Sets supported by the EDMA3 Controller +

+

+ +

+
+ + + + +
#define NUM_QDMA_CHANNELS   (8u)
+
+
+ +

+Total number of QDMA Channels supported by the EDMA3 Controller +

+

+ +

+
+ + + + +
#define NUM_REGION   (4u)
+
+
+ +

+Number of Regions on this EDMA3 controller +

+

+ +

+
+ + + + +
#define NUM_TC   (2u)
+
+
+ +

+Total number of Transfer Controllers (TCs) in the EDMA3 Controller +

+

+ +

+
+ + + + +
#define NUM_TCC   (32u)
+
+
+ +

+Total number of TCCs supported by the EDMA3 Controller +

+

+ +

+
+ + + + +
#define TC0_BASE_ADDRESS   (0x01C08000u)
+
+
+ +

+Transfer Controller 0 Registers +

+

+ +

+
+ + + + +
#define TC0_ERROR_INT   (57u)
+
+
+ +

+Interrupt no. for TC 0 Error +

+

+ +

+
+ + + + +
#define TC1_BASE_ADDRESS   (0x01C08400u)
+
+
+ +

+Transfer Controller 1 Registers +

+

+ +

+
+ + + + +
#define TC1_ERROR_INT   (58u)
+
+
+ +

+Interrupt no. for TC 1 Error +

+

+ +

+
+ + + + +
#define TC2_BASE_ADDRESS   NULL
+
+
+ +

+Transfer Controller 2 Registers +

+

+ +

+
+ + + + +
#define TC2_ERROR_INT   (0u)
+
+
+ +

+Interrupt no. for TC 2 Error +

+

+ +

+
+ + + + +
#define TC3_BASE_ADDRESS   NULL
+
+
+ +

+Transfer Controller 3 Registers +

+

+ +

+
+ + + + +
#define TC3_ERROR_INT   (0u)
+
+
+ +

+Interrupt no. for TC 3 Error +

+

+ +

+
+ + + + +
#define TC4_BASE_ADDRESS   NULL
+
+
+ +

+Transfer Controller 4 Registers +

+

+ +

+
+ + + + +
#define TC4_ERROR_INT   (0u)
+
+
+ +

+Interrupt no. for TC 4 Error +

+

+ +

+
+ + + + +
#define TC5_BASE_ADDRESS   NULL
+
+
+ +

+Transfer Controller 5 Registers +

+

+ +

+
+ + + + +
#define TC5_ERROR_INT   (0u)
+
+
+ +

+Interrupt no. for TC 5 Error +

+

+ +

+
+ + + + +
#define TC6_BASE_ADDRESS   NULL
+
+
+ +

+Transfer Controller 6 Registers +

+

+ +

+
+ + + + +
#define TC6_ERROR_INT   (0u)
+
+
+ +

+Interrupt no. for TC 6 Error +

+

+ +

+
+ + + + +
#define TC7_BASE_ADDRESS   NULL
+
+
+ +

+Transfer Controller 7 Registers +

+

+ +

+
+ + + + +
#define TC7_ERROR_INT   (0u)
+
+
+ +

+Interrupt no. for TC 7 Error +

+

+ +

+
+ + + + +
#define XFER_COMPLETION_INT   (8u)
+
+
+ +

+Interrupt no. for Transfer Completion +

+

+

Variable Documentation

+ +
+
+ + + + +
EDMA3_RM_GblConfigParams edma3GblCfgParams[EDMA3_MAX_EDMA3_INSTANCES]
+
+
+ +

+Static Configuration structure for EDMA3 controller, to provide Global SoC specific Information. +

+This configuration info can also be provided by the user at run-time, while calling EDMA3_RM_create (). If not provided at run-time, this info will be taken from the config file "edma3_<PLATFORM_NAME>_cfg.c", for the specified platform. +

+

+

+
Generated on Thu Oct 16 16:21:27 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/edma3__log_8h-source.html b/packages/ti/sdo/edma3/rm/docs/html/edma3__log_8h-source.html new file mode 100644 index 0000000..34d9c2b --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/edma3__log_8h-source.html @@ -0,0 +1,233 @@ + + +EDMA3 Resource Manager: edma3_log.h Source File + + + + + +
Generated on Thu Oct 16 16:21:26 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/edma3__log_8h.html b/packages/ti/sdo/edma3/rm/docs/html/edma3__log_8h.html new file mode 100644 index 0000000..828d655 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/edma3__log_8h.html @@ -0,0 +1,127 @@ + + +EDMA3 Resource Manager: edma3_log.h File Reference + + + + + +
+

edma3_log.h File Reference

EDMA3 logging/tracing service. More... +

+#include <std.h>
+#include <log.h>
+ +

+Go to the source code of this file. + + + + + + + + + + + + + + + + + + + + +

Defines

+#define ARG1(arg1)   (arg1 << 8)
+#define ARG2(arg2)   (arg2 << 16)
+#define ARG3(arg3)   (arg3 << 24)
+#define EDMA3_DVT_DESC(event, arg1, arg2, arg3)   (event | ARG1(arg1) | ARG2(arg2) | ARG3(arg3))
+#define EDMA3_LOG_EVENT   LOG_printf4

Enumerations

enum  EDMA3_logEventType {
+  EDMA3_DVT_eINT, +
+  EDMA3_DVT_eINT_START, +
+  EDMA3_DVT_eINT_END, +
+  EDMA3_DVT_eFUNC, +
+  EDMA3_DVT_eFUNC_START, +
+  EDMA3_DVT_eFUNC_END, +
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Data Structures

struct  EDMA3_CCRL_DraRegs
struct  EDMA3_CCRL_QueevtentryRegs
struct  EDMA3_CCRL_ShadowRegs
struct  EDMA3_CCRL_ParamentryRegs
struct  EDMA3_CCRL_Regs

Defines

+#define EDMA3_CCRL_REV_TYPE_MASK   (0x00FF0000u)
+#define EDMA3_CCRL_REV_TYPE_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_REV_TYPE_RESETVAL   (0x00000007u)
+#define EDMA3_CCRL_REV_CLASS_MASK   (0x0000FF00u)
+#define EDMA3_CCRL_REV_CLASS_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_REV_CLASS_RESETVAL   (0x00000004u)
+#define EDMA3_CCRL_REV_RESERVED_MASK   (0x000000FFu)
+#define EDMA3_CCRL_REV_RESERVED_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_REV_RESERVED_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_REV_RESETVAL   (0x00070400u)
+#define EDMA3_CCRL_CCCFG_MP_EXIST_MASK   (0x02000000u)
+#define EDMA3_CCRL_CCCFG_MP_EXIST_SHIFT   (0x00000019u)
+#define EDMA3_CCRL_CCCFG_MP_EXIST_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCCFG_MP_EXIST_NONE   (0x00000000u)
+#define EDMA3_CCRL_CCCFG_MP_EXIST_INCLUDED   (0x00000001u)
+#define EDMA3_CCRL_CCCFG_CHMAP_EXIST_MASK   (0x01000000u)
+#define EDMA3_CCRL_CCCFG_CHMAP_EXIST_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_CCCFG_CHMAP_EXIST_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCCFG_CHMAP_EXIST_NONE   (0x00000000u)
+#define EDMA3_CCRL_CCCFG_CHMAP_EXIST_INCLUDED   (0x00000001u)
+#define EDMA3_CCRL_CCCFG_NUM_REGN_MASK   (0x00300000u)
+#define EDMA3_CCRL_CCCFG_NUM_REGN_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_CCCFG_NUM_REGN_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCCFG_NUM_REGN_0   (0x00000000u)
+#define EDMA3_CCRL_CCCFG_NUM_REGN_2   (0x00000001u)
+#define EDMA3_CCRL_CCCFG_NUM_REGN_4   (0x00000002u)
+#define EDMA3_CCRL_CCCFG_NUM_REGN_8   (0x00000003u)
+#define EDMA3_CCRL_CCCFG_NUM_TC_MASK   (0x00070000u)
+#define EDMA3_CCRL_CCCFG_NUM_TC_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_CCCFG_NUM_TC_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCCFG_NUM_TC_1   (0x00000000u)
+#define EDMA3_CCRL_CCCFG_NUM_TC_2   (0x00000001u)
+#define EDMA3_CCRL_CCCFG_NUM_TC_3   (0x00000002u)
+#define EDMA3_CCRL_CCCFG_NUM_TC_4   (0x00000003u)
+#define EDMA3_CCRL_CCCFG_NUM_TC_5   (0x00000004u)
+#define EDMA3_CCRL_CCCFG_NUM_TC_6   (0x00000005u)
+#define EDMA3_CCRL_CCCFG_NUM_TC_7   (0x00000006u)
+#define EDMA3_CCRL_CCCFG_NUM_TC_8   (0x00000007u)
+#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_MASK   (0x00007000u)
+#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_16   (0x00000000u)
+#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_32   (0x00000001u)
+#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_64   (0x00000002u)
+#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_128   (0x00000003u)
+#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_256   (0x00000004u)
+#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_512   (0x00000005u)
+#define EDMA3_CCRL_CCCFG_NUM_INTCH_MASK   (0x00000700u)
+#define EDMA3_CCRL_CCCFG_NUM_INTCH_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_CCCFG_NUM_INTCH_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCCFG_NUM_INTCH_8   (0x00000001u)
+#define EDMA3_CCRL_CCCFG_NUM_INTCH_16   (0x00000002u)
+#define EDMA3_CCRL_CCCFG_NUM_INTCH_32   (0x00000003u)
+#define EDMA3_CCRL_CCCFG_NUM_INTCH_64   (0x00000004u)
+#define EDMA3_CCRL_CCCFG_NUM_QDMACH_MASK   (0x00000070u)
+#define EDMA3_CCRL_CCCFG_NUM_QDMACH_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_CCCFG_NUM_QDMACH_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCCFG_NUM_QDMACH_NONE   (0x00000000u)
+#define EDMA3_CCRL_CCCFG_NUM_QDMACH_2   (0x00000001u)
+#define EDMA3_CCRL_CCCFG_NUM_QDMACH_4   (0x00000002u)
+#define EDMA3_CCRL_CCCFG_NUM_QDMACH_6   (0x00000003u)
+#define EDMA3_CCRL_CCCFG_NUM_QDMACH_8   (0x00000004u)
+#define EDMA3_CCRL_CCCFG_NUM_DMACH_MASK   (0x00000007u)
+#define EDMA3_CCRL_CCCFG_NUM_DMACH_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_CCCFG_NUM_DMACH_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCCFG_NUM_DMACH_NONE   (0x00000000u)
+#define EDMA3_CCRL_CCCFG_NUM_DMACH_4   (0x00000001u)
+#define EDMA3_CCRL_CCCFG_NUM_DMACH_8   (0x00000002u)
+#define EDMA3_CCRL_CCCFG_NUM_DMACH_16   (0x00000003u)
+#define EDMA3_CCRL_CCCFG_NUM_DMACH_32   (0x00000004u)
+#define EDMA3_CCRL_CCCFG_NUM_DMACH_64   (0x00000005u)
+#define EDMA3_CCRL_CCCFG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DCHMAP_PAENTRY_MASK   (0x00003FE0u)
+#define EDMA3_CCRL_DCHMAP_PAENTRY_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_DCHMAP_PAENTRY_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DCHMAP_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QCHMAP_PAENTRY_MASK   (0x00003FE0u)
+#define EDMA3_CCRL_QCHMAP_PAENTRY_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_QCHMAP_PAENTRY_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QCHMAP_TRWORD_MASK   (0x0000001Cu)
+#define EDMA3_CCRL_QCHMAP_TRWORD_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_QCHMAP_TRWORD_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QCHMAP_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DMAQNUM_E7_MASK   (0x70000000u)
+#define EDMA3_CCRL_DMAQNUM_E7_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_DMAQNUM_E7_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DMAQNUM_E6_MASK   (0x07000000u)
+#define EDMA3_CCRL_DMAQNUM_E6_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_DMAQNUM_E6_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DMAQNUM_E5_MASK   (0x00700000u)
+#define EDMA3_CCRL_DMAQNUM_E5_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_DMAQNUM_E5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DMAQNUM_E4_MASK   (0x00070000u)
+#define EDMA3_CCRL_DMAQNUM_E4_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_DMAQNUM_E4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DMAQNUM_E3_MASK   (0x00007000u)
+#define EDMA3_CCRL_DMAQNUM_E3_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_DMAQNUM_E3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DMAQNUM_E2_MASK   (0x00000700u)
+#define EDMA3_CCRL_DMAQNUM_E2_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_DMAQNUM_E2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DMAQNUM_E1_MASK   (0x00000070u)
+#define EDMA3_CCRL_DMAQNUM_E1_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_DMAQNUM_E1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DMAQNUM_E0_MASK   (0x00000007u)
+#define EDMA3_CCRL_DMAQNUM_E0_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_DMAQNUM_E0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DMAQNUM_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QDMAQNUM_E7_MASK   (0x70000000u)
+#define EDMA3_CCRL_QDMAQNUM_E7_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_QDMAQNUM_E7_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QDMAQNUM_E6_MASK   (0x07000000u)
+#define EDMA3_CCRL_QDMAQNUM_E6_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_QDMAQNUM_E6_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QDMAQNUM_E5_MASK   (0x00700000u)
+#define EDMA3_CCRL_QDMAQNUM_E5_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_QDMAQNUM_E5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QDMAQNUM_E4_MASK   (0x00070000u)
+#define EDMA3_CCRL_QDMAQNUM_E4_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_QDMAQNUM_E4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QDMAQNUM_E3_MASK   (0x00007000u)
+#define EDMA3_CCRL_QDMAQNUM_E3_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_QDMAQNUM_E3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QDMAQNUM_E2_MASK   (0x00000700u)
+#define EDMA3_CCRL_QDMAQNUM_E2_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_QDMAQNUM_E2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QDMAQNUM_E1_MASK   (0x00000070u)
+#define EDMA3_CCRL_QDMAQNUM_E1_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_QDMAQNUM_E1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QDMAQNUM_E0_MASK   (0x00000007u)
+#define EDMA3_CCRL_QDMAQNUM_E0_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_QDMAQNUM_E0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QDMAQNUM_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ7_MASK   (0x70000000u)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ7_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ7_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ6_MASK   (0x07000000u)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ6_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ6_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ5_MASK   (0x00700000u)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ5_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ4_MASK   (0x00070000u)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ4_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ3_MASK   (0x00007000u)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ3_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ2_MASK   (0x00000700u)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ2_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ1_MASK   (0x00000070u)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ1_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ0_MASK   (0x00000007u)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ0_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QUETCMAP_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QUEPRI_PRIQ7_MASK   (0x70000000u)
+#define EDMA3_CCRL_QUEPRI_PRIQ7_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_QUEPRI_PRIQ7_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QUEPRI_PRIQ6_MASK   (0x07000000u)
+#define EDMA3_CCRL_QUEPRI_PRIQ6_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_QUEPRI_PRIQ6_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QUEPRI_PRIQ5_MASK   (0x00700000u)
+#define EDMA3_CCRL_QUEPRI_PRIQ5_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_QUEPRI_PRIQ5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QUEPRI_PRIQ4_MASK   (0x00070000u)
+#define EDMA3_CCRL_QUEPRI_PRIQ4_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_QUEPRI_PRIQ4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QUEPRI_PRIQ3_MASK   (0x00007000u)
+#define EDMA3_CCRL_QUEPRI_PRIQ3_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_QUEPRI_PRIQ3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QUEPRI_PRIQ2_MASK   (0x00000700u)
+#define EDMA3_CCRL_QUEPRI_PRIQ2_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_QUEPRI_PRIQ2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QUEPRI_PRIQ1_MASK   (0x00000070u)
+#define EDMA3_CCRL_QUEPRI_PRIQ1_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_QUEPRI_PRIQ1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QUEPRI_PRIQ0_MASK   (0x00000007u)
+#define EDMA3_CCRL_QUEPRI_PRIQ0_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_QUEPRI_PRIQ0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QUEPRI_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMR_E31_MASK   (0x80000000u)
+#define EDMA3_CCRL_EMR_E31_SHIFT   (0x0000001Fu)
+#define EDMA3_CCRL_EMR_E31_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMR_E30_MASK   (0x40000000u)
+#define EDMA3_CCRL_EMR_E30_SHIFT   (0x0000001Eu)
+#define EDMA3_CCRL_EMR_E30_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMR_E29_MASK   (0x20000000u)
+#define EDMA3_CCRL_EMR_E29_SHIFT   (0x0000001Du)
+#define EDMA3_CCRL_EMR_E29_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMR_E28_MASK   (0x10000000u)
+#define EDMA3_CCRL_EMR_E28_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_EMR_E28_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMR_E27_MASK   (0x08000000u)
+#define EDMA3_CCRL_EMR_E27_SHIFT   (0x0000001Bu)
+#define EDMA3_CCRL_EMR_E27_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMR_E26_MASK   (0x04000000u)
+#define EDMA3_CCRL_EMR_E26_SHIFT   (0x0000001Au)
+#define EDMA3_CCRL_EMR_E26_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMR_E25_MASK   (0x02000000u)
+#define EDMA3_CCRL_EMR_E25_SHIFT   (0x00000019u)
+#define EDMA3_CCRL_EMR_E25_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMR_E24_MASK   (0x01000000u)
+#define EDMA3_CCRL_EMR_E24_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_EMR_E24_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMR_E23_MASK   (0x00800000u)
+#define EDMA3_CCRL_EMR_E23_SHIFT   (0x00000017u)
+#define EDMA3_CCRL_EMR_E23_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMR_E22_MASK   (0x00400000u)
+#define EDMA3_CCRL_EMR_E22_SHIFT   (0x00000016u)
+#define EDMA3_CCRL_EMR_E22_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMR_E21_MASK   (0x00200000u)
+#define EDMA3_CCRL_EMR_E21_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_EMR_E21_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMR_E20_MASK   (0x00100000u)
+#define EDMA3_CCRL_EMR_E20_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_EMR_E20_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMR_E19_MASK   (0x00080000u)
+#define EDMA3_CCRL_EMR_E19_SHIFT   (0x00000013u)
+#define EDMA3_CCRL_EMR_E19_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMR_E18_MASK   (0x00040000u)
+#define EDMA3_CCRL_EMR_E18_SHIFT   (0x00000012u)
+#define EDMA3_CCRL_EMR_E18_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMR_E17_MASK   (0x00020000u)
+#define EDMA3_CCRL_EMR_E17_SHIFT   (0x00000011u)
+#define EDMA3_CCRL_EMR_E17_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMR_E16_MASK   (0x00010000u)
+#define EDMA3_CCRL_EMR_E16_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_EMR_E16_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMR_E15_MASK   (0x00008000u)
+#define EDMA3_CCRL_EMR_E15_SHIFT   (0x0000000Fu)
+#define EDMA3_CCRL_EMR_E15_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMR_E14_MASK   (0x00004000u)
+#define EDMA3_CCRL_EMR_E14_SHIFT   (0x0000000Eu)
+#define EDMA3_CCRL_EMR_E14_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMR_E13_MASK   (0x00002000u)
+#define EDMA3_CCRL_EMR_E13_SHIFT   (0x0000000Du)
+#define EDMA3_CCRL_EMR_E13_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMR_E12_MASK   (0x00001000u)
+#define EDMA3_CCRL_EMR_E12_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_EMR_E12_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMR_E11_MASK   (0x00000800u)
+#define EDMA3_CCRL_EMR_E11_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_EMR_E11_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMR_E10_MASK   (0x00000400u)
+#define EDMA3_CCRL_EMR_E10_SHIFT   (0x0000000Au)
+#define EDMA3_CCRL_EMR_E10_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMR_E9_MASK   (0x00000200u)
+#define EDMA3_CCRL_EMR_E9_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_EMR_E9_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMR_E8_MASK   (0x00000100u)
+#define EDMA3_CCRL_EMR_E8_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_EMR_E8_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMR_E7_MASK   (0x00000080u)
+#define EDMA3_CCRL_EMR_E7_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_EMR_E7_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMR_E6_MASK   (0x00000040u)
+#define EDMA3_CCRL_EMR_E6_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_EMR_E6_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMR_E5_MASK   (0x00000020u)
+#define EDMA3_CCRL_EMR_E5_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_EMR_E5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMR_E4_MASK   (0x00000010u)
+#define EDMA3_CCRL_EMR_E4_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_EMR_E4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMR_E3_MASK   (0x00000008u)
+#define EDMA3_CCRL_EMR_E3_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_EMR_E3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMR_E2_MASK   (0x00000004u)
+#define EDMA3_CCRL_EMR_E2_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_EMR_E2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMR_E1_MASK   (0x00000002u)
+#define EDMA3_CCRL_EMR_E1_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_EMR_E1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMR_E0_MASK   (0x00000001u)
+#define EDMA3_CCRL_EMR_E0_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_EMR_E0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMRH_E63_MASK   (0x80000000u)
+#define EDMA3_CCRL_EMRH_E63_SHIFT   (0x0000001Fu)
+#define EDMA3_CCRL_EMRH_E63_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMRH_E62_MASK   (0x40000000u)
+#define EDMA3_CCRL_EMRH_E62_SHIFT   (0x0000001Eu)
+#define EDMA3_CCRL_EMRH_E62_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMRH_E61_MASK   (0x20000000u)
+#define EDMA3_CCRL_EMRH_E61_SHIFT   (0x0000001Du)
+#define EDMA3_CCRL_EMRH_E61_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMRH_E60_MASK   (0x10000000u)
+#define EDMA3_CCRL_EMRH_E60_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_EMRH_E60_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMRH_E59_MASK   (0x08000000u)
+#define EDMA3_CCRL_EMRH_E59_SHIFT   (0x0000001Bu)
+#define EDMA3_CCRL_EMRH_E59_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMRH_E58_MASK   (0x04000000u)
+#define EDMA3_CCRL_EMRH_E58_SHIFT   (0x0000001Au)
+#define EDMA3_CCRL_EMRH_E58_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMRH_E57_MASK   (0x02000000u)
+#define EDMA3_CCRL_EMRH_E57_SHIFT   (0x00000019u)
+#define EDMA3_CCRL_EMRH_E57_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMRH_E56_MASK   (0x01000000u)
+#define EDMA3_CCRL_EMRH_E56_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_EMRH_E56_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMRH_E55_MASK   (0x00800000u)
+#define EDMA3_CCRL_EMRH_E55_SHIFT   (0x00000017u)
+#define EDMA3_CCRL_EMRH_E55_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMRH_E54_MASK   (0x00400000u)
+#define EDMA3_CCRL_EMRH_E54_SHIFT   (0x00000016u)
+#define EDMA3_CCRL_EMRH_E54_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMRH_E53_MASK   (0x00200000u)
+#define EDMA3_CCRL_EMRH_E53_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_EMRH_E53_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMRH_E52_MASK   (0x00100000u)
+#define EDMA3_CCRL_EMRH_E52_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_EMRH_E52_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMRH_E51_MASK   (0x00080000u)
+#define EDMA3_CCRL_EMRH_E51_SHIFT   (0x00000013u)
+#define EDMA3_CCRL_EMRH_E51_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMRH_E50_MASK   (0x00040000u)
+#define EDMA3_CCRL_EMRH_E50_SHIFT   (0x00000012u)
+#define EDMA3_CCRL_EMRH_E50_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMRH_E49_MASK   (0x00020000u)
+#define EDMA3_CCRL_EMRH_E49_SHIFT   (0x00000011u)
+#define EDMA3_CCRL_EMRH_E49_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMRH_E48_MASK   (0x00010000u)
+#define EDMA3_CCRL_EMRH_E48_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_EMRH_E48_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMRH_E47_MASK   (0x00008000u)
+#define EDMA3_CCRL_EMRH_E47_SHIFT   (0x0000000Fu)
+#define EDMA3_CCRL_EMRH_E47_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMRH_E46_MASK   (0x00004000u)
+#define EDMA3_CCRL_EMRH_E46_SHIFT   (0x0000000Eu)
+#define EDMA3_CCRL_EMRH_E46_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMRH_E45_MASK   (0x00002000u)
+#define EDMA3_CCRL_EMRH_E45_SHIFT   (0x0000000Du)
+#define EDMA3_CCRL_EMRH_E45_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMRH_E44_MASK   (0x00001000u)
+#define EDMA3_CCRL_EMRH_E44_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_EMRH_E44_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMRH_E43_MASK   (0x00000800u)
+#define EDMA3_CCRL_EMRH_E43_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_EMRH_E43_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMRH_E42_MASK   (0x00000400u)
+#define EDMA3_CCRL_EMRH_E42_SHIFT   (0x0000000Au)
+#define EDMA3_CCRL_EMRH_E42_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMRH_E41_MASK   (0x00000200u)
+#define EDMA3_CCRL_EMRH_E41_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_EMRH_E41_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMRH_E40_MASK   (0x00000100u)
+#define EDMA3_CCRL_EMRH_E40_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_EMRH_E40_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMRH_E39_MASK   (0x00000080u)
+#define EDMA3_CCRL_EMRH_E39_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_EMRH_E39_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMRH_E38_MASK   (0x00000040u)
+#define EDMA3_CCRL_EMRH_E38_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_EMRH_E38_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMRH_E37_MASK   (0x00000020u)
+#define EDMA3_CCRL_EMRH_E37_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_EMRH_E37_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMRH_E36_MASK   (0x00000010u)
+#define EDMA3_CCRL_EMRH_E36_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_EMRH_E36_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMRH_E35_MASK   (0x00000008u)
+#define EDMA3_CCRL_EMRH_E35_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_EMRH_E35_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMRH_E34_MASK   (0x00000004u)
+#define EDMA3_CCRL_EMRH_E34_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_EMRH_E34_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMRH_E33_MASK   (0x00000002u)
+#define EDMA3_CCRL_EMRH_E33_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_EMRH_E33_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMRH_E32_MASK   (0x00000001u)
+#define EDMA3_CCRL_EMRH_E32_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_EMRH_E32_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMRH_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCR_E31_MASK   (0x80000000u)
+#define EDMA3_CCRL_EMCR_E31_SHIFT   (0x0000001Fu)
+#define EDMA3_CCRL_EMCR_E31_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCR_E30_MASK   (0x40000000u)
+#define EDMA3_CCRL_EMCR_E30_SHIFT   (0x0000001Eu)
+#define EDMA3_CCRL_EMCR_E30_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCR_E29_MASK   (0x20000000u)
+#define EDMA3_CCRL_EMCR_E29_SHIFT   (0x0000001Du)
+#define EDMA3_CCRL_EMCR_E29_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCR_E28_MASK   (0x10000000u)
+#define EDMA3_CCRL_EMCR_E28_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_EMCR_E28_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCR_E27_MASK   (0x08000000u)
+#define EDMA3_CCRL_EMCR_E27_SHIFT   (0x0000001Bu)
+#define EDMA3_CCRL_EMCR_E27_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCR_E26_MASK   (0x04000000u)
+#define EDMA3_CCRL_EMCR_E26_SHIFT   (0x0000001Au)
+#define EDMA3_CCRL_EMCR_E26_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCR_E25_MASK   (0x02000000u)
+#define EDMA3_CCRL_EMCR_E25_SHIFT   (0x00000019u)
+#define EDMA3_CCRL_EMCR_E25_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCR_E24_MASK   (0x01000000u)
+#define EDMA3_CCRL_EMCR_E24_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_EMCR_E24_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCR_E23_MASK   (0x00800000u)
+#define EDMA3_CCRL_EMCR_E23_SHIFT   (0x00000017u)
+#define EDMA3_CCRL_EMCR_E23_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCR_E22_MASK   (0x00400000u)
+#define EDMA3_CCRL_EMCR_E22_SHIFT   (0x00000016u)
+#define EDMA3_CCRL_EMCR_E22_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCR_E21_MASK   (0x00200000u)
+#define EDMA3_CCRL_EMCR_E21_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_EMCR_E21_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCR_E20_MASK   (0x00100000u)
+#define EDMA3_CCRL_EMCR_E20_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_EMCR_E20_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCR_E19_MASK   (0x00080000u)
+#define EDMA3_CCRL_EMCR_E19_SHIFT   (0x00000013u)
+#define EDMA3_CCRL_EMCR_E19_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCR_E18_MASK   (0x00040000u)
+#define EDMA3_CCRL_EMCR_E18_SHIFT   (0x00000012u)
+#define EDMA3_CCRL_EMCR_E18_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCR_E17_MASK   (0x00020000u)
+#define EDMA3_CCRL_EMCR_E17_SHIFT   (0x00000011u)
+#define EDMA3_CCRL_EMCR_E17_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCR_E16_MASK   (0x00010000u)
+#define EDMA3_CCRL_EMCR_E16_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_EMCR_E16_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCR_E15_MASK   (0x00008000u)
+#define EDMA3_CCRL_EMCR_E15_SHIFT   (0x0000000Fu)
+#define EDMA3_CCRL_EMCR_E15_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCR_E14_MASK   (0x00004000u)
+#define EDMA3_CCRL_EMCR_E14_SHIFT   (0x0000000Eu)
+#define EDMA3_CCRL_EMCR_E14_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCR_E13_MASK   (0x00002000u)
+#define EDMA3_CCRL_EMCR_E13_SHIFT   (0x0000000Du)
+#define EDMA3_CCRL_EMCR_E13_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCR_E12_MASK   (0x00001000u)
+#define EDMA3_CCRL_EMCR_E12_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_EMCR_E12_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCR_E11_MASK   (0x00000800u)
+#define EDMA3_CCRL_EMCR_E11_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_EMCR_E11_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCR_E10_MASK   (0x00000400u)
+#define EDMA3_CCRL_EMCR_E10_SHIFT   (0x0000000Au)
+#define EDMA3_CCRL_EMCR_E10_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCR_E9_MASK   (0x00000200u)
+#define EDMA3_CCRL_EMCR_E9_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_EMCR_E9_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCR_E8_MASK   (0x00000100u)
+#define EDMA3_CCRL_EMCR_E8_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_EMCR_E8_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCR_E7_MASK   (0x00000080u)
+#define EDMA3_CCRL_EMCR_E7_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_EMCR_E7_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCR_E6_MASK   (0x00000040u)
+#define EDMA3_CCRL_EMCR_E6_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_EMCR_E6_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCR_E5_MASK   (0x00000020u)
+#define EDMA3_CCRL_EMCR_E5_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_EMCR_E5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCR_E4_MASK   (0x00000010u)
+#define EDMA3_CCRL_EMCR_E4_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_EMCR_E4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCR_E3_MASK   (0x00000008u)
+#define EDMA3_CCRL_EMCR_E3_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_EMCR_E3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCR_E2_MASK   (0x00000004u)
+#define EDMA3_CCRL_EMCR_E2_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_EMCR_E2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCR_E1_MASK   (0x00000002u)
+#define EDMA3_CCRL_EMCR_E1_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_EMCR_E1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCR_E0_MASK   (0x00000001u)
+#define EDMA3_CCRL_EMCR_E0_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_EMCR_E0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E63_MASK   (0x80000000u)
+#define EDMA3_CCRL_EMCRH_E63_SHIFT   (0x0000001Fu)
+#define EDMA3_CCRL_EMCRH_E63_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E62_MASK   (0x40000000u)
+#define EDMA3_CCRL_EMCRH_E62_SHIFT   (0x0000001Eu)
+#define EDMA3_CCRL_EMCRH_E62_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E61_MASK   (0x20000000u)
+#define EDMA3_CCRL_EMCRH_E61_SHIFT   (0x0000001Du)
+#define EDMA3_CCRL_EMCRH_E61_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E60_MASK   (0x10000000u)
+#define EDMA3_CCRL_EMCRH_E60_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_EMCRH_E60_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E59_MASK   (0x08000000u)
+#define EDMA3_CCRL_EMCRH_E59_SHIFT   (0x0000001Bu)
+#define EDMA3_CCRL_EMCRH_E59_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E58_MASK   (0x04000000u)
+#define EDMA3_CCRL_EMCRH_E58_SHIFT   (0x0000001Au)
+#define EDMA3_CCRL_EMCRH_E58_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E57_MASK   (0x02000000u)
+#define EDMA3_CCRL_EMCRH_E57_SHIFT   (0x00000019u)
+#define EDMA3_CCRL_EMCRH_E57_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E56_MASK   (0x01000000u)
+#define EDMA3_CCRL_EMCRH_E56_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_EMCRH_E56_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E55_MASK   (0x00800000u)
+#define EDMA3_CCRL_EMCRH_E55_SHIFT   (0x00000017u)
+#define EDMA3_CCRL_EMCRH_E55_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E54_MASK   (0x00400000u)
+#define EDMA3_CCRL_EMCRH_E54_SHIFT   (0x00000016u)
+#define EDMA3_CCRL_EMCRH_E54_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E53_MASK   (0x00200000u)
+#define EDMA3_CCRL_EMCRH_E53_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_EMCRH_E53_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E52_MASK   (0x00100000u)
+#define EDMA3_CCRL_EMCRH_E52_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_EMCRH_E52_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E51_MASK   (0x00080000u)
+#define EDMA3_CCRL_EMCRH_E51_SHIFT   (0x00000013u)
+#define EDMA3_CCRL_EMCRH_E51_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E50_MASK   (0x00040000u)
+#define EDMA3_CCRL_EMCRH_E50_SHIFT   (0x00000012u)
+#define EDMA3_CCRL_EMCRH_E50_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E49_MASK   (0x00020000u)
+#define EDMA3_CCRL_EMCRH_E49_SHIFT   (0x00000011u)
+#define EDMA3_CCRL_EMCRH_E49_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E48_MASK   (0x00010000u)
+#define EDMA3_CCRL_EMCRH_E48_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_EMCRH_E48_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E47_MASK   (0x00008000u)
+#define EDMA3_CCRL_EMCRH_E47_SHIFT   (0x0000000Fu)
+#define EDMA3_CCRL_EMCRH_E47_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E46_MASK   (0x00004000u)
+#define EDMA3_CCRL_EMCRH_E46_SHIFT   (0x0000000Eu)
+#define EDMA3_CCRL_EMCRH_E46_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E45_MASK   (0x00002000u)
+#define EDMA3_CCRL_EMCRH_E45_SHIFT   (0x0000000Du)
+#define EDMA3_CCRL_EMCRH_E45_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E44_MASK   (0x00001000u)
+#define EDMA3_CCRL_EMCRH_E44_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_EMCRH_E44_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E43_MASK   (0x00000800u)
+#define EDMA3_CCRL_EMCRH_E43_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_EMCRH_E43_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E42_MASK   (0x00000400u)
+#define EDMA3_CCRL_EMCRH_E42_SHIFT   (0x0000000Au)
+#define EDMA3_CCRL_EMCRH_E42_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E41_MASK   (0x00000200u)
+#define EDMA3_CCRL_EMCRH_E41_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_EMCRH_E41_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E40_MASK   (0x00000100u)
+#define EDMA3_CCRL_EMCRH_E40_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_EMCRH_E40_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E39_MASK   (0x00000080u)
+#define EDMA3_CCRL_EMCRH_E39_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_EMCRH_E39_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E38_MASK   (0x00000040u)
+#define EDMA3_CCRL_EMCRH_E38_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_EMCRH_E38_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E37_MASK   (0x00000020u)
+#define EDMA3_CCRL_EMCRH_E37_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_EMCRH_E37_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E36_MASK   (0x00000010u)
+#define EDMA3_CCRL_EMCRH_E36_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_EMCRH_E36_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E35_MASK   (0x00000008u)
+#define EDMA3_CCRL_EMCRH_E35_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_EMCRH_E35_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E34_MASK   (0x00000004u)
+#define EDMA3_CCRL_EMCRH_E34_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_EMCRH_E34_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E33_MASK   (0x00000002u)
+#define EDMA3_CCRL_EMCRH_E33_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_EMCRH_E33_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E32_MASK   (0x00000001u)
+#define EDMA3_CCRL_EMCRH_E32_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E32_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EMCRH_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEMR_E7_MASK   (0x00000080u)
+#define EDMA3_CCRL_QEMR_E7_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_QEMR_E7_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEMR_E6_MASK   (0x00000040u)
+#define EDMA3_CCRL_QEMR_E6_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_QEMR_E6_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEMR_E5_MASK   (0x00000020u)
+#define EDMA3_CCRL_QEMR_E5_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_QEMR_E5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEMR_E4_MASK   (0x00000010u)
+#define EDMA3_CCRL_QEMR_E4_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_QEMR_E4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEMR_E3_MASK   (0x00000008u)
+#define EDMA3_CCRL_QEMR_E3_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_QEMR_E3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEMR_E2_MASK   (0x00000004u)
+#define EDMA3_CCRL_QEMR_E2_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_QEMR_E2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEMR_E1_MASK   (0x00000002u)
+#define EDMA3_CCRL_QEMR_E1_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_QEMR_E1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEMR_E0_MASK   (0x00000001u)
+#define EDMA3_CCRL_QEMR_E0_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_QEMR_E0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEMR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEMCR_E7_MASK   (0x00000080u)
+#define EDMA3_CCRL_QEMCR_E7_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_QEMCR_E7_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEMCR_E6_MASK   (0x00000040u)
+#define EDMA3_CCRL_QEMCR_E6_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_QEMCR_E6_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEMCR_E5_MASK   (0x00000020u)
+#define EDMA3_CCRL_QEMCR_E5_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_QEMCR_E5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEMCR_E4_MASK   (0x00000010u)
+#define EDMA3_CCRL_QEMCR_E4_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_QEMCR_E4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEMCR_E3_MASK   (0x00000008u)
+#define EDMA3_CCRL_QEMCR_E3_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_QEMCR_E3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEMCR_E2_MASK   (0x00000004u)
+#define EDMA3_CCRL_QEMCR_E2_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_QEMCR_E2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEMCR_E1_MASK   (0x00000002u)
+#define EDMA3_CCRL_QEMCR_E1_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_QEMCR_E1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEMCR_E0_MASK   (0x00000001u)
+#define EDMA3_CCRL_QEMCR_E0_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_QEMCR_E0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEMCR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCERR_TCCERR_MASK   (0x00010000u)
+#define EDMA3_CCRL_CCERR_TCCERR_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_CCERR_TCCERR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCERR_QTHRXCD7_MASK   (0x00000080u)
+#define EDMA3_CCRL_CCERR_QTHRXCD7_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_CCERR_QTHRXCD7_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCERR_QTHRXCD6_MASK   (0x00000040u)
+#define EDMA3_CCRL_CCERR_QTHRXCD6_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_CCERR_QTHRXCD6_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCERR_QTHRXCD5_MASK   (0x00000020u)
+#define EDMA3_CCRL_CCERR_QTHRXCD5_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_CCERR_QTHRXCD5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCERR_QTHRXCD4_MASK   (0x00000010u)
+#define EDMA3_CCRL_CCERR_QTHRXCD4_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_CCERR_QTHRXCD4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCERR_QTHRXCD3_MASK   (0x00000008u)
+#define EDMA3_CCRL_CCERR_QTHRXCD3_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_CCERR_QTHRXCD3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCERR_QTHRXCD2_MASK   (0x00000004u)
+#define EDMA3_CCRL_CCERR_QTHRXCD2_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_CCERR_QTHRXCD2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCERR_QTHRXCD1_MASK   (0x00000002u)
+#define EDMA3_CCRL_CCERR_QTHRXCD1_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_CCERR_QTHRXCD1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCERR_QTHRXCD0_MASK   (0x00000001u)
+#define EDMA3_CCRL_CCERR_QTHRXCD0_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_CCERR_QTHRXCD0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCERR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCERRCLR_TCCERR_MASK   (0x00010000u)
+#define EDMA3_CCRL_CCERRCLR_TCCERR_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_CCERRCLR_TCCERR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD7_MASK   (0x00000080u)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD7_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD7_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD6_MASK   (0x00000040u)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD6_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD6_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD5_MASK   (0x00000020u)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD5_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD4_MASK   (0x00000010u)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD4_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD3_MASK   (0x00000008u)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD3_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD2_MASK   (0x00000004u)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD2_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD1_MASK   (0x00000002u)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD1_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD0_MASK   (0x00000001u)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD0_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCERRCLR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EEVAL_SET_MASK   (0x00000002u)
+#define EDMA3_CCRL_EEVAL_SET_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_EEVAL_SET_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EEVAL_SET_SET   (0x00000001u)
+#define EDMA3_CCRL_EEVAL_EVAL_MASK   (0x00000001u)
+#define EDMA3_CCRL_EEVAL_EVAL_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_EEVAL_EVAL_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EEVAL_EVAL_EVAL   (0x00000001u)
+#define EDMA3_CCRL_EEVAL_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAE_E31_MASK   (0x80000000u)
+#define EDMA3_CCRL_DRAE_E31_SHIFT   (0x0000001Fu)
+#define EDMA3_CCRL_DRAE_E31_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAE_E30_MASK   (0x40000000u)
+#define EDMA3_CCRL_DRAE_E30_SHIFT   (0x0000001Eu)
+#define EDMA3_CCRL_DRAE_E30_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAE_E29_MASK   (0x20000000u)
+#define EDMA3_CCRL_DRAE_E29_SHIFT   (0x0000001Du)
+#define EDMA3_CCRL_DRAE_E29_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAE_E28_MASK   (0x10000000u)
+#define EDMA3_CCRL_DRAE_E28_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_DRAE_E28_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAE_E27_MASK   (0x08000000u)
+#define EDMA3_CCRL_DRAE_E27_SHIFT   (0x0000001Bu)
+#define EDMA3_CCRL_DRAE_E27_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAE_E26_MASK   (0x04000000u)
+#define EDMA3_CCRL_DRAE_E26_SHIFT   (0x0000001Au)
+#define EDMA3_CCRL_DRAE_E26_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAE_E25_MASK   (0x02000000u)
+#define EDMA3_CCRL_DRAE_E25_SHIFT   (0x00000019u)
+#define EDMA3_CCRL_DRAE_E25_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAE_E24_MASK   (0x01000000u)
+#define EDMA3_CCRL_DRAE_E24_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_DRAE_E24_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAE_E23_MASK   (0x00800000u)
+#define EDMA3_CCRL_DRAE_E23_SHIFT   (0x00000017u)
+#define EDMA3_CCRL_DRAE_E23_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAE_E22_MASK   (0x00400000u)
+#define EDMA3_CCRL_DRAE_E22_SHIFT   (0x00000016u)
+#define EDMA3_CCRL_DRAE_E22_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAE_E21_MASK   (0x00200000u)
+#define EDMA3_CCRL_DRAE_E21_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_DRAE_E21_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAE_E20_MASK   (0x00100000u)
+#define EDMA3_CCRL_DRAE_E20_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_DRAE_E20_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAE_E19_MASK   (0x00080000u)
+#define EDMA3_CCRL_DRAE_E19_SHIFT   (0x00000013u)
+#define EDMA3_CCRL_DRAE_E19_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAE_E18_MASK   (0x00040000u)
+#define EDMA3_CCRL_DRAE_E18_SHIFT   (0x00000012u)
+#define EDMA3_CCRL_DRAE_E18_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAE_E17_MASK   (0x00020000u)
+#define EDMA3_CCRL_DRAE_E17_SHIFT   (0x00000011u)
+#define EDMA3_CCRL_DRAE_E17_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAE_E16_MASK   (0x00010000u)
+#define EDMA3_CCRL_DRAE_E16_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_DRAE_E16_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAE_E15_MASK   (0x00008000u)
+#define EDMA3_CCRL_DRAE_E15_SHIFT   (0x0000000Fu)
+#define EDMA3_CCRL_DRAE_E15_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAE_E14_MASK   (0x00004000u)
+#define EDMA3_CCRL_DRAE_E14_SHIFT   (0x0000000Eu)
+#define EDMA3_CCRL_DRAE_E14_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAE_E13_MASK   (0x00002000u)
+#define EDMA3_CCRL_DRAE_E13_SHIFT   (0x0000000Du)
+#define EDMA3_CCRL_DRAE_E13_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAE_E12_MASK   (0x00001000u)
+#define EDMA3_CCRL_DRAE_E12_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_DRAE_E12_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAE_E11_MASK   (0x00000800u)
+#define EDMA3_CCRL_DRAE_E11_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_DRAE_E11_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAE_E10_MASK   (0x00000400u)
+#define EDMA3_CCRL_DRAE_E10_SHIFT   (0x0000000Au)
+#define EDMA3_CCRL_DRAE_E10_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAE_E9_MASK   (0x00000200u)
+#define EDMA3_CCRL_DRAE_E9_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_DRAE_E9_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAE_E8_MASK   (0x00000100u)
+#define EDMA3_CCRL_DRAE_E8_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_DRAE_E8_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAE_E7_MASK   (0x00000080u)
+#define EDMA3_CCRL_DRAE_E7_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_DRAE_E7_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAE_E6_MASK   (0x00000040u)
+#define EDMA3_CCRL_DRAE_E6_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_DRAE_E6_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAE_E5_MASK   (0x00000020u)
+#define EDMA3_CCRL_DRAE_E5_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_DRAE_E5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAE_E4_MASK   (0x00000010u)
+#define EDMA3_CCRL_DRAE_E4_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_DRAE_E4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAE_E3_MASK   (0x00000008u)
+#define EDMA3_CCRL_DRAE_E3_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_DRAE_E3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAE_E2_MASK   (0x00000004u)
+#define EDMA3_CCRL_DRAE_E2_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_DRAE_E2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAE_E1_MASK   (0x00000002u)
+#define EDMA3_CCRL_DRAE_E1_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_DRAE_E1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAE_E0_MASK   (0x00000001u)
+#define EDMA3_CCRL_DRAE_E0_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_DRAE_E0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAE_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E63_MASK   (0x80000000u)
+#define EDMA3_CCRL_DRAEH_E63_SHIFT   (0x0000001Fu)
+#define EDMA3_CCRL_DRAEH_E63_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E62_MASK   (0x40000000u)
+#define EDMA3_CCRL_DRAEH_E62_SHIFT   (0x0000001Eu)
+#define EDMA3_CCRL_DRAEH_E62_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E61_MASK   (0x20000000u)
+#define EDMA3_CCRL_DRAEH_E61_SHIFT   (0x0000001Du)
+#define EDMA3_CCRL_DRAEH_E61_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E60_MASK   (0x10000000u)
+#define EDMA3_CCRL_DRAEH_E60_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_DRAEH_E60_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E59_MASK   (0x08000000u)
+#define EDMA3_CCRL_DRAEH_E59_SHIFT   (0x0000001Bu)
+#define EDMA3_CCRL_DRAEH_E59_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E58_MASK   (0x04000000u)
+#define EDMA3_CCRL_DRAEH_E58_SHIFT   (0x0000001Au)
+#define EDMA3_CCRL_DRAEH_E58_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E57_MASK   (0x02000000u)
+#define EDMA3_CCRL_DRAEH_E57_SHIFT   (0x00000019u)
+#define EDMA3_CCRL_DRAEH_E57_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E56_MASK   (0x01000000u)
+#define EDMA3_CCRL_DRAEH_E56_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_DRAEH_E56_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E55_MASK   (0x00800000u)
+#define EDMA3_CCRL_DRAEH_E55_SHIFT   (0x00000017u)
+#define EDMA3_CCRL_DRAEH_E55_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E54_MASK   (0x00400000u)
+#define EDMA3_CCRL_DRAEH_E54_SHIFT   (0x00000016u)
+#define EDMA3_CCRL_DRAEH_E54_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E53_MASK   (0x00200000u)
+#define EDMA3_CCRL_DRAEH_E53_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_DRAEH_E53_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E52_MASK   (0x00100000u)
+#define EDMA3_CCRL_DRAEH_E52_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_DRAEH_E52_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E51_MASK   (0x00080000u)
+#define EDMA3_CCRL_DRAEH_E51_SHIFT   (0x00000013u)
+#define EDMA3_CCRL_DRAEH_E51_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E50_MASK   (0x00040000u)
+#define EDMA3_CCRL_DRAEH_E50_SHIFT   (0x00000012u)
+#define EDMA3_CCRL_DRAEH_E50_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E49_MASK   (0x00020000u)
+#define EDMA3_CCRL_DRAEH_E49_SHIFT   (0x00000011u)
+#define EDMA3_CCRL_DRAEH_E49_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E48_MASK   (0x00010000u)
+#define EDMA3_CCRL_DRAEH_E48_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_DRAEH_E48_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E47_MASK   (0x00008000u)
+#define EDMA3_CCRL_DRAEH_E47_SHIFT   (0x0000000Fu)
+#define EDMA3_CCRL_DRAEH_E47_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E46_MASK   (0x00004000u)
+#define EDMA3_CCRL_DRAEH_E46_SHIFT   (0x0000000Eu)
+#define EDMA3_CCRL_DRAEH_E46_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E45_MASK   (0x00002000u)
+#define EDMA3_CCRL_DRAEH_E45_SHIFT   (0x0000000Du)
+#define EDMA3_CCRL_DRAEH_E45_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E44_MASK   (0x00001000u)
+#define EDMA3_CCRL_DRAEH_E44_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_DRAEH_E44_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E43_MASK   (0x00000800u)
+#define EDMA3_CCRL_DRAEH_E43_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_DRAEH_E43_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E42_MASK   (0x00000400u)
+#define EDMA3_CCRL_DRAEH_E42_SHIFT   (0x0000000Au)
+#define EDMA3_CCRL_DRAEH_E42_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E41_MASK   (0x00000200u)
+#define EDMA3_CCRL_DRAEH_E41_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_DRAEH_E41_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E40_MASK   (0x00000100u)
+#define EDMA3_CCRL_DRAEH_E40_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_DRAEH_E40_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E39_MASK   (0x00000080u)
+#define EDMA3_CCRL_DRAEH_E39_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_DRAEH_E39_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E38_MASK   (0x00000040u)
+#define EDMA3_CCRL_DRAEH_E38_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_DRAEH_E38_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E37_MASK   (0x00000020u)
+#define EDMA3_CCRL_DRAEH_E37_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_DRAEH_E37_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E36_MASK   (0x00000010u)
+#define EDMA3_CCRL_DRAEH_E36_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_DRAEH_E36_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E35_MASK   (0x00000008u)
+#define EDMA3_CCRL_DRAEH_E35_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_DRAEH_E35_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E34_MASK   (0x00000004u)
+#define EDMA3_CCRL_DRAEH_E34_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_DRAEH_E34_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E33_MASK   (0x00000002u)
+#define EDMA3_CCRL_DRAEH_E33_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_DRAEH_E33_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E32_MASK   (0x00000001u)
+#define EDMA3_CCRL_DRAEH_E32_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E32_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DRAEH_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QRAE_E7_MASK   (0x00000080u)
+#define EDMA3_CCRL_QRAE_E7_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_QRAE_E7_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QRAE_E6_MASK   (0x00000080u)
+#define EDMA3_CCRL_QRAE_E6_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_QRAE_E6_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QRAE_E5_MASK   (0x00000080u)
+#define EDMA3_CCRL_QRAE_E5_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_QRAE_E5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QRAE_E4_MASK   (0x00000080u)
+#define EDMA3_CCRL_QRAE_E4_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_QRAE_E4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QRAE_E3_MASK   (0x00000080u)
+#define EDMA3_CCRL_QRAE_E3_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_QRAE_E3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QRAE_E2_MASK   (0x00000080u)
+#define EDMA3_CCRL_QRAE_E2_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_QRAE_E2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QRAE_E1_MASK   (0x00000080u)
+#define EDMA3_CCRL_QRAE_E1_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_QRAE_E1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QRAE_E0_MASK   (0x00000080u)
+#define EDMA3_CCRL_QRAE_E0_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_QRAE_E0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QRAE_RESERVED_MASK   (0x0000007Fu)
+#define EDMA3_CCRL_QRAE_RESERVED_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_QRAE_RESERVED_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QRAE_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QUEEVT_ENTRY_RESV_MASK   (0xFFFFFF00u)
+#define EDMA3_CCRL_QUEEVT_ENTRY_RESV_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_QUEEVT_ENTRY_RESV_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QUEEVT_ENTRY_EVT_SRC_MASK   (0x000000C0u)
+#define EDMA3_CCRL_QUEEVT_ENTRY_EVT_SRC_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_QUEEVT_ENTRY_EVT_SRC_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QUEEVT_ENTRY_EVT_MASK   (0x0000003Fu)
+#define EDMA3_CCRL_QUEEVT_ENTRY_EVT_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_QUEEVT_ENTRY_EVT_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QUEEVT_ENTRY_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QSTAT_THRXD_MASK   (0x01000000u)
+#define EDMA3_CCRL_QSTAT_THRXD_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_QSTAT_THRXD_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QSTAT_RESERVED_MASK   (0x00600000u)
+#define EDMA3_CCRL_QSTAT_RESERVED_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_QSTAT_RESERVED_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QSTAT_WM_MASK   (0x001F0000u)
+#define EDMA3_CCRL_QSTAT_WM_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_QSTAT_WM_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QSTAT_NUMVAL_MASK   (0x00001F00u)
+#define EDMA3_CCRL_QSTAT_NUMVAL_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_QSTAT_NUMVAL_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QSTAT_STRTPTR_MASK   (0x0000000Fu)
+#define EDMA3_CCRL_QSTAT_STRTPTR_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_QSTAT_STRTPTR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QSTAT_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QWMTHRA_Q3_MASK   (0x1F000000u)
+#define EDMA3_CCRL_QWMTHRA_Q3_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_QWMTHRA_Q3_RESETVAL   (0x00000010u)
+#define EDMA3_CCRL_QWMTHRA_Q2_MASK   (0x001F0000u)
+#define EDMA3_CCRL_QWMTHRA_Q2_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_QWMTHRA_Q2_RESETVAL   (0x00000010u)
+#define EDMA3_CCRL_QWMTHRA_Q1_MASK   (0x00001F00u)
+#define EDMA3_CCRL_QWMTHRA_Q1_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_QWMTHRA_Q1_RESETVAL   (0x00000010u)
+#define EDMA3_CCRL_QWMTHRA_Q0_MASK   (0x0000001Fu)
+#define EDMA3_CCRL_QWMTHRA_Q0_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_QWMTHRA_Q0_RESETVAL   (0x00000010u)
+#define EDMA3_CCRL_QWMTHRA_RESETVAL   (0x10101010u)
+#define EDMA3_CCRL_QWMTHRB_Q7_MASK   (0x1F000000u)
+#define EDMA3_CCRL_QWMTHRB_Q7_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_QWMTHRB_Q7_RESETVAL   (0x00000010u)
+#define EDMA3_CCRL_QWMTHRB_Q6_MASK   (0x001F0000u)
+#define EDMA3_CCRL_QWMTHRB_Q6_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_QWMTHRB_Q6_RESETVAL   (0x00000010u)
+#define EDMA3_CCRL_QWMTHRB_Q5_MASK   (0x00001F00u)
+#define EDMA3_CCRL_QWMTHRB_Q5_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_QWMTHRB_Q5_RESETVAL   (0x00000010u)
+#define EDMA3_CCRL_QWMTHRB_Q4_MASK   (0x0000001Fu)
+#define EDMA3_CCRL_QWMTHRB_Q4_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_QWMTHRB_Q4_RESETVAL   (0x00000010u)
+#define EDMA3_CCRL_QWMTHRB_RESETVAL   (0x10101010u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV7_MASK   (0x00800000u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV7_SHIFT   (0x00000017u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV7_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV7_NONE   (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV7_ACTIVE   (0x00000001u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV6_MASK   (0x00400000u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV6_SHIFT   (0x00000016u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV6_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV6_NONE   (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV6_ACTIVE   (0x00000001u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV5_MASK   (0x00200000u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV5_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV5_NONE   (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV5_ACTIVE   (0x00000001u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV4_MASK   (0x00100000u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV4_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV4_NONE   (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV4_ACTIVE   (0x00000001u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV3_MASK   (0x00080000u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV3_SHIFT   (0x00000013u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV3_NONE   (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV3_ACTIVE   (0x00000001u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV2_MASK   (0x00040000u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV2_SHIFT   (0x00000012u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV2_NONE   (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV2_ACTIVE   (0x00000001u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV1_MASK   (0x00020000u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV1_SHIFT   (0x00000011u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV1_NONE   (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV1_ACTIVE   (0x00000001u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV0_MASK   (0x00010000u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV0_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV0_NONE   (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV0_ACTIVE   (0x00000001u)
+#define EDMA3_CCRL_CCSTAT_COMPACT_MASK   (0x00003F00u)
+#define EDMA3_CCRL_CCSTAT_COMPACT_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_CCSTAT_COMPACT_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_COMPACT_NONE   (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_ACTV_MASK   (0x00000010u)
+#define EDMA3_CCRL_CCSTAT_ACTV_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_CCSTAT_ACTV_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_ACTV_IDLE   (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_ACTV_BUSY   (0x00000001u)
+#define EDMA3_CCRL_CCSTAT_TRACTV_MASK   (0x00000004u)
+#define EDMA3_CCRL_CCSTAT_TRACTV_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_CCSTAT_TRACTV_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_TRACTV_NONE   (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_TRACTV_ACTIVE   (0x00000001u)
+#define EDMA3_CCRL_CCSTAT_QEVTACTV_MASK   (0x00000002u)
+#define EDMA3_CCRL_CCSTAT_QEVTACTV_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_CCSTAT_QEVTACTV_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_QEVTACTV_NONE   (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_QEVTACTV_ACTIVE   (0x00000001u)
+#define EDMA3_CCRL_CCSTAT_EVTACTV_MASK   (0x00000001u)
+#define EDMA3_CCRL_CCSTAT_EVTACTV_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_EVTACTV_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_EVTACTV_NONE   (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_EVTACTV_ACTIVE   (0x00000001u)
+#define EDMA3_CCRL_CCSTAT_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_AETCTL_EN_MASK   (0x80000000u)
+#define EDMA3_CCRL_AETCTL_EN_SHIFT   (0x0000001Fu)
+#define EDMA3_CCRL_AETCTL_EN_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_AETCTL_EN_DISABLE   (0x00000000u)
+#define EDMA3_CCRL_AETCTL_EN_ENABLE   (0x00000001u)
+#define EDMA3_CCRL_AETCTL_ENDINT_MASK   (0x00003F00u)
+#define EDMA3_CCRL_AETCTL_ENDINT_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_AETCTL_ENDINT_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_AETCTL_TYPE_MASK   (0x00000040u)
+#define EDMA3_CCRL_AETCTL_TYPE_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_AETCTL_TYPE_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_AETCTL_TYPE_DMA   (0x00000000u)
+#define EDMA3_CCRL_AETCTL_TYPE_QDMA   (0x00000001u)
+#define EDMA3_CCRL_AETCTL_STRTEVT_MASK   (0x0000003Fu)
+#define EDMA3_CCRL_AETCTL_STRTEVT_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_AETCTL_STRTEVT_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_AETCTL_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_AETSTAT_STAT_MASK   (0x00000001u)
+#define EDMA3_CCRL_AETSTAT_STAT_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_AETSTAT_STAT_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_AETSTAT_STAT_LOW   (0x00000000u)
+#define EDMA3_CCRL_AETSTAT_STAT_HIGH   (0x00000001u)
+#define EDMA3_CCRL_AETSTAT_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_AETCMD_CLR_MASK   (0x00000001u)
+#define EDMA3_CCRL_AETCMD_CLR_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_AETCMD_CLR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_AETCMD_CLR_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_AETCMD_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPFAR_FADDR_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_MPFAR_FADDR_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_MPFAR_FADDR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPFAR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPFSR_FID_MASK   (0x00001E00u)
+#define EDMA3_CCRL_MPFSR_FID_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_MPFSR_FID_RESETVAL   (0x00000009u)
+#define EDMA3_CCRL_MPFSR_SECE_MASK   (0x00000080u)
+#define EDMA3_CCRL_MPFSR_SECE_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_MPFSR_SECE_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPFSR_SRE_MASK   (0x00000020u)
+#define EDMA3_CCRL_MPFSR_SRE_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_MPFSR_SRE_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPFSR_SWE_MASK   (0x00000010u)
+#define EDMA3_CCRL_MPFSR_SWE_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_MPFSR_SWE_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPFSR_SXE_MASK   (0x00000008u)
+#define EDMA3_CCRL_MPFSR_SXE_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_MPFSR_SXE_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPFSR_URE_MASK   (0x00000004u)
+#define EDMA3_CCRL_MPFSR_URE_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_MPFSR_URE_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPFSR_UWE_MASK   (0x00000002u)
+#define EDMA3_CCRL_MPFSR_UWE_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_MPFSR_UWE_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPFSR_UXE_MASK   (0x00000001u)
+#define EDMA3_CCRL_MPFSR_UXE_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_MPFSR_UXE_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPFSR_RESETVAL   (0x00001200u)
+#define EDMA3_CCRL_MPFCR_MPFCLR_MASK   (0x00000001u)
+#define EDMA3_CCRL_MPFCR_MPFCLR_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_MPFCR_MPFCLR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPFCR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_AID5_MASK   (0x00008000u)
+#define EDMA3_CCRL_MPPAG_AID5_SHIFT   (0x0000000Fu)
+#define EDMA3_CCRL_MPPAG_AID5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_AID5_BLOCK   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_AID5_PERMIT   (0x00000001u)
+#define EDMA3_CCRL_MPPAG_AID4_MASK   (0x00004000u)
+#define EDMA3_CCRL_MPPAG_AID4_SHIFT   (0x0000000Eu)
+#define EDMA3_CCRL_MPPAG_AID4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_AID4_BLOCK   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_AID4_PERMIT   (0x00000001u)
+#define EDMA3_CCRL_MPPAG_AID3_MASK   (0x00002000u)
+#define EDMA3_CCRL_MPPAG_AID3_SHIFT   (0x0000000Du)
+#define EDMA3_CCRL_MPPAG_AID3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_AID3_BLOCK   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_AID3_PERMIT   (0x00000001u)
+#define EDMA3_CCRL_MPPAG_AID2_MASK   (0x00001000u)
+#define EDMA3_CCRL_MPPAG_AID2_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_MPPAG_AID2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_AID2_BLOCK   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_AID2_PERMIT   (0x00000001u)
+#define EDMA3_CCRL_MPPAG_AID1_MASK   (0x00000800u)
+#define EDMA3_CCRL_MPPAG_AID1_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_MPPAG_AID1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_AID1_BLOCK   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_AID1_PERMIT   (0x00000001u)
+#define EDMA3_CCRL_MPPAG_AID0_MASK   (0x00000400u)
+#define EDMA3_CCRL_MPPAG_AID0_SHIFT   (0x0000000Au)
+#define EDMA3_CCRL_MPPAG_AID0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_AID0_BLOCK   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_AID0_PERMIT   (0x00000001u)
+#define EDMA3_CCRL_MPPAG_EXT_MASK   (0x00000200u)
+#define EDMA3_CCRL_MPPAG_EXT_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_MPPAG_EXT_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_EXT_BLOCK   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_EXT_PERMIT   (0x00000001u)
+#define EDMA3_CCRL_MPPAG_LCL_MASK   (0x00000100u)
+#define EDMA3_CCRL_MPPAG_LCL_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_MPPAG_LCL_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_NS_MASK   (0x00000080u)
+#define EDMA3_CCRL_MPPAG_NS_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_MPPAG_NS_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_NS_SECURE   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_NS_NONSECURE   (0x00000001u)
+#define EDMA3_CCRL_MPPAG_EMU_MASK   (0x00000040u)
+#define EDMA3_CCRL_MPPAG_EMU_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_MPPAG_EMU_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_EMU_BLOCK   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_EMU_PERMIT   (0x00000001u)
+#define EDMA3_CCRL_MPPAG_SR_MASK   (0x00000020u)
+#define EDMA3_CCRL_MPPAG_SR_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_MPPAG_SR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_SR_BLOCK   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_SR_PERMIT   (0x00000001u)
+#define EDMA3_CCRL_MPPAG_SW_MASK   (0x00000010u)
+#define EDMA3_CCRL_MPPAG_SW_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_MPPAG_SW_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_SW_BLOCK   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_SW_PERMIT   (0x00000001u)
+#define EDMA3_CCRL_MPPAG_SX_MASK   (0x00000008u)
+#define EDMA3_CCRL_MPPAG_SX_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_MPPAG_SX_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_SX_BLOCK   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_SX_PERMIT   (0x00000001u)
+#define EDMA3_CCRL_MPPAG_UR_MASK   (0x00000004u)
+#define EDMA3_CCRL_MPPAG_UR_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_MPPAG_UR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_UR_BLOCK   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_UR_PERMIT   (0x00000001u)
+#define EDMA3_CCRL_MPPAG_UW_MASK   (0x00000002u)
+#define EDMA3_CCRL_MPPAG_UW_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_MPPAG_UW_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_UW_BLOCK   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_UW_PERMIT   (0x00000001u)
+#define EDMA3_CCRL_MPPAG_UX_MASK   (0x00000001u)
+#define EDMA3_CCRL_MPPAG_UX_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_UX_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_UX_BLOCK   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_UX_PERMIT   (0x00000001u)
+#define EDMA3_CCRL_MPPAG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPA_AID5_MASK   (0x00008000u)
+#define EDMA3_CCRL_MPPA_AID5_SHIFT   (0x0000000Fu)
+#define EDMA3_CCRL_MPPA_AID5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPA_AID5_BLOCK   (0x00000000u)
+#define EDMA3_CCRL_MPPA_AID5_PERMIT   (0x00000001u)
+#define EDMA3_CCRL_MPPA_AID4_MASK   (0x00004000u)
+#define EDMA3_CCRL_MPPA_AID4_SHIFT   (0x0000000Eu)
+#define EDMA3_CCRL_MPPA_AID4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPA_AID4_BLOCK   (0x00000000u)
+#define EDMA3_CCRL_MPPA_AID4_PERMIT   (0x00000001u)
+#define EDMA3_CCRL_MPPA_AID3_MASK   (0x00002000u)
+#define EDMA3_CCRL_MPPA_AID3_SHIFT   (0x0000000Du)
+#define EDMA3_CCRL_MPPA_AID3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPA_AID3_BLOCK   (0x00000000u)
+#define EDMA3_CCRL_MPPA_AID3_PERMIT   (0x00000001u)
+#define EDMA3_CCRL_MPPA_AID2_MASK   (0x00001000u)
+#define EDMA3_CCRL_MPPA_AID2_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_MPPA_AID2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPA_AID2_BLOCK   (0x00000000u)
+#define EDMA3_CCRL_MPPA_AID2_PERMIT   (0x00000001u)
+#define EDMA3_CCRL_MPPA_AID1_MASK   (0x00000800u)
+#define EDMA3_CCRL_MPPA_AID1_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_MPPA_AID1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPA_AID1_BLOCK   (0x00000000u)
+#define EDMA3_CCRL_MPPA_AID1_PERMIT   (0x00000001u)
+#define EDMA3_CCRL_MPPA_AID0_MASK   (0x00000400u)
+#define EDMA3_CCRL_MPPA_AID0_SHIFT   (0x0000000Au)
+#define EDMA3_CCRL_MPPA_AID0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPA_AID0_BLOCK   (0x00000000u)
+#define EDMA3_CCRL_MPPA_AID0_PERMIT   (0x00000001u)
+#define EDMA3_CCRL_MPPA_EXT_MASK   (0x00000200u)
+#define EDMA3_CCRL_MPPA_EXT_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_MPPA_EXT_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPA_EXT_BLOCK   (0x00000000u)
+#define EDMA3_CCRL_MPPA_EXT_PERMIT   (0x00000001u)
+#define EDMA3_CCRL_MPPA_LCL_MASK   (0x00000100u)
+#define EDMA3_CCRL_MPPA_LCL_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_MPPA_LCL_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPA_NS_MASK   (0x00000080u)
+#define EDMA3_CCRL_MPPA_NS_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_MPPA_NS_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPA_NS_SECURE   (0x00000000u)
+#define EDMA3_CCRL_MPPA_NS_NONSECURE   (0x00000001u)
+#define EDMA3_CCRL_MPPA_EMU_MASK   (0x00000040u)
+#define EDMA3_CCRL_MPPA_EMU_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_MPPA_EMU_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPA_EMU_BLOCK   (0x00000000u)
+#define EDMA3_CCRL_MPPA_EMU_PERMIT   (0x00000001u)
+#define EDMA3_CCRL_MPPA_SR_MASK   (0x00000020u)
+#define EDMA3_CCRL_MPPA_SR_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_MPPA_SR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPA_SR_BLOCK   (0x00000000u)
+#define EDMA3_CCRL_MPPA_SR_PERMIT   (0x00000001u)
+#define EDMA3_CCRL_MPPA_SW_MASK   (0x00000010u)
+#define EDMA3_CCRL_MPPA_SW_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_MPPA_SW_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPA_SW_BLOCK   (0x00000000u)
+#define EDMA3_CCRL_MPPA_SW_PERMIT   (0x00000001u)
+#define EDMA3_CCRL_MPPA_SX_MASK   (0x00000008u)
+#define EDMA3_CCRL_MPPA_SX_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_MPPA_SX_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPA_SX_BLOCK   (0x00000000u)
+#define EDMA3_CCRL_MPPA_SX_PERMIT   (0x00000001u)
+#define EDMA3_CCRL_MPPA_UR_MASK   (0x00000004u)
+#define EDMA3_CCRL_MPPA_UR_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_MPPA_UR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPA_UR_BLOCK   (0x00000000u)
+#define EDMA3_CCRL_MPPA_UR_PERMIT   (0x00000001u)
+#define EDMA3_CCRL_MPPA_UW_MASK   (0x00000002u)
+#define EDMA3_CCRL_MPPA_UW_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_MPPA_UW_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPA_UW_BLOCK   (0x00000000u)
+#define EDMA3_CCRL_MPPA_UW_PERMIT   (0x00000001u)
+#define EDMA3_CCRL_MPPA_UX_MASK   (0x00000001u)
+#define EDMA3_CCRL_MPPA_UX_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_MPPA_UX_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPA_UX_BLOCK   (0x00000000u)
+#define EDMA3_CCRL_MPPA_UX_PERMIT   (0x00000001u)
+#define EDMA3_CCRL_MPPA_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ER_E31_MASK   (0x80000000u)
+#define EDMA3_CCRL_ER_E31_SHIFT   (0x0000001Fu)
+#define EDMA3_CCRL_ER_E31_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ER_E30_MASK   (0x40000000u)
+#define EDMA3_CCRL_ER_E30_SHIFT   (0x0000001Eu)
+#define EDMA3_CCRL_ER_E30_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ER_E29_MASK   (0x20000000u)
+#define EDMA3_CCRL_ER_E29_SHIFT   (0x0000001Du)
+#define EDMA3_CCRL_ER_E29_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ER_E28_MASK   (0x10000000u)
+#define EDMA3_CCRL_ER_E28_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_ER_E28_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ER_E27_MASK   (0x08000000u)
+#define EDMA3_CCRL_ER_E27_SHIFT   (0x0000001Bu)
+#define EDMA3_CCRL_ER_E27_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ER_E26_MASK   (0x04000000u)
+#define EDMA3_CCRL_ER_E26_SHIFT   (0x0000001Au)
+#define EDMA3_CCRL_ER_E26_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ER_E25_MASK   (0x02000000u)
+#define EDMA3_CCRL_ER_E25_SHIFT   (0x00000019u)
+#define EDMA3_CCRL_ER_E25_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ER_E24_MASK   (0x01000000u)
+#define EDMA3_CCRL_ER_E24_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_ER_E24_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ER_E23_MASK   (0x00800000u)
+#define EDMA3_CCRL_ER_E23_SHIFT   (0x00000017u)
+#define EDMA3_CCRL_ER_E23_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ER_E22_MASK   (0x00400000u)
+#define EDMA3_CCRL_ER_E22_SHIFT   (0x00000016u)
+#define EDMA3_CCRL_ER_E22_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ER_E21_MASK   (0x00200000u)
+#define EDMA3_CCRL_ER_E21_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_ER_E21_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ER_E20_MASK   (0x00100000u)
+#define EDMA3_CCRL_ER_E20_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_ER_E20_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ER_E19_MASK   (0x00080000u)
+#define EDMA3_CCRL_ER_E19_SHIFT   (0x00000013u)
+#define EDMA3_CCRL_ER_E19_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ER_E18_MASK   (0x00040000u)
+#define EDMA3_CCRL_ER_E18_SHIFT   (0x00000012u)
+#define EDMA3_CCRL_ER_E18_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ER_E17_MASK   (0x00020000u)
+#define EDMA3_CCRL_ER_E17_SHIFT   (0x00000011u)
+#define EDMA3_CCRL_ER_E17_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ER_E16_MASK   (0x00010000u)
+#define EDMA3_CCRL_ER_E16_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_ER_E16_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ER_E15_MASK   (0x00008000u)
+#define EDMA3_CCRL_ER_E15_SHIFT   (0x0000000Fu)
+#define EDMA3_CCRL_ER_E15_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ER_E14_MASK   (0x00004000u)
+#define EDMA3_CCRL_ER_E14_SHIFT   (0x0000000Eu)
+#define EDMA3_CCRL_ER_E14_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ER_E13_MASK   (0x00002000u)
+#define EDMA3_CCRL_ER_E13_SHIFT   (0x0000000Du)
+#define EDMA3_CCRL_ER_E13_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ER_E12_MASK   (0x00001000u)
+#define EDMA3_CCRL_ER_E12_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_ER_E12_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ER_E11_MASK   (0x00000800u)
+#define EDMA3_CCRL_ER_E11_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_ER_E11_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ER_E10_MASK   (0x00000400u)
+#define EDMA3_CCRL_ER_E10_SHIFT   (0x0000000Au)
+#define EDMA3_CCRL_ER_E10_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ER_E9_MASK   (0x00000200u)
+#define EDMA3_CCRL_ER_E9_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_ER_E9_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ER_E8_MASK   (0x00000100u)
+#define EDMA3_CCRL_ER_E8_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_ER_E8_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ER_E7_MASK   (0x00000080u)
+#define EDMA3_CCRL_ER_E7_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_ER_E7_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ER_E6_MASK   (0x00000040u)
+#define EDMA3_CCRL_ER_E6_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_ER_E6_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ER_E5_MASK   (0x00000020u)
+#define EDMA3_CCRL_ER_E5_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_ER_E5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ER_E4_MASK   (0x00000010u)
+#define EDMA3_CCRL_ER_E4_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_ER_E4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ER_E3_MASK   (0x00000008u)
+#define EDMA3_CCRL_ER_E3_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_ER_E3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ER_E2_MASK   (0x00000004u)
+#define EDMA3_CCRL_ER_E2_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_ER_E2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ER_E1_MASK   (0x00000002u)
+#define EDMA3_CCRL_ER_E1_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_ER_E1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ER_E0_MASK   (0x00000001u)
+#define EDMA3_CCRL_ER_E0_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_ER_E0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ER_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ERH_E63_MASK   (0x80000000u)
+#define EDMA3_CCRL_ERH_E63_SHIFT   (0x0000001Fu)
+#define EDMA3_CCRL_ERH_E63_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ERH_E62_MASK   (0x40000000u)
+#define EDMA3_CCRL_ERH_E62_SHIFT   (0x0000001Eu)
+#define EDMA3_CCRL_ERH_E62_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ERH_E61_MASK   (0x20000000u)
+#define EDMA3_CCRL_ERH_E61_SHIFT   (0x0000001Du)
+#define EDMA3_CCRL_ERH_E61_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ERH_E60_MASK   (0x10000000u)
+#define EDMA3_CCRL_ERH_E60_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_ERH_E60_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ERH_E59_MASK   (0x08000000u)
+#define EDMA3_CCRL_ERH_E59_SHIFT   (0x0000001Bu)
+#define EDMA3_CCRL_ERH_E59_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ERH_E58_MASK   (0x04000000u)
+#define EDMA3_CCRL_ERH_E58_SHIFT   (0x0000001Au)
+#define EDMA3_CCRL_ERH_E58_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ERH_E57_MASK   (0x02000000u)
+#define EDMA3_CCRL_ERH_E57_SHIFT   (0x00000019u)
+#define EDMA3_CCRL_ERH_E57_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ERH_E56_MASK   (0x01000000u)
+#define EDMA3_CCRL_ERH_E56_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_ERH_E56_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ERH_E55_MASK   (0x00800000u)
+#define EDMA3_CCRL_ERH_E55_SHIFT   (0x00000017u)
+#define EDMA3_CCRL_ERH_E55_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ERH_E54_MASK   (0x00400000u)
+#define EDMA3_CCRL_ERH_E54_SHIFT   (0x00000016u)
+#define EDMA3_CCRL_ERH_E54_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ERH_E53_MASK   (0x00200000u)
+#define EDMA3_CCRL_ERH_E53_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_ERH_E53_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ERH_E52_MASK   (0x00100000u)
+#define EDMA3_CCRL_ERH_E52_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_ERH_E52_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ERH_E51_MASK   (0x00080000u)
+#define EDMA3_CCRL_ERH_E51_SHIFT   (0x00000013u)
+#define EDMA3_CCRL_ERH_E51_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ERH_E50_MASK   (0x00040000u)
+#define EDMA3_CCRL_ERH_E50_SHIFT   (0x00000012u)
+#define EDMA3_CCRL_ERH_E50_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ERH_E49_MASK   (0x00020000u)
+#define EDMA3_CCRL_ERH_E49_SHIFT   (0x00000011u)
+#define EDMA3_CCRL_ERH_E49_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ERH_E48_MASK   (0x00010000u)
+#define EDMA3_CCRL_ERH_E48_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_ERH_E48_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ERH_E47_MASK   (0x00008000u)
+#define EDMA3_CCRL_ERH_E47_SHIFT   (0x0000000Fu)
+#define EDMA3_CCRL_ERH_E47_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ERH_E46_MASK   (0x00004000u)
+#define EDMA3_CCRL_ERH_E46_SHIFT   (0x0000000Eu)
+#define EDMA3_CCRL_ERH_E46_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ERH_E45_MASK   (0x00002000u)
+#define EDMA3_CCRL_ERH_E45_SHIFT   (0x0000000Du)
+#define EDMA3_CCRL_ERH_E45_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ERH_E44_MASK   (0x00001000u)
+#define EDMA3_CCRL_ERH_E44_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_ERH_E44_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ERH_E43_MASK   (0x00000800u)
+#define EDMA3_CCRL_ERH_E43_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_ERH_E43_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ERH_E42_MASK   (0x00000400u)
+#define EDMA3_CCRL_ERH_E42_SHIFT   (0x0000000Au)
+#define EDMA3_CCRL_ERH_E42_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ERH_E41_MASK   (0x00000200u)
+#define EDMA3_CCRL_ERH_E41_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_ERH_E41_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ERH_E40_MASK   (0x00000100u)
+#define EDMA3_CCRL_ERH_E40_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_ERH_E40_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ERH_E39_MASK   (0x00000080u)
+#define EDMA3_CCRL_ERH_E39_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_ERH_E39_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ERH_E38_MASK   (0x00000040u)
+#define EDMA3_CCRL_ERH_E38_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_ERH_E38_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ERH_E37_MASK   (0x00000020u)
+#define EDMA3_CCRL_ERH_E37_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_ERH_E37_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ERH_E36_MASK   (0x00000010u)
+#define EDMA3_CCRL_ERH_E36_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_ERH_E36_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ERH_E35_MASK   (0x00000008u)
+#define EDMA3_CCRL_ERH_E35_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_ERH_E35_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ERH_E34_MASK   (0x00000004u)
+#define EDMA3_CCRL_ERH_E34_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_ERH_E34_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ERH_E33_MASK   (0x00000002u)
+#define EDMA3_CCRL_ERH_E33_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_ERH_E33_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ERH_E32_MASK   (0x00000001u)
+#define EDMA3_CCRL_ERH_E32_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_ERH_E32_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ERH_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECR_E31_MASK   (0x80000000u)
+#define EDMA3_CCRL_ECR_E31_SHIFT   (0x0000001Fu)
+#define EDMA3_CCRL_ECR_E31_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECR_E31_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECR_E30_MASK   (0x40000000u)
+#define EDMA3_CCRL_ECR_E30_SHIFT   (0x0000001Eu)
+#define EDMA3_CCRL_ECR_E30_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECR_E30_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECR_E29_MASK   (0x20000000u)
+#define EDMA3_CCRL_ECR_E29_SHIFT   (0x0000001Du)
+#define EDMA3_CCRL_ECR_E29_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECR_E29_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECR_E28_MASK   (0x10000000u)
+#define EDMA3_CCRL_ECR_E28_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_ECR_E28_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECR_E28_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECR_E27_MASK   (0x08000000u)
+#define EDMA3_CCRL_ECR_E27_SHIFT   (0x0000001Bu)
+#define EDMA3_CCRL_ECR_E27_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECR_E27_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECR_E26_MASK   (0x04000000u)
+#define EDMA3_CCRL_ECR_E26_SHIFT   (0x0000001Au)
+#define EDMA3_CCRL_ECR_E26_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECR_E26_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECR_E25_MASK   (0x02000000u)
+#define EDMA3_CCRL_ECR_E25_SHIFT   (0x00000019u)
+#define EDMA3_CCRL_ECR_E25_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECR_E25_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECR_E24_MASK   (0x01000000u)
+#define EDMA3_CCRL_ECR_E24_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_ECR_E24_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECR_E24_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECR_E23_MASK   (0x00800000u)
+#define EDMA3_CCRL_ECR_E23_SHIFT   (0x00000017u)
+#define EDMA3_CCRL_ECR_E23_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECR_E23_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECR_E22_MASK   (0x00400000u)
+#define EDMA3_CCRL_ECR_E22_SHIFT   (0x00000016u)
+#define EDMA3_CCRL_ECR_E22_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECR_E22_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECR_E21_MASK   (0x00200000u)
+#define EDMA3_CCRL_ECR_E21_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_ECR_E21_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECR_E21_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECR_E20_MASK   (0x00100000u)
+#define EDMA3_CCRL_ECR_E20_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_ECR_E20_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECR_E20_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECR_E19_MASK   (0x00080000u)
+#define EDMA3_CCRL_ECR_E19_SHIFT   (0x00000013u)
+#define EDMA3_CCRL_ECR_E19_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECR_E19_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECR_E18_MASK   (0x00040000u)
+#define EDMA3_CCRL_ECR_E18_SHIFT   (0x00000012u)
+#define EDMA3_CCRL_ECR_E18_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECR_E18_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECR_E17_MASK   (0x00020000u)
+#define EDMA3_CCRL_ECR_E17_SHIFT   (0x00000011u)
+#define EDMA3_CCRL_ECR_E17_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECR_E17_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECR_E16_MASK   (0x00010000u)
+#define EDMA3_CCRL_ECR_E16_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_ECR_E16_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECR_E16_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECR_E15_MASK   (0x00008000u)
+#define EDMA3_CCRL_ECR_E15_SHIFT   (0x0000000Fu)
+#define EDMA3_CCRL_ECR_E15_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECR_E15_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECR_E14_MASK   (0x00004000u)
+#define EDMA3_CCRL_ECR_E14_SHIFT   (0x0000000Eu)
+#define EDMA3_CCRL_ECR_E14_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECR_E14_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECR_E13_MASK   (0x00002000u)
+#define EDMA3_CCRL_ECR_E13_SHIFT   (0x0000000Du)
+#define EDMA3_CCRL_ECR_E13_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECR_E13_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECR_E12_MASK   (0x00001000u)
+#define EDMA3_CCRL_ECR_E12_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_ECR_E12_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECR_E12_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECR_E11_MASK   (0x00000800u)
+#define EDMA3_CCRL_ECR_E11_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_ECR_E11_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECR_E11_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECR_E10_MASK   (0x00000400u)
+#define EDMA3_CCRL_ECR_E10_SHIFT   (0x0000000Au)
+#define EDMA3_CCRL_ECR_E10_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECR_E10_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECR_E9_MASK   (0x00000200u)
+#define EDMA3_CCRL_ECR_E9_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_ECR_E9_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECR_E9_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECR_E8_MASK   (0x00000100u)
+#define EDMA3_CCRL_ECR_E8_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_ECR_E8_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECR_E8_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECR_E7_MASK   (0x00000080u)
+#define EDMA3_CCRL_ECR_E7_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_ECR_E7_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECR_E7_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECR_E6_MASK   (0x00000040u)
+#define EDMA3_CCRL_ECR_E6_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_ECR_E6_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECR_E6_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECR_E5_MASK   (0x00000020u)
+#define EDMA3_CCRL_ECR_E5_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_ECR_E5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECR_E5_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECR_E4_MASK   (0x00000010u)
+#define EDMA3_CCRL_ECR_E4_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_ECR_E4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECR_E4_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECR_E3_MASK   (0x00000008u)
+#define EDMA3_CCRL_ECR_E3_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_ECR_E3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECR_E3_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECR_E2_MASK   (0x00000004u)
+#define EDMA3_CCRL_ECR_E2_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_ECR_E2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECR_E2_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECR_E1_MASK   (0x00000002u)
+#define EDMA3_CCRL_ECR_E1_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_ECR_E1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECR_E1_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECR_E0_MASK   (0x00000001u)
+#define EDMA3_CCRL_ECR_E0_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_ECR_E0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECR_E0_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECRH_E63_MASK   (0x80000000u)
+#define EDMA3_CCRL_ECRH_E63_SHIFT   (0x0000001Fu)
+#define EDMA3_CCRL_ECRH_E63_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECRH_E63_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECRH_E62_MASK   (0x40000000u)
+#define EDMA3_CCRL_ECRH_E62_SHIFT   (0x0000001Eu)
+#define EDMA3_CCRL_ECRH_E62_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECRH_E62_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECRH_E61_MASK   (0x20000000u)
+#define EDMA3_CCRL_ECRH_E61_SHIFT   (0x0000001Du)
+#define EDMA3_CCRL_ECRH_E61_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECRH_E61_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECRH_E60_MASK   (0x10000000u)
+#define EDMA3_CCRL_ECRH_E60_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_ECRH_E60_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECRH_E60_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECRH_E59_MASK   (0x08000000u)
+#define EDMA3_CCRL_ECRH_E59_SHIFT   (0x0000001Bu)
+#define EDMA3_CCRL_ECRH_E59_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECRH_E59_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECRH_E58_MASK   (0x04000000u)
+#define EDMA3_CCRL_ECRH_E58_SHIFT   (0x0000001Au)
+#define EDMA3_CCRL_ECRH_E58_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECRH_E58_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECRH_E57_MASK   (0x02000000u)
+#define EDMA3_CCRL_ECRH_E57_SHIFT   (0x00000019u)
+#define EDMA3_CCRL_ECRH_E57_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECRH_E57_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECRH_E56_MASK   (0x01000000u)
+#define EDMA3_CCRL_ECRH_E56_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_ECRH_E56_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECRH_E56_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECRH_E55_MASK   (0x00800000u)
+#define EDMA3_CCRL_ECRH_E55_SHIFT   (0x00000017u)
+#define EDMA3_CCRL_ECRH_E55_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECRH_E55_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECRH_E54_MASK   (0x00400000u)
+#define EDMA3_CCRL_ECRH_E54_SHIFT   (0x00000016u)
+#define EDMA3_CCRL_ECRH_E54_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECRH_E54_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECRH_E53_MASK   (0x00200000u)
+#define EDMA3_CCRL_ECRH_E53_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_ECRH_E53_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECRH_E53_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECRH_E52_MASK   (0x00100000u)
+#define EDMA3_CCRL_ECRH_E52_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_ECRH_E52_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECRH_E52_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECRH_E51_MASK   (0x00080000u)
+#define EDMA3_CCRL_ECRH_E51_SHIFT   (0x00000013u)
+#define EDMA3_CCRL_ECRH_E51_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECRH_E51_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECRH_E50_MASK   (0x00040000u)
+#define EDMA3_CCRL_ECRH_E50_SHIFT   (0x00000012u)
+#define EDMA3_CCRL_ECRH_E50_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECRH_E50_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECRH_E49_MASK   (0x00020000u)
+#define EDMA3_CCRL_ECRH_E49_SHIFT   (0x00000011u)
+#define EDMA3_CCRL_ECRH_E49_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECRH_E49_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECRH_E48_MASK   (0x00010000u)
+#define EDMA3_CCRL_ECRH_E48_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_ECRH_E48_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECRH_E48_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECRH_E47_MASK   (0x00008000u)
+#define EDMA3_CCRL_ECRH_E47_SHIFT   (0x0000000Fu)
+#define EDMA3_CCRL_ECRH_E47_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECRH_E47_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECRH_E46_MASK   (0x00004000u)
+#define EDMA3_CCRL_ECRH_E46_SHIFT   (0x0000000Eu)
+#define EDMA3_CCRL_ECRH_E46_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECRH_E46_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECRH_E45_MASK   (0x00002000u)
+#define EDMA3_CCRL_ECRH_E45_SHIFT   (0x0000000Du)
+#define EDMA3_CCRL_ECRH_E45_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECRH_E45_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECRH_E44_MASK   (0x00001000u)
+#define EDMA3_CCRL_ECRH_E44_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_ECRH_E44_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECRH_E44_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECRH_E43_MASK   (0x00000800u)
+#define EDMA3_CCRL_ECRH_E43_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_ECRH_E43_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECRH_E43_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECRH_E42_MASK   (0x00000400u)
+#define EDMA3_CCRL_ECRH_E42_SHIFT   (0x0000000Au)
+#define EDMA3_CCRL_ECRH_E42_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECRH_E42_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECRH_E41_MASK   (0x00000200u)
+#define EDMA3_CCRL_ECRH_E41_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_ECRH_E41_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECRH_E41_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECRH_E40_MASK   (0x00000100u)
+#define EDMA3_CCRL_ECRH_E40_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_ECRH_E40_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECRH_E40_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECRH_E39_MASK   (0x00000080u)
+#define EDMA3_CCRL_ECRH_E39_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_ECRH_E39_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECRH_E39_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECRH_E38_MASK   (0x00000040u)
+#define EDMA3_CCRL_ECRH_E38_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_ECRH_E38_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECRH_E38_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECRH_E37_MASK   (0x00000020u)
+#define EDMA3_CCRL_ECRH_E37_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_ECRH_E37_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECRH_E37_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECRH_E36_MASK   (0x00000010u)
+#define EDMA3_CCRL_ECRH_E36_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_ECRH_E36_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECRH_E36_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECRH_E35_MASK   (0x00000008u)
+#define EDMA3_CCRL_ECRH_E35_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_ECRH_E35_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECRH_E35_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECRH_E34_MASK   (0x00000004u)
+#define EDMA3_CCRL_ECRH_E34_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_ECRH_E34_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECRH_E34_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECRH_E33_MASK   (0x00000002u)
+#define EDMA3_CCRL_ECRH_E33_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_ECRH_E33_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECRH_E33_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECRH_E32_MASK   (0x00000001u)
+#define EDMA3_CCRL_ECRH_E32_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_ECRH_E32_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECRH_E32_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ECRH_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESR_E31_MASK   (0x80000000u)
+#define EDMA3_CCRL_ESR_E31_SHIFT   (0x0000001Fu)
+#define EDMA3_CCRL_ESR_E31_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESR_E31_SET   (0x00000001u)
+#define EDMA3_CCRL_ESR_E30_MASK   (0x40000000u)
+#define EDMA3_CCRL_ESR_E30_SHIFT   (0x0000001Eu)
+#define EDMA3_CCRL_ESR_E30_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESR_E30_SET   (0x00000001u)
+#define EDMA3_CCRL_ESR_E29_MASK   (0x20000000u)
+#define EDMA3_CCRL_ESR_E29_SHIFT   (0x0000001Du)
+#define EDMA3_CCRL_ESR_E29_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESR_E29_SET   (0x00000001u)
+#define EDMA3_CCRL_ESR_E28_MASK   (0x10000000u)
+#define EDMA3_CCRL_ESR_E28_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_ESR_E28_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESR_E28_SET   (0x00000001u)
+#define EDMA3_CCRL_ESR_E27_MASK   (0x08000000u)
+#define EDMA3_CCRL_ESR_E27_SHIFT   (0x0000001Bu)
+#define EDMA3_CCRL_ESR_E27_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESR_E27_SET   (0x00000001u)
+#define EDMA3_CCRL_ESR_E26_MASK   (0x04000000u)
+#define EDMA3_CCRL_ESR_E26_SHIFT   (0x0000001Au)
+#define EDMA3_CCRL_ESR_E26_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESR_E26_SET   (0x00000001u)
+#define EDMA3_CCRL_ESR_E25_MASK   (0x02000000u)
+#define EDMA3_CCRL_ESR_E25_SHIFT   (0x00000019u)
+#define EDMA3_CCRL_ESR_E25_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESR_E25_SET   (0x00000001u)
+#define EDMA3_CCRL_ESR_E24_MASK   (0x01000000u)
+#define EDMA3_CCRL_ESR_E24_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_ESR_E24_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESR_E24_SET   (0x00000001u)
+#define EDMA3_CCRL_ESR_E23_MASK   (0x00800000u)
+#define EDMA3_CCRL_ESR_E23_SHIFT   (0x00000017u)
+#define EDMA3_CCRL_ESR_E23_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESR_E23_SET   (0x00000001u)
+#define EDMA3_CCRL_ESR_E22_MASK   (0x00400000u)
+#define EDMA3_CCRL_ESR_E22_SHIFT   (0x00000016u)
+#define EDMA3_CCRL_ESR_E22_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESR_E22_SET   (0x00000001u)
+#define EDMA3_CCRL_ESR_E21_MASK   (0x00200000u)
+#define EDMA3_CCRL_ESR_E21_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_ESR_E21_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESR_E21_SET   (0x00000001u)
+#define EDMA3_CCRL_ESR_E20_MASK   (0x00100000u)
+#define EDMA3_CCRL_ESR_E20_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_ESR_E20_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESR_E20_SET   (0x00000001u)
+#define EDMA3_CCRL_ESR_E19_MASK   (0x00080000u)
+#define EDMA3_CCRL_ESR_E19_SHIFT   (0x00000013u)
+#define EDMA3_CCRL_ESR_E19_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESR_E19_SET   (0x00000001u)
+#define EDMA3_CCRL_ESR_E18_MASK   (0x00040000u)
+#define EDMA3_CCRL_ESR_E18_SHIFT   (0x00000012u)
+#define EDMA3_CCRL_ESR_E18_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESR_E18_SET   (0x00000001u)
+#define EDMA3_CCRL_ESR_E17_MASK   (0x00020000u)
+#define EDMA3_CCRL_ESR_E17_SHIFT   (0x00000011u)
+#define EDMA3_CCRL_ESR_E17_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESR_E17_SET   (0x00000001u)
+#define EDMA3_CCRL_ESR_E16_MASK   (0x00010000u)
+#define EDMA3_CCRL_ESR_E16_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_ESR_E16_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESR_E16_SET   (0x00000001u)
+#define EDMA3_CCRL_ESR_E15_MASK   (0x00008000u)
+#define EDMA3_CCRL_ESR_E15_SHIFT   (0x0000000Fu)
+#define EDMA3_CCRL_ESR_E15_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESR_E15_SET   (0x00000001u)
+#define EDMA3_CCRL_ESR_E14_MASK   (0x00004000u)
+#define EDMA3_CCRL_ESR_E14_SHIFT   (0x0000000Eu)
+#define EDMA3_CCRL_ESR_E14_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESR_E14_SET   (0x00000001u)
+#define EDMA3_CCRL_ESR_E13_MASK   (0x00002000u)
+#define EDMA3_CCRL_ESR_E13_SHIFT   (0x0000000Du)
+#define EDMA3_CCRL_ESR_E13_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESR_E13_SET   (0x00000001u)
+#define EDMA3_CCRL_ESR_E12_MASK   (0x00001000u)
+#define EDMA3_CCRL_ESR_E12_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_ESR_E12_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESR_E12_SET   (0x00000001u)
+#define EDMA3_CCRL_ESR_E11_MASK   (0x00000800u)
+#define EDMA3_CCRL_ESR_E11_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_ESR_E11_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESR_E11_SET   (0x00000001u)
+#define EDMA3_CCRL_ESR_E10_MASK   (0x00000400u)
+#define EDMA3_CCRL_ESR_E10_SHIFT   (0x0000000Au)
+#define EDMA3_CCRL_ESR_E10_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESR_E10_SET   (0x00000001u)
+#define EDMA3_CCRL_ESR_E9_MASK   (0x00000200u)
+#define EDMA3_CCRL_ESR_E9_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_ESR_E9_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESR_E9_SET   (0x00000001u)
+#define EDMA3_CCRL_ESR_E8_MASK   (0x00000100u)
+#define EDMA3_CCRL_ESR_E8_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_ESR_E8_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESR_E8_SET   (0x00000001u)
+#define EDMA3_CCRL_ESR_E7_MASK   (0x00000080u)
+#define EDMA3_CCRL_ESR_E7_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_ESR_E7_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESR_E7_SET   (0x00000001u)
+#define EDMA3_CCRL_ESR_E6_MASK   (0x00000040u)
+#define EDMA3_CCRL_ESR_E6_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_ESR_E6_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESR_E6_SET   (0x00000001u)
+#define EDMA3_CCRL_ESR_E5_MASK   (0x00000020u)
+#define EDMA3_CCRL_ESR_E5_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_ESR_E5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESR_E5_SET   (0x00000001u)
+#define EDMA3_CCRL_ESR_E4_MASK   (0x00000010u)
+#define EDMA3_CCRL_ESR_E4_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_ESR_E4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESR_E4_SET   (0x00000001u)
+#define EDMA3_CCRL_ESR_E3_MASK   (0x00000008u)
+#define EDMA3_CCRL_ESR_E3_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_ESR_E3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESR_E3_SET   (0x00000001u)
+#define EDMA3_CCRL_ESR_E2_MASK   (0x00000004u)
+#define EDMA3_CCRL_ESR_E2_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_ESR_E2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESR_E2_SET   (0x00000001u)
+#define EDMA3_CCRL_ESR_E1_MASK   (0x00000002u)
+#define EDMA3_CCRL_ESR_E1_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_ESR_E1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESR_E1_SET   (0x00000001u)
+#define EDMA3_CCRL_ESR_E0_MASK   (0x00000001u)
+#define EDMA3_CCRL_ESR_E0_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_ESR_E0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESR_E0_SET   (0x00000001u)
+#define EDMA3_CCRL_ESR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESRH_E63_MASK   (0x80000000u)
+#define EDMA3_CCRL_ESRH_E63_SHIFT   (0x0000001Fu)
+#define EDMA3_CCRL_ESRH_E63_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESRH_E63_SET   (0x00000001u)
+#define EDMA3_CCRL_ESRH_E62_MASK   (0x40000000u)
+#define EDMA3_CCRL_ESRH_E62_SHIFT   (0x0000001Eu)
+#define EDMA3_CCRL_ESRH_E62_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESRH_E62_SET   (0x00000001u)
+#define EDMA3_CCRL_ESRH_E61_MASK   (0x20000000u)
+#define EDMA3_CCRL_ESRH_E61_SHIFT   (0x0000001Du)
+#define EDMA3_CCRL_ESRH_E61_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESRH_E61_SET   (0x00000001u)
+#define EDMA3_CCRL_ESRH_E60_MASK   (0x10000000u)
+#define EDMA3_CCRL_ESRH_E60_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_ESRH_E60_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESRH_E60_SET   (0x00000001u)
+#define EDMA3_CCRL_ESRH_E59_MASK   (0x08000000u)
+#define EDMA3_CCRL_ESRH_E59_SHIFT   (0x0000001Bu)
+#define EDMA3_CCRL_ESRH_E59_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESRH_E59_SET   (0x00000001u)
+#define EDMA3_CCRL_ESRH_E58_MASK   (0x04000000u)
+#define EDMA3_CCRL_ESRH_E58_SHIFT   (0x0000001Au)
+#define EDMA3_CCRL_ESRH_E58_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESRH_E58_SET   (0x00000001u)
+#define EDMA3_CCRL_ESRH_E57_MASK   (0x02000000u)
+#define EDMA3_CCRL_ESRH_E57_SHIFT   (0x00000019u)
+#define EDMA3_CCRL_ESRH_E57_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESRH_E57_SET   (0x00000001u)
+#define EDMA3_CCRL_ESRH_E56_MASK   (0x01000000u)
+#define EDMA3_CCRL_ESRH_E56_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_ESRH_E56_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESRH_E56_SET   (0x00000001u)
+#define EDMA3_CCRL_ESRH_E55_MASK   (0x00800000u)
+#define EDMA3_CCRL_ESRH_E55_SHIFT   (0x00000017u)
+#define EDMA3_CCRL_ESRH_E55_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESRH_E55_SET   (0x00000001u)
+#define EDMA3_CCRL_ESRH_E54_MASK   (0x00400000u)
+#define EDMA3_CCRL_ESRH_E54_SHIFT   (0x00000016u)
+#define EDMA3_CCRL_ESRH_E54_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESRH_E54_SET   (0x00000001u)
+#define EDMA3_CCRL_ESRH_E53_MASK   (0x00200000u)
+#define EDMA3_CCRL_ESRH_E53_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_ESRH_E53_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESRH_E53_SET   (0x00000001u)
+#define EDMA3_CCRL_ESRH_E52_MASK   (0x00100000u)
+#define EDMA3_CCRL_ESRH_E52_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_ESRH_E52_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESRH_E52_SET   (0x00000001u)
+#define EDMA3_CCRL_ESRH_E51_MASK   (0x00080000u)
+#define EDMA3_CCRL_ESRH_E51_SHIFT   (0x00000013u)
+#define EDMA3_CCRL_ESRH_E51_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESRH_E51_SET   (0x00000001u)
+#define EDMA3_CCRL_ESRH_E50_MASK   (0x00040000u)
+#define EDMA3_CCRL_ESRH_E50_SHIFT   (0x00000012u)
+#define EDMA3_CCRL_ESRH_E50_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESRH_E50_SET   (0x00000001u)
+#define EDMA3_CCRL_ESRH_E49_MASK   (0x00020000u)
+#define EDMA3_CCRL_ESRH_E49_SHIFT   (0x00000011u)
+#define EDMA3_CCRL_ESRH_E49_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESRH_E49_SET   (0x00000001u)
+#define EDMA3_CCRL_ESRH_E48_MASK   (0x00010000u)
+#define EDMA3_CCRL_ESRH_E48_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_ESRH_E48_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESRH_E48_SET   (0x00000001u)
+#define EDMA3_CCRL_ESRH_E47_MASK   (0x00008000u)
+#define EDMA3_CCRL_ESRH_E47_SHIFT   (0x0000000Fu)
+#define EDMA3_CCRL_ESRH_E47_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESRH_E47_SET   (0x00000001u)
+#define EDMA3_CCRL_ESRH_E46_MASK   (0x00004000u)
+#define EDMA3_CCRL_ESRH_E46_SHIFT   (0x0000000Eu)
+#define EDMA3_CCRL_ESRH_E46_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESRH_E46_SET   (0x00000001u)
+#define EDMA3_CCRL_ESRH_E45_MASK   (0x00002000u)
+#define EDMA3_CCRL_ESRH_E45_SHIFT   (0x0000000Du)
+#define EDMA3_CCRL_ESRH_E45_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESRH_E45_SET   (0x00000001u)
+#define EDMA3_CCRL_ESRH_E44_MASK   (0x00001000u)
+#define EDMA3_CCRL_ESRH_E44_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_ESRH_E44_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESRH_E44_SET   (0x00000001u)
+#define EDMA3_CCRL_ESRH_E43_MASK   (0x00000800u)
+#define EDMA3_CCRL_ESRH_E43_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_ESRH_E43_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESRH_E43_SET   (0x00000001u)
+#define EDMA3_CCRL_ESRH_E42_MASK   (0x00000400u)
+#define EDMA3_CCRL_ESRH_E42_SHIFT   (0x0000000Au)
+#define EDMA3_CCRL_ESRH_E42_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESRH_E42_SET   (0x00000001u)
+#define EDMA3_CCRL_ESRH_E41_MASK   (0x00000200u)
+#define EDMA3_CCRL_ESRH_E41_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_ESRH_E41_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESRH_E41_SET   (0x00000001u)
+#define EDMA3_CCRL_ESRH_E40_MASK   (0x00000100u)
+#define EDMA3_CCRL_ESRH_E40_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_ESRH_E40_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESRH_E40_SET   (0x00000001u)
+#define EDMA3_CCRL_ESRH_E39_MASK   (0x00000080u)
+#define EDMA3_CCRL_ESRH_E39_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_ESRH_E39_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESRH_E39_SET   (0x00000001u)
+#define EDMA3_CCRL_ESRH_E38_MASK   (0x00000040u)
+#define EDMA3_CCRL_ESRH_E38_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_ESRH_E38_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESRH_E38_SET   (0x00000001u)
+#define EDMA3_CCRL_ESRH_E37_MASK   (0x00000020u)
+#define EDMA3_CCRL_ESRH_E37_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_ESRH_E37_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESRH_E37_SET   (0x00000001u)
+#define EDMA3_CCRL_ESRH_E36_MASK   (0x00000010u)
+#define EDMA3_CCRL_ESRH_E36_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_ESRH_E36_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESRH_E36_SET   (0x00000001u)
+#define EDMA3_CCRL_ESRH_E35_MASK   (0x00000008u)
+#define EDMA3_CCRL_ESRH_E35_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_ESRH_E35_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESRH_E35_SET   (0x00000001u)
+#define EDMA3_CCRL_ESRH_E34_MASK   (0x00000004u)
+#define EDMA3_CCRL_ESRH_E34_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_ESRH_E34_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESRH_E34_SET   (0x00000001u)
+#define EDMA3_CCRL_ESRH_E33_MASK   (0x00000002u)
+#define EDMA3_CCRL_ESRH_E33_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_ESRH_E33_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESRH_E33_SET   (0x00000001u)
+#define EDMA3_CCRL_ESRH_E32_MASK   (0x00000001u)
+#define EDMA3_CCRL_ESRH_E32_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_ESRH_E32_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESRH_E32_SET   (0x00000001u)
+#define EDMA3_CCRL_ESRH_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CER_E31_MASK   (0x80000000u)
+#define EDMA3_CCRL_CER_E31_SHIFT   (0x0000001Fu)
+#define EDMA3_CCRL_CER_E31_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CER_E30_MASK   (0x40000000u)
+#define EDMA3_CCRL_CER_E30_SHIFT   (0x0000001Eu)
+#define EDMA3_CCRL_CER_E30_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CER_E29_MASK   (0x20000000u)
+#define EDMA3_CCRL_CER_E29_SHIFT   (0x0000001Du)
+#define EDMA3_CCRL_CER_E29_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CER_E28_MASK   (0x10000000u)
+#define EDMA3_CCRL_CER_E28_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_CER_E28_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CER_E27_MASK   (0x08000000u)
+#define EDMA3_CCRL_CER_E27_SHIFT   (0x0000001Bu)
+#define EDMA3_CCRL_CER_E27_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CER_E26_MASK   (0x04000000u)
+#define EDMA3_CCRL_CER_E26_SHIFT   (0x0000001Au)
+#define EDMA3_CCRL_CER_E26_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CER_E25_MASK   (0x02000000u)
+#define EDMA3_CCRL_CER_E25_SHIFT   (0x00000019u)
+#define EDMA3_CCRL_CER_E25_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CER_E24_MASK   (0x01000000u)
+#define EDMA3_CCRL_CER_E24_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_CER_E24_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CER_E23_MASK   (0x00800000u)
+#define EDMA3_CCRL_CER_E23_SHIFT   (0x00000017u)
+#define EDMA3_CCRL_CER_E23_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CER_E22_MASK   (0x00400000u)
+#define EDMA3_CCRL_CER_E22_SHIFT   (0x00000016u)
+#define EDMA3_CCRL_CER_E22_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CER_E21_MASK   (0x00200000u)
+#define EDMA3_CCRL_CER_E21_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_CER_E21_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CER_E20_MASK   (0x00100000u)
+#define EDMA3_CCRL_CER_E20_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_CER_E20_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CER_E19_MASK   (0x00080000u)
+#define EDMA3_CCRL_CER_E19_SHIFT   (0x00000013u)
+#define EDMA3_CCRL_CER_E19_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CER_E18_MASK   (0x00040000u)
+#define EDMA3_CCRL_CER_E18_SHIFT   (0x00000012u)
+#define EDMA3_CCRL_CER_E18_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CER_E17_MASK   (0x00020000u)
+#define EDMA3_CCRL_CER_E17_SHIFT   (0x00000011u)
+#define EDMA3_CCRL_CER_E17_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CER_E16_MASK   (0x00010000u)
+#define EDMA3_CCRL_CER_E16_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_CER_E16_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CER_E15_MASK   (0x00008000u)
+#define EDMA3_CCRL_CER_E15_SHIFT   (0x0000000Fu)
+#define EDMA3_CCRL_CER_E15_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CER_E14_MASK   (0x00004000u)
+#define EDMA3_CCRL_CER_E14_SHIFT   (0x0000000Eu)
+#define EDMA3_CCRL_CER_E14_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CER_E13_MASK   (0x00002000u)
+#define EDMA3_CCRL_CER_E13_SHIFT   (0x0000000Du)
+#define EDMA3_CCRL_CER_E13_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CER_E12_MASK   (0x00001000u)
+#define EDMA3_CCRL_CER_E12_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_CER_E12_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CER_E11_MASK   (0x00000800u)
+#define EDMA3_CCRL_CER_E11_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_CER_E11_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CER_E10_MASK   (0x00000400u)
+#define EDMA3_CCRL_CER_E10_SHIFT   (0x0000000Au)
+#define EDMA3_CCRL_CER_E10_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CER_E9_MASK   (0x00000200u)
+#define EDMA3_CCRL_CER_E9_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_CER_E9_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CER_E8_MASK   (0x00000100u)
+#define EDMA3_CCRL_CER_E8_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_CER_E8_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CER_E7_MASK   (0x00000080u)
+#define EDMA3_CCRL_CER_E7_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_CER_E7_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CER_E6_MASK   (0x00000040u)
+#define EDMA3_CCRL_CER_E6_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_CER_E6_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CER_E5_MASK   (0x00000020u)
+#define EDMA3_CCRL_CER_E5_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_CER_E5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CER_E4_MASK   (0x00000010u)
+#define EDMA3_CCRL_CER_E4_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_CER_E4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CER_E3_MASK   (0x00000008u)
+#define EDMA3_CCRL_CER_E3_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_CER_E3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CER_E2_MASK   (0x00000004u)
+#define EDMA3_CCRL_CER_E2_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_CER_E2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CER_E1_MASK   (0x00000002u)
+#define EDMA3_CCRL_CER_E1_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_CER_E1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CER_E0_MASK   (0x00000001u)
+#define EDMA3_CCRL_CER_E0_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_CER_E0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CER_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CERH_E63_MASK   (0x80000000u)
+#define EDMA3_CCRL_CERH_E63_SHIFT   (0x0000001Fu)
+#define EDMA3_CCRL_CERH_E63_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CERH_E62_MASK   (0x40000000u)
+#define EDMA3_CCRL_CERH_E62_SHIFT   (0x0000001Eu)
+#define EDMA3_CCRL_CERH_E62_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CERH_E61_MASK   (0x20000000u)
+#define EDMA3_CCRL_CERH_E61_SHIFT   (0x0000001Du)
+#define EDMA3_CCRL_CERH_E61_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CERH_E60_MASK   (0x10000000u)
+#define EDMA3_CCRL_CERH_E60_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_CERH_E60_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CERH_E59_MASK   (0x08000000u)
+#define EDMA3_CCRL_CERH_E59_SHIFT   (0x0000001Bu)
+#define EDMA3_CCRL_CERH_E59_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CERH_E58_MASK   (0x04000000u)
+#define EDMA3_CCRL_CERH_E58_SHIFT   (0x0000001Au)
+#define EDMA3_CCRL_CERH_E58_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CERH_E57_MASK   (0x02000000u)
+#define EDMA3_CCRL_CERH_E57_SHIFT   (0x00000019u)
+#define EDMA3_CCRL_CERH_E57_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CERH_E56_MASK   (0x01000000u)
+#define EDMA3_CCRL_CERH_E56_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_CERH_E56_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CERH_E55_MASK   (0x00800000u)
+#define EDMA3_CCRL_CERH_E55_SHIFT   (0x00000017u)
+#define EDMA3_CCRL_CERH_E55_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CERH_E54_MASK   (0x00400000u)
+#define EDMA3_CCRL_CERH_E54_SHIFT   (0x00000016u)
+#define EDMA3_CCRL_CERH_E54_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CERH_E53_MASK   (0x00200000u)
+#define EDMA3_CCRL_CERH_E53_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_CERH_E53_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CERH_E52_MASK   (0x00100000u)
+#define EDMA3_CCRL_CERH_E52_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_CERH_E52_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CERH_E51_MASK   (0x00080000u)
+#define EDMA3_CCRL_CERH_E51_SHIFT   (0x00000013u)
+#define EDMA3_CCRL_CERH_E51_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CERH_E50_MASK   (0x00040000u)
+#define EDMA3_CCRL_CERH_E50_SHIFT   (0x00000012u)
+#define EDMA3_CCRL_CERH_E50_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CERH_E49_MASK   (0x00020000u)
+#define EDMA3_CCRL_CERH_E49_SHIFT   (0x00000011u)
+#define EDMA3_CCRL_CERH_E49_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CERH_E48_MASK   (0x00010000u)
+#define EDMA3_CCRL_CERH_E48_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_CERH_E48_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CERH_E47_MASK   (0x00008000u)
+#define EDMA3_CCRL_CERH_E47_SHIFT   (0x0000000Fu)
+#define EDMA3_CCRL_CERH_E47_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CERH_E46_MASK   (0x00004000u)
+#define EDMA3_CCRL_CERH_E46_SHIFT   (0x0000000Eu)
+#define EDMA3_CCRL_CERH_E46_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CERH_E45_MASK   (0x00002000u)
+#define EDMA3_CCRL_CERH_E45_SHIFT   (0x0000000Du)
+#define EDMA3_CCRL_CERH_E45_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CERH_E44_MASK   (0x00001000u)
+#define EDMA3_CCRL_CERH_E44_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_CERH_E44_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CERH_E43_MASK   (0x00000800u)
+#define EDMA3_CCRL_CERH_E43_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_CERH_E43_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CERH_E42_MASK   (0x00000400u)
+#define EDMA3_CCRL_CERH_E42_SHIFT   (0x0000000Au)
+#define EDMA3_CCRL_CERH_E42_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CERH_E41_MASK   (0x00000200u)
+#define EDMA3_CCRL_CERH_E41_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_CERH_E41_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CERH_E40_MASK   (0x00000100u)
+#define EDMA3_CCRL_CERH_E40_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_CERH_E40_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CERH_E39_MASK   (0x00000080u)
+#define EDMA3_CCRL_CERH_E39_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_CERH_E39_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CERH_E38_MASK   (0x00000040u)
+#define EDMA3_CCRL_CERH_E38_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_CERH_E38_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CERH_E37_MASK   (0x00000020u)
+#define EDMA3_CCRL_CERH_E37_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_CERH_E37_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CERH_E36_MASK   (0x00000010u)
+#define EDMA3_CCRL_CERH_E36_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_CERH_E36_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CERH_E35_MASK   (0x00000008u)
+#define EDMA3_CCRL_CERH_E35_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_CERH_E35_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CERH_E34_MASK   (0x00000004u)
+#define EDMA3_CCRL_CERH_E34_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_CERH_E34_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CERH_E33_MASK   (0x00000002u)
+#define EDMA3_CCRL_CERH_E33_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_CERH_E33_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CERH_E32_MASK   (0x00000001u)
+#define EDMA3_CCRL_CERH_E32_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_CERH_E32_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CERH_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EER_E31_MASK   (0x80000000u)
+#define EDMA3_CCRL_EER_E31_SHIFT   (0x0000001Fu)
+#define EDMA3_CCRL_EER_E31_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EER_E31_   (0x00000001u)
+#define EDMA3_CCRL_EER_E30_MASK   (0x40000000u)
+#define EDMA3_CCRL_EER_E30_SHIFT   (0x0000001Eu)
+#define EDMA3_CCRL_EER_E30_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EER_E29_MASK   (0x20000000u)
+#define EDMA3_CCRL_EER_E29_SHIFT   (0x0000001Du)
+#define EDMA3_CCRL_EER_E29_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EER_E28_MASK   (0x10000000u)
+#define EDMA3_CCRL_EER_E28_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_EER_E28_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EER_E27_MASK   (0x08000000u)
+#define EDMA3_CCRL_EER_E27_SHIFT   (0x0000001Bu)
+#define EDMA3_CCRL_EER_E27_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EER_E26_MASK   (0x04000000u)
+#define EDMA3_CCRL_EER_E26_SHIFT   (0x0000001Au)
+#define EDMA3_CCRL_EER_E26_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EER_E25_MASK   (0x02000000u)
+#define EDMA3_CCRL_EER_E25_SHIFT   (0x00000019u)
+#define EDMA3_CCRL_EER_E25_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EER_E24_MASK   (0x01000000u)
+#define EDMA3_CCRL_EER_E24_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_EER_E24_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EER_E23_MASK   (0x00800000u)
+#define EDMA3_CCRL_EER_E23_SHIFT   (0x00000017u)
+#define EDMA3_CCRL_EER_E23_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EER_E22_MASK   (0x00400000u)
+#define EDMA3_CCRL_EER_E22_SHIFT   (0x00000016u)
+#define EDMA3_CCRL_EER_E22_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EER_E21_MASK   (0x00200000u)
+#define EDMA3_CCRL_EER_E21_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_EER_E21_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EER_E20_MASK   (0x00100000u)
+#define EDMA3_CCRL_EER_E20_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_EER_E20_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EER_E19_MASK   (0x00080000u)
+#define EDMA3_CCRL_EER_E19_SHIFT   (0x00000013u)
+#define EDMA3_CCRL_EER_E19_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EER_E18_MASK   (0x00040000u)
+#define EDMA3_CCRL_EER_E18_SHIFT   (0x00000012u)
+#define EDMA3_CCRL_EER_E18_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EER_E17_MASK   (0x00020000u)
+#define EDMA3_CCRL_EER_E17_SHIFT   (0x00000011u)
+#define EDMA3_CCRL_EER_E17_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EER_E16_MASK   (0x00010000u)
+#define EDMA3_CCRL_EER_E16_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_EER_E16_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EER_E15_MASK   (0x00008000u)
+#define EDMA3_CCRL_EER_E15_SHIFT   (0x0000000Fu)
+#define EDMA3_CCRL_EER_E15_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EER_E14_MASK   (0x00004000u)
+#define EDMA3_CCRL_EER_E14_SHIFT   (0x0000000Eu)
+#define EDMA3_CCRL_EER_E14_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EER_E13_MASK   (0x00002000u)
+#define EDMA3_CCRL_EER_E13_SHIFT   (0x0000000Du)
+#define EDMA3_CCRL_EER_E13_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EER_E12_MASK   (0x00001000u)
+#define EDMA3_CCRL_EER_E12_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_EER_E12_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EER_E11_MASK   (0x00000800u)
+#define EDMA3_CCRL_EER_E11_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_EER_E11_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EER_E10_MASK   (0x00000400u)
+#define EDMA3_CCRL_EER_E10_SHIFT   (0x0000000Au)
+#define EDMA3_CCRL_EER_E10_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EER_E9_MASK   (0x00000200u)
+#define EDMA3_CCRL_EER_E9_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_EER_E9_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EER_E8_MASK   (0x00000100u)
+#define EDMA3_CCRL_EER_E8_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_EER_E8_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EER_E7_MASK   (0x00000080u)
+#define EDMA3_CCRL_EER_E7_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_EER_E7_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EER_E6_MASK   (0x00000040u)
+#define EDMA3_CCRL_EER_E6_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_EER_E6_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EER_E5_MASK   (0x00000020u)
+#define EDMA3_CCRL_EER_E5_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_EER_E5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EER_E4_MASK   (0x00000010u)
+#define EDMA3_CCRL_EER_E4_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_EER_E4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EER_E3_MASK   (0x00000008u)
+#define EDMA3_CCRL_EER_E3_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_EER_E3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EER_E2_MASK   (0x00000004u)
+#define EDMA3_CCRL_EER_E2_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_EER_E2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EER_E1_MASK   (0x00000002u)
+#define EDMA3_CCRL_EER_E1_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_EER_E1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EER_E0_MASK   (0x00000001u)
+#define EDMA3_CCRL_EER_E0_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_EER_E0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EER_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EERH_E63_MASK   (0x80000000u)
+#define EDMA3_CCRL_EERH_E63_SHIFT   (0x0000001Fu)
+#define EDMA3_CCRL_EERH_E63_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EERH_E62_MASK   (0x40000000u)
+#define EDMA3_CCRL_EERH_E62_SHIFT   (0x0000001Eu)
+#define EDMA3_CCRL_EERH_E62_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EERH_E61_MASK   (0x20000000u)
+#define EDMA3_CCRL_EERH_E61_SHIFT   (0x0000001Du)
+#define EDMA3_CCRL_EERH_E61_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EERH_E60_MASK   (0x10000000u)
+#define EDMA3_CCRL_EERH_E60_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_EERH_E60_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EERH_E59_MASK   (0x08000000u)
+#define EDMA3_CCRL_EERH_E59_SHIFT   (0x0000001Bu)
+#define EDMA3_CCRL_EERH_E59_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EERH_E58_MASK   (0x04000000u)
+#define EDMA3_CCRL_EERH_E58_SHIFT   (0x0000001Au)
+#define EDMA3_CCRL_EERH_E58_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EERH_E57_MASK   (0x02000000u)
+#define EDMA3_CCRL_EERH_E57_SHIFT   (0x00000019u)
+#define EDMA3_CCRL_EERH_E57_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EERH_E56_MASK   (0x01000000u)
+#define EDMA3_CCRL_EERH_E56_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_EERH_E56_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EERH_E55_MASK   (0x00800000u)
+#define EDMA3_CCRL_EERH_E55_SHIFT   (0x00000017u)
+#define EDMA3_CCRL_EERH_E55_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EERH_E54_MASK   (0x00400000u)
+#define EDMA3_CCRL_EERH_E54_SHIFT   (0x00000016u)
+#define EDMA3_CCRL_EERH_E54_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EERH_E53_MASK   (0x00200000u)
+#define EDMA3_CCRL_EERH_E53_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_EERH_E53_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EERH_E52_MASK   (0x00100000u)
+#define EDMA3_CCRL_EERH_E52_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_EERH_E52_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EERH_E51_MASK   (0x00080000u)
+#define EDMA3_CCRL_EERH_E51_SHIFT   (0x00000013u)
+#define EDMA3_CCRL_EERH_E51_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EERH_E50_MASK   (0x00040000u)
+#define EDMA3_CCRL_EERH_E50_SHIFT   (0x00000012u)
+#define EDMA3_CCRL_EERH_E50_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EERH_E49_MASK   (0x00020000u)
+#define EDMA3_CCRL_EERH_E49_SHIFT   (0x00000011u)
+#define EDMA3_CCRL_EERH_E49_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EERH_E48_MASK   (0x00010000u)
+#define EDMA3_CCRL_EERH_E48_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_EERH_E48_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EERH_E47_MASK   (0x00008000u)
+#define EDMA3_CCRL_EERH_E47_SHIFT   (0x0000000Fu)
+#define EDMA3_CCRL_EERH_E47_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EERH_E46_MASK   (0x00004000u)
+#define EDMA3_CCRL_EERH_E46_SHIFT   (0x0000000Eu)
+#define EDMA3_CCRL_EERH_E46_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EERH_E45_MASK   (0x00002000u)
+#define EDMA3_CCRL_EERH_E45_SHIFT   (0x0000000Du)
+#define EDMA3_CCRL_EERH_E45_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EERH_E44_MASK   (0x00001000u)
+#define EDMA3_CCRL_EERH_E44_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_EERH_E44_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EERH_E43_MASK   (0x00000800u)
+#define EDMA3_CCRL_EERH_E43_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_EERH_E43_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EERH_E42_MASK   (0x00000400u)
+#define EDMA3_CCRL_EERH_E42_SHIFT   (0x0000000Au)
+#define EDMA3_CCRL_EERH_E42_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EERH_E41_MASK   (0x00000200u)
+#define EDMA3_CCRL_EERH_E41_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_EERH_E41_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EERH_E40_MASK   (0x00000100u)
+#define EDMA3_CCRL_EERH_E40_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_EERH_E40_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EERH_E39_MASK   (0x00000080u)
+#define EDMA3_CCRL_EERH_E39_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_EERH_E39_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EERH_E38_MASK   (0x00000040u)
+#define EDMA3_CCRL_EERH_E38_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_EERH_E38_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EERH_E37_MASK   (0x00000020u)
+#define EDMA3_CCRL_EERH_E37_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_EERH_E37_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EERH_E36_MASK   (0x00000010u)
+#define EDMA3_CCRL_EERH_E36_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_EERH_E36_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EERH_E35_MASK   (0x00000008u)
+#define EDMA3_CCRL_EERH_E35_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_EERH_E35_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EERH_E34_MASK   (0x00000004u)
+#define EDMA3_CCRL_EERH_E34_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_EERH_E34_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EERH_E33_MASK   (0x00000002u)
+#define EDMA3_CCRL_EERH_E33_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_EERH_E33_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EERH_E32_MASK   (0x00000001u)
+#define EDMA3_CCRL_EERH_E32_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_EERH_E32_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EERH_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECR_E31_MASK   (0x80000000u)
+#define EDMA3_CCRL_EECR_E31_SHIFT   (0x0000001Fu)
+#define EDMA3_CCRL_EECR_E31_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECR_E31_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECR_E30_MASK   (0x40000000u)
+#define EDMA3_CCRL_EECR_E30_SHIFT   (0x0000001Eu)
+#define EDMA3_CCRL_EECR_E30_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECR_E30_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECR_E29_MASK   (0x20000000u)
+#define EDMA3_CCRL_EECR_E29_SHIFT   (0x0000001Du)
+#define EDMA3_CCRL_EECR_E29_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECR_E29_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECR_E28_MASK   (0x10000000u)
+#define EDMA3_CCRL_EECR_E28_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_EECR_E28_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECR_E28_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECR_E27_MASK   (0x08000000u)
+#define EDMA3_CCRL_EECR_E27_SHIFT   (0x0000001Bu)
+#define EDMA3_CCRL_EECR_E27_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECR_E27_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECR_E26_MASK   (0x04000000u)
+#define EDMA3_CCRL_EECR_E26_SHIFT   (0x0000001Au)
+#define EDMA3_CCRL_EECR_E26_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECR_E26_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECR_E25_MASK   (0x02000000u)
+#define EDMA3_CCRL_EECR_E25_SHIFT   (0x00000019u)
+#define EDMA3_CCRL_EECR_E25_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECR_E25_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECR_E24_MASK   (0x01000000u)
+#define EDMA3_CCRL_EECR_E24_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_EECR_E24_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECR_E24_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECR_E23_MASK   (0x00800000u)
+#define EDMA3_CCRL_EECR_E23_SHIFT   (0x00000017u)
+#define EDMA3_CCRL_EECR_E23_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECR_E23_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECR_E22_MASK   (0x00400000u)
+#define EDMA3_CCRL_EECR_E22_SHIFT   (0x00000016u)
+#define EDMA3_CCRL_EECR_E22_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECR_E22_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECR_E21_MASK   (0x00200000u)
+#define EDMA3_CCRL_EECR_E21_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_EECR_E21_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECR_E21_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECR_E20_MASK   (0x00100000u)
+#define EDMA3_CCRL_EECR_E20_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_EECR_E20_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECR_E20_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECR_E19_MASK   (0x00080000u)
+#define EDMA3_CCRL_EECR_E19_SHIFT   (0x00000013u)
+#define EDMA3_CCRL_EECR_E19_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECR_E19_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECR_E18_MASK   (0x00040000u)
+#define EDMA3_CCRL_EECR_E18_SHIFT   (0x00000012u)
+#define EDMA3_CCRL_EECR_E18_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECR_E18_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECR_E17_MASK   (0x00020000u)
+#define EDMA3_CCRL_EECR_E17_SHIFT   (0x00000011u)
+#define EDMA3_CCRL_EECR_E17_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECR_E17_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECR_E16_MASK   (0x00010000u)
+#define EDMA3_CCRL_EECR_E16_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_EECR_E16_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECR_E16_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECR_E15_MASK   (0x00008000u)
+#define EDMA3_CCRL_EECR_E15_SHIFT   (0x0000000Fu)
+#define EDMA3_CCRL_EECR_E15_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECR_E15_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECR_E14_MASK   (0x00004000u)
+#define EDMA3_CCRL_EECR_E14_SHIFT   (0x0000000Eu)
+#define EDMA3_CCRL_EECR_E14_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECR_E14_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECR_E13_MASK   (0x00002000u)
+#define EDMA3_CCRL_EECR_E13_SHIFT   (0x0000000Du)
+#define EDMA3_CCRL_EECR_E13_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECR_E13_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECR_E12_MASK   (0x00001000u)
+#define EDMA3_CCRL_EECR_E12_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_EECR_E12_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECR_E12_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECR_E11_MASK   (0x00000800u)
+#define EDMA3_CCRL_EECR_E11_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_EECR_E11_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECR_E11_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECR_E10_MASK   (0x00000400u)
+#define EDMA3_CCRL_EECR_E10_SHIFT   (0x0000000Au)
+#define EDMA3_CCRL_EECR_E10_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECR_E10_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECR_E9_MASK   (0x00000200u)
+#define EDMA3_CCRL_EECR_E9_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_EECR_E9_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECR_E9_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECR_E8_MASK   (0x00000100u)
+#define EDMA3_CCRL_EECR_E8_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_EECR_E8_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECR_E8_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECR_E7_MASK   (0x00000080u)
+#define EDMA3_CCRL_EECR_E7_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_EECR_E7_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECR_E7_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECR_E6_MASK   (0x00000040u)
+#define EDMA3_CCRL_EECR_E6_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_EECR_E6_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECR_E6_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECR_E5_MASK   (0x00000020u)
+#define EDMA3_CCRL_EECR_E5_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_EECR_E5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECR_E5_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECR_E4_MASK   (0x00000010u)
+#define EDMA3_CCRL_EECR_E4_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_EECR_E4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECR_E4_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECR_E3_MASK   (0x00000008u)
+#define EDMA3_CCRL_EECR_E3_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_EECR_E3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECR_E3_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECR_E2_MASK   (0x00000004u)
+#define EDMA3_CCRL_EECR_E2_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_EECR_E2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECR_E2_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECR_E1_MASK   (0x00000002u)
+#define EDMA3_CCRL_EECR_E1_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_EECR_E1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECR_E1_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECR_E0_MASK   (0x00000001u)
+#define EDMA3_CCRL_EECR_E0_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_EECR_E0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECR_E0_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECRH_E63_MASK   (0x80000000u)
+#define EDMA3_CCRL_EECRH_E63_SHIFT   (0x0000001Fu)
+#define EDMA3_CCRL_EECRH_E63_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECRH_E63_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECRH_E62_MASK   (0x40000000u)
+#define EDMA3_CCRL_EECRH_E62_SHIFT   (0x0000001Eu)
+#define EDMA3_CCRL_EECRH_E62_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECRH_E62_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECRH_E61_MASK   (0x20000000u)
+#define EDMA3_CCRL_EECRH_E61_SHIFT   (0x0000001Du)
+#define EDMA3_CCRL_EECRH_E61_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECRH_E61_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECRH_E60_MASK   (0x10000000u)
+#define EDMA3_CCRL_EECRH_E60_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_EECRH_E60_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECRH_E60_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECRH_E59_MASK   (0x08000000u)
+#define EDMA3_CCRL_EECRH_E59_SHIFT   (0x0000001Bu)
+#define EDMA3_CCRL_EECRH_E59_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECRH_E59_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECRH_E58_MASK   (0x04000000u)
+#define EDMA3_CCRL_EECRH_E58_SHIFT   (0x0000001Au)
+#define EDMA3_CCRL_EECRH_E58_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECRH_E58_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECRH_E57_MASK   (0x02000000u)
+#define EDMA3_CCRL_EECRH_E57_SHIFT   (0x00000019u)
+#define EDMA3_CCRL_EECRH_E57_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECRH_E57_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECRH_E56_MASK   (0x01000000u)
+#define EDMA3_CCRL_EECRH_E56_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_EECRH_E56_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECRH_E56_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECRH_E55_MASK   (0x00800000u)
+#define EDMA3_CCRL_EECRH_E55_SHIFT   (0x00000017u)
+#define EDMA3_CCRL_EECRH_E55_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECRH_E55_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECRH_E54_MASK   (0x00400000u)
+#define EDMA3_CCRL_EECRH_E54_SHIFT   (0x00000016u)
+#define EDMA3_CCRL_EECRH_E54_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECRH_E54_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECRH_E53_MASK   (0x00200000u)
+#define EDMA3_CCRL_EECRH_E53_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_EECRH_E53_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECRH_E53_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECRH_E52_MASK   (0x00100000u)
+#define EDMA3_CCRL_EECRH_E52_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_EECRH_E52_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECRH_E52_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECRH_E51_MASK   (0x00080000u)
+#define EDMA3_CCRL_EECRH_E51_SHIFT   (0x00000013u)
+#define EDMA3_CCRL_EECRH_E51_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECRH_E51_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECRH_E50_MASK   (0x00040000u)
+#define EDMA3_CCRL_EECRH_E50_SHIFT   (0x00000012u)
+#define EDMA3_CCRL_EECRH_E50_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECRH_E50_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECRH_E49_MASK   (0x00020000u)
+#define EDMA3_CCRL_EECRH_E49_SHIFT   (0x00000011u)
+#define EDMA3_CCRL_EECRH_E49_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECRH_E49_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECRH_E48_MASK   (0x00010000u)
+#define EDMA3_CCRL_EECRH_E48_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_EECRH_E48_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECRH_E48_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECRH_E47_MASK   (0x00008000u)
+#define EDMA3_CCRL_EECRH_E47_SHIFT   (0x0000000Fu)
+#define EDMA3_CCRL_EECRH_E47_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECRH_E47_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECRH_E46_MASK   (0x00004000u)
+#define EDMA3_CCRL_EECRH_E46_SHIFT   (0x0000000Eu)
+#define EDMA3_CCRL_EECRH_E46_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECRH_E46_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECRH_E45_MASK   (0x00002000u)
+#define EDMA3_CCRL_EECRH_E45_SHIFT   (0x0000000Du)
+#define EDMA3_CCRL_EECRH_E45_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECRH_E45_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECRH_E44_MASK   (0x00001000u)
+#define EDMA3_CCRL_EECRH_E44_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_EECRH_E44_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECRH_E44_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECRH_E43_MASK   (0x00000800u)
+#define EDMA3_CCRL_EECRH_E43_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_EECRH_E43_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECRH_E43_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECRH_E42_MASK   (0x00000400u)
+#define EDMA3_CCRL_EECRH_E42_SHIFT   (0x0000000Au)
+#define EDMA3_CCRL_EECRH_E42_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECRH_E42_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECRH_E41_MASK   (0x00000200u)
+#define EDMA3_CCRL_EECRH_E41_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_EECRH_E41_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECRH_E41_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECRH_E40_MASK   (0x00000100u)
+#define EDMA3_CCRL_EECRH_E40_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_EECRH_E40_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECRH_E40_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECRH_E39_MASK   (0x00000080u)
+#define EDMA3_CCRL_EECRH_E39_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_EECRH_E39_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECRH_E39_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECRH_E38_MASK   (0x00000040u)
+#define EDMA3_CCRL_EECRH_E38_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_EECRH_E38_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECRH_E38_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECRH_E37_MASK   (0x00000020u)
+#define EDMA3_CCRL_EECRH_E37_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_EECRH_E37_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECRH_E37_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECRH_E36_MASK   (0x00000010u)
+#define EDMA3_CCRL_EECRH_E36_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_EECRH_E36_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECRH_E36_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECRH_E35_MASK   (0x00000008u)
+#define EDMA3_CCRL_EECRH_E35_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_EECRH_E35_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECRH_E35_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECRH_E34_MASK   (0x00000004u)
+#define EDMA3_CCRL_EECRH_E34_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_EECRH_E34_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECRH_E34_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECRH_E33_MASK   (0x00000002u)
+#define EDMA3_CCRL_EECRH_E33_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_EECRH_E33_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECRH_E33_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECRH_E32_MASK   (0x00000001u)
+#define EDMA3_CCRL_EECRH_E32_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_EECRH_E32_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECRH_E32_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_EECRH_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESR_E31_MASK   (0x80000000u)
+#define EDMA3_CCRL_EESR_E31_SHIFT   (0x0000001Fu)
+#define EDMA3_CCRL_EESR_E31_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESR_E31_SET   (0x00000001u)
+#define EDMA3_CCRL_EESR_E30_MASK   (0x40000000u)
+#define EDMA3_CCRL_EESR_E30_SHIFT   (0x0000001Eu)
+#define EDMA3_CCRL_EESR_E30_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESR_E30_SET   (0x00000001u)
+#define EDMA3_CCRL_EESR_E29_MASK   (0x20000000u)
+#define EDMA3_CCRL_EESR_E29_SHIFT   (0x0000001Du)
+#define EDMA3_CCRL_EESR_E29_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESR_E29_SET   (0x00000001u)
+#define EDMA3_CCRL_EESR_E28_MASK   (0x10000000u)
+#define EDMA3_CCRL_EESR_E28_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_EESR_E28_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESR_E28_SET   (0x00000001u)
+#define EDMA3_CCRL_EESR_E27_MASK   (0x08000000u)
+#define EDMA3_CCRL_EESR_E27_SHIFT   (0x0000001Bu)
+#define EDMA3_CCRL_EESR_E27_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESR_E27_SET   (0x00000001u)
+#define EDMA3_CCRL_EESR_E26_MASK   (0x04000000u)
+#define EDMA3_CCRL_EESR_E26_SHIFT   (0x0000001Au)
+#define EDMA3_CCRL_EESR_E26_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESR_E26_SET   (0x00000001u)
+#define EDMA3_CCRL_EESR_E25_MASK   (0x02000000u)
+#define EDMA3_CCRL_EESR_E25_SHIFT   (0x00000019u)
+#define EDMA3_CCRL_EESR_E25_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESR_E25_SET   (0x00000001u)
+#define EDMA3_CCRL_EESR_E24_MASK   (0x01000000u)
+#define EDMA3_CCRL_EESR_E24_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_EESR_E24_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESR_E24_SET   (0x00000001u)
+#define EDMA3_CCRL_EESR_E23_MASK   (0x00800000u)
+#define EDMA3_CCRL_EESR_E23_SHIFT   (0x00000017u)
+#define EDMA3_CCRL_EESR_E23_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESR_E23_SET   (0x00000001u)
+#define EDMA3_CCRL_EESR_E22_MASK   (0x00400000u)
+#define EDMA3_CCRL_EESR_E22_SHIFT   (0x00000016u)
+#define EDMA3_CCRL_EESR_E22_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESR_E22_SET   (0x00000001u)
+#define EDMA3_CCRL_EESR_E21_MASK   (0x00200000u)
+#define EDMA3_CCRL_EESR_E21_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_EESR_E21_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESR_E21_SET   (0x00000001u)
+#define EDMA3_CCRL_EESR_E20_MASK   (0x00100000u)
+#define EDMA3_CCRL_EESR_E20_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_EESR_E20_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESR_E20_SET   (0x00000001u)
+#define EDMA3_CCRL_EESR_E19_MASK   (0x00080000u)
+#define EDMA3_CCRL_EESR_E19_SHIFT   (0x00000013u)
+#define EDMA3_CCRL_EESR_E19_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESR_E19_SET   (0x00000001u)
+#define EDMA3_CCRL_EESR_E18_MASK   (0x00040000u)
+#define EDMA3_CCRL_EESR_E18_SHIFT   (0x00000012u)
+#define EDMA3_CCRL_EESR_E18_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESR_E18_SET   (0x00000001u)
+#define EDMA3_CCRL_EESR_E17_MASK   (0x00020000u)
+#define EDMA3_CCRL_EESR_E17_SHIFT   (0x00000011u)
+#define EDMA3_CCRL_EESR_E17_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESR_E17_SET   (0x00000001u)
+#define EDMA3_CCRL_EESR_E16_MASK   (0x00010000u)
+#define EDMA3_CCRL_EESR_E16_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_EESR_E16_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESR_E16_SET   (0x00000001u)
+#define EDMA3_CCRL_EESR_E15_MASK   (0x00008000u)
+#define EDMA3_CCRL_EESR_E15_SHIFT   (0x0000000Fu)
+#define EDMA3_CCRL_EESR_E15_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESR_E15_SET   (0x00000001u)
+#define EDMA3_CCRL_EESR_E14_MASK   (0x00004000u)
+#define EDMA3_CCRL_EESR_E14_SHIFT   (0x0000000Eu)
+#define EDMA3_CCRL_EESR_E14_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESR_E14_SET   (0x00000001u)
+#define EDMA3_CCRL_EESR_E13_MASK   (0x00002000u)
+#define EDMA3_CCRL_EESR_E13_SHIFT   (0x0000000Du)
+#define EDMA3_CCRL_EESR_E13_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESR_E13_SET   (0x00000001u)
+#define EDMA3_CCRL_EESR_E12_MASK   (0x00001000u)
+#define EDMA3_CCRL_EESR_E12_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_EESR_E12_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESR_E12_SET   (0x00000001u)
+#define EDMA3_CCRL_EESR_E11_MASK   (0x00000800u)
+#define EDMA3_CCRL_EESR_E11_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_EESR_E11_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESR_E11_SET   (0x00000001u)
+#define EDMA3_CCRL_EESR_E10_MASK   (0x00000400u)
+#define EDMA3_CCRL_EESR_E10_SHIFT   (0x0000000Au)
+#define EDMA3_CCRL_EESR_E10_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESR_E10_SET   (0x00000001u)
+#define EDMA3_CCRL_EESR_E9_MASK   (0x00000200u)
+#define EDMA3_CCRL_EESR_E9_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_EESR_E9_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESR_E9_SET   (0x00000001u)
+#define EDMA3_CCRL_EESR_E8_MASK   (0x00000100u)
+#define EDMA3_CCRL_EESR_E8_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_EESR_E8_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESR_E8_SET   (0x00000001u)
+#define EDMA3_CCRL_EESR_E7_MASK   (0x00000080u)
+#define EDMA3_CCRL_EESR_E7_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_EESR_E7_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESR_E7_SET   (0x00000001u)
+#define EDMA3_CCRL_EESR_E6_MASK   (0x00000040u)
+#define EDMA3_CCRL_EESR_E6_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_EESR_E6_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESR_E6_SET   (0x00000001u)
+#define EDMA3_CCRL_EESR_E5_MASK   (0x00000020u)
+#define EDMA3_CCRL_EESR_E5_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_EESR_E5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESR_E5_SET   (0x00000001u)
+#define EDMA3_CCRL_EESR_E4_MASK   (0x00000010u)
+#define EDMA3_CCRL_EESR_E4_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_EESR_E4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESR_E4_SET   (0x00000001u)
+#define EDMA3_CCRL_EESR_E3_MASK   (0x00000008u)
+#define EDMA3_CCRL_EESR_E3_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_EESR_E3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESR_E3_SET   (0x00000001u)
+#define EDMA3_CCRL_EESR_E2_MASK   (0x00000004u)
+#define EDMA3_CCRL_EESR_E2_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_EESR_E2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESR_E2_SET   (0x00000001u)
+#define EDMA3_CCRL_EESR_E1_MASK   (0x00000002u)
+#define EDMA3_CCRL_EESR_E1_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_EESR_E1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESR_E1_SET   (0x00000001u)
+#define EDMA3_CCRL_EESR_E0_MASK   (0x00000001u)
+#define EDMA3_CCRL_EESR_E0_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_EESR_E0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESR_E0_SET   (0x00000001u)
+#define EDMA3_CCRL_EESR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESRH_E63_MASK   (0x80000000u)
+#define EDMA3_CCRL_EESRH_E63_SHIFT   (0x0000001Fu)
+#define EDMA3_CCRL_EESRH_E63_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESRH_E63_SET   (0x00000001u)
+#define EDMA3_CCRL_EESRH_E62_MASK   (0x40000000u)
+#define EDMA3_CCRL_EESRH_E62_SHIFT   (0x0000001Eu)
+#define EDMA3_CCRL_EESRH_E62_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESRH_E62_SET   (0x00000001u)
+#define EDMA3_CCRL_EESRH_E61_MASK   (0x20000000u)
+#define EDMA3_CCRL_EESRH_E61_SHIFT   (0x0000001Du)
+#define EDMA3_CCRL_EESRH_E61_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESRH_E61_SET   (0x00000001u)
+#define EDMA3_CCRL_EESRH_E60_MASK   (0x10000000u)
+#define EDMA3_CCRL_EESRH_E60_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_EESRH_E60_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESRH_E60_SET   (0x00000001u)
+#define EDMA3_CCRL_EESRH_E59_MASK   (0x08000000u)
+#define EDMA3_CCRL_EESRH_E59_SHIFT   (0x0000001Bu)
+#define EDMA3_CCRL_EESRH_E59_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESRH_E59_SET   (0x00000001u)
+#define EDMA3_CCRL_EESRH_E58_MASK   (0x04000000u)
+#define EDMA3_CCRL_EESRH_E58_SHIFT   (0x0000001Au)
+#define EDMA3_CCRL_EESRH_E58_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESRH_E58_SET   (0x00000001u)
+#define EDMA3_CCRL_EESRH_E57_MASK   (0x02000000u)
+#define EDMA3_CCRL_EESRH_E57_SHIFT   (0x00000019u)
+#define EDMA3_CCRL_EESRH_E57_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESRH_E57_SET   (0x00000001u)
+#define EDMA3_CCRL_EESRH_E56_MASK   (0x01000000u)
+#define EDMA3_CCRL_EESRH_E56_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_EESRH_E56_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESRH_E56_SET   (0x00000001u)
+#define EDMA3_CCRL_EESRH_E55_MASK   (0x00800000u)
+#define EDMA3_CCRL_EESRH_E55_SHIFT   (0x00000017u)
+#define EDMA3_CCRL_EESRH_E55_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESRH_E55_SET   (0x00000001u)
+#define EDMA3_CCRL_EESRH_E54_MASK   (0x00400000u)
+#define EDMA3_CCRL_EESRH_E54_SHIFT   (0x00000016u)
+#define EDMA3_CCRL_EESRH_E54_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESRH_E54_SET   (0x00000001u)
+#define EDMA3_CCRL_EESRH_E53_MASK   (0x00200000u)
+#define EDMA3_CCRL_EESRH_E53_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_EESRH_E53_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESRH_E53_SET   (0x00000001u)
+#define EDMA3_CCRL_EESRH_E52_MASK   (0x00100000u)
+#define EDMA3_CCRL_EESRH_E52_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_EESRH_E52_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESRH_E52_SET   (0x00000001u)
+#define EDMA3_CCRL_EESRH_E51_MASK   (0x00080000u)
+#define EDMA3_CCRL_EESRH_E51_SHIFT   (0x00000013u)
+#define EDMA3_CCRL_EESRH_E51_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESRH_E51_SET   (0x00000001u)
+#define EDMA3_CCRL_EESRH_E50_MASK   (0x00040000u)
+#define EDMA3_CCRL_EESRH_E50_SHIFT   (0x00000012u)
+#define EDMA3_CCRL_EESRH_E50_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESRH_E50_SET   (0x00000001u)
+#define EDMA3_CCRL_EESRH_E49_MASK   (0x00020000u)
+#define EDMA3_CCRL_EESRH_E49_SHIFT   (0x00000011u)
+#define EDMA3_CCRL_EESRH_E49_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESRH_E49_SET   (0x00000001u)
+#define EDMA3_CCRL_EESRH_E48_MASK   (0x00010000u)
+#define EDMA3_CCRL_EESRH_E48_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_EESRH_E48_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESRH_E48_SET   (0x00000001u)
+#define EDMA3_CCRL_EESRH_E47_MASK   (0x00008000u)
+#define EDMA3_CCRL_EESRH_E47_SHIFT   (0x0000000Fu)
+#define EDMA3_CCRL_EESRH_E47_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESRH_E47_SET   (0x00000001u)
+#define EDMA3_CCRL_EESRH_E46_MASK   (0x00004000u)
+#define EDMA3_CCRL_EESRH_E46_SHIFT   (0x0000000Eu)
+#define EDMA3_CCRL_EESRH_E46_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESRH_E46_SET   (0x00000001u)
+#define EDMA3_CCRL_EESRH_E45_MASK   (0x00002000u)
+#define EDMA3_CCRL_EESRH_E45_SHIFT   (0x0000000Du)
+#define EDMA3_CCRL_EESRH_E45_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESRH_E45_SET   (0x00000001u)
+#define EDMA3_CCRL_EESRH_E44_MASK   (0x00001000u)
+#define EDMA3_CCRL_EESRH_E44_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_EESRH_E44_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESRH_E44_SET   (0x00000001u)
+#define EDMA3_CCRL_EESRH_E43_MASK   (0x00000800u)
+#define EDMA3_CCRL_EESRH_E43_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_EESRH_E43_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESRH_E43_SET   (0x00000001u)
+#define EDMA3_CCRL_EESRH_E42_MASK   (0x00000400u)
+#define EDMA3_CCRL_EESRH_E42_SHIFT   (0x0000000Au)
+#define EDMA3_CCRL_EESRH_E42_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESRH_E42_SET   (0x00000001u)
+#define EDMA3_CCRL_EESRH_E41_MASK   (0x00000200u)
+#define EDMA3_CCRL_EESRH_E41_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_EESRH_E41_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESRH_E41_SET   (0x00000001u)
+#define EDMA3_CCRL_EESRH_E40_MASK   (0x00000100u)
+#define EDMA3_CCRL_EESRH_E40_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_EESRH_E40_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESRH_E40_SET   (0x00000001u)
+#define EDMA3_CCRL_EESRH_E39_MASK   (0x00000080u)
+#define EDMA3_CCRL_EESRH_E39_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_EESRH_E39_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESRH_E39_SET   (0x00000001u)
+#define EDMA3_CCRL_EESRH_E38_MASK   (0x00000040u)
+#define EDMA3_CCRL_EESRH_E38_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_EESRH_E38_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESRH_E38_SET   (0x00000001u)
+#define EDMA3_CCRL_EESRH_E37_MASK   (0x00000020u)
+#define EDMA3_CCRL_EESRH_E37_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_EESRH_E37_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESRH_E37_SET   (0x00000001u)
+#define EDMA3_CCRL_EESRH_E36_MASK   (0x00000010u)
+#define EDMA3_CCRL_EESRH_E36_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_EESRH_E36_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESRH_E36_SET   (0x00000001u)
+#define EDMA3_CCRL_EESRH_E35_MASK   (0x00000008u)
+#define EDMA3_CCRL_EESRH_E35_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_EESRH_E35_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESRH_E35_SET   (0x00000001u)
+#define EDMA3_CCRL_EESRH_E34_MASK   (0x00000004u)
+#define EDMA3_CCRL_EESRH_E34_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_EESRH_E34_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESRH_E34_SET   (0x00000001u)
+#define EDMA3_CCRL_EESRH_E33_MASK   (0x00000002u)
+#define EDMA3_CCRL_EESRH_E33_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_EESRH_E33_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESRH_E33_SET   (0x00000001u)
+#define EDMA3_CCRL_EESRH_E32_MASK   (0x00000001u)
+#define EDMA3_CCRL_EESRH_E32_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_EESRH_E32_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESRH_E32_SET   (0x00000001u)
+#define EDMA3_CCRL_EESRH_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SER_E31_MASK   (0x80000000u)
+#define EDMA3_CCRL_SER_E31_SHIFT   (0x0000001Fu)
+#define EDMA3_CCRL_SER_E31_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SER_E30_MASK   (0x40000000u)
+#define EDMA3_CCRL_SER_E30_SHIFT   (0x0000001Eu)
+#define EDMA3_CCRL_SER_E30_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SER_E29_MASK   (0x20000000u)
+#define EDMA3_CCRL_SER_E29_SHIFT   (0x0000001Du)
+#define EDMA3_CCRL_SER_E29_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SER_E28_MASK   (0x10000000u)
+#define EDMA3_CCRL_SER_E28_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_SER_E28_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SER_E27_MASK   (0x08000000u)
+#define EDMA3_CCRL_SER_E27_SHIFT   (0x0000001Bu)
+#define EDMA3_CCRL_SER_E27_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SER_E26_MASK   (0x04000000u)
+#define EDMA3_CCRL_SER_E26_SHIFT   (0x0000001Au)
+#define EDMA3_CCRL_SER_E26_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SER_E25_MASK   (0x02000000u)
+#define EDMA3_CCRL_SER_E25_SHIFT   (0x00000019u)
+#define EDMA3_CCRL_SER_E25_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SER_E24_MASK   (0x01000000u)
+#define EDMA3_CCRL_SER_E24_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_SER_E24_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SER_E23_MASK   (0x00800000u)
+#define EDMA3_CCRL_SER_E23_SHIFT   (0x00000017u)
+#define EDMA3_CCRL_SER_E23_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SER_E22_MASK   (0x00400000u)
+#define EDMA3_CCRL_SER_E22_SHIFT   (0x00000016u)
+#define EDMA3_CCRL_SER_E22_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SER_E21_MASK   (0x00200000u)
+#define EDMA3_CCRL_SER_E21_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_SER_E21_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SER_E20_MASK   (0x00100000u)
+#define EDMA3_CCRL_SER_E20_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_SER_E20_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SER_E19_MASK   (0x00080000u)
+#define EDMA3_CCRL_SER_E19_SHIFT   (0x00000013u)
+#define EDMA3_CCRL_SER_E19_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SER_E18_MASK   (0x00040000u)
+#define EDMA3_CCRL_SER_E18_SHIFT   (0x00000012u)
+#define EDMA3_CCRL_SER_E18_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SER_E17_MASK   (0x00020000u)
+#define EDMA3_CCRL_SER_E17_SHIFT   (0x00000011u)
+#define EDMA3_CCRL_SER_E17_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SER_E16_MASK   (0x00010000u)
+#define EDMA3_CCRL_SER_E16_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_SER_E16_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SER_E15_MASK   (0x00008000u)
+#define EDMA3_CCRL_SER_E15_SHIFT   (0x0000000Fu)
+#define EDMA3_CCRL_SER_E15_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SER_E14_MASK   (0x00004000u)
+#define EDMA3_CCRL_SER_E14_SHIFT   (0x0000000Eu)
+#define EDMA3_CCRL_SER_E14_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SER_E13_MASK   (0x00002000u)
+#define EDMA3_CCRL_SER_E13_SHIFT   (0x0000000Du)
+#define EDMA3_CCRL_SER_E13_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SER_E12_MASK   (0x00001000u)
+#define EDMA3_CCRL_SER_E12_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_SER_E12_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SER_E11_MASK   (0x00000800u)
+#define EDMA3_CCRL_SER_E11_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_SER_E11_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SER_E10_MASK   (0x00000400u)
+#define EDMA3_CCRL_SER_E10_SHIFT   (0x0000000Au)
+#define EDMA3_CCRL_SER_E10_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SER_E9_MASK   (0x00000200u)
+#define EDMA3_CCRL_SER_E9_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_SER_E9_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SER_E8_MASK   (0x00000100u)
+#define EDMA3_CCRL_SER_E8_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_SER_E8_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SER_E7_MASK   (0x00000080u)
+#define EDMA3_CCRL_SER_E7_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_SER_E7_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SER_E6_MASK   (0x00000040u)
+#define EDMA3_CCRL_SER_E6_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_SER_E6_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SER_E5_MASK   (0x00000020u)
+#define EDMA3_CCRL_SER_E5_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_SER_E5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SER_E4_MASK   (0x00000010u)
+#define EDMA3_CCRL_SER_E4_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_SER_E4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SER_E3_MASK   (0x00000008u)
+#define EDMA3_CCRL_SER_E3_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_SER_E3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SER_E2_MASK   (0x00000004u)
+#define EDMA3_CCRL_SER_E2_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_SER_E2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SER_E1_MASK   (0x00000002u)
+#define EDMA3_CCRL_SER_E1_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_SER_E1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SER_E0_MASK   (0x00000001u)
+#define EDMA3_CCRL_SER_E0_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_SER_E0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SER_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SERH_E63_MASK   (0x80000000u)
+#define EDMA3_CCRL_SERH_E63_SHIFT   (0x0000001Fu)
+#define EDMA3_CCRL_SERH_E63_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SERH_E62_MASK   (0x40000000u)
+#define EDMA3_CCRL_SERH_E62_SHIFT   (0x0000001Eu)
+#define EDMA3_CCRL_SERH_E62_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SERH_E61_MASK   (0x20000000u)
+#define EDMA3_CCRL_SERH_E61_SHIFT   (0x0000001Du)
+#define EDMA3_CCRL_SERH_E61_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SERH_E60_MASK   (0x10000000u)
+#define EDMA3_CCRL_SERH_E60_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_SERH_E60_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SERH_E59_MASK   (0x08000000u)
+#define EDMA3_CCRL_SERH_E59_SHIFT   (0x0000001Bu)
+#define EDMA3_CCRL_SERH_E59_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SERH_E58_MASK   (0x04000000u)
+#define EDMA3_CCRL_SERH_E58_SHIFT   (0x0000001Au)
+#define EDMA3_CCRL_SERH_E58_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SERH_E57_MASK   (0x02000000u)
+#define EDMA3_CCRL_SERH_E57_SHIFT   (0x00000019u)
+#define EDMA3_CCRL_SERH_E57_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SERH_E56_MASK   (0x01000000u)
+#define EDMA3_CCRL_SERH_E56_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_SERH_E56_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SERH_E55_MASK   (0x00800000u)
+#define EDMA3_CCRL_SERH_E55_SHIFT   (0x00000017u)
+#define EDMA3_CCRL_SERH_E55_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SERH_E54_MASK   (0x00400000u)
+#define EDMA3_CCRL_SERH_E54_SHIFT   (0x00000016u)
+#define EDMA3_CCRL_SERH_E54_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SERH_E53_MASK   (0x00200000u)
+#define EDMA3_CCRL_SERH_E53_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_SERH_E53_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SERH_E52_MASK   (0x00100000u)
+#define EDMA3_CCRL_SERH_E52_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_SERH_E52_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SERH_E51_MASK   (0x00080000u)
+#define EDMA3_CCRL_SERH_E51_SHIFT   (0x00000013u)
+#define EDMA3_CCRL_SERH_E51_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SERH_E50_MASK   (0x00040000u)
+#define EDMA3_CCRL_SERH_E50_SHIFT   (0x00000012u)
+#define EDMA3_CCRL_SERH_E50_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SERH_E49_MASK   (0x00020000u)
+#define EDMA3_CCRL_SERH_E49_SHIFT   (0x00000011u)
+#define EDMA3_CCRL_SERH_E49_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SERH_E48_MASK   (0x00010000u)
+#define EDMA3_CCRL_SERH_E48_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_SERH_E48_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SERH_E47_MASK   (0x00008000u)
+#define EDMA3_CCRL_SERH_E47_SHIFT   (0x0000000Fu)
+#define EDMA3_CCRL_SERH_E47_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SERH_E46_MASK   (0x00004000u)
+#define EDMA3_CCRL_SERH_E46_SHIFT   (0x0000000Eu)
+#define EDMA3_CCRL_SERH_E46_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SERH_E45_MASK   (0x00002000u)
+#define EDMA3_CCRL_SERH_E45_SHIFT   (0x0000000Du)
+#define EDMA3_CCRL_SERH_E45_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SERH_E44_MASK   (0x00001000u)
+#define EDMA3_CCRL_SERH_E44_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_SERH_E44_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SERH_E43_MASK   (0x00000800u)
+#define EDMA3_CCRL_SERH_E43_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_SERH_E43_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SERH_E42_MASK   (0x00000400u)
+#define EDMA3_CCRL_SERH_E42_SHIFT   (0x0000000Au)
+#define EDMA3_CCRL_SERH_E42_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SERH_E41_MASK   (0x00000200u)
+#define EDMA3_CCRL_SERH_E41_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_SERH_E41_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SERH_E40_MASK   (0x00000100u)
+#define EDMA3_CCRL_SERH_E40_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_SERH_E40_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SERH_E39_MASK   (0x00000080u)
+#define EDMA3_CCRL_SERH_E39_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_SERH_E39_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SERH_E38_MASK   (0x00000040u)
+#define EDMA3_CCRL_SERH_E38_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_SERH_E38_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SERH_E37_MASK   (0x00000020u)
+#define EDMA3_CCRL_SERH_E37_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_SERH_E37_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SERH_E36_MASK   (0x00000010u)
+#define EDMA3_CCRL_SERH_E36_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_SERH_E36_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SERH_E35_MASK   (0x00000008u)
+#define EDMA3_CCRL_SERH_E35_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_SERH_E35_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SERH_E34_MASK   (0x00000004u)
+#define EDMA3_CCRL_SERH_E34_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_SERH_E34_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SERH_E33_MASK   (0x00000002u)
+#define EDMA3_CCRL_SERH_E33_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_SERH_E33_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SERH_E32_MASK   (0x00000001u)
+#define EDMA3_CCRL_SERH_E32_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_SERH_E32_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SERH_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECR_E31_MASK   (0x80000000u)
+#define EDMA3_CCRL_SECR_E31_SHIFT   (0x0000001Fu)
+#define EDMA3_CCRL_SECR_E31_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECR_E31_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECR_E30_MASK   (0x40000000u)
+#define EDMA3_CCRL_SECR_E30_SHIFT   (0x0000001Eu)
+#define EDMA3_CCRL_SECR_E30_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECR_E30_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECR_E29_MASK   (0x20000000u)
+#define EDMA3_CCRL_SECR_E29_SHIFT   (0x0000001Du)
+#define EDMA3_CCRL_SECR_E29_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECR_E29_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECR_E28_MASK   (0x10000000u)
+#define EDMA3_CCRL_SECR_E28_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_SECR_E28_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECR_E28_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECR_E27_MASK   (0x08000000u)
+#define EDMA3_CCRL_SECR_E27_SHIFT   (0x0000001Bu)
+#define EDMA3_CCRL_SECR_E27_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECR_E27_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECR_E26_MASK   (0x04000000u)
+#define EDMA3_CCRL_SECR_E26_SHIFT   (0x0000001Au)
+#define EDMA3_CCRL_SECR_E26_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECR_E26_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECR_E25_MASK   (0x02000000u)
+#define EDMA3_CCRL_SECR_E25_SHIFT   (0x00000019u)
+#define EDMA3_CCRL_SECR_E25_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECR_E25_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECR_E24_MASK   (0x01000000u)
+#define EDMA3_CCRL_SECR_E24_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_SECR_E24_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECR_E24_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECR_E23_MASK   (0x00800000u)
+#define EDMA3_CCRL_SECR_E23_SHIFT   (0x00000017u)
+#define EDMA3_CCRL_SECR_E23_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECR_E23_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECR_E22_MASK   (0x00400000u)
+#define EDMA3_CCRL_SECR_E22_SHIFT   (0x00000016u)
+#define EDMA3_CCRL_SECR_E22_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECR_E22_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECR_E21_MASK   (0x00200000u)
+#define EDMA3_CCRL_SECR_E21_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_SECR_E21_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECR_E21_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECR_E20_MASK   (0x00100000u)
+#define EDMA3_CCRL_SECR_E20_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_SECR_E20_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECR_E20_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECR_E19_MASK   (0x00080000u)
+#define EDMA3_CCRL_SECR_E19_SHIFT   (0x00000013u)
+#define EDMA3_CCRL_SECR_E19_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECR_E19_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECR_E18_MASK   (0x00040000u)
+#define EDMA3_CCRL_SECR_E18_SHIFT   (0x00000012u)
+#define EDMA3_CCRL_SECR_E18_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECR_E18_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECR_E17_MASK   (0x00020000u)
+#define EDMA3_CCRL_SECR_E17_SHIFT   (0x00000011u)
+#define EDMA3_CCRL_SECR_E17_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECR_E17_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECR_E16_MASK   (0x00010000u)
+#define EDMA3_CCRL_SECR_E16_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_SECR_E16_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECR_E16_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECR_E15_MASK   (0x00008000u)
+#define EDMA3_CCRL_SECR_E15_SHIFT   (0x0000000Fu)
+#define EDMA3_CCRL_SECR_E15_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECR_E15_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECR_E14_MASK   (0x00004000u)
+#define EDMA3_CCRL_SECR_E14_SHIFT   (0x0000000Eu)
+#define EDMA3_CCRL_SECR_E14_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECR_E14_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECR_E13_MASK   (0x00002000u)
+#define EDMA3_CCRL_SECR_E13_SHIFT   (0x0000000Du)
+#define EDMA3_CCRL_SECR_E13_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECR_E13_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECR_E12_MASK   (0x00001000u)
+#define EDMA3_CCRL_SECR_E12_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_SECR_E12_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECR_E12_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECR_E11_MASK   (0x00000800u)
+#define EDMA3_CCRL_SECR_E11_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_SECR_E11_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECR_E11_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECR_E10_MASK   (0x00000400u)
+#define EDMA3_CCRL_SECR_E10_SHIFT   (0x0000000Au)
+#define EDMA3_CCRL_SECR_E10_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECR_E10_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECR_E9_MASK   (0x00000200u)
+#define EDMA3_CCRL_SECR_E9_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_SECR_E9_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECR_E9_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECR_E8_MASK   (0x00000100u)
+#define EDMA3_CCRL_SECR_E8_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_SECR_E8_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECR_E8_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECR_E7_MASK   (0x00000080u)
+#define EDMA3_CCRL_SECR_E7_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_SECR_E7_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECR_E7_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECR_E6_MASK   (0x00000040u)
+#define EDMA3_CCRL_SECR_E6_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_SECR_E6_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECR_E6_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECR_E5_MASK   (0x00000020u)
+#define EDMA3_CCRL_SECR_E5_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_SECR_E5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECR_E5_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECR_E4_MASK   (0x00000010u)
+#define EDMA3_CCRL_SECR_E4_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_SECR_E4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECR_E4_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECR_E3_MASK   (0x00000008u)
+#define EDMA3_CCRL_SECR_E3_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_SECR_E3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECR_E3_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECR_E2_MASK   (0x00000004u)
+#define EDMA3_CCRL_SECR_E2_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_SECR_E2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECR_E2_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECR_E1_MASK   (0x00000002u)
+#define EDMA3_CCRL_SECR_E1_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_SECR_E1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECR_E1_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECR_E0_MASK   (0x00000001u)
+#define EDMA3_CCRL_SECR_E0_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_SECR_E0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECR_E0_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECRH_E63_MASK   (0x80000000u)
+#define EDMA3_CCRL_SECRH_E63_SHIFT   (0x0000001Fu)
+#define EDMA3_CCRL_SECRH_E63_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECRH_E63_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECRH_E62_MASK   (0x40000000u)
+#define EDMA3_CCRL_SECRH_E62_SHIFT   (0x0000001Eu)
+#define EDMA3_CCRL_SECRH_E62_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECRH_E62_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECRH_E61_MASK   (0x20000000u)
+#define EDMA3_CCRL_SECRH_E61_SHIFT   (0x0000001Du)
+#define EDMA3_CCRL_SECRH_E61_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECRH_E61_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECRH_E60_MASK   (0x10000000u)
+#define EDMA3_CCRL_SECRH_E60_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_SECRH_E60_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECRH_E60_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECRH_E59_MASK   (0x08000000u)
+#define EDMA3_CCRL_SECRH_E59_SHIFT   (0x0000001Bu)
+#define EDMA3_CCRL_SECRH_E59_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECRH_E59_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECRH_E58_MASK   (0x04000000u)
+#define EDMA3_CCRL_SECRH_E58_SHIFT   (0x0000001Au)
+#define EDMA3_CCRL_SECRH_E58_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECRH_E58_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECRH_E57_MASK   (0x02000000u)
+#define EDMA3_CCRL_SECRH_E57_SHIFT   (0x00000019u)
+#define EDMA3_CCRL_SECRH_E57_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECRH_E57_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECRH_E56_MASK   (0x01000000u)
+#define EDMA3_CCRL_SECRH_E56_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_SECRH_E56_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECRH_E56_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECRH_E55_MASK   (0x00800000u)
+#define EDMA3_CCRL_SECRH_E55_SHIFT   (0x00000017u)
+#define EDMA3_CCRL_SECRH_E55_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECRH_E55_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECRH_E54_MASK   (0x00400000u)
+#define EDMA3_CCRL_SECRH_E54_SHIFT   (0x00000016u)
+#define EDMA3_CCRL_SECRH_E54_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECRH_E54_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECRH_E53_MASK   (0x00200000u)
+#define EDMA3_CCRL_SECRH_E53_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_SECRH_E53_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECRH_E53_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECRH_E52_MASK   (0x00100000u)
+#define EDMA3_CCRL_SECRH_E52_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_SECRH_E52_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECRH_E52_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECRH_E51_MASK   (0x00080000u)
+#define EDMA3_CCRL_SECRH_E51_SHIFT   (0x00000013u)
+#define EDMA3_CCRL_SECRH_E51_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECRH_E51_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECRH_E50_MASK   (0x00040000u)
+#define EDMA3_CCRL_SECRH_E50_SHIFT   (0x00000012u)
+#define EDMA3_CCRL_SECRH_E50_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECRH_E50_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECRH_E49_MASK   (0x00020000u)
+#define EDMA3_CCRL_SECRH_E49_SHIFT   (0x00000011u)
+#define EDMA3_CCRL_SECRH_E49_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECRH_E49_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECRH_E48_MASK   (0x00010000u)
+#define EDMA3_CCRL_SECRH_E48_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_SECRH_E48_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECRH_E48_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECRH_E47_MASK   (0x00008000u)
+#define EDMA3_CCRL_SECRH_E47_SHIFT   (0x0000000Fu)
+#define EDMA3_CCRL_SECRH_E47_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECRH_E47_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECRH_E46_MASK   (0x00004000u)
+#define EDMA3_CCRL_SECRH_E46_SHIFT   (0x0000000Eu)
+#define EDMA3_CCRL_SECRH_E46_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECRH_E46_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECRH_E45_MASK   (0x00002000u)
+#define EDMA3_CCRL_SECRH_E45_SHIFT   (0x0000000Du)
+#define EDMA3_CCRL_SECRH_E45_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECRH_E45_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECRH_E44_MASK   (0x00001000u)
+#define EDMA3_CCRL_SECRH_E44_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_SECRH_E44_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECRH_E44_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECRH_E43_MASK   (0x00000800u)
+#define EDMA3_CCRL_SECRH_E43_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_SECRH_E43_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECRH_E43_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECRH_E42_MASK   (0x00000400u)
+#define EDMA3_CCRL_SECRH_E42_SHIFT   (0x0000000Au)
+#define EDMA3_CCRL_SECRH_E42_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECRH_E42_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECRH_E41_MASK   (0x00000200u)
+#define EDMA3_CCRL_SECRH_E41_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_SECRH_E41_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECRH_E41_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECRH_E40_MASK   (0x00000100u)
+#define EDMA3_CCRL_SECRH_E40_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_SECRH_E40_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECRH_E40_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECRH_E39_MASK   (0x00000080u)
+#define EDMA3_CCRL_SECRH_E39_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_SECRH_E39_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECRH_E39_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECRH_E38_MASK   (0x00000040u)
+#define EDMA3_CCRL_SECRH_E38_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_SECRH_E38_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECRH_E38_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECRH_E37_MASK   (0x00000020u)
+#define EDMA3_CCRL_SECRH_E37_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_SECRH_E37_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECRH_E37_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECRH_E36_MASK   (0x00000010u)
+#define EDMA3_CCRL_SECRH_E36_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_SECRH_E36_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECRH_E36_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECRH_E35_MASK   (0x00000008u)
+#define EDMA3_CCRL_SECRH_E35_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_SECRH_E35_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECRH_E35_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECRH_E34_MASK   (0x00000004u)
+#define EDMA3_CCRL_SECRH_E34_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_SECRH_E34_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECRH_E34_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECRH_E33_MASK   (0x00000002u)
+#define EDMA3_CCRL_SECRH_E33_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_SECRH_E33_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECRH_E33_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECRH_E32_MASK   (0x00000001u)
+#define EDMA3_CCRL_SECRH_E32_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_SECRH_E32_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECRH_E32_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_SECRH_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IER_I31_MASK   (0x80000000u)
+#define EDMA3_CCRL_IER_I31_SHIFT   (0x0000001Fu)
+#define EDMA3_CCRL_IER_I31_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IER_I30_MASK   (0x40000000u)
+#define EDMA3_CCRL_IER_I30_SHIFT   (0x0000001Eu)
+#define EDMA3_CCRL_IER_I30_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IER_I29_MASK   (0x20000000u)
+#define EDMA3_CCRL_IER_I29_SHIFT   (0x0000001Du)
+#define EDMA3_CCRL_IER_I29_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IER_I28_MASK   (0x10000000u)
+#define EDMA3_CCRL_IER_I28_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_IER_I28_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IER_I27_MASK   (0x08000000u)
+#define EDMA3_CCRL_IER_I27_SHIFT   (0x0000001Bu)
+#define EDMA3_CCRL_IER_I27_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IER_I26_MASK   (0x04000000u)
+#define EDMA3_CCRL_IER_I26_SHIFT   (0x0000001Au)
+#define EDMA3_CCRL_IER_I26_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IER_I25_MASK   (0x02000000u)
+#define EDMA3_CCRL_IER_I25_SHIFT   (0x00000019u)
+#define EDMA3_CCRL_IER_I25_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IER_I24_MASK   (0x01000000u)
+#define EDMA3_CCRL_IER_I24_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_IER_I24_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IER_I23_MASK   (0x00800000u)
+#define EDMA3_CCRL_IER_I23_SHIFT   (0x00000017u)
+#define EDMA3_CCRL_IER_I23_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IER_I22_MASK   (0x00400000u)
+#define EDMA3_CCRL_IER_I22_SHIFT   (0x00000016u)
+#define EDMA3_CCRL_IER_I22_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IER_I21_MASK   (0x00200000u)
+#define EDMA3_CCRL_IER_I21_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_IER_I21_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IER_I20_MASK   (0x00100000u)
+#define EDMA3_CCRL_IER_I20_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_IER_I20_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IER_I19_MASK   (0x00080000u)
+#define EDMA3_CCRL_IER_I19_SHIFT   (0x00000013u)
+#define EDMA3_CCRL_IER_I19_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IER_I18_MASK   (0x00040000u)
+#define EDMA3_CCRL_IER_I18_SHIFT   (0x00000012u)
+#define EDMA3_CCRL_IER_I18_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IER_I17_MASK   (0x00020000u)
+#define EDMA3_CCRL_IER_I17_SHIFT   (0x00000011u)
+#define EDMA3_CCRL_IER_I17_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IER_I16_MASK   (0x00010000u)
+#define EDMA3_CCRL_IER_I16_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_IER_I16_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IER_I15_MASK   (0x00008000u)
+#define EDMA3_CCRL_IER_I15_SHIFT   (0x0000000Fu)
+#define EDMA3_CCRL_IER_I15_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IER_I14_MASK   (0x00004000u)
+#define EDMA3_CCRL_IER_I14_SHIFT   (0x0000000Eu)
+#define EDMA3_CCRL_IER_I14_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IER_I13_MASK   (0x00002000u)
+#define EDMA3_CCRL_IER_I13_SHIFT   (0x0000000Du)
+#define EDMA3_CCRL_IER_I13_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IER_I12_MASK   (0x00001000u)
+#define EDMA3_CCRL_IER_I12_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_IER_I12_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IER_I11_MASK   (0x00000800u)
+#define EDMA3_CCRL_IER_I11_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_IER_I11_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IER_I10_MASK   (0x00000400u)
+#define EDMA3_CCRL_IER_I10_SHIFT   (0x0000000Au)
+#define EDMA3_CCRL_IER_I10_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IER_I9_MASK   (0x00000200u)
+#define EDMA3_CCRL_IER_I9_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_IER_I9_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IER_I8_MASK   (0x00000100u)
+#define EDMA3_CCRL_IER_I8_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_IER_I8_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IER_I7_MASK   (0x00000080u)
+#define EDMA3_CCRL_IER_I7_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_IER_I7_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IER_I6_MASK   (0x00000040u)
+#define EDMA3_CCRL_IER_I6_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_IER_I6_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IER_I5_MASK   (0x00000020u)
+#define EDMA3_CCRL_IER_I5_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_IER_I5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IER_I4_MASK   (0x00000010u)
+#define EDMA3_CCRL_IER_I4_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_IER_I4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IER_I3_MASK   (0x00000008u)
+#define EDMA3_CCRL_IER_I3_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_IER_I3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IER_I2_MASK   (0x00000004u)
+#define EDMA3_CCRL_IER_I2_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_IER_I2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IER_I1_MASK   (0x00000002u)
+#define EDMA3_CCRL_IER_I1_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_IER_I1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IER_I0_MASK   (0x00000001u)
+#define EDMA3_CCRL_IER_I0_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_IER_I0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IER_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IERH_I63_MASK   (0x80000000u)
+#define EDMA3_CCRL_IERH_I63_SHIFT   (0x0000001Fu)
+#define EDMA3_CCRL_IERH_I63_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IERH_I62_MASK   (0x40000000u)
+#define EDMA3_CCRL_IERH_I62_SHIFT   (0x0000001Eu)
+#define EDMA3_CCRL_IERH_I62_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IERH_I61_MASK   (0x20000000u)
+#define EDMA3_CCRL_IERH_I61_SHIFT   (0x0000001Du)
+#define EDMA3_CCRL_IERH_I61_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IERH_I60_MASK   (0x10000000u)
+#define EDMA3_CCRL_IERH_I60_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_IERH_I60_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IERH_I59_MASK   (0x08000000u)
+#define EDMA3_CCRL_IERH_I59_SHIFT   (0x0000001Bu)
+#define EDMA3_CCRL_IERH_I59_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IERH_I58_MASK   (0x04000000u)
+#define EDMA3_CCRL_IERH_I58_SHIFT   (0x0000001Au)
+#define EDMA3_CCRL_IERH_I58_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IERH_I57_MASK   (0x02000000u)
+#define EDMA3_CCRL_IERH_I57_SHIFT   (0x00000019u)
+#define EDMA3_CCRL_IERH_I57_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IERH_I56_MASK   (0x01000000u)
+#define EDMA3_CCRL_IERH_I56_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_IERH_I56_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IERH_I55_MASK   (0x00800000u)
+#define EDMA3_CCRL_IERH_I55_SHIFT   (0x00000017u)
+#define EDMA3_CCRL_IERH_I55_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IERH_I54_MASK   (0x00400000u)
+#define EDMA3_CCRL_IERH_I54_SHIFT   (0x00000016u)
+#define EDMA3_CCRL_IERH_I54_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IERH_I53_MASK   (0x00200000u)
+#define EDMA3_CCRL_IERH_I53_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_IERH_I53_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IERH_I52_MASK   (0x00100000u)
+#define EDMA3_CCRL_IERH_I52_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_IERH_I52_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IERH_I51_MASK   (0x00080000u)
+#define EDMA3_CCRL_IERH_I51_SHIFT   (0x00000013u)
+#define EDMA3_CCRL_IERH_I51_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IERH_I50_MASK   (0x00040000u)
+#define EDMA3_CCRL_IERH_I50_SHIFT   (0x00000012u)
+#define EDMA3_CCRL_IERH_I50_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IERH_I49_MASK   (0x00020000u)
+#define EDMA3_CCRL_IERH_I49_SHIFT   (0x00000011u)
+#define EDMA3_CCRL_IERH_I49_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IERH_I48_MASK   (0x00010000u)
+#define EDMA3_CCRL_IERH_I48_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_IERH_I48_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IERH_I47_MASK   (0x00008000u)
+#define EDMA3_CCRL_IERH_I47_SHIFT   (0x0000000Fu)
+#define EDMA3_CCRL_IERH_I47_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IERH_I46_MASK   (0x00004000u)
+#define EDMA3_CCRL_IERH_I46_SHIFT   (0x0000000Eu)
+#define EDMA3_CCRL_IERH_I46_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IERH_I45_MASK   (0x00002000u)
+#define EDMA3_CCRL_IERH_I45_SHIFT   (0x0000000Du)
+#define EDMA3_CCRL_IERH_I45_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IERH_I44_MASK   (0x00001000u)
+#define EDMA3_CCRL_IERH_I44_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_IERH_I44_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IERH_I43_MASK   (0x00000800u)
+#define EDMA3_CCRL_IERH_I43_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_IERH_I43_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IERH_I42_MASK   (0x00000400u)
+#define EDMA3_CCRL_IERH_I42_SHIFT   (0x0000000Au)
+#define EDMA3_CCRL_IERH_I42_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IERH_I41_MASK   (0x00000200u)
+#define EDMA3_CCRL_IERH_I41_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_IERH_I41_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IERH_I40_MASK   (0x00000100u)
+#define EDMA3_CCRL_IERH_I40_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_IERH_I40_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IERH_I39_MASK   (0x00000080u)
+#define EDMA3_CCRL_IERH_I39_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_IERH_I39_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IERH_I38_MASK   (0x00000040u)
+#define EDMA3_CCRL_IERH_I38_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_IERH_I38_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IERH_I37_MASK   (0x00000020u)
+#define EDMA3_CCRL_IERH_I37_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_IERH_I37_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IERH_I36_MASK   (0x00000010u)
+#define EDMA3_CCRL_IERH_I36_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_IERH_I36_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IERH_I35_MASK   (0x00000008u)
+#define EDMA3_CCRL_IERH_I35_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_IERH_I35_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IERH_I34_MASK   (0x00000004u)
+#define EDMA3_CCRL_IERH_I34_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_IERH_I34_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IERH_I33_MASK   (0x00000002u)
+#define EDMA3_CCRL_IERH_I33_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_IERH_I33_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IERH_I32_MASK   (0x00000001u)
+#define EDMA3_CCRL_IERH_I32_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_IERH_I32_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IERH_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECR_I31_MASK   (0x80000000u)
+#define EDMA3_CCRL_IECR_I31_SHIFT   (0x0000001Fu)
+#define EDMA3_CCRL_IECR_I31_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECR_I31_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECR_I30_MASK   (0x40000000u)
+#define EDMA3_CCRL_IECR_I30_SHIFT   (0x0000001Eu)
+#define EDMA3_CCRL_IECR_I30_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECR_I30_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECR_I29_MASK   (0x20000000u)
+#define EDMA3_CCRL_IECR_I29_SHIFT   (0x0000001Du)
+#define EDMA3_CCRL_IECR_I29_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECR_I29_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECR_I28_MASK   (0x10000000u)
+#define EDMA3_CCRL_IECR_I28_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_IECR_I28_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECR_I28_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECR_I27_MASK   (0x08000000u)
+#define EDMA3_CCRL_IECR_I27_SHIFT   (0x0000001Bu)
+#define EDMA3_CCRL_IECR_I27_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECR_I27_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECR_I26_MASK   (0x04000000u)
+#define EDMA3_CCRL_IECR_I26_SHIFT   (0x0000001Au)
+#define EDMA3_CCRL_IECR_I26_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECR_I26_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECR_I25_MASK   (0x02000000u)
+#define EDMA3_CCRL_IECR_I25_SHIFT   (0x00000019u)
+#define EDMA3_CCRL_IECR_I25_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECR_I25_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECR_I24_MASK   (0x01000000u)
+#define EDMA3_CCRL_IECR_I24_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_IECR_I24_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECR_I24_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECR_I23_MASK   (0x00800000u)
+#define EDMA3_CCRL_IECR_I23_SHIFT   (0x00000017u)
+#define EDMA3_CCRL_IECR_I23_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECR_I23_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECR_I22_MASK   (0x00400000u)
+#define EDMA3_CCRL_IECR_I22_SHIFT   (0x00000016u)
+#define EDMA3_CCRL_IECR_I22_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECR_I22_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECR_I21_MASK   (0x00200000u)
+#define EDMA3_CCRL_IECR_I21_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_IECR_I21_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECR_I21_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECR_I20_MASK   (0x00100000u)
+#define EDMA3_CCRL_IECR_I20_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_IECR_I20_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECR_I20_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECR_I19_MASK   (0x00080000u)
+#define EDMA3_CCRL_IECR_I19_SHIFT   (0x00000013u)
+#define EDMA3_CCRL_IECR_I19_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECR_I19_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECR_I18_MASK   (0x00040000u)
+#define EDMA3_CCRL_IECR_I18_SHIFT   (0x00000012u)
+#define EDMA3_CCRL_IECR_I18_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECR_I18_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECR_I17_MASK   (0x00020000u)
+#define EDMA3_CCRL_IECR_I17_SHIFT   (0x00000011u)
+#define EDMA3_CCRL_IECR_I17_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECR_I17_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECR_I16_MASK   (0x00010000u)
+#define EDMA3_CCRL_IECR_I16_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_IECR_I16_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECR_I16_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECR_I15_MASK   (0x00008000u)
+#define EDMA3_CCRL_IECR_I15_SHIFT   (0x0000000Fu)
+#define EDMA3_CCRL_IECR_I15_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECR_I15_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECR_I14_MASK   (0x00004000u)
+#define EDMA3_CCRL_IECR_I14_SHIFT   (0x0000000Eu)
+#define EDMA3_CCRL_IECR_I14_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECR_I14_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECR_I13_MASK   (0x00002000u)
+#define EDMA3_CCRL_IECR_I13_SHIFT   (0x0000000Du)
+#define EDMA3_CCRL_IECR_I13_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECR_I13_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECR_I12_MASK   (0x00001000u)
+#define EDMA3_CCRL_IECR_I12_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_IECR_I12_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECR_I12_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECR_I11_MASK   (0x00000800u)
+#define EDMA3_CCRL_IECR_I11_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_IECR_I11_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECR_I11_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECR_I10_MASK   (0x00000400u)
+#define EDMA3_CCRL_IECR_I10_SHIFT   (0x0000000Au)
+#define EDMA3_CCRL_IECR_I10_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECR_I10_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECR_I9_MASK   (0x00000200u)
+#define EDMA3_CCRL_IECR_I9_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_IECR_I9_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECR_I9_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECR_I8_MASK   (0x00000100u)
+#define EDMA3_CCRL_IECR_I8_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_IECR_I8_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECR_I8_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECR_I7_MASK   (0x00000080u)
+#define EDMA3_CCRL_IECR_I7_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_IECR_I7_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECR_I7_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECR_I6_MASK   (0x00000040u)
+#define EDMA3_CCRL_IECR_I6_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_IECR_I6_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECR_I6_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECR_I5_MASK   (0x00000020u)
+#define EDMA3_CCRL_IECR_I5_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_IECR_I5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECR_I5_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECR_I4_MASK   (0x00000010u)
+#define EDMA3_CCRL_IECR_I4_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_IECR_I4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECR_I4_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECR_I3_MASK   (0x00000008u)
+#define EDMA3_CCRL_IECR_I3_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_IECR_I3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECR_I3_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECR_I2_MASK   (0x00000004u)
+#define EDMA3_CCRL_IECR_I2_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_IECR_I2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECR_I2_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECR_I1_MASK   (0x00000002u)
+#define EDMA3_CCRL_IECR_I1_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_IECR_I1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECR_I1_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECR_I0_MASK   (0x00000001u)
+#define EDMA3_CCRL_IECR_I0_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_IECR_I0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECR_I0_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECRH_I63_MASK   (0x80000000u)
+#define EDMA3_CCRL_IECRH_I63_SHIFT   (0x0000001Fu)
+#define EDMA3_CCRL_IECRH_I63_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECRH_I63_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECRH_I62_MASK   (0x40000000u)
+#define EDMA3_CCRL_IECRH_I62_SHIFT   (0x0000001Eu)
+#define EDMA3_CCRL_IECRH_I62_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECRH_I62_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECRH_I61_MASK   (0x20000000u)
+#define EDMA3_CCRL_IECRH_I61_SHIFT   (0x0000001Du)
+#define EDMA3_CCRL_IECRH_I61_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECRH_I61_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECRH_I60_MASK   (0x10000000u)
+#define EDMA3_CCRL_IECRH_I60_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_IECRH_I60_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECRH_I60_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECRH_I59_MASK   (0x08000000u)
+#define EDMA3_CCRL_IECRH_I59_SHIFT   (0x0000001Bu)
+#define EDMA3_CCRL_IECRH_I59_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECRH_I59_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECRH_I58_MASK   (0x04000000u)
+#define EDMA3_CCRL_IECRH_I58_SHIFT   (0x0000001Au)
+#define EDMA3_CCRL_IECRH_I58_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECRH_I58_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECRH_I57_MASK   (0x02000000u)
+#define EDMA3_CCRL_IECRH_I57_SHIFT   (0x00000019u)
+#define EDMA3_CCRL_IECRH_I57_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECRH_I57_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECRH_I56_MASK   (0x01000000u)
+#define EDMA3_CCRL_IECRH_I56_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_IECRH_I56_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECRH_I56_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECRH_I55_MASK   (0x00800000u)
+#define EDMA3_CCRL_IECRH_I55_SHIFT   (0x00000017u)
+#define EDMA3_CCRL_IECRH_I55_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECRH_I55_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECRH_I54_MASK   (0x00400000u)
+#define EDMA3_CCRL_IECRH_I54_SHIFT   (0x00000016u)
+#define EDMA3_CCRL_IECRH_I54_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECRH_I54_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECRH_I53_MASK   (0x00200000u)
+#define EDMA3_CCRL_IECRH_I53_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_IECRH_I53_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECRH_I53_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECRH_I52_MASK   (0x00100000u)
+#define EDMA3_CCRL_IECRH_I52_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_IECRH_I52_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECRH_I52_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECRH_I51_MASK   (0x00080000u)
+#define EDMA3_CCRL_IECRH_I51_SHIFT   (0x00000013u)
+#define EDMA3_CCRL_IECRH_I51_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECRH_I51_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECRH_I50_MASK   (0x00040000u)
+#define EDMA3_CCRL_IECRH_I50_SHIFT   (0x00000012u)
+#define EDMA3_CCRL_IECRH_I50_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECRH_I50_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECRH_I49_MASK   (0x00020000u)
+#define EDMA3_CCRL_IECRH_I49_SHIFT   (0x00000011u)
+#define EDMA3_CCRL_IECRH_I49_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECRH_I49_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECRH_I48_MASK   (0x00010000u)
+#define EDMA3_CCRL_IECRH_I48_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_IECRH_I48_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECRH_I48_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECRH_I47_MASK   (0x00008000u)
+#define EDMA3_CCRL_IECRH_I47_SHIFT   (0x0000000Fu)
+#define EDMA3_CCRL_IECRH_I47_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECRH_I47_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECRH_I46_MASK   (0x00004000u)
+#define EDMA3_CCRL_IECRH_I46_SHIFT   (0x0000000Eu)
+#define EDMA3_CCRL_IECRH_I46_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECRH_I46_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECRH_I45_MASK   (0x00002000u)
+#define EDMA3_CCRL_IECRH_I45_SHIFT   (0x0000000Du)
+#define EDMA3_CCRL_IECRH_I45_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECRH_I45_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECRH_I44_MASK   (0x00001000u)
+#define EDMA3_CCRL_IECRH_I44_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_IECRH_I44_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECRH_I44_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECRH_I43_MASK   (0x00000800u)
+#define EDMA3_CCRL_IECRH_I43_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_IECRH_I43_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECRH_I43_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECRH_I42_MASK   (0x00000400u)
+#define EDMA3_CCRL_IECRH_I42_SHIFT   (0x0000000Au)
+#define EDMA3_CCRL_IECRH_I42_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECRH_I42_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECRH_I41_MASK   (0x00000200u)
+#define EDMA3_CCRL_IECRH_I41_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_IECRH_I41_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECRH_I41_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECRH_I40_MASK   (0x00000100u)
+#define EDMA3_CCRL_IECRH_I40_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_IECRH_I40_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECRH_I40_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECRH_I39_MASK   (0x00000080u)
+#define EDMA3_CCRL_IECRH_I39_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_IECRH_I39_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECRH_I39_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECRH_I38_MASK   (0x00000040u)
+#define EDMA3_CCRL_IECRH_I38_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_IECRH_I38_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECRH_I38_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECRH_I37_MASK   (0x00000020u)
+#define EDMA3_CCRL_IECRH_I37_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_IECRH_I37_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECRH_I37_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECRH_I36_MASK   (0x00000010u)
+#define EDMA3_CCRL_IECRH_I36_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_IECRH_I36_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECRH_I36_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECRH_I35_MASK   (0x00000008u)
+#define EDMA3_CCRL_IECRH_I35_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_IECRH_I35_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECRH_I35_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECRH_I34_MASK   (0x00000004u)
+#define EDMA3_CCRL_IECRH_I34_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_IECRH_I34_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECRH_I34_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECRH_I33_MASK   (0x00000002u)
+#define EDMA3_CCRL_IECRH_I33_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_IECRH_I33_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECRH_I33_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECRH_I32_MASK   (0x00000001u)
+#define EDMA3_CCRL_IECRH_I32_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_IECRH_I32_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECRH_I32_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_IECRH_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESR_I31_MASK   (0x80000000u)
+#define EDMA3_CCRL_IESR_I31_SHIFT   (0x0000001Fu)
+#define EDMA3_CCRL_IESR_I31_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESR_I31_SET   (0x00000001u)
+#define EDMA3_CCRL_IESR_I30_MASK   (0x40000000u)
+#define EDMA3_CCRL_IESR_I30_SHIFT   (0x0000001Eu)
+#define EDMA3_CCRL_IESR_I30_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESR_I30_SET   (0x00000001u)
+#define EDMA3_CCRL_IESR_I29_MASK   (0x20000000u)
+#define EDMA3_CCRL_IESR_I29_SHIFT   (0x0000001Du)
+#define EDMA3_CCRL_IESR_I29_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESR_I29_SET   (0x00000001u)
+#define EDMA3_CCRL_IESR_I28_MASK   (0x10000000u)
+#define EDMA3_CCRL_IESR_I28_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_IESR_I28_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESR_I28_SET   (0x00000001u)
+#define EDMA3_CCRL_IESR_I27_MASK   (0x08000000u)
+#define EDMA3_CCRL_IESR_I27_SHIFT   (0x0000001Bu)
+#define EDMA3_CCRL_IESR_I27_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESR_I27_SET   (0x00000001u)
+#define EDMA3_CCRL_IESR_I26_MASK   (0x04000000u)
+#define EDMA3_CCRL_IESR_I26_SHIFT   (0x0000001Au)
+#define EDMA3_CCRL_IESR_I26_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESR_I26_SET   (0x00000001u)
+#define EDMA3_CCRL_IESR_I25_MASK   (0x02000000u)
+#define EDMA3_CCRL_IESR_I25_SHIFT   (0x00000019u)
+#define EDMA3_CCRL_IESR_I25_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESR_I25_SET   (0x00000001u)
+#define EDMA3_CCRL_IESR_I24_MASK   (0x01000000u)
+#define EDMA3_CCRL_IESR_I24_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_IESR_I24_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESR_I24_SET   (0x00000001u)
+#define EDMA3_CCRL_IESR_I23_MASK   (0x00800000u)
+#define EDMA3_CCRL_IESR_I23_SHIFT   (0x00000017u)
+#define EDMA3_CCRL_IESR_I23_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESR_I23_SET   (0x00000001u)
+#define EDMA3_CCRL_IESR_I22_MASK   (0x00400000u)
+#define EDMA3_CCRL_IESR_I22_SHIFT   (0x00000016u)
+#define EDMA3_CCRL_IESR_I22_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESR_I22_SET   (0x00000001u)
+#define EDMA3_CCRL_IESR_I21_MASK   (0x00200000u)
+#define EDMA3_CCRL_IESR_I21_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_IESR_I21_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESR_I21_SET   (0x00000001u)
+#define EDMA3_CCRL_IESR_I20_MASK   (0x00100000u)
+#define EDMA3_CCRL_IESR_I20_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_IESR_I20_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESR_I20_SET   (0x00000001u)
+#define EDMA3_CCRL_IESR_I19_MASK   (0x00080000u)
+#define EDMA3_CCRL_IESR_I19_SHIFT   (0x00000013u)
+#define EDMA3_CCRL_IESR_I19_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESR_I19_SET   (0x00000001u)
+#define EDMA3_CCRL_IESR_I18_MASK   (0x00040000u)
+#define EDMA3_CCRL_IESR_I18_SHIFT   (0x00000012u)
+#define EDMA3_CCRL_IESR_I18_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESR_I18_SET   (0x00000001u)
+#define EDMA3_CCRL_IESR_I17_MASK   (0x00020000u)
+#define EDMA3_CCRL_IESR_I17_SHIFT   (0x00000011u)
+#define EDMA3_CCRL_IESR_I17_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESR_I17_SET   (0x00000001u)
+#define EDMA3_CCRL_IESR_I16_MASK   (0x00010000u)
+#define EDMA3_CCRL_IESR_I16_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_IESR_I16_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESR_I16_SET   (0x00000001u)
+#define EDMA3_CCRL_IESR_I15_MASK   (0x00008000u)
+#define EDMA3_CCRL_IESR_I15_SHIFT   (0x0000000Fu)
+#define EDMA3_CCRL_IESR_I15_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESR_I15_SET   (0x00000001u)
+#define EDMA3_CCRL_IESR_I14_MASK   (0x00004000u)
+#define EDMA3_CCRL_IESR_I14_SHIFT   (0x0000000Eu)
+#define EDMA3_CCRL_IESR_I14_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESR_I14_SET   (0x00000001u)
+#define EDMA3_CCRL_IESR_I13_MASK   (0x00002000u)
+#define EDMA3_CCRL_IESR_I13_SHIFT   (0x0000000Du)
+#define EDMA3_CCRL_IESR_I13_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESR_I13_SET   (0x00000001u)
+#define EDMA3_CCRL_IESR_I12_MASK   (0x00001000u)
+#define EDMA3_CCRL_IESR_I12_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_IESR_I12_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESR_I12_SET   (0x00000001u)
+#define EDMA3_CCRL_IESR_I11_MASK   (0x00000800u)
+#define EDMA3_CCRL_IESR_I11_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_IESR_I11_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESR_I11_SET   (0x00000001u)
+#define EDMA3_CCRL_IESR_I10_MASK   (0x00000400u)
+#define EDMA3_CCRL_IESR_I10_SHIFT   (0x0000000Au)
+#define EDMA3_CCRL_IESR_I10_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESR_I10_SET   (0x00000001u)
+#define EDMA3_CCRL_IESR_I9_MASK   (0x00000200u)
+#define EDMA3_CCRL_IESR_I9_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_IESR_I9_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESR_I9_SET   (0x00000001u)
+#define EDMA3_CCRL_IESR_I8_MASK   (0x00000100u)
+#define EDMA3_CCRL_IESR_I8_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_IESR_I8_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESR_I8_SET   (0x00000001u)
+#define EDMA3_CCRL_IESR_I7_MASK   (0x00000080u)
+#define EDMA3_CCRL_IESR_I7_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_IESR_I7_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESR_I7_SET   (0x00000001u)
+#define EDMA3_CCRL_IESR_I6_MASK   (0x00000040u)
+#define EDMA3_CCRL_IESR_I6_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_IESR_I6_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESR_I6_SET   (0x00000001u)
+#define EDMA3_CCRL_IESR_I5_MASK   (0x00000020u)
+#define EDMA3_CCRL_IESR_I5_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_IESR_I5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESR_I5_SET   (0x00000001u)
+#define EDMA3_CCRL_IESR_I4_MASK   (0x00000010u)
+#define EDMA3_CCRL_IESR_I4_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_IESR_I4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESR_I4_SET   (0x00000001u)
+#define EDMA3_CCRL_IESR_I3_MASK   (0x00000008u)
+#define EDMA3_CCRL_IESR_I3_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_IESR_I3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESR_I3_SET   (0x00000001u)
+#define EDMA3_CCRL_IESR_I2_MASK   (0x00000004u)
+#define EDMA3_CCRL_IESR_I2_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_IESR_I2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESR_I2_SET   (0x00000001u)
+#define EDMA3_CCRL_IESR_I1_MASK   (0x00000002u)
+#define EDMA3_CCRL_IESR_I1_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_IESR_I1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESR_I1_SET   (0x00000001u)
+#define EDMA3_CCRL_IESR_I0_MASK   (0x00000001u)
+#define EDMA3_CCRL_IESR_I0_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_IESR_I0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESR_I0_SET   (0x00000001u)
+#define EDMA3_CCRL_IESR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESRH_I63_MASK   (0x80000000u)
+#define EDMA3_CCRL_IESRH_I63_SHIFT   (0x0000001Fu)
+#define EDMA3_CCRL_IESRH_I63_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESRH_I63_SET   (0x00000001u)
+#define EDMA3_CCRL_IESRH_I62_MASK   (0x40000000u)
+#define EDMA3_CCRL_IESRH_I62_SHIFT   (0x0000001Eu)
+#define EDMA3_CCRL_IESRH_I62_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESRH_I62_SET   (0x00000001u)
+#define EDMA3_CCRL_IESRH_I61_MASK   (0x20000000u)
+#define EDMA3_CCRL_IESRH_I61_SHIFT   (0x0000001Du)
+#define EDMA3_CCRL_IESRH_I61_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESRH_I61_SET   (0x00000001u)
+#define EDMA3_CCRL_IESRH_I60_MASK   (0x10000000u)
+#define EDMA3_CCRL_IESRH_I60_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_IESRH_I60_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESRH_I60_SET   (0x00000001u)
+#define EDMA3_CCRL_IESRH_I59_MASK   (0x08000000u)
+#define EDMA3_CCRL_IESRH_I59_SHIFT   (0x0000001Bu)
+#define EDMA3_CCRL_IESRH_I59_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESRH_I59_SET   (0x00000001u)
+#define EDMA3_CCRL_IESRH_I58_MASK   (0x04000000u)
+#define EDMA3_CCRL_IESRH_I58_SHIFT   (0x0000001Au)
+#define EDMA3_CCRL_IESRH_I58_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESRH_I58_SET   (0x00000001u)
+#define EDMA3_CCRL_IESRH_I57_MASK   (0x02000000u)
+#define EDMA3_CCRL_IESRH_I57_SHIFT   (0x00000019u)
+#define EDMA3_CCRL_IESRH_I57_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESRH_I57_SET   (0x00000001u)
+#define EDMA3_CCRL_IESRH_I56_MASK   (0x01000000u)
+#define EDMA3_CCRL_IESRH_I56_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_IESRH_I56_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESRH_I56_SET   (0x00000001u)
+#define EDMA3_CCRL_IESRH_I55_MASK   (0x00800000u)
+#define EDMA3_CCRL_IESRH_I55_SHIFT   (0x00000017u)
+#define EDMA3_CCRL_IESRH_I55_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESRH_I55_SET   (0x00000001u)
+#define EDMA3_CCRL_IESRH_I54_MASK   (0x00400000u)
+#define EDMA3_CCRL_IESRH_I54_SHIFT   (0x00000016u)
+#define EDMA3_CCRL_IESRH_I54_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESRH_I54_SET   (0x00000001u)
+#define EDMA3_CCRL_IESRH_I53_MASK   (0x00200000u)
+#define EDMA3_CCRL_IESRH_I53_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_IESRH_I53_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESRH_I53_SET   (0x00000001u)
+#define EDMA3_CCRL_IESRH_I52_MASK   (0x00100000u)
+#define EDMA3_CCRL_IESRH_I52_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_IESRH_I52_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESRH_I52_SET   (0x00000001u)
+#define EDMA3_CCRL_IESRH_I51_MASK   (0x00080000u)
+#define EDMA3_CCRL_IESRH_I51_SHIFT   (0x00000013u)
+#define EDMA3_CCRL_IESRH_I51_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESRH_I51_SET   (0x00000001u)
+#define EDMA3_CCRL_IESRH_I50_MASK   (0x00040000u)
+#define EDMA3_CCRL_IESRH_I50_SHIFT   (0x00000012u)
+#define EDMA3_CCRL_IESRH_I50_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESRH_I50_SET   (0x00000001u)
+#define EDMA3_CCRL_IESRH_I49_MASK   (0x00020000u)
+#define EDMA3_CCRL_IESRH_I49_SHIFT   (0x00000011u)
+#define EDMA3_CCRL_IESRH_I49_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESRH_I49_SET   (0x00000001u)
+#define EDMA3_CCRL_IESRH_I48_MASK   (0x00010000u)
+#define EDMA3_CCRL_IESRH_I48_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_IESRH_I48_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESRH_I48_SET   (0x00000001u)
+#define EDMA3_CCRL_IESRH_I47_MASK   (0x00008000u)
+#define EDMA3_CCRL_IESRH_I47_SHIFT   (0x0000000Fu)
+#define EDMA3_CCRL_IESRH_I47_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESRH_I47_SET   (0x00000001u)
+#define EDMA3_CCRL_IESRH_I46_MASK   (0x00004000u)
+#define EDMA3_CCRL_IESRH_I46_SHIFT   (0x0000000Eu)
+#define EDMA3_CCRL_IESRH_I46_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESRH_I46_SET   (0x00000001u)
+#define EDMA3_CCRL_IESRH_I45_MASK   (0x00002000u)
+#define EDMA3_CCRL_IESRH_I45_SHIFT   (0x0000000Du)
+#define EDMA3_CCRL_IESRH_I45_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESRH_I45_SET   (0x00000001u)
+#define EDMA3_CCRL_IESRH_I44_MASK   (0x00001000u)
+#define EDMA3_CCRL_IESRH_I44_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_IESRH_I44_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESRH_I44_SET   (0x00000001u)
+#define EDMA3_CCRL_IESRH_I43_MASK   (0x00000800u)
+#define EDMA3_CCRL_IESRH_I43_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_IESRH_I43_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESRH_I43_SET   (0x00000001u)
+#define EDMA3_CCRL_IESRH_I42_MASK   (0x00000400u)
+#define EDMA3_CCRL_IESRH_I42_SHIFT   (0x0000000Au)
+#define EDMA3_CCRL_IESRH_I42_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESRH_I42_SET   (0x00000001u)
+#define EDMA3_CCRL_IESRH_I41_MASK   (0x00000200u)
+#define EDMA3_CCRL_IESRH_I41_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_IESRH_I41_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESRH_I41_SET   (0x00000001u)
+#define EDMA3_CCRL_IESRH_I40_MASK   (0x00000100u)
+#define EDMA3_CCRL_IESRH_I40_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_IESRH_I40_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESRH_I40_SET   (0x00000001u)
+#define EDMA3_CCRL_IESRH_I39_MASK   (0x00000080u)
+#define EDMA3_CCRL_IESRH_I39_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_IESRH_I39_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESRH_I39_SET   (0x00000001u)
+#define EDMA3_CCRL_IESRH_I38_MASK   (0x00000040u)
+#define EDMA3_CCRL_IESRH_I38_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_IESRH_I38_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESRH_I38_SET   (0x00000001u)
+#define EDMA3_CCRL_IESRH_I37_MASK   (0x00000020u)
+#define EDMA3_CCRL_IESRH_I37_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_IESRH_I37_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESRH_I37_SET   (0x00000001u)
+#define EDMA3_CCRL_IESRH_I36_MASK   (0x00000010u)
+#define EDMA3_CCRL_IESRH_I36_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_IESRH_I36_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESRH_I36_SET   (0x00000001u)
+#define EDMA3_CCRL_IESRH_I35_MASK   (0x00000008u)
+#define EDMA3_CCRL_IESRH_I35_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_IESRH_I35_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESRH_I35_SET   (0x00000001u)
+#define EDMA3_CCRL_IESRH_I34_MASK   (0x00000004u)
+#define EDMA3_CCRL_IESRH_I34_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_IESRH_I34_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESRH_I34_SET   (0x00000001u)
+#define EDMA3_CCRL_IESRH_I33_MASK   (0x00000002u)
+#define EDMA3_CCRL_IESRH_I33_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_IESRH_I33_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESRH_I33_SET   (0x00000001u)
+#define EDMA3_CCRL_IESRH_I32_MASK   (0x00000001u)
+#define EDMA3_CCRL_IESRH_I32_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_IESRH_I32_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESRH_I32_SET   (0x00000001u)
+#define EDMA3_CCRL_IESRH_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPR_I31_MASK   (0x80000000u)
+#define EDMA3_CCRL_IPR_I31_SHIFT   (0x0000001Fu)
+#define EDMA3_CCRL_IPR_I31_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPR_I30_MASK   (0x40000000u)
+#define EDMA3_CCRL_IPR_I30_SHIFT   (0x0000001Eu)
+#define EDMA3_CCRL_IPR_I30_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPR_I29_MASK   (0x20000000u)
+#define EDMA3_CCRL_IPR_I29_SHIFT   (0x0000001Du)
+#define EDMA3_CCRL_IPR_I29_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPR_I28_MASK   (0x10000000u)
+#define EDMA3_CCRL_IPR_I28_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_IPR_I28_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPR_I27_MASK   (0x08000000u)
+#define EDMA3_CCRL_IPR_I27_SHIFT   (0x0000001Bu)
+#define EDMA3_CCRL_IPR_I27_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPR_I26_MASK   (0x04000000u)
+#define EDMA3_CCRL_IPR_I26_SHIFT   (0x0000001Au)
+#define EDMA3_CCRL_IPR_I26_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPR_I25_MASK   (0x02000000u)
+#define EDMA3_CCRL_IPR_I25_SHIFT   (0x00000019u)
+#define EDMA3_CCRL_IPR_I25_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPR_I24_MASK   (0x01000000u)
+#define EDMA3_CCRL_IPR_I24_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_IPR_I24_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPR_I23_MASK   (0x00800000u)
+#define EDMA3_CCRL_IPR_I23_SHIFT   (0x00000017u)
+#define EDMA3_CCRL_IPR_I23_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPR_I22_MASK   (0x00400000u)
+#define EDMA3_CCRL_IPR_I22_SHIFT   (0x00000016u)
+#define EDMA3_CCRL_IPR_I22_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPR_I21_MASK   (0x00200000u)
+#define EDMA3_CCRL_IPR_I21_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_IPR_I21_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPR_I20_MASK   (0x00100000u)
+#define EDMA3_CCRL_IPR_I20_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_IPR_I20_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPR_I19_MASK   (0x00080000u)
+#define EDMA3_CCRL_IPR_I19_SHIFT   (0x00000013u)
+#define EDMA3_CCRL_IPR_I19_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPR_I18_MASK   (0x00040000u)
+#define EDMA3_CCRL_IPR_I18_SHIFT   (0x00000012u)
+#define EDMA3_CCRL_IPR_I18_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPR_I17_MASK   (0x00020000u)
+#define EDMA3_CCRL_IPR_I17_SHIFT   (0x00000011u)
+#define EDMA3_CCRL_IPR_I17_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPR_I16_MASK   (0x00010000u)
+#define EDMA3_CCRL_IPR_I16_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_IPR_I16_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPR_I15_MASK   (0x00008000u)
+#define EDMA3_CCRL_IPR_I15_SHIFT   (0x0000000Fu)
+#define EDMA3_CCRL_IPR_I15_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPR_I14_MASK   (0x00004000u)
+#define EDMA3_CCRL_IPR_I14_SHIFT   (0x0000000Eu)
+#define EDMA3_CCRL_IPR_I14_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPR_I13_MASK   (0x00002000u)
+#define EDMA3_CCRL_IPR_I13_SHIFT   (0x0000000Du)
+#define EDMA3_CCRL_IPR_I13_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPR_I12_MASK   (0x00001000u)
+#define EDMA3_CCRL_IPR_I12_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_IPR_I12_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPR_I11_MASK   (0x00000800u)
+#define EDMA3_CCRL_IPR_I11_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_IPR_I11_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPR_I10_MASK   (0x00000400u)
+#define EDMA3_CCRL_IPR_I10_SHIFT   (0x0000000Au)
+#define EDMA3_CCRL_IPR_I10_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPR_I9_MASK   (0x00000200u)
+#define EDMA3_CCRL_IPR_I9_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_IPR_I9_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPR_I8_MASK   (0x00000100u)
+#define EDMA3_CCRL_IPR_I8_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_IPR_I8_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPR_I7_MASK   (0x00000080u)
+#define EDMA3_CCRL_IPR_I7_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_IPR_I7_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPR_I6_MASK   (0x00000040u)
+#define EDMA3_CCRL_IPR_I6_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_IPR_I6_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPR_I5_MASK   (0x00000020u)
+#define EDMA3_CCRL_IPR_I5_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_IPR_I5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPR_I4_MASK   (0x00000010u)
+#define EDMA3_CCRL_IPR_I4_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_IPR_I4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPR_I3_MASK   (0x00000008u)
+#define EDMA3_CCRL_IPR_I3_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_IPR_I3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPR_I2_MASK   (0x00000004u)
+#define EDMA3_CCRL_IPR_I2_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_IPR_I2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPR_I1_MASK   (0x00000002u)
+#define EDMA3_CCRL_IPR_I1_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_IPR_I1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPR_I0_MASK   (0x00000001u)
+#define EDMA3_CCRL_IPR_I0_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_IPR_I0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPRH_I63_MASK   (0x80000000u)
+#define EDMA3_CCRL_IPRH_I63_SHIFT   (0x0000001Fu)
+#define EDMA3_CCRL_IPRH_I63_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPRH_I62_MASK   (0x40000000u)
+#define EDMA3_CCRL_IPRH_I62_SHIFT   (0x0000001Eu)
+#define EDMA3_CCRL_IPRH_I62_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPRH_I61_MASK   (0x20000000u)
+#define EDMA3_CCRL_IPRH_I61_SHIFT   (0x0000001Du)
+#define EDMA3_CCRL_IPRH_I61_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPRH_I60_MASK   (0x10000000u)
+#define EDMA3_CCRL_IPRH_I60_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_IPRH_I60_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPRH_I59_MASK   (0x08000000u)
+#define EDMA3_CCRL_IPRH_I59_SHIFT   (0x0000001Bu)
+#define EDMA3_CCRL_IPRH_I59_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPRH_I58_MASK   (0x04000000u)
+#define EDMA3_CCRL_IPRH_I58_SHIFT   (0x0000001Au)
+#define EDMA3_CCRL_IPRH_I58_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPRH_I57_MASK   (0x02000000u)
+#define EDMA3_CCRL_IPRH_I57_SHIFT   (0x00000019u)
+#define EDMA3_CCRL_IPRH_I57_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPRH_I56_MASK   (0x01000000u)
+#define EDMA3_CCRL_IPRH_I56_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_IPRH_I56_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPRH_I55_MASK   (0x00800000u)
+#define EDMA3_CCRL_IPRH_I55_SHIFT   (0x00000017u)
+#define EDMA3_CCRL_IPRH_I55_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPRH_I54_MASK   (0x00400000u)
+#define EDMA3_CCRL_IPRH_I54_SHIFT   (0x00000016u)
+#define EDMA3_CCRL_IPRH_I54_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPRH_I53_MASK   (0x00200000u)
+#define EDMA3_CCRL_IPRH_I53_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_IPRH_I53_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPRH_I52_MASK   (0x00100000u)
+#define EDMA3_CCRL_IPRH_I52_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_IPRH_I52_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPRH_I51_MASK   (0x00080000u)
+#define EDMA3_CCRL_IPRH_I51_SHIFT   (0x00000013u)
+#define EDMA3_CCRL_IPRH_I51_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPRH_I50_MASK   (0x00040000u)
+#define EDMA3_CCRL_IPRH_I50_SHIFT   (0x00000012u)
+#define EDMA3_CCRL_IPRH_I50_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPRH_I49_MASK   (0x00020000u)
+#define EDMA3_CCRL_IPRH_I49_SHIFT   (0x00000011u)
+#define EDMA3_CCRL_IPRH_I49_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPRH_I48_MASK   (0x00010000u)
+#define EDMA3_CCRL_IPRH_I48_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_IPRH_I48_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPRH_I47_MASK   (0x00008000u)
+#define EDMA3_CCRL_IPRH_I47_SHIFT   (0x0000000Fu)
+#define EDMA3_CCRL_IPRH_I47_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPRH_I46_MASK   (0x00004000u)
+#define EDMA3_CCRL_IPRH_I46_SHIFT   (0x0000000Eu)
+#define EDMA3_CCRL_IPRH_I46_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPRH_I45_MASK   (0x00002000u)
+#define EDMA3_CCRL_IPRH_I45_SHIFT   (0x0000000Du)
+#define EDMA3_CCRL_IPRH_I45_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPRH_I44_MASK   (0x00001000u)
+#define EDMA3_CCRL_IPRH_I44_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_IPRH_I44_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPRH_I43_MASK   (0x00000800u)
+#define EDMA3_CCRL_IPRH_I43_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_IPRH_I43_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPRH_I42_MASK   (0x00000400u)
+#define EDMA3_CCRL_IPRH_I42_SHIFT   (0x0000000Au)
+#define EDMA3_CCRL_IPRH_I42_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPRH_I41_MASK   (0x00000200u)
+#define EDMA3_CCRL_IPRH_I41_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_IPRH_I41_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPRH_I40_MASK   (0x00000100u)
+#define EDMA3_CCRL_IPRH_I40_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_IPRH_I40_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPRH_I39_MASK   (0x00000080u)
+#define EDMA3_CCRL_IPRH_I39_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_IPRH_I39_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPRH_I38_MASK   (0x00000040u)
+#define EDMA3_CCRL_IPRH_I38_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_IPRH_I38_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPRH_I37_MASK   (0x00000020u)
+#define EDMA3_CCRL_IPRH_I37_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_IPRH_I37_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPRH_I36_MASK   (0x00000010u)
+#define EDMA3_CCRL_IPRH_I36_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_IPRH_I36_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPRH_I35_MASK   (0x00000008u)
+#define EDMA3_CCRL_IPRH_I35_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_IPRH_I35_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPRH_I34_MASK   (0x00000004u)
+#define EDMA3_CCRL_IPRH_I34_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_IPRH_I34_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPRH_I33_MASK   (0x00000002u)
+#define EDMA3_CCRL_IPRH_I33_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_IPRH_I33_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPRH_I32_MASK   (0x00000001u)
+#define EDMA3_CCRL_IPRH_I32_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_IPRH_I32_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPRH_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICR_I31_MASK   (0x80000000u)
+#define EDMA3_CCRL_ICR_I31_SHIFT   (0x0000001Fu)
+#define EDMA3_CCRL_ICR_I31_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICR_I31_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICR_I30_MASK   (0x40000000u)
+#define EDMA3_CCRL_ICR_I30_SHIFT   (0x0000001Eu)
+#define EDMA3_CCRL_ICR_I30_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICR_I30_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICR_I29_MASK   (0x20000000u)
+#define EDMA3_CCRL_ICR_I29_SHIFT   (0x0000001Du)
+#define EDMA3_CCRL_ICR_I29_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICR_I29_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICR_I28_MASK   (0x10000000u)
+#define EDMA3_CCRL_ICR_I28_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_ICR_I28_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICR_I28_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICR_I27_MASK   (0x08000000u)
+#define EDMA3_CCRL_ICR_I27_SHIFT   (0x0000001Bu)
+#define EDMA3_CCRL_ICR_I27_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICR_I27_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICR_I26_MASK   (0x04000000u)
+#define EDMA3_CCRL_ICR_I26_SHIFT   (0x0000001Au)
+#define EDMA3_CCRL_ICR_I26_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICR_I26_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICR_I25_MASK   (0x02000000u)
+#define EDMA3_CCRL_ICR_I25_SHIFT   (0x00000019u)
+#define EDMA3_CCRL_ICR_I25_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICR_I25_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICR_I24_MASK   (0x01000000u)
+#define EDMA3_CCRL_ICR_I24_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_ICR_I24_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICR_I24_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICR_I23_MASK   (0x00800000u)
+#define EDMA3_CCRL_ICR_I23_SHIFT   (0x00000017u)
+#define EDMA3_CCRL_ICR_I23_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICR_I23_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICR_I22_MASK   (0x00400000u)
+#define EDMA3_CCRL_ICR_I22_SHIFT   (0x00000016u)
+#define EDMA3_CCRL_ICR_I22_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICR_I22_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICR_I21_MASK   (0x00200000u)
+#define EDMA3_CCRL_ICR_I21_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_ICR_I21_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICR_I21_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICR_I20_MASK   (0x00100000u)
+#define EDMA3_CCRL_ICR_I20_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_ICR_I20_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICR_I20_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICR_I19_MASK   (0x00080000u)
+#define EDMA3_CCRL_ICR_I19_SHIFT   (0x00000013u)
+#define EDMA3_CCRL_ICR_I19_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICR_I19_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICR_I18_MASK   (0x00040000u)
+#define EDMA3_CCRL_ICR_I18_SHIFT   (0x00000012u)
+#define EDMA3_CCRL_ICR_I18_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICR_I18_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICR_I17_MASK   (0x00020000u)
+#define EDMA3_CCRL_ICR_I17_SHIFT   (0x00000011u)
+#define EDMA3_CCRL_ICR_I17_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICR_I17_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICR_I16_MASK   (0x00010000u)
+#define EDMA3_CCRL_ICR_I16_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_ICR_I16_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICR_I16_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICR_I15_MASK   (0x00008000u)
+#define EDMA3_CCRL_ICR_I15_SHIFT   (0x0000000Fu)
+#define EDMA3_CCRL_ICR_I15_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICR_I15_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICR_I14_MASK   (0x00004000u)
+#define EDMA3_CCRL_ICR_I14_SHIFT   (0x0000000Eu)
+#define EDMA3_CCRL_ICR_I14_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICR_I14_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICR_I13_MASK   (0x00002000u)
+#define EDMA3_CCRL_ICR_I13_SHIFT   (0x0000000Du)
+#define EDMA3_CCRL_ICR_I13_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICR_I13_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICR_I12_MASK   (0x00001000u)
+#define EDMA3_CCRL_ICR_I12_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_ICR_I12_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICR_I12_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICR_I11_MASK   (0x00000800u)
+#define EDMA3_CCRL_ICR_I11_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_ICR_I11_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICR_I11_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICR_I10_MASK   (0x00000400u)
+#define EDMA3_CCRL_ICR_I10_SHIFT   (0x0000000Au)
+#define EDMA3_CCRL_ICR_I10_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICR_I10_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICR_I9_MASK   (0x00000200u)
+#define EDMA3_CCRL_ICR_I9_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_ICR_I9_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICR_I9_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICR_I8_MASK   (0x00000100u)
+#define EDMA3_CCRL_ICR_I8_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_ICR_I8_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICR_I8_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICR_I7_MASK   (0x00000080u)
+#define EDMA3_CCRL_ICR_I7_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_ICR_I7_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICR_I7_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICR_I6_MASK   (0x00000040u)
+#define EDMA3_CCRL_ICR_I6_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_ICR_I6_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICR_I6_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICR_I5_MASK   (0x00000020u)
+#define EDMA3_CCRL_ICR_I5_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_ICR_I5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICR_I5_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICR_I4_MASK   (0x00000010u)
+#define EDMA3_CCRL_ICR_I4_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_ICR_I4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICR_I4_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICR_I3_MASK   (0x00000008u)
+#define EDMA3_CCRL_ICR_I3_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_ICR_I3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICR_I3_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICR_I2_MASK   (0x00000004u)
+#define EDMA3_CCRL_ICR_I2_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_ICR_I2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICR_I2_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICR_I1_MASK   (0x00000002u)
+#define EDMA3_CCRL_ICR_I1_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_ICR_I1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICR_I1_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICR_I0_MASK   (0x00000001u)
+#define EDMA3_CCRL_ICR_I0_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_ICR_I0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICR_I0_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICRH_I63_MASK   (0x80000000u)
+#define EDMA3_CCRL_ICRH_I63_SHIFT   (0x0000001Fu)
+#define EDMA3_CCRL_ICRH_I63_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICRH_I63_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICRH_I62_MASK   (0x40000000u)
+#define EDMA3_CCRL_ICRH_I62_SHIFT   (0x0000001Eu)
+#define EDMA3_CCRL_ICRH_I62_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICRH_I62_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICRH_I61_MASK   (0x20000000u)
+#define EDMA3_CCRL_ICRH_I61_SHIFT   (0x0000001Du)
+#define EDMA3_CCRL_ICRH_I61_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICRH_I61_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICRH_I60_MASK   (0x10000000u)
+#define EDMA3_CCRL_ICRH_I60_SHIFT   (0x0000001Cu)
+#define EDMA3_CCRL_ICRH_I60_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICRH_I60_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICRH_I59_MASK   (0x08000000u)
+#define EDMA3_CCRL_ICRH_I59_SHIFT   (0x0000001Bu)
+#define EDMA3_CCRL_ICRH_I59_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICRH_I59_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICRH_I58_MASK   (0x04000000u)
+#define EDMA3_CCRL_ICRH_I58_SHIFT   (0x0000001Au)
+#define EDMA3_CCRL_ICRH_I58_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICRH_I58_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICRH_I57_MASK   (0x02000000u)
+#define EDMA3_CCRL_ICRH_I57_SHIFT   (0x00000019u)
+#define EDMA3_CCRL_ICRH_I57_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICRH_I57_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICRH_I56_MASK   (0x01000000u)
+#define EDMA3_CCRL_ICRH_I56_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_ICRH_I56_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICRH_I56_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICRH_I55_MASK   (0x00800000u)
+#define EDMA3_CCRL_ICRH_I55_SHIFT   (0x00000017u)
+#define EDMA3_CCRL_ICRH_I55_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICRH_I55_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICRH_I54_MASK   (0x00400000u)
+#define EDMA3_CCRL_ICRH_I54_SHIFT   (0x00000016u)
+#define EDMA3_CCRL_ICRH_I54_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICRH_I54_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICRH_I53_MASK   (0x00200000u)
+#define EDMA3_CCRL_ICRH_I53_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_ICRH_I53_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICRH_I53_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICRH_I52_MASK   (0x00100000u)
+#define EDMA3_CCRL_ICRH_I52_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_ICRH_I52_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICRH_I52_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICRH_I51_MASK   (0x00080000u)
+#define EDMA3_CCRL_ICRH_I51_SHIFT   (0x00000013u)
+#define EDMA3_CCRL_ICRH_I51_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICRH_I51_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICRH_I50_MASK   (0x00040000u)
+#define EDMA3_CCRL_ICRH_I50_SHIFT   (0x00000012u)
+#define EDMA3_CCRL_ICRH_I50_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICRH_I50_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICRH_I49_MASK   (0x00020000u)
+#define EDMA3_CCRL_ICRH_I49_SHIFT   (0x00000011u)
+#define EDMA3_CCRL_ICRH_I49_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICRH_I49_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICRH_I48_MASK   (0x00010000u)
+#define EDMA3_CCRL_ICRH_I48_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_ICRH_I48_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICRH_I48_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICRH_I47_MASK   (0x00008000u)
+#define EDMA3_CCRL_ICRH_I47_SHIFT   (0x0000000Fu)
+#define EDMA3_CCRL_ICRH_I47_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICRH_I47_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICRH_I46_MASK   (0x00004000u)
+#define EDMA3_CCRL_ICRH_I46_SHIFT   (0x0000000Eu)
+#define EDMA3_CCRL_ICRH_I46_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICRH_I46_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICRH_I45_MASK   (0x00002000u)
+#define EDMA3_CCRL_ICRH_I45_SHIFT   (0x0000000Du)
+#define EDMA3_CCRL_ICRH_I45_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICRH_I45_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICRH_I44_MASK   (0x00001000u)
+#define EDMA3_CCRL_ICRH_I44_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_ICRH_I44_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICRH_I44_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICRH_I43_MASK   (0x00000800u)
+#define EDMA3_CCRL_ICRH_I43_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_ICRH_I43_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICRH_I43_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICRH_I42_MASK   (0x00000400u)
+#define EDMA3_CCRL_ICRH_I42_SHIFT   (0x0000000Au)
+#define EDMA3_CCRL_ICRH_I42_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICRH_I42_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICRH_I41_MASK   (0x00000200u)
+#define EDMA3_CCRL_ICRH_I41_SHIFT   (0x00000009u)
+#define EDMA3_CCRL_ICRH_I41_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICRH_I41_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICRH_I40_MASK   (0x00000100u)
+#define EDMA3_CCRL_ICRH_I40_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_ICRH_I40_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICRH_I40_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICRH_I39_MASK   (0x00000080u)
+#define EDMA3_CCRL_ICRH_I39_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_ICRH_I39_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICRH_I39_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICRH_I38_MASK   (0x00000040u)
+#define EDMA3_CCRL_ICRH_I38_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_ICRH_I38_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICRH_I38_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICRH_I37_MASK   (0x00000020u)
+#define EDMA3_CCRL_ICRH_I37_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_ICRH_I37_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICRH_I37_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICRH_I36_MASK   (0x00000010u)
+#define EDMA3_CCRL_ICRH_I36_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_ICRH_I36_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICRH_I36_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICRH_I35_MASK   (0x00000008u)
+#define EDMA3_CCRL_ICRH_I35_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_ICRH_I35_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICRH_I35_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICRH_I34_MASK   (0x00000004u)
+#define EDMA3_CCRL_ICRH_I34_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_ICRH_I34_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICRH_I34_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICRH_I33_MASK   (0x00000002u)
+#define EDMA3_CCRL_ICRH_I33_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_ICRH_I33_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICRH_I33_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICRH_I32_MASK   (0x00000001u)
+#define EDMA3_CCRL_ICRH_I32_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_ICRH_I32_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICRH_I32_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_ICRH_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IEVAL_SET_MASK   (0x00000002u)
+#define EDMA3_CCRL_IEVAL_SET_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_IEVAL_SET_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IEVAL_SET_SET   (0x00000001u)
+#define EDMA3_CCRL_IEVAL_EVAL_MASK   (0x00000001u)
+#define EDMA3_CCRL_IEVAL_EVAL_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_IEVAL_EVAL_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IEVAL_EVAL_EVAL   (0x00000001u)
+#define EDMA3_CCRL_IEVAL_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QER_E7_MASK   (0x00000080u)
+#define EDMA3_CCRL_QER_E7_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_QER_E7_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QER_E6_MASK   (0x00000040u)
+#define EDMA3_CCRL_QER_E6_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_QER_E6_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QER_E5_MASK   (0x00000020u)
+#define EDMA3_CCRL_QER_E5_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_QER_E5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QER_E4_MASK   (0x00000010u)
+#define EDMA3_CCRL_QER_E4_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_QER_E4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QER_E3_MASK   (0x00000008u)
+#define EDMA3_CCRL_QER_E3_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_QER_E3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QER_E2_MASK   (0x00000004u)
+#define EDMA3_CCRL_QER_E2_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_QER_E2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QER_E1_MASK   (0x00000002u)
+#define EDMA3_CCRL_QER_E1_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_QER_E1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QER_E0_MASK   (0x00000001u)
+#define EDMA3_CCRL_QER_E0_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_QER_E0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QER_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEER_E7_MASK   (0x00000080u)
+#define EDMA3_CCRL_QEER_E7_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_QEER_E7_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEER_E6_MASK   (0x00000040u)
+#define EDMA3_CCRL_QEER_E6_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_QEER_E6_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEER_E5_MASK   (0x00000020u)
+#define EDMA3_CCRL_QEER_E5_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_QEER_E5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEER_E4_MASK   (0x00000010u)
+#define EDMA3_CCRL_QEER_E4_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_QEER_E4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEER_E3_MASK   (0x00000008u)
+#define EDMA3_CCRL_QEER_E3_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_QEER_E3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEER_E2_MASK   (0x00000004u)
+#define EDMA3_CCRL_QEER_E2_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_QEER_E2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEER_E1_MASK   (0x00000002u)
+#define EDMA3_CCRL_QEER_E1_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_QEER_E1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEER_E0_MASK   (0x00000001u)
+#define EDMA3_CCRL_QEER_E0_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_QEER_E0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEER_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEECR_E7_MASK   (0x00000080u)
+#define EDMA3_CCRL_QEECR_E7_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_QEECR_E7_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEECR_E7_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_QEECR_E6_MASK   (0x00000040u)
+#define EDMA3_CCRL_QEECR_E6_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_QEECR_E6_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEECR_E6_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_QEECR_E5_MASK   (0x00000020u)
+#define EDMA3_CCRL_QEECR_E5_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_QEECR_E5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEECR_E5_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_QEECR_E4_MASK   (0x00000010u)
+#define EDMA3_CCRL_QEECR_E4_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_QEECR_E4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEECR_E4_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_QEECR_E3_MASK   (0x00000008u)
+#define EDMA3_CCRL_QEECR_E3_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_QEECR_E3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEECR_E3_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_QEECR_E2_MASK   (0x00000004u)
+#define EDMA3_CCRL_QEECR_E2_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_QEECR_E2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEECR_E2_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_QEECR_E1_MASK   (0x00000002u)
+#define EDMA3_CCRL_QEECR_E1_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_QEECR_E1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEECR_E1_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_QEECR_E0_MASK   (0x00000001u)
+#define EDMA3_CCRL_QEECR_E0_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_QEECR_E0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEECR_E0_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_QEECR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEESR_E7_MASK   (0x00000080u)
+#define EDMA3_CCRL_QEESR_E7_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_QEESR_E7_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEESR_E7_SET   (0x00000001u)
+#define EDMA3_CCRL_QEESR_E6_MASK   (0x00000040u)
+#define EDMA3_CCRL_QEESR_E6_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_QEESR_E6_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEESR_E6_SET   (0x00000001u)
+#define EDMA3_CCRL_QEESR_E5_MASK   (0x00000020u)
+#define EDMA3_CCRL_QEESR_E5_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_QEESR_E5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEESR_E5_SET   (0x00000001u)
+#define EDMA3_CCRL_QEESR_E4_MASK   (0x00000010u)
+#define EDMA3_CCRL_QEESR_E4_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_QEESR_E4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEESR_E4_SET   (0x00000001u)
+#define EDMA3_CCRL_QEESR_E3_MASK   (0x00000008u)
+#define EDMA3_CCRL_QEESR_E3_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_QEESR_E3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEESR_E3_SET   (0x00000001u)
+#define EDMA3_CCRL_QEESR_E2_MASK   (0x00000004u)
+#define EDMA3_CCRL_QEESR_E2_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_QEESR_E2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEESR_E2_SET   (0x00000001u)
+#define EDMA3_CCRL_QEESR_E1_MASK   (0x00000002u)
+#define EDMA3_CCRL_QEESR_E1_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_QEESR_E1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEESR_E1_SET   (0x00000001u)
+#define EDMA3_CCRL_QEESR_E0_MASK   (0x00000001u)
+#define EDMA3_CCRL_QEESR_E0_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_QEESR_E0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEESR_E0_SET   (0x00000001u)
+#define EDMA3_CCRL_QEESR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QSER_E7_MASK   (0x00000080u)
+#define EDMA3_CCRL_QSER_E7_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_QSER_E7_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QSER_E6_MASK   (0x00000040u)
+#define EDMA3_CCRL_QSER_E6_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_QSER_E6_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QSER_E5_MASK   (0x00000020u)
+#define EDMA3_CCRL_QSER_E5_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_QSER_E5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QSER_E4_MASK   (0x00000010u)
+#define EDMA3_CCRL_QSER_E4_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_QSER_E4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QSER_E3_MASK   (0x00000008u)
+#define EDMA3_CCRL_QSER_E3_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_QSER_E3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QSER_E2_MASK   (0x00000004u)
+#define EDMA3_CCRL_QSER_E2_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_QSER_E2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QSER_E1_MASK   (0x00000002u)
+#define EDMA3_CCRL_QSER_E1_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_QSER_E1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QSER_E0_MASK   (0x00000001u)
+#define EDMA3_CCRL_QSER_E0_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_QSER_E0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QSER_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QSECR_E7_MASK   (0x00000080u)
+#define EDMA3_CCRL_QSECR_E7_SHIFT   (0x00000007u)
+#define EDMA3_CCRL_QSECR_E7_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QSECR_E7_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_QSECR_E6_MASK   (0x00000040u)
+#define EDMA3_CCRL_QSECR_E6_SHIFT   (0x00000006u)
+#define EDMA3_CCRL_QSECR_E6_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QSECR_E6_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_QSECR_E5_MASK   (0x00000020u)
+#define EDMA3_CCRL_QSECR_E5_SHIFT   (0x00000005u)
+#define EDMA3_CCRL_QSECR_E5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QSECR_E5_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_QSECR_E4_MASK   (0x00000010u)
+#define EDMA3_CCRL_QSECR_E4_SHIFT   (0x00000004u)
+#define EDMA3_CCRL_QSECR_E4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QSECR_E4_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_QSECR_E3_MASK   (0x00000008u)
+#define EDMA3_CCRL_QSECR_E3_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_QSECR_E3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QSECR_E3_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_QSECR_E2_MASK   (0x00000004u)
+#define EDMA3_CCRL_QSECR_E2_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_QSECR_E2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QSECR_E2_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_QSECR_E1_MASK   (0x00000002u)
+#define EDMA3_CCRL_QSECR_E1_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_QSECR_E1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QSECR_E1_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_QSECR_E0_MASK   (0x00000001u)
+#define EDMA3_CCRL_QSECR_E0_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_QSECR_E0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QSECR_E0_CLEAR   (0x00000001u)
+#define EDMA3_CCRL_QSECR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_OPT_PRIV_MASK   (0x80000000u)
+#define EDMA3_CCRL_OPT_PRIV_SHIFT   (0x0000001Fu)
+#define EDMA3_CCRL_OPT_PRIV_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_OPT_PRIV_USER   (0x00000000u)
+#define EDMA3_CCRL_OPT_PRIV_SUPERVISOR   (0x00000001u)
+#define EDMA3_CCRL_OPT_SECURE_MASK   (0x40000000u)
+#define EDMA3_CCRL_OPT_SECURE_SHIFT   (0x0000001Eu)
+#define EDMA3_CCRL_OPT_SECURE_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_OPT_SECURE_SECURE   (0x00000000u)
+#define EDMA3_CCRL_OPT_SECURE_NONSECURE   (0x00000001u)
+#define EDMA3_CCRL_OPT_PRIVID_MASK   (0x0F000000u)
+#define EDMA3_CCRL_OPT_PRIVID_SHIFT   (0x00000018u)
+#define EDMA3_CCRL_OPT_PRIVID_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_OPT_ITCCHEN_MASK   (0x00800000u)
+#define EDMA3_CCRL_OPT_ITCCHEN_SHIFT   (0x00000017u)
+#define EDMA3_CCRL_OPT_ITCCHEN_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_OPT_ITCCHEN_DISABLE   (0x00000000u)
+#define EDMA3_CCRL_OPT_ITCCHEN_ENABLE   (0x00000001u)
+#define EDMA3_CCRL_OPT_TCCHEN_MASK   (0x00400000u)
+#define EDMA3_CCRL_OPT_TCCHEN_SHIFT   (0x00000016u)
+#define EDMA3_CCRL_OPT_TCCHEN_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_OPT_TCCHEN_DISABLE   (0x00000000u)
+#define EDMA3_CCRL_OPT_TCCHEN_ENABLE   (0x00000001u)
+#define EDMA3_CCRL_OPT_ITCINTEN_MASK   (0x00200000u)
+#define EDMA3_CCRL_OPT_ITCINTEN_SHIFT   (0x00000015u)
+#define EDMA3_CCRL_OPT_ITCINTEN_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_OPT_ITCINTEN_DISABLE   (0x00000000u)
+#define EDMA3_CCRL_OPT_ITCINTEN_ENABLE   (0x00000001u)
+#define EDMA3_CCRL_OPT_TCINTEN_MASK   (0x00100000u)
+#define EDMA3_CCRL_OPT_TCINTEN_SHIFT   (0x00000014u)
+#define EDMA3_CCRL_OPT_TCINTEN_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_OPT_TCINTEN_DISABLE   (0x00000000u)
+#define EDMA3_CCRL_OPT_TCINTEN_ENABLE   (0x00000001u)
+#define EDMA3_CCRL_OPT_WIMODE_MASK   (0x00080000u)
+#define EDMA3_CCRL_OPT_WIMODE_SHIFT   (0x00000013u)
+#define EDMA3_CCRL_OPT_WIMODE_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_OPT_WIMODE_NORMAL   (0x00000000u)
+#define EDMA3_CCRL_OPT_WIMODE_WI   (0x00000001u)
+#define EDMA3_CCRL_OPT_TCC_MASK   (0x0003F000u)
+#define EDMA3_CCRL_OPT_TCC_SHIFT   (0x0000000Cu)
+#define EDMA3_CCRL_OPT_TCC_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_OPT_TCCMODE_MASK   (0x00000800u)
+#define EDMA3_CCRL_OPT_TCCMODE_SHIFT   (0x0000000Bu)
+#define EDMA3_CCRL_OPT_TCCMODE_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_OPT_TCCMODE_NORMAL   (0x00000000u)
+#define EDMA3_CCRL_OPT_TCCMODE_EARLY   (0x00000001u)
+#define EDMA3_CCRL_OPT_FWID_MASK   (0x00000700u)
+#define EDMA3_CCRL_OPT_FWID_SHIFT   (0x00000008u)
+#define EDMA3_CCRL_OPT_FWID_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_OPT_FWID_8   (0x00000000u)
+#define EDMA3_CCRL_OPT_FWID_16   (0x00000001u)
+#define EDMA3_CCRL_OPT_FWID_32   (0x00000002u)
+#define EDMA3_CCRL_OPT_FWID_64   (0x00000003u)
+#define EDMA3_CCRL_OPT_FWID_128   (0x00000004u)
+#define EDMA3_CCRL_OPT_FWID_256   (0x00000005u)
+#define EDMA3_CCRL_OPT_STATIC_MASK   (0x00000008u)
+#define EDMA3_CCRL_OPT_STATIC_SHIFT   (0x00000003u)
+#define EDMA3_CCRL_OPT_STATIC_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_OPT_STATIC_NORMAL   (0x00000000u)
+#define EDMA3_CCRL_OPT_STATIC_STATIC   (0x00000001u)
+#define EDMA3_CCRL_OPT_SYNCDIM_MASK   (0x00000004u)
+#define EDMA3_CCRL_OPT_SYNCDIM_SHIFT   (0x00000002u)
+#define EDMA3_CCRL_OPT_SYNCDIM_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_OPT_SYNCDIM_ASYNC   (0x00000000u)
+#define EDMA3_CCRL_OPT_SYNCDIM_ABSYNC   (0x00000001u)
+#define EDMA3_CCRL_OPT_DAM_MASK   (0x00000002u)
+#define EDMA3_CCRL_OPT_DAM_SHIFT   (0x00000001u)
+#define EDMA3_CCRL_OPT_DAM_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_OPT_DAM_INCR   (0x00000000u)
+#define EDMA3_CCRL_OPT_DAM_FIFO   (0x00000001u)
+#define EDMA3_CCRL_OPT_SAM_MASK   (0x00000001u)
+#define EDMA3_CCRL_OPT_SAM_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_OPT_SAM_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_OPT_SAM_INCR   (0x00000000u)
+#define EDMA3_CCRL_OPT_SAM_FIFO   (0x00000001u)
+#define EDMA3_CCRL_OPT_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SRC_SRC_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_SRC_SRC_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_SRC_SRC_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SRC_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_A_B_CNT_BCNT_MASK   (0xFFFF0000u)
+#define EDMA3_CCRL_A_B_CNT_BCNT_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_A_B_CNT_BCNT_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_A_B_CNT_ACNT_MASK   (0x0000FFFFu)
+#define EDMA3_CCRL_A_B_CNT_ACNT_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_A_B_CNT_ACNT_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_A_B_CNT_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DST_DST_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_DST_DST_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_DST_DST_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DST_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SRC_DST_BIDX_DSTBIDX_MASK   (0xFFFF0000u)
+#define EDMA3_CCRL_SRC_DST_BIDX_DSTBIDX_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_SRC_DST_BIDX_DSTBIDX_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SRC_DST_BIDX_SRCBIDX_MASK   (0x0000FFFFu)
+#define EDMA3_CCRL_SRC_DST_BIDX_SRCBIDX_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_SRC_DST_BIDX_SRCBIDX_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SRC_DST_BIDX_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_LINK_BCNTRLD_BCNTRLD_MASK   (0xFFFF0000u)
+#define EDMA3_CCRL_LINK_BCNTRLD_BCNTRLD_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_LINK_BCNTRLD_BCNTRLD_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_LINK_BCNTRLD_LINK_MASK   (0x0000FFFFu)
+#define EDMA3_CCRL_LINK_BCNTRLD_LINK_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_LINK_BCNTRLD_LINK_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_LINK_BCNTRLD_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SRC_DST_CIDX_DSTCIDX_MASK   (0xFFFF0000u)
+#define EDMA3_CCRL_SRC_DST_CIDX_DSTCIDX_SHIFT   (0x00000010u)
+#define EDMA3_CCRL_SRC_DST_CIDX_DSTCIDX_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SRC_DST_CIDX_SRCCIDX_MASK   (0x0000FFFFu)
+#define EDMA3_CCRL_SRC_DST_CIDX_SRCCIDX_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_SRC_DST_CIDX_SRCCIDX_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SRC_DST_CIDX_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCNT_CCNT_MASK   (0x0000FFFFu)
+#define EDMA3_CCRL_CCNT_CCNT_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_CCNT_CCNT_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CCNT_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ER_REG_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_ER_REG_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_ER_REG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ER_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ERH_REG_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_ERH_REG_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_ERH_REG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ERH_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECR_REG_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_ECR_REG_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_ECR_REG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECRH_REG_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_ECRH_REG_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_ECRH_REG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ECRH_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESR_REG_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_ESR_REG_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_ESR_REG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESRH_REG_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_ESRH_REG_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_ESRH_REG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ESRH_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CER_REG_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_CER_REG_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_CER_REG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CER_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CERH_REG_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_CERH_REG_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_CERH_REG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_CERH_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EER_REG_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_EER_REG_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_EER_REG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EER_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EERH_REG_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_EERH_REG_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_EERH_REG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EERH_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECR_REG_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_EECR_REG_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_EECR_REG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECRH_REG_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_EECRH_REG_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_EECRH_REG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EECRH_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESR_REG_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_EESR_REG_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_EESR_REG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESRH_REG_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_EESRH_REG_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_EESRH_REG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EESRH_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SER_REG_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_SER_REG_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_SER_REG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SER_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SERH_REG_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_SERH_REG_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_SERH_REG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SERH_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECR_REG_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_SECR_REG_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_SECR_REG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECRH_REG_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_SECRH_REG_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_SECRH_REG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_SECRH_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IER_REG_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_IER_REG_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_IER_REG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IER_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IERH_REG_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_IERH_REG_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_IERH_REG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IERH_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECR_REG_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_IECR_REG_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_IECR_REG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECRH_REG_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_IECRH_REG_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_IECRH_REG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IECRH_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESR_REG_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_IESR_REG_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_IESR_REG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESRH_REG_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_IESRH_REG_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_IESRH_REG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IESRH_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPR_REG_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_IPR_REG_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_IPR_REG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPRH_REG_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_IPRH_REG_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_IPRH_REG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IPRH_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICR_REG_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_ICR_REG_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_ICR_REG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICRH_REG_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_ICRH_REG_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_ICRH_REG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_ICRH_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IEVAL_REG_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_IEVAL_REG_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_IEVAL_REG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_IEVAL_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QER_REG_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_QER_REG_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_QER_REG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QER_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEER_REG_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_QEER_REG_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_QEER_REG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEER_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEECR_REG_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_QEECR_REG_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_QEECR_REG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEECR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEESR_REG_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_QEESR_REG_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_QEESR_REG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QEESR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QSER_REG_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_QSER_REG_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_QSER_REG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QSER_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QSECR_REG_MASK   (0xFFFFFFFFu)
+#define EDMA3_CCRL_QSECR_REG_SHIFT   (0x00000000u)
+#define EDMA3_CCRL_QSECR_REG_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_QSECR_RESETVAL   (0x00000000u)

Typedefs

+typedef volatile
+EDMA3_CCRL_ShadowRegs * 		EDMA3_CCRL_ShadowRegsOvly
+typedef volatile
+EDMA3_CCRL_ParamentryRegs * 		EDMA3_CCRL_ParamentryRegsOvly
+typedef volatile EDMA3_CCRL_Regs * EDMA3_CCRL_RegsOvly
+

Detailed Description

+EDMA3 Channel Controller Register Desciption. +

+This file contains the register layer for the EDMA3 Channel Controller.

+(C) Copyright 2006, Texas Instruments, Inc

+

Version:
1.0 Anuj Aggarwal - Created
+
+
Generated on Thu Oct 16 16:22:26 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/edma3__rl__tc_8h-source.html b/packages/ti/sdo/edma3/rm/docs/html/edma3__rl__tc_8h-source.html new file mode 100644 index 0000000..91809c2 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/edma3__rl__tc_8h-source.html @@ -0,0 +1,816 @@ + + +EDMA3 Resource Manager: edma3_rl_tc.h Source File + + + + + +
Generated on Thu Oct 16 16:21:27 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/edma3__rl__tc_8h.html b/packages/ti/sdo/edma3/rm/docs/html/edma3__rl__tc_8h.html new file mode 100644 index 0000000..1541823 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/edma3__rl__tc_8h.html @@ -0,0 +1,1252 @@ + + +EDMA3 Resource Manager: edma3_rl_tc.h File Reference + + + + + +
+

edma3_rl_tc.h File Reference

EDMA3 Transfer Controller Register Desciption. More... +

+ +

+Go to the source code of this file. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Data Structures

struct  EDMA3_TCRL_DfiregRegs
struct  EDMA3_TCRL_Regs

Defines

+#define EDMA3_TCRL_REV_TYPE_MASK   (0x00FF0000u)
+#define EDMA3_TCRL_REV_TYPE_SHIFT   (0x00000010u)
+#define EDMA3_TCRL_REV_TYPE_RESETVAL   (0x00000006u)
+#define EDMA3_TCRL_REV_CLASS_MASK   (0x0000FF00u)
+#define EDMA3_TCRL_REV_CLASS_SHIFT   (0x00000008u)
+#define EDMA3_TCRL_REV_CLASS_RESETVAL   (0x00000004u)
+#define EDMA3_TCRL_REV_REV_MASK   (0x000000FFu)
+#define EDMA3_TCRL_REV_REV_SHIFT   (0x00000000u)
+#define EDMA3_TCRL_REV_REV_RESETVAL   (0x00000001u)
+#define EDMA3_TCRL_REV_RESETVAL   (0x00060401u)
+#define EDMA3_TCRL_TCCFG_DREGDEPTH_MASK   (0x00000300u)
+#define EDMA3_TCRL_TCCFG_DREGDEPTH_SHIFT   (0x00000008u)
+#define EDMA3_TCRL_TCCFG_DREGDEPTH_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_TCCFG_DREGDEPTH_1ENTRY   (0x00000000u)
+#define EDMA3_TCRL_TCCFG_DREGDEPTH_2ENTRY   (0x00000001u)
+#define EDMA3_TCRL_TCCFG_DREGDEPTH_4ENTRY   (0x00000002u)
+#define EDMA3_TCRL_TCCFG_BUSWIDTH_MASK   (0x00000030u)
+#define EDMA3_TCRL_TCCFG_BUSWIDTH_SHIFT   (0x00000004u)
+#define EDMA3_TCRL_TCCFG_BUSWIDTH_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_TCCFG_BUSWIDTH_32BIT   (0x00000000u)
+#define EDMA3_TCRL_TCCFG_BUSWIDTH_64BIY   (0x00000001u)
+#define EDMA3_TCRL_TCCFG_BUSWIDTH_128BIT   (0x00000002u)
+#define EDMA3_TCRL_TCCFG_FIFOSIZE_MASK   (0x00000007u)
+#define EDMA3_TCRL_TCCFG_FIFOSIZE_SHIFT   (0x00000000u)
+#define EDMA3_TCRL_TCCFG_FIFOSIZE_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_TCCFG_FIFOSIZE_32BYTE   (0x00000000u)
+#define EDMA3_TCRL_TCCFG_FIFOSIZE_64BYTE   (0x00000001u)
+#define EDMA3_TCRL_TCCFG_FIFOSIZE_128BYTE   (0x00000002u)
+#define EDMA3_TCRL_TCCFG_FIFOSIZE_256BYTE   (0x00000003u)
+#define EDMA3_TCRL_TCCFG_FIFOSIZE_512BYTE   (0x00000004u)
+#define EDMA3_TCRL_TCCFG_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_TCSTAT_DFSTRT_MASK   (0x00003000u)
+#define EDMA3_TCRL_TCSTAT_DFSTRT_SHIFT   (0x0000000Cu)
+#define EDMA3_TCRL_TCSTAT_DFSTRT_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_TCSTAT_ATCV_MASK   (0x00000100u)
+#define EDMA3_TCRL_TCSTAT_ATCV_SHIFT   (0x00000008u)
+#define EDMA3_TCRL_TCSTAT_ATCV_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_TCSTAT_ATCV_IDLE   (0x00000000u)
+#define EDMA3_TCRL_TCSTAT_ATCV_BUSY   (0x00000001u)
+#define EDMA3_TCRL_TCSTAT_DSTACT_MASK   (0x00000070u)
+#define EDMA3_TCRL_TCSTAT_DSTACT_SHIFT   (0x00000004u)
+#define EDMA3_TCRL_TCSTAT_DSTACT_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_TCSTAT_DSTACT_EMPTY   (0x00000000u)
+#define EDMA3_TCRL_TCSTAT_DSTACT_1TR   (0x00000001u)
+#define EDMA3_TCRL_TCSTAT_DSTACT_2TR   (0x00000002u)
+#define EDMA3_TCRL_TCSTAT_DSTACT_3TR   (0x00000003u)
+#define EDMA3_TCRL_TCSTAT_DSTACT_4TR   (0x00000004u)
+#define EDMA3_TCRL_TCSTAT_WSACTV_MASK   (0x00000004u)
+#define EDMA3_TCRL_TCSTAT_WSACTV_SHIFT   (0x00000002u)
+#define EDMA3_TCRL_TCSTAT_WSACTV_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_TCSTAT_WSACTV_NONE   (0x00000000u)
+#define EDMA3_TCRL_TCSTAT_WSACTV_PEND   (0x00000001u)
+#define EDMA3_TCRL_TCSTAT_SRCACTV_MASK   (0x00000002u)
+#define EDMA3_TCRL_TCSTAT_SRCACTV_SHIFT   (0x00000001u)
+#define EDMA3_TCRL_TCSTAT_SRCACTV_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_TCSTAT_SRCACTV_IDLE   (0x00000000u)
+#define EDMA3_TCRL_TCSTAT_SRCACTV_BUSY   (0x00000001u)
+#define EDMA3_TCRL_TCSTAT_PROGBUSY_MASK   (0x00000001u)
+#define EDMA3_TCRL_TCSTAT_PROGBUSY_SHIFT   (0x00000000u)
+#define EDMA3_TCRL_TCSTAT_PROGBUSY_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_TCSTAT_PROGBUSY_IDLE   (0x00000000u)
+#define EDMA3_TCRL_TCSTAT_PROGBUSY_BUSY   (0x00000001u)
+#define EDMA3_TCRL_TCSTAT_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_INTSTAT_TRDONE_MASK   (0x00000002u)
+#define EDMA3_TCRL_INTSTAT_TRDONE_SHIFT   (0x00000001u)
+#define EDMA3_TCRL_INTSTAT_TRDONE_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_INTSTAT_TRDONE_NONE   (0x00000000u)
+#define EDMA3_TCRL_INTSTAT_TRDONE_DONE   (0x00000001u)
+#define EDMA3_TCRL_INTSTAT_PROGEMPTY_MASK   (0x00000001u)
+#define EDMA3_TCRL_INTSTAT_PROGEMPTY_SHIFT   (0x00000000u)
+#define EDMA3_TCRL_INTSTAT_PROGEMPTY_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_INTSTAT_PROGEMPTY_NONE   (0x00000000u)
+#define EDMA3_TCRL_INTSTAT_PROGEMPTY_EMPTY   (0x00000001u)
+#define EDMA3_TCRL_INTSTAT_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_INTEN_TRDONE_MASK   (0x00000002u)
+#define EDMA3_TCRL_INTEN_TRDONE_SHIFT   (0x00000001u)
+#define EDMA3_TCRL_INTEN_TRDONE_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_INTEN_TRDONE_DISABLE   (0x00000000u)
+#define EDMA3_TCRL_INTEN_TRDONE_ENABLE   (0x00000001u)
+#define EDMA3_TCRL_INTEN_PROGEMPTY_MASK   (0x00000001u)
+#define EDMA3_TCRL_INTEN_PROGEMPTY_SHIFT   (0x00000000u)
+#define EDMA3_TCRL_INTEN_PROGEMPTY_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_INTEN_PROGEMPTY_DISABLE   (0x00000000u)
+#define EDMA3_TCRL_INTEN_PROGEMPTY_ENABLE   (0x00000001u)
+#define EDMA3_TCRL_INTEN_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_INTCLR_TRDONE_MASK   (0x00000002u)
+#define EDMA3_TCRL_INTCLR_TRDONE_SHIFT   (0x00000001u)
+#define EDMA3_TCRL_INTCLR_TRDONE_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_INTCLR_TRDONE_CLEAR   (0x00000001u)
+#define EDMA3_TCRL_INTCLR_PROGEMPTY_MASK   (0x00000001u)
+#define EDMA3_TCRL_INTCLR_PROGEMPTY_SHIFT   (0x00000000u)
+#define EDMA3_TCRL_INTCLR_PROGEMPTY_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_INTCLR_PROGEMPTY_CLEAR   (0x00000001u)
+#define EDMA3_TCRL_INTCLR_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_INTCMD_SET_MASK   (0x00000002u)
+#define EDMA3_TCRL_INTCMD_SET_SHIFT   (0x00000001u)
+#define EDMA3_TCRL_INTCMD_SET_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_INTCMD_SET_SET   (0x00000001u)
+#define EDMA3_TCRL_INTCMD_EVAL_MASK   (0x00000001u)
+#define EDMA3_TCRL_INTCMD_EVAL_SHIFT   (0x00000000u)
+#define EDMA3_TCRL_INTCMD_EVAL_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_INTCMD_EVAL_EVAL   (0x00000001u)
+#define EDMA3_TCRL_INTCMD_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_ERRSTAT_MMRAERR_MASK   (0x00000008u)
+#define EDMA3_TCRL_ERRSTAT_MMRAERR_SHIFT   (0x00000003u)
+#define EDMA3_TCRL_ERRSTAT_MMRAERR_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_ERRSTAT_MMRAERR_NONE   (0x00000000u)
+#define EDMA3_TCRL_ERRSTAT_MMRAERR_ERROR   (0x00000001u)
+#define EDMA3_TCRL_ERRSTAT_TRERR_MASK   (0x00000004u)
+#define EDMA3_TCRL_ERRSTAT_TRERR_SHIFT   (0x00000002u)
+#define EDMA3_TCRL_ERRSTAT_TRERR_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_ERRSTAT_TRERR_NONE   (0x00000000u)
+#define EDMA3_TCRL_ERRSTAT_TRERR_ERROR   (0x00000001u)
+#define EDMA3_TCRL_ERRSTAT_BUSERR_MASK   (0x00000001u)
+#define EDMA3_TCRL_ERRSTAT_BUSERR_SHIFT   (0x00000000u)
+#define EDMA3_TCRL_ERRSTAT_BUSERR_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_ERRSTAT_BUSERR_NONE   (0x00000000u)
+#define EDMA3_TCRL_ERRSTAT_BUSERR_ERROR   (0x00000001u)
+#define EDMA3_TCRL_ERRSTAT_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_ERREN_MMRAERR_MASK   (0x00000008u)
+#define EDMA3_TCRL_ERREN_MMRAERR_SHIFT   (0x00000003u)
+#define EDMA3_TCRL_ERREN_MMRAERR_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_ERREN_MMRAERR_ENABLE   (0x00000001u)
+#define EDMA3_TCRL_ERREN_MMRAERR_DISABLE   (0x00000000u)
+#define EDMA3_TCRL_ERREN_TRERR_MASK   (0x00000004u)
+#define EDMA3_TCRL_ERREN_TRERR_SHIFT   (0x00000002u)
+#define EDMA3_TCRL_ERREN_TRERR_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_ERREN_TRERR_ENABLE   (0x00000001u)
+#define EDMA3_TCRL_ERREN_TRERR_DISABLE   (0x00000000u)
+#define EDMA3_TCRL_ERREN_BUSERR_MASK   (0x00000001u)
+#define EDMA3_TCRL_ERREN_BUSERR_SHIFT   (0x00000000u)
+#define EDMA3_TCRL_ERREN_BUSERR_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_ERREN_BUSERR_ENABLE   (0x00000001u)
+#define EDMA3_TCRL_ERREN_BUSERR_DISABLE   (0x00000000u)
+#define EDMA3_TCRL_ERREN_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_ERRCLR_MMRAERR_MASK   (0x00000008u)
+#define EDMA3_TCRL_ERRCLR_MMRAERR_SHIFT   (0x00000003u)
+#define EDMA3_TCRL_ERRCLR_MMRAERR_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_ERRCLR_MMRAERR_CLEAR   (0x00000001u)
+#define EDMA3_TCRL_ERRCLR_TRERR_MASK   (0x00000004u)
+#define EDMA3_TCRL_ERRCLR_TRERR_SHIFT   (0x00000002u)
+#define EDMA3_TCRL_ERRCLR_TRERR_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_ERRCLR_TRERR_CLEAR   (0x00000001u)
+#define EDMA3_TCRL_ERRCLR_BUSERR_MASK   (0x00000001u)
+#define EDMA3_TCRL_ERRCLR_BUSERR_SHIFT   (0x00000000u)
+#define EDMA3_TCRL_ERRCLR_BUSERR_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_ERRCLR_BUSERR_CLEAR   (0x00000001u)
+#define EDMA3_TCRL_ERRCLR_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_ERRDET_TCCHEN_MASK   (0x00020000u)
+#define EDMA3_TCRL_ERRDET_TCCHEN_SHIFT   (0x00000011u)
+#define EDMA3_TCRL_ERRDET_TCCHEN_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_ERRDET_TCINTEN_MASK   (0x00010000u)
+#define EDMA3_TCRL_ERRDET_TCINTEN_SHIFT   (0x00000010u)
+#define EDMA3_TCRL_ERRDET_TCINTEN_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_ERRDET_TCC_MASK   (0x00003F00u)
+#define EDMA3_TCRL_ERRDET_TCC_SHIFT   (0x00000008u)
+#define EDMA3_TCRL_ERRDET_TCC_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_ERRDET_STAT_MASK   (0x0000000Fu)
+#define EDMA3_TCRL_ERRDET_STAT_SHIFT   (0x00000000u)
+#define EDMA3_TCRL_ERRDET_STAT_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_ERRDET_STAT_NONE   (0x00000000u)
+#define EDMA3_TCRL_ERRDET_STAT_READ_ADDRESS   (0x00000001u)
+#define EDMA3_TCRL_ERRDET_STAT_READ_PRIVILEGE   (0x00000002u)
+#define EDMA3_TCRL_ERRDET_STAT_READ_TIMEOUT   (0x00000003u)
+#define EDMA3_TCRL_ERRDET_STAT_READ_DATA   (0x00000004u)
+#define EDMA3_TCRL_ERRDET_STAT_READ_EXCLUSIVE   (0x00000007u)
+#define EDMA3_TCRL_ERRDET_STAT_WRITE_ADDRESS   (0x00000009u)
+#define EDMA3_TCRL_ERRDET_STAT_WRITE_PRIVILEGE   (0x0000000Au)
+#define EDMA3_TCRL_ERRDET_STAT_WRITE_TIMEOUT   (0x0000000Bu)
+#define EDMA3_TCRL_ERRDET_STAT_WRITE_DATA   (0x0000000Cu)
+#define EDMA3_TCRL_ERRDET_STAT_WRITE_EXCLUSIVE   (0x0000000Fu)
+#define EDMA3_TCRL_ERRDET_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_ERRCMD_SET_MASK   (0x00000002u)
+#define EDMA3_TCRL_ERRCMD_SET_SHIFT   (0x00000001u)
+#define EDMA3_TCRL_ERRCMD_SET_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_ERRCMD_SET_SET   (0x00000001u)
+#define EDMA3_TCRL_ERRCMD_EVAL_MASK   (0x00000001u)
+#define EDMA3_TCRL_ERRCMD_EVAL_SHIFT   (0x00000000u)
+#define EDMA3_TCRL_ERRCMD_EVAL_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_ERRCMD_EVAL_EVAL   (0x00000001u)
+#define EDMA3_TCRL_ERRCMD_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_RDRATE_RDRATE_MASK   (0x00000007u)
+#define EDMA3_TCRL_RDRATE_RDRATE_SHIFT   (0x00000000u)
+#define EDMA3_TCRL_RDRATE_RDRATE_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_RDRATE_RDRATE_AFAP   (0x00000000u)
+#define EDMA3_TCRL_RDRATE_RDRATE_4CYCLE   (0x00000001u)
+#define EDMA3_TCRL_RDRATE_RDRATE_8CYCLE   (0x00000002u)
+#define EDMA3_TCRL_RDRATE_RDRATE_16CYCLE   (0x00000003u)
+#define EDMA3_TCRL_RDRATE_RDRATE_32CYCLE   (0x00000004u)
+#define EDMA3_TCRL_RDRATE_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_POPT_TCCHEN_MASK   (0x00400000u)
+#define EDMA3_TCRL_POPT_TCCHEN_SHIFT   (0x00000016u)
+#define EDMA3_TCRL_POPT_TCCHEN_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_POPT_TCCHEN_DISABLE   (0x00000000u)
+#define EDMA3_TCRL_POPT_TCCHEN_ENABLE   (0x00000001u)
+#define EDMA3_TCRL_POPT_TCINTEN_MASK   (0x00100000u)
+#define EDMA3_TCRL_POPT_TCINTEN_SHIFT   (0x00000014u)
+#define EDMA3_TCRL_POPT_TCINTEN_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_POPT_TCINTEN_DISABLE   (0x00000000u)
+#define EDMA3_TCRL_POPT_TCINTEN_ENABLE   (0x00000001u)
+#define EDMA3_TCRL_POPT_TCC_MASK   (0x0003F000u)
+#define EDMA3_TCRL_POPT_TCC_SHIFT   (0x0000000Cu)
+#define EDMA3_TCRL_POPT_TCC_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_POPT_FWID_MASK   (0x00000700u)
+#define EDMA3_TCRL_POPT_FWID_SHIFT   (0x00000008u)
+#define EDMA3_TCRL_POPT_FWID_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_POPT_FWID_8BIT   (0x00000000u)
+#define EDMA3_TCRL_POPT_FWID_16BIT   (0x00000001u)
+#define EDMA3_TCRL_POPT_FWID_32BIT   (0x00000002u)
+#define EDMA3_TCRL_POPT_FWID_64BIT   (0x00000003u)
+#define EDMA3_TCRL_POPT_FWID_128BIT   (0x00000004u)
+#define EDMA3_TCRL_POPT_FWID_256BIT   (0x00000005u)
+#define EDMA3_TCRL_POPT_PRI_MASK   (0x00000070u)
+#define EDMA3_TCRL_POPT_PRI_SHIFT   (0x00000004u)
+#define EDMA3_TCRL_POPT_PRI_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_POPT_DAM_MASK   (0x00000002u)
+#define EDMA3_TCRL_POPT_DAM_SHIFT   (0x00000001u)
+#define EDMA3_TCRL_POPT_DAM_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_POPT_DAM_INCR   (0x00000000u)
+#define EDMA3_TCRL_POPT_DAM_FIFO   (0x00000001u)
+#define EDMA3_TCRL_POPT_SAM_MASK   (0x00000001u)
+#define EDMA3_TCRL_POPT_SAM_SHIFT   (0x00000000u)
+#define EDMA3_TCRL_POPT_SAM_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_POPT_SAM_INCR   (0x00000000u)
+#define EDMA3_TCRL_POPT_SAM_FIFO   (0x00000001u)
+#define EDMA3_TCRL_POPT_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_PSRC_SADDR_MASK   (0xFFFFFFFFu)
+#define EDMA3_TCRL_PSRC_SADDR_SHIFT   (0x00000000u)
+#define EDMA3_TCRL_PSRC_SADDR_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_PSRC_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_PCNT_BCNT_MASK   (0xFFFF0000u)
+#define EDMA3_TCRL_PCNT_BCNT_SHIFT   (0x00000010u)
+#define EDMA3_TCRL_PCNT_BCNT_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_PCNT_ACNT_MASK   (0x0000FFFFu)
+#define EDMA3_TCRL_PCNT_ACNT_SHIFT   (0x00000000u)
+#define EDMA3_TCRL_PCNT_ACNT_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_PCNT_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_PDST_DADDR_MASK   (0xFFFFFFFFu)
+#define EDMA3_TCRL_PDST_DADDR_SHIFT   (0x00000000u)
+#define EDMA3_TCRL_PDST_DADDR_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_PDST_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_PBIDX_DBIDX_MASK   (0xFFFF0000u)
+#define EDMA3_TCRL_PBIDX_DBIDX_SHIFT   (0x00000010u)
+#define EDMA3_TCRL_PBIDX_DBIDX_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_PBIDX_SBIDX_MASK   (0x0000FFFFu)
+#define EDMA3_TCRL_PBIDX_SBIDX_SHIFT   (0x00000000u)
+#define EDMA3_TCRL_PBIDX_SBIDX_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_PBIDX_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_PMPPRXY_PRIV_MASK   (0x00000100u)
+#define EDMA3_TCRL_PMPPRXY_PRIV_SHIFT   (0x00000008u)
+#define EDMA3_TCRL_PMPPRXY_PRIV_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_PMPPRXY_PRIV_USER   (0x00000000u)
+#define EDMA3_TCRL_PMPPRXY_PRIV_SUPERVISOR   (0x00000001u)
+#define EDMA3_TCRL_PMPPRXY_PRIVID_MASK   (0x0000000Fu)
+#define EDMA3_TCRL_PMPPRXY_PRIVID_SHIFT   (0x00000000u)
+#define EDMA3_TCRL_PMPPRXY_PRIVID_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_PMPPRXY_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_SAOPT_TCCHEN_MASK   (0x00400000u)
+#define EDMA3_TCRL_SAOPT_TCCHEN_SHIFT   (0x00000016u)
+#define EDMA3_TCRL_SAOPT_TCCHEN_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_SAOPT_TCCHEN_DISABLE   (0x00000000u)
+#define EDMA3_TCRL_SAOPT_TCCHEN_ENABLE   (0x00000001u)
+#define EDMA3_TCRL_SAOPT_TCINTEN_MASK   (0x00100000u)
+#define EDMA3_TCRL_SAOPT_TCINTEN_SHIFT   (0x00000014u)
+#define EDMA3_TCRL_SAOPT_TCINTEN_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_SAOPT_TCINTEN_DISABLE   (0x00000000u)
+#define EDMA3_TCRL_SAOPT_TCINTEN_ENABLE   (0x00000001u)
+#define EDMA3_TCRL_SAOPT_TCC_MASK   (0x0003F000u)
+#define EDMA3_TCRL_SAOPT_TCC_SHIFT   (0x0000000Cu)
+#define EDMA3_TCRL_SAOPT_TCC_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_SAOPT_FWID_MASK   (0x00000700u)
+#define EDMA3_TCRL_SAOPT_FWID_SHIFT   (0x00000008u)
+#define EDMA3_TCRL_SAOPT_FWID_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_SAOPT_FWID_8BIT   (0x00000000u)
+#define EDMA3_TCRL_SAOPT_FWID_16BIT   (0x00000001u)
+#define EDMA3_TCRL_SAOPT_FWID_32BIT   (0x00000002u)
+#define EDMA3_TCRL_SAOPT_FWID_64BIT   (0x00000003u)
+#define EDMA3_TCRL_SAOPT_FWID_128BIT   (0x00000004u)
+#define EDMA3_TCRL_SAOPT_FWID_256BIT   (0x00000005u)
+#define EDMA3_TCRL_SAOPT_PRI_MASK   (0x00000070u)
+#define EDMA3_TCRL_SAOPT_PRI_SHIFT   (0x00000004u)
+#define EDMA3_TCRL_SAOPT_PRI_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_SAOPT_DAM_MASK   (0x00000002u)
+#define EDMA3_TCRL_SAOPT_DAM_SHIFT   (0x00000001u)
+#define EDMA3_TCRL_SAOPT_DAM_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_SAOPT_DAM_INCR   (0x00000000u)
+#define EDMA3_TCRL_SAOPT_DAM_FIFO   (0x00000001u)
+#define EDMA3_TCRL_SAOPT_SAM_MASK   (0x00000001u)
+#define EDMA3_TCRL_SAOPT_SAM_SHIFT   (0x00000000u)
+#define EDMA3_TCRL_SAOPT_SAM_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_SAOPT_SAM_INCR   (0x00000000u)
+#define EDMA3_TCRL_SAOPT_SAM_FIFO   (0x00000001u)
+#define EDMA3_TCRL_SAOPT_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_SASRC_SADDR_MASK   (0xFFFFFFFFu)
+#define EDMA3_TCRL_SASRC_SADDR_SHIFT   (0x00000000u)
+#define EDMA3_TCRL_SASRC_SADDR_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_SASRC_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_SACNT_BCNT_MASK   (0xFFFF0000u)
+#define EDMA3_TCRL_SACNT_BCNT_SHIFT   (0x00000010u)
+#define EDMA3_TCRL_SACNT_BCNT_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_SACNT_ACNT_MASK   (0x0000FFFFu)
+#define EDMA3_TCRL_SACNT_ACNT_SHIFT   (0x00000000u)
+#define EDMA3_TCRL_SACNT_ACNT_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_SACNT_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_SADST_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_SABIDX_DBIDX_MASK   (0xFFFF0000u)
+#define EDMA3_TCRL_SABIDX_DBIDX_SHIFT   (0x00000010u)
+#define EDMA3_TCRL_SABIDX_DBIDX_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_SABIDX_SBIDX_MASK   (0x0000FFFFu)
+#define EDMA3_TCRL_SABIDX_SBIDX_SHIFT   (0x00000000u)
+#define EDMA3_TCRL_SABIDX_SBIDX_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_SABIDX_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_SAMPPRXY_PRIV_MASK   (0x00000100u)
+#define EDMA3_TCRL_SAMPPRXY_PRIV_SHIFT   (0x00000008u)
+#define EDMA3_TCRL_SAMPPRXY_PRIV_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_SAMPPRXY_PRIV_USER   (0x00000000u)
+#define EDMA3_TCRL_SAMPPRXY_PRIV_SUPERVISOR   (0x00000001u)
+#define EDMA3_TCRL_SAMPPRXY_PRIVID_MASK   (0x0000000Fu)
+#define EDMA3_TCRL_SAMPPRXY_PRIVID_SHIFT   (0x00000000u)
+#define EDMA3_TCRL_SAMPPRXY_PRIVID_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_SAMPPRXY_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_SACNTRLD_ACNTRLD_MASK   (0x0000FFFFu)
+#define EDMA3_TCRL_SACNTRLD_ACNTRLD_SHIFT   (0x00000000u)
+#define EDMA3_TCRL_SACNTRLD_ACNTRLD_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_SACNTRLD_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_SASRCBREF_SADDRBREFG_MASK   (0xFFFFFFFFu)
+#define EDMA3_TCRL_SASRCBREF_SADDRBREFG_SHIFT   (0x00000000u)
+#define EDMA3_TCRL_SASRCBREF_SADDRBREFG_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_SASRCBREF_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_SADSTBREF_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_DFCNTRLD_ACNTRLD_MASK   (0x0000FFFFu)
+#define EDMA3_TCRL_DFCNTRLD_ACNTRLD_SHIFT   (0x00000000u)
+#define EDMA3_TCRL_DFCNTRLD_ACNTRLD_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_DFCNTRLD_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_DFSRCBREF_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_DFDSTBREF_DADDRBREF_MASK   (0xFFFFFFFFu)
+#define EDMA3_TCRL_DFDSTBREF_DADDRBREF_SHIFT   (0x00000000u)
+#define EDMA3_TCRL_DFDSTBREF_DADDRBREF_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_DFDSTBREF_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_DFOPT_TCCHEN_MASK   (0x00400000u)
+#define EDMA3_TCRL_DFOPT_TCCHEN_SHIFT   (0x00000016u)
+#define EDMA3_TCRL_DFOPT_TCCHEN_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_DFOPT_TCCHEN_DISABLE   (0x00000000u)
+#define EDMA3_TCRL_DFOPT_TCCHEN_ENABLE   (0x00000001u)
+#define EDMA3_TCRL_DFOPT_TCINTEN_MASK   (0x00100000u)
+#define EDMA3_TCRL_DFOPT_TCINTEN_SHIFT   (0x00000014u)
+#define EDMA3_TCRL_DFOPT_TCINTEN_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_DFOPT_TCINTEN_DISABLE   (0x00000000u)
+#define EDMA3_TCRL_DFOPT_TCINTEN_ENABLE   (0x00000001u)
+#define EDMA3_TCRL_DFOPT_TCC_MASK   (0x0003F000u)
+#define EDMA3_TCRL_DFOPT_TCC_SHIFT   (0x0000000Cu)
+#define EDMA3_TCRL_DFOPT_TCC_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_DFOPT_FWID_MASK   (0x00000700u)
+#define EDMA3_TCRL_DFOPT_FWID_SHIFT   (0x00000008u)
+#define EDMA3_TCRL_DFOPT_FWID_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_DFOPT_FWID_8BIT   (0x00000000u)
+#define EDMA3_TCRL_DFOPT_FWID_16BIT   (0x00000001u)
+#define EDMA3_TCRL_DFOPT_FWID_32BIT   (0x00000002u)
+#define EDMA3_TCRL_DFOPT_FWID_64BIT   (0x00000003u)
+#define EDMA3_TCRL_DFOPT_FWID_128BIT   (0x00000004u)
+#define EDMA3_TCRL_DFOPT_FWID_256BIT   (0x00000005u)
+#define EDMA3_TCRL_DFOPT_PRI_MASK   (0x00000070u)
+#define EDMA3_TCRL_DFOPT_PRI_SHIFT   (0x00000004u)
+#define EDMA3_TCRL_DFOPT_PRI_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_DFOPT_DAM_MASK   (0x00000002u)
+#define EDMA3_TCRL_DFOPT_DAM_SHIFT   (0x00000001u)
+#define EDMA3_TCRL_DFOPT_DAM_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_DFOPT_DAM_INCR   (0x00000000u)
+#define EDMA3_TCRL_DFOPT_DAM_FIFO   (0x00000001u)
+#define EDMA3_TCRL_DFOPT_SAM_MASK   (0x00000001u)
+#define EDMA3_TCRL_DFOPT_SAM_SHIFT   (0x00000000u)
+#define EDMA3_TCRL_DFOPT_SAM_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_DFOPT_SAM_INCR   (0x00000000u)
+#define EDMA3_TCRL_DFOPT_SAM_FIFO   (0x00000001u)
+#define EDMA3_TCRL_DFOPT_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_DFSRC_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_DFCNT_BCNT_MASK   (0xFFFF0000u)
+#define EDMA3_TCRL_DFCNT_BCNT_SHIFT   (0x00000010u)
+#define EDMA3_TCRL_DFCNT_BCNT_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_DFCNT_ACNT_MASK   (0x0000FFFFu)
+#define EDMA3_TCRL_DFCNT_ACNT_SHIFT   (0x00000000u)
+#define EDMA3_TCRL_DFCNT_ACNT_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_DFCNT_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_DFDST_DADDR_MASK   (0xFFFFFFFFu)
+#define EDMA3_TCRL_DFDST_DADDR_SHIFT   (0x00000000u)
+#define EDMA3_TCRL_DFDST_DADDR_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_DFDST_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_DFBIDX_DBIDX_MASK   (0xFFFF0000u)
+#define EDMA3_TCRL_DFBIDX_DBIDX_SHIFT   (0x00000010u)
+#define EDMA3_TCRL_DFBIDX_DBIDX_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_DFBIDX_SBIDX_MASK   (0x0000FFFFu)
+#define EDMA3_TCRL_DFBIDX_SBIDX_SHIFT   (0x00000000u)
+#define EDMA3_TCRL_DFBIDX_SBIDX_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_DFBIDX_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_DFMPPRXY_PRIV_MASK   (0x00000100u)
+#define EDMA3_TCRL_DFMPPRXY_PRIV_SHIFT   (0x00000008u)
+#define EDMA3_TCRL_DFMPPRXY_PRIV_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_DFMPPRXY_PRIV_USER   (0x00000000u)
+#define EDMA3_TCRL_DFMPPRXY_PRIV_SUPERVISOR   (0x00000001u)
+#define EDMA3_TCRL_DFMPPRXY_PRIVID_MASK   (0x0000000Fu)
+#define EDMA3_TCRL_DFMPPRXY_PRIVID_SHIFT   (0x00000000u)
+#define EDMA3_TCRL_DFMPPRXY_PRIVID_RESETVAL   (0x00000000u)
+#define EDMA3_TCRL_DFMPPRXY_RESETVAL   (0x00000000u)
+

Detailed Description

+EDMA3 Transfer Controller Register Desciption. +

+This file contains the register layer for the EDMA3 Transfer Controller.

+(C) Copyright 2006, Texas Instruments, Inc

+

Version:
1.0 Anuj Aggarwal - Created
+
+
Generated on Thu Oct 16 16:22:36 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/edma3__rm_8h-source.html b/packages/ti/sdo/edma3/rm/docs/html/edma3__rm_8h-source.html new file mode 100644 index 0000000..80e6751 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/edma3__rm_8h-source.html @@ -0,0 +1,627 @@ + + +EDMA3 Resource Manager: edma3_rm.h Source File + + + + + +
Generated on Thu Oct 16 16:21:27 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/edma3__rm_8h.html b/packages/ti/sdo/edma3/rm/docs/html/edma3__rm_8h.html new file mode 100644 index 0000000..bae0a85 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/edma3__rm_8h.html @@ -0,0 +1,434 @@ + + +EDMA3 Resource Manager: edma3_rm.h File Reference + + + + + +
+

edma3_rm.h File Reference

EDMA3 Controller Resource Manager Interface. More... +

+#include <ti/sdo/edma3/rm/edma3_common.h>
+ +

+Go to the source code of this file. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Data Structures

struct  EDMA3_RM_GblErrCallbackParams
 Global Error Callback parameters. More...
struct  EDMA3_RM_ResDesc
 Handle to a Resource. More...
struct  EDMA3_RM_GblConfigParams
 Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. More...
struct  EDMA3_RM_InstanceInitConfig
 Init-time Region Specific Configuration structure for EDMA3 RM, to provide region specific Information. More...
struct  EDMA3_RM_Param
 Used to Initialize the Resource Manager Instance. More...
struct  EDMA3_RM_MiscParam
 Used to specify the miscellaneous options during Resource Manager Initialization. More...
struct  EDMA3_RM_ParamentryRegs
 EDMA3 PaRAM Set. More...
struct  EDMA3_RM_PaRAMRegs
 EDMA3 PaRAM Set in User Configurable format. More...

Defines

+#define EDMA3_RM_RES_ANY   (1010u)
 Used to specify any available Resource Id (EDMA3_RM_ResDesc.resId).
#define EDMA3_RM_E_BASE   (-155)
#define EDMA3_RM_E_OBJ_NOT_DELETED   (EDMA3_RM_E_BASE)
#define EDMA3_RM_E_OBJ_NOT_CLOSED   (EDMA3_RM_E_BASE-1)
#define EDMA3_RM_E_OBJ_NOT_OPENED   (EDMA3_RM_E_BASE-2)
#define EDMA3_RM_E_INVALID_PARAM   (EDMA3_RM_E_BASE-3)
#define EDMA3_RM_E_RES_ALREADY_FREE   (EDMA3_RM_E_BASE-4)
#define EDMA3_RM_E_RES_NOT_OWNED   (EDMA3_RM_E_BASE-5)
#define EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE   (EDMA3_RM_E_BASE-6)
#define EDMA3_RM_E_ALL_RES_NOT_AVAILABLE   (EDMA3_RM_E_BASE-7)
#define EDMA3_RM_E_INVALID_STATE   (EDMA3_RM_E_BASE-8)
#define EDMA3_RM_E_MAX_RM_INST_OPENED   (EDMA3_RM_E_BASE-9)
#define EDMA3_RM_E_RM_MASTER_ALREADY_EXISTS   (EDMA3_RM_E_BASE-10)
#define EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED   (EDMA3_RM_E_BASE-11)
#define EDMA3_RM_E_SEMAPHORE   (EDMA3_RM_E_BASE-12)
#define EDMA3_RM_E_FEATURE_UNSUPPORTED   (EDMA3_RM_E_BASE-13)
#define EDMA3_RM_E_RES_NOT_ALLOCATED   (EDMA3_RM_E_BASE-14)
#define EDMA3_RM_DMA_CHANNEL_ANY   (1011u)
#define EDMA3_RM_QDMA_CHANNEL_ANY   (1012u)
#define EDMA3_RM_TCC_ANY   (1013u)
#define EDMA3_RM_PARAM_ANY   (1014u)
#define EDMA3_RM_CH_NO_PARAM_MAP   (1015u)
#define EDMA3_RM_CH_NO_TCC_MAP   (1016u)

Typedefs

typedef void(* EDMA3_RM_GblErrCallback )(EDMA3_RM_GlobalError deviceStatus, unsigned int instanceId, void *gblerrData)
 Global Error callback - caters to module events like bus error etc which are not channel specific. Runs in ISR context.
typedef void(* EDMA3_RM_TccCallback )(unsigned int tcc, EDMA3_RM_TccStatus status, void *appData)
 TCC callback - caters to channel-specific events like "Event Miss Error" or "Transfer Complete". Runs in ISR context.
typedef unsigned int EDMA3_RM_RegionId
 EDMA3 Region Id.
typedef unsigned int EDMA3_RM_EventQueue
 EDMA3 Event Queue assignment.

Enumerations

enum  EDMA3_RM_TccStatus {
+  EDMA3_RM_XFER_COMPLETE = 1, +
+  EDMA3_RM_E_CC_DMA_EVT_MISS = 2, +
+  EDMA3_RM_E_CC_QDMA_EVT_MISS = 3 +
+ }
 This enum defines the channel specific status codes of an EDMA3 transfer. It is returned while calling the channel specific callback function to tell the status. More...
enum  EDMA3_RM_GlobalError {
+  EDMA3_RM_E_CC_QUE_THRES_EXCEED = 1, +
+  EDMA3_RM_E_CC_TCC = 2, +
+  EDMA3_RM_E_TC_MEM_LOCATION_READ_ERROR = 3, +
+  EDMA3_RM_E_TC_MEM_LOCATION_WRITE_ERROR = 4, +
+  EDMA3_RM_E_TC_INVALID_ADDR = 5, +
+  EDMA3_RM_E_TC_TR_ERROR = 6 +
+ }
 This enum defines the global (not specific to any channel) error codes of completion of an EDMA3 transfer. More...
enum  EDMA3_RM_ResType {
+  EDMA3_RM_RES_DMA_CHANNEL = 1, +
+  EDMA3_RM_RES_QDMA_CHANNEL = 2, +
+  EDMA3_RM_RES_TCC = 3, +
+  EDMA3_RM_RES_PARAM_SET = 4 +
+ }
 EDMA3 Resource Type. More...
enum  EDMA3_RM_HW_CHANNEL_EVENT {
+  EDMA3_RM_HW_CHANNEL_EVENT_0 = 0, +
+  EDMA3_RM_HW_CHANNEL_EVENT_1, +
+  EDMA3_RM_HW_CHANNEL_EVENT_2, +
+  EDMA3_RM_HW_CHANNEL_EVENT_3, +
+  EDMA3_RM_HW_CHANNEL_EVENT_4, +
+  EDMA3_RM_HW_CHANNEL_EVENT_5, +
+  EDMA3_RM_HW_CHANNEL_EVENT_6, +
+  EDMA3_RM_HW_CHANNEL_EVENT_7, +
+  EDMA3_RM_HW_CHANNEL_EVENT_8, +
+  EDMA3_RM_HW_CHANNEL_EVENT_9, +
+  EDMA3_RM_HW_CHANNEL_EVENT_10, +
+  EDMA3_RM_HW_CHANNEL_EVENT_11, +
+  EDMA3_RM_HW_CHANNEL_EVENT_12, +
+  EDMA3_RM_HW_CHANNEL_EVENT_13, +
+  EDMA3_RM_HW_CHANNEL_EVENT_14, +
+  EDMA3_RM_HW_CHANNEL_EVENT_15, +
+  EDMA3_RM_HW_CHANNEL_EVENT_16, +
+  EDMA3_RM_HW_CHANNEL_EVENT_17, +
+  EDMA3_RM_HW_CHANNEL_EVENT_18, +
+  EDMA3_RM_HW_CHANNEL_EVENT_19, +
+  EDMA3_RM_HW_CHANNEL_EVENT_20, +
+  EDMA3_RM_HW_CHANNEL_EVENT_21, +
+  EDMA3_RM_HW_CHANNEL_EVENT_22, +
+  EDMA3_RM_HW_CHANNEL_EVENT_23, +
+  EDMA3_RM_HW_CHANNEL_EVENT_24, +
+  EDMA3_RM_HW_CHANNEL_EVENT_25, +
+  EDMA3_RM_HW_CHANNEL_EVENT_26, +
+  EDMA3_RM_HW_CHANNEL_EVENT_27, +
+  EDMA3_RM_HW_CHANNEL_EVENT_28, +
+  EDMA3_RM_HW_CHANNEL_EVENT_29, +
+  EDMA3_RM_HW_CHANNEL_EVENT_30, +
+  EDMA3_RM_HW_CHANNEL_EVENT_31, +
+  EDMA3_RM_HW_CHANNEL_EVENT_32, +
+  EDMA3_RM_HW_CHANNEL_EVENT_33, +
+  EDMA3_RM_HW_CHANNEL_EVENT_34, +
+  EDMA3_RM_HW_CHANNEL_EVENT_35, +
+  EDMA3_RM_HW_CHANNEL_EVENT_36, +
+  EDMA3_RM_HW_CHANNEL_EVENT_37, +
+  EDMA3_RM_HW_CHANNEL_EVENT_38, +
+  EDMA3_RM_HW_CHANNEL_EVENT_39, +
+  EDMA3_RM_HW_CHANNEL_EVENT_40, +
+  EDMA3_RM_HW_CHANNEL_EVENT_41, +
+  EDMA3_RM_HW_CHANNEL_EVENT_42, +
+  EDMA3_RM_HW_CHANNEL_EVENT_43, +
+  EDMA3_RM_HW_CHANNEL_EVENT_44, +
+  EDMA3_RM_HW_CHANNEL_EVENT_45, +
+  EDMA3_RM_HW_CHANNEL_EVENT_46, +
+  EDMA3_RM_HW_CHANNEL_EVENT_47, +
+  EDMA3_RM_HW_CHANNEL_EVENT_48, +
+  EDMA3_RM_HW_CHANNEL_EVENT_49, +
+  EDMA3_RM_HW_CHANNEL_EVENT_50, +
+  EDMA3_RM_HW_CHANNEL_EVENT_51, +
+  EDMA3_RM_HW_CHANNEL_EVENT_52, +
+  EDMA3_RM_HW_CHANNEL_EVENT_53, +
+  EDMA3_RM_HW_CHANNEL_EVENT_54, +
+  EDMA3_RM_HW_CHANNEL_EVENT_55, +
+  EDMA3_RM_HW_CHANNEL_EVENT_56, +
+  EDMA3_RM_HW_CHANNEL_EVENT_57, +
+  EDMA3_RM_HW_CHANNEL_EVENT_58, +
+  EDMA3_RM_HW_CHANNEL_EVENT_59, +
+  EDMA3_RM_HW_CHANNEL_EVENT_60, +
+  EDMA3_RM_HW_CHANNEL_EVENT_61, +
+  EDMA3_RM_HW_CHANNEL_EVENT_62, +
+  EDMA3_RM_HW_CHANNEL_EVENT_63 +
+ }
 DMA Channels assigned to different Hardware Events. They should be used while requesting a specific DMA channel. One possible usage is to maintain a SoC specific file, which will contain the mapping of these hardware events to the respective peripherals for better understanding and lesser probability of errors. Also, if any event associated with a particular peripheral gets changed, only that SoC specific file needs to be changed. More...
enum  EDMA3_RM_QdmaTrigWord {
+  EDMA3_RM_QDMA_TRIG_OPT = 0, +
+  EDMA3_RM_QDMA_TRIG_SRC = 1, +
+  EDMA3_RM_QDMA_TRIG_ACNT_BCNT = 2, +
+  EDMA3_RM_QDMA_TRIG_DST = 3, +
+  EDMA3_RM_QDMA_TRIG_SRC_DST_BIDX = 4, +
+  EDMA3_RM_QDMA_TRIG_LINK_BCNTRLD = 5, +
+  EDMA3_RM_QDMA_TRIG_SRC_DST_CIDX = 6, +
+  EDMA3_RM_QDMA_TRIG_CCNT = 7, +
+  EDMA3_RM_QDMA_TRIG_DEFAULT = 7 +
+ }
 QDMA Trigger Word. More...
enum  EDMA3_RM_Cntrlr_PhyAddr {
+  EDMA3_RM_CC_PHY_ADDR = 0, +
+  EDMA3_RM_TC0_PHY_ADDR, +
+  EDMA3_RM_TC1_PHY_ADDR, +
+  EDMA3_RM_TC2_PHY_ADDR, +
+  EDMA3_RM_TC3_PHY_ADDR, +
+  EDMA3_RM_TC4_PHY_ADDR, +
+  EDMA3_RM_TC5_PHY_ADDR, +
+  EDMA3_RM_TC6_PHY_ADDR, +
+  EDMA3_RM_TC7_PHY_ADDR +
+ }
 CC/TC Physical Address. More...
enum  EDMA3_RM_IoctlCmd {
+  EDMA3_RM_IOCTL_MIN_IOCTL = 0, +
+  EDMA3_RM_IOCTL_SET_PARAM_CLEAR_OPTION, +
+  EDMA3_RM_IOCTL_GET_PARAM_CLEAR_OPTION, +
+  EDMA3_RM_IOCTL_SET_GBL_REG_MODIFY_OPTION, +
+  EDMA3_RM_IOCTL_GET_GBL_REG_MODIFY_OPTION, +
+  EDMA3_RM_IOCTL_MAX_IOCTL +
+ }
 EDMA3 Resource Manager IOCTL commands. More...

Functions

EDMA3_RM_Result EDMA3_RM_registerTccCb (EDMA3_RM_Handle hEdmaResMgr, const EDMA3_RM_ResDesc *channelObj, unsigned int tcc, EDMA3_RM_TccCallback tccCb, void *cbData)
 Register Interrupt / Completion Handler for a given TCC.
EDMA3_RM_Result EDMA3_RM_unregisterTccCb (EDMA3_RM_Handle hEdmaResMgr, const EDMA3_RM_ResDesc *channelObj)
 Unregister the previously registered callback function against a DMA/QDMA channel.
EDMA3_RM_Result EDMA3_RM_create (unsigned int phyCtrllerInstId, const EDMA3_RM_GblConfigParams *gblCfgParams, const void *miscParam)
 Create EDMA3 Resource Manager Object.
EDMA3_RM_Result EDMA3_RM_delete (unsigned int phyCtrllerInstId, const void *param)
 Delete EDMA3 Resource Manager Object.
EDMA3_RM_Handle EDMA3_RM_open (unsigned int phyCtrllerInstId, const EDMA3_RM_Param *initParam, EDMA3_RM_Result *errorCode)
 Open EDMA3 Resource Manager Instance.
EDMA3_RM_Result EDMA3_RM_close (EDMA3_RM_Handle hEdmaResMgr, const void *param)
 Close EDMA3 Resource Manager Instance.
EDMA3_RM_Result EDMA3_RM_allocResource (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *resObj)
 This API is used to allocate specified EDMA3 Resources like DMA/QDMA channel, PaRAM Set or TCC.
EDMA3_RM_Result EDMA3_RM_freeResource (EDMA3_RM_Handle hEdmaResMgr, const EDMA3_RM_ResDesc *resObj)
 This API is used to free previously allocated EDMA3 Resources like DMA/QDMA channel, PaRAM Set or TCC.
EDMA3_RM_Result EDMA3_RM_allocContiguousResource (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *firstResIdObj, unsigned int numResources)
 Allocate a contiguous region of specified EDMA3 Resource like DMA channel, QDMA channel, PaRAM Set or TCC.
EDMA3_RM_Result EDMA3_RM_freeContiguousResource (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *firstResIdObj, unsigned int numResources)
 Free a contiguous region of specified EDMA3 Resource like DMA channel, QDMA channel, PaRAM Set or TCC, previously allocated.
EDMA3_RM_Result EDMA3_RM_allocLogicalChannel (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *lChObj, unsigned int *pParam, unsigned int *pTcc)
 Request a DMA/QDMA/Link channel.
EDMA3_RM_Result EDMA3_RM_freeLogicalChannel (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *lChObj)
 This API is used to free the specified channel (DMA/QDMA/Link) and its associated resources (PaRAM Set, TCC etc).
EDMA3_RM_Result EDMA3_RM_mapEdmaChannel (EDMA3_RM_Handle hEdmaResMgr, unsigned int channelId, unsigned int paRAMId)
 Bind the resources DMA Channel and PaRAM Set. Both the DMA channel and the PaRAM set should be previously allocated. If they are not, this API will result in error.
EDMA3_RM_Result EDMA3_RM_mapQdmaChannel (EDMA3_RM_Handle hEdmaResMgr, unsigned int channelId, unsigned int paRAMId, EDMA3_RM_QdmaTrigWord trigWord)
 Bind the resources QDMA Channel and PaRAM Set. Also, Set the trigger word for the QDMA channel. Both the QDMA channel and the PaRAM set should be previously allocated. If they are not, this API will result in error.
EDMA3_RM_Result EDMA3_RM_setCCRegister (EDMA3_RM_Handle hEdmaResMgr, unsigned int regOffset, unsigned int newRegValue)
 Set the Channel Controller (CC) Register value.
EDMA3_RM_Result EDMA3_RM_getCCRegister (EDMA3_RM_Handle hEdmaResMgr, unsigned int regOffset, unsigned int *regValue)
 Get the Channel Controller (CC) Register value.
EDMA3_RM_Result EDMA3_RM_waitAndClearTcc (EDMA3_RM_Handle hEdmaResMgr, unsigned int tccNo)
 Wait for a transfer completion interrupt to occur and clear it.
EDMA3_RM_Result EDMA3_RM_checkAndClearTcc (EDMA3_RM_Handle hEdmaResMgr, unsigned int tccNo, unsigned short *tccStatus)
 Returns the status of a previously initiated transfer.
EDMA3_RM_Result EDMA3_RM_setPaRAM (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *lChObj, const EDMA3_RM_PaRAMRegs *newPaRAM)
 Copy the user specified PaRAM Set onto the PaRAM Set associated with the logical channel (DMA/QDMA/Link).
EDMA3_RM_Result EDMA3_RM_getPaRAM (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *lChObj, EDMA3_RM_PaRAMRegs *currPaRAM)
 Retrieve existing PaRAM set associated with specified logical channel (DMA/QDMA/Link).
EDMA3_RM_Result EDMA3_RM_getPaRAMPhyAddr (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *lChObj, unsigned int *paramPhyAddr)
 Get the PaRAM Set Physical Address associated with a logical channel.
EDMA3_RM_Result EDMA3_RM_getBaseAddress (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_Cntrlr_PhyAddr controllerId, unsigned int *phyAddress)
 Get the Channel Controller or Transfer Controller (n) Physical Address.
EDMA3_RM_Result EDMA3_RM_getGblConfigParams (unsigned int phyCtrllerInstId, EDMA3_RM_GblConfigParams *gblCfgParams)
 Get the SoC specific configuration structure for the EDMA3 Hardware.
EDMA3_RM_Result EDMA3_RM_getInstanceInitCfg (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_InstanceInitConfig *instanceInitConfig)
 Get the RM Instance specific configuration structure for different EDMA3 resources' usage (owned resources, reserved resources etc).
EDMA3_RM_Result EDMA3_RM_Ioctl (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_IoctlCmd cmd, void *cmdArg, void *param)
 EDMA3 Resource Manager IOCTL.
+

Detailed Description

+EDMA3 Controller Resource Manager Interface. +

+This file contains Application Interface for the EDMA3 Controller Resource Manager.

+(C) Copyright 2006, Texas Instruments, Inc

+

Version:
0.0.1 Purushotam Kumar - Created 0.1.0 Joseph Fernandez - Made generic
    +
  • Added documentation
  • Moved SoC specific defines to SoC specific header. 0.2.0 Anuj Aggarwal - Modified it for EDMA3 package
  • Added multiple instances capability 0.2.1 Anuj Aggarwal - Modified it for more run time configuration.
  • Made EDMA3 package OS independent. 0.2.2 Anuj Aggarwal - Critical section handling code modification. Uses semaphore and interrupts disabling mechanism for resource sharing. 0.3.0 Anuj Aggarwal - Renamed EDMA3_DVR to EDMA3_DRV
  • IPR bit clearing in RM ISR issue fixed.
  • Sample application made generic 0.3.1 Anuj Aggarwal - Added DMA/QDMA Channel to TCC mapping, to fix QDMA missed event issue. 0.3.2 Anuj Aggarwal - Added support for POLL mode
  • Added a new API to modify the CC Register. 1.0.0 Anuj Aggarwal - Fixed resource allocation related bugs. 1.0.0.1 Anuj Aggarwal - Fixed spurious missed event generation related bug. 1.0.0.2 Anuj Aggarwal - Made the EDMA3 package RTSC compliant. 1.0.0.3 Anuj Aggarwal - Changed the directory structure as per RTSC standard. 1.01.00.01 Anuj Aggarwal - a) Added new APIs to allocate logical channels b) Created EDMA3 config files for different platforms c) Misc changes 1.02.00.01 Anuj Aggarwal - a) Added DM6467 support b) Fixed some MRs 1.03.00.01 Anuj Aggarwal - a) Added non-RTSC PJT files b) IOCTL Interface added. c) Fixed some MRs. 1.04 Anuj Aggarwal - a) Added new IOCTLs and APIs. b) Number of maximum Resource Manager Instances is configurable. c) Header files modified to have extern "C" declarations.
+
+
+
Generated on Thu Oct 16 16:22:37 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/edma3__rm__gbl__data_8c.html b/packages/ti/sdo/edma3/rm/docs/html/edma3__rm__gbl__data_8c.html new file mode 100644 index 0000000..9866a21 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/edma3__rm__gbl__data_8c.html @@ -0,0 +1,157 @@ + + +EDMA3 Resource Manager: edma3_rm_gbl_data.c File Reference + + + + + +
+

edma3_rm_gbl_data.c File Reference

Source file for the Resource Manager, for internal data structures. More... +

+#include <ti/sdo/edma3/rm/src/edma3resmgr.h>
+ + + + + + + + + + + + + + + + + + + + + + +

Defines

#define MAX_EDMA3_RM_INSTANCES   (8u)

Variables

const unsigned int EDMA3_MAX_RM_INSTANCES = 8u
EDMA3_RM_InstanceInitConfig userInstInitConfigArray [EDMA3_MAX_EDMA3_INSTANCES][MAX_EDMA3_RM_INSTANCES]
 Region Specific Configuration structure for EDMA3 controller, to provide region specific Information.
EDMA3_RM_Instance resMgrInstanceArray [EDMA3_MAX_EDMA3_INSTANCES][MAX_EDMA3_RM_INSTANCES]
EDMA3_RM_Instance * resMgrInstance = (EDMA3_RM_Instance *)resMgrInstanceArray
EDMA3_RM_InstanceInitConfig * userInitConfig = (EDMA3_RM_InstanceInitConfig *)userInstInitConfigArray
 Region Specific Configuration structure for EDMA3 controller, to provide region specific Information.
+EDMA3_RM_Instance * ptrRMIArray = (EDMA3_RM_Instance *)resMgrInstanceArray
+EDMA3_RM_InstanceInitConfig * ptrInitCfgArray = (EDMA3_RM_InstanceInitConfig *)userInstInitConfigArray
+

Detailed Description

+Source file for the Resource Manager, for internal data structures. +

+(C) Copyright 2006, Texas Instruments, Inc

+

Version:
0.1.0 Anuj Aggarwal - Created
+

Define Documentation

+ +
+
+ + + + +
#define MAX_EDMA3_RM_INSTANCES   (8u)
+
+
+ +

+Maximum Resource Manager Instances supported by the EDMA3 Package. USE THE SAME VALUE FOR BOTH THE DEFINE AND CONST UNSIGNED INT BELOW. +

+

+

Variable Documentation

+ +
+
+ + + + +
const unsigned int EDMA3_MAX_RM_INSTANCES = 8u
+
+
+ +

+Maximum Resource Manager Instances supported by the EDMA3 Package. +

Referenced by EDMA3_RM_create(), EDMA3_RM_getInstanceInitCfg(), EDMA3_RM_open(), edma3CCErrHandler(), and edma3TCErrHandler().

+ +
+

+ +

+
+ + + + +
EDMA3_RM_Instance* resMgrInstance = (EDMA3_RM_Instance *)resMgrInstanceArray
+
+
+ +

+Handles of EDMA3 Resource Manager Instances.

+Used to maintain information of the EDMA3 RM Instances for each HW controller. There could be a maximum of EDMA3_MAX_RM_INSTANCES instances per EDMA3 HW. +

+

+ +

+
+ + + + +
EDMA3_RM_Instance resMgrInstanceArray[EDMA3_MAX_EDMA3_INSTANCES][MAX_EDMA3_RM_INSTANCES]
+
+
+ +

+Handles of EDMA3 Resource Manager Instances.

+Used to maintain information of the EDMA3 RM Instances for each HW controller. There could be a maximum of EDMA3_MAX_RM_INSTANCES instances per EDMA3 HW. +

+

+ +

+
+ + + + +
EDMA3_RM_InstanceInitConfig* userInitConfig = (EDMA3_RM_InstanceInitConfig *)userInstInitConfigArray
+
+
+ +

+Region Specific Configuration structure for EDMA3 controller, to provide region specific Information. +

+This configuration info can also be provided by the user at run-time, while calling EDMA3_RM_open (). If not provided at run-time, this info will be taken from the config file "edma3_<PLATFORM_NAME>_cfg.c", for the specified platform. +

+

+ +

+
+ + + + +
EDMA3_RM_InstanceInitConfig userInstInitConfigArray[EDMA3_MAX_EDMA3_INSTANCES][MAX_EDMA3_RM_INSTANCES]
+
+
+ +

+Region Specific Configuration structure for EDMA3 controller, to provide region specific Information. +

+This configuration info can also be provided by the user at run-time, while calling EDMA3_RM_open (). If not provided at run-time, this info will be taken from the config file "edma3_<PLATFORM_NAME>_cfg.c", for the specified platform. +

+

+

+
Generated on Thu Oct 16 16:22:37 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/edma3resmgr_8c.html b/packages/ti/sdo/edma3/rm/docs/html/edma3resmgr_8c.html new file mode 100644 index 0000000..4a5c3f1 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/edma3resmgr_8c.html @@ -0,0 +1,1013 @@ + + +EDMA3 Resource Manager: edma3resmgr.c File Reference + + + + + +
+

edma3resmgr.c File Reference

EDMA3 Controller Resource Manager Interface Implementation. More... +

+#include <ti/sdo/edma3/rm/src/edma3resmgr.h>
+#include <assert.h>
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Defines

#define EDMA3_RM_RES_CLEAR_ERROR_STATUS_FOR_ALL_CHANNELS   (TRUE)
 EDMA3 Resource Manager behaviour of clearing CC ERROR interrupts. This macro controls the driver to enable/disable clearing of error status of all channels.
+#define EDMA3_RM_COMPL_HANDLER_RETRY_COUNT   (10u)
 EDMA3 Resource Manager retry count to check the pending interrupts inside ISR. This macro controls the driver to check the pending interrupt for 'n' number of times. Minumum value is 1.
+#define EDMA3_RM_CCERR_HANDLER_RETRY_COUNT   (10u)
 EDMA3 Resource Manager retry count to check the pending CC Error Interrupt inside ISR This macro controls the driver to check the pending CC Error interrupt for 'n' number of times. Minumum value is 1.

Functions

void lisrEdma3ComplHandler0 (unsigned int arg)
void lisrEdma3CCErrHandler0 (unsigned int arg)
void lisrEdma3TC0ErrHandler0 (unsigned int arg)
+void lisrEdma3TC1ErrHandler0 (unsigned int arg)
+void lisrEdma3TC2ErrHandler0 (unsigned int arg)
+void lisrEdma3TC3ErrHandler0 (unsigned int arg)
+void lisrEdma3TC4ErrHandler0 (unsigned int arg)
+void lisrEdma3TC5ErrHandler0 (unsigned int arg)
+void lisrEdma3TC6ErrHandler0 (unsigned int arg)
+void lisrEdma3TC7ErrHandler0 (unsigned int arg)
static void edma3ComplHandler (const EDMA3_RM_Obj *rmObj)
 Interrupt handler for successful transfer completion.
static void edma3CCErrHandler (const EDMA3_RM_Obj *rmObj)
 Interrupt handler for Channel Controller Error.
static void edma3TCErrHandler (const EDMA3_RM_Obj *rmObj, unsigned int tcNum)
 Interrupt handler for Transfer Controller Error.
void edma3MemSet (void *dst, unsigned char data, unsigned int len)
void edma3MemCpy (void *dst, const void *src, unsigned int len)
static void edma3GlobalRegionInit (unsigned int phyCtrllerInstId)
static void edma3ShadowRegionInit (const EDMA3_RM_Instance *pRMInstance)
static int findBitInWord (int source, unsigned int start, unsigned short bit)
static int findBit (EDMA3_RM_ResType resType, unsigned int start, unsigned int end, unsigned short bit)
static EDMA3_RM_Result allocAnyContigRes (EDMA3_RM_ResType resType, unsigned int numResources, unsigned int *positionRes)
static EDMA3_RM_Result gblChngAllocContigRes (EDMA3_RM_Instance *rmInstance, const EDMA3_RM_ResDesc *firstResIdObj, unsigned int numResources)
EDMA3_RM_Result EDMA3_RM_create (unsigned int phyCtrllerInstId, const EDMA3_RM_GblConfigParams *gblCfgParams, const void *miscParam)
 Create EDMA3 Resource Manager Object.
EDMA3_RM_Result EDMA3_RM_delete (unsigned int phyCtrllerInstId, const void *param)
 Delete EDMA3 Resource Manager Object.
EDMA3_RM_Handle EDMA3_RM_open (unsigned int phyCtrllerInstId, const EDMA3_RM_Param *initParam, EDMA3_RM_Result *errorCode)
 Open EDMA3 Resource Manager Instance.
EDMA3_RM_Result EDMA3_RM_close (EDMA3_RM_Handle hEdmaResMgr, const void *param)
 Close EDMA3 Resource Manager Instance.
EDMA3_RM_Result EDMA3_RM_allocResource (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *resObj)
 This API is used to allocate specified EDMA3 Resources like DMA/QDMA channel, PaRAM Set or TCC.
EDMA3_RM_Result EDMA3_RM_freeResource (EDMA3_RM_Handle hEdmaResMgr, const EDMA3_RM_ResDesc *resObj)
 This API is used to free previously allocated EDMA3 Resources like DMA/QDMA channel, PaRAM Set or TCC.
EDMA3_RM_Result EDMA3_RM_allocLogicalChannel (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *lChObj, unsigned int *pParam, unsigned int *pTcc)
 Request a DMA/QDMA/Link channel.
EDMA3_RM_Result EDMA3_RM_freeLogicalChannel (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *lChObj)
 This API is used to free the specified channel (DMA/QDMA/Link) and its associated resources (PaRAM Set, TCC etc).
EDMA3_RM_Result EDMA3_RM_mapEdmaChannel (EDMA3_RM_Handle hEdmaResMgr, unsigned int channelId, unsigned int paRAMId)
 Bind the resources DMA Channel and PaRAM Set. Both the DMA channel and the PaRAM set should be previously allocated. If they are not, this API will result in error.
EDMA3_RM_Result EDMA3_RM_mapQdmaChannel (EDMA3_RM_Handle hEdmaResMgr, unsigned int channelId, unsigned int paRAMId, EDMA3_RM_QdmaTrigWord trigWord)
 Bind the resources QDMA Channel and PaRAM Set. Also, Set the trigger word for the QDMA channel. Both the QDMA channel and the PaRAM set should be previously allocated. If they are not, this API will result in error.
EDMA3_RM_Result EDMA3_RM_registerTccCb (EDMA3_RM_Handle hEdmaResMgr, const EDMA3_RM_ResDesc *channelObj, unsigned int tcc, EDMA3_RM_TccCallback tccCb, void *cbData)
 Register Interrupt / Completion Handler for a given TCC.
EDMA3_RM_Result EDMA3_RM_unregisterTccCb (EDMA3_RM_Handle hEdmaResMgr, const EDMA3_RM_ResDesc *channelObj)
 Unregister the previously registered callback function against a DMA/QDMA channel.
EDMA3_RM_Result EDMA3_RM_allocContiguousResource (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *firstResIdObj, unsigned int numResources)
 Allocate a contiguous region of specified EDMA3 Resource like DMA channel, QDMA channel, PaRAM Set or TCC.
EDMA3_RM_Result EDMA3_RM_freeContiguousResource (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *firstResIdObj, unsigned int numResources)
 Free a contiguous region of specified EDMA3 Resource like DMA channel, QDMA channel, PaRAM Set or TCC, previously allocated.
EDMA3_RM_Result EDMA3_RM_setCCRegister (EDMA3_RM_Handle hEdmaResMgr, unsigned int regOffset, unsigned int newRegValue)
 Set the Channel Controller (CC) Register value.
EDMA3_RM_Result EDMA3_RM_getCCRegister (EDMA3_RM_Handle hEdmaResMgr, unsigned int regOffset, unsigned int *regValue)
 Get the Channel Controller (CC) Register value.
EDMA3_RM_Result EDMA3_RM_waitAndClearTcc (EDMA3_RM_Handle hEdmaResMgr, unsigned int tccNo)
 Wait for a transfer completion interrupt to occur and clear it.
EDMA3_RM_Result EDMA3_RM_checkAndClearTcc (EDMA3_RM_Handle hEdmaResMgr, unsigned int tccNo, unsigned short *tccStatus)
 Returns the status of a previously initiated transfer.
EDMA3_RM_Result EDMA3_RM_setPaRAM (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *lChObj, const EDMA3_RM_PaRAMRegs *newPaRAM)
 Copy the user specified PaRAM Set onto the PaRAM Set associated with the logical channel (DMA/QDMA/Link).
EDMA3_RM_Result EDMA3_RM_getPaRAM (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *lChObj, EDMA3_RM_PaRAMRegs *currPaRAM)
 Retrieve existing PaRAM set associated with specified logical channel (DMA/QDMA/Link).
EDMA3_RM_Result EDMA3_RM_getPaRAMPhyAddr (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *lChObj, unsigned int *paramPhyAddr)
 Get the PaRAM Set Physical Address associated with a logical channel.
EDMA3_RM_Result EDMA3_RM_getBaseAddress (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_Cntrlr_PhyAddr controllerId, unsigned int *phyAddress)
 Get the Channel Controller or Transfer Controller (n) Physical Address.
EDMA3_RM_Result EDMA3_RM_getGblConfigParams (unsigned int phyCtrllerInstId, EDMA3_RM_GblConfigParams *gblCfgParams)
 Get the SoC specific configuration structure for the EDMA3 Hardware.
EDMA3_RM_Result EDMA3_RM_getInstanceInitCfg (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_InstanceInitConfig *instanceInitConfig)
 Get the RM Instance specific configuration structure for different EDMA3 resources' usage (owned resources, reserved resources etc).
EDMA3_RM_Result EDMA3_RM_Ioctl (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_IoctlCmd cmd, void *cmdArg, void *param)
 EDMA3 Resource Manager IOCTL.

Variables

const unsigned int EDMA3_MAX_RM_INSTANCES
EDMA3_RM_GblConfigParams edma3GblCfgParams [EDMA3_MAX_EDMA3_INSTANCES]
 Static Configuration structure for EDMA3 controller, to provide Global SoC specific Information.
+EDMA3_RM_InstanceInitConfig defInstInitConfig [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS]
 Default Static Region Specific Configuration structure for EDMA3 controller, to provide region specific Information.
EDMA3_RM_InstanceInitConfig * userInitConfig
 Region Specific Configuration structure for EDMA3 controller, to provide region specific Information.
+EDMA3_RM_InstanceInitConfig * ptrInitCfgArray
EDMA3_RM_Instance * resMgrInstance
+EDMA3_RM_Instance * ptrRMIArray
EDMA3_RM_Obj resMgrObj [EDMA3_MAX_EDMA3_INSTANCES]
 EDMA3 Resource Manager Objects, tied to each EDMA3 HW Controller.
static unsigned int edma3DmaChTccMapping [EDMA3_MAX_DMA_CH]
static unsigned int edma3QdmaChTccMapping [EDMA3_MAX_QDMA_CH]
static EDMA3_RM_TccCallbackParams edma3IntrParams [EDMA3_MAX_TCC]
static EDMA3_RM_RegionId edma3RegionId = EDMA3_MAX_REGIONS
static unsigned short masterExists = FALSE
unsigned int edma3NumPaRAMSets = EDMA3_MAX_PARAM_SETS
static unsigned int allocatedTCCs [2u] = {0x0u, 0x0u}
static unsigned int contiguousDmaRes [EDMA3_MAX_DMA_CHAN_DWRDS] = {0x0u, 0x0u}
static unsigned int contiguousQdmaRes [EDMA3_MAX_QDMA_CHAN_DWRDS] = {0x0u}
static unsigned int contiguousTccRes [EDMA3_MAX_TCC_DWRDS] = {0x0u, 0x0u}
static unsigned int contiguousParamRes [EDMA3_MAX_PARAM_DWRDS]
static EDMA3_RM_ChBoundResources edma3RmChBoundRes [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_LOGICAL_CH]
 Resources bound to a Channel.
+

Detailed Description

+EDMA3 Controller Resource Manager Interface Implementation. +

+This file contains Resource Manager Implementation for the EDMA3 Controller.

+(C) Copyright 2006, Texas Instruments, Inc

+

Version:
0.0.1 Purushotam Kumar - Created 0.1.0 Joseph Fernandez - Made generic
    +
  • Added documentation
  • Moved SoC specific defines to SoC specific header. 0.2.0 Anuj Aggarwal - Modified it for EDMA3 package
  • Added multiple instances capability 0.2.1 Anuj Aggarwal - Modified it for more run time configuration.
  • Made EDMA3 package OS independent. 0.2.2 Anuj Aggarwal - Critical section handling code modification. Uses semaphore and interrupts disabling mechanism for resource sharing. 0.3.0 Anuj Aggarwal - Renamed EDMA3_DVR to EDMA3_DRV
  • IPR bit clearing in RM ISR issue fixed.
  • Sample application made generic 0.3.1 Anuj Aggarwal - Added DMA/QDMA Channel to TCC mapping, to fix QDMA missed event issue. 0.3.2 Anuj Aggarwal - Added support for POLL mode
  • Added a new API to modify the CC Register. 1.0.0 Anuj Aggarwal - Fixed resource allocation related bugs. 1.0.0.1 Anuj Aggarwal - Fixed spurious missed event generation related bug. 1.0.0.2 Anuj Aggarwal - Made the EDMA3 package RTSC compliant. 1.0.0.3 Anuj Aggarwal - Changed the directory structure as per RTSC standard. 1.01.00.01 Anuj Aggarwal - a) Added new APIs to allocate logical channels b) Created EDMA3 config files for different platforms c) Misc changes 1.02.00.01 Anuj Aggarwal - a) Added DM6467 support b) Fixed some MRs 1.03.00.01 Anuj Aggarwal - a) Added non-RTSC PJT files b) IOCTL Interface added. c) Fixed some MRs. 1.04 Anuj Aggarwal - a) Added new IOCTLs and APIs. b) Number of maximum Resource Manager Instances is configurable. c) Header files modified to have extern "C" declarations.
+
+

Define Documentation

+ +
+
+ + + + +
#define EDMA3_RM_RES_CLEAR_ERROR_STATUS_FOR_ALL_CHANNELS   (TRUE)
+
+
+ +

+EDMA3 Resource Manager behaviour of clearing CC ERROR interrupts. This macro controls the driver to enable/disable clearing of error status of all channels. +

+Define NDEBUG to ignore assert(). NDEBUG should be defined before including assert.h header file. On disabling this (with value 0x0), the channels owned by the region is cleared and its expected that some other entity is responsible for clearing the error status for channels not owned.

+Its recomended that this flag is a positive value, to ensure that error flags are cleared for all the channels. +

+

+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
static EDMA3_RM_Result allocAnyContigRes (EDMA3_RM_ResType  resType,
unsigned int  numResources,
unsigned int *  positionRes 
) [static]
+
+
+ +

+If successful, this function returns EDMA3_RM_SOK and the position of first available resource in 'positionRes'. Else returns error. +

+Algorithm used for finding N contiguous resources. In the resources' array, '1' means available and '0' means not-available. Step a) Find first '1' starting from 'start'. If successful, store it in first_one, else return error. Step b) Find first '0' starting from (first_one+1) to 'end'. If successful, store returned value in next_zero. If '0' could not be located, it means all the resources are available. Store 'end' (i.e. the last resource id) in next_zero. Step c) Count the number of contiguous resources available by subtracting first_one from next_zero. Step d) If result < N, do the whole process again untill you reach end. Else you have found enough resources, return success. +

References EDMA3_MAX_DMA_CH, EDMA3_MAX_QDMA_CH, EDMA3_MAX_TCC, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE, EDMA3_RM_RES_DMA_CHANNEL, EDMA3_RM_RES_PARAM_SET, EDMA3_RM_RES_QDMA_CHANNEL, EDMA3_RM_RES_TCC, EDMA3_RM_SOK, edma3NumPaRAMSets, findBit(), and NULL.

+ +

Referenced by EDMA3_RM_allocContiguousResource().

+ +
+

+ +

+
+ + + + + + + + + +
static void edma3CCErrHandler (const EDMA3_RM_Obj *  rmObj  )  [static]
+
+
+ +

+Interrupt handler for Channel Controller Error. +

+Interrupt Handler for the Channel Controller Error interrupt

+

Note:
This function first disables its own interrupt to make it non- entrant. Later, after calling all the callback functions, it re-enables its own interrupt.
+
Returns:
None.
+ +

+Using the 'index' value (basically the DMA channel), fetch the corresponding TCC value, mapped to this DMA channel.

+Ensure that the mapped tcc is valid and the call back is not NULL

+TCC owned and allocated by RM. Write to EMCR to clear the corresponding EMR bits.

+DMA channel not owned by the RM instance. Check the global error interrupt clearing option. If it is TRUE, clear the error interupt else leave it like that.

+Using the 'index' value (basically the DMA channel), fetch the corresponding TCC value, mapped to this DMA channel.

+Ensure that the mapped tcc is valid and the call back is not NULL

+TCC owned and allocated by RM. Write to EMCR to clear the corresponding EMR bits.

+DMA channel not owned by the RM instance. Check the global error interrupt clearing option. If it is TRUE, clear the error interupt else leave it like that.

+TCC NOT owned by RM. Write to EMCRH to clear the corresponding EMRH bits.

+Using the 'index' value (basically the QDMA channel), fetch the corresponding TCC value, mapped to this QDMA channel.

+QDMA channel not owned by the RM instance. Check the global error interrupt clearing option. If it is TRUE, clear the error interupt else leave the ISR.

+Queue threshold error for queue 'evtqueNum' raised. Inform all the RM instances working on this region about the error by calling their global callback functions.

+Transfer completion code error raised. Inform all the RM instances working on this region about the error by calling their global callback functions.

+Read the error registers again. If any interrupt is pending, write the EEVAL register. Moreover, according to the global error interrupt clearing option, check either error bits associated with all the DMA/QDMA channels (option is SET) OR check error bits associated with owned DMA/QDMA channels. +

References EDMA3_MAX_RM_INSTANCES, EDMA3_MAX_TCC, EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR, EDMA3_RM_CCERR_HANDLER_RETRY_COUNT, EDMA3_RM_E_CC_DMA_EVT_MISS, EDMA3_RM_E_CC_QDMA_EVT_MISS, EDMA3_RM_E_CC_QUE_THRES_EXCEED, EDMA3_RM_E_CC_TCC, edma3DmaChTccMapping, edma3OsProtectEntry(), edma3OsProtectExit(), edma3QdmaChTccMapping, edma3RegionId, EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_GblErrCallbackParams::gblerrCb, EDMA3_RM_Param::gblerrCbParams, EDMA3_RM_GblErrCallbackParams::gblerrData, EDMA3_RM_GblConfigParams::globalRegs, EDMA3_RM_Instance::initParam, NULL, EDMA3_RM_GblConfigParams::numEvtQueue, EDMA3_RM_Obj::numOpens, EDMA3_RM_InstanceInitConfig::ownDmaChannels, EDMA3_RM_InstanceInitConfig::ownQdmaChannels, EDMA3_RM_Obj::phyCtrllerInstId, EDMA3_RM_Param::regionId, EDMA3_RM_Param::rmInstInitConfig, EDMA3_RM_TccCallbackParams::tccCb, and TRUE.

+ +

Referenced by lisrEdma3CCErrHandler0().

+ +
+

+ +

+
+ + + + + + + + + +
static void edma3ComplHandler (const EDMA3_RM_Obj *  rmObj  )  [static]
+
+
+ +

+Interrupt handler for successful transfer completion. +

+Interrupt Handler for the Transfer Completion interrupt

+edma3ComplHandler

Note:
This function first disables its own interrupt to make it non- entrant. Later, after calling all the callback functions, it re-enables its own interrupt.
+
Returns:
None.
+ +

+Since an interrupt has found, we have to make sure that this interrupt (TCC) belongs to the TCCs allocated by us only. It might happen that someone else, who is using EDMA3 also, is the owner of this interrupt channel i.e. the TCC. For this, use the allocatedTCCs[], to check which all interrupt channels are owned by the EDMA3 RM Instances.

+Choose interrupts coming from our allocated TCCs and MASK remaining ones.

+If the user has not given any callback function while requesting the TCC, its TCC specific bit in the IPR register will NOT be cleared.

+Choose interrupts coming from our allocated TCCs and MASK remaining ones.

+If the user has not given any callback function while requesting the TCC, its TCC specific bit in the IPRH register will NOT be cleared. +

References allocatedTCCs, EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION, EDMA3_RM_COMPL_HANDLER_RETRY_COUNT, EDMA3_RM_XFER_COMPLETE, edma3OsProtectEntry(), edma3OsProtectExit(), edma3RegionId, EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_GblConfigParams::globalRegs, NULL, EDMA3_RM_TccCallbackParams::tccCb, and TRUE.

+ +

Referenced by lisrEdma3ComplHandler0().

+ +
+

+ +

+
+ + + + + + + + + +
static void edma3GlobalRegionInit (unsigned int  phyCtrllerInstId  )  [static]
+
+
+ +

+Initialization of the Global region registers of the EDMA3 Controller +

+Set TC Priority among system-wide bus-masters and Queue Watermark Level +

References EDMA3_MAX_EDMA3_INSTANCES, EDMA3_RM_QUEPRI_CLR_MASK, EDMA3_RM_QUEPRI_SET_MASK, EDMA3_RM_QUEWMTHR_SET_MASK, EDMA3_RM_SET_ALL_BITS, and NULL.

+ +

Referenced by EDMA3_RM_create().

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void edma3MemCpy (void *  dst,
const void *  src,
unsigned int  len 
)
+
+
+ +

+Local MemCpy function +

References NULL.

+ +

Referenced by EDMA3_RM_create(), EDMA3_RM_getGblConfigParams(), EDMA3_RM_getInstanceInitCfg(), EDMA3_RM_getPaRAM(), EDMA3_RM_open(), and EDMA3_RM_setPaRAM().

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void edma3MemSet (void *  dst,
unsigned char  data,
unsigned int  len 
)
+
+
+ +

+Local MemSet function +

References NULL.

+ +

Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_close(), EDMA3_RM_create(), EDMA3_RM_delete(), EDMA3_RM_open(), and gblChngAllocContigRes().

+ +
+

+ +

+
+ + + + + + + + + +
static void edma3ShadowRegionInit (const EDMA3_RM_Instance *  pRMInstance  )  [static]
+
+
+ +

+Initialization of the Shadow region registers of the EDMA3 Controller +

References EDMA3_OS_PROTECT_INTERRUPT, edma3OsProtectEntry(), edma3OsProtectExit(), EDMA3_RM_Instance::initParam, NULL, EDMA3_RM_InstanceInitConfig::ownDmaChannels, EDMA3_RM_InstanceInitConfig::ownQdmaChannels, EDMA3_RM_InstanceInitConfig::ownTccs, EDMA3_RM_Obj::phyCtrllerInstId, EDMA3_RM_Instance::pResMgrObjHandle, EDMA3_RM_Param::regionId, and EDMA3_RM_Param::rmInstInitConfig.

+ +

Referenced by EDMA3_RM_open().

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
static void edma3TCErrHandler (const EDMA3_RM_Obj *  rmObj,
unsigned int  tcNum 
) [static]
+
+
+ +

+Interrupt handler for Transfer Controller Error. +

+Interrupt Handler for the Transfer Controller Error interrupt

+

Note:
This function first disables its own interrupt to make it non- entrant. Later, after calling all the callback functions, it re-enables its own interrupt.
+
Returns:
None.
+ +

+EDMA3TC has detected an error at source or destination address. Error information can be read from the error details register (ERRDET).

+Inform all the RM instances working on this region about the error by calling their global callback functions.

+Inform all the RM instances working on this region about the error by calling their global callback functions. +

References EDMA3_MAX_RM_INSTANCES, EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR, EDMA3_RM_E_TC_INVALID_ADDR, EDMA3_RM_E_TC_MEM_LOCATION_READ_ERROR, EDMA3_RM_E_TC_MEM_LOCATION_WRITE_ERROR, EDMA3_RM_E_TC_TR_ERROR, edma3OsProtectEntry(), edma3OsProtectExit(), edma3RegionId, EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_GblErrCallbackParams::gblerrCb, EDMA3_RM_Param::gblerrCbParams, EDMA3_RM_GblErrCallbackParams::gblerrData, EDMA3_RM_Instance::initParam, NULL, EDMA3_RM_Obj::numOpens, EDMA3_RM_Obj::phyCtrllerInstId, EDMA3_RM_Param::regionId, and EDMA3_RM_GblConfigParams::tcRegs.

+ +

Referenced by lisrEdma3TC0ErrHandler0(), lisrEdma3TC1ErrHandler0(), lisrEdma3TC2ErrHandler0(), lisrEdma3TC3ErrHandler0(), lisrEdma3TC4ErrHandler0(), lisrEdma3TC5ErrHandler0(), lisrEdma3TC6ErrHandler0(), and lisrEdma3TC7ErrHandler0().

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
static int findBit (EDMA3_RM_ResType  resType,
unsigned int  start,
unsigned int  end,
unsigned short  bit 
) [static]
+
+
+ +

+Finds a particular bit ('0' or '1') in the specified resources' array from 'start' to 'end'. If found, returns the position, else return -1. +

+job is to find 'bit' in an array[start_index:end_index] algo used: first search in array[start_index] then search in array[start_index + 1 : end_index - 1] then search in array[end_index] +

References contiguousDmaRes, contiguousParamRes, contiguousQdmaRes, contiguousTccRes, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_RES_DMA_CHANNEL, EDMA3_RM_RES_PARAM_SET, EDMA3_RM_RES_QDMA_CHANNEL, EDMA3_RM_RES_TCC, EDMA3_RM_SOK, and findBitInWord().

+ +

Referenced by allocAnyContigRes().

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
static int findBitInWord (int  source,
unsigned int  start,
unsigned short  bit 
) [static]
+
+
+ +

+Finds a particular bit ('0' or '1') in the particular word from 'start'. If found, returns the position, else return -1. +

Referenced by findBit().

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
static EDMA3_RM_Result gblChngAllocContigRes (EDMA3_RM_Instance *  rmInstance,
const EDMA3_RM_ResDesc *  firstResIdObj,
unsigned int  numResources 
) [static]
+
+
+ +

+Starting from 'firstResIdObj', this function makes the next 'numResources' Resources non-available for future. Also, it does some global resisters' setting also. +

+Enable the DMA channel in the DRAE/DRAEH registers also.

+Enable the QDMA channel in the QRAE register also.

+Enable the Interrupt channel in the DRAE/DRAEH registers. Also, If the region id coming from this RM instance is same as the Master RM Instance's region id, only then we will be getting the interrupts on the same side. So save the TCC in the allocatedTCCs[] array.

+Also, make the actual PARAM Set NULL, checking the flag whether it is required or not. +

References allocatedTCCs, EDMA3_RM_Instance::avlblDmaChannels, EDMA3_RM_Instance::avlblPaRAMSets, EDMA3_RM_Instance::avlblQdmaChannels, EDMA3_RM_Instance::avlblTccs, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_RES_DMA_CHANNEL, EDMA3_RM_RES_PARAM_SET, EDMA3_RM_RES_QDMA_CHANNEL, EDMA3_RM_RES_TCC, EDMA3_RM_SOK, edma3MemSet(), edma3RegionId, EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_GblConfigParams::globalRegs, EDMA3_RM_Instance::initParam, NULL, EDMA3_RM_Instance::paramInitRequired, EDMA3_RM_Instance::pResMgrObjHandle, EDMA3_RM_Param::regionId, EDMA3_RM_ResDesc::resId, TRUE, and EDMA3_RM_ResDesc::type.

+ +

Referenced by EDMA3_RM_allocContiguousResource().

+ +
+

+ +

+
+ + + + + + + + + +
void lisrEdma3CCErrHandler0 (unsigned int  arg  ) 
+
+
+ +

+EDMA3 Instance 0 CC Error Interrupt Service Routine +

+

+ +

+
+ + + + + + + + + +
void lisrEdma3ComplHandler0 (unsigned int  arg  ) 
+
+
+ +

+EDMA3 Instance 0 Completion Handler Interrupt Service Routine +

+

+ +

+
+ + + + + + + + + +
void lisrEdma3TC0ErrHandler0 (unsigned int  arg  ) 
+
+
+ +

+EDMA3 Instance 0 TC[0-7] Error Interrupt Service Routines for a maximum of 8 TCs (Transfer Controllers). +

+

+

Variable Documentation

+ +
+
+ + + + +
unsigned int allocatedTCCs[2u] = {0x0u, 0x0u} [static]
+
+
+ +

+The list of Interrupt Channels which get allocated while requesting the TCC. It will be used while checking the IPR/IPRH bits in the RM ISR. +

Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_delete(), EDMA3_RM_freeResource(), edma3ComplHandler(), and gblChngAllocContigRes().

+ +
+

+ +

+
+ + + + +
unsigned int contiguousDmaRes[EDMA3_MAX_DMA_CHAN_DWRDS] = {0x0u, 0x0u} [static]
+
+
+ +

+Arrays ownDmaChannels[], resvdDmaChannels and avlblDmaChannels will be ANDed and stored in this array. It will be referenced in EDMA3_RM_allocContiguousResource () to look for contiguous resources. +

Referenced by EDMA3_RM_allocContiguousResource(), and findBit().

+ +
+

+ +

+
+ + + + +
unsigned int contiguousParamRes[EDMA3_MAX_PARAM_DWRDS] [static]
+
+
+ +

+Arrays ownDmaChannels[], resvdDmaChannels and avlblDmaChannels will be ANDed and stored in this array. It will be referenced in EDMA3_RM_allocContiguousResource () to look for contiguous resources. +

Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_create(), and findBit().

+ +
+

+ +

+
+ + + + +
unsigned int contiguousQdmaRes[EDMA3_MAX_QDMA_CHAN_DWRDS] = {0x0u} [static]
+
+
+ +

+Arrays ownDmaChannels[], resvdDmaChannels and avlblDmaChannels will be ANDed and stored in this array. It will be referenced in EDMA3_RM_allocContiguousResource () to look for contiguous resources. +

Referenced by EDMA3_RM_allocContiguousResource(), and findBit().

+ +
+

+ +

+
+ + + + +
unsigned int contiguousTccRes[EDMA3_MAX_TCC_DWRDS] = {0x0u, 0x0u} [static]
+
+
+ +

+Arrays ownDmaChannels[], resvdDmaChannels and avlblDmaChannels will be ANDed and stored in this array. It will be referenced in EDMA3_RM_allocContiguousResource () to look for contiguous resources. +

Referenced by EDMA3_RM_allocContiguousResource(), and findBit().

+ +
+

+ +

+
+ + + + +
const unsigned int EDMA3_MAX_RM_INSTANCES
+
+
+ +

+Maximum Resource Manager Instances supported by the EDMA3 Package. +

Referenced by EDMA3_RM_create(), EDMA3_RM_getInstanceInitCfg(), EDMA3_RM_open(), edma3CCErrHandler(), and edma3TCErrHandler().

+ +
+

+ +

+
+ + + + +
unsigned int edma3DmaChTccMapping[EDMA3_MAX_DMA_CH] [static]
+
+
+ +

+Global Array to store the mapping between DMA channels and Interrupt channels i.e. TCCs. DMA channel X can use any TCC Y. Transfer completion interrupt will occur on the TCC Y (IPR/IPRH Register, bit Y), but error interrupt will occur on DMA channel X (EMR/EMRH register, bit X). In that scenario, this DMA channel <-> TCC mapping will be used to point to the correct callback function. +

Referenced by EDMA3_RM_create(), EDMA3_RM_registerTccCb(), EDMA3_RM_unregisterTccCb(), and edma3CCErrHandler().

+ +
+

+ +

+
+ + + + +
EDMA3_RM_GblConfigParams edma3GblCfgParams[EDMA3_MAX_EDMA3_INSTANCES]
+
+
+ +

+Static Configuration structure for EDMA3 controller, to provide Global SoC specific Information. +

+This configuration info can also be provided by the user at run-time, while calling EDMA3_RM_create (). If not provided at run-time, this info will be taken from the config file "edma3_<PLATFORM_NAME>_cfg.c", for the specified platform. +

+

+ +

+
+ + + + +
EDMA3_RM_TccCallbackParams edma3IntrParams[EDMA3_MAX_TCC] [static]
+
+
+ +

+Global Array to maintain the Callback details registered against a particular TCC. Used to call the callback functions linked to the particular channel. +

+

+ +

+
+ + + + +
unsigned int edma3NumPaRAMSets = EDMA3_MAX_PARAM_SETS
+
+
+ +

+Number of PaRAM Sets actually present on the SoC. This will be updated while creating the Resource Manager Object. +

Referenced by allocAnyContigRes(), EDMA3_RM_allocLogicalChannel(), EDMA3_RM_create(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_getPaRAM(), EDMA3_RM_getPaRAMPhyAddr(), and EDMA3_RM_setPaRAM().

+ +
+

+ +

+
+ + + + +
unsigned int edma3QdmaChTccMapping[EDMA3_MAX_QDMA_CH] [static]
+
+
+ +

+Global Array to store the mapping between QDMA channels and Interrupt channels i.e. TCCs. QDMA channel X can use any TCC Y. Transfer completion interrupt will occur on the TCC Y (IPR/IPRH Register, bit Y), but error interrupt will occur on QDMA channel X (QEMR register, bit X). In that scenario, this QDMA channel <-> TCC mapping will be used to point to the correct callback function. +

Referenced by EDMA3_RM_create(), EDMA3_RM_registerTccCb(), EDMA3_RM_unregisterTccCb(), and edma3CCErrHandler().

+ +
+

+ +

+
+ + + + +
EDMA3_RM_RegionId edma3RegionId = EDMA3_MAX_REGIONS [static]
+
+
+ +

+edma3RegionId will be updated ONCE using the parameter regionId passed to the EDMA3_RM_open() function, for the Master RM instance (one who configures the Global Registers). This global variable will be used within the Interrupt handlers to know which shadow region registers to access. All other interrupts coming from other shadow regions will not be handled. +

Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_close(), EDMA3_RM_freeResource(), EDMA3_RM_open(), edma3CCErrHandler(), edma3ComplHandler(), edma3TCErrHandler(), and gblChngAllocContigRes().

+ +
+

+ +

+
+ + + + +
EDMA3_RM_ChBoundResources edma3RmChBoundRes[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_LOGICAL_CH] [static]
+
+
+ +

+Resources bound to a Channel. +

+When a request for a channel is made, the resources PaRAM Set and TCC get bound to that channel. This information is needed internally by the resource manager, when a request is made to free the channel, to free up the channel-associated resources. +

+

+ +

+
+ + + + +
unsigned short masterExists = FALSE [static]
+
+
+ +

+masterExists will be updated when the Master RM Instance modifies the Global EDMA3 configuration registers. It is used to prevent any other Master RM Instance creation. +

Referenced by EDMA3_RM_close(), and EDMA3_RM_open().

+ +
+

+ +

+
+ + + + +
EDMA3_RM_Instance* resMgrInstance
+
+
+ +

+Handles of EDMA3 Resource Manager Instances.

+Used to maintain information of the EDMA3 RM Instances for each HW controller. There could be a maximum of EDMA3_MAX_RM_INSTANCES instances per EDMA3 HW. +

+

+ +

+
+ + + + +
EDMA3_RM_Obj resMgrObj[EDMA3_MAX_EDMA3_INSTANCES]
+
+
+ +

+EDMA3 Resource Manager Objects, tied to each EDMA3 HW Controller. +

+Typically one RM object will cater to one EDMA3 HW controller and will have all the global config information. +

+

+ +

+
+ + + + +
EDMA3_RM_InstanceInitConfig* userInitConfig
+
+
+ +

+Region Specific Configuration structure for EDMA3 controller, to provide region specific Information. +

+This configuration info can also be provided by the user at run-time, while calling EDMA3_RM_open (). If not provided at run-time, this info will be taken from the config file "edma3_<PLATFORM_NAME>_cfg.c", for the specified platform. +

+

+

+
Generated on Thu Oct 16 16:22:38 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/edma3resmgr_8h-source.html b/packages/ti/sdo/edma3/rm/docs/html/edma3resmgr_8h-source.html new file mode 100644 index 0000000..943389e --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/edma3resmgr_8h-source.html @@ -0,0 +1,186 @@ + + +EDMA3 Resource Manager: edma3resmgr.h Source File + + + + + +
Generated on Thu Oct 16 16:21:27 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/edma3resmgr_8h.html b/packages/ti/sdo/edma3/rm/docs/html/edma3resmgr_8h.html new file mode 100644 index 0000000..271dbfc --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/edma3resmgr_8h.html @@ -0,0 +1,413 @@ + + +EDMA3 Resource Manager: edma3resmgr.h File Reference + + + + + +
+

edma3resmgr.h File Reference

EDMA3 Resource Manager Internal header file. More... +

+#include <ti/sdo/edma3/rm/edma3_rm.h>
+#include <ti/sdo/edma3/rm/src/edma3_rl_cc.h>
+#include <ti/sdo/edma3/rm/src/edma3_rl_tc.h>
+ +

+Go to the source code of this file. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Data Structures

struct  EDMA3_RM_Obj
 EDMA3 Hardware Instance Configuration Structure. More...
struct  EDMA3_RM_Instance
 EDMA3 RM Instance Specific Configuration Structure. More...
struct  EDMA3_RM_ChBoundResources
 EDMA3 Channel-Bound resources. More...
struct  EDMA3_RM_TccCallbackParams
 TCC Callback - Caters to channel specific status reporting. More...

Defines

#define EDMA3_RM_SET_ALL_BITS   (0xFFFFFFFFu)
#define EDMA3_RM_DCH_PARAM_CLR_MASK   (~EDMA3_CCRL_DCHMAP_PAENTRY_MASK)
#define EDMA3_RM_DCH_PARAM_SET_MASK(paRAMId)   (((EDMA3_CCRL_DCHMAP_PAENTRY_MASK >> EDMA3_CCRL_DCHMAP_PAENTRY_SHIFT) & (paRAMId)) << EDMA3_CCRL_DCHMAP_PAENTRY_SHIFT)
#define EDMA3_RM_QCH_PARAM_CLR_MASK   (~EDMA3_CCRL_QCHMAP_PAENTRY_MASK)
#define EDMA3_RM_QCH_PARAM_SET_MASK(paRAMId)   (((EDMA3_CCRL_QCHMAP_PAENTRY_MASK >> EDMA3_CCRL_QCHMAP_PAENTRY_SHIFT) & (paRAMId)) << EDMA3_CCRL_QCHMAP_PAENTRY_SHIFT)
#define EDMA3_RM_QCH_TRWORD_CLR_MASK   (~EDMA3_CCRL_QCHMAP_TRWORD_MASK)
#define EDMA3_RM_QCH_TRWORD_SET_MASK(paRAMId)   (((EDMA3_CCRL_QCHMAP_TRWORD_MASK >> EDMA3_CCRL_QCHMAP_TRWORD_SHIFT) & (paRAMId)) << EDMA3_CCRL_QCHMAP_TRWORD_SHIFT)
#define EDMA3_RM_QUEPRI_CLR_MASK(queNum)   (~(EDMA3_CCRL_QUEPRI_PRIQ0_MASK << ((queNum) * EDMA3_CCRL_QUEPRI_PRIQ1_SHIFT)))
#define EDMA3_RM_QUEPRI_SET_MASK(queNum, quePri)   ((EDMA3_CCRL_QUEPRI_PRIQ0_MASK & (quePri)) << ((queNum) * EDMA3_CCRL_QUEPRI_PRIQ1_SHIFT))
#define EDMA3_RM_QUEWMTHR_CLR_MASK(queNum)   (~(EDMA3_CCRL_QWMTHRA_Q0_MASK << ((queNum) * EDMA3_CCRL_QWMTHRA_Q1_SHIFT)))
#define EDMA3_RM_QUEWMTHR_SET_MASK(queNum, queThr)   ((EDMA3_CCRL_QWMTHRA_Q0_MASK & (queThr)) << ((queNum) * EDMA3_CCRL_QWMTHRA_Q1_SHIFT))
#define EDMA3_RM_OPT_TCC_CLR_MASK   (~EDMA3_CCRL_OPT_TCC_MASK)
#define EDMA3_RM_OPT_TCC_SET_MASK(tcc)   (((EDMA3_CCRL_OPT_TCC_MASK >> EDMA3_CCRL_OPT_TCC_SHIFT) & (tcc)) << EDMA3_CCRL_OPT_TCC_SHIFT)
#define EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD   (5u)
#define EDMA3_RM_DMA_CH_MAX_VAL   (EDMA3_MAX_DMA_CH - 1u)
#define EDMA3_RM_LINK_CH_MIN_VAL   (EDMA3_MAX_DMA_CH)
#define EDMA3_RM_LINK_CH_MAX_VAL   (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS - 1u)
#define EDMA3_RM_QDMA_CH_MIN_VAL   (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS)
#define EDMA3_RM_QDMA_CH_MAX_VAL   (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS + EDMA3_MAX_QDMA_CH - 1u)
#define EDMA3_RM_LOG_CH_MAX_VAL   (EDMA3_RM_QDMA_CH_MAX_VAL)

Enumerations

enum  EDMA3_RM_ObjState {
+  EDMA3_RM_DELETED = 0, +
+  EDMA3_RM_CREATED = 1, +
+  EDMA3_RM_OPENED = 2, +
+  EDMA3_RM_CLOSED = 3 +
+ }

Variables

unsigned int edma3NumPaRAMSets
+

Detailed Description

+EDMA3 Resource Manager Internal header file. +

+This file contains implementation specific details used by the RM internally

+(C) Copyright 2006, Texas Instruments, Inc

+

Version:
0.1.0 Joseph Fernandez - Created 0.2.0 Anuj Aggarwal - Modified it for EDMA3 package
    +
  • Added multiple instances capability 0.2.1 Anuj Aggarwal - Modified it for more run time configuration.
  • Made EDMA3 package OS independent. 0.2.2 Anuj Aggarwal - Critical section handling code modification. Uses semaphore and interrupts disabling mechanism for resource sharing. 0.3.0 Anuj Aggarwal - Renamed EDMA3_DVR to EDMA3_DRV
  • IPR bit clearing in RM ISR issue fixed.
  • Sample application made generic 0.3.1 Anuj Aggarwal - Added DMA/QDMA Channel to TCC mapping, to fix QDMA missed event issue. 0.3.2 Anuj Aggarwal - Added support for POLL mode
  • Added a new API to modify the CC Register. 1.0.0 Anuj Aggarwal - Fixed resource allocation related bugs. 1.0.0.1 Anuj Aggarwal - Fixed spurious missed event generation related bug. 1.0.0.2 Anuj Aggarwal - Made the EDMA3 package RTSC compliant. 1.0.0.3 Anuj Aggarwal - Changed the directory structure as per RTSC standard. 1.01.00.01 Anuj Aggarwal - a) Added new APIs to allocate logical channels b) Created EDMA3 config files for different platforms c) Misc changes 1.02.00.01 Anuj Aggarwal - a) Added DM6467 support b) Fixed some MRs 1.03.00.01 Anuj Aggarwal - a) Added non-RTSC PJT files b) IOCTL Interface added. c) Fixed some MRs. 1.04 Anuj Aggarwal - a) Added new IOCTLs and APIs. b) Number of maximum Resource Manager Instances is configurable. c) Header files modified to have extern "C" declarations.
+
+

Define Documentation

+ +
+
+ + + + +
#define EDMA3_RM_DCH_PARAM_CLR_MASK   (~EDMA3_CCRL_DCHMAP_PAENTRY_MASK)
+
+
+ +

+DCHMAP-PaRAMEntry bitfield Clear +

Referenced by EDMA3_RM_allocLogicalChannel(), EDMA3_RM_freeLogicalChannel(), and EDMA3_RM_mapEdmaChannel().

+ +
+

+ +

+
+ + + + + + + + + +
#define EDMA3_RM_DCH_PARAM_SET_MASK (paRAMId   )    (((EDMA3_CCRL_DCHMAP_PAENTRY_MASK >> EDMA3_CCRL_DCHMAP_PAENTRY_SHIFT) & (paRAMId)) << EDMA3_CCRL_DCHMAP_PAENTRY_SHIFT)
+
+
+ +

+DCHMAP-PaRAMEntry bitfield Set +

Referenced by EDMA3_RM_allocLogicalChannel(), and EDMA3_RM_mapEdmaChannel().

+ +
+

+ +

+
+ + + + +
#define EDMA3_RM_OPT_TCC_CLR_MASK   (~EDMA3_CCRL_OPT_TCC_MASK)
+
+
+ +

+OPT-TCC bitfield Clear +

Referenced by EDMA3_RM_allocLogicalChannel().

+ +
+

+ +

+
+ + + + + + + + + +
#define EDMA3_RM_OPT_TCC_SET_MASK (tcc   )    (((EDMA3_CCRL_OPT_TCC_MASK >> EDMA3_CCRL_OPT_TCC_SHIFT) & (tcc)) << EDMA3_CCRL_OPT_TCC_SHIFT)
+
+
+ +

+OPT-TCC bitfield Set +

Referenced by EDMA3_RM_allocLogicalChannel().

+ +
+

+ +

+
+ + + + +
#define EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD   (5u)
+
+
+ +

+PaRAM Set Entry for Link and B count Reload field +

Referenced by EDMA3_RM_allocLogicalChannel().

+ +
+

+ +

+
+ + + + +
#define EDMA3_RM_QCH_PARAM_CLR_MASK   (~EDMA3_CCRL_QCHMAP_PAENTRY_MASK)
+
+
+ +

+QCHMAP-PaRAMEntry bitfield Clear +

Referenced by EDMA3_RM_allocLogicalChannel(), EDMA3_RM_freeLogicalChannel(), and EDMA3_RM_mapQdmaChannel().

+ +
+

+ +

+
+ + + + + + + + + +
#define EDMA3_RM_QCH_PARAM_SET_MASK (paRAMId   )    (((EDMA3_CCRL_QCHMAP_PAENTRY_MASK >> EDMA3_CCRL_QCHMAP_PAENTRY_SHIFT) & (paRAMId)) << EDMA3_CCRL_QCHMAP_PAENTRY_SHIFT)
+
+
+ +

+QCHMAP-PaRAMEntry bitfield Set +

Referenced by EDMA3_RM_allocLogicalChannel(), and EDMA3_RM_mapQdmaChannel().

+ +
+

+ +

+
+ + + + +
#define EDMA3_RM_QCH_TRWORD_CLR_MASK   (~EDMA3_CCRL_QCHMAP_TRWORD_MASK)
+
+
+ +

+QCHMAP-TrigWord bitfield Clear +

Referenced by EDMA3_RM_allocLogicalChannel(), EDMA3_RM_freeLogicalChannel(), and EDMA3_RM_mapQdmaChannel().

+ +
+

+ +

+
+ + + + + + + + + +
#define EDMA3_RM_QCH_TRWORD_SET_MASK (paRAMId   )    (((EDMA3_CCRL_QCHMAP_TRWORD_MASK >> EDMA3_CCRL_QCHMAP_TRWORD_SHIFT) & (paRAMId)) << EDMA3_CCRL_QCHMAP_TRWORD_SHIFT)
+
+
+ +

+QCHMAP-TrigWord bitfield Set +

Referenced by EDMA3_RM_allocLogicalChannel(), and EDMA3_RM_mapQdmaChannel().

+ +
+

+ +

+
+ + + + + + + + + +
#define EDMA3_RM_QUEPRI_CLR_MASK (queNum   )    (~(EDMA3_CCRL_QUEPRI_PRIQ0_MASK << ((queNum) * EDMA3_CCRL_QUEPRI_PRIQ1_SHIFT)))
+
+
+ +

+QUEPRI bits Clear +

Referenced by edma3GlobalRegionInit().

+ +
+

+ +

+
+ + + + + + + + + + + + +
#define EDMA3_RM_QUEPRI_SET_MASK (queNum,
quePri   )    ((EDMA3_CCRL_QUEPRI_PRIQ0_MASK & (quePri)) << ((queNum) * EDMA3_CCRL_QUEPRI_PRIQ1_SHIFT))
+
+
+ +

+QUEPRI bits Set +

Referenced by edma3GlobalRegionInit().

+ +
+

+ +

+
+ + + + + + + + + +
#define EDMA3_RM_QUEWMTHR_CLR_MASK (queNum   )    (~(EDMA3_CCRL_QWMTHRA_Q0_MASK << ((queNum) * EDMA3_CCRL_QWMTHRA_Q1_SHIFT)))
+
+
+ +

+QUEWMTHR bits Clear +

+

+ +

+
+ + + + + + + + + + + + +
#define EDMA3_RM_QUEWMTHR_SET_MASK (queNum,
queThr   )    ((EDMA3_CCRL_QWMTHRA_Q0_MASK & (queThr)) << ((queNum) * EDMA3_CCRL_QWMTHRA_Q1_SHIFT))
+
+
+ +

+QUEWMTHR bits Set +

Referenced by edma3GlobalRegionInit().

+ +
+

+ +

+
+ + + + +
#define EDMA3_RM_SET_ALL_BITS   (0xFFFFFFFFu)
+
+
+ +

+Define for setting all bits of the EDMA3 Controller Registers +

Referenced by edma3GlobalRegionInit().

+ +
+

+

Variable Documentation

+ +
+
+ + + + +
unsigned int edma3NumPaRAMSets
+
+
+ +

+Include Resource Manager header file Number of PaRAM Sets actually present on the SoC. This will be updated while creating the Resource Manager Object.

+Number of PaRAM Sets actually present on the SoC. This will be updated while creating the Resource Manager Object. +

Referenced by allocAnyContigRes(), EDMA3_RM_allocLogicalChannel(), EDMA3_RM_create(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_getPaRAM(), EDMA3_RM_getPaRAMPhyAddr(), and EDMA3_RM_setPaRAM().

+ +
+

+

+
Generated on Thu Oct 16 16:22:39 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/files.html b/packages/ti/sdo/edma3/rm/docs/html/files.html new file mode 100644 index 0000000..d64caee --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/files.html @@ -0,0 +1,41 @@ + + +EDMA3 Resource Manager: File Index + + + + + +
+

File List

Here is a list of all documented files with brief descriptions: + + + + + + + + + +
edma3_common.h [code]EDMA3 Common header provides generic defines/typedefs and debugging info
edma3_da830_cfg.cEDMA3 Driver Adaptation Configuration File (Soc Specific) for DA8xx platform
edma3_log.h [code]EDMA3 logging/tracing service
edma3_rl_cc.h [code]EDMA3 Channel Controller Register Desciption
edma3_rl_tc.h [code]EDMA3 Transfer Controller Register Desciption
edma3_rm.h [code]EDMA3 Controller Resource Manager Interface
edma3_rm_gbl_data.cSource file for the Resource Manager, for internal data structures
edma3resmgr.cEDMA3 Controller Resource Manager Interface Implementation
edma3resmgr.h [code]EDMA3 Resource Manager Internal header file
+
+
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+Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: +

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+Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: +

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+Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: +

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+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/globals_type.html b/packages/ti/sdo/edma3/rm/docs/html/globals_type.html new file mode 100644 index 0000000..8f58331 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/globals_type.html @@ -0,0 +1,63 @@ + + +EDMA3 Resource Manager: Data Fields + + + + + +
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Generated on Thu Oct 16 16:22:43 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/globals_vars.html b/packages/ti/sdo/edma3/rm/docs/html/globals_vars.html new file mode 100644 index 0000000..05b0960 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/globals_vars.html @@ -0,0 +1,91 @@ + + +EDMA3 Resource Manager: Data Fields + + + + + +
+  +

+

+
+
Generated on Thu Oct 16 16:22:43 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/group__edma3.html b/packages/ti/sdo/edma3/rm/docs/html/group__edma3.html new file mode 100644 index 0000000..a1763fb --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/group__edma3.html @@ -0,0 +1,115 @@ + + +EDMA3 Resource Manager: Log Service + + + + + +
+

Log Service

+ + + + + + + + + + + + + + + + + + + + +

Defines

+#define ARG1(arg1)   (arg1 << 8)
+#define ARG2(arg2)   (arg2 << 16)
+#define ARG3(arg3)   (arg3 << 24)
+#define EDMA3_DVT_DESC(event, arg1, arg2, arg3)   (event | ARG1(arg1) | ARG2(arg2) | ARG3(arg3))
+#define EDMA3_LOG_EVENT   LOG_printf4

Enumerations

enum  EDMA3_logEventType {
+  EDMA3_DVT_eINT, +
+  EDMA3_DVT_eINT_START, +
+  EDMA3_DVT_eINT_END, +
+  EDMA3_DVT_eFUNC, +
+  EDMA3_DVT_eFUNC_START, +
+  EDMA3_DVT_eFUNC_END, +
+  EDMA3_DVT_ePACKET_START, +
+  EDMA3_DVT_ePACKET_END, +
+  EDMA3_DVT_eDATA_SND, +
+  EDMA3_DVT_eDATA_SND_START, +
+  EDMA3_DVT_eDATA_SND_END, +
+  EDMA3_DVT_eDATA_RCV, +
+  EDMA3_DVT_eRCV_START, +
+  EDMA3_DVT_eRCV_END, +
+  EDMA3_DVT_eSMPL_COUNTER, +
+  EDMA3_DVT_eEVENT, +
+  EDMA3_DVT_eEVENT_START, +
+  EDMA3_DVT_eEVENT_END +
+ }
enum  EDMA3_logDataDesc {
+  EDMA3_DVT_dNONE, +
+  EDMA3_DVT_dINST, +
+  EDMA3_DVT_dINITIATOR, +
+  EDMA3_DVT_dMSG_ID, +
+  EDMA3_DVT_dCOUNTER, +
+  EDMA3_DVT_dSIZE_BYTES, +
+  EDMA3_DVT_dSIZE_WORDS, +
+  EDMA3_DVT_dPADD, +
+  EDMA3_DVT_dDADD, +
+  EDMA3_DVT_dDATA, +
+  EDMA3_DVT_dPACKET_ID, +
+  EDMA3_DVT_dCHANNEL_ID +
+ }

Variables

+far LOG_Obj DVTEvent_Log
+

Detailed Description

+EDMA3 error/event/message logging/tracing service
+
Generated on Thu Oct 16 16:22:41 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/group__edma3resmgr.html b/packages/ti/sdo/edma3/rm/docs/html/group__edma3resmgr.html new file mode 100644 index 0000000..ffadf0d --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/group__edma3resmgr.html @@ -0,0 +1,1732 @@ + + +EDMA3 Resource Manager: EDMA3 Resources Management + + + + + +
+

EDMA3 Resources Management
+ +[EDMA3 Interrupt Manager Interface] +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Data Structures

struct  EDMA3_RM_ParamentryRegs
 EDMA3 PaRAM Set. More...
struct  EDMA3_RM_PaRAMRegs
 EDMA3 PaRAM Set in User Configurable format. More...

Defines

#define EDMA3_RM_DMA_CHANNEL_ANY   (1011u)
#define EDMA3_RM_QDMA_CHANNEL_ANY   (1012u)
#define EDMA3_RM_TCC_ANY   (1013u)
#define EDMA3_RM_PARAM_ANY   (1014u)
#define EDMA3_RM_CH_NO_PARAM_MAP   (1015u)
#define EDMA3_RM_CH_NO_TCC_MAP   (1016u)

Enumerations

enum  EDMA3_RM_HW_CHANNEL_EVENT {
+  EDMA3_RM_HW_CHANNEL_EVENT_0 = 0, +
+  EDMA3_RM_HW_CHANNEL_EVENT_1, +
+  EDMA3_RM_HW_CHANNEL_EVENT_2, +
+  EDMA3_RM_HW_CHANNEL_EVENT_3, +
+  EDMA3_RM_HW_CHANNEL_EVENT_4, +
+  EDMA3_RM_HW_CHANNEL_EVENT_5, +
+  EDMA3_RM_HW_CHANNEL_EVENT_6, +
+  EDMA3_RM_HW_CHANNEL_EVENT_7, +
+  EDMA3_RM_HW_CHANNEL_EVENT_8, +
+  EDMA3_RM_HW_CHANNEL_EVENT_9, +
+  EDMA3_RM_HW_CHANNEL_EVENT_10, +
+  EDMA3_RM_HW_CHANNEL_EVENT_11, +
+  EDMA3_RM_HW_CHANNEL_EVENT_12, +
+  EDMA3_RM_HW_CHANNEL_EVENT_13, +
+  EDMA3_RM_HW_CHANNEL_EVENT_14, +
+  EDMA3_RM_HW_CHANNEL_EVENT_15, +
+  EDMA3_RM_HW_CHANNEL_EVENT_16, +
+  EDMA3_RM_HW_CHANNEL_EVENT_17, +
+  EDMA3_RM_HW_CHANNEL_EVENT_18, +
+  EDMA3_RM_HW_CHANNEL_EVENT_19, +
+  EDMA3_RM_HW_CHANNEL_EVENT_20, +
+  EDMA3_RM_HW_CHANNEL_EVENT_21, +
+  EDMA3_RM_HW_CHANNEL_EVENT_22, +
+  EDMA3_RM_HW_CHANNEL_EVENT_23, +
+  EDMA3_RM_HW_CHANNEL_EVENT_24, +
+  EDMA3_RM_HW_CHANNEL_EVENT_25, +
+  EDMA3_RM_HW_CHANNEL_EVENT_26, +
+  EDMA3_RM_HW_CHANNEL_EVENT_27, +
+  EDMA3_RM_HW_CHANNEL_EVENT_28, +
+  EDMA3_RM_HW_CHANNEL_EVENT_29, +
+  EDMA3_RM_HW_CHANNEL_EVENT_30, +
+  EDMA3_RM_HW_CHANNEL_EVENT_31, +
+  EDMA3_RM_HW_CHANNEL_EVENT_32, +
+  EDMA3_RM_HW_CHANNEL_EVENT_33, +
+  EDMA3_RM_HW_CHANNEL_EVENT_34, +
+  EDMA3_RM_HW_CHANNEL_EVENT_35, +
+  EDMA3_RM_HW_CHANNEL_EVENT_36, +
+  EDMA3_RM_HW_CHANNEL_EVENT_37, +
+  EDMA3_RM_HW_CHANNEL_EVENT_38, +
+  EDMA3_RM_HW_CHANNEL_EVENT_39, +
+  EDMA3_RM_HW_CHANNEL_EVENT_40, +
+  EDMA3_RM_HW_CHANNEL_EVENT_41, +
+  EDMA3_RM_HW_CHANNEL_EVENT_42, +
+  EDMA3_RM_HW_CHANNEL_EVENT_43, +
+  EDMA3_RM_HW_CHANNEL_EVENT_44, +
+  EDMA3_RM_HW_CHANNEL_EVENT_45, +
+  EDMA3_RM_HW_CHANNEL_EVENT_46, +
+  EDMA3_RM_HW_CHANNEL_EVENT_47, +
+  EDMA3_RM_HW_CHANNEL_EVENT_48, +
+  EDMA3_RM_HW_CHANNEL_EVENT_49, +
+  EDMA3_RM_HW_CHANNEL_EVENT_50, +
+  EDMA3_RM_HW_CHANNEL_EVENT_51, +
+  EDMA3_RM_HW_CHANNEL_EVENT_52, +
+  EDMA3_RM_HW_CHANNEL_EVENT_53, +
+  EDMA3_RM_HW_CHANNEL_EVENT_54, +
+  EDMA3_RM_HW_CHANNEL_EVENT_55, +
+  EDMA3_RM_HW_CHANNEL_EVENT_56, +
+  EDMA3_RM_HW_CHANNEL_EVENT_57, +
+  EDMA3_RM_HW_CHANNEL_EVENT_58, +
+  EDMA3_RM_HW_CHANNEL_EVENT_59, +
+  EDMA3_RM_HW_CHANNEL_EVENT_60, +
+  EDMA3_RM_HW_CHANNEL_EVENT_61, +
+  EDMA3_RM_HW_CHANNEL_EVENT_62, +
+  EDMA3_RM_HW_CHANNEL_EVENT_63 +
+ }
 DMA Channels assigned to different Hardware Events. They should be used while requesting a specific DMA channel. One possible usage is to maintain a SoC specific file, which will contain the mapping of these hardware events to the respective peripherals for better understanding and lesser probability of errors. Also, if any event associated with a particular peripheral gets changed, only that SoC specific file needs to be changed. More...
enum  EDMA3_RM_QdmaTrigWord {
+  EDMA3_RM_QDMA_TRIG_OPT = 0, +
+  EDMA3_RM_QDMA_TRIG_SRC = 1, +
+  EDMA3_RM_QDMA_TRIG_ACNT_BCNT = 2, +
+  EDMA3_RM_QDMA_TRIG_DST = 3, +
+  EDMA3_RM_QDMA_TRIG_SRC_DST_BIDX = 4, +
+  EDMA3_RM_QDMA_TRIG_LINK_BCNTRLD = 5, +
+  EDMA3_RM_QDMA_TRIG_SRC_DST_CIDX = 6, +
+  EDMA3_RM_QDMA_TRIG_CCNT = 7, +
+  EDMA3_RM_QDMA_TRIG_DEFAULT = 7 +
+ }
 QDMA Trigger Word. More...
enum  EDMA3_RM_Cntrlr_PhyAddr {
+  EDMA3_RM_CC_PHY_ADDR = 0, +
+  EDMA3_RM_TC0_PHY_ADDR, +
+  EDMA3_RM_TC1_PHY_ADDR, +
+  EDMA3_RM_TC2_PHY_ADDR, +
+  EDMA3_RM_TC3_PHY_ADDR, +
+  EDMA3_RM_TC4_PHY_ADDR, +
+  EDMA3_RM_TC5_PHY_ADDR, +
+  EDMA3_RM_TC6_PHY_ADDR, +
+  EDMA3_RM_TC7_PHY_ADDR +
+ }
 CC/TC Physical Address. More...
enum  EDMA3_RM_IoctlCmd {
+  EDMA3_RM_IOCTL_MIN_IOCTL = 0, +
+  EDMA3_RM_IOCTL_SET_PARAM_CLEAR_OPTION, +
+  EDMA3_RM_IOCTL_GET_PARAM_CLEAR_OPTION, +
+  EDMA3_RM_IOCTL_SET_GBL_REG_MODIFY_OPTION, +
+  EDMA3_RM_IOCTL_GET_GBL_REG_MODIFY_OPTION, +
+  EDMA3_RM_IOCTL_MAX_IOCTL +
+ }
 EDMA3 Resource Manager IOCTL commands. More...

Functions

EDMA3_RM_Result EDMA3_RM_allocResource (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *resObj)
 This API is used to allocate specified EDMA3 Resources like DMA/QDMA channel, PaRAM Set or TCC.
EDMA3_RM_Result EDMA3_RM_freeResource (EDMA3_RM_Handle hEdmaResMgr, const EDMA3_RM_ResDesc *resObj)
 This API is used to free previously allocated EDMA3 Resources like DMA/QDMA channel, PaRAM Set or TCC.
EDMA3_RM_Result EDMA3_RM_allocContiguousResource (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *firstResIdObj, unsigned int numResources)
 Allocate a contiguous region of specified EDMA3 Resource like DMA channel, QDMA channel, PaRAM Set or TCC.
EDMA3_RM_Result EDMA3_RM_freeContiguousResource (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *firstResIdObj, unsigned int numResources)
 Free a contiguous region of specified EDMA3 Resource like DMA channel, QDMA channel, PaRAM Set or TCC, previously allocated.
EDMA3_RM_Result EDMA3_RM_allocLogicalChannel (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *lChObj, unsigned int *pParam, unsigned int *pTcc)
 Request a DMA/QDMA/Link channel.
EDMA3_RM_Result EDMA3_RM_freeLogicalChannel (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *lChObj)
 This API is used to free the specified channel (DMA/QDMA/Link) and its associated resources (PaRAM Set, TCC etc).
EDMA3_RM_Result EDMA3_RM_mapEdmaChannel (EDMA3_RM_Handle hEdmaResMgr, unsigned int channelId, unsigned int paRAMId)
 Bind the resources DMA Channel and PaRAM Set. Both the DMA channel and the PaRAM set should be previously allocated. If they are not, this API will result in error.
EDMA3_RM_Result EDMA3_RM_mapQdmaChannel (EDMA3_RM_Handle hEdmaResMgr, unsigned int channelId, unsigned int paRAMId, EDMA3_RM_QdmaTrigWord trigWord)
 Bind the resources QDMA Channel and PaRAM Set. Also, Set the trigger word for the QDMA channel. Both the QDMA channel and the PaRAM set should be previously allocated. If they are not, this API will result in error.
EDMA3_RM_Result EDMA3_RM_setCCRegister (EDMA3_RM_Handle hEdmaResMgr, unsigned int regOffset, unsigned int newRegValue)
 Set the Channel Controller (CC) Register value.
EDMA3_RM_Result EDMA3_RM_getCCRegister (EDMA3_RM_Handle hEdmaResMgr, unsigned int regOffset, unsigned int *regValue)
 Get the Channel Controller (CC) Register value.
EDMA3_RM_Result EDMA3_RM_waitAndClearTcc (EDMA3_RM_Handle hEdmaResMgr, unsigned int tccNo)
 Wait for a transfer completion interrupt to occur and clear it.
EDMA3_RM_Result EDMA3_RM_checkAndClearTcc (EDMA3_RM_Handle hEdmaResMgr, unsigned int tccNo, unsigned short *tccStatus)
 Returns the status of a previously initiated transfer.
EDMA3_RM_Result EDMA3_RM_setPaRAM (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *lChObj, const EDMA3_RM_PaRAMRegs *newPaRAM)
 Copy the user specified PaRAM Set onto the PaRAM Set associated with the logical channel (DMA/QDMA/Link).
EDMA3_RM_Result EDMA3_RM_getPaRAM (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *lChObj, EDMA3_RM_PaRAMRegs *currPaRAM)
 Retrieve existing PaRAM set associated with specified logical channel (DMA/QDMA/Link).
EDMA3_RM_Result EDMA3_RM_getPaRAMPhyAddr (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *lChObj, unsigned int *paramPhyAddr)
 Get the PaRAM Set Physical Address associated with a logical channel.
EDMA3_RM_Result EDMA3_RM_getBaseAddress (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_Cntrlr_PhyAddr controllerId, unsigned int *phyAddress)
 Get the Channel Controller or Transfer Controller (n) Physical Address.
EDMA3_RM_Result EDMA3_RM_getGblConfigParams (unsigned int phyCtrllerInstId, EDMA3_RM_GblConfigParams *gblCfgParams)
 Get the SoC specific configuration structure for the EDMA3 Hardware.
EDMA3_RM_Result EDMA3_RM_getInstanceInitCfg (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_InstanceInitConfig *instanceInitConfig)
 Get the RM Instance specific configuration structure for different EDMA3 resources' usage (owned resources, reserved resources etc).
EDMA3_RM_Result EDMA3_RM_Ioctl (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_IoctlCmd cmd, void *cmdArg, void *param)
 EDMA3 Resource Manager IOCTL.
+

Detailed Description

+Resource Management part of the EDMA3 Resource Manager.

Define Documentation

+ +
+
+ + + + +
#define EDMA3_RM_CH_NO_PARAM_MAP   (1015u)
+
+
+ +

+This define is used to specify that a DMA channel is NOT tied to any PaRAM Set and hence any available PaRAM Set could be used for that DMA channel. It could be used in dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH], in global configuration structure EDMA3_RM_GblConfigParams.

+This value should mandatorily be used to mark DMA channels with no initial mapping to specific PaRAM Sets. +

Referenced by EDMA3_RM_allocLogicalChannel(), and EDMA3_RM_open().

+ +
+

+ +

+
+ + + + +
#define EDMA3_RM_CH_NO_TCC_MAP   (1016u)
+
+
+ +

+This define is used to specify that the DMA/QDMA channel is not tied to any TCC and hence any available TCC could be used for that DMA/QDMA channel. It could be used in dmaChannelTccMap [EDMA3_MAX_DMA_CH], in global configuration structure EDMA3_RM_GblConfigParams.

+This value should mandatorily be used to mark DMA channels with no initial mapping to specific TCCs. +

Referenced by EDMA3_RM_allocLogicalChannel().

+ +
+

+ +

+
+ + + + +
#define EDMA3_RM_DMA_CHANNEL_ANY   (1011u)
+
+
+ +

+Used to specify any available DMA Channel while requesting one. Used in the API EDMA3_RM_allocLogicalChannel (). DMA channel from the pool of (owned && non_reserved && available_right_now) DMA channels will be chosen and returned. +

Referenced by EDMA3_RM_allocLogicalChannel().

+ +
+

+ +

+
+ + + + +
#define EDMA3_RM_PARAM_ANY   (1014u)
+
+
+ +

+Used to specify any available PaRAM Set while requesting one. Used in the API EDMA3_RM_allocLogicalChannel(), for both DMA/QDMA and Link channels. PaRAM Set from the pool of (owned && non_reserved && available_right_now) PaRAM Sets will be chosen and returned. +

Referenced by EDMA3_RM_allocLogicalChannel().

+ +
+

+ +

+
+ + + + +
#define EDMA3_RM_QDMA_CHANNEL_ANY   (1012u)
+
+
+ +

+Used to specify any available QDMA Channel while requesting one. Used in the API EDMA3_RM_allocLogicalChannel(). QDMA channel from the pool of (owned && non_reserved && available_right_now) QDMA channels will be chosen and returned. +

Referenced by EDMA3_RM_allocLogicalChannel().

+ +
+

+ +

+
+ + + + +
#define EDMA3_RM_TCC_ANY   (1013u)
+
+
+ +

+Used to specify any available TCC while requesting one. Used in the API EDMA3_RM_allocLogicalChannel(), for both DMA and QDMA channels. TCC from the pool of (owned && non_reserved && available_right_now) TCCs will be chosen and returned. +

Referenced by EDMA3_RM_allocLogicalChannel().

+ +
+

+

Enumeration Type Documentation

+ +
+
+ + + + +
enum EDMA3_RM_Cntrlr_PhyAddr
+
+
+ +

+CC/TC Physical Address. +

+Use this enum to get the physical address of the Channel Controller or the Transfer Controller. The address returned could be used by the advanced usres to set/get some specific registers direclty.

Enumerator:
+ + + + + + + + + + +
EDMA3_RM_CC_PHY_ADDR  +Channel Controller Physical Address
EDMA3_RM_TC0_PHY_ADDR  +Transfer Controller 0 Physical Address
EDMA3_RM_TC1_PHY_ADDR  +Transfer Controller 1 Physical Address
EDMA3_RM_TC2_PHY_ADDR  +Transfer Controller 2 Physical Address
EDMA3_RM_TC3_PHY_ADDR  +Transfer Controller 3 Physical Address
EDMA3_RM_TC4_PHY_ADDR  +Transfer Controller 4 Physical Address
EDMA3_RM_TC5_PHY_ADDR  +Transfer Controller 5 Physical Address
EDMA3_RM_TC6_PHY_ADDR  +Transfer Controller 6 Physical Address
EDMA3_RM_TC7_PHY_ADDR  +Transfer Controller 7 Physical Address
+
+ +
+

+ +

+
+ + + + +
enum EDMA3_RM_HW_CHANNEL_EVENT
+
+
+ +

+DMA Channels assigned to different Hardware Events. They should be used while requesting a specific DMA channel. One possible usage is to maintain a SoC specific file, which will contain the mapping of these hardware events to the respective peripherals for better understanding and lesser probability of errors. Also, if any event associated with a particular peripheral gets changed, only that SoC specific file needs to be changed. +

+for eg, the sample SoC specific file "soc.h" can have these defines:

+define EDMA3_RM_HW_CHANNEL_MCBSP_TX EDMA3_RM_HW_CHANNEL_EVENT_2 define EDMA3_RM_HW_CHANNEL_MCBSP_RX EDMA3_RM_HW_CHANNEL_EVENT_3

+These defines will be used by the MCBSP driver. The same event EDMA3_RM_HW_CHANNEL_EVENT_2/3 could be mapped to some other peripheral also.

Enumerator:
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_RM_HW_CHANNEL_EVENT_0  +Channel assigned to EDMA3 Event 0
EDMA3_RM_HW_CHANNEL_EVENT_1  +Channel assigned to EDMA3 Event 1
EDMA3_RM_HW_CHANNEL_EVENT_2  +Channel assigned to EDMA3 Event 2
EDMA3_RM_HW_CHANNEL_EVENT_3  +Channel assigned to EDMA3 Event 3
EDMA3_RM_HW_CHANNEL_EVENT_4  +Channel assigned to EDMA3 Event 4
EDMA3_RM_HW_CHANNEL_EVENT_5  +Channel assigned to EDMA3 Event 5
EDMA3_RM_HW_CHANNEL_EVENT_6  +Channel assigned to EDMA3 Event 6
EDMA3_RM_HW_CHANNEL_EVENT_7  +Channel assigned to EDMA3 Event 7
EDMA3_RM_HW_CHANNEL_EVENT_8  +Channel assigned to EDMA3 Event 8
EDMA3_RM_HW_CHANNEL_EVENT_9  +Channel assigned to EDMA3 Event 9
EDMA3_RM_HW_CHANNEL_EVENT_10  +Channel assigned to EDMA3 Event 10
EDMA3_RM_HW_CHANNEL_EVENT_11  +Channel assigned to EDMA3 Event 11
EDMA3_RM_HW_CHANNEL_EVENT_12  +Channel assigned to EDMA3 Event 12
EDMA3_RM_HW_CHANNEL_EVENT_13  +Channel assigned to EDMA3 Event 13
EDMA3_RM_HW_CHANNEL_EVENT_14  +Channel assigned to EDMA3 Event 14
EDMA3_RM_HW_CHANNEL_EVENT_15  +Channel assigned to EDMA3 Event 15
EDMA3_RM_HW_CHANNEL_EVENT_16  +Channel assigned to EDMA3 Event 16
EDMA3_RM_HW_CHANNEL_EVENT_17  +Channel assigned to EDMA3 Event 17
EDMA3_RM_HW_CHANNEL_EVENT_18  +Channel assigned to EDMA3 Event 18
EDMA3_RM_HW_CHANNEL_EVENT_19  +Channel assigned to EDMA3 Event 19
EDMA3_RM_HW_CHANNEL_EVENT_20  +Channel assigned to EDMA3 Event 20
EDMA3_RM_HW_CHANNEL_EVENT_21  +Channel assigned to EDMA3 Event 21
EDMA3_RM_HW_CHANNEL_EVENT_22  +Channel assigned to EDMA3 Event 22
EDMA3_RM_HW_CHANNEL_EVENT_23  +Channel assigned to EDMA3 Event 23
EDMA3_RM_HW_CHANNEL_EVENT_24  +Channel assigned to EDMA3 Event 24
EDMA3_RM_HW_CHANNEL_EVENT_25  +Channel assigned to EDMA3 Event 25
EDMA3_RM_HW_CHANNEL_EVENT_26  +Channel assigned to EDMA3 Event 26
EDMA3_RM_HW_CHANNEL_EVENT_27  +Channel assigned to EDMA3 Event 27
EDMA3_RM_HW_CHANNEL_EVENT_28  +Channel assigned to EDMA3 Event 28
EDMA3_RM_HW_CHANNEL_EVENT_29  +Channel assigned to EDMA3 Event 29
EDMA3_RM_HW_CHANNEL_EVENT_30  +Channel assigned to EDMA3 Event 30
EDMA3_RM_HW_CHANNEL_EVENT_31  +Channel assigned to EDMA3 Event 31
EDMA3_RM_HW_CHANNEL_EVENT_32  +Channel assigned to EDMA3 Event 32
EDMA3_RM_HW_CHANNEL_EVENT_33  +Channel assigned to EDMA3 Event 33
EDMA3_RM_HW_CHANNEL_EVENT_34  +Channel assigned to EDMA3 Event 34
EDMA3_RM_HW_CHANNEL_EVENT_35  +Channel assigned to EDMA3 Event 35
EDMA3_RM_HW_CHANNEL_EVENT_36  +Channel assigned to EDMA3 Event 36
EDMA3_RM_HW_CHANNEL_EVENT_37  +Channel assigned to EDMA3 Event 37
EDMA3_RM_HW_CHANNEL_EVENT_38  +Channel assigned to EDMA3 Event 38
EDMA3_RM_HW_CHANNEL_EVENT_39  +Channel assigned to EDMA3 Event 39
EDMA3_RM_HW_CHANNEL_EVENT_40  +Channel assigned to EDMA3 Event 40
EDMA3_RM_HW_CHANNEL_EVENT_41  +Channel assigned to EDMA3 Event 41
EDMA3_RM_HW_CHANNEL_EVENT_42  +Channel assigned to EDMA3 Event 42
EDMA3_RM_HW_CHANNEL_EVENT_43  +Channel assigned to EDMA3 Event 43
EDMA3_RM_HW_CHANNEL_EVENT_44  +Channel assigned to EDMA3 Event 44
EDMA3_RM_HW_CHANNEL_EVENT_45  +Channel assigned to EDMA3 Event 45
EDMA3_RM_HW_CHANNEL_EVENT_46  +Channel assigned to EDMA3 Event 46
EDMA3_RM_HW_CHANNEL_EVENT_47  +Channel assigned to EDMA3 Event 47
EDMA3_RM_HW_CHANNEL_EVENT_48  +Channel assigned to EDMA3 Event 48
EDMA3_RM_HW_CHANNEL_EVENT_49  +Channel assigned to EDMA3 Event 49
EDMA3_RM_HW_CHANNEL_EVENT_50  +Channel assigned to EDMA3 Event 50
EDMA3_RM_HW_CHANNEL_EVENT_51  +Channel assigned to EDMA3 Event 51
EDMA3_RM_HW_CHANNEL_EVENT_52  +Channel assigned to EDMA3 Event 52
EDMA3_RM_HW_CHANNEL_EVENT_53  +Channel assigned to EDMA3 Event 53
EDMA3_RM_HW_CHANNEL_EVENT_54  +Channel assigned to EDMA3 Event 54
EDMA3_RM_HW_CHANNEL_EVENT_55  +Channel assigned to EDMA3 Event 55
EDMA3_RM_HW_CHANNEL_EVENT_56  +Channel assigned to EDMA3 Event 56
EDMA3_RM_HW_CHANNEL_EVENT_57  +Channel assigned to EDMA3 Event 57
EDMA3_RM_HW_CHANNEL_EVENT_58  +Channel assigned to EDMA3 Event 58
EDMA3_RM_HW_CHANNEL_EVENT_59  +Channel assigned to EDMA3 Event 59
EDMA3_RM_HW_CHANNEL_EVENT_60  +Channel assigned to EDMA3 Event 60
EDMA3_RM_HW_CHANNEL_EVENT_61  +Channel assigned to EDMA3 Event 61
EDMA3_RM_HW_CHANNEL_EVENT_62  +Channel assigned to EDMA3 Event 62
EDMA3_RM_HW_CHANNEL_EVENT_63  +Channel assigned to EDMA3 Event 63
+
+ +
+

+ +

+
+ + + + +
enum EDMA3_RM_IoctlCmd
+
+
+ +

+EDMA3 Resource Manager IOCTL commands. +

+

Enumerator:
+ + + + + +
EDMA3_RM_IOCTL_SET_PARAM_CLEAR_OPTION  +PaRAM Sets will be cleared OR will not be cleared during allocation, depending upon this option.

+For e.g., To clear the PaRAM Sets during allocation, cmdArg = (void *)1;

+To NOT clear the PaRAM Sets during allocation, cmdArg = (void *)0;

+For all other values, it will return error.

+By default, PaRAM Sets will be cleared during allocation.

+Note: Since this enum can change the behavior how the resources are initialized during their allocation, user is adviced to not use this command while allocating the resources. User should first change the behavior of resources' initialization and then should use start allocating resources.

EDMA3_RM_IOCTL_GET_PARAM_CLEAR_OPTION  +To check whether PaRAM Sets will be cleared or not during allocation. If the value read is '1', it means that PaRAM Sets are getting cleared during allocation. If the value read is '0', it means that PaRAM Sets are NOT getting cleared during allocation.

+For e.g., unsigned int *isParamClearingDone = (unsigned int *)cmdArg; (*isParamClearingDone) = paramClearingRequired;

EDMA3_RM_IOCTL_SET_GBL_REG_MODIFY_OPTION  +Global EDMA3 registers (DCHMAP/QCHMAP) and PaRAM Sets will be modified OR will not be modified during EDMA3_RM_allocLogicalChannel (), depending upon this option.

+For e.g., To modify the Registers or PaRAM Sets during allocation, cmdArg = (void *)1;

+To NOT modify the Registers or PaRAM Sets during allocation, cmdArg = (void *)0;

+For all other values, it will return error.

+By default, Registers or PaRAM Sets will be programmed during allocation.

+Note: Since this enum can change the behavior how the resources are initialized during their allocation, user is adviced to not use this command while allocating the resources. User should first change the behavior of resources' initialization and then should use start allocating resources.

EDMA3_RM_IOCTL_GET_GBL_REG_MODIFY_OPTION  +To check whether Global EDMA3 registers (DCHMAP/QCHMAP) and PaRAM Sets will be programmed or not during allocation (EDMA3_RM_allocLogicalChannel ()). If the value read is '1', it means that the registers/PaRAMs are getting programmed during allocation. If the value read is '0', it means that the registers/PaRAMs are NOT getting programmed during allocation.

+For e.g., unsigned int *isParamClearingDone = (unsigned int *)cmdArg; (*isParamClearingDone) = paramClearingRequired;

+
+ +
+

+ +

+
+ + + + +
enum EDMA3_RM_QdmaTrigWord
+
+
+ +

+QDMA Trigger Word. +

+Use this enum to set the QDMA trigger word to any of the 8 DWords(unsigned int) within a Parameter RAM set

Enumerator:
+ + + + + + + + + + +
EDMA3_RM_QDMA_TRIG_OPT  +Set the OPT field (Offset Address 0h Bytes) as the QDMA trigger word
EDMA3_RM_QDMA_TRIG_SRC  +Set the SRC field (Offset Address 4h Bytes) as the QDMA trigger word
EDMA3_RM_QDMA_TRIG_ACNT_BCNT  +Set the (ACNT + BCNT) field (Offset Address 8h Bytes) as the QDMA trigger word
EDMA3_RM_QDMA_TRIG_DST  +Set the DST field (Offset Address Ch Bytes) as the QDMA trigger word
EDMA3_RM_QDMA_TRIG_SRC_DST_BIDX  +Set the (SRCBIDX + DSTBIDX) field (Offset Address 10h Bytes) as the QDMA trigger word
EDMA3_RM_QDMA_TRIG_LINK_BCNTRLD  +Set the (LINK + BCNTRLD) field (Offset Address 14h Bytes) as the QDMA trigger word
EDMA3_RM_QDMA_TRIG_SRC_DST_CIDX  +Set the (SRCCIDX + DSTCIDX) field (Offset Address 18h Bytes) as the QDMA trigger word
EDMA3_RM_QDMA_TRIG_CCNT  +Set the (CCNT + RSVD) field (Offset Address 1Ch Bytes) as the QDMA trigger word
EDMA3_RM_QDMA_TRIG_DEFAULT  +Default Trigger Word
+
+ +
+

+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_RM_Result EDMA3_RM_allocContiguousResource (EDMA3_RM_Handle  hEdmaResMgr,
EDMA3_RM_ResDesc *  firstResIdObj,
unsigned int  numResources 
)
+
+
+ +

+Allocate a contiguous region of specified EDMA3 Resource like DMA channel, QDMA channel, PaRAM Set or TCC. +

+This API is used to allocate a contiguous region of specified EDMA3 Resources like DMA channel, QDMA channel, PaRAM Set or TCC.

+User can specify a particular resource Id to start with and go up to the number of resources requested. The specific resource id to start from could be passed in 'firstResIdObject->resId' and the number of resources requested in 'numResources'.

+User can also request ANY available resource(s) of the type 'firstResIdObject->type' by specifying 'firstResIdObject->resId' as EDMA3_RM_RES_ANY.

+ANY types of resources are those resources when user doesn't care about the actual resource allocated; user just wants a resource of the type specified. One use-case is to perform memory-to-memory data transfer operation. This operation can be performed using any available DMA or QDMA channel. User doesn't need any specific channel for the same.

+To allocate specific contiguous resources, first this API checks whether those requested resources are OWNED by the Resource Manager instance. Then it checks the current availability of those resources.

+To allocate ANY available contiguous resources, this API tries to allocate resources from the pool of (owned && non_reserved && available_right_now) resources.

+After allocating DMA/QDMA channels or TCCs, the same resources are enabled in the shadow region specific register (DRAE/DRAEH/QRAE). Allocated PaRAM Sets are initialized to NULL before this API returns.

+

Parameters:
+ + + + +
hEdmaResMgr [IN] Handle to the previously opened Resource Manager Instance.
firstResIdObj [IN] Handle to the first resource descriptor object, which needs to be allocated. firstResIdObject->resId could be a valid resource id in case user wants to allocate specific resources OR it could be EDMA3_RM_RES_ANY in case user wants only the required number of resources and doesn't care about which resources were allocated.
numResources [IN] Number of contiguous resources user wants to allocate.
+
+
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
+
Note:
This function acquires a RM Instance specific semaphore to prevent simultaneous access to the global pool of resources. It is re-entrant, but should not be called from the user callback function (ISR context).
+ +

+Take the instance specific semaphore, to prevent simultaneous access to the shared resources.

+Enable the DMA channel in the DRAE registers also.

+Enable the DMA channel in the DRAEH registers also.

+Enable the QDMA channel in the QRAE register also.

+Enable the Interrupt channel in the DRAE/DRAEH registers also. Also, If the region id coming from this RM instance is same as the Master RM Instance's region id, only then we will be getting the interrupts on the same side. So save the TCC in the allocatedTCCs[] array.

+Also, make the actual PARAM Set NULL, checking the flag whether it is required or not.

+Take the instance specific semaphore, to prevent simultaneous access to the shared resources.

+We have to search three different arrays, namely ownedResoures, avlblResources and resvdResources, to find the 'common' contiguous resources. For this, take an 'AND' of all three arrays in one single array and use your algorithm on that array.

+Try to allocate 'numResources' contiguous resources of type RES_ANY.

+If result != EDMA3_RM_SOK, resource allocation failed. Else resources successfully allocated.

+Check the Resource Allocation Result 'result' first. If Resource Allocation has resulted in an error, return it (having more priority than semResult. Else, return semResult.

+Resource Allocation successful, return semResult for returning semaphore. +

References allocAnyContigRes(), allocatedTCCs, EDMA3_RM_Instance::avlblDmaChannels, EDMA3_RM_Instance::avlblPaRAMSets, EDMA3_RM_Instance::avlblQdmaChannels, EDMA3_RM_Instance::avlblTccs, contiguousDmaRes, contiguousParamRes, contiguousQdmaRes, contiguousTccRes, EDMA3_OSSEM_NO_TIMEOUT, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_E_RES_NOT_OWNED, EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE, EDMA3_RM_RES_ANY, EDMA3_RM_RES_DMA_CHANNEL, EDMA3_RM_RES_PARAM_SET, EDMA3_RM_RES_QDMA_CHANNEL, EDMA3_RM_RES_TCC, EDMA3_RM_SOK, edma3MemSet(), edma3OsSemGive(), edma3OsSemTake(), edma3RegionId, FALSE, EDMA3_RM_Obj::gblCfgParams, gblChngAllocContigRes(), EDMA3_RM_GblConfigParams::globalRegs, EDMA3_RM_Instance::initParam, NULL, EDMA3_RM_GblConfigParams::numDmaChannels, EDMA3_RM_GblConfigParams::numPaRAMSets, EDMA3_RM_GblConfigParams::numQdmaChannels, EDMA3_RM_GblConfigParams::numTccs, EDMA3_RM_InstanceInitConfig::ownDmaChannels, EDMA3_RM_InstanceInitConfig::ownPaRAMSets, EDMA3_RM_InstanceInitConfig::ownQdmaChannels, EDMA3_RM_InstanceInitConfig::ownTccs, EDMA3_RM_Instance::paramInitRequired, EDMA3_RM_Instance::pResMgrObjHandle, EDMA3_RM_Param::regionId, EDMA3_RM_ResDesc::resId, EDMA3_RM_InstanceInitConfig::resvdDmaChannels, EDMA3_RM_InstanceInitConfig::resvdPaRAMSets, EDMA3_RM_InstanceInitConfig::resvdQdmaChannels, EDMA3_RM_InstanceInitConfig::resvdTccs, EDMA3_RM_Param::rmInstInitConfig, EDMA3_RM_Param::rmSemHandle, EDMA3_RM_Instance::shadowRegs, TRUE, and EDMA3_RM_ResDesc::type.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_RM_Result EDMA3_RM_allocLogicalChannel (EDMA3_RM_Handle  hEdmaResMgr,
EDMA3_RM_ResDesc *  lChObj,
unsigned int *  pParam,
unsigned int *  pTcc 
)
+
+
+ +

+Request a DMA/QDMA/Link channel. +

+This API is used to allocate a logical channel (DMA/QDMA/Link) along with the associated resources. For DMA and QDMA channels, TCC and PaRAM Set are also allocated along with the requested channel. For Link channel, ONLY a PaRAM Set is allocated.

+Note: To free the logical channel allocated by this API, user should call EDMA3_RM_freeLogicalChannel () ONLY to de-allocate all the allocated resources and remove certain mappings.

+User can request a specific logical channel by passing the channel id in 'lChObj->resId' and channel type in 'lChObj->type'. Note that the channel id is the same as the actual resource id. For e.g. in the case of QDMA channels, valid channel ids are from 0 to 7 only.

+User can also request ANY available logical channel of the type 'lChObj->type' by specifying 'lChObj->resId' as: a) EDMA3_RM_DMA_CHANNEL_ANY: For DMA channels b) EDMA3_RM_QDMA_CHANNEL_ANY: For QDMA channels, and c) EDMA3_RM_PARAM_ANY: For Link channels. Normally user should use this value to request link channels (PaRAM Sets used for linking purpose only), unless he wants to use some specific link channels (PaRAM Sets) which is also allowed.

+This API internally uses EDMA3_RM_allocResource () to allocate the desired resources (DMA/QDMA channel, PaRAM Set and TCC).

+For DMA/QDMA channels, after allocating all the EDMA3 resources, this API sets the TCC field of the OPT PaRAM Word with the allocated TCC.

+For DMA channel, it also sets the DCHMAP register, if required.

+For QDMA channel, it sets the QCHMAP register and CCNT as trigger word and enables the QDMA channel by writing to the QEESR register.

+

Parameters:
+ + + + + +
hEdmaResMgr [IN] Handle to the previously opened Resource Manager Instance.
lChObj [IN/OUT] Handle to the requested logical channel object, which needs to be allocated. It could be a specific logical channel or ANY available logical channel of the requested type. In case user passes a specific resource Id, lChObj value is left unchanged. In case user requests ANY available resource, the allocated resource id is returned in lChObj->resId.
pParam [IN/OUT] PaRAM Set for a particular logical (DMA/QDMA) channel. Not used if user requested for a Link channel. In case user passes a specific PaRAM Set value, pParam value is left unchanged. In case user requests ANY available PaRAM Set by passing 'EDMA3_RM_PARAM_ANY' in pParam, the allocated one is returned in pParam.
pTcc [IN/OUT] TCC for a particular logical (DMA/QDMA) channel. Not used if user requested for a Link channel. In case user passes a specific TCC value, pTcc value is left unchanged. In case user requests ANY available TCC by passing 'EDMA3_RM_TCC_ANY' in pTcc, the allocated one is returned in pTcc.
+
+
Returns:
EDMA3_RM_SOK or EDMA_RM Error Code
+
Note:
This function internally calls EDMA3_RM_allocResource (), which acquires a RM Instance specific semaphore to prevent simultaneous access to the global pool of resources. It is re-entrant for unique logical channel values, but SHOULD NOT be called from the user callback function (ISR context).
+This API is used to allocate a logical channel (DMA/QDMA/Link) along with the associated resources. For DMA and QDMA channels, TCC and PaRAM Set are also allocated along with the requested channel. For Link channel, ONLY a PaRAM Set is allocated.

+Note: To free the logical channel allocated by this API, user should call EDMA3_RM_freeLogicalChannel () ONLY to de-allocate all the allocated resources and remove certain mappings.

+User can request a specific logical channel by passing the channel id in 'lChObj->resId' and channel type in 'lChObj->type'. Note that the channel id is the same as the actual resource id. For e.g. in the case of QDMA channels, valid channel ids are from 0 to 7 only.

+User can also request ANY available logical channel of the type 'lChObj->type' by specifying 'lChObj->resId' as: a) EDMA3_RM_DMA_CHANNEL_ANY: For DMA channels b) EDMA3_RM_QDMA_CHANNEL_ANY: For QDMA channels, and c) EDMA3_RM_PARAM_ANY: For Link channels. Normally user should use this value to request link channels (PaRAM Sets used for linking purpose only), unless he wants to use some specific link channels (PaRAM Sets) which is also allowed.

+This API internally uses EDMA3_RM_allocResource () to allocate the desired resources (DMA/QDMA channel, PaRAM Set and TCC).

+For DMA/QDMA channels, after allocating all the EDMA3 resources, this API sets the TCC field of the OPT PaRAM Word with the allocated TCC.

+For DMA channel, it also sets the DCHMAP register, if required.

+For QDMA channel, it sets the QCHMAP register and CCNT as trigger word and enables the QDMA channel by writing to the QEESR register.

+

Parameters:
+ + + + + +
hEdmaResMgr [IN] Handle to the previously opened Resource Manager Instance.
lChObj [IN/OUT] Handle to the requested logical channel object, which needs to be allocated. It could be a specific logical channel or ANY available logical channel of the requested type. In case user passes a specific resource Id, lChObj value is left unchanged. In case user requests ANY available resource, the allocated resource id is returned in lChObj->resId.
pParam [IN/OUT] PaRAM Set for a particular logical (DMA/QDMA) channel. Not used if user requested for a Link channel. In case user passes a specific PaRAM Set value, pParam value is left unchanged. In case user requests ANY available PaRAM Set, the allocated one is returned in pParam.
pTcc [IN/OUT] TCC for a particular logical (DMA/QDMA) channel. Not used if user requested for a Link channel. In case user passes a specific TCC value, pTcc value is left unchanged. In case user requests ANY available TCC, the allocated one is returned in pTcc
+
+
Returns:
EDMA3_RM_SOK or EDMA_RM Error Code
+
Note:
This function internally calls EDMA3_RM_allocResource (), which acquires a RM Instance specific semaphore to prevent simultaneous access to the global pool of resources. It is re-entrant for unique logical channel values, but SHOULD NOT be called from the user callback function (ISR context).
+ +

+If the request is for a DMA or QDMA channel, check the pParam and pTcc objects also. For the Link channel request, they could be NULL.

+Check the PaRAM Set user has specified for this DMA channel. Two cases exist: a) DCHMAP exists: Any PaRAM Set can be used b) DCHMAP does not exist: Should not be possible only if the channel allocated (ANY) and PaRAM requested are same.

+If some PaRAM set is statically mapped to the returned channel number, use that.

+Channel mapping does not exist. If the PaRAM Set requested is the same as dma channel allocated (coincidentally), it is fine. Else return error.

+Free the previously allocated DMA channel also.

+Check the PaRAM Set user has specified for this DMA channel. Two cases exist: a) DCHMAP exists: Any PaRAM Set can be used b) DCHMAP does not exist: Should not be possible only if the channel allocated (ANY) and PaRAM requested are same.

+If some PaRAM set is statically mapped to the returned channel number, use that.

+Channel mapping does not exist. If the PaRAM Set requested is the same as dma channel allocated (coincidentally), it is fine. Else return error.

+Free the previously allocated DMA channel also.

+Check the PaRAM Set user has specified for this QDMA channel. If he has specified any particular PaRAM Set, use that.

+Check the PaRAM Set user has specified for this QDMA channel. If he has specified any particular PaRAM Set, use that.

+Remove any linking. Before doing that, check whether it is permitted or not.

+For DMA/QDMA channels, we still have to allocate more resources like TCC, PaRAM Set etc. For Link channel, only the PaRAMSet is required and that has been allocated so no further operations required.

+PaRAM Set allocation succeeded. Save the PaRAM Set first.

+Check first whether the global registers and the allocated PaRAM Set can be modified or not. If yes, do the needful. Else leave this for the user.

+Do the mapping between DMA channel and PaRAM Set. Do this for the EDMA3 Controllers which have a register for mapping DMA Channel to a particular PaRAM Set.

+TCC allocation failed, free the previously allocated PaRAM Set and DMA channel.

+PaRAM Set allocation failed, free the previously allocated DMA channel also.

+PaRAM Set allocation succeeded. Save the PaRAM Set first.

+Check first whether the global registers and the allocated PaRAM Set can be modified or not. If yes, do the needful. Else leave this for the user.

+TCC allocation failed, free the previously allocated PaRAM Set and QDMA channel.

+PaRAM Set allocation failed, free the previously allocated QDMA channel also. +

References EDMA3_RM_GblConfigParams::dmaChannelPaRAMMap, EDMA3_RM_GblConfigParams::dmaChannelTccMap, EDMA3_RM_GblConfigParams::dmaChPaRAMMapExists, EDMA3_MAX_PARAM_SETS, EDMA3_MAX_QDMA_CH, EDMA3_RM_allocResource(), EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_DCH_PARAM_CLR_MASK, EDMA3_RM_DCH_PARAM_SET_MASK, EDMA3_RM_DMA_CH_MAX_VAL, EDMA3_RM_DMA_CHANNEL_ANY, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_freeResource(), EDMA3_RM_LINK_CH_MAX_VAL, EDMA3_RM_LINK_CH_MIN_VAL, EDMA3_RM_OPT_TCC_CLR_MASK, EDMA3_RM_OPT_TCC_SET_MASK, EDMA3_RM_PARAM_ANY, EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD, EDMA3_RM_QCH_PARAM_CLR_MASK, EDMA3_RM_QCH_PARAM_SET_MASK, EDMA3_RM_QCH_TRWORD_CLR_MASK, EDMA3_RM_QCH_TRWORD_SET_MASK, EDMA3_RM_QDMA_CH_MIN_VAL, EDMA3_RM_QDMA_CHANNEL_ANY, EDMA3_RM_QDMA_TRIG_DEFAULT, EDMA3_RM_RES_ANY, EDMA3_RM_RES_DMA_CHANNEL, EDMA3_RM_RES_PARAM_SET, EDMA3_RM_RES_QDMA_CHANNEL, EDMA3_RM_RES_TCC, EDMA3_RM_SOK, EDMA3_RM_TCC_ANY, edma3NumPaRAMSets, EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_GblConfigParams::globalRegs, NULL, EDMA3_RM_ChBoundResources::paRAMId, EDMA3_RM_Obj::phyCtrllerInstId, EDMA3_RM_Instance::pResMgrObjHandle, EDMA3_RM_Instance::regModificationRequired, EDMA3_RM_ResDesc::resId, EDMA3_RM_Instance::shadowRegs, EDMA3_RM_ChBoundResources::tcc, TRUE, and EDMA3_RM_ResDesc::type.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
EDMA3_RM_Result EDMA3_RM_allocResource (EDMA3_RM_Handle  hEdmaResMgr,
EDMA3_RM_ResDesc *  resObj 
)
+
+
+ +

+This API is used to allocate specified EDMA3 Resources like DMA/QDMA channel, PaRAM Set or TCC. +

+Note: To free the resources allocated by this API, user should call EDMA3_RM_freeResource () ONLY to de-allocate all the allocated resources.

+User can either request a specific resource by passing the resource id in 'resObj->resId' OR request ANY available resource of the type 'resObj->type'.

+ANY types of resources are those resources when user doesn't care about the actual resource allocated; user just wants a resource of the type specified. One use-case is to perform memory-to-memory data transfer operation. This operation can be performed using any available DMA or QDMA channel. User doesn't need any specific channel for the same.

+To allocate a specific resource, first this API checks whether that resource is OWNED by the Resource Manager instance. Then it checks the current availability of that resource.

+To allocate ANY available resource, this API tries to allocate a resource from the pool of (owned && non_reserved && available_right_now) resources.

+After allocating a DMA/QDMA channel or TCC, the same resource is enabled in the shadow region specific register (DRAE/DRAEH/QRAE).

+Allocated PaRAM Set is initialized to NULL before this API returns if user has requested for one.

+

Parameters:
+ + + +
hEdmaResMgr [IN] Handle to the previously opened Resource Manager Instance.
resObj [IN/OUT] Handle to the resource descriptor object, which needs to be allocated. In case user passes a specific resource Id, resObj value is left unchanged. In case user requests ANY available resource, the allocated resource id is returned in resObj.
+
+
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
+
Note:
This function acquires a RM Instance specific semaphore to prevent simultaneous access to the global pool of resources. It is re-entrant, but should not be called from the user callback function (ISR context).
+ +

+Take the instance specific semaphore, to prevent simultaneous access to the shared resources.

+Check if the register modification flag is set or not.

+Enable the DMA channel in the DRAE/DRAEH registers also.

+Check if the register modification flag is set or not.

+Enable the DMA channel in the DRAE registers also.

+Enable the DMA channel in the DRAEH registers also.

+Check if the register modification flag is set or not.

+Enable the QDMA channel in the QRAE register also.

+Check if the register modification flag is set or not.

+Enable the QDMA channel in the QRAE register also.

+Check if the register modification flag is set or not.

+Enable the Interrupt channel in the DRAE/DRAEH registers also. Also, If the region id coming from this RM instance is same as the Master RM Instance's region id, only then we will be getting the interrupts on the same side. So save the TCC in the allocatedTCCs[] array.

+Do not modify this global array if the register modificatio flag is not set. Reason being is based on this flag, the IPR/ICR or error bit is cleared in the completion or error handler ISR.

+Do not modify this global array if the register modificatio flag is not set. Reason being is based on this flag, the IPR/ICR or error bit is cleared in the completion or error handler ISR.

+Check if the register modification flag is set or not.

+Enable the Interrupt channel in the DRAE/DRAEH registers also. Also, If the region id coming from this RM instance is same as the Master RM Instance's region id, only then we will be getting the interrupts on the same side. So save the TCC in the allocatedTCCs[] array.

+Do not modify this global array if the register modificatio flag is not set. Reason being is based on this flag, the IPR/ICR or error bit is cleared in the completion or error handler ISR.

+Do not modify this global array if the register modificatio flag is not set. Reason being is based on this flag, the IPR/ICR or error bit is cleared in the completion or error handler ISR.

+Also, make the actual PARAM Set NULL, checking the flag whether it is required or not.

+Also, make the actual PARAM Set NULL, checking the flag whether it is required or not.

+Check the Resource Allocation Result 'result' first. If Resource Allocation has resulted in an error, return it (having more priority than semResult. Else, return semResult.

+Resource Allocation successful, return semResult for returning semaphore. +

References allocatedTCCs, EDMA3_RM_Instance::avlblDmaChannels, EDMA3_RM_Instance::avlblPaRAMSets, EDMA3_RM_Instance::avlblQdmaChannels, EDMA3_RM_Instance::avlblTccs, EDMA3_OSSEM_NO_TIMEOUT, EDMA3_RM_E_ALL_RES_NOT_AVAILABLE, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_E_RES_NOT_OWNED, EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE, EDMA3_RM_RES_ANY, EDMA3_RM_RES_DMA_CHANNEL, EDMA3_RM_RES_PARAM_SET, EDMA3_RM_RES_QDMA_CHANNEL, EDMA3_RM_RES_TCC, EDMA3_RM_SOK, edma3MemSet(), edma3OsSemGive(), edma3OsSemTake(), edma3RegionId, FALSE, EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_GblConfigParams::globalRegs, EDMA3_RM_Instance::initParam, NULL, EDMA3_RM_GblConfigParams::numDmaChannels, EDMA3_RM_GblConfigParams::numPaRAMSets, EDMA3_RM_GblConfigParams::numQdmaChannels, EDMA3_RM_GblConfigParams::numTccs, EDMA3_RM_InstanceInitConfig::ownDmaChannels, EDMA3_RM_InstanceInitConfig::ownPaRAMSets, EDMA3_RM_InstanceInitConfig::ownQdmaChannels, EDMA3_RM_InstanceInitConfig::ownTccs, EDMA3_RM_Instance::paramInitRequired, EDMA3_RM_Instance::pResMgrObjHandle, EDMA3_RM_Param::regionId, EDMA3_RM_Instance::regModificationRequired, EDMA3_RM_ResDesc::resId, EDMA3_RM_InstanceInitConfig::resvdDmaChannels, EDMA3_RM_InstanceInitConfig::resvdPaRAMSets, EDMA3_RM_InstanceInitConfig::resvdQdmaChannels, EDMA3_RM_InstanceInitConfig::resvdTccs, EDMA3_RM_Param::rmInstInitConfig, EDMA3_RM_Param::rmSemHandle, EDMA3_RM_Instance::shadowRegs, TRUE, and EDMA3_RM_ResDesc::type.

+ +

Referenced by EDMA3_RM_allocLogicalChannel().

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_RM_Result EDMA3_RM_checkAndClearTcc (EDMA3_RM_Handle  hEdmaResMgr,
unsigned int  tccNo,
unsigned short *  tccStatus 
)
+
+
+ +

+Returns the status of a previously initiated transfer. +

+This is a non-blocking function that returns the status of a previously initiated transfer, based on the IPR/IPRH bit. This bit corresponds to the tccNo specified by the user. It clears the corresponding bit, if SET, while returning also.

+

Parameters:
+ + + + +
hEdmaResMgr [IN] Handle to the previously opened Resource Manager Instance.
tccNo [IN] TCC, specific to which the function checks the status of the IPR/IPRH bit.
tccStatus [IN/OUT] Status of the transfer is returned here. Returns "TRUE" if the transfer has completed (IPR/IPRH bit SET), "FALSE" if the transfer has not completed successfully (IPR/IPRH bit NOT SET).
+
+
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
+
Note:
This function is re-entrant for different tccNo.
+ +

References EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_SOK, FALSE, EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_GblConfigParams::globalRegs, EDMA3_RM_Instance::initParam, NULL, EDMA3_RM_GblConfigParams::numTccs, EDMA3_RM_Instance::pResMgrObjHandle, EDMA3_RM_Param::regionId, and TRUE.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_RM_Result EDMA3_RM_freeContiguousResource (EDMA3_RM_Handle  hEdmaResMgr,
EDMA3_RM_ResDesc *  firstResIdObj,
unsigned int  numResources 
)
+
+
+ +

+Free a contiguous region of specified EDMA3 Resource like DMA channel, QDMA channel, PaRAM Set or TCC, previously allocated. +

+This API frees a contiguous region of specified EDMA3 Resources like DMA channel, QDMA channel, PaRAM Set or TCC, which have been previously allocated. In case of an error during the freeing of any specific resource, user can check the 'firstResIdObj' object to know the last resource id whose freeing has failed. In case of success, there is no need to check this object.

+

Parameters:
+ + + + +
hEdmaResMgr [IN] Handle to the previously opened Resource Manager Instance.
firstResIdObj [IN/OUT] Handle to the first resource descriptor object, which needs to be freed. In case of an error while freeing any particular resource, the last resource id whose freeing has failed is returned in this resource descriptor object.
numResources [IN] Number of contiguous resources allocated previously which user wants to release
+
+
Note:
This is a re-entrant function which internally calls EDMA3_RM_freeResource() for resource de-allocation.
+ +

References EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_freeResource(), EDMA3_RM_RES_DMA_CHANNEL, EDMA3_RM_RES_PARAM_SET, EDMA3_RM_RES_QDMA_CHANNEL, EDMA3_RM_RES_TCC, EDMA3_RM_SOK, EDMA3_RM_Obj::gblCfgParams, NULL, EDMA3_RM_GblConfigParams::numDmaChannels, EDMA3_RM_GblConfigParams::numPaRAMSets, EDMA3_RM_GblConfigParams::numQdmaChannels, EDMA3_RM_GblConfigParams::numTccs, EDMA3_RM_Instance::pResMgrObjHandle, EDMA3_RM_ResDesc::resId, and EDMA3_RM_ResDesc::type.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
EDMA3_RM_Result EDMA3_RM_freeLogicalChannel (EDMA3_RM_Handle  hEdmaResMgr,
EDMA3_RM_ResDesc *  lChObj 
)
+
+
+ +

+This API is used to free the specified channel (DMA/QDMA/Link) and its associated resources (PaRAM Set, TCC etc). +

+This API internally uses EDMA3_RM_freeResource () to free the desired resources.

+For DMA/QDMA channels, it also clears the DCHMAP/QCHMAP registers

+

Parameters:
+ + + +
hEdmaResMgr [IN] Handle to the previously opened Resource Manager Instance.
lChObj [IN] Handle to the logical channel object, which needs to be freed
+
+
Returns:
EDMA3_RM_SOK or EDMA_RM Error Code
+
Note:
This is a re-entrant function which internally calls EDMA3_RM_freeResource () for resource de-allocation.
+ +

+Validate DMA channel id first. It should be a valid channel id.

+Perfectly valid channel id. Clear some channel specific registers, if it is permitted.

+Try to free the DMA Channel now. DMA Channel should be freed only in the end because while freeing, DRAE registers will be RESET. After that, no shadow region specific DMA channel register can be modified. So reset that DRAE register ONLY in the end.

+Calculate QDMA Logical Channel Id first. User has given the actual QDMA channel id. So we have to convert it to make the logical QDMA channel id first.

+Validate QDMA channel id first. It should be a valid channel id.

+Perfectly valid channel id. Clear some channel specific registers, if it is permitted.

+Try to free the QDMA Channel now. QDMA Channel should be freed only in the end because while freeing, QRAE registers will be RESET. After that, no shadow region specific QDMA channel register can be modified. So reset that QDRAE register ONLY in the end. +

References EDMA3_RM_Instance::avlblDmaChannels, EDMA3_RM_Instance::avlblQdmaChannels, EDMA3_RM_GblConfigParams::dmaChPaRAMMapExists, EDMA3_MAX_DMA_CH, EDMA3_MAX_QDMA_CH, EDMA3_MAX_TCC, EDMA3_RM_DCH_PARAM_CLR_MASK, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_freeResource(), EDMA3_RM_LINK_CH_MAX_VAL, EDMA3_RM_LINK_CH_MIN_VAL, EDMA3_RM_QCH_PARAM_CLR_MASK, EDMA3_RM_QCH_TRWORD_CLR_MASK, EDMA3_RM_QDMA_CH_MIN_VAL, EDMA3_RM_RES_DMA_CHANNEL, EDMA3_RM_RES_PARAM_SET, EDMA3_RM_RES_QDMA_CHANNEL, EDMA3_RM_RES_TCC, EDMA3_RM_SOK, edma3NumPaRAMSets, FALSE, EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_GblConfigParams::globalRegs, EDMA3_RM_Instance::initParam, NULL, EDMA3_RM_InstanceInitConfig::ownDmaChannels, EDMA3_RM_InstanceInitConfig::ownQdmaChannels, EDMA3_RM_ChBoundResources::paRAMId, EDMA3_RM_Obj::phyCtrllerInstId, EDMA3_RM_Instance::pResMgrObjHandle, EDMA3_RM_Instance::regModificationRequired, EDMA3_RM_ResDesc::resId, EDMA3_RM_Param::rmInstInitConfig, EDMA3_RM_Instance::shadowRegs, EDMA3_RM_ChBoundResources::tcc, TRUE, and EDMA3_RM_ResDesc::type.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
EDMA3_RM_Result EDMA3_RM_freeResource (EDMA3_RM_Handle  hEdmaResMgr,
const EDMA3_RM_ResDesc *  resObj 
)
+
+
+ +

+This API is used to free previously allocated EDMA3 Resources like DMA/QDMA channel, PaRAM Set or TCC. +

+To free a specific resource, first this API checks whether that resource is OWNED by the Resource Manager Instance. Then it checks whether that resource has been allocated by the Resource Manager instance or not.

+After freeing a DMA/QDMA channel or TCC, the same resource is disabled in the shadow region specific register (DRAE/DRAEH/QRAE).

+

Parameters:
+ + + +
hEdmaResMgr [IN] Handle to the previously opened Resource Manager Instance.
resObj [IN] Handle to the resource descriptor object, which needs to be freed.
+
+
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
+
Note:
This function disables the global interrupts to prevent simultaneous access to the global pool of resources. It is re-entrant.
+ +

+Check if the register modification flag is set or not.

+DMA Channel is freed. Reset the bit specific to the DMA channel in the DRAE/DRAEH register also.

+Check if the register modification flag is set or not.

+QDMA Channel is freed. Reset the bit specific to the QDMA channel in the QRAE register also.

+Check if the register modification flag is set or not.

+Interrupt Channel is freed. Reset the bit specific to the Interrupt channel in the DRAE/DRAEH register also. Also, if we have earlier saved this TCC in allocatedTCCs[] array, remove it from there too. +

References allocatedTCCs, EDMA3_RM_Instance::avlblDmaChannels, EDMA3_RM_Instance::avlblPaRAMSets, EDMA3_RM_Instance::avlblQdmaChannels, EDMA3_RM_Instance::avlblTccs, EDMA3_OS_PROTECT_INTERRUPT, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_E_RES_ALREADY_FREE, EDMA3_RM_E_RES_NOT_OWNED, EDMA3_RM_RES_DMA_CHANNEL, EDMA3_RM_RES_PARAM_SET, EDMA3_RM_RES_QDMA_CHANNEL, EDMA3_RM_RES_TCC, EDMA3_RM_SOK, edma3OsProtectEntry(), edma3OsProtectExit(), edma3RegionId, FALSE, EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_GblConfigParams::globalRegs, EDMA3_RM_Instance::initParam, NULL, EDMA3_RM_InstanceInitConfig::ownDmaChannels, EDMA3_RM_InstanceInitConfig::ownPaRAMSets, EDMA3_RM_InstanceInitConfig::ownQdmaChannels, EDMA3_RM_InstanceInitConfig::ownTccs, EDMA3_RM_Instance::pResMgrObjHandle, EDMA3_RM_Param::regionId, EDMA3_RM_Instance::regModificationRequired, EDMA3_RM_ResDesc::resId, EDMA3_RM_Param::rmInstInitConfig, TRUE, and EDMA3_RM_ResDesc::type.

+ +

Referenced by EDMA3_RM_allocLogicalChannel(), EDMA3_RM_freeContiguousResource(), and EDMA3_RM_freeLogicalChannel().

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_RM_Result EDMA3_RM_getBaseAddress (EDMA3_RM_Handle  hEdmaResMgr,
EDMA3_RM_Cntrlr_PhyAddr  controllerId,
unsigned int *  phyAddress 
)
+
+
+ +

+Get the Channel Controller or Transfer Controller (n) Physical Address. +

+

Parameters:
+ + + + +
hEdmaResMgr [IN] Handle to the previously opened Resource Manager Instance.
controllerId [IN] Channel Controller or Transfer Controller (n) for which the physical address is required.
phyAddress [IN/OUT] Physical address is returned here.
+
+
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
+
Note:
This function is re-entrant.
+ +

+Since the TCs enum start from 1, and TCs start from 0, subtract 1 from the enum to get the actual address. +

References EDMA3_RM_CC_PHY_ADDR, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_SOK, EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_GblConfigParams::globalRegs, NULL, EDMA3_RM_GblConfigParams::numTcs, EDMA3_RM_Instance::pResMgrObjHandle, and EDMA3_RM_GblConfigParams::tcRegs.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_RM_Result EDMA3_RM_getCCRegister (EDMA3_RM_Handle  hEdmaResMgr,
unsigned int  regOffset,
unsigned int *  regValue 
)
+
+
+ +

+Get the Channel Controller (CC) Register value. +

+

Parameters:
+ + + + +
hEdmaResMgr [IN] Handle to the previously opened Resource Manager Instance.
regOffset [IN] CC Register offset whose value is needed. It should be word-aligned.
regValue [IN/OUT] Fetched CC Register Value
+
+
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
+
Note:
This function is re-entrant.
+ +

References EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_SOK, EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_GblConfigParams::globalRegs, NULL, and EDMA3_RM_Instance::pResMgrObjHandle.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
EDMA3_RM_Result EDMA3_RM_getGblConfigParams (unsigned int  phyCtrllerInstId,
EDMA3_RM_GblConfigParams *  gblCfgParams 
)
+
+
+ +

+Get the SoC specific configuration structure for the EDMA3 Hardware. +

+This API is used to fetch the global SoC specific configuration structure for the EDMA3 Hardware. It is useful for the user who has not passed this information during EDMA3_RM_create() and taken the default configuration coming along with the package.

+

Parameters:
+ + + +
phyCtrllerInstId [IN] EDMA3 Controller Instance Id (Hardware instance id, starting from 0).
gblCfgParams [IN/OUT] SoC specific configuration structure for the EDMA3 Hardware will be returned here.
+
+
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
+
Note:
This function is re-entrant.
+ +

References EDMA3_MAX_EDMA3_INSTANCES, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_SOK, edma3MemCpy(), and NULL.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
EDMA3_RM_Result EDMA3_RM_getInstanceInitCfg (EDMA3_RM_Handle  hEdmaResMgr,
EDMA3_RM_InstanceInitConfig *  instanceInitConfig 
)
+
+
+ +

+Get the RM Instance specific configuration structure for different EDMA3 resources' usage (owned resources, reserved resources etc). +

+This API is used to fetch the Resource Manager Instance specific configuration structure, for a specific shadow region. It is useful for the user who has not passed this information during EDMA3_RM_opn() and taken the default configuration coming along with the package. EDMA3 resources, owned and reserved by this RM instance, will be returned from this API.

+

Parameters:
+ + + +
hEdmaResMgr [IN] Handle to the previously opened Resource Manager Instance.
instanceInitConfig [IN/OUT] RM Instance specific configuration structure will be returned here.
+
+
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
+
Note:
This function is re-entrant.
+ +

References EDMA3_MAX_RM_INSTANCES, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_SOK, edma3MemCpy(), NULL, EDMA3_RM_Obj::phyCtrllerInstId, and EDMA3_RM_Instance::pResMgrObjHandle.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_RM_Result EDMA3_RM_getPaRAM (EDMA3_RM_Handle  hEdmaResMgr,
EDMA3_RM_ResDesc *  lChObj,
EDMA3_RM_PaRAMRegs *  currPaRAM 
)
+
+
+ +

+Retrieve existing PaRAM set associated with specified logical channel (DMA/QDMA/Link). +

+

Parameters:
+ + + + +
hEdmaResMgr [IN] Handle to the previously opened Resource Manager Instance.
lChObj [IN] Logical Channel object for which the PaRAM set is requested. User should pass the resource type and id in this object.
currPaRAM [IN/OUT] User gets the existing PaRAM here.
+
+
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
+
Note:
This function is re-entrant.
+ +

+User has passed the actual param set value here. Use this value only +

References EDMA3_MAX_QDMA_CH, EDMA3_RM_DMA_CH_MAX_VAL, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_QDMA_CH_MIN_VAL, EDMA3_RM_RES_DMA_CHANNEL, EDMA3_RM_RES_PARAM_SET, EDMA3_RM_RES_QDMA_CHANNEL, EDMA3_RM_SOK, edma3MemCpy(), edma3NumPaRAMSets, EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_GblConfigParams::globalRegs, NULL, EDMA3_RM_ChBoundResources::paRAMId, EDMA3_RM_Obj::phyCtrllerInstId, EDMA3_RM_Instance::pResMgrObjHandle, EDMA3_RM_ResDesc::resId, and EDMA3_RM_ResDesc::type.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_RM_Result EDMA3_RM_getPaRAMPhyAddr (EDMA3_RM_Handle  hEdmaResMgr,
EDMA3_RM_ResDesc *  lChObj,
unsigned int *  paramPhyAddr 
)
+
+
+ +

+Get the PaRAM Set Physical Address associated with a logical channel. +

+This function returns the PaRAM Set Phy Address (unsigned 32 bits). The returned address could be used by the advanced users to program the PaRAM Set directly without using any APIs.

+Least significant 16 bits of this address could be used to program the LINK field in the PaRAM Set. Users which program the LINK field directly SHOULD use this API to get the associated PaRAM Set address with the LINK channel.

+

Parameters:
+ + + + +
hEdmaResMgr [IN] Handle to the previously opened Resource Manager Instance.
lChObj [IN] Logical Channel object for which the PaRAM set physical address is required. User should pass the resource type and id in this object.
paramPhyAddr [IN/OUT] PaRAM Set physical address is returned here.
+
+
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
+
Note:
This function is re-entrant.
+ +

+User has passed the actual param set value here. Use this value only +

References EDMA3_MAX_QDMA_CH, EDMA3_RM_DMA_CH_MAX_VAL, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_QDMA_CH_MIN_VAL, EDMA3_RM_RES_DMA_CHANNEL, EDMA3_RM_RES_PARAM_SET, EDMA3_RM_RES_QDMA_CHANNEL, EDMA3_RM_SOK, edma3NumPaRAMSets, EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_GblConfigParams::globalRegs, NULL, EDMA3_RM_ChBoundResources::paRAMId, EDMA3_RM_Obj::phyCtrllerInstId, EDMA3_RM_Instance::pResMgrObjHandle, EDMA3_RM_ResDesc::resId, and EDMA3_RM_ResDesc::type.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_RM_Result EDMA3_RM_Ioctl (EDMA3_RM_Handle  hEdmaResMgr,
EDMA3_RM_IoctlCmd  cmd,
void *  cmdArg,
void *  param 
)
+
+
+ +

+EDMA3 Resource Manager IOCTL. +

+This function provides IOCTL functionality for EDMA3 Resource Manager

+

Parameters:
+ + + + + +
hEdmaResMgr [IN] Handle to the previously opened Resource Manager Instance.
cmd [IN] IOCTL command to be performed
cmdArg [IN/OUT] IOCTL command argument (if any)
param [IN/OUT] Device/Cmd specific argument.
+
+
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
+
Note:
For 'EDMA3_RM_IOCTL_GET_PARAM_CLEAR_OPTION', this function is re-entrant. For 'EDMA3_RM_IOCTL_SET_PARAM_CLEAR_OPTION', this function is re-entrant for different Resource Manager Instances (handles).
+This function provides IOCTL functionality for EDMA3 Resource Manager

+

Parameters:
+ + + + + +
hEdmaResMgr [IN] Handle to the previously opened Resource Manager Instance.
cmd [IN] IOCTL command to be performed
cmdArg [IN/OUT] IOCTL command argument (if any)
param [IN/OUT] Device/Cmd specific argument
+
+
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
+ +

+Set/Reset the flag which is being used to do the global registers and PaRAM modification.

+Get the flag which is being used to do the global registers and PaRAM modification. +

References EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_IOCTL_GET_GBL_REG_MODIFY_OPTION, EDMA3_RM_IOCTL_GET_PARAM_CLEAR_OPTION, EDMA3_RM_IOCTL_SET_GBL_REG_MODIFY_OPTION, EDMA3_RM_IOCTL_SET_PARAM_CLEAR_OPTION, EDMA3_RM_SOK, NULL, EDMA3_RM_Instance::paramInitRequired, and EDMA3_RM_Instance::regModificationRequired.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_RM_Result EDMA3_RM_mapEdmaChannel (EDMA3_RM_Handle  hEdmaResMgr,
unsigned int  channelId,
unsigned int  paRAMId 
)
+
+
+ +

+Bind the resources DMA Channel and PaRAM Set. Both the DMA channel and the PaRAM set should be previously allocated. If they are not, this API will result in error. +

+This API sets the DCHMAP register for a specific DMA channel. This register is used to specify the PaRAM Set associated with that particular DMA Channel.

+

Parameters:
+ + + + +
hEdmaResMgr [IN] Handle to the previously opened Resource Manager Instance.
channelId [IN] Previously allocated DMA Channel on which Transfer will occur.
paRAMId [IN] Previously allocated PaRAM Set which needs to be associated with the dma channel.
+
+
Returns:
EDMA3_RM_SOK or EDMA_RM Error Code
+
Note:
This API is useful only for the EDMA3 Controllers which have a register for mapping a DMA Channel to a particular PaRAM Set (DCHMAP register). On platforms where this feature is not supported, this API returns error code: EDMA3_RM_E_FEATURE_UNSUPPORTED. This function is re-entrant for unique channelId. It is non-re-entrant for same channelId values.
+ +

+Do this for the EDMA3 Controllers which have a register for mapping DMA Channel to a particular PaRAM Set. So check dmaChPaRAMMapExists first. +

References EDMA3_RM_Instance::avlblDmaChannels, EDMA3_RM_Instance::avlblPaRAMSets, EDMA3_RM_GblConfigParams::dmaChPaRAMMapExists, EDMA3_RM_DCH_PARAM_CLR_MASK, EDMA3_RM_DCH_PARAM_SET_MASK, EDMA3_RM_E_FEATURE_UNSUPPORTED, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_E_RES_NOT_ALLOCATED, EDMA3_RM_SOK, FALSE, EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_GblConfigParams::globalRegs, EDMA3_RM_Instance::initParam, NULL, EDMA3_RM_GblConfigParams::numDmaChannels, EDMA3_RM_GblConfigParams::numPaRAMSets, EDMA3_RM_InstanceInitConfig::ownDmaChannels, EDMA3_RM_InstanceInitConfig::ownPaRAMSets, EDMA3_RM_Instance::pResMgrObjHandle, EDMA3_RM_Param::rmInstInitConfig, and TRUE.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_RM_Result EDMA3_RM_mapQdmaChannel (EDMA3_RM_Handle  hEdmaResMgr,
unsigned int  channelId,
unsigned int  paRAMId,
EDMA3_RM_QdmaTrigWord  trigWord 
)
+
+
+ +

+Bind the resources QDMA Channel and PaRAM Set. Also, Set the trigger word for the QDMA channel. Both the QDMA channel and the PaRAM set should be previously allocated. If they are not, this API will result in error. +

+This API sets the QCHMAP register for a specific QDMA channel. This register is used to specify the PaRAM Set associated with that particular QDMA Channel along with the trigger word.

+

Parameters:
+ + + + + +
hEdmaResMgr [IN] Handle to the previously opened Resource Manager Instance.
channelId [IN] Previously allocated QDMA Channel on which Transfer will occur.
paRAMId [IN] Previously allocated PaRAM Set, which needs to be associated with channelId
trigWord [IN] The Trigger Word for the channel. Trigger Word is the word in the PaRAM Register Set which - when written to by CPU -will start the QDMA transfer automatically
+
+
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
+
Note:
This function is re-entrant for unique channelId. It is non-re-entrant for same channelId values.
+ +

References EDMA3_RM_Instance::avlblPaRAMSets, EDMA3_RM_Instance::avlblQdmaChannels, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_E_RES_NOT_ALLOCATED, EDMA3_RM_QCH_PARAM_CLR_MASK, EDMA3_RM_QCH_PARAM_SET_MASK, EDMA3_RM_QCH_TRWORD_CLR_MASK, EDMA3_RM_QCH_TRWORD_SET_MASK, EDMA3_RM_QDMA_TRIG_CCNT, EDMA3_RM_QDMA_TRIG_OPT, EDMA3_RM_SOK, FALSE, EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_GblConfigParams::globalRegs, EDMA3_RM_Instance::initParam, NULL, EDMA3_RM_GblConfigParams::numPaRAMSets, EDMA3_RM_GblConfigParams::numQdmaChannels, EDMA3_RM_InstanceInitConfig::ownPaRAMSets, EDMA3_RM_InstanceInitConfig::ownQdmaChannels, EDMA3_RM_Instance::pResMgrObjHandle, and EDMA3_RM_Param::rmInstInitConfig.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_RM_Result EDMA3_RM_setCCRegister (EDMA3_RM_Handle  hEdmaResMgr,
unsigned int  regOffset,
unsigned int  newRegValue 
)
+
+
+ +

+Set the Channel Controller (CC) Register value. +

+

Parameters:
+ + + + +
hEdmaResMgr [IN] Handle to the previously opened Resource Manager Instance.
regOffset [IN] CC Register offset whose value needs to be set. It should be word-aligned.
newRegValue [IN] New CC Register Value
+
+
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
+
Note:
This function is non re-entrant for users using the same Resource Manager handle. Before modifying a register, it tries to acquire a semaphore (RM instance specific), to protect simultaneous modification of the same register by two different users. After the successful change, it releases the semaphore. For users using different RM handles, this function is re-entrant.
+ +

+Take the instance specific semaphore, to prevent simultaneous access to the shared resources. +

References EDMA3_OSSEM_NO_TIMEOUT, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_SOK, edma3OsSemGive(), edma3OsSemTake(), EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_GblConfigParams::globalRegs, EDMA3_RM_Instance::initParam, NULL, EDMA3_RM_Instance::pResMgrObjHandle, and EDMA3_RM_Param::rmSemHandle.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_RM_Result EDMA3_RM_setPaRAM (EDMA3_RM_Handle  hEdmaResMgr,
EDMA3_RM_ResDesc *  lChObj,
const EDMA3_RM_PaRAMRegs *  newPaRAM 
)
+
+
+ +

+Copy the user specified PaRAM Set onto the PaRAM Set associated with the logical channel (DMA/QDMA/Link). +

+This API takes a PaRAM Set as input and copies it onto the actual PaRAM Set associated with the logical channel. OPT field of the PaRAM Set is written first and the CCNT field is written last.

+Caution: It should be used carefully when programming the QDMA channels whose trigger words are not CCNT field.

+

Parameters:
+ + + + +
hEdmaResMgr [IN] Handle to the previously opened Resource Manager Instance.
lChObj [IN] Logical Channel object for which new PaRAM set is specified. User should pass the resource type and id in this object.
newPaRAM [IN] PaRAM set to be copied onto existing one
+
+
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
+
Note:
This function is re-entrant for unique lChObj values. It is non- re-entrant for same lChObj value.
+ +

+User has passed the actual param set value here. Use this value only +

References EDMA3_MAX_QDMA_CH, EDMA3_RM_DMA_CH_MAX_VAL, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_QDMA_CH_MIN_VAL, EDMA3_RM_RES_DMA_CHANNEL, EDMA3_RM_RES_PARAM_SET, EDMA3_RM_RES_QDMA_CHANNEL, EDMA3_RM_SOK, edma3MemCpy(), edma3NumPaRAMSets, EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_GblConfigParams::globalRegs, NULL, EDMA3_RM_ChBoundResources::paRAMId, EDMA3_RM_Obj::phyCtrllerInstId, EDMA3_RM_Instance::pResMgrObjHandle, EDMA3_RM_ResDesc::resId, and EDMA3_RM_ResDesc::type.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
EDMA3_RM_Result EDMA3_RM_waitAndClearTcc (EDMA3_RM_Handle  hEdmaResMgr,
unsigned int  tccNo 
)
+
+
+ +

+Wait for a transfer completion interrupt to occur and clear it. +

+This is a blocking function that returns when the IPR/IPRH bit corresponding to the tccNo specified, is SET. It clears the corresponding bit while returning also.

+This function waits for the specific bit indefinitely in a tight loop, with out any delay in between. USE IT CAUTIOUSLY.

+

Parameters:
+ + + +
hEdmaResMgr [IN] Handle to the previously opened Resource Manager Instance.
tccNo [IN] TCC, specific to which the function waits on a IPR/IPRH bit.
+
+
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
+
Note:
This function is re-entrant for different tccNo.
+ +

+Bit found SET, transfer is completed, clear the pending interrupt and return.

+Bit found SET, transfer is completed, clear the pending interrupt and return. +

References EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_SOK, FALSE, EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_GblConfigParams::globalRegs, EDMA3_RM_Instance::initParam, NULL, EDMA3_RM_GblConfigParams::numTccs, EDMA3_RM_Instance::pResMgrObjHandle, and EDMA3_RM_Param::regionId.

+ +
+

+

+
Generated on Thu Oct 16 16:22:41 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/group__edma3resmgrint.html b/packages/ti/sdo/edma3/rm/docs/html/group__edma3resmgrint.html new file mode 100644 index 0000000..41aa7b9 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/group__edma3resmgrint.html @@ -0,0 +1,38 @@ + + +EDMA3 Resource Manager: Internal Interface Definition for Resource Manager + + + + + +
+

Internal Interface Definition for Resource Manager

+ + + + + + + + + + + +

Modules

 Object Maintenance

Data Structures

struct  EDMA3_RM_ChBoundResources
 EDMA3 Channel-Bound resources. More...
struct  EDMA3_RM_TccCallbackParams
 TCC Callback - Caters to channel specific status reporting. More...
+

Detailed Description

+Documentation of the Internal Interface of Resource Manager
+
Generated on Thu Oct 16 16:22:41 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/group__edma3resmgrintobjmaint.html b/packages/ti/sdo/edma3/rm/docs/html/group__edma3resmgrintobjmaint.html new file mode 100644 index 0000000..4e7d6a5 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/group__edma3resmgrintobjmaint.html @@ -0,0 +1,81 @@ + + +EDMA3 Resource Manager: Object Maintenance + + + + + +
+

Object Maintenance
+ +[Internal Interface Definition for Resource Manager] +

+ + + + + + + + + + + + + + +

Modules

 Boundary Values

Data Structures

struct  EDMA3_RM_Obj
 EDMA3 Hardware Instance Configuration Structure. More...
struct  EDMA3_RM_Instance
 EDMA3 RM Instance Specific Configuration Structure. More...

Enumerations

enum  EDMA3_RM_ObjState {
+  EDMA3_RM_DELETED = 0, +
+  EDMA3_RM_CREATED = 1, +
+  EDMA3_RM_OPENED = 2, +
+  EDMA3_RM_CLOSED = 3 +
+ }
+

Detailed Description

+Maintenance of the EDMA3 Resource Manager Object

Enumeration Type Documentation

+ +
+
+ + + + +
enum EDMA3_RM_ObjState
+
+
+ +

+To maintain the state of the EDMA3 Resource Manager Object

Enumerator:
+ + + + + +
EDMA3_RM_DELETED  +Object deleted
EDMA3_RM_CREATED  +Obect Created
EDMA3_RM_OPENED  +Object Opened
EDMA3_RM_CLOSED  +Object Closed
+
+ +
+

+

+
Generated on Thu Oct 16 16:22:42 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/group__edma3restype.html b/packages/ti/sdo/edma3/rm/docs/html/group__edma3restype.html new file mode 100644 index 0000000..0cca1c0 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/group__edma3restype.html @@ -0,0 +1,83 @@ + + +EDMA3 Resource Manager: Resource Type + + + + + +
+

Resource Type
+ +[Channel Specific Interface] +

+ + + + + + + + + + + + + +

Data Structures

struct  EDMA3_RM_ResDesc
 Handle to a Resource. More...

Defines

+#define EDMA3_RM_RES_ANY   (1010u)
 Used to specify any available Resource Id (EDMA3_RM_ResDesc.resId).

Enumerations

enum  EDMA3_RM_ResType {
+  EDMA3_RM_RES_DMA_CHANNEL = 1, +
+  EDMA3_RM_RES_QDMA_CHANNEL = 2, +
+  EDMA3_RM_RES_TCC = 3, +
+  EDMA3_RM_RES_PARAM_SET = 4 +
+ }
 EDMA3 Resource Type. More...
+

Detailed Description

+Resource Type part of the EDMA3 Resource Manager.

Enumeration Type Documentation

+ +
+
+ + + + +
enum EDMA3_RM_ResType
+
+
+ +

+EDMA3 Resource Type. +

+

Enumerator:
+ + + + + +
EDMA3_RM_RES_DMA_CHANNEL  +DMA Channel resource
EDMA3_RM_RES_QDMA_CHANNEL  +QDMA Channel resource
EDMA3_RM_RES_TCC  +TCC resource
EDMA3_RM_RES_PARAM_SET  +Parameter RAM Set resource
+
+ +
+

+

+
Generated on Thu Oct 16 16:22:39 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/group__edma3rmerrcode.html b/packages/ti/sdo/edma3/rm/docs/html/group__edma3rmerrcode.html new file mode 100644 index 0000000..e388fa0 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/group__edma3rmerrcode.html @@ -0,0 +1,602 @@ + + +EDMA3 Resource Manager: Error Codes + + + + + +
+

Error Codes
+ +[Interface Definition for EDMA3 Resource Manager Layer] +

Usage of Resource Manager. +More... + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Defines

#define EDMA3_RM_E_BASE   (-155)
#define EDMA3_RM_E_OBJ_NOT_DELETED   (EDMA3_RM_E_BASE)
#define EDMA3_RM_E_OBJ_NOT_CLOSED   (EDMA3_RM_E_BASE-1)
#define EDMA3_RM_E_OBJ_NOT_OPENED   (EDMA3_RM_E_BASE-2)
#define EDMA3_RM_E_INVALID_PARAM   (EDMA3_RM_E_BASE-3)
#define EDMA3_RM_E_RES_ALREADY_FREE   (EDMA3_RM_E_BASE-4)
#define EDMA3_RM_E_RES_NOT_OWNED   (EDMA3_RM_E_BASE-5)
#define EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE   (EDMA3_RM_E_BASE-6)
#define EDMA3_RM_E_ALL_RES_NOT_AVAILABLE   (EDMA3_RM_E_BASE-7)
#define EDMA3_RM_E_INVALID_STATE   (EDMA3_RM_E_BASE-8)
#define EDMA3_RM_E_MAX_RM_INST_OPENED   (EDMA3_RM_E_BASE-9)
#define EDMA3_RM_E_RM_MASTER_ALREADY_EXISTS   (EDMA3_RM_E_BASE-10)
#define EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED   (EDMA3_RM_E_BASE-11)
#define EDMA3_RM_E_SEMAPHORE   (EDMA3_RM_E_BASE-12)
#define EDMA3_RM_E_FEATURE_UNSUPPORTED   (EDMA3_RM_E_BASE-13)
#define EDMA3_RM_E_RES_NOT_ALLOCATED   (EDMA3_RM_E_BASE-14)
+

Detailed Description

+Usage of Resource Manager. +

+

    +
  1. Create Resource Manager Object (one for each EDMA3 hardware instance)
      +
    • EDMA3_RM_Result result = EDMA3_RM_SOK;
    • unsigned int edma3HwInstanceId = 0u;
    • EDMA3_RM_GblConfigParams *gblCfgParams = NULL;
    • Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. This could be NULL also. In that case, static configuration will be taken.
    • result = EDMA3_RM_create (edma3HwInstanceId, gblCfgParams, NULL);
    +
  2. Open Resource Manager Instance
      +
    • Steps
        +
      • EDMA3_RM_Param initParam;
      • unsigned int resMgrIdx = 0;
      • EDMA3_RM_Handle hRes = NULL;
      • unsigned int mappedPaRAMId;
      • EDMA3_OS_SemAttrs semAttrs = {EDMA3_OS_SEMTYPE_FIFO, NULL};
      • EDMA3_RM_Result edma3Result; -To get the error code while opening Resource Manager instance
      +
    +
+

+

    +
  1. initParam.regionId = Region Id e.g. (EDMA3_RM_RegionId)0u OR (EDMA3_RM_RegionId)1u
+

+

    +
  1. initParam.isMaster = TRUE/FALSE (Whether this EDMA3 RM instance is Master or not. The EDMA3 Shadow Region tied to the Master RM Instance will ONLY receive the EDMA3 interrupts (error or completion), if enabled).
+

+

    +
  1. initParam.rmSemHandle = EDMA3 RM Instance specific semaphore handle. It should be provided by the user for proper sharing of resources.
      +
    • edma3Result = edma3OsSemCreate(1, &semAttrs, &initParam.rmSemHandle );
    +
+

+

    +
  1. initParam.regionInitEnable = TRUE/FALSE (Whether init of Region Specifc registers should be done or not?);
+

+

    +
  1. initParam.gblerrCbParams.gblerrCb = Instance wide callback function to catch non-channel specific errors
  2. initParam.gblerrCbParams.gblerrData = Data to be passed to global error callback function, gblerrCb.
+

+

    +
  1. initParam.rmInstInitConfig->ownDmaChannels[] = The bitmap(s) which indicate the DMA channels owned by this instance of the Resource Manager
    + E.g. A '1' at bit position 24 indicates that this instance of the Resource Manager owns DMA Channel Id 24
    + Later when a request is made based on a particular Channel Id, the Resource Manager will check first if it owns that channel. If it doesnot own it, Resource Manager returns error EDMA3_RM_E_RES_NOT_OWNED.
  2. initParam.rmInstInitConfig->ownQdmaChannels[] = The bitmap(s) which indicate the QDMA channels owned by this instance of the Resource Manager
    +
  3. initParam.rmInstInitConfig->ownPaRAMSets[] = The bitmap(s) which indicate the PaRAM Sets owned by this instance of the Resource Manager
    +
  4. initParam.rmInstInitConfig->ownTccs[] = The bitmap(s) which indicate the TCCs owned by this instance of the Resource Manager
    +
+

+

    +
  1. initParam.rmInstInitConfig->resvdDmaChannels[] = The bitmap(s) which indicate the DMA channels reserved by this instance of the Resource Manager
    + E.g. A '1' at bit position 24 indicates that this instance of the Resource Manager reserves Channel Id 24
    + These channels are reserved and may be mapped to HW events, these are not given to 'EDMA3_RM_DMA_CHANNEL_ANY' or 'EDMA3_RM_RES_ANY' requests.
    +
  2. initParam.rmInstInitConfig->resvdQdmaChannels[] = The bitmap(s) which indicate the QDMA channels reserved by this instance of the Resource Manager
    + E.g. A '1' at bit position 1 indicates that this instance of the Resource Manager reserves QDMA Channel Id 1
    + These channels are reserved for some specific purpose, these are not given to 'EDMA3_RM_QDMA_CHANNEL_ANY' or 'EDMA3_RM_RES_ANY' request
    +
  3. initParam.rmInstInitConfig->resvdPaRAMSets[] = PaRAM Sets which are reserved by this Region;
  4. initParam.rmInstInitConfig->resvdTccs[] = TCCs which are reserved by this Region;
+

+-hRes = EDMA3_RM_open (instId, &initParam, &edma3Result);

+

    +
  1. Register Interrupt Handlers for various interrupts like transfer completion interrupt, CC error interrupt, TC error interrupts etc, if required.
+

+

    +
  1. Resource Management APIs:
      +
    • EDMA3_RM_ResDesc resObj;
    • EDMA3_RM_Result result;
    • unsigned int dmaChId;
    • unsigned int qdmaChId;
    • unsigned int paRAMId;
    • unsigned int tcc;
    • EDMA3_RM_QdmaTrigWord trigword;
    • EDMA3_RM_TccCallback tccCb;
    • void *cbData;
    +
+

+

    +
  • Use Case 1: Request specific DMA Channel, say EDMA Channel 5.
    +
    +
      +
    • dmaChId = 5;
      +
      +
    • resObj.type = EDMA3_RM_RES_DMA_CHANNEL;
    • resObj.resId = dmaChId;
    • result = EDMA3_RM_allocResource(hRes, &resObj);
      +
      +
    +
+

+

    +
  • Use Case 2: Request any available DMA Channel.
    +
    +
      +
    • dmaChId = EDMA3_RM_RES_ANY;
      +
      +
    • resObj.type = EDMA3_RM_RES_DMA_CHANNEL;
    • resObj.resId = dmaChId;
    • result = EDMA3_RM_allocResource(hRes, &resObj);
      +
      +
    • dmaCh1Id = resObj.resId;
      +
      +
    +
+

+

    +
  • Use Case 3: Request a specific QDMA Channel, say QDMA Channel 0.
    +
    +
      +
    • qdmaChId = 0;
      +
      +
    • resObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
    • resObj.resId = qdmaChId;
    • result = EDMA3_RM_allocResource(hRes, &resObj);
      +
      +
    +
+

+

    +
  • Use Case 4: Request any available QDMA Channel.
    +
    +
      +
    • qdmaChId = EDMA3_RM_RES_ANY;
      +
      +
    • resObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
    • resObj.resId = qdmaChId;
    • result = EDMA3_RM_allocResource(hRes, &resObj);
      +
      +
    • qdmaChId = resObj.resId;
      +
      +
    +
+

+

    +
  • Use Case 5: Request specific Parameter RAM Set, say 20.
    +
    +
      +
    • paRAMId = 20;
      +
      +
    • resObj.type = EDMA3_RM_RES_PARAM_SET;
    • resObj.resId = paRAMId;
    • result = EDMA3_RM_allocResource(hRes, &resObj);
      +
      +
    +
+

+

    +
  • Use Case 6: Request any available Parameter RAM Set.
    +
    +
      +
    • paRAMId = EDMA3_RM_RES_ANY;
      +
      +
    • resObj.type = EDMA3_RM_RES_PARAM_SET;
    • resObj.resId = paRAMId;
    • result = EDMA3_RM_allocResource(hRes, &resObj);
      +
      +
    • paRAMId = resObj.resId;
      +
      +
    +
+

+

    +
  • Use Case 7: Request a specific TCC, say TCC 35.
    +
    +
      +
    • tcc = 35;
      +
      +
    • resObj.type = EDMA3_RM_RES_TCC;
    • resObj.resId = tcc;
    • result = EDMA3_RM_allocResource(hRes, &resObj);
      +
      +
    +
+

+

    +
  • Use Case 8: Request any available TCC.
    +
    +
      +
    • tcc = EDMA3_RM_RES_ANY;
      +
      +
    • resObj.type = EDMA3_RM_RES_TCC;
    • resObj.resId = tcc;
    • result = EDMA3_RM_allocResource(hRes, &resObj);
      +
      +
    • tcc = resObj.resId;
      +
      +
    +
+

+

    +
  • Use Case 9: Free the already allocated DMA channel
      +
    • resObj.type = EDMA3_RM_RES_DMA_CHANNEL;
    • resObj.resId = dmaChId;
    • result = EDMA3_RM_freeResource(hRes, &resObj);
      +
      +
    +
+

+

    +
  • Use Case 10: Free the already allocated QDMA channel
      +
    • resObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
    • resObj.resId = qdmaChId;
    • result = EDMA3_RM_freeResource(hRes, &resObj);
      +
      +
    +
+

+

    +
  • Use Case 11: Free the already allocated PaRAM Set
      +
    • resObj.type = EDMA3_RM_RES_PARAM_SET;
    • resObj.resId = paRAMId;
    • result = EDMA3_RM_freeResource(hRes, &resObj);
      +
      +
    +
+

+

    +
  • Use Case 12: Free the already allocated TCC
      +
    • resObj.type = EDMA3_RM_RES_TCC;
    • resObj.resId = tcc;
    • result = EDMA3_RM_freeResource(hRes, &resObj);
      +
      +
    +
+

+

    +
  • Use Case 13: Bind DMA Channel and a PaRAM Set
      +
    • result = EDMA3_RM_mapEdmaChannel (hRes,dmaChId,paRAMId);
      +
      +
    +
+

+

    +
  • Use Case 14: Bind QDMA Channel and a PaRAM Set. Also, specify the Trigger word for the QDMA channel.
      +
    • result = EDMA3_RM_mapQdmaChannel (hRes, qdmaChId, paRAMId, trigword);
      +
      +
    +
+

+

    +
  • Use Case 15: Register a Callback function associated with a TCC
    +
    +
      +
    • result = EDMA3_RM_registerTccCb (hRes,tcc,tccCb,cbData);
      +
      +
    +
+

+

    +
  • Use Case 16: Unregister a Callback function associated with a TCC
    +
    +
      +
    • result = EDMA3_RM_unregisterTccCb (hRes,tcc);
      +
      +
    +
+

+

    +
  • Use Case 17: Allocate a logical (ANY) DMA channel. It will also allocate PaRAM Set and TCC alongwitht a DMA channel.
      +
    • resObj.type = EDMA3_RM_RES_DMA_CHANNEL;
    • resObj.resId = EDMA3_RM_DMA_CHANNEL_ANY;
    • result = EDMA3_RM_allocLogicalChannel (hRes, &resObj, paRAMId, tcc);
    • dmaCh1Id = resObj.resId;
      +
      +
    +
+

+

    +
  • Use Case 18: Allocate a logical (ANY) QDMA channel. It will also allocate PaRAM Set and TCC alongwitht a QDMA channel.
      +
    • resObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
    • resObj.resId = EDMA3_RM_QDMA_CHANNEL_ANY;
    • result = EDMA3_RM_allocLogicalChannel (hRes, &resObj, paRAMId, tcc);
    • qdmaChId = resObj.resId;
      +
      +
    +
+

+

    +
  • Use Case 19: Allocate a Link channel. Link channel is nothing but a PaRAM Set, used for Linking purpose specifically. The allocated PaRAM Set is returned in the resObj.resId value.
      +
    • resObj.type = EDMA3_RM_RES_PARAM_SET;
    • resObj.resId = EDMA3_RM_PARAM_ANY;
    • result = EDMA3_RM_allocLogicalChannel (hRes, &resObj, NULL, NULL);
    +
+

+

    +
  • Use Case 20: Free the previously allocated Link channel. It will free the PaRAM Set used for linking.
      +
    • result = EDMA3_RM_freeLogicalChannel (hRes, &resObj);
    +
+

+

    +
  • Use Case 21: Free the previously allocated logical DMA channel. It will also free the associated PaRAM Set and TCC.
      +
    • resObj.type = EDMA3_RM_RES_DMA_CHANNEL;
    • resObj.resId = dmaCh1Id;
    • result = EDMA3_RM_freeLogicalChannel (hRes, &resObj);
    +
+

+

    +
  • Use Case 22: Free the previously allocated logical QDMA channel. It will also free the associated PaRAM Set and TCC.
      +
    • resObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
    • resObj.resId = qdmaChId;
    • result = EDMA3_RM_freeLogicalChannel (hRes, &resObj);
    +
+

+

    +
  1. Close Resource Manager Instance
      +
    • Steps
        +
      • EDMA3_RM_Result edma3Result = EDMA3_RM_SOK;
      +
    +
+

+

    +
  • Unregister Interrupt Handlers first, if previously registered.
  • Delete the semaphore created during RM Instance Opening.
      +
    • edma3Result = edma3OsSemDelete (rmSemHandle);
    +
  • Close the EDMA3 RM Instance
      +
    • edma3Result = EDMA3_RM_close (hRes, NULL);
    +
+

+

    +
  1. Delete Resource Manager Object
      +
    • Steps
        +
      • EDMA3_RM_Result edma3Result = EDMA3_RM_SOK;
      • unsigned int edmaInstanceId = 0;
      +
    +
+

+

    +
  • edma3Result = EDMA3_RM_delete (edmaInstanceId, NULL);
+

+Error Codes returned by the EDMA3 Resource Manager Layer

Define Documentation

+ +
+
+ + + + +
#define EDMA3_RM_E_ALL_RES_NOT_AVAILABLE   (EDMA3_RM_E_BASE-7)
+
+
+ +

+No Resource of specified type is available +

Referenced by EDMA3_RM_allocResource().

+ +
+

+ +

+
+ + + + +
#define EDMA3_RM_E_BASE   (-155)
+
+
+ +

+Resource Manager Error Codes base define +

+

+ +

+
+ + + + +
#define EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED   (EDMA3_RM_E_BASE-11)
+
+
+ +

+Callback function already registered. +

Referenced by EDMA3_RM_registerTccCb().

+ +
+

+ +

+
+ + + + +
#define EDMA3_RM_E_FEATURE_UNSUPPORTED   (EDMA3_RM_E_BASE-13)
+
+
+ +

+Hardware feature NOT supported +

Referenced by EDMA3_RM_mapEdmaChannel().

+ +
+

+ +

+
+ + + + +
#define EDMA3_RM_E_INVALID_PARAM   (EDMA3_RM_E_BASE-3)
+
+
+ +

+Invalid Parameter passed to API +

Referenced by allocAnyContigRes(), EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocLogicalChannel(), EDMA3_RM_allocResource(), EDMA3_RM_checkAndClearTcc(), EDMA3_RM_close(), EDMA3_RM_create(), EDMA3_RM_delete(), EDMA3_RM_freeContiguousResource(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_freeResource(), EDMA3_RM_getBaseAddress(), EDMA3_RM_getCCRegister(), EDMA3_RM_getGblConfigParams(), EDMA3_RM_getInstanceInitCfg(), EDMA3_RM_getPaRAM(), EDMA3_RM_getPaRAMPhyAddr(), EDMA3_RM_Ioctl(), EDMA3_RM_mapEdmaChannel(), EDMA3_RM_mapQdmaChannel(), EDMA3_RM_open(), EDMA3_RM_registerTccCb(), EDMA3_RM_setCCRegister(), EDMA3_RM_setPaRAM(), EDMA3_RM_unregisterTccCb(), EDMA3_RM_waitAndClearTcc(), findBit(), and gblChngAllocContigRes().

+ +
+

+ +

+
+ + + + +
#define EDMA3_RM_E_INVALID_STATE   (EDMA3_RM_E_BASE-8)
+
+
+ +

+Invalid State of EDMA3 RM Obj +

Referenced by EDMA3_RM_delete(), and EDMA3_RM_open().

+ +
+

+ +

+
+ + + + +
#define EDMA3_RM_E_MAX_RM_INST_OPENED   (EDMA3_RM_E_BASE-9)
+
+
+ +

+Maximum no of Res Mgr Instances already Opened +

Referenced by EDMA3_RM_open().

+ +
+

+ +

+
+ + + + +
#define EDMA3_RM_E_OBJ_NOT_CLOSED   (EDMA3_RM_E_BASE-1)
+
+
+ +

+Resource Manager Object Not Closed yet. So the object cannot be deleted. +

Referenced by EDMA3_RM_delete().

+ +
+

+ +

+
+ + + + +
#define EDMA3_RM_E_OBJ_NOT_DELETED   (EDMA3_RM_E_BASE)
+
+
+ +

+Resource Manager Object Not Deleted yet. So the object cannot be created. +

Referenced by EDMA3_RM_create().

+ +
+

+ +

+
+ + + + +
#define EDMA3_RM_E_OBJ_NOT_OPENED   (EDMA3_RM_E_BASE-2)
+
+
+ +

+Resource Manager Object Not Opened yet So the object cannot be closed. +

Referenced by EDMA3_RM_close().

+ +
+

+ +

+
+ + + + +
#define EDMA3_RM_E_RES_ALREADY_FREE   (EDMA3_RM_E_BASE-4)
+
+
+ +

+Resource requested for freeing is already free +

Referenced by EDMA3_RM_freeResource().

+ +
+

+ +

+
+ + + + +
#define EDMA3_RM_E_RES_NOT_ALLOCATED   (EDMA3_RM_E_BASE-14)
+
+
+ +

+EDMA3 Resource NOT allocated +

Referenced by EDMA3_RM_mapEdmaChannel(), and EDMA3_RM_mapQdmaChannel().

+ +
+

+ +

+
+ + + + +
#define EDMA3_RM_E_RES_NOT_OWNED   (EDMA3_RM_E_BASE-5)
+
+
+ +

+Resource requested for allocation/freeing is not owned +

Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), and EDMA3_RM_freeResource().

+ +
+

+ +

+
+ + + + +
#define EDMA3_RM_E_RM_MASTER_ALREADY_EXISTS   (EDMA3_RM_E_BASE-10)
+
+
+ +

+More than one Res Mgr Master Instance NOT supported. Only 1 master can exist. +

Referenced by EDMA3_RM_open().

+ +
+

+ +

+
+ + + + +
#define EDMA3_RM_E_SEMAPHORE   (EDMA3_RM_E_BASE-12)
+
+
+ +

+Semaphore related error +

+

+ +

+
+ + + + +
#define EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE   (EDMA3_RM_E_BASE-6)
+
+
+ +

+Resource is not available +

Referenced by allocAnyContigRes(), EDMA3_RM_allocContiguousResource(), and EDMA3_RM_allocResource().

+ +
+

+

+
Generated on Thu Oct 16 16:22:40 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/group__edma3rmintboundvals.html b/packages/ti/sdo/edma3/rm/docs/html/group__edma3rmintboundvals.html new file mode 100644 index 0000000..5173c30 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/group__edma3rmintboundvals.html @@ -0,0 +1,143 @@ + + +EDMA3 Resource Manager: Boundary Values + + + + + +
+

Boundary Values
+ +[Object Maintenance] +

+ + + + + + + + + + + + + + +

Defines

#define EDMA3_RM_DMA_CH_MAX_VAL   (EDMA3_MAX_DMA_CH - 1u)
#define EDMA3_RM_LINK_CH_MIN_VAL   (EDMA3_MAX_DMA_CH)
#define EDMA3_RM_LINK_CH_MAX_VAL   (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS - 1u)
#define EDMA3_RM_QDMA_CH_MIN_VAL   (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS)
#define EDMA3_RM_QDMA_CH_MAX_VAL   (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS + EDMA3_MAX_QDMA_CH - 1u)
#define EDMA3_RM_LOG_CH_MAX_VAL   (EDMA3_RM_QDMA_CH_MAX_VAL)
+

Detailed Description

+Boundary Values for Logical Channel Ranges

Define Documentation

+ +
+
+ + + + +
#define EDMA3_RM_DMA_CH_MAX_VAL   (EDMA3_MAX_DMA_CH - 1u)
+
+
+ +

+Max of DMA Channels +

Referenced by EDMA3_RM_allocLogicalChannel(), EDMA3_RM_getPaRAM(), EDMA3_RM_getPaRAMPhyAddr(), and EDMA3_RM_setPaRAM().

+ +
+

+ +

+
+ + + + +
#define EDMA3_RM_LINK_CH_MAX_VAL   (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS - 1u)
+
+
+ +

+Max of Link Channels +

Referenced by EDMA3_RM_allocLogicalChannel(), and EDMA3_RM_freeLogicalChannel().

+ +
+

+ +

+
+ + + + +
#define EDMA3_RM_LINK_CH_MIN_VAL   (EDMA3_MAX_DMA_CH)
+
+
+ +

+Min of Link Channels +

Referenced by EDMA3_RM_allocLogicalChannel(), and EDMA3_RM_freeLogicalChannel().

+ +
+

+ +

+
+ + + + +
#define EDMA3_RM_LOG_CH_MAX_VAL   (EDMA3_RM_QDMA_CH_MAX_VAL)
+
+
+ +

+Max of Logical Channels +

+

+ +

+
+ + + + +
#define EDMA3_RM_QDMA_CH_MAX_VAL   (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS + EDMA3_MAX_QDMA_CH - 1u)
+
+
+ +

+Max of QDMA Channels +

+

+ +

+
+ + + + +
#define EDMA3_RM_QDMA_CH_MIN_VAL   (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS)
+
+
+ +

+Min of QDMA Channels +

Referenced by EDMA3_RM_allocLogicalChannel(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_getPaRAM(), EDMA3_RM_getPaRAMPhyAddr(), and EDMA3_RM_setPaRAM().

+ +
+

+

+
Generated on Thu Oct 16 16:22:42 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/group__edma3rmintrmgrchannel.html b/packages/ti/sdo/edma3/rm/docs/html/group__edma3rmintrmgrchannel.html new file mode 100644 index 0000000..e6ca179 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/group__edma3rmintrmgrchannel.html @@ -0,0 +1,171 @@ + + +EDMA3 Resource Manager: Channel Specific Interface + + + + + +
+

Channel Specific Interface
+ +[Instance Wide Interface] +

+ + + + + + + + + + + + + + + +

Modules

 Resource Type

Typedefs

typedef void(* EDMA3_RM_TccCallback )(unsigned int tcc, EDMA3_RM_TccStatus status, void *appData)
 TCC callback - caters to channel-specific events like "Event Miss Error" or "Transfer Complete". Runs in ISR context.

Functions

EDMA3_RM_Result EDMA3_RM_registerTccCb (EDMA3_RM_Handle hEdmaResMgr, const EDMA3_RM_ResDesc *channelObj, unsigned int tcc, EDMA3_RM_TccCallback tccCb, void *cbData)
 Register Interrupt / Completion Handler for a given TCC.
EDMA3_RM_Result EDMA3_RM_unregisterTccCb (EDMA3_RM_Handle hEdmaResMgr, const EDMA3_RM_ResDesc *channelObj)
 Unregister the previously registered callback function against a DMA/QDMA channel.
+

Detailed Description

+Channel Specific Interface of the EDMA3 Interrupt Manager Layer

Typedef Documentation

+ +
+
+ + + + +
typedef void(* EDMA3_RM_TccCallback)(unsigned int tcc, EDMA3_RM_TccStatus status, void *appData)
+
+
+ +

+TCC callback - caters to channel-specific events like "Event Miss Error" or "Transfer Complete". Runs in ISR context. +

+appData is passed by the application during Register'ing of TCC Callback function. +

+

+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_RM_Result EDMA3_RM_registerTccCb (EDMA3_RM_Handle  hEdmaResMgr,
const EDMA3_RM_ResDesc *  channelObj,
unsigned int  tcc,
EDMA3_RM_TccCallback  tccCb,
void *  cbData 
)
+
+
+ +

+Register Interrupt / Completion Handler for a given TCC. +

+This function enables the interrupts in IESR/IESRH, only if the callback function provided by the user is NON-NULL. Moreover, if a call-back function is already registered against that TCC, the API fails with the error code EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED. For a NULL callback function, this API returns error.

+

Parameters:
+ + + + + + +
hEdmaResMgr [IN] Handle to the previously opened EDMA3 Resource Manager Instance
channelObj [IN] Channel ID and type (DMA or QDMA Channel), allocated earlier, and corresponding to which a callback function needs to be registered against the associated TCC.
tcc [IN] TCC against which the handler needs to be registered.
tccCb [IN] The Callback function to be registered against the TCC.
cbData [IN] Callback data to be passed while calling the callback function.
+
+
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
+
Note:
This function is re-entrant for unique tcc values. It is non- re-entrant for same tcc value.
+ +

+Enable the interrupts in IESR/IESRH, only if the Callback function is NOT NULL. +

References EDMA3_RM_TccCallbackParams::cbData, EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_RES_DMA_CHANNEL, EDMA3_RM_RES_QDMA_CHANNEL, EDMA3_RM_SOK, edma3DmaChTccMapping, edma3QdmaChTccMapping, EDMA3_RM_Obj::gblCfgParams, NULL, EDMA3_RM_GblConfigParams::numDmaChannels, EDMA3_RM_GblConfigParams::numQdmaChannels, EDMA3_RM_GblConfigParams::numTccs, EDMA3_RM_Instance::pResMgrObjHandle, EDMA3_RM_ResDesc::resId, EDMA3_RM_Instance::shadowRegs, EDMA3_RM_TccCallbackParams::tccCb, and EDMA3_RM_ResDesc::type.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
EDMA3_RM_Result EDMA3_RM_unregisterTccCb (EDMA3_RM_Handle  hEdmaResMgr,
const EDMA3_RM_ResDesc *  channelObj 
)
+
+
+ +

+Unregister the previously registered callback function against a DMA/QDMA channel. +

+This function unregisters the previously registered callback function against a DMA/QDMA channel by removing any stored callback function. Moreover, it clears the interrupt enable register (IESR/IESRH) by writing to the IECR/ IECRH register, for the TCC associated with that particular channel.

+

Parameters:
+ + + +
hEdmaResMgr [IN] Handle to the previously opened EDMA3 Resource Manager Instance
channelObj [IN] Channel ID and type, allocated earlier (DMA or QDMA Channel ONLY), and corresponding to which a TCC is there. Against that TCC, the callback needs to be un-registered.
+
+
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code.
+
Note:
This function is re-entrant for unique (channelObj->type + channelObj->resId) combination. It is non-re-entrant for same channelObj Resource.
+ +

References EDMA3_RM_TccCallbackParams::cbData, EDMA3_MAX_TCC, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_RES_DMA_CHANNEL, EDMA3_RM_RES_QDMA_CHANNEL, EDMA3_RM_SOK, edma3DmaChTccMapping, edma3QdmaChTccMapping, EDMA3_RM_Obj::gblCfgParams, NULL, EDMA3_RM_GblConfigParams::numDmaChannels, EDMA3_RM_GblConfigParams::numQdmaChannels, EDMA3_RM_Instance::pResMgrObjHandle, EDMA3_RM_ResDesc::resId, EDMA3_RM_Instance::shadowRegs, EDMA3_RM_TccCallbackParams::tccCb, and EDMA3_RM_ResDesc::type.

+ +
+

+

+
Generated on Thu Oct 16 16:22:39 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/group__edma3rmintrmgrinst.html b/packages/ti/sdo/edma3/rm/docs/html/group__edma3rmintrmgrinst.html new file mode 100644 index 0000000..fe10ae1 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/group__edma3rmintrmgrinst.html @@ -0,0 +1,36 @@ + + +EDMA3 Resource Manager: Instance Wide Interface + + + + + +
+

Instance Wide Interface
+ +[EDMA3 Interrupt Manager Interface] +

+ + + + + + +

Modules

 Completion status
 Channel Specific Interface
+

Detailed Description

+Instance Wide Interface of the EDMA3 Interrupt Manager Layer
+
Generated on Thu Oct 16 16:22:39 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/group__edma3rmintrmgrmain.html b/packages/ti/sdo/edma3/rm/docs/html/group__edma3rmintrmgrmain.html new file mode 100644 index 0000000..88021fa --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/group__edma3rmintrmgrmain.html @@ -0,0 +1,36 @@ + + +EDMA3 Resource Manager: EDMA3 Interrupt Manager Interface + + + + + +
+

EDMA3 Interrupt Manager Interface

+ + + + + + + + +

Modules

 Instance Wide Interface
 Interface Definition for EDMA3 Resource Manager Layer
 EDMA3 Resources Management
+

Detailed Description

+Include common header file

+Top-level Encapsulation of documentation for EDMA3 Interrupt Manager Layer

+
Generated on Thu Oct 16 16:22:39 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/group__edma3rmmain.html b/packages/ti/sdo/edma3/rm/docs/html/group__edma3rmmain.html new file mode 100644 index 0000000..ef345ee --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/group__edma3rmmain.html @@ -0,0 +1,327 @@ + + +EDMA3 Resource Manager: Interface Definition for EDMA3 Resource Manager Layer + + + + + +
+

Interface Definition for EDMA3 Resource Manager Layer
+ +[EDMA3 Interrupt Manager Interface] +

+ + + + + + + + +

+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Modules

 EDMA3 Resource Manager Usage Guidelines
 Error Codes
 Usage of Resource Manager.

Data Structures

struct  EDMA3_RM_GblConfigParams
 Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. More...
struct  EDMA3_RM_InstanceInitConfig
 Init-time Region Specific Configuration structure for EDMA3 RM, to provide region specific Information. More...
struct  EDMA3_RM_Param
 Used to Initialize the Resource Manager Instance. More...
struct  EDMA3_RM_MiscParam
 Used to specify the miscellaneous options during Resource Manager Initialization. More...

Typedefs

typedef unsigned int EDMA3_RM_RegionId
 EDMA3 Region Id.
typedef unsigned int EDMA3_RM_EventQueue
 EDMA3 Event Queue assignment.

Functions

EDMA3_RM_Result EDMA3_RM_create (unsigned int phyCtrllerInstId, const EDMA3_RM_GblConfigParams *gblCfgParams, const void *miscParam)
 Create EDMA3 Resource Manager Object.
EDMA3_RM_Result EDMA3_RM_delete (unsigned int phyCtrllerInstId, const void *param)
 Delete EDMA3 Resource Manager Object.
EDMA3_RM_Handle EDMA3_RM_open (unsigned int phyCtrllerInstId, const EDMA3_RM_Param *initParam, EDMA3_RM_Result *errorCode)
 Open EDMA3 Resource Manager Instance.
EDMA3_RM_Result EDMA3_RM_close (EDMA3_RM_Handle hEdmaResMgr, const void *param)
 Close EDMA3 Resource Manager Instance.
+

Detailed Description

+Top-level Encapsulation of all documentation for EDMA3 Resource Manager Layer

Typedef Documentation

+ +
+
+ + + + +
EDMA3_RM_EventQueue
+
+
+ +

+EDMA3 Event Queue assignment. +

+There can be 8 Event Queues. Either of them can be assigned to a DMA/QDMA channel using this. +

+

+ +

+
+ + + + +
EDMA3_RM_RegionId
+
+
+ +

+EDMA3 Region Id. +

+Use this to assign channels/PaRAM sets/TCCs to a particular Region. +

+

+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
EDMA3_RM_Result EDMA3_RM_close (EDMA3_RM_Handle  hEdmaResMgr,
const void *  param 
)
+
+
+ +

+Close EDMA3 Resource Manager Instance. +

+This API is used to close a previously opened EDMA3 RM Instance.

+

Parameters:
+ + + +
hEdmaResMgr [IN] Handle to the previously opened Resource Manager Instance.
param [IN] For possible future use.
+
+
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
+
Note:
This function disables the global interrupts (by calling API edma3OsProtectEntry with protection level EDMA3_OS_PROTECT_INTERRUPT) while modifying the global RM data structures, to make it re-entrant.
+ +

+If this is the Master Instance, reset the static variable 'masterExists'. +

References EDMA3_RM_Instance::avlblDmaChannels, EDMA3_RM_Instance::avlblPaRAMSets, EDMA3_RM_Instance::avlblQdmaChannels, EDMA3_RM_Instance::avlblTccs, EDMA3_MAX_REGIONS, EDMA3_OS_PROTECT_INTERRUPT, EDMA3_RM_CLOSED, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_E_OBJ_NOT_OPENED, EDMA3_RM_OPENED, EDMA3_RM_SOK, edma3MemSet(), edma3OsProtectEntry(), edma3OsProtectExit(), edma3RegionId, FALSE, EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_Instance::initParam, EDMA3_RM_Param::isMaster, masterExists, NULL, EDMA3_RM_GblConfigParams::numDmaChannels, EDMA3_RM_Obj::numOpens, EDMA3_RM_GblConfigParams::numPaRAMSets, EDMA3_RM_GblConfigParams::numTccs, EDMA3_RM_Obj::phyCtrllerInstId, EDMA3_RM_Instance::pResMgrObjHandle, EDMA3_RM_Instance::shadowRegs, EDMA3_RM_Obj::state, and TRUE.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_RM_Result EDMA3_RM_create (unsigned int  phyCtrllerInstId,
const EDMA3_RM_GblConfigParams *  gblCfgParams,
const void *  miscParam 
)
+
+
+ +

+Create EDMA3 Resource Manager Object. +

+This API is used to create the EDMA3 Resource Manager Object. It should be called only ONCE for each EDMA3 hardware instance.

+Init-time Configuration structure for EDMA3 hardware is provided to pass the SoC specific information. This configuration information could be provided by the user at init-time. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c, in case it is available.

+This API clears the error specific registers (EMCR/EMCRh, QEMCR, CCERRCLR) and sets the TCs priorities and Event Queues' watermark levels, if the 'miscParam' argument is NULL. User can avoid these registers' programming (in some specific use cases) by SETTING the 'isSlave' field of 'EDMA3_RM_MiscParam' configuration structure and passing this structure as the third argument (miscParam).

+After successful completion of this API, Resource Manager Object's state changes to EDMA3_RM_CREATED from EDMA3_RM_DELETED.

+

Parameters:
+ + + + +
phyCtrllerInstId [IN] EDMA3 Controller Instance Id (Hardware instance id, starting from 0).
gblCfgParams [IN] SoC specific configuration structure for the EDMA3 Hardware.
miscParam [IN] Misc configuration options provided in the structure 'EDMA3_RM_MiscParam'. For default options, user can pass NULL in this argument.
+
+
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
+ +

+Used to reset the Internal EDMA3 Resource Manager Data Structures for the first time.

+We are NOT checking 'gblCfgParams' for NULL. If user has passed NULL, default config info will be taken from config file. 'param' is also not being checked because it could be NULL also.

+Check whether user has passed the Global Config Info. If yes, copy it to the driver data structures. Else, use the info from the config file edma3Cfg.c

+Check whether DMA channel to PaRAM Set mapping exists or not. If it does not exist, set the mapping array as 1-to-1 mapped.

+Update the actual number of PaRAM sets.

+Check the misc configuration options structure. Check whether the global registers' initialization is required or not. It is required ONLY if RM is running on the Master Processor. +

References contiguousParamRes, EDMA3_RM_GblConfigParams::dmaChannelPaRAMMap, EDMA3_RM_GblConfigParams::dmaChPaRAMMapExists, EDMA3_MAX_EDMA3_INSTANCES, EDMA3_MAX_LOGICAL_CH, EDMA3_MAX_RM_INSTANCES, EDMA3_MAX_TCC, EDMA3_RM_CREATED, EDMA3_RM_DELETED, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_E_OBJ_NOT_DELETED, EDMA3_RM_SOK, edma3DmaChTccMapping, edma3GlobalRegionInit(), edma3MemCpy(), edma3MemSet(), edma3NumPaRAMSets, edma3QdmaChTccMapping, FALSE, EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_MiscParam::isSlave, NULL, EDMA3_RM_GblConfigParams::numDmaChannels, EDMA3_RM_Obj::numOpens, EDMA3_RM_GblConfigParams::numPaRAMSets, EDMA3_RM_GblConfigParams::numQdmaChannels, EDMA3_RM_ChBoundResources::paRAMId, EDMA3_RM_Obj::phyCtrllerInstId, EDMA3_RM_Obj::state, EDMA3_RM_ChBoundResources::tcc, and TRUE.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + +
EDMA3_RM_Result EDMA3_RM_delete (unsigned int  phyCtrllerInstId,
const void *  param 
)
+
+
+ +

+Delete EDMA3 Resource Manager Object. +

+This API is used to delete the EDMA3 RM Object. It should be called once for each EDMA3 hardware instance, ONLY after closing all the previously opened EDMA3 RM Instances.

+After successful completion of this API, Resource Manager Object's state changes to EDMA3_RM_DELETED.

+

Parameters:
+ + + +
phyCtrllerInstId [IN] EDMA3 Phy Controller Instance Id (Hardware instance id, starting from 0).
param [IN] For possible future use.
+
+
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
+ +

+If number of RM Instances is 0, then state should be EDMA3_RM_CLOSED OR EDMA3_RM_CREATED.

+If number of RM Instances is NOT 0, then this function SHOULD NOT be called by anybody.

+Change state to EDMA3_RM_DELETED +

References allocatedTCCs, EDMA3_MAX_EDMA3_INSTANCES, EDMA3_RM_CLOSED, EDMA3_RM_CREATED, EDMA3_RM_DELETED, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_E_INVALID_STATE, EDMA3_RM_E_OBJ_NOT_CLOSED, EDMA3_RM_SOK, edma3MemSet(), NULL, and EDMA3_RM_Obj::state.

+ +
+

+ +

+
+ + + + + + + + + + + + + + + + + + + + + + + + +
EDMA3_RM_Handle EDMA3_RM_open (unsigned int  phyCtrllerInstId,
const EDMA3_RM_Param *  initParam,
EDMA3_RM_Result *  errorCode 
)
+
+
+ +

+Open EDMA3 Resource Manager Instance. +

+This API is used to open an EDMA3 Resource Manager Instance. It could be called multiple times, for each possible EDMA3 shadow region. Maximum EDMA3_MAX_RM_INSTANCES instances are allowed for each EDMA3 hardware instance.

+Also, only ONE Master Resource Manager Instance is permitted. This master instance (and hence the region to which it belongs) will only receive the EDMA3 interrupts, if enabled.

+User could pass the instance specific configuration structure (initParam->rmInstInitConfig) as a part of the 'initParam' structure, during init-time. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c, in case it is available.

+By default, this Resource Manager instance will clear the PaRAM Sets while allocating them. To change the default behavior, user should use the IOCTL interface appropriately.

+

Parameters:
+ + + + +
phyCtrllerInstId [IN] EDMA3 Controller Instance Id (Hardware instance id, starting from 0).
initParam [IN] Used to Initialize the Resource Manager Instance (Master or Slave).
errorCode [OUT] Error code while opening RM instance.
+
+
Returns:
Handle to the opened Resource Manager instance Or NULL in case of error.
+
Note:
This function disables the global interrupts (by calling API edma3OsProtectEntry with protection level EDMA3_OS_PROTECT_INTERRUPT) while modifying the global RM data structures, to make it re-entrant.
+This API is used to open an EDMA3 Resource Manager Instance. It could be called multiple times, for each possible EDMA3 shadow region. Maximum EDMA3_MAX_RM_INSTANCES instances are allowed for each EDMA3 hardware instance.

+Also, only ONE Master Resource Manager Instance is permitted. This master instance (and hence the region to which it belongs) will only receive the EDMA3 interrupts, if enabled.

+User could pass the instance specific configuration structure (initParam->rmInstInitConfig) as a part of the 'initParam' structure, during init-time. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c, in case it is available.

+

Parameters:
+ + + + +
phyCtrllerInstId [IN] EDMA3 Controller Instance Id (Hardware instance id, starting from 0).
initParam [IN] Used to Initialize the Resource Manager Instance (Master or Slave).
errorCode [OUT] Error code while opening RM instance.
+
+
Returns:
Handle to the opened Resource Manager instance Or NULL in case of error.
+
Note:
This function disables the global interrupts (by calling API edma3OsProtectEntry with protection level EDMA3_OS_PROTECT_INTERRUPT) while modifying the global RM data structures, to make it re-entrant.
+ +

+Check state of RM Object. If no RM instance is opened and this is the first one, then state should be created/closed.

+If num of instances opened is more than 0 and less than max allowed, then state should be opened.

+Check whether user has passed information about resources owned and reserved by this instance. This is region specific information. If he has not passed, dafault static config info will be taken from the config file edma3Cfg.c, according to the regionId specified.

+resMgrIdx specifies the RM instance number created just now. Use it to populate the userInitConfig [].

+By default, PaRAM Sets allocated using this RM Instance will get cleared during their allocation. User can stop their clearing by calling specific IOCTL command.

+By default, during the EDMA3_RM_allocLogicalChannel (), global EDMA3 registers (DCHMAP/QCHMAP) and the allocated PaRAM Set will be programmed accordingly, for users using this RM Instance. User can stop their pre-programming by calling EDMA3_RM_IOCTL_SET_GBL_REG_MODIFY_OPTION IOCTL command. +

References EDMA3_RM_Instance::avlblDmaChannels, EDMA3_RM_Instance::avlblPaRAMSets, EDMA3_RM_Instance::avlblQdmaChannels, EDMA3_RM_Instance::avlblTccs, EDMA3_RM_GblConfigParams::dmaChannelPaRAMMap, EDMA3_RM_GblConfigParams::dmaChPaRAMMapExists, EDMA3_MAX_EDMA3_INSTANCES, EDMA3_MAX_RM_INSTANCES, EDMA3_OS_PROTECT_INTERRUPT, EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CLOSED, EDMA3_RM_CREATED, EDMA3_RM_E_INVALID_PARAM, EDMA3_RM_E_INVALID_STATE, EDMA3_RM_E_MAX_RM_INST_OPENED, EDMA3_RM_E_RM_MASTER_ALREADY_EXISTS, EDMA3_RM_OPENED, EDMA3_RM_SOK, edma3MemCpy(), edma3MemSet(), edma3OsProtectEntry(), edma3OsProtectExit(), edma3RegionId, edma3ShadowRegionInit(), EDMA3_RM_Obj::gblCfgParams, EDMA3_RM_GblConfigParams::globalRegs, EDMA3_RM_Instance::initParam, EDMA3_RM_Param::isMaster, masterExists, NULL, EDMA3_RM_GblConfigParams::numDmaChannels, EDMA3_RM_Obj::numOpens, EDMA3_RM_GblConfigParams::numPaRAMSets, EDMA3_RM_GblConfigParams::numRegions, EDMA3_RM_GblConfigParams::numTccs, EDMA3_RM_InstanceInitConfig::ownDmaChannels, EDMA3_RM_InstanceInitConfig::ownPaRAMSets, EDMA3_RM_InstanceInitConfig::ownQdmaChannels, EDMA3_RM_InstanceInitConfig::ownTccs, EDMA3_RM_Instance::paramInitRequired, EDMA3_RM_Instance::pResMgrObjHandle, EDMA3_RM_Param::regionId, EDMA3_RM_Param::regionInitEnable, EDMA3_RM_Instance::regModificationRequired, EDMA3_RM_InstanceInitConfig::resvdPaRAMSets, EDMA3_RM_Param::rmInstInitConfig, EDMA3_RM_Param::rmSemHandle, EDMA3_RM_Instance::shadowRegs, EDMA3_RM_Obj::state, and TRUE.

+ +
+

+

+
Generated on Thu Oct 16 16:22:39 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/group__edma3rmstatus.html b/packages/ti/sdo/edma3/rm/docs/html/group__edma3rmstatus.html new file mode 100644 index 0000000..89c1681 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/group__edma3rmstatus.html @@ -0,0 +1,145 @@ + + +EDMA3 Resource Manager: Completion status + + + + + +
+

Completion status
+ +[Instance Wide Interface] +

+ + + + + + + + + + + + + + + + +

Data Structures

struct  EDMA3_RM_GblErrCallbackParams
 Global Error Callback parameters. More...

Typedefs

typedef void(* EDMA3_RM_GblErrCallback )(EDMA3_RM_GlobalError deviceStatus, unsigned int instanceId, void *gblerrData)
 Global Error callback - caters to module events like bus error etc which are not channel specific. Runs in ISR context.

Enumerations

enum  EDMA3_RM_TccStatus {
+  EDMA3_RM_XFER_COMPLETE = 1, +
+  EDMA3_RM_E_CC_DMA_EVT_MISS = 2, +
+  EDMA3_RM_E_CC_QDMA_EVT_MISS = 3 +
+ }
 This enum defines the channel specific status codes of an EDMA3 transfer. It is returned while calling the channel specific callback function to tell the status. More...
enum  EDMA3_RM_GlobalError {
+  EDMA3_RM_E_CC_QUE_THRES_EXCEED = 1, +
+  EDMA3_RM_E_CC_TCC = 2, +
+  EDMA3_RM_E_TC_MEM_LOCATION_READ_ERROR = 3, +
+  EDMA3_RM_E_TC_MEM_LOCATION_WRITE_ERROR = 4, +
+  EDMA3_RM_E_TC_INVALID_ADDR = 5, +
+  EDMA3_RM_E_TC_TR_ERROR = 6 +
+ }
 This enum defines the global (not specific to any channel) error codes of completion of an EDMA3 transfer. More...
+

Detailed Description

+This group defines the error codes of completion of an EDMA3 transfer.

Typedef Documentation

+ +
+
+ + + + +
typedef void(* EDMA3_RM_GblErrCallback)(EDMA3_RM_GlobalError deviceStatus, unsigned int instanceId, void *gblerrData)
+
+
+ +

+Global Error callback - caters to module events like bus error etc which are not channel specific. Runs in ISR context. +

+gblerrData is application provided data when open'ing the Resource Manager. +

+

+

Enumeration Type Documentation

+ +
+
+ + + + +
enum EDMA3_RM_GlobalError
+
+
+ +

+This enum defines the global (not specific to any channel) error codes of completion of an EDMA3 transfer. +

+

Enumerator:
+ + + + + + + +
EDMA3_RM_E_CC_QUE_THRES_EXCEED  +Threshold exceed:- for all event queues. These get latched in EDMA3CC error register (CCERR). This error has a direct relation with the setting of EDMA3_RM_GblConfigParams.evtQueueWaterMarkLvl
EDMA3_RM_E_CC_TCC  +TCC error:- for outstanding transfer requests expected to return completion code (TCCHEN or TCINTEN bit in OPT is set to 1) exceeding the maximum limit of 63. This also gets latched in the CCERR.
EDMA3_RM_E_TC_MEM_LOCATION_READ_ERROR  +Transfer Controller has reported an error Detection of a Read error signaled by the source or destination address
EDMA3_RM_E_TC_MEM_LOCATION_WRITE_ERROR  +Detection of a Write error signaled by the source or destination address
EDMA3_RM_E_TC_INVALID_ADDR  +Attempt to read or write to an invalid address in the configuration memory map.
EDMA3_RM_E_TC_TR_ERROR  +Detection of a FIFO mode TR violating the FIFO mode transfer rules (the source/destination addresses and source/destination indexes must be aligned to 32 bytes).
+
+ +
+

+ +

+
+ + + + +
enum EDMA3_RM_TccStatus
+
+
+ +

+This enum defines the channel specific status codes of an EDMA3 transfer. It is returned while calling the channel specific callback function to tell the status. +

+

Enumerator:
+ + + + +
EDMA3_RM_XFER_COMPLETE  +DMA Transfer successfully completed (true completion mode) or submitted to the TC (early completion mode).
EDMA3_RM_E_CC_DMA_EVT_MISS  +Channel Controller has reported an error DMA missed events:- for all 64 DMA channels. These get latched in the event missed registers (EMR/EMRH).
EDMA3_RM_E_CC_QDMA_EVT_MISS  +QDMA missed events:- for all QDMA channels. These get latched in the QDMA event missed register (QEMR).
+
+ +
+

+

+
Generated on Thu Oct 16 16:22:39 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/group__edma3rmusage.html b/packages/ti/sdo/edma3/rm/docs/html/group__edma3rmusage.html new file mode 100644 index 0000000..8569222 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/group__edma3rmusage.html @@ -0,0 +1,30 @@ + + +EDMA3 Resource Manager: EDMA3 Resource Manager Usage Guidelines + + + + + +
+

EDMA3 Resource Manager Usage Guidelines
+ +[Interface Definition for EDMA3 Resource Manager Layer] +

+ +
+Guidelines for typical usage of EDMA3 Resource Manager.
+
Generated on Thu Oct 16 16:22:39 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/index.hhc b/packages/ti/sdo/edma3/rm/docs/html/index.hhc new file mode 100644 index 0000000..0ed23f1 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/index.hhc @@ -0,0 +1,80 @@ + + + + + +
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+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/index.hhp b/packages/ti/sdo/edma3/rm/docs/html/index.hhp new file mode 100644 index 0000000..37a9b19 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/index.hhp @@ -0,0 +1,85 @@ +[OPTIONS] +Compiled file=..\EDMA3_Resource_Manager.chm +Compatibility=1.1 +Full-text search=Yes +Contents file=index.hhc +Default Window=main +Default topic=index.html +Index file=index.hhk +Language=0x409 English (United States) +Title=EDMA3 Resource Manager + +[WINDOWS] +main="EDMA3 Resource Manager","index.hhc","index.hhk","index.html","index.html",,,,,0x23520,,0x10387e,,,,,,,,0 + +[FILES] +index.html +edma3__common_8h-source.html +edma3__log_8h-source.html +edma3__rl__cc_8h-source.html +edma3__rl__tc_8h-source.html +edma3__rm_8h-source.html +edma3resmgr_8h-source.html +edma3__common_8h.html +edma3__da830__cfg_8c.html +edma3__log_8h.html +edma3__rl__cc_8h.html +edma3__rl__tc_8h.html +edma3__rm_8h.html +edma3__rm__gbl__data_8c.html +edma3resmgr_8c.html +edma3resmgr_8h.html +group__Edma3RMIntrMgrMain.html +group__Edma3RMIntrMgrInst.html +group__Edma3RMStatus.html +group__Edma3RMIntrMgrChannel.html +group__Edma3ResType.html +group__Edma3RMMain.html +group__Edma3RMUsage.html +group__Edma3RMErrCode.html +group__Edma3ResMgr.html +group__EDMA3.html +group__Edma3ResMgrInt.html +group__Edma3ResMgrIntObjMaint.html +group__Edma3RMIntBoundVals.html +modules.html +annotated.html +classes.html +functions.html +functions_vars.html +structEDMA3__RM__ChBoundResources.html +structEDMA3__RM__GblConfigParams.html +structEDMA3__RM__GblErrCallbackParams.html +structEDMA3__RM__Instance.html +structEDMA3__RM__InstanceInitConfig.html +structEDMA3__RM__MiscParam.html +structEDMA3__RM__Obj.html +structEDMA3__RM__Param.html +structEDMA3__RM__ParamentryRegs.html +structEDMA3__RM__PaRAMRegs.html +structEDMA3__RM__ResDesc.html +structEDMA3__RM__TccCallbackParams.html +files.html +globals.html +globals_0x63.html +globals_0x64.html +globals_0x65.html +globals_0x66.html +globals_0x67.html +globals_0x6c.html +globals_0x6d.html +globals_0x6e.html +globals_0x72.html +globals_0x74.html +globals_0x75.html +globals_0x78.html +globals_func.html +globals_vars.html +globals_type.html +globals_enum.html +globals_eval.html +globals_defs.html +tabs.css +tab_b.gif +tab_l.gif +tab_r.gif diff --git a/packages/ti/sdo/edma3/rm/docs/html/index.html b/packages/ti/sdo/edma3/rm/docs/html/index.html new file mode 100644 index 0000000..4310386 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/index.html @@ -0,0 +1,26 @@ + + +EDMA3 Resource Manager: Main Page + + + + + +
+

EDMA3 Resource Manager Documentation

+

+

+
Generated on Thu Oct 16 16:21:26 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/modules.html b/packages/ti/sdo/edma3/rm/docs/html/modules.html new file mode 100644 index 0000000..d2053a2 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/modules.html @@ -0,0 +1,51 @@ + + +EDMA3 Resource Manager: Module Index + + + + + +
+

Modules

Here is a list of all modules: +
+
Generated on Thu Oct 16 16:22:42 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__chboundresources.html b/packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__chboundresources.html new file mode 100644 index 0000000..868b490 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__chboundresources.html @@ -0,0 +1,87 @@ + + +EDMA3 Resource Manager: EDMA3_RM_ChBoundResources Struct Reference + + + + + +
+

EDMA3_RM_ChBoundResources Struct Reference
+ +[Internal Interface Definition for Resource Manager] +

EDMA3 Channel-Bound resources. +More... +

+#include <edma3resmgr.h> +

+ + + + + + + +

Data Fields

int paRAMId
unsigned int tcc
+

Detailed Description

+EDMA3 Channel-Bound resources. +

+Used to maintain information of the EDMA3 resources (specifically Parameter RAM set and TCC), bound to the particular channel within EDMA3_RM_allocLogicalChannel ().

Field Documentation

+ +
+
+ + + + +
int EDMA3_RM_ChBoundResources::paRAMId
+
+
+ +

+PaRAM Set number associated with the particular channel +

Referenced by EDMA3_RM_allocLogicalChannel(), EDMA3_RM_create(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_getPaRAM(), EDMA3_RM_getPaRAMPhyAddr(), and EDMA3_RM_setPaRAM().

+ +
+

+ +

+
+ + + + +
unsigned int EDMA3_RM_ChBoundResources::tcc
+
+
+ +

+TCC associated with the particular channel +

Referenced by EDMA3_RM_allocLogicalChannel(), EDMA3_RM_create(), and EDMA3_RM_freeLogicalChannel().

+ +
+

+

The documentation for this struct was generated from the following file: +
+
Generated on Thu Oct 16 16:22:42 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__gblconfigparams.html b/packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__gblconfigparams.html new file mode 100644 index 0000000..0180c23 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__gblconfigparams.html @@ -0,0 +1,435 @@ + + +EDMA3 Resource Manager: EDMA3_RM_GblConfigParams Struct Reference + + + + + +
+

EDMA3_RM_GblConfigParams Struct Reference
+ +[Interface Definition for EDMA3 Resource Manager Layer] +

Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. +More... +

+#include <edma3_rm.h> +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Data Fields

unsigned int numDmaChannels
unsigned int numQdmaChannels
unsigned int numTccs
unsigned int numPaRAMSets
unsigned int numEvtQueue
unsigned int numTcs
unsigned int numRegions
unsigned short dmaChPaRAMMapExists
 Channel mapping existence.
unsigned short memProtectionExists
void * globalRegs
void * tcRegs [EDMA3_MAX_TC]
unsigned int xferCompleteInt
unsigned int ccError
unsigned int tcError [EDMA3_MAX_TC]
unsigned int evtQPri [EDMA3_MAX_EVT_QUE]
 EDMA3 TC priority setting.
unsigned int evtQueueWaterMarkLvl [EDMA3_MAX_EVT_QUE]
 Event Queues Watermark Levels.
unsigned int tcDefaultBurstSize [EDMA3_MAX_TC]
 Default Burst Size (DBS) of TCs.
unsigned int dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH]
 Mapping from DMA channels to PaRAM Sets.
unsigned int dmaChannelTccMap [EDMA3_MAX_DMA_CH]
 Mapping from DMA channels to TCCs.
unsigned int dmaChannelHwEvtMap [EDMA3_MAX_DMA_CHAN_DWRDS]
 Mapping from DMA channels to Hardware Events.
+

Detailed Description

+Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. +

+This configuration structure is used to specify the EDMA3 Resource Manager global settings, specific to the SoC. For e.g. number of DMA/QDMA channels, number of PaRAM sets, TCCs, event queues, transfer controllers, base addresses of CC global registers and TC registers, interrupt number for EDMA3 transfer completion, CC error, event queues' priority, watermark threshold level etc. This configuration information is SoC specific and could be provided by the user at run-time while creating the EDMA3 RM Object, using API EDMA3_RM_create. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c, in case it is available.

Field Documentation

+ +
+
+ + + + +
unsigned int EDMA3_RM_GblConfigParams::numDmaChannels
+
+
+ +

+Number of DMA Channels supported by the underlying EDMA3 Controller. +

Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_close(), EDMA3_RM_create(), EDMA3_RM_freeContiguousResource(), EDMA3_RM_mapEdmaChannel(), EDMA3_RM_open(), EDMA3_RM_registerTccCb(), and EDMA3_RM_unregisterTccCb().

+ +
+

+ +

+
+ + + + +
unsigned int EDMA3_RM_GblConfigParams::numQdmaChannels
+
+
+ +

+Number of QDMA Channels supported by the underlying EDMA3 Controller +

Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_create(), EDMA3_RM_freeContiguousResource(), EDMA3_RM_mapQdmaChannel(), EDMA3_RM_registerTccCb(), and EDMA3_RM_unregisterTccCb().

+ +
+

+ +

+
+ + + + +
unsigned int EDMA3_RM_GblConfigParams::numTccs
+
+
+ +

+Number of Interrupt Channels supported by the underlying EDMA3 Controller +

Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_checkAndClearTcc(), EDMA3_RM_close(), EDMA3_RM_freeContiguousResource(), EDMA3_RM_open(), EDMA3_RM_registerTccCb(), and EDMA3_RM_waitAndClearTcc().

+ +
+

+ +

+
+ + + + +
unsigned int EDMA3_RM_GblConfigParams::numPaRAMSets
+
+
+ +

+Number of PaRAM Sets supported by the underlying EDMA3 Controller +

Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_close(), EDMA3_RM_create(), EDMA3_RM_freeContiguousResource(), EDMA3_RM_mapEdmaChannel(), EDMA3_RM_mapQdmaChannel(), and EDMA3_RM_open().

+ +
+

+ +

+
+ + + + +
unsigned int EDMA3_RM_GblConfigParams::numEvtQueue
+
+
+ +

+Number of Event Queues in the underlying EDMA3 Controller +

Referenced by edma3CCErrHandler().

+ +
+

+ +

+
+ + + + +
unsigned int EDMA3_RM_GblConfigParams::numTcs
+
+
+ +

+Number of Transfer Controllers (TCs) in the underlying EDMA3 Controller +

Referenced by EDMA3_RM_getBaseAddress().

+ +
+

+ +

+
+ + + + +
unsigned int EDMA3_RM_GblConfigParams::numRegions
+
+
+ +

+Number of Regions in the underlying EDMA3 Controller +

Referenced by EDMA3_RM_open().

+ +
+

+ +

+
+ + + + +
unsigned short EDMA3_RM_GblConfigParams::dmaChPaRAMMapExists
+
+
+ +

+Channel mapping existence. +

+A value of 0 (No channel mapping) implies that there is fixed association between a DMA channel and a PaRAM Set or, in other words, DMA channel n can ONLY use PaRAM Set n (No availability of DCHMAP registers) for transfers to happen.

+A value of 1 implies the presence of DCHMAP registers for the DMA channels and hence the flexibility of associating any DMA channel to any PaRAM Set. In other words, ANY PaRAM Set can be used for ANY DMA channel (like QDMA Channels). +

Referenced by EDMA3_RM_allocLogicalChannel(), EDMA3_RM_create(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_mapEdmaChannel(), and EDMA3_RM_open().

+ +
+

+ +

+
+ + + + +
unsigned short EDMA3_RM_GblConfigParams::memProtectionExists
+
+
+ +

+Existence of memory protection feature +

+

+ +

+
+ + + + +
void* EDMA3_RM_GblConfigParams::globalRegs
+
+
+ +

+Base address of EDMA3 CC memory mapped registers. +

Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocLogicalChannel(), EDMA3_RM_allocResource(), EDMA3_RM_checkAndClearTcc(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_freeResource(), EDMA3_RM_getBaseAddress(), EDMA3_RM_getCCRegister(), EDMA3_RM_getPaRAM(), EDMA3_RM_getPaRAMPhyAddr(), EDMA3_RM_mapEdmaChannel(), EDMA3_RM_mapQdmaChannel(), EDMA3_RM_open(), EDMA3_RM_setCCRegister(), EDMA3_RM_setPaRAM(), EDMA3_RM_waitAndClearTcc(), edma3CCErrHandler(), edma3ComplHandler(), and gblChngAllocContigRes().

+ +
+

+ +

+
+ + + + +
void* EDMA3_RM_GblConfigParams::tcRegs[EDMA3_MAX_TC]
+
+
+ +

+Base address of EDMA3 TCs memory mapped registers. +

Referenced by EDMA3_RM_getBaseAddress(), and edma3TCErrHandler().

+ +
+

+ +

+
+ + + + +
unsigned int EDMA3_RM_GblConfigParams::xferCompleteInt
+
+
+ +

+EDMA3 transfer completion interrupt line (could be different for ARM and DSP) +

+

+ +

+
+ + + + +
unsigned int EDMA3_RM_GblConfigParams::ccError
+
+
+ +

+EDMA3 CC error interrupt line (could be different for ARM and DSP) +

+

+ +

+
+ + + + +
unsigned int EDMA3_RM_GblConfigParams::tcError[EDMA3_MAX_TC]
+
+
+ +

+EDMA3 TCs error interrupt line (could be different for ARM and DSP) +

+

+ +

+
+ + + + +
unsigned int EDMA3_RM_GblConfigParams::evtQPri[EDMA3_MAX_EVT_QUE]
+
+
+ +

+EDMA3 TC priority setting. +

+User can program the priority of the Event Queues at a system-wide level. This means that the user can set the priority of an IO initiated by either of the TCs (Transfer Controllers) relative to IO initiated by the other bus masters on the device (ARM, DSP, USB, etc) +

+

+ +

+
+ + + + +
unsigned int EDMA3_RM_GblConfigParams::evtQueueWaterMarkLvl[EDMA3_MAX_EVT_QUE]
+
+
+ +

+Event Queues Watermark Levels. +

+To Configure the Threshold level of number of events that can be queued up in the Event queues. EDMA3CC error register (CCERR) will indicate whether or not at any instant of time the number of events queued up in any of the event queues exceeds or equals the threshold/watermark value that is set in the queue watermark threshold register (QWMTHRA). +

+

+ +

+
+ + + + +
unsigned int EDMA3_RM_GblConfigParams::tcDefaultBurstSize[EDMA3_MAX_TC]
+
+
+ +

+Default Burst Size (DBS) of TCs. +

+An optimally-sized command is defined by the transfer controller default burst size (DBS). Different TCs can have different DBS values. It is defined in Bytes. +

+

+ +

+
+ + + + +
unsigned int EDMA3_RM_GblConfigParams::dmaChannelPaRAMMap[EDMA3_MAX_DMA_CH]
+
+
+ +

+Mapping from DMA channels to PaRAM Sets. +

+If channel mapping exists (DCHMAP registers are present), this array stores the respective PaRAM Set for each DMA channel. User can initialize each array member with a specific PaRAM Set or with EDMA3_DRV_CH_NO_PARAM_MAP. If channel mapping doesn't exist, it is of no use as the EDMA3 RM automatically uses the right PaRAM Set for that DMA channel. Useful only if mapping exists, otherwise of no use. +

Referenced by EDMA3_RM_allocLogicalChannel(), EDMA3_RM_create(), and EDMA3_RM_open().

+ +
+

+ +

+
+ + + + +
unsigned int EDMA3_RM_GblConfigParams::dmaChannelTccMap[EDMA3_MAX_DMA_CH]
+
+
+ +

+Mapping from DMA channels to TCCs. +

+This array stores the respective TCC (interrupt channel) for each DMA channel. User can initialize each array member with a specific TCC or with EDMA3_DRV_CH_NO_TCC_MAP. This specific TCC code will be returned when the transfer is completed on the mapped DMA channel. +

Referenced by EDMA3_RM_allocLogicalChannel().

+ +
+

+ +

+
+ + + + +
unsigned int EDMA3_RM_GblConfigParams::dmaChannelHwEvtMap[EDMA3_MAX_DMA_CHAN_DWRDS]
+
+
+ +

+Mapping from DMA channels to Hardware Events. +

+Each bit in this array corresponds to one DMA channel and tells whether this DMA channel is tied to any peripheral. That is whether any peripheral can send the synch event on this DMA channel or not. 1 means the channel is tied to some peripheral; 0 means it is not. DMA channels which are tied to some peripheral are RESERVED for that peripheral only. They are not allocated when user asks for 'ANY' DMA channel. All channels need not be mapped, some can be free also. +

+

+

The documentation for this struct was generated from the following file: +
+
Generated on Thu Oct 16 16:22:42 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__gblerrcallbackparams.html b/packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__gblerrcallbackparams.html new file mode 100644 index 0000000..663ad56 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__gblerrcallbackparams.html @@ -0,0 +1,87 @@ + + +EDMA3 Resource Manager: EDMA3_RM_GblErrCallbackParams Struct Reference + + + + + +
+

EDMA3_RM_GblErrCallbackParams Struct Reference
+ +[Completion status] +

Global Error Callback parameters. +More... +

+#include <edma3_rm.h> +

+ + + + + + + +

Data Fields

EDMA3_RM_GblErrCallback gblerrCb
void * gblerrData
+

Detailed Description

+Global Error Callback parameters. +

+Consists of the Callback function and the data to be passed to it.

Field Documentation

+ +
+
+ + + + +
EDMA3_RM_GblErrCallback EDMA3_RM_GblErrCallbackParams::gblerrCb
+
+
+ +

+Instance wide callback function to catch non-channel specific errors. +

Referenced by edma3CCErrHandler(), and edma3TCErrHandler().

+ +
+

+ +

+
+ + + + +
void* EDMA3_RM_GblErrCallbackParams::gblerrData
+
+
+ +

+Application data to be passed back to the Global Error callback +

Referenced by edma3CCErrHandler(), and edma3TCErrHandler().

+ +
+

+

The documentation for this struct was generated from the following file: +
+
Generated on Thu Oct 16 16:22:42 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__instance.html b/packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__instance.html new file mode 100644 index 0000000..27fa1cb --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__instance.html @@ -0,0 +1,225 @@ + + +EDMA3 Resource Manager: EDMA3_RM_Instance Struct Reference + + + + + +
+

EDMA3_RM_Instance Struct Reference
+ +[Object Maintenance] +

EDMA3 RM Instance Specific Configuration Structure. +More... +

+#include <edma3resmgr.h> +

+ + + + + + + + + + + + + + + + + + + + + +

Data Fields

EDMA3_RM_Param initParam
EDMA3_CCRL_ShadowRegs * shadowRegs
EDMA3_RM_Obj * pResMgrObjHandle
unsigned int avlblDmaChannels [EDMA3_MAX_DMA_CHAN_DWRDS]
unsigned int avlblQdmaChannels [EDMA3_MAX_QDMA_CHAN_DWRDS]
unsigned int avlblPaRAMSets [EDMA3_MAX_PARAM_DWRDS]
unsigned int avlblTccs [EDMA3_MAX_TCC_DWRDS]
unsigned int paramInitRequired
unsigned int regModificationRequired
+

Detailed Description

+EDMA3 RM Instance Specific Configuration Structure. +

+Used to maintain information of the EDMA3 Res Mgr instances. One such storage exists for each instance of the EDMA3 Res Mgr.

+Maximum EDMA3_MAX_RM_INSTANCES instances are allowed for each EDMA3 hardware instance, for same or different shadow regions.

Field Documentation

+ +
+
+ + + + +
EDMA3_RM_Param EDMA3_RM_Instance::initParam
+
+
+ +

+Configuration such as region id, IsMaster, Callback function This configuration is passed to the "Open" API. For a single EDMA3 HW controller, there can be EDMA3_MAX_REGIONS different instances tied to different regions. +

Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_checkAndClearTcc(), EDMA3_RM_close(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_freeResource(), EDMA3_RM_mapEdmaChannel(), EDMA3_RM_mapQdmaChannel(), EDMA3_RM_open(), EDMA3_RM_setCCRegister(), EDMA3_RM_waitAndClearTcc(), edma3CCErrHandler(), edma3ShadowRegionInit(), edma3TCErrHandler(), and gblChngAllocContigRes().

+ +
+

+ +

+
+ + + + +
EDMA3_CCRL_ShadowRegs* EDMA3_RM_Instance::shadowRegs
+
+
+ +

+Pointer to appropriate Shadow Register region of CC Registers +

Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocLogicalChannel(), EDMA3_RM_allocResource(), EDMA3_RM_close(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_open(), EDMA3_RM_registerTccCb(), and EDMA3_RM_unregisterTccCb().

+ +
+

+ +

+
+ + + + +
EDMA3_RM_Obj* EDMA3_RM_Instance::pResMgrObjHandle
+
+
+ +

+Pointer to the EDMA3 RM Object (HW specific) opened by RM instance. +

Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocLogicalChannel(), EDMA3_RM_allocResource(), EDMA3_RM_checkAndClearTcc(), EDMA3_RM_close(), EDMA3_RM_freeContiguousResource(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_freeResource(), EDMA3_RM_getBaseAddress(), EDMA3_RM_getCCRegister(), EDMA3_RM_getInstanceInitCfg(), EDMA3_RM_getPaRAM(), EDMA3_RM_getPaRAMPhyAddr(), EDMA3_RM_mapEdmaChannel(), EDMA3_RM_mapQdmaChannel(), EDMA3_RM_open(), EDMA3_RM_registerTccCb(), EDMA3_RM_setCCRegister(), EDMA3_RM_setPaRAM(), EDMA3_RM_unregisterTccCb(), EDMA3_RM_waitAndClearTcc(), edma3ShadowRegionInit(), and gblChngAllocContigRes().

+ +
+

+ +

+
+ + + + +
unsigned int EDMA3_RM_Instance::avlblDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS]
+
+
+ +

+Available DMA Channels to the RM Instance +

Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_close(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_freeResource(), EDMA3_RM_mapEdmaChannel(), EDMA3_RM_open(), and gblChngAllocContigRes().

+ +
+

+ +

+
+ + + + +
unsigned int EDMA3_RM_Instance::avlblQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS]
+
+
+ +

+Available QDMA Channels to the RM Instance +

Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_close(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_freeResource(), EDMA3_RM_mapQdmaChannel(), EDMA3_RM_open(), and gblChngAllocContigRes().

+ +
+

+ +

+
+ + + + +
unsigned int EDMA3_RM_Instance::avlblPaRAMSets[EDMA3_MAX_PARAM_DWRDS]
+
+
+ +

+Available PaRAM Sets to the RM Instance +

Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_close(), EDMA3_RM_freeResource(), EDMA3_RM_mapEdmaChannel(), EDMA3_RM_mapQdmaChannel(), EDMA3_RM_open(), and gblChngAllocContigRes().

+ +
+

+ +

+
+ + + + +
unsigned int EDMA3_RM_Instance::avlblTccs[EDMA3_MAX_TCC_DWRDS]
+
+
+ +

+Available TCCs to the RM Instance +

Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_close(), EDMA3_RM_freeResource(), EDMA3_RM_open(), and gblChngAllocContigRes().

+ +
+

+ +

+
+ + + + +
unsigned int EDMA3_RM_Instance::paramInitRequired
+
+
+ +

+Sometimes, PaRAM clearing is not required for some particular RM Instances. In that case, PaRAM Sets allocated will NOT be cleared before allocating to any particular user. It is the responsibility of user to program it accordingly, without assuming anything for a specific field because the PaRAM Set might contain junk values. Not programming it fully might result in erroneous behavior. On the other hand, RM instances can also use this variable to get the PaRAM Sets cleared before allocating them to the specific user. User can program only the selected fields in this case.

+Value '0' : PaRAM Sets will NOT be cleared during their allocation. Value '1' : PaRAM Sets will be cleared during their allocation.

+This value can be modified using the IOCTL commands. +

Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_Ioctl(), EDMA3_RM_open(), and gblChngAllocContigRes().

+ +
+

+ +

+
+ + + + +
unsigned int EDMA3_RM_Instance::regModificationRequired
+
+
+ +

+Sometimes, global EDMA3 registers (DCHMAP/QCHMAP) and PaRAM Sets should not be modified during EDMA3_RM_allocLogicalChannel (), for some particular RM Instances. In that case, it is the responsibility of user to program them accordingly, when needed, without assuming anything because they might contain junk values. Not programming the registers/PaRAMs fully might result in erroneous behavior. On the other hand, RM instances can also use this variable to get the global registers and PaRAM Sets minimally programmed before allocating them to the specific user. User can program only the remaining fields in this case.

+Value '0' : EDMA3 registers (DCHMAP/QCHMAP) and PaRAM Sets will NOT be programmed during their allocation. Value '1' : EDMA3 registers (DCHMAP/QCHMAP) and PaRAM Sets will be programmed during their allocation.

+This value can be modified using the IOCTL commands. +

Referenced by EDMA3_RM_allocLogicalChannel(), EDMA3_RM_allocResource(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_freeResource(), EDMA3_RM_Ioctl(), and EDMA3_RM_open().

+ +
+

+

The documentation for this struct was generated from the following file: +
+
Generated on Thu Oct 16 16:22:42 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__instanceinitconfig.html b/packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__instanceinitconfig.html new file mode 100644 index 0000000..fa555a9 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__instanceinitconfig.html @@ -0,0 +1,224 @@ + + +EDMA3 Resource Manager: EDMA3_RM_InstanceInitConfig Struct Reference + + + + + +
+

EDMA3_RM_InstanceInitConfig Struct Reference
+ +[Interface Definition for EDMA3 Resource Manager Layer] +

Init-time Region Specific Configuration structure for EDMA3 RM, to provide region specific Information. +More... +

+#include <edma3_rm.h> +

+ + + + + + + + + + + + + + + + + + + + + + + +

Data Fields

unsigned int ownPaRAMSets [EDMA3_MAX_PARAM_DWRDS]
unsigned int ownDmaChannels [EDMA3_MAX_DMA_CHAN_DWRDS]
unsigned int ownQdmaChannels [EDMA3_MAX_QDMA_CHAN_DWRDS]
unsigned int ownTccs [EDMA3_MAX_TCC_DWRDS]
unsigned int resvdPaRAMSets [EDMA3_MAX_PARAM_DWRDS]
 Reserved PaRAM Sets.
unsigned int resvdDmaChannels [EDMA3_MAX_DMA_CHAN_DWRDS]
 Reserved DMA channels.
unsigned int resvdQdmaChannels [EDMA3_MAX_QDMA_CHAN_DWRDS]
 Reserved QDMA channels.
unsigned int resvdTccs [EDMA3_MAX_TCC_DWRDS]
 Reserved TCCs.
+

Detailed Description

+Init-time Region Specific Configuration structure for EDMA3 RM, to provide region specific Information. +

+This configuration structure is used to specify which EDMA3 resources are owned and reserved by the EDMA3 RM instance. This configuration structure is shadow region specific and will be provided by the user at run-time while calling EDMA3_RM_open ().

+Owned resources: ****************

+EDMA3 RM Instances are tied to different shadow regions and hence different masters. Regions could be:

+a) ARM, b) DSP, c) IMCOP (Imaging Co-processor) etc.

+User can assign each EDMA3 resource to a shadow region using this structure. In this way, user specifies which resources are owned by the specific EDMA3 RM Instance. This assignment should also ensure that the same resource is not assigned to more than one shadow regions (unless desired in that way). Any assignment not following the above mentioned approach may have catastrophic consequences.

+Reserved resources: *******************

+During EDMA3 RM initialization, user can reserve some of the EDMA3 resources for future use, by specifying which resources to reserve in the configuration data structure. These (critical) resources are reserved in advance so that they should not be allocated to someone else and thus could be used in future for some specific purpose.

+User can request different EDMA3 resources using two methods: a) By passing the resource type and the actual resource id, b) By passing the resource type and ANY as resource id

+For e.g. to request DMA channel 31, user will pass 31 as the resource id. But to request ANY available DMA channel (mainly used for memory-to-memory data transfer operations), user will pass EDMA3_DRV_DMA_CHANNEL_ANY as the resource id.

+During initialization, user may have reserved some of the DMA channels for some specific purpose (mainly for peripherals using EDMA). These reserved DMA channels then will not be returned when user requests ANY as the resource id.

+Same logic applies for QDMA channels and TCCs.

+For PaRAM Set, there is one difference. If the DMA channels are one-to-one tied to their respective PaRAM Sets (i.e. user cannot 'choose' the PaRAM Set for a particular DMA channel), EDMA3 RM automatically reserves all those PaRAM Sets which are tied to the DMA channels. Then those PaRAM Sets would not be returned when user requests for ANY PaRAM Set (specifically for linking purpose). This is done in order to avoid allocating the PaRAM Set, tied to a particular DMA channel, for linking purpose. If this constraint is not there, that DMA channel thus could not be used at all, because of the unavailability of the desired PaRAM Set.

Field Documentation

+ +
+
+ + + + +
unsigned int EDMA3_RM_InstanceInitConfig::ownPaRAMSets[EDMA3_MAX_PARAM_DWRDS]
+
+
+ +

+PaRAM Sets owned by the EDMA3 RM Instance. +

Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_freeResource(), EDMA3_RM_mapEdmaChannel(), EDMA3_RM_mapQdmaChannel(), and EDMA3_RM_open().

+ +
+

+ +

+
+ + + + +
unsigned int EDMA3_RM_InstanceInitConfig::ownDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS]
+
+
+ +

+DMA Channels owned by the EDMA3 RM Instance. +

Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_freeResource(), EDMA3_RM_mapEdmaChannel(), EDMA3_RM_open(), edma3CCErrHandler(), and edma3ShadowRegionInit().

+ +
+

+ +

+
+ + + + +
unsigned int EDMA3_RM_InstanceInitConfig::ownQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS]
+
+
+ +

+QDMA Channels owned by the EDMA3 RM Instance. +

Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_freeResource(), EDMA3_RM_mapQdmaChannel(), EDMA3_RM_open(), edma3CCErrHandler(), and edma3ShadowRegionInit().

+ +
+

+ +

+
+ + + + +
unsigned int EDMA3_RM_InstanceInitConfig::ownTccs[EDMA3_MAX_TCC_DWRDS]
+
+
+ +

+TCCs owned by the EDMA3 RM Instance. +

Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_freeResource(), EDMA3_RM_open(), and edma3ShadowRegionInit().

+ +
+

+ +

+
+ + + + +
unsigned int EDMA3_RM_InstanceInitConfig::resvdPaRAMSets[EDMA3_MAX_PARAM_DWRDS]
+
+
+ +

+Reserved PaRAM Sets. +

+PaRAM Sets reserved during initialization for future use. These will not be given when user requests for ANY available PaRAM Set using 'EDMA3_RM_PARAM_ANY' as resource/channel id. +

Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), and EDMA3_RM_open().

+ +
+

+ +

+
+ + + + +
unsigned int EDMA3_RM_InstanceInitConfig::resvdDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS]
+
+
+ +

+Reserved DMA channels. +

+DMA channels reserved during initialization for future use. These will not be given when user requests for ANY available DMA channel using 'EDMA3_RM_DMA_CHANNEL_ANY' as resource/channel id. +

Referenced by EDMA3_RM_allocContiguousResource(), and EDMA3_RM_allocResource().

+ +
+

+ +

+
+ + + + +
unsigned int EDMA3_RM_InstanceInitConfig::resvdQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS]
+
+
+ +

+Reserved QDMA channels. +

+QDMA channels reserved during initialization for future use. These will not be given when user requests for ANY available QDMA channel using 'EDMA3_RM_QDMA_CHANNEL_ANY' as resource/channel id. +

Referenced by EDMA3_RM_allocContiguousResource(), and EDMA3_RM_allocResource().

+ +
+

+ +

+
+ + + + +
unsigned int EDMA3_RM_InstanceInitConfig::resvdTccs[EDMA3_MAX_TCC_DWRDS]
+
+
+ +

+Reserved TCCs. +

+TCCs reserved during initialization for future use. These will not be given when user requests for ANY available TCC using 'EDMA3_RM_TCC_ANY' as resource/channel id. +

Referenced by EDMA3_RM_allocContiguousResource(), and EDMA3_RM_allocResource().

+ +
+

+

The documentation for this struct was generated from the following file: +
+
Generated on Thu Oct 16 16:22:42 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__miscparam.html b/packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__miscparam.html new file mode 100644 index 0000000..45c732d --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__miscparam.html @@ -0,0 +1,85 @@ + + +EDMA3 Resource Manager: EDMA3_RM_MiscParam Struct Reference + + + + + +
+

EDMA3_RM_MiscParam Struct Reference
+ +[Interface Definition for EDMA3 Resource Manager Layer] +

Used to specify the miscellaneous options during Resource Manager Initialization. +More... +

+#include <edma3_rm.h> +

+ + + + + + + +

Data Fields

unsigned short isSlave
unsigned short param
+

Detailed Description

+Used to specify the miscellaneous options during Resource Manager Initialization. +

+This configuration structure is used to specify some misc options while creating the RM Object. New options may also be added into this structure in future.

Field Documentation

+ +
+
+ + + + +
unsigned short EDMA3_RM_MiscParam::isSlave
+
+
+ +

+In a multi-master system (for e.g. ARM + DSP), this option is used to distinguish between Master and Slave. Only the Master is allowed to program the global EDMA3 registers (like Queue priority, Queue water- mark level, error registers etc). +

Referenced by EDMA3_RM_create().

+ +
+

+ +

+
+ + + + +
unsigned short EDMA3_RM_MiscParam::param
+
+
+ +

+For future use +

+

+

The documentation for this struct was generated from the following file: +
+
Generated on Thu Oct 16 16:22:42 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__obj.html b/packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__obj.html new file mode 100644 index 0000000..53eed07 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__obj.html @@ -0,0 +1,128 @@ + + +EDMA3 Resource Manager: EDMA3_RM_Obj Struct Reference + + + + + +
+

EDMA3_RM_Obj Struct Reference
+ +[Object Maintenance] +

EDMA3 Hardware Instance Configuration Structure. +More... +

+#include <edma3resmgr.h> +

+ + + + + + + + + + + + +

Data Fields

unsigned int phyCtrllerInstId
EDMA3_RM_ObjState state
unsigned int numOpens
EDMA3_RM_GblConfigParams gblCfgParams
 Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information.
+

Detailed Description

+EDMA3 Hardware Instance Configuration Structure. +

+Used to maintain information of the EDMA3 HW configuration. One such storage exists for each instance of the EDMA 3 HW.

Field Documentation

+ +
+
+ + + + +
unsigned int EDMA3_RM_Obj::phyCtrllerInstId
+
+
+ +

+HW Instance Id of the EDMA3 Controller +

Referenced by EDMA3_RM_allocLogicalChannel(), EDMA3_RM_close(), EDMA3_RM_create(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_getInstanceInitCfg(), EDMA3_RM_getPaRAM(), EDMA3_RM_getPaRAMPhyAddr(), EDMA3_RM_setPaRAM(), edma3CCErrHandler(), edma3ShadowRegionInit(), and edma3TCErrHandler().

+ +
+

+ +

+
+ + + + +
EDMA3_RM_ObjState EDMA3_RM_Obj::state
+
+
+ +

+State information of the Resource Manager object +

Referenced by EDMA3_RM_close(), EDMA3_RM_create(), EDMA3_RM_delete(), and EDMA3_RM_open().

+ +
+

+ +

+
+ + + + +
unsigned int EDMA3_RM_Obj::numOpens
+
+
+ +

+Number of active opens of RM Instances +

Referenced by EDMA3_RM_close(), EDMA3_RM_create(), EDMA3_RM_open(), edma3CCErrHandler(), and edma3TCErrHandler().

+ +
+

+ +

+
+ + + + +
EDMA3_RM_GblConfigParams EDMA3_RM_Obj::gblCfgParams
+
+
+ +

+Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. +

+This configuration will can be provided by the user at run-time, while calling EDMA3_RM_create(). +

Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocLogicalChannel(), EDMA3_RM_allocResource(), EDMA3_RM_checkAndClearTcc(), EDMA3_RM_close(), EDMA3_RM_create(), EDMA3_RM_freeContiguousResource(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_freeResource(), EDMA3_RM_getBaseAddress(), EDMA3_RM_getCCRegister(), EDMA3_RM_getPaRAM(), EDMA3_RM_getPaRAMPhyAddr(), EDMA3_RM_mapEdmaChannel(), EDMA3_RM_mapQdmaChannel(), EDMA3_RM_open(), EDMA3_RM_registerTccCb(), EDMA3_RM_setCCRegister(), EDMA3_RM_setPaRAM(), EDMA3_RM_unregisterTccCb(), EDMA3_RM_waitAndClearTcc(), edma3CCErrHandler(), edma3ComplHandler(), edma3TCErrHandler(), and gblChngAllocContigRes().

+ +
+

+

The documentation for this struct was generated from the following file: +
+
Generated on Thu Oct 16 16:22:43 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__param.html b/packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__param.html new file mode 100644 index 0000000..78d81db --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__param.html @@ -0,0 +1,163 @@ + + +EDMA3 Resource Manager: EDMA3_RM_Param Struct Reference + + + + + +
+

EDMA3_RM_Param Struct Reference
+ +[Interface Definition for EDMA3 Resource Manager Layer] +

Used to Initialize the Resource Manager Instance. +More... +

+#include <edma3_rm.h> +

+ + + + + + + + + + + + + + + +

Data Fields

EDMA3_RM_RegionId regionId
unsigned short isMaster
EDMA3_RM_InstanceInitConfig * rmInstInitConfig
void * rmSemHandle
unsigned short regionInitEnable
EDMA3_RM_GblErrCallbackParams gblerrCbParams
+

Detailed Description

+Used to Initialize the Resource Manager Instance. +

+This configuration structure is used to initialize the EDMA3 RM Instance. This configuration information is passed while opening the RM instance.

Field Documentation

+ +
+
+ + + + +
EDMA3_RM_RegionId EDMA3_RM_Param::regionId
+
+
+ +

+Shadow Region Identification +

Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_checkAndClearTcc(), EDMA3_RM_freeResource(), EDMA3_RM_open(), EDMA3_RM_waitAndClearTcc(), edma3CCErrHandler(), edma3ShadowRegionInit(), edma3TCErrHandler(), and gblChngAllocContigRes().

+ +
+

+ +

+
+ + + + +
unsigned short EDMA3_RM_Param::isMaster
+
+
+ +

+It tells whether the EDMA3 RM instance is Master or not. Only the shadow region associated with this master instance will receive the EDMA3 interrupts (if enabled). +

Referenced by EDMA3_RM_close(), and EDMA3_RM_open().

+ +
+

+ +

+
+ + + + +
EDMA3_RM_InstanceInitConfig* EDMA3_RM_Param::rmInstInitConfig
+
+
+ +

+EDMA3 resources related shadow region specific information. Which all EDMA3 resources are owned and reserved by this particular instance are told in this configuration structure. User can also pass this structure as NULL. In that case, default static configuration would be taken from the platform specific configuration files (part of the Resource Manager), if available. +

Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_freeResource(), EDMA3_RM_mapEdmaChannel(), EDMA3_RM_mapQdmaChannel(), EDMA3_RM_open(), edma3CCErrHandler(), and edma3ShadowRegionInit().

+ +
+

+ +

+
+ + + + +
void* EDMA3_RM_Param::rmSemHandle
+
+
+ +

+EDMA3 RM Instance specific semaphore handle. Used to share resources (DMA/QDMA channels, PaRAM Sets, TCCs etc) among different users. +

Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocResource(), EDMA3_RM_open(), and EDMA3_RM_setCCRegister().

+ +
+

+ +

+
+ + + + +
unsigned short EDMA3_RM_Param::regionInitEnable
+
+
+ +

+Whether initialization of Region Specific Registers is required or not? +

Referenced by EDMA3_RM_open().

+ +
+

+ +

+
+ + + + +
EDMA3_RM_GblErrCallbackParams EDMA3_RM_Param::gblerrCbParams
+
+
+ +

+Instance wide Global Error callback parameters +

Referenced by edma3CCErrHandler(), and edma3TCErrHandler().

+ +
+

+

The documentation for this struct was generated from the following file: +
+
Generated on Thu Oct 16 16:22:43 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__paramentryregs.html b/packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__paramentryregs.html new file mode 100644 index 0000000..ce7a5fe --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__paramentryregs.html @@ -0,0 +1,140 @@ + + +EDMA3 Resource Manager: EDMA3_RM_ParamentryRegs Struct Reference + + + + + +
+

EDMA3_RM_ParamentryRegs Struct Reference
+ +[EDMA3 Resources Management] +

EDMA3 PaRAM Set. +More... +

+#include <edma3_rm.h> +

+ + + + + + + + + + + + + + + + + + + + + + + + +

Data Fields

volatile unsigned int OPT
+volatile unsigned int SRC
 Starting byte address of Source For FIFO mode, srcAddr must be a 256-bit aligned address.
volatile unsigned int A_B_CNT
+volatile unsigned int DST
 Starting byte address of destination For FIFO mode, destAddr must be a 256-bit aligned address. i.e. 5 LSBs should be 0.
volatile unsigned int SRC_DST_BIDX
volatile unsigned int LINK_BCNTRLD
 Address for linking (AutoReloading of a PaRAM Set) (16 bits) and Reload value of the numArrInFrame (BCNT) (16 bits).
+volatile unsigned int SRC_DST_CIDX
 Index between consecutive frames of a Source Block (SRCCIDX) (16 bits) and Index between consecutive frames of a Dest Block (DSTCIDX) (16 bits).
+volatile unsigned int CCNT
 Number of Frames in a block (CCNT) (16 bits).
+

Detailed Description

+EDMA3 PaRAM Set. +

+This is a mapping of the EDMA3 PaRAM set provided to the user for ease of modification of the individual PaRAM words.

+It could be used by the advanced users to program the PaRAM Set directly, without using any API.

Field Documentation

+ +
+
+ + + + +
volatile unsigned int EDMA3_RM_ParamentryRegs::OPT
+
+
+ +

+OPT field of PaRAM Set +

+

+ +

+
+ + + + +
volatile unsigned int EDMA3_RM_ParamentryRegs::A_B_CNT
+
+
+ +

+Number of bytes in each Array (ACNT) (16 bits) and Number of Arrays in each Frame (BCNT) (16 bits). +

+

+ +

+
+ + + + +
volatile unsigned int EDMA3_RM_ParamentryRegs::SRC_DST_BIDX
+
+
+ +

+Index between consec. arrays of a Source Frame (SRCBIDX) (16 bits) and Index between consec. arrays of a Destination Frame (DSTBIDX) (16 bits).

+If SAM is set to 1 (via channelOptions) then srcInterArrIndex should be an even multiple of 32 bytes.

+If DAM is set to 1 (via channelOptions) then destInterArrIndex should be an even multiple of 32 bytes +

+

+ +

+
+ + + + +
volatile unsigned int EDMA3_RM_ParamentryRegs::LINK_BCNTRLD
+
+
+ +

+Address for linking (AutoReloading of a PaRAM Set) (16 bits) and Reload value of the numArrInFrame (BCNT) (16 bits). +

+Link field must point to a valid aligned 32-byte PaRAM set A value of 0xFFFF means no linking.

+B count reload field is relevant only for A-sync transfers. +

+

+

The documentation for this struct was generated from the following file: +
+
Generated on Thu Oct 16 16:22:43 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__paramregs.html b/packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__paramregs.html new file mode 100644 index 0000000..b8ba9b2 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__paramregs.html @@ -0,0 +1,110 @@ + + +EDMA3 Resource Manager: EDMA3_RM_PaRAMRegs Struct Reference + + + + + +
+

EDMA3_RM_PaRAMRegs Struct Reference
+ +[EDMA3 Resources Management] +

EDMA3 PaRAM Set in User Configurable format. +More... +

+#include <edma3_rm.h> +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Data Fields

volatile unsigned int opt
+volatile unsigned int srcAddr
 Starting byte address of Source For FIFO mode, srcAddr must be a 256-bit aligned address.
+volatile unsigned short aCnt
 Number of bytes in each Array (ACNT).
+volatile unsigned short bCnt
 Number of Arrays in each Frame (BCNT).
+volatile unsigned int destAddr
 Starting byte address of destination For FIFO mode, destAddr must be a 256-bit aligned address. i.e. 5 LSBs should be 0.
+volatile short srcBIdx
 Index between consec. arrays of a Source Frame (SRCBIDX) If SAM is set to 1 (via channelOptions) then srcInterArrIndex should be an even multiple of 32 bytes.
+volatile short destBIdx
 Index between consec. arrays of a Destination Frame (DSTBIDX) If DAM is set to 1 (via channelOptions) then destInterArrIndex should be an even multiple of 32 bytes.
+volatile unsigned short linkAddr
 Address for linking (AutoReloading of a PaRAM Set) This must point to a valid aligned 32-byte PaRAM set A value of 0xFFFF means no linking Linking is especially useful for use with ping-pong buffers and circular buffers.
+volatile unsigned short bCntReload
 Reload value of the numArrInFrame (BCNT) Relevant only for A-sync transfers.
+volatile short srcCIdx
 Index between consecutive frames of a Source Block (SRCCIDX).
+volatile short destCIdx
 Index between consecutive frames of a Dest Block (DSTCIDX).
+volatile unsigned short cCnt
 Number of Frames in a block (CCNT).
+

Detailed Description

+EDMA3 PaRAM Set in User Configurable format. +

+This is a mapping of the EDMA3 PaRAM set provided to the user for ease of modification of the individual fields.

Field Documentation

+ +
+
+ + + + +
volatile unsigned int EDMA3_RM_PaRAMRegs::opt
+
+
+ +

+OPT field of PaRAM Set +

+

+

The documentation for this struct was generated from the following file: +
+
Generated on Thu Oct 16 16:22:43 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__resdesc.html b/packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__resdesc.html new file mode 100644 index 0000000..db0a92c --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__resdesc.html @@ -0,0 +1,85 @@ + + +EDMA3 Resource Manager: EDMA3_RM_ResDesc Struct Reference + + + + + +
+

EDMA3_RM_ResDesc Struct Reference
+ +[Resource Type] +

Handle to a Resource. +More... +

+#include <edma3_rm.h> +

+ + + + + + + +

Data Fields

unsigned int resId
EDMA3_RM_ResType type
+

Detailed Description

+Handle to a Resource.

Field Documentation

+ +
+
+ + + + +
unsigned int EDMA3_RM_ResDesc::resId
+
+
+ +

+Resource Id Range of resId values : As an example, for resource Type = EDMA3_RM_RES_DMA_CHANNEL, resId can take values from 0 to EDMA3_MAX_DMA_CH Or resId can take the value EDMA3_RM_RES_ANY. +

Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocLogicalChannel(), EDMA3_RM_allocResource(), EDMA3_RM_freeContiguousResource(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_freeResource(), EDMA3_RM_getPaRAM(), EDMA3_RM_getPaRAMPhyAddr(), EDMA3_RM_registerTccCb(), EDMA3_RM_setPaRAM(), EDMA3_RM_unregisterTccCb(), and gblChngAllocContigRes().

+ +
+

+ +

+
+ + + + +
EDMA3_RM_ResType EDMA3_RM_ResDesc::type
+
+
+ +

+Resource Type +

Referenced by EDMA3_RM_allocContiguousResource(), EDMA3_RM_allocLogicalChannel(), EDMA3_RM_allocResource(), EDMA3_RM_freeContiguousResource(), EDMA3_RM_freeLogicalChannel(), EDMA3_RM_freeResource(), EDMA3_RM_getPaRAM(), EDMA3_RM_getPaRAMPhyAddr(), EDMA3_RM_registerTccCb(), EDMA3_RM_setPaRAM(), EDMA3_RM_unregisterTccCb(), and gblChngAllocContigRes().

+ +
+

+

The documentation for this struct was generated from the following file: +
+
Generated on Thu Oct 16 16:22:43 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
+ + diff --git a/packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__tcccallbackparams.html b/packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__tcccallbackparams.html new file mode 100644 index 0000000..596e06e --- /dev/null +++ b/packages/ti/sdo/edma3/rm/docs/html/structedma3__rm__tcccallbackparams.html @@ -0,0 +1,85 @@ + + +EDMA3 Resource Manager: EDMA3_RM_TccCallbackParams Struct Reference + + + + + +
+

EDMA3_RM_TccCallbackParams Struct Reference
+ +[Internal Interface Definition for Resource Manager] +

TCC Callback - Caters to channel specific status reporting. +More... +

+#include <edma3resmgr.h> +

+ + + + + + + +

Data Fields

EDMA3_RM_TccCallback tccCb
void * cbData
+

Detailed Description

+TCC Callback - Caters to channel specific status reporting.

Field Documentation

+ +
+
+ + + + +
EDMA3_RM_TccCallback EDMA3_RM_TccCallbackParams::tccCb
+
+
+ +

+Callback function +

Referenced by EDMA3_RM_registerTccCb(), EDMA3_RM_unregisterTccCb(), edma3CCErrHandler(), and edma3ComplHandler().

+ +
+

+ +

+
+ + + + +
void* EDMA3_RM_TccCallbackParams::cbData
+
+
+ +

+Callback data, passed to the Callback function +

Referenced by EDMA3_RM_registerTccCb(), and EDMA3_RM_unregisterTccCb().

+ +
+

+

The documentation for this struct was generated from the following file: +
+
Generated on Thu Oct 16 16:22:43 2008 for EDMA3 Resource Manager by  + +doxygen 1.5.6
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Uses semaphore and + interrupts disabling mechanism + for resource sharing. + 0.3.0 Anuj Aggarwal - Renamed EDMA3_DVR to EDMA3_DRV + - IPR bit clearing in RM ISR + issue fixed. + - Sample application made generic + 0.3.1 Anuj Aggarwal - Added DMA/QDMA Channel to TCC + mapping, to fix QDMA missed + event issue. + 0.3.2 Anuj Aggarwal - Added support for POLL mode + - Added a new API to modify the + CC Register. + 1.0.0 Anuj Aggarwal - Fixed resource allocation related + bugs. + 1.0.0.1 Anuj Aggarwal - Fixed spurious missed event + generation related bug. + 1.0.0.2 Anuj Aggarwal - Made the EDMA3 package RTSC + compliant. + 1.0.0.3 Anuj Aggarwal - Changed the directory structure + as per RTSC standard. + 1.01.00.01 Anuj Aggarwal - a) Added new APIs to allocate + logical channels + b) Created EDMA3 config files + for different platforms + c) Misc changes + 1.02.00.01 Anuj Aggarwal - a) Added DM6467 support + b) Fixed some MRs + 1.03.00.01 Anuj Aggarwal - a) Added non-RTSC PJT files + b) IOCTL Interface added. + c) Fixed some MRs. + 1.04 Anuj Aggarwal - a) Added new IOCTLs and APIs. + b) Number of maximum Resource + Manager Instances is configurable. + c) Header files modified to have + extern "C" declarations. + + + */ + +#ifndef _EDMA3_COMMON_H_ +#define _EDMA3_COMMON_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** define to enable/disable Resource Manager debug messages*/ +#define EDMA3_RM_DEBUG +#undef EDMA3_RM_DEBUG + +/** define to enable/disable EDMA3 Driver debug messages*/ +#define EDMA3_DRV_DEBUG +#undef EDMA3_DRV_DEBUG + + +/** Debug mechanism used for Resource Manager */ +#ifdef EDMA3_RM_DEBUG +#include +#define EDMA3_RM_PRINTF printf +#endif + +/** Debug mechanism used for EDMA Driver */ +#ifdef EDMA3_DRV_DEBUG +#include +#define EDMA3_DRV_PRINTF printf +#endif + + +/** Defines for boolean variables */ +#ifndef TRUE + /** TRUE */ + #define TRUE (1u) + /** FALSE */ + #define FALSE (0u) +#endif + + +/** Define for NULL values*/ +#ifndef NULL +#define NULL 0u +#endif + + +/** EDMA3_RM Result - return value of a function */ +typedef int EDMA3_RM_Result; +/** EDMA3_DRV Result - return value of a function */ +typedef int EDMA3_DRV_Result; + + +/** EDMA3 Resource Manager Result OK */ +#define EDMA3_RM_SOK (0u) +/** EDMA3 Driver Result OK */ +#define EDMA3_DRV_SOK (0u) + + +/** + * EDMA3 Resource Manager Handle. + * It will be returned from EDMA3_RM_open() and will be used to call + * other Resource Manager APIs. + */ +typedef void *EDMA3_RM_Handle; +/** + * EDMA3 Driver Handle. + * It will be returned from EDMA3_DRV_open() and will be used to call + * other EDMA3 Driver APIs. + */ +typedef void *EDMA3_DRV_Handle; + + +/** + * OS specific Semaphore Handle. + * Used to acquire/free the semaphore, used for sharing of resources + * among multiple users. + */ +typedef void *EDMA3_OS_Sem_Handle; + +/** Blocking call without timeout */ +#define EDMA3_OSSEM_NO_TIMEOUT (-1) + + +/** + * Defines used to support the maximum resources supported + * by the EDMA3 controller. These are used to allocate the maximum + * memory for different data structures of the EDMA3 Driver and Resource + * Manager. + */ +/** Maximum EDMA3 Controllers on the SoC */ +#define EDMA3_MAX_EDMA3_INSTANCES (1u) +/** Maximum DMA channels supported by the EDMA3 Controller */ +#define EDMA3_MAX_DMA_CH (64u) +/** Maximum QDMA channels supported by the EDMA3 Controller */ +#define EDMA3_MAX_QDMA_CH (8u) +/** Maximum PaRAM Sets supported by the EDMA3 Controller */ +#define EDMA3_MAX_PARAM_SETS (512u) +/** Maximum Logical channels supported by the EDMA3 Package */ +#define EDMA3_MAX_LOGICAL_CH (EDMA3_MAX_DMA_CH + \ + EDMA3_MAX_PARAM_SETS + \ + EDMA3_MAX_QDMA_CH) +/** Maximum TCCs (Interrupt Channels) supported by the EDMA3 Controller */ +#define EDMA3_MAX_TCC (64u) +/** Maximum Event Queues supported by the EDMA3 Controller */ +#define EDMA3_MAX_EVT_QUE (8u) +/** Maximum Transfer Controllers supported by the EDMA3 Controller */ +#define EDMA3_MAX_TC (8u) +/** Maximum Shadow Regions supported by the EDMA3 Controller */ +#define EDMA3_MAX_REGIONS (8u) + +/** + * Maximum Words (4-bytes region) required for the book-keeping information + * specific to the maximum possible DMA channels. + */ +#define EDMA3_MAX_DMA_CHAN_DWRDS (EDMA3_MAX_DMA_CH / 32u) + +/** + * Maximum Words (4-bytes region) required for the book-keeping information + * specific to the maximum possible QDMA channels. + */ +#define EDMA3_MAX_QDMA_CHAN_DWRDS (1u) + +/** + * Maximum Words (4-bytes region) required for the book-keeping information + * specific to the maximum possible PaRAM Sets. + */ +#define EDMA3_MAX_PARAM_DWRDS (EDMA3_MAX_PARAM_SETS / 32u) + +/** + * Maximum Words (4-bytes region) required for the book-keeping information + * specific to the maximum possible TCCs. + */ +#define EDMA3_MAX_TCC_DWRDS (EDMA3_MAX_TCC / 32u) + + + +/** + * EDMA3 ISRs which need to be registered with the underlying OS by the user + * (Not all TC error ISRs need to be registered, register only for the + * available Transfer Controllers). + */ + +/** EDMA3 Completion Handler ISR Routine */ +extern void lisrEdma3ComplHandler0 (unsigned int arg); + +/** EDMA3 CC Error Interrupt Handler ISR Routine */ +extern void lisrEdma3CCErrHandler0 (unsigned int arg); + +/** EDMA3 TC0 Error Interrupt Handler ISR Routine */ +extern void lisrEdma3TC0ErrHandler0(unsigned int arg); +/** EDMA3 TC1 Error Interrupt Handler ISR Routine */ +extern void lisrEdma3TC1ErrHandler0(unsigned int arg); +/** EDMA3 TC2 Error Interrupt Handler ISR Routine */ +extern void lisrEdma3TC2ErrHandler0(unsigned int arg); +/** EDMA3 TC3 Error Interrupt Handler ISR Routine */ +extern void lisrEdma3TC3ErrHandler0(unsigned int arg); +/** EDMA3 TC4 Error Interrupt Handler ISR Routine */ +extern void lisrEdma3TC4ErrHandler0(unsigned int arg); +/** EDMA3 TC5 Error Interrupt Handler ISR Routine */ +extern void lisrEdma3TC5ErrHandler0(unsigned int arg); +/** EDMA3 TC6 Error Interrupt Handler ISR Routine */ +extern void lisrEdma3TC6ErrHandler0(unsigned int arg); +/** EDMA3 TC7 Error Interrupt Handler ISR Routine */ +extern void lisrEdma3TC7ErrHandler0(unsigned int arg); + + + +/** + * Defines for the level of OS protection needed when calling + * edma3OsProtectEntry() + */ + +/** Protection from All Interrupts required */ +#define EDMA3_OS_PROTECT_INTERRUPT 1 +/** Protection from scheduling required */ +#define EDMA3_OS_PROTECT_SCHEDULER 2 +/** Protection from EDMA3 Transfer Completion Interrupt required */ +#define EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION 3 +/** Protection from EDMA3 CC Error Interrupt required */ +#define EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR 4 +/** Protection from EDMA3 TC Error Interrupt required */ +#define EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR 5 + + + +/** + * Critical section entry and exit functions (OS dependent) should be + * implemented by the application for proper linking with the EDMA3 Driver + * and/or EDMA3 Resource Manager. Without the definitions being provided, + * the image wonÂ’t get linked properly. + * + * It is possible that for some regions of code, user needs ultimate + * degree of protection where some or all external interrupts are blocked, + * essentially locking out the CPU exclusively for the critical + * section of code. On the other hand, user may wish to merely avoid + * thread or task switch from occuring inside said region of code, + * but he may wish to entertain ISRs to run if so required. + * + * Depending on the underlying OS, the number of levels of protection + * offered may vary. At the least, these basic levels of protection are + * supported -- + * - EDMA3_OS_PROTECT_INTERRUPT - Mask interrupts globally. This has + * real-time implications and must be used with descretion. + + * - EDMA3_OS_PROTECT_SCHEDULER - Only turns off Kernel scheduler + * completely, but still allows h/w interrupts from being serviced. + + * - EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION - Mask EDMA3 Transfer + Completion Interrupt. + + * - EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR - Mask EDMA3 CC Error Interrupt. + + * - EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR - Mask EDMA3 TC Error Interrupt. + + * These APIs should be mandatorily implemented ONCE by the global + * initialization routine or by the user itself. + */ + +/** \fn extern void edma3OsProtectEntry (int level, unsigned int *intState); + * \brief EDMA3 OS Protect Entry + * + * This function saves the current state of protection in 'intState' + * variable passed by caller, if the protection level is + * EDMA3_OS_PROTECT_INTERRUPT. It then applies the requested level of + * protection. + * For EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION and + * EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR, variable 'intState' is ignored, + * and the requested interrupt is disabled. + * For EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR, '*intState' specifies the + * Transfer Controller number whose interrupt needs to be disabled. + * + * \param level is numeric identifier of the desired degree of protection. + * \param intState is memory location where current state of protection is + * saved for future use while restoring it via edma3OsProtectExit() (Only + * for EDMA3_OS_PROTECT_INTERRUPT protection level). + * + * \return None + */ +extern void edma3OsProtectEntry (int level, unsigned int *intState); + + +/** \fn extern void edma3OsProtectExit (int level, unsigned int intState); + * \brief EDMA3 OS Protect Exit + * + * This function undoes the protection enforced to original state + * as is specified by the variable 'intState' passed, if the protection + * level is EDMA3_OS_PROTECT_INTERRUPT. + * For EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION and + * EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR, variable 'intState' is ignored, + * and the requested interrupt is enabled. + * For EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR, 'intState' specifies the + * Transfer Controller number whose interrupt needs to be enabled. + * + * \param level is numeric identifier of the desired degree of protection. + * \param intState is original state of protection at time when the + * corresponding edma3OsProtectEntry() was called (Only + * for EDMA3_OS_PROTECT_INTERRUPT protection level). + * + * \return None + */ +extern void edma3OsProtectExit (int level, unsigned int intState); + + +/** + * Counting Semaphore related functions (OS dependent) should be + * implemented by the application for proper linking with the EDMA3 + * Driver and Resource Manager. The EDMA3 Resource Manager + * uses these functions for proper sharing of resources (among various users) + * and assume the implementation of these functions + * to be provided by the application. Without the definitions being provided, + * the image wonÂ’t get linked properly. + */ +/** \fn extern EDMA3_DRV_Result edma3OsSemTake (EDMA3_OS_Sem_Handle hSem, + * int mSecTimeout); + * \brief EDMA3 OS Semaphore Take + * + * This function takes a semaphore token if available. + * If a semaphore is unavailable, it blocks currently + * running thread in wait (for specified duration) for + * a free semaphore. + * + * \param hSem [IN] is the handle of the specified semaphore + * \param mSecTimeout [IN] is wait time in milliseconds + * + * \return EDMA3_DRV_Result if successful else a suitable error code + */ +extern EDMA3_DRV_Result edma3OsSemTake (EDMA3_OS_Sem_Handle hSem, + int mSecTimeout); + +/** \fn extern EDMA3_DRV_Result edma3OsSemGive(EDMA3_OS_Sem_Handle hSem); + * \brief EDMA3 OS Semaphore Give + * + * This function gives or relinquishes an already + * acquired semaphore token + * + * \param hSem [IN] is the handle of the specified semaphore + * + * \return EDMA3_DRV_Result if successful else a suitable error code + */ +extern EDMA3_DRV_Result edma3OsSemGive(EDMA3_OS_Sem_Handle hSem); + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif /* _EDMA3_COMMON_H_ */ + diff --git a/packages/ti/sdo/edma3/rm/edma3_rm.h b/packages/ti/sdo/edma3/rm/edma3_rm.h new file mode 100644 index 0000000..24afc26 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/edma3_rm.h @@ -0,0 +1,2421 @@ +/******************************************************************************* +**+--------------------------------------------------------------------------+** +**| **** |** +**| **** |** +**| ******o*** |** +**| ********_///_**** |** +**| ***** /_//_/ **** |** +**| ** ** (__/ **** |** +**| ********* |** +**| **** |** +**| *** |** +**| |** +**| Copyright (c) 1998-2006 Texas Instruments Incorporated |** +**| ALL RIGHTS RESERVED |** +**| |** +**| Permission is hereby granted to licensees of Texas Instruments |** +**| Incorporated (TI) products to use this computer program for the sole |** +**| purpose of implementing a licensee product based on TI products. |** +**| No other rights to reproduce, use, or disseminate this computer |** +**| program, whether in part or in whole, are granted. |** +**| |** +**| TI makes no representation or warranties with respect to the |** +**| performance of this computer program, and specifically disclaims |** +**| any responsibility for any damages, special or consequential, |** +**| connected with the use of this program. |** +**| |** +**+--------------------------------------------------------------------------+** +*******************************************************************************/ + +/** \file edma3_rm.h + \brief EDMA3 Controller Resource Manager Interface + + This file contains Application Interface for the EDMA3 Controller + Resource Manager. + + (C) Copyright 2006, Texas Instruments, Inc + + \version 0.0.1 Purushotam Kumar - Created + 0.1.0 Joseph Fernandez - Made generic + - Added documentation + - Moved SoC specific defines + to SoC specific header. + 0.2.0 Anuj Aggarwal - Modified it for EDMA3 package + - Added multiple instances + capability + 0.2.1 Anuj Aggarwal - Modified it for more run time + configuration. + - Made EDMA3 package OS + independent. + 0.2.2 Anuj Aggarwal - Critical section handling code + modification. Uses semaphore and + interrupts disabling mechanism + for resource sharing. + 0.3.0 Anuj Aggarwal - Renamed EDMA3_DVR to EDMA3_DRV + - IPR bit clearing in RM ISR + issue fixed. + - Sample application made generic + 0.3.1 Anuj Aggarwal - Added DMA/QDMA Channel to TCC + mapping, to fix QDMA missed + event issue. + 0.3.2 Anuj Aggarwal - Added support for POLL mode + - Added a new API to modify the + CC Register. + 1.0.0 Anuj Aggarwal - Fixed resource allocation related + bugs. + 1.0.0.1 Anuj Aggarwal - Fixed spurious missed event + generation related bug. + 1.0.0.2 Anuj Aggarwal - Made the EDMA3 package RTSC + compliant. + 1.0.0.3 Anuj Aggarwal - Changed the directory structure + as per RTSC standard. + 1.01.00.01 Anuj Aggarwal - a) Added new APIs to allocate + logical channels + b) Created EDMA3 config files + for different platforms + c) Misc changes + 1.02.00.01 Anuj Aggarwal - a) Added DM6467 support + b) Fixed some MRs + 1.03.00.01 Anuj Aggarwal - a) Added non-RTSC PJT files + b) IOCTL Interface added. + c) Fixed some MRs. + 1.04 Anuj Aggarwal - a) Added new IOCTLs and APIs. + b) Number of maximum Resource + Manager Instances is configurable. + c) Header files modified to have + extern "C" declarations. + + + */ + +#ifndef _EDMA3_RM_H_ +#define _EDMA3_RM_H_ + +/** Include common header file */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + + + +/** + * \defgroup Edma3RMIntrMgrMain EDMA3 Interrupt Manager Interface + * + * Top-level Encapsulation of documentation for EDMA3 Interrupt Manager Layer + * + * @{ + */ + + +/** + * \defgroup Edma3RMIntrMgrInst Instance Wide Interface + * + * Instance Wide Interface of the EDMA3 Interrupt Manager Layer + * + * @{ + */ + + +/** + * \defgroup Edma3RMStatus Completion status + * + * This group defines the error codes of completion + * of an EDMA3 transfer. + * + * @{ + */ + +/**\enum EDMA3_RM_TccStatus + * \brief This enum defines the channel specific status codes of + * an EDMA3 transfer. It is returned while calling the channel + * specific callback function to tell the status. + */ +typedef enum +{ + /** + * DMA Transfer successfully completed (true completion mode) + * or submitted to the TC (early completion mode). + */ + EDMA3_RM_XFER_COMPLETE = 1, + + /** Channel Controller has reported an error */ + /** + * DMA missed events:- for all 64 DMA channels. + * These get latched in the event missed registers (EMR/EMRH). + */ + EDMA3_RM_E_CC_DMA_EVT_MISS = 2, + + /** + * QDMA missed events:- for all QDMA channels. + * These get latched in the QDMA event missed register (QEMR). + */ + EDMA3_RM_E_CC_QDMA_EVT_MISS = 3 + +} EDMA3_RM_TccStatus; + + + +/**\enum EDMA3_RM_GlobalError + * \brief This enum defines the global (not specific to any channel) + * error codes of completion of an EDMA3 transfer. + */ +typedef enum +{ + /** + * Threshold exceed:- for all event queues. + * These get latched in EDMA3CC error register (CCERR). + * This error has a direct relation with the setting of + * EDMA3_RM_GblConfigParams.evtQueueWaterMarkLvl + */ + EDMA3_RM_E_CC_QUE_THRES_EXCEED = 1, + + /** + * TCC error:- for outstanding transfer requests expected to return + * completion code (TCCHEN or TCINTEN bit in OPT is set to 1) exceeding + * the maximum limit of 63. This also gets latched in the CCERR. + */ + EDMA3_RM_E_CC_TCC = 2, + + /** Transfer Controller has reported an error */ + /** + * Detection of a Read error signaled by the source or destination address + */ + EDMA3_RM_E_TC_MEM_LOCATION_READ_ERROR = 3, + + /** + * Detection of a Write error signaled by the source or destination address + */ + EDMA3_RM_E_TC_MEM_LOCATION_WRITE_ERROR = 4, + + /** + * Attempt to read or write to an invalid address in the configuration + * memory map. + */ + EDMA3_RM_E_TC_INVALID_ADDR = 5, + + /** + * Detection of a FIFO mode TR violating the FIFO mode transfer rules + * (the source/destination addresses and source/destination indexes must + * be aligned to 32 bytes). + */ + EDMA3_RM_E_TC_TR_ERROR = 6 +} EDMA3_RM_GlobalError; + + +/* }@ Edma3RMStatus */ + + +/** + * \brief Global Error callback - caters to module events like bus error etc + * which are not channel specific. Runs in ISR context. + * + * gblerrData is application provided data when open'ing the Resource Manager. + */ +typedef void (* EDMA3_RM_GblErrCallback)(EDMA3_RM_GlobalError deviceStatus, + unsigned int instanceId, + void *gblerrData); + +/**\struct EDMA3_RM_GblErrCallbackParams + * \brief Global Error Callback parameters + * + * Consists of the Callback function and the data to be passed to it. + */ +typedef struct { + /** + * Instance wide callback function to catch non-channel specific errors. + */ + EDMA3_RM_GblErrCallback gblerrCb; + + /** Application data to be passed back to the Global Error callback */ + void *gblerrData; + +} EDMA3_RM_GblErrCallbackParams; + +/* @} Edma3RMIntrMgrInst */ + + +/** + * \defgroup Edma3RMIntrMgrChannel Channel Specific Interface + * + * Channel Specific Interface of the EDMA3 Interrupt Manager Layer + * + * @{ + */ + +/** + * \brief TCC callback - caters to channel-specific events like + * "Event Miss Error" or "Transfer Complete". Runs in ISR context. + * + * appData is passed by the application during Register'ing of + * TCC Callback function. + */ +typedef void (* EDMA3_RM_TccCallback)(unsigned int tcc, + EDMA3_RM_TccStatus status, + void *appData); + + +/** + * \defgroup Edma3ResType Resource Type + * + * Resource Type part of the EDMA3 Resource Manager. + * + * @{ + */ + +/**\def EDMA3_RM_RES_ANY + * \brief Used to specify any available Resource Id (EDMA3_RM_ResDesc.resId) + */ +#define EDMA3_RM_RES_ANY (1010u) + + +/**\enum EDMA3_RM_ResType + * \brief EDMA3 Resource Type + */ +typedef enum +{ + /** DMA Channel resource */ + EDMA3_RM_RES_DMA_CHANNEL = 1, + + /** QDMA Channel resource*/ + EDMA3_RM_RES_QDMA_CHANNEL = 2, + + /** TCC resource*/ + EDMA3_RM_RES_TCC = 3, + + /** Parameter RAM Set resource*/ + EDMA3_RM_RES_PARAM_SET = 4 + +} EDMA3_RM_ResType; + + +/**\struct EDMA3_RM_ResDesc + * \brief Handle to a Resource. + */ +typedef struct +{ + /** Resource Id */ + /** + * Range of resId values : + * As an example, for resource Type = EDMA3_RM_RES_DMA_CHANNEL, + * resId can take values from 0 to EDMA3_MAX_DMA_CH + * Or + * resId can take the value EDMA3_RM_RES_ANY. + */ + unsigned int resId; + + /** Resource Type */ + EDMA3_RM_ResType type; +} EDMA3_RM_ResDesc; + +/* @} Edma3ResType */ + + +/** + * \fn EDMA3_RM_Result EDMA3_RM_registerTccCb(EDMA3_RM_Handle hEdmaResMgr, + * const EDMA3_RM_ResDesc *channelObj, unsigned int tcc, + * EDMA3_RM_TccCallback tccCb, void *cbData); + * \brief Register Interrupt / Completion Handler for a given TCC. + * + * This function enables the interrupts in IESR/IESRH, only if the callback + * function provided by the user is NON-NULL. Moreover, if a call-back function + * is already registered against that TCC, the API fails with the error code + * EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED. For a NULL callback function, + * this API returns error. + * + * \param hEdmaResMgr [IN] Handle to the previously opened + * EDMA3 Resource Manager Instance + * \param channelObj [IN] Channel ID and type (DMA or QDMA + * Channel), allocated earlier, and + * corresponding to which a callback + * function needs to be registered + * against the associated TCC. + * \param tcc [IN] TCC against which the handler needs to + * be registered. + * \param tccCb [IN] The Callback function to be registered + * against the TCC. + * \param cbData [IN] Callback data to be passed while calling + * the callback function. + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + * + * \note This function is re-entrant for unique tcc values. It is non- + * re-entrant for same tcc value. + */ +EDMA3_RM_Result EDMA3_RM_registerTccCb(EDMA3_RM_Handle hEdmaResMgr, + const EDMA3_RM_ResDesc *channelObj, + unsigned int tcc, + EDMA3_RM_TccCallback tccCb, + void *cbData); + + +/** + * \fn EDMA3_RM_Result EDMA3_RM_unregisterTccCb(EDMA3_RM_Handle + * hEdmaResMgr, const EDMA3_RM_ResDesc *channelObj); + * \brief Unregister the previously registered callback function against a + * DMA/QDMA channel. + * + * This function unregisters the previously registered callback function against + * a DMA/QDMA channel by removing any stored callback function. Moreover, it + * clears the interrupt enable register (IESR/IESRH) by writing to the IECR/ + * IECRH register, for the TCC associated with that particular channel. + * + * \param hEdmaResMgr [IN] Handle to the previously opened + * EDMA3 Resource Manager Instance + * \param channelObj [IN] Channel ID and type, allocated earlier + * (DMA or QDMA Channel ONLY), and + * corresponding to which a TCC is there. + * Against that TCC, the callback needs + * to be un-registered. + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code. + * + * \note This function is re-entrant for unique (channelObj->type + + * channelObj->resId) combination. It is non-re-entrant for same + * channelObj Resource. + */ +EDMA3_RM_Result EDMA3_RM_unregisterTccCb(EDMA3_RM_Handle hEdmaResMgr, + const EDMA3_RM_ResDesc *channelObj); + +/* @} Edma3RMIntrMgrChannel */ + +/* @} Edma3RMIntrMgrMain */ + + + +/** + * \defgroup Edma3RMMain Interface Definition for EDMA3 Resource Manager Layer + * + * Top-level Encapsulation of all documentation for EDMA3 Resource Manager Layer + * + * @{ + */ + + +/*---------------------------------------------------------------------------*/ +/*------------------Usage Guidelines Start-----------------------------------*/ +/*---------------------------------------------------------------------------*/ + +/** + * \defgroup Edma3RMUsage EDMA3 Resource Manager Usage Guidelines + * + * Guidelines for typical usage of EDMA3 Resource Manager. + * + * @{ + */ + +/** + \brief Usage of Resource Manager. + + -# Create Resource Manager Object (one for each EDMA3 hardware instance) + - EDMA3_RM_Result result = EDMA3_RM_SOK; + - unsigned int edma3HwInstanceId = 0u; + - EDMA3_RM_GblConfigParams *gblCfgParams = NULL; + - Init-time Configuration structure for EDMA3 controller, to provide + Global SoC specific Information. This could be NULL also. In that + case, static configuration will be taken. + - result = EDMA3_RM_create (edma3HwInstanceId, gblCfgParams, NULL); + -# Open Resource Manager Instance + - Steps + - EDMA3_RM_Param initParam; + - unsigned int resMgrIdx = 0; + - EDMA3_RM_Handle hRes = NULL; + - unsigned int mappedPaRAMId; + - EDMA3_OS_SemAttrs semAttrs = {EDMA3_OS_SEMTYPE_FIFO, NULL}; + - EDMA3_RM_Result edma3Result; + -To get the error code while opening Resource Manager instance + + -# initParam.regionId = Region Id + e.g. (EDMA3_RM_RegionId)0u OR (EDMA3_RM_RegionId)1u + + -# initParam.isMaster = TRUE/FALSE (Whether this EDMA3 + RM instance is Master or not. The EDMA3 Shadow Region tied to the + Master RM Instance will ONLY receive the EDMA3 interrupts (error + or completion), if enabled). + + -# initParam.rmSemHandle = + EDMA3 RM Instance specific semaphore handle. It should + be provided by the user for proper sharing of resources. + - edma3Result = edma3OsSemCreate(1, &semAttrs, + &initParam.rmSemHandle ); + + -# initParam.regionInitEnable = TRUE/FALSE (Whether init of Region + Specifc registers should be done or not?); + + -# initParam.gblerrCbParams.gblerrCb = + Instance wide callback function to catch non-channel specific + errors + -# initParam.gblerrCbParams.gblerrData = + Data to be passed to global error callback function, gblerrCb. + + -# initParam.rmInstInitConfig->ownDmaChannels[] = + The bitmap(s) which indicate the DMA channels owned by this + instance of the Resource Manager\n + E.g. A '1' at bit position 24 indicates that this instance of + the Resource Manager owns DMA Channel Id 24\n + Later when a request is made based on a particular Channel Id, + the Resource Manager will check first if it owns that channel. + If it doesnot own it, Resource Manager returns error + EDMA3_RM_E_RES_NOT_OWNED. + -# initParam.rmInstInitConfig->ownQdmaChannels[] = + The bitmap(s) which indicate the QDMA channels owned by this + instance of the Resource Manager\n + -# initParam.rmInstInitConfig->ownPaRAMSets[] = + The bitmap(s) which indicate the PaRAM Sets owned by this + instance of the Resource Manager\n + -# initParam.rmInstInitConfig->ownTccs[] = + The bitmap(s) which indicate the TCCs owned by this + instance of the Resource Manager\n + + -# initParam.rmInstInitConfig->resvdDmaChannels[] = + The bitmap(s) which indicate the DMA channels reserved by this + instance of the Resource Manager\n + E.g. A '1' at bit position 24 indicates that this instance of + the Resource Manager reserves Channel Id 24\n + These channels are reserved and may be mapped to HW events, + these are not given to 'EDMA3_RM_DMA_CHANNEL_ANY' or + 'EDMA3_RM_RES_ANY' requests.\n + -# initParam.rmInstInitConfig->resvdQdmaChannels[] = + The bitmap(s) which indicate the QDMA channels reserved by this + instance of the Resource Manager\n + E.g. A '1' at bit position 1 indicates that this instance of + the Resource Manager reserves QDMA Channel Id 1\n + These channels are reserved for some specific purpose, + these are not given to 'EDMA3_RM_QDMA_CHANNEL_ANY' + or 'EDMA3_RM_RES_ANY' request\n + -# initParam.rmInstInitConfig->resvdPaRAMSets[] = + PaRAM Sets which are reserved by this Region; + -# initParam.rmInstInitConfig->resvdTccs[] = + TCCs which are reserved by this Region; + + -hRes = EDMA3_RM_open (instId, &initParam, &edma3Result); + + -# Register Interrupt Handlers for various interrupts like transfer + completion interrupt, CC error interrupt, TC error interrupts etc, + if required. + + -# Resource Management APIs: + - EDMA3_RM_ResDesc resObj; + - EDMA3_RM_Result result; + - unsigned int dmaChId; + - unsigned int qdmaChId; + - unsigned int paRAMId; + - unsigned int tcc; + - EDMA3_RM_QdmaTrigWord trigword; + - EDMA3_RM_TccCallback tccCb; + - void *cbData; + + - Use Case 1: Request specific DMA Channel, say EDMA Channel 5.\n\n + - dmaChId = 5;\n\n + - resObj.type = EDMA3_RM_RES_DMA_CHANNEL; + - resObj.resId = dmaChId; + - result = EDMA3_RM_allocResource(hRes, &resObj);\n\n + + - Use Case 2: Request any available DMA Channel.\n\n + - dmaChId = EDMA3_RM_RES_ANY;\n\n + - resObj.type = EDMA3_RM_RES_DMA_CHANNEL; + - resObj.resId = dmaChId; + - result = EDMA3_RM_allocResource(hRes, &resObj);\n\n + - dmaCh1Id = resObj.resId; \n\n + + - Use Case 3: Request a specific QDMA Channel, say QDMA Channel 0.\n\n + - qdmaChId = 0;\n\n + - resObj.type = EDMA3_RM_RES_QDMA_CHANNEL; + - resObj.resId = qdmaChId; + - result = EDMA3_RM_allocResource(hRes, &resObj);\n\n + + - Use Case 4: Request any available QDMA Channel.\n\n + - qdmaChId = EDMA3_RM_RES_ANY;\n\n + - resObj.type = EDMA3_RM_RES_QDMA_CHANNEL; + - resObj.resId = qdmaChId; + - result = EDMA3_RM_allocResource(hRes, &resObj);\n\n + - qdmaChId = resObj.resId;\n\n + + - Use Case 5: Request specific Parameter RAM Set, say 20.\n\n + - paRAMId = 20; \n\n + - resObj.type = EDMA3_RM_RES_PARAM_SET; + - resObj.resId = paRAMId; + - result = EDMA3_RM_allocResource(hRes, &resObj); \n\n + + - Use Case 6: Request any available Parameter RAM Set.\n\n + - paRAMId = EDMA3_RM_RES_ANY;\n\n + - resObj.type = EDMA3_RM_RES_PARAM_SET; + - resObj.resId = paRAMId; + - result = EDMA3_RM_allocResource(hRes, &resObj);\n\n + - paRAMId = resObj.resId; \n\n + + - Use Case 7: Request a specific TCC, say TCC 35. \n\n + - tcc = 35; \n\n + - resObj.type = EDMA3_RM_RES_TCC; + - resObj.resId = tcc; + - result = EDMA3_RM_allocResource(hRes, &resObj); \n\n + + - Use Case 8: Request any available TCC. \n\n + - tcc = EDMA3_RM_RES_ANY; \n\n + - resObj.type = EDMA3_RM_RES_TCC; + - resObj.resId = tcc; + - result = EDMA3_RM_allocResource(hRes, &resObj); \n\n + - tcc = resObj.resId; \n\n + + - Use Case 9: Free the already allocated DMA channel + - resObj.type = EDMA3_RM_RES_DMA_CHANNEL; + - resObj.resId = dmaChId; + - result = EDMA3_RM_freeResource(hRes, &resObj); \n\n + + - Use Case 10: Free the already allocated QDMA channel + - resObj.type = EDMA3_RM_RES_QDMA_CHANNEL; + - resObj.resId = qdmaChId; + - result = EDMA3_RM_freeResource(hRes, &resObj); \n\n + + - Use Case 11: Free the already allocated PaRAM Set + - resObj.type = EDMA3_RM_RES_PARAM_SET; + - resObj.resId = paRAMId; + - result = EDMA3_RM_freeResource(hRes, &resObj); \n\n + + - Use Case 12: Free the already allocated TCC + - resObj.type = EDMA3_RM_RES_TCC; + - resObj.resId = tcc; + - result = EDMA3_RM_freeResource(hRes, &resObj); \n\n + + - Use Case 13: Bind DMA Channel and a PaRAM Set + - result = EDMA3_RM_mapEdmaChannel (hRes,dmaChId,paRAMId); \n\n + + - Use Case 14: Bind QDMA Channel and a PaRAM Set. Also, specify + the Trigger word for the QDMA channel. + - result = EDMA3_RM_mapQdmaChannel (hRes, qdmaChId, paRAMId, + trigword); \n\n + + - Use Case 15: Register a Callback function associated with a TCC \n\n + - result = EDMA3_RM_registerTccCb (hRes,tcc,tccCb,cbData); \n\n + + - Use Case 16: Unregister a Callback function associated with a TCC \n\n + - result = EDMA3_RM_unregisterTccCb (hRes,tcc); \n\n + + - Use Case 17: Allocate a logical (ANY) DMA channel. It will also + allocate PaRAM Set and TCC alongwitht a DMA channel. + - resObj.type = EDMA3_RM_RES_DMA_CHANNEL; + - resObj.resId = EDMA3_RM_DMA_CHANNEL_ANY; + - result = EDMA3_RM_allocLogicalChannel (hRes, &resObj, + paRAMId, tcc); + - dmaCh1Id = resObj.resId; \n\n + + - Use Case 18: Allocate a logical (ANY) QDMA channel. It will also + allocate PaRAM Set and TCC alongwitht a QDMA channel. + - resObj.type = EDMA3_RM_RES_QDMA_CHANNEL; + - resObj.resId = EDMA3_RM_QDMA_CHANNEL_ANY; + - result = EDMA3_RM_allocLogicalChannel (hRes, &resObj, + paRAMId, tcc); + - qdmaChId = resObj.resId;\n\n + + - Use Case 19: Allocate a Link channel. Link channel is nothing but a + PaRAM Set, used for Linking purpose specifically. The allocated + PaRAM Set is returned in the resObj.resId value. + - resObj.type = EDMA3_RM_RES_PARAM_SET; + - resObj.resId = EDMA3_RM_PARAM_ANY; + - result = EDMA3_RM_allocLogicalChannel (hRes, &resObj, + NULL, NULL); + + - Use Case 20: Free the previously allocated Link channel. It will free + the PaRAM Set used for linking. + - result = EDMA3_RM_freeLogicalChannel (hRes, &resObj); + + - Use Case 21: Free the previously allocated logical DMA channel. It + will also free the associated PaRAM Set and TCC. + - resObj.type = EDMA3_RM_RES_DMA_CHANNEL; + - resObj.resId = dmaCh1Id; + - result = EDMA3_RM_freeLogicalChannel (hRes, &resObj); + + - Use Case 22: Free the previously allocated logical QDMA channel. It + will also free the associated PaRAM Set and TCC. + - resObj.type = EDMA3_RM_RES_QDMA_CHANNEL; + - resObj.resId = qdmaChId; + - result = EDMA3_RM_freeLogicalChannel (hRes, &resObj); + + + -# Close Resource Manager Instance + - Steps + - EDMA3_RM_Result edma3Result = EDMA3_RM_SOK; + + - Unregister Interrupt Handlers first, if previously registered. + - Delete the semaphore created during RM Instance Opening. + - edma3Result = edma3OsSemDelete (rmSemHandle); + - Close the EDMA3 RM Instance + - edma3Result = EDMA3_RM_close (hRes, NULL); + + + -# Delete Resource Manager Object + - Steps + - EDMA3_RM_Result edma3Result = EDMA3_RM_SOK; + - unsigned int edmaInstanceId = 0; + + - edma3Result = EDMA3_RM_delete (edmaInstanceId, NULL); + +*/ + +/* @} Edma3RMUsage */ + +/*---------------------------------------------------------------------------*/ +/*------------------Usage Guidelines End-------------------------------------*/ +/*---------------------------------------------------------------------------*/ + + +/** + * \defgroup Edma3RMErrCode Error Codes + * + * Error Codes returned by the EDMA3 Resource Manager Layer + * + * @{ + */ + +/** Resource Manager Error Codes base define */ +#define EDMA3_RM_E_BASE (-155) + +/** + * Resource Manager Object Not Deleted yet. + * So the object cannot be created. + */ +#define EDMA3_RM_E_OBJ_NOT_DELETED (EDMA3_RM_E_BASE) + +/** + * Resource Manager Object Not Closed yet. + * So the object cannot be deleted. + */ +#define EDMA3_RM_E_OBJ_NOT_CLOSED (EDMA3_RM_E_BASE-1) + +/** + * Resource Manager Object Not Opened yet + * So the object cannot be closed. + */ +#define EDMA3_RM_E_OBJ_NOT_OPENED (EDMA3_RM_E_BASE-2) + +/** Invalid Parameter passed to API */ +#define EDMA3_RM_E_INVALID_PARAM (EDMA3_RM_E_BASE-3) + +/** Resource requested for freeing is already free */ +#define EDMA3_RM_E_RES_ALREADY_FREE (EDMA3_RM_E_BASE-4) + +/** Resource requested for allocation/freeing is not owned */ +#define EDMA3_RM_E_RES_NOT_OWNED (EDMA3_RM_E_BASE-5) + +/** Resource is not available */ +#define EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE (EDMA3_RM_E_BASE-6) + +/** No Resource of specified type is available */ +#define EDMA3_RM_E_ALL_RES_NOT_AVAILABLE (EDMA3_RM_E_BASE-7) + +/** Invalid State of EDMA3 RM Obj */ +#define EDMA3_RM_E_INVALID_STATE (EDMA3_RM_E_BASE-8) + +/** Maximum no of Res Mgr Instances already Opened */ +#define EDMA3_RM_E_MAX_RM_INST_OPENED (EDMA3_RM_E_BASE-9) + +/** + * More than one Res Mgr Master Instance NOT supported. + * Only 1 master can exist. + */ +#define EDMA3_RM_E_RM_MASTER_ALREADY_EXISTS (EDMA3_RM_E_BASE-10) + +/** Callback function already registered. */ +#define EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED (EDMA3_RM_E_BASE-11) + +/** Semaphore related error */ +#define EDMA3_RM_E_SEMAPHORE (EDMA3_RM_E_BASE-12) + +/** Hardware feature NOT supported */ +#define EDMA3_RM_E_FEATURE_UNSUPPORTED (EDMA3_RM_E_BASE-13) + +/** EDMA3 Resource NOT allocated */ +#define EDMA3_RM_E_RES_NOT_ALLOCATED (EDMA3_RM_E_BASE-14) + +/* @} Edma3RMErrCode */ + + + + +/**\typedef EDMA3_RM_RegionId + * \brief EDMA3 Region Id + * + * Use this to assign channels/PaRAM sets/TCCs to a particular Region. + */ +typedef unsigned int EDMA3_RM_RegionId; + +/**\typedef EDMA3_RM_EventQueue + * \brief EDMA3 Event Queue assignment + * + * There can be 8 Event Queues. Either of them can be assigned + * to a DMA/QDMA channel using this. + * + */ +typedef unsigned int EDMA3_RM_EventQueue; + + + +/**\struct EDMA3_RM_GblConfigParams + * \brief Init-time Configuration structure for EDMA3 + * controller, to provide Global SoC specific Information. + * + * This configuration structure is used to specify the EDMA3 Resource Manager + * global settings, specific to the SoC. For e.g. number of DMA/QDMA channels, + * number of PaRAM sets, TCCs, event queues, transfer controllers, base + * addresses of CC global registers and TC registers, interrupt number for + * EDMA3 transfer completion, CC error, event queues' priority, watermark + * threshold level etc. + * This configuration information is SoC specific and could be provided by the + * user at run-time while creating the EDMA3 RM Object, using API + * EDMA3_RM_create. In case user doesn't provide it, this information could be + * taken from the SoC specific configuration file edma3__cfg.c, in + * case it is available. + */ +typedef struct { + /** Number of DMA Channels supported by the underlying EDMA3 Controller. */ + unsigned int numDmaChannels; + + /** Number of QDMA Channels supported by the underlying EDMA3 Controller */ + unsigned int numQdmaChannels; + + /** + * Number of Interrupt Channels supported by the underlying EDMA3 + * Controller + */ + unsigned int numTccs; + + /** Number of PaRAM Sets supported by the underlying EDMA3 Controller */ + unsigned int numPaRAMSets; + + /** Number of Event Queues in the underlying EDMA3 Controller */ + unsigned int numEvtQueue; + + /** + * Number of Transfer Controllers (TCs) in the underlying EDMA3 Controller + */ + unsigned int numTcs; + + /** Number of Regions in the underlying EDMA3 Controller */ + unsigned int numRegions; + + /** + * \brief Channel mapping existence + * + * A value of 0 (No channel mapping) implies that there is fixed + * association between a DMA channel and a PaRAM Set or, in other words, + * DMA channel n can ONLY use PaRAM Set n (No availability of DCHMAP + * registers) for transfers to happen. + * + * A value of 1 implies the presence of DCHMAP registers for the DMA + * channels and hence the flexibility of associating any DMA channel to + * any PaRAM Set. In other words, ANY PaRAM Set can be used for ANY DMA + * channel (like QDMA Channels). + */ + unsigned short dmaChPaRAMMapExists; + + /** Existence of memory protection feature */ + unsigned short memProtectionExists; + + /** Base address of EDMA3 CC memory mapped registers. */ + void *globalRegs; + + /** Base address of EDMA3 TCs memory mapped registers. */ + void *tcRegs[EDMA3_MAX_TC]; + + /** + * EDMA3 transfer completion interrupt line (could be different for ARM + * and DSP) + */ + unsigned int xferCompleteInt; + + /** EDMA3 CC error interrupt line (could be different for ARM and DSP) */ + unsigned int ccError; + + /** EDMA3 TCs error interrupt line (could be different for ARM and DSP) */ + unsigned int tcError[EDMA3_MAX_TC]; + + /** + * \brief EDMA3 TC priority setting + * + * User can program the priority of the Event Queues + * at a system-wide level. This means that the user can set the + * priority of an IO initiated by either of the TCs (Transfer Controllers) + * relative to IO initiated by the other bus masters on the + * device (ARM, DSP, USB, etc) + */ + unsigned int evtQPri [EDMA3_MAX_EVT_QUE]; + + /** + * \brief Event Queues Watermark Levels + + * To Configure the Threshold level of number of events + * that can be queued up in the Event queues. EDMA3CC error register + * (CCERR) will indicate whether or not at any instant of time the + * number of events queued up in any of the event queues exceeds + * or equals the threshold/watermark value that is set + * in the queue watermark threshold register (QWMTHRA). + */ + unsigned int evtQueueWaterMarkLvl [EDMA3_MAX_EVT_QUE]; + + /** + * \brief Default Burst Size (DBS) of TCs. + + * An optimally-sized command is defined by the transfer controller + * default burst size (DBS). Different TCs can have different + * DBS values. It is defined in Bytes. + */ + unsigned int tcDefaultBurstSize[EDMA3_MAX_TC]; + + /** + * \brief Mapping from DMA channels to PaRAM Sets + + * If channel mapping exists (DCHMAP registers are present), this array + * stores the respective PaRAM Set for each DMA channel. User can + * initialize each array member with a specific PaRAM Set or with + * EDMA3_DRV_CH_NO_PARAM_MAP. + * If channel mapping doesn't exist, it is of no use as the EDMA3 RM + * automatically uses the right PaRAM Set for that DMA channel. + * Useful only if mapping exists, otherwise of no use. + */ + unsigned int dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH]; + + /** + * \brief Mapping from DMA channels to TCCs + * + * This array stores the respective TCC (interrupt channel) for each + * DMA channel. User can initialize each array member with a specific TCC + * or with EDMA3_DRV_CH_NO_TCC_MAP. This specific + * TCC code will be returned when the transfer is completed + * on the mapped DMA channel. + */ + unsigned int dmaChannelTccMap [EDMA3_MAX_DMA_CH]; + + /** + * \brief Mapping from DMA channels to Hardware Events + * + * Each bit in this array corresponds to one DMA channel and tells whether + * this DMA channel is tied to any peripheral. That is whether any + * peripheral can send the synch event on this DMA channel or not. + * 1 means the channel is tied to some peripheral; 0 means it is not. + * DMA channels which are tied to some peripheral are RESERVED for that + * peripheral only. They are not allocated when user asks for 'ANY' DMA + * channel. + * All channels need not be mapped, some can be free also. + */ + unsigned int dmaChannelHwEvtMap [EDMA3_MAX_DMA_CHAN_DWRDS]; + } EDMA3_RM_GblConfigParams; + + + +/**\struct EDMA3_RM_InstanceInitConfig + * \brief Init-time Region Specific Configuration structure for + * EDMA3 RM, to provide region specific Information. + * + * This configuration structure is used to specify which EDMA3 resources are + * owned and reserved by the EDMA3 RM instance. This configuration + * structure is shadow region specific and will be provided by the user at + * run-time while calling EDMA3_RM_open (). + * + * Owned resources: + * **************** + * + * EDMA3 RM Instances are tied to different shadow regions and hence different + * masters. Regions could be: + * + * a) ARM, + * b) DSP, + * c) IMCOP (Imaging Co-processor) etc. + * + * User can assign each EDMA3 resource to a shadow region using this structure. + * In this way, user specifies which resources are owned by the specific EDMA3 + * RM Instance. + * This assignment should also ensure that the same resource is not assigned + * to more than one shadow regions (unless desired in that way). Any assignment + * not following the above mentioned approach may have catastrophic + * consequences. + * + * + * Reserved resources: + * ******************* + * + * During EDMA3 RM initialization, user can reserve some of the EDMA3 resources + * for future use, by specifying which resources to reserve in the configuration + * data structure. These (critical) resources are reserved in advance so that + * they should not be allocated to someone else and thus could be used in + * future for some specific purpose. + * + * User can request different EDMA3 resources using two methods: + * a) By passing the resource type and the actual resource id, + * b) By passing the resource type and ANY as resource id + * + * For e.g. to request DMA channel 31, user will pass 31 as the resource id. + * But to request ANY available DMA channel (mainly used for memory-to-memory + * data transfer operations), user will pass EDMA3_DRV_DMA_CHANNEL_ANY as the + * resource id. + * + * During initialization, user may have reserved some of the DMA channels for + * some specific purpose (mainly for peripherals using EDMA). These reserved + * DMA channels then will not be returned when user requests ANY as the + * resource id. + * + * Same logic applies for QDMA channels and TCCs. + * + * For PaRAM Set, there is one difference. If the DMA channels are one-to-one + * tied to their respective PaRAM Sets (i.e. user cannot 'choose' the PaRAM Set + * for a particular DMA channel), EDMA3 RM automatically reserves all those + * PaRAM Sets which are tied to the DMA channels. Then those PaRAM Sets would + * not be returned when user requests for ANY PaRAM Set (specifically for + * linking purpose). This is done in order to avoid allocating the PaRAM Set, + * tied to a particular DMA channel, for linking purpose. If this constraint is + * not there, that DMA channel thus could not be used at all, because of the + * unavailability of the desired PaRAM Set. + */ +typedef struct +{ + /** PaRAM Sets owned by the EDMA3 RM Instance. */ + unsigned int ownPaRAMSets[EDMA3_MAX_PARAM_DWRDS]; + + /** DMA Channels owned by the EDMA3 RM Instance. */ + unsigned int ownDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS]; + + /** QDMA Channels owned by the EDMA3 RM Instance. */ + unsigned int ownQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS]; + + /** TCCs owned by the EDMA3 RM Instance. */ + unsigned int ownTccs[EDMA3_MAX_TCC_DWRDS]; + + /** + * \brief Reserved PaRAM Sets + * + * PaRAM Sets reserved during initialization for future use. These will not + * be given when user requests for ANY available PaRAM Set using + * 'EDMA3_RM_PARAM_ANY' as resource/channel id. + */ + unsigned int resvdPaRAMSets[EDMA3_MAX_PARAM_DWRDS]; + + /** + * \brief Reserved DMA channels + * + * DMA channels reserved during initialization for future use. These will + * not be given when user requests for ANY available DMA channel using + * 'EDMA3_RM_DMA_CHANNEL_ANY' as resource/channel id. + */ + unsigned int resvdDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS]; + + /** + * \brief Reserved QDMA channels + * + * QDMA channels reserved during initialization for future use. These will + * not be given when user requests for ANY available QDMA channel using + * 'EDMA3_RM_QDMA_CHANNEL_ANY' as resource/channel id. + */ + unsigned int resvdQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS]; + + /** + * \brief Reserved TCCs + * + * TCCs reserved during initialization for future use. These will not + * be given when user requests for ANY available TCC using + * 'EDMA3_RM_TCC_ANY' as resource/channel id. + */ + unsigned int resvdTccs[EDMA3_MAX_TCC_DWRDS]; +}EDMA3_RM_InstanceInitConfig; + + + +/**\struct EDMA3_RM_Param + * \brief Used to Initialize the Resource Manager Instance + * + * This configuration structure is used to initialize the EDMA3 RM Instance. + * This configuration information is passed while opening the RM instance. + */ +typedef struct { + /** Shadow Region Identification */ + EDMA3_RM_RegionId regionId; + + /** + * It tells whether the EDMA3 RM instance is Master or not. Only the shadow + * region associated with this master instance will receive the EDMA3 + * interrupts (if enabled). + */ + unsigned short isMaster; + + /** + * EDMA3 resources related shadow region specific information. Which all + * EDMA3 resources are owned and reserved by this particular instance are + * told in this configuration structure. + * User can also pass this structure as NULL. In that case, default static + * configuration would be taken from the platform specific configuration + * files (part of the Resource Manager), if available. + */ + EDMA3_RM_InstanceInitConfig *rmInstInitConfig; + + /** + * EDMA3 RM Instance specific semaphore handle. + * Used to share resources (DMA/QDMA channels, PaRAM Sets, TCCs etc) + * among different users. + */ + void *rmSemHandle; + + /** + * Whether initialization of Region Specific Registers is required or not? + */ + unsigned short regionInitEnable; + + /** Instance wide Global Error callback parameters */ + EDMA3_RM_GblErrCallbackParams gblerrCbParams; +} EDMA3_RM_Param; + + + +/**\struct EDMA3_RM_MiscParam + * \brief Used to specify the miscellaneous options during Resource + * Manager Initialization. + * + * This configuration structure is used to specify some misc options + * while creating the RM Object. New options may also be added into this + * structure in future. + */ +typedef struct { + /** + * In a multi-master system (for e.g. ARM + DSP), this option is used to + * distinguish between Master and Slave. Only the Master is allowed to + * program the global EDMA3 registers (like Queue priority, Queue water- + * mark level, error registers etc). + */ + unsigned short isSlave; + + /** For future use **/ + unsigned short param; +}EDMA3_RM_MiscParam; + + + + +/**\fn EDMA3_RM_Result EDMA3_RM_create (unsigned int phyCtrllerInstId, + * const EDMA3_RM_GblConfigParams *gblCfgParams, + * const void *param) + * \brief Create EDMA3 Resource Manager Object + * + * This API is used to create the EDMA3 Resource Manager Object. It should be + * called only ONCE for each EDMA3 hardware instance. + * + * Init-time Configuration structure for EDMA3 hardware is provided to pass the + * SoC specific information. This configuration information could be provided + * by the user at init-time. In case user doesn't provide it, this information + * could be taken from the SoC specific configuration file + * edma3__cfg.c, in case it is available. + * + * This API clears the error specific registers (EMCR/EMCRh, QEMCR, CCERRCLR) + * and sets the TCs priorities and Event Queues' watermark levels, if the 'miscParam' + * argument is NULL. User can avoid these registers' programming (in some specific + * use cases) by SETTING the 'isSlave' field of 'EDMA3_RM_MiscParam' configuration + * structure and passing this structure as the third argument (miscParam). + * + * After successful completion of this API, Resource Manager Object's state + * changes to EDMA3_RM_CREATED from EDMA3_RM_DELETED. + * + * \param phyCtrllerInstId [IN] EDMA3 Controller Instance Id + * (Hardware instance id, starting from 0). + * \param gblCfgParams [IN] SoC specific configuration structure for the + * EDMA3 Hardware. + * \param miscParam [IN] Misc configuration options provided in the + * structure 'EDMA3_RM_MiscParam'. + * For default options, user can pass NULL + * in this argument. + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + */ +EDMA3_RM_Result EDMA3_RM_create (unsigned int phyCtrllerInstId, + const EDMA3_RM_GblConfigParams *gblCfgParams, + const void *miscParam); + + +/**\fn EDMA3_RM_Result EDMA3_RM_delete (unsigned int phyCtrllerInstId, + * const void *param) + * \brief Delete EDMA3 Resource Manager Object + * + * This API is used to delete the EDMA3 RM Object. It should be called + * once for each EDMA3 hardware instance, ONLY after closing all the + * previously opened EDMA3 RM Instances. + * + * After successful completion of this API, Resource Manager Object's state + * changes to EDMA3_RM_DELETED. + * + * \param phyCtrllerInstId [IN] EDMA3 Phy Controller Instance Id (Hardware + * instance id, starting from 0). + * \param param [IN] For possible future use. + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + */ +EDMA3_RM_Result EDMA3_RM_delete (unsigned int phyCtrllerInstId, + const void *param); + + + +/**\fn EDMA3_RM_Handle EDMA3_RM_open (unsigned int phyCtrllerInstId, + * const EDMA3_RM_Param *initParam, + * EDMA3_RM_Result *errorCode) + * \brief Open EDMA3 Resource Manager Instance + * + * This API is used to open an EDMA3 Resource Manager Instance. It could be + * called multiple times, for each possible EDMA3 shadow region. Maximum + * EDMA3_MAX_RM_INSTANCES instances are allowed for each EDMA3 hardware + * instance. + * + * Also, only ONE Master Resource Manager Instance is permitted. This master + * instance (and hence the region to which it belongs) will only receive the + * EDMA3 interrupts, if enabled. + * + * User could pass the instance specific configuration structure + * (initParam->rmInstInitConfig) as a part of the 'initParam' structure, + * during init-time. In case user doesn't provide it, this information could + * be taken from the SoC specific configuration file edma3__cfg.c, + * in case it is available. + * + * By default, this Resource Manager instance will clear the PaRAM Sets while + * allocating them. To change the default behavior, user should use the IOCTL + * interface appropriately. + * + * \param phyCtrllerInstId [IN] EDMA3 Controller Instance Id (Hardware + * instance id, starting from 0). + * \param initParam [IN] Used to Initialize the Resource Manager + * Instance (Master or Slave). + * \param errorCode [OUT] Error code while opening RM instance. + * + * \return Handle to the opened Resource Manager instance Or NULL in case of + * error. + * + * \note This function disables the global interrupts (by calling API + * edma3OsProtectEntry with protection level + * EDMA3_OS_PROTECT_INTERRUPT) while modifying the global RM data + * structures, to make it re-entrant. + */ +EDMA3_RM_Handle EDMA3_RM_open (unsigned int phyCtrllerInstId, + const EDMA3_RM_Param *initParam, + EDMA3_RM_Result *errorCode); + + + +/**\fn EDMA3_RM_Result EDMA3_RM_close (EDMA3_RM_Handle hEdmaResMgr, + * const void *param) + * \brief Close EDMA3 Resource Manager Instance + * + * This API is used to close a previously opened EDMA3 RM Instance. + * + * \param hEdmaResMgr [IN] Handle to the previously opened Resource + * Manager Instance. + * \param param [IN] For possible future use. + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + * + * \note This function disables the global interrupts (by calling API + * edma3OsProtectEntry with protection level + * EDMA3_OS_PROTECT_INTERRUPT) while modifying the global RM data + * structures, to make it re-entrant. + */ +EDMA3_RM_Result EDMA3_RM_close (EDMA3_RM_Handle hEdmaResMgr, + const void *param); + +/* @} Edma3RMBookkeep */ + + + + +/** + * \defgroup Edma3ResMgr EDMA3 Resources Management + * + * Resource Management part of the EDMA3 Resource Manager. + * + * @{ + */ + +/**\fn EDMA3_RM_Result EDMA3_RM_allocResource (EDMA3_RM_Handle hEdmaResMgr, + * EDMA3_RM_ResDesc *resObj) + * \brief This API is used to allocate specified EDMA3 Resources like + * DMA/QDMA channel, PaRAM Set or TCC. + * + * Note: To free the resources allocated by this API, user should call + * EDMA3_RM_freeResource () ONLY to de-allocate all the allocated resources. + * + * User can either request a specific resource by passing the resource id + * in 'resObj->resId' OR request ANY available resource of the type + * 'resObj->type'. + * + * ANY types of resources are those resources when user doesn't care about the + * actual resource allocated; user just wants a resource of the type specified. + * One use-case is to perform memory-to-memory data transfer operation. This + * operation can be performed using any available DMA or QDMA channel. + * User doesn't need any specific channel for the same. + * + * To allocate a specific resource, first this API checks whether that resource + * is OWNED by the Resource Manager instance. Then it checks the current + * availability of that resource. + * + * To allocate ANY available resource, this API tries to allocate a resource + * from the pool of (owned && non_reserved && available_right_now) resources. + * + * After allocating a DMA/QDMA channel or TCC, the same resource is enabled in + * the shadow region specific register (DRAE/DRAEH/QRAE). + * + * Allocated PaRAM Set is initialized to NULL before this API returns if user + * has requested for one. + * + * \param hEdmaResMgr [IN] Handle to the previously opened Resource + * Manager Instance. + * \param resObj [IN/OUT] Handle to the resource descriptor + * object, which needs to be allocated. + * In case user passes a specific resource + * Id, resObj value is left unchanged. + * In case user requests ANY available + * resource, the allocated resource id is + * returned in resObj. + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + * + * \note This function acquires a RM Instance specific semaphore + * to prevent simultaneous access to the global pool of resources. + * It is re-entrant, but should not be called from the user callback + * function (ISR context). + */ +EDMA3_RM_Result EDMA3_RM_allocResource (EDMA3_RM_Handle hEdmaResMgr, + EDMA3_RM_ResDesc *resObj); + + + +/**\fn EDMA3_RM_Result EDMA3_RM_freeResource(EDMA3_RM_Handle hEdmaResMgr, + * const EDMA3_RM_ResDesc *resObj) + * \brief This API is used to free previously allocated EDMA3 Resources like + * DMA/QDMA channel, PaRAM Set or TCC. + * + * To free a specific resource, first this API checks whether that resource is + * OWNED by the Resource Manager Instance. Then it checks whether that resource + * has been allocated by the Resource Manager instance or not. + * + * After freeing a DMA/QDMA channel or TCC, the same resource is disabled in + * the shadow region specific register (DRAE/DRAEH/QRAE). + * + * \param hEdmaResMgr [IN] Handle to the previously opened Resource + * Manager Instance. + * \param resObj [IN] Handle to the resource descriptor + * object, which needs to be freed. + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + * + * \note This function disables the global interrupts to prevent + * simultaneous access to the global pool of resources. + * It is re-entrant. + */ +EDMA3_RM_Result EDMA3_RM_freeResource(EDMA3_RM_Handle hEdmaResMgr, + const EDMA3_RM_ResDesc *resObj); + + + +/**\fn EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle + * hEdmaResMgr, EDMA3_RM_ResDesc *firstResIdObj, + * unsigned int numResources) + * \brief Allocate a contiguous region of specified EDMA3 Resource + * like DMA channel, QDMA channel, PaRAM Set or TCC. + * + * This API is used to allocate a contiguous region of specified EDMA3 + * Resources like DMA channel, QDMA channel, PaRAM Set or TCC. + * + * User can specify a particular resource Id to start with and go up to the + * number of resources requested. The specific resource id to start from could + * be passed in 'firstResIdObject->resId' and the number of resources requested + * in 'numResources'. + * + * User can also request ANY available resource(s) of the type + * 'firstResIdObject->type' by specifying 'firstResIdObject->resId' as + * EDMA3_RM_RES_ANY. + * + * ANY types of resources are those resources when user doesn't care about the + * actual resource allocated; user just wants a resource of the type specified. + * One use-case is to perform memory-to-memory data transfer operation. This + * operation can be performed using any available DMA or QDMA channel. User + * doesn't need any specific channel for the same. + * + * To allocate specific contiguous resources, first this API checks whether + * those requested resources are OWNED by the Resource Manager instance. Then + * it checks the current availability of those resources. + * + * To allocate ANY available contiguous resources, this API tries to allocate + * resources from the pool of (owned && non_reserved && available_right_now) + * resources. + * + * After allocating DMA/QDMA channels or TCCs, the same resources are enabled in + * the shadow region specific register (DRAE/DRAEH/QRAE). Allocated PaRAM Sets + * are initialized to NULL before this API returns. + * + * \param hEdmaResMgr [IN] Handle to the previously opened Resource + * Manager Instance. + * \param firstResIdObj [IN] Handle to the first resource descriptor + * object, which needs to be allocated. + * firstResIdObject->resId could be a valid + * resource id in case user wants to + * allocate specific resources OR it could + * be EDMA3_RM_RES_ANY in case user wants + * only the required number of resources + * and doesn't care about which resources + * were allocated. + * \param numResources [IN] Number of contiguous resources user + * wants to allocate. + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + * + * \note This function acquires a RM Instance specific semaphore + * to prevent simultaneous access to the global pool of resources. + * It is re-entrant, but should not be called from the user callback + * function (ISR context). + */ +EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr, + EDMA3_RM_ResDesc *firstResIdObj, + unsigned int numResources); + + + +/** + * \fn EDMA3_RM_Result EDMA3_RM_freeContiguousResource(EDMA3_RM_Handle + * hEdmaResMgr, EDMA3_RM_ResDesc *firstResIdObj, + * unsigned int numResources) + * \brief Free a contiguous region of specified EDMA3 Resource + * like DMA channel, QDMA channel, PaRAM Set or TCC, previously allocated. + * + * This API frees a contiguous region of specified EDMA3 Resources + * like DMA channel, QDMA channel, PaRAM Set or TCC, which have been previously + * allocated. In case of an error during the freeing of any specific resource, + * user can check the 'firstResIdObj' object to know the last resource id + * whose freeing has failed. In case of success, there is no need to check this + * object. + * + * \param hEdmaResMgr [IN] Handle to the previously opened + * Resource Manager Instance. + * \param firstResIdObj [IN/OUT] Handle to the first resource + * descriptor object, which needs to be + * freed. In case of an error while + * freeing any particular resource, + * the last resource id whose freeing has + * failed is returned in this resource + * descriptor object. + * \param numResources [IN] Number of contiguous resources allocated + * previously which user wants to release + * + * \note This is a re-entrant function which internally calls + * EDMA3_RM_freeResource() for resource de-allocation. + */ +EDMA3_RM_Result EDMA3_RM_freeContiguousResource(EDMA3_RM_Handle hEdmaResMgr, + EDMA3_RM_ResDesc *firstResIdObj, + unsigned int numResources); + + + + +/* Defines for Logical Channel Values */ +/*---------------------------------------------------------------------------*/ +/** + * Used to specify any available DMA Channel while requesting + * one. Used in the API EDMA3_RM_allocLogicalChannel (). + * DMA channel from the pool of (owned && non_reserved && available_right_now) + * DMA channels will be chosen and returned. + */ +#define EDMA3_RM_DMA_CHANNEL_ANY (1011u) + +/** + * Used to specify any available QDMA Channel while requesting + * one. Used in the API EDMA3_RM_allocLogicalChannel(). + * QDMA channel from the pool of (owned && non_reserved && available_right_now) + * QDMA channels will be chosen and returned. + */ +#define EDMA3_RM_QDMA_CHANNEL_ANY (1012u) + +/** + * Used to specify any available TCC while requesting + * one. Used in the API EDMA3_RM_allocLogicalChannel(), for + * both DMA and QDMA channels. + * TCC from the pool of (owned && non_reserved && available_right_now) + * TCCs will be chosen and returned. + */ +#define EDMA3_RM_TCC_ANY (1013u) + +/** + * Used to specify any available PaRAM Set while requesting + * one. Used in the API EDMA3_RM_allocLogicalChannel(), for + * both DMA/QDMA and Link channels. + * PaRAM Set from the pool of (owned && non_reserved && available_right_now) + * PaRAM Sets will be chosen and returned. + */ +#define EDMA3_RM_PARAM_ANY (1014u) + +/** + * This define is used to specify that a DMA channel is NOT tied to any PaRAM + * Set and hence any available PaRAM Set could be used for that DMA channel. + * It could be used in dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH], in global + * configuration structure EDMA3_RM_GblConfigParams. + * + * This value should mandatorily be used to mark DMA channels with no initial + * mapping to specific PaRAM Sets. + */ +#define EDMA3_RM_CH_NO_PARAM_MAP (1015u) + +/** + * This define is used to specify that the DMA/QDMA channel is not tied to any + * TCC and hence any available TCC could be used for that DMA/QDMA channel. + * It could be used in dmaChannelTccMap [EDMA3_MAX_DMA_CH], in global + * configuration structure EDMA3_RM_GblConfigParams. + * + * This value should mandatorily be used to mark DMA channels with no initial + * mapping to specific TCCs. + */ +#define EDMA3_RM_CH_NO_TCC_MAP (1016u) + +/*---------------------------------------------------------------------------*/ + +/** + * \brief DMA Channels assigned to different Hardware Events. + * They should be used while requesting a specific DMA channel. + * One possible usage is to maintain a SoC specific file, which will + * contain the mapping of these hardware events to the respective + * peripherals for better understanding and lesser probability of + * errors. Also, if any event associated with a particular peripheral + * gets changed, only that SoC specific file needs to be changed. + * + * for eg, the sample SoC specific file "soc.h" can have these defines: + * + * #define EDMA3_RM_HW_CHANNEL_MCBSP_TX EDMA3_RM_HW_CHANNEL_EVENT_2 + * #define EDMA3_RM_HW_CHANNEL_MCBSP_RX EDMA3_RM_HW_CHANNEL_EVENT_3 + * + * These defines will be used by the MCBSP driver. The same event + * EDMA3_RM_HW_CHANNEL_EVENT_2/3 could be mapped to some other + * peripheral also. + */ +typedef enum +{ + /** Channel assigned to EDMA3 Event 0 */ + EDMA3_RM_HW_CHANNEL_EVENT_0 = 0, + /** Channel assigned to EDMA3 Event 1 */ + EDMA3_RM_HW_CHANNEL_EVENT_1, + /** Channel assigned to EDMA3 Event 2 */ + EDMA3_RM_HW_CHANNEL_EVENT_2, + /** Channel assigned to EDMA3 Event 3 */ + EDMA3_RM_HW_CHANNEL_EVENT_3, + /** Channel assigned to EDMA3 Event 4 */ + EDMA3_RM_HW_CHANNEL_EVENT_4, + /** Channel assigned to EDMA3 Event 5 */ + EDMA3_RM_HW_CHANNEL_EVENT_5, + /** Channel assigned to EDMA3 Event 6 */ + EDMA3_RM_HW_CHANNEL_EVENT_6, + /** Channel assigned to EDMA3 Event 7 */ + EDMA3_RM_HW_CHANNEL_EVENT_7, + /** Channel assigned to EDMA3 Event 8 */ + EDMA3_RM_HW_CHANNEL_EVENT_8, + /** Channel assigned to EDMA3 Event 9 */ + EDMA3_RM_HW_CHANNEL_EVENT_9, + /** Channel assigned to EDMA3 Event 10 */ + EDMA3_RM_HW_CHANNEL_EVENT_10, + /** Channel assigned to EDMA3 Event 11 */ + EDMA3_RM_HW_CHANNEL_EVENT_11, + /** Channel assigned to EDMA3 Event 12 */ + EDMA3_RM_HW_CHANNEL_EVENT_12, + /** Channel assigned to EDMA3 Event 13 */ + EDMA3_RM_HW_CHANNEL_EVENT_13, + /** Channel assigned to EDMA3 Event 14 */ + EDMA3_RM_HW_CHANNEL_EVENT_14, + /** Channel assigned to EDMA3 Event 15 */ + EDMA3_RM_HW_CHANNEL_EVENT_15, + /** Channel assigned to EDMA3 Event 16 */ + EDMA3_RM_HW_CHANNEL_EVENT_16, + /** Channel assigned to EDMA3 Event 17 */ + EDMA3_RM_HW_CHANNEL_EVENT_17, + /** Channel assigned to EDMA3 Event 18 */ + EDMA3_RM_HW_CHANNEL_EVENT_18, + /** Channel assigned to EDMA3 Event 19 */ + EDMA3_RM_HW_CHANNEL_EVENT_19, + /** Channel assigned to EDMA3 Event 20 */ + EDMA3_RM_HW_CHANNEL_EVENT_20, + /** Channel assigned to EDMA3 Event 21 */ + EDMA3_RM_HW_CHANNEL_EVENT_21, + /** Channel assigned to EDMA3 Event 22 */ + EDMA3_RM_HW_CHANNEL_EVENT_22, + /** Channel assigned to EDMA3 Event 23 */ + EDMA3_RM_HW_CHANNEL_EVENT_23, + /** Channel assigned to EDMA3 Event 24 */ + EDMA3_RM_HW_CHANNEL_EVENT_24, + /** Channel assigned to EDMA3 Event 25 */ + EDMA3_RM_HW_CHANNEL_EVENT_25, + /** Channel assigned to EDMA3 Event 26 */ + EDMA3_RM_HW_CHANNEL_EVENT_26, + /** Channel assigned to EDMA3 Event 27 */ + EDMA3_RM_HW_CHANNEL_EVENT_27, + /** Channel assigned to EDMA3 Event 28 */ + EDMA3_RM_HW_CHANNEL_EVENT_28, + /** Channel assigned to EDMA3 Event 29 */ + EDMA3_RM_HW_CHANNEL_EVENT_29, + /** Channel assigned to EDMA3 Event 30 */ + EDMA3_RM_HW_CHANNEL_EVENT_30, + /** Channel assigned to EDMA3 Event 31 */ + EDMA3_RM_HW_CHANNEL_EVENT_31, + /** Channel assigned to EDMA3 Event 32 */ + EDMA3_RM_HW_CHANNEL_EVENT_32, + /** Channel assigned to EDMA3 Event 33 */ + EDMA3_RM_HW_CHANNEL_EVENT_33, + /** Channel assigned to EDMA3 Event 34 */ + EDMA3_RM_HW_CHANNEL_EVENT_34, + /** Channel assigned to EDMA3 Event 35 */ + EDMA3_RM_HW_CHANNEL_EVENT_35, + /** Channel assigned to EDMA3 Event 36 */ + EDMA3_RM_HW_CHANNEL_EVENT_36, + /** Channel assigned to EDMA3 Event 37 */ + EDMA3_RM_HW_CHANNEL_EVENT_37, + /** Channel assigned to EDMA3 Event 38 */ + EDMA3_RM_HW_CHANNEL_EVENT_38, + /** Channel assigned to EDMA3 Event 39 */ + EDMA3_RM_HW_CHANNEL_EVENT_39, + /** Channel assigned to EDMA3 Event 40 */ + EDMA3_RM_HW_CHANNEL_EVENT_40, + /** Channel assigned to EDMA3 Event 41 */ + EDMA3_RM_HW_CHANNEL_EVENT_41, + /** Channel assigned to EDMA3 Event 42 */ + EDMA3_RM_HW_CHANNEL_EVENT_42, + /** Channel assigned to EDMA3 Event 43 */ + EDMA3_RM_HW_CHANNEL_EVENT_43, + /** Channel assigned to EDMA3 Event 44 */ + EDMA3_RM_HW_CHANNEL_EVENT_44, + /** Channel assigned to EDMA3 Event 45 */ + EDMA3_RM_HW_CHANNEL_EVENT_45, + /** Channel assigned to EDMA3 Event 46 */ + EDMA3_RM_HW_CHANNEL_EVENT_46, + /** Channel assigned to EDMA3 Event 47 */ + EDMA3_RM_HW_CHANNEL_EVENT_47, + /** Channel assigned to EDMA3 Event 48 */ + EDMA3_RM_HW_CHANNEL_EVENT_48, + /** Channel assigned to EDMA3 Event 49 */ + EDMA3_RM_HW_CHANNEL_EVENT_49, + /** Channel assigned to EDMA3 Event 50 */ + EDMA3_RM_HW_CHANNEL_EVENT_50, + /** Channel assigned to EDMA3 Event 51 */ + EDMA3_RM_HW_CHANNEL_EVENT_51, + /** Channel assigned to EDMA3 Event 52 */ + EDMA3_RM_HW_CHANNEL_EVENT_52, + /** Channel assigned to EDMA3 Event 53 */ + EDMA3_RM_HW_CHANNEL_EVENT_53, + /** Channel assigned to EDMA3 Event 54 */ + EDMA3_RM_HW_CHANNEL_EVENT_54, + /** Channel assigned to EDMA3 Event 55 */ + EDMA3_RM_HW_CHANNEL_EVENT_55, + /** Channel assigned to EDMA3 Event 56 */ + EDMA3_RM_HW_CHANNEL_EVENT_56, + /** Channel assigned to EDMA3 Event 57 */ + EDMA3_RM_HW_CHANNEL_EVENT_57, + /** Channel assigned to EDMA3 Event 58 */ + EDMA3_RM_HW_CHANNEL_EVENT_58, + /** Channel assigned to EDMA3 Event 59 */ + EDMA3_RM_HW_CHANNEL_EVENT_59, + /** Channel assigned to EDMA3 Event 60 */ + EDMA3_RM_HW_CHANNEL_EVENT_60, + /** Channel assigned to EDMA3 Event 61 */ + EDMA3_RM_HW_CHANNEL_EVENT_61, + /** Channel assigned to EDMA3 Event 62 */ + EDMA3_RM_HW_CHANNEL_EVENT_62, + /** Channel assigned to EDMA3 Event 63 */ + EDMA3_RM_HW_CHANNEL_EVENT_63 +} EDMA3_RM_HW_CHANNEL_EVENT; + + + +/** + * \fn EDMA3_RM_Result EDMA3_RM_allocLogicalChannel(EDMA3_RM_Handle + * hEdmaResMgr, EDMA3_RM_ResDesc *lChObj, + * unsigned int *pParam, unsigned int *pTcc) + * \brief Request a DMA/QDMA/Link channel. + * + * This API is used to allocate a logical channel (DMA/QDMA/Link) along with + * the associated resources. For DMA and QDMA channels, TCC and PaRAM Set are + * also allocated along with the requested channel. For Link channel, ONLY a + * PaRAM Set is allocated. + * + * Note: To free the logical channel allocated by this API, user should call + * EDMA3_RM_freeLogicalChannel () ONLY to de-allocate all the allocated resources + * and remove certain mappings. + * + * User can request a specific logical channel by passing the channel id in + * 'lChObj->resId' and channel type in 'lChObj->type'. Note that the channel + * id is the same as the actual resource id. For e.g. in the case of QDMA + * channels, valid channel ids are from 0 to 7 only. + * + * User can also request ANY available logical channel of the type + * 'lChObj->type' by specifying 'lChObj->resId' as: + * a) EDMA3_RM_DMA_CHANNEL_ANY: For DMA channels + * b) EDMA3_RM_QDMA_CHANNEL_ANY: For QDMA channels, and + * c) EDMA3_RM_PARAM_ANY: For Link channels. Normally user should use this + * value to request link channels (PaRAM Sets used for linking purpose + * only), unless he wants to use some specific link channels (PaRAM Sets) + * which is also allowed. + * + * This API internally uses EDMA3_RM_allocResource () to allocate the desired + * resources (DMA/QDMA channel, PaRAM Set and TCC). + * + * For DMA/QDMA channels, after allocating all the EDMA3 resources, this API + * sets the TCC field of the OPT PaRAM Word with the allocated TCC. + * + * For DMA channel, it also sets the DCHMAP register, if required. + * + * For QDMA channel, it sets the QCHMAP register and CCNT as trigger word and + * enables the QDMA channel by writing to the QEESR register. + * + * \param hEdmaResMgr [IN] Handle to the previously opened Resource + * Manager Instance. + * \param lChObj [IN/OUT] Handle to the requested logical channel + * object, which needs to be allocated. + * It could be a specific logical channel + * or ANY available logical channel of the + * requested type. + * In case user passes a specific resource + * Id, lChObj value is left unchanged. In + * case user requests ANY available + * resource, the allocated resource id is + * returned in lChObj->resId. + * + * \param pParam [IN/OUT] PaRAM Set for a particular logical + * (DMA/QDMA) channel. Not used if user + * requested for a Link channel. + * In case user passes a specific PaRAM + * Set value, pParam value is left + * unchanged. In case user requests ANY + * available PaRAM Set by passing + * 'EDMA3_RM_PARAM_ANY' in pParam, + * the allocated one is returned in pParam. + * + * \param pTcc [IN/OUT] TCC for a particular logical (DMA/QDMA) + * channel. Not used if user requested for + * a Link channel. + * In case user passes a specific TCC + * value, pTcc value is left unchanged. + * In case user requests ANY + * available TCC by passing + * 'EDMA3_RM_TCC_ANY' in pTcc, + * the allocated one is returned in pTcc. + * + * \return EDMA3_RM_SOK or EDMA_RM Error Code + * + * \note This function internally calls EDMA3_RM_allocResource (), which + * acquires a RM Instance specific semaphore to prevent simultaneous + * access to the global pool of resources. It is re-entrant for unique + * logical channel values, but SHOULD NOT be called from the user + * callback function (ISR context). + */ +EDMA3_RM_Result EDMA3_RM_allocLogicalChannel(EDMA3_RM_Handle hEdmaResMgr, + EDMA3_RM_ResDesc *lChObj, + unsigned int *pParam, + unsigned int *pTcc); + + + +/** \fn EDMA3_RM_Result EDMA3_RM_freeLogicalChannel (EDMA3_RM_Handle + * hEdmaResMgr, EDMA3_RM_ResDesc *lChObj) + * \brief This API is used to free the specified channel (DMA/QDMA/Link) and + * its associated resources (PaRAM Set, TCC etc). + * + * This API internally uses EDMA3_RM_freeResource () to free the desired + * resources. + * + * For DMA/QDMA channels, it also clears the DCHMAP/QCHMAP registers + * + * \param hEdmaResMgr [IN] Handle to the previously opened Resource + * Manager Instance. + * \param lChObj [IN] Handle to the logical channel object, + * which needs to be freed + * + * \return EDMA3_RM_SOK or EDMA_RM Error Code + * + * \note This is a re-entrant function which internally calls + * EDMA3_RM_freeResource () for resource de-allocation. + */ +EDMA3_RM_Result EDMA3_RM_freeLogicalChannel (EDMA3_RM_Handle hEdmaResMgr, + EDMA3_RM_ResDesc *lChObj); + + + + +/**\struct EDMA3_RM_ParamentryRegs + * \brief EDMA3 PaRAM Set + * + * This is a mapping of the EDMA3 PaRAM set provided to the user + * for ease of modification of the individual PaRAM words. + * + * It could be used by the advanced users to program the PaRAM Set directly, + * without using any API. + */ +typedef struct { + /** OPT field of PaRAM Set */ + volatile unsigned int OPT; + + /** + * \brief Starting byte address of Source + * For FIFO mode, srcAddr must be a 256-bit aligned address. + */ + volatile unsigned int SRC; + + /** + * Number of bytes in each Array (ACNT) (16 bits) and + * Number of Arrays in each Frame (BCNT) (16 bits). + */ + volatile unsigned int A_B_CNT; + + /** + * \brief Starting byte address of destination + * For FIFO mode, destAddr must be a 256-bit aligned address. + * i.e. 5 LSBs should be 0. + */ + volatile unsigned int DST; + + /** + * Index between consec. arrays of a Source Frame (SRCBIDX) (16 bits) and + * Index between consec. arrays of a Destination Frame (DSTBIDX) (16 bits). + * + * If SAM is set to 1 (via channelOptions) then srcInterArrIndex should + * be an even multiple of 32 bytes. + * + * If DAM is set to 1 (via channelOptions) then destInterArrIndex should + * be an even multiple of 32 bytes + */ + volatile unsigned int SRC_DST_BIDX; + + /** + * \brief Address for linking (AutoReloading of a PaRAM Set) (16 bits) + * and Reload value of the numArrInFrame (BCNT) (16 bits). + * + * Link field must point to a valid aligned 32-byte PaRAM set + * A value of 0xFFFF means no linking. + * + * B count reload field is relevant only for A-sync transfers. + */ + volatile unsigned int LINK_BCNTRLD; + + /** + * \brief Index between consecutive frames of a Source Block (SRCCIDX) + * (16 bits) and Index between consecutive frames of a Dest Block + * (DSTCIDX) (16 bits). + */ + volatile unsigned int SRC_DST_CIDX; + + /** + * \brief Number of Frames in a block (CCNT) (16 bits). + */ + volatile unsigned int CCNT; +} EDMA3_RM_ParamentryRegs; + + + +/**\struct EDMA3_RM_PaRAMRegs + * \brief EDMA3 PaRAM Set in User Configurable format + * + * This is a mapping of the EDMA3 PaRAM set provided to the user + * for ease of modification of the individual fields. + */ +typedef struct { + /** OPT field of PaRAM Set */ + volatile unsigned int opt; + + /** + * \brief Starting byte address of Source + * For FIFO mode, srcAddr must be a 256-bit aligned address. + */ + volatile unsigned int srcAddr; + + /** + * \brief Number of bytes in each Array (ACNT) + */ + volatile unsigned short aCnt; + + /** + * \brief Number of Arrays in each Frame (BCNT) + */ + volatile unsigned short bCnt; + + /** + * \brief Starting byte address of destination + * For FIFO mode, destAddr must be a 256-bit aligned address. + * i.e. 5 LSBs should be 0. + */ + volatile unsigned int destAddr; + + /** + * \brief Index between consec. arrays of a Source Frame (SRCBIDX) + * If SAM is set to 1 (via channelOptions) then srcInterArrIndex should + * be an even multiple of 32 bytes. + */ + volatile short srcBIdx; + + /** + * \brief Index between consec. arrays of a Destination Frame (DSTBIDX) + * If DAM is set to 1 (via channelOptions) then destInterArrIndex should + * be an even multiple of 32 bytes + */ + volatile short destBIdx; + + /** + * \brief Address for linking (AutoReloading of a PaRAM Set) + * This must point to a valid aligned 32-byte PaRAM set + * A value of 0xFFFF means no linking + * Linking is especially useful for use with ping-pong buffers and + * circular buffers + */ + volatile unsigned short linkAddr; + + /** + * \brief Reload value of the numArrInFrame (BCNT) + * Relevant only for A-sync transfers + */ + volatile unsigned short bCntReload; + + /** + * \brief Index between consecutive frames of a Source Block (SRCCIDX) + */ + volatile short srcCIdx; + + /** + * \brief Index between consecutive frames of a Dest Block (DSTCIDX) + */ + volatile short destCIdx; + + /** + * \brief Number of Frames in a block (CCNT) + */ + volatile unsigned short cCnt; + +} EDMA3_RM_PaRAMRegs; + + + + +/**\enum EDMA3_RM_QdmaTrigWord + * \brief QDMA Trigger Word + * + * Use this enum to set the QDMA trigger word to any of the + * 8 DWords(unsigned int) within a Parameter RAM set + */ +typedef enum +{ + /** + * Set the OPT field (Offset Address 0h Bytes) + * as the QDMA trigger word + */ + EDMA3_RM_QDMA_TRIG_OPT = 0, + /** + * Set the SRC field (Offset Address 4h Bytes) + * as the QDMA trigger word + */ + EDMA3_RM_QDMA_TRIG_SRC = 1, + /** + * Set the (ACNT + BCNT) field (Offset Address 8h Bytes) + * as the QDMA trigger word + */ + EDMA3_RM_QDMA_TRIG_ACNT_BCNT = 2, + /** + * Set the DST field (Offset Address Ch Bytes) + * as the QDMA trigger word + */ + EDMA3_RM_QDMA_TRIG_DST = 3, + /** + * Set the (SRCBIDX + DSTBIDX) field (Offset Address 10h Bytes) + * as the QDMA trigger word + */ + EDMA3_RM_QDMA_TRIG_SRC_DST_BIDX = 4, + /** + * Set the (LINK + BCNTRLD) field (Offset Address 14h Bytes) + * as the QDMA trigger word + */ + EDMA3_RM_QDMA_TRIG_LINK_BCNTRLD = 5, + /** + * Set the (SRCCIDX + DSTCIDX) field (Offset Address 18h Bytes) + * as the QDMA trigger word + */ + EDMA3_RM_QDMA_TRIG_SRC_DST_CIDX = 6, + /** + * Set the (CCNT + RSVD) field (Offset Address 1Ch Bytes) + * as the QDMA trigger word + */ + EDMA3_RM_QDMA_TRIG_CCNT = 7, + /** Default Trigger Word */ + EDMA3_RM_QDMA_TRIG_DEFAULT = 7 +} EDMA3_RM_QdmaTrigWord; + + + +/**\enum EDMA3_RM_Cntrlr_PhyAddr + * \brief CC/TC Physical Address + * + * Use this enum to get the physical address of the Channel Controller or the + * Transfer Controller. The address returned could be used by the advanced + * usres to set/get some specific registers direclty. + */ +typedef enum +{ + /** Channel Controller Physical Address */ + EDMA3_RM_CC_PHY_ADDR = 0, + /** Transfer Controller 0 Physical Address */ + EDMA3_RM_TC0_PHY_ADDR, + /** Transfer Controller 1 Physical Address */ + EDMA3_RM_TC1_PHY_ADDR, + /** Transfer Controller 2 Physical Address */ + EDMA3_RM_TC2_PHY_ADDR, + /** Transfer Controller 3 Physical Address */ + EDMA3_RM_TC3_PHY_ADDR, + /** Transfer Controller 4 Physical Address */ + EDMA3_RM_TC4_PHY_ADDR, + /** Transfer Controller 5 Physical Address */ + EDMA3_RM_TC5_PHY_ADDR, + /** Transfer Controller 6 Physical Address */ + EDMA3_RM_TC6_PHY_ADDR, + /** Transfer Controller 7 Physical Address */ + EDMA3_RM_TC7_PHY_ADDR +}EDMA3_RM_Cntrlr_PhyAddr; + + + +/**\fn EDMA3_RM_Result EDMA3_RM_mapEdmaChannel (EDMA3_RM_Handle + * hEdmaResMgr, unsigned int channelId, unsigned int paRAMId) + * \brief Bind the resources DMA Channel and PaRAM Set. Both the DMA channel + * and the PaRAM set should be previously allocated. If they are not, + * this API will result in error. + * + * This API sets the DCHMAP register for a specific DMA channel. This register + * is used to specify the PaRAM Set associated with that particular DMA Channel. + * + * \param hEdmaResMgr [IN] Handle to the previously opened Resource + * Manager Instance. + * \param channelId [IN] Previously allocated DMA Channel on which + * Transfer will occur. + * \param paRAMId [IN] Previously allocated PaRAM Set which + * needs to be associated with the dma channel. + * + * \return EDMA3_RM_SOK or EDMA_RM Error Code + * + * \note This API is useful only for the EDMA3 Controllers which have a + * register for mapping a DMA Channel to a particular PaRAM Set + * (DCHMAP register). + * On platforms where this feature is not supported, this API + * returns error code: EDMA3_RM_E_FEATURE_UNSUPPORTED. + * This function is re-entrant for unique channelId. It is + * non-re-entrant for same channelId values. + */ +EDMA3_RM_Result EDMA3_RM_mapEdmaChannel (EDMA3_RM_Handle hEdmaResMgr, + unsigned int channelId, + unsigned int paRAMId); + + +/**\fn EDMA3_RM_Result EDMA3_RM_mapQdmaChannel (EDMA3_RM_Handle + * hEdmaResMgr, unsigned int channelId, + * unsigned int paRAMId, + * EDMA3_RM_QdmaTrigWord trigWord) + * \brief Bind the resources QDMA Channel and PaRAM Set. Also, Set the + * trigger word for the QDMA channel. Both the QDMA channel and the PaRAM set + * should be previously allocated. If they are not, this API will result in error. + * + * This API sets the QCHMAP register for a specific QDMA channel. This register + * is used to specify the PaRAM Set associated with that particular QDMA + * Channel along with the trigger word. + * + * \param hEdmaResMgr [IN] Handle to the previously opened Resource + * Manager Instance. + * \param channelId [IN] Previously allocated QDMA Channel on which + * Transfer will occur. + * \param paRAMId [IN] Previously allocated PaRAM Set, which needs to + * be associated with channelId + * \param trigWord [IN] The Trigger Word for the channel. + * Trigger Word is the word in the PaRAM + * Register Set which - when written to by CPU + * -will start the QDMA transfer automatically + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + * + * \note This function is re-entrant for unique channelId. It is non-re-entrant + * for same channelId values. + */ +EDMA3_RM_Result EDMA3_RM_mapQdmaChannel (EDMA3_RM_Handle hEdmaResMgr, + unsigned int channelId, + unsigned int paRAMId, + EDMA3_RM_QdmaTrigWord trigWord); + + + +/**\fn EDMA3_RM_Result EDMA3_RM_setCCRegister (EDMA3_RM_Handle hEdmaResMgr, + * unsigned int regOffset, + * unsigned int newRegValue) + * \brief Set the Channel Controller (CC) Register value + * + * \param hEdmaResMgr [IN] Handle to the previously opened Resource + * Manager Instance. + * \param regOffset [IN] CC Register offset whose value needs to be + * set. It should be word-aligned. + * \param newRegValue [IN] New CC Register Value + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + * + * \note This function is non re-entrant for users using the same + * Resource Manager handle. + * Before modifying a register, it tries to acquire a semaphore + * (RM instance specific), to protect simultaneous + * modification of the same register by two different users. + * After the successful change, it releases the semaphore. + * For users using different RM handles, this function is re-entrant. + */ +EDMA3_RM_Result EDMA3_RM_setCCRegister (EDMA3_RM_Handle hEdmaResMgr, + unsigned int regOffset, + unsigned int newRegValue); + + +/**\fn EDMA3_RM_Result EDMA3_RM_getCCRegister (EDMA3_RM_Handle hEdmaResMgr, + * unsigned int regOffset, + * unsigned int *regValue) + * \brief Get the Channel Controller (CC) Register value + * + * \param hEdmaResMgr [IN] Handle to the previously opened Resource + * Manager Instance. + * \param regOffset [IN] CC Register offset whose value is + * needed. It should be word-aligned. + * \param regValue [IN/OUT] Fetched CC Register Value + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + * + * \note This function is re-entrant. + */ +EDMA3_RM_Result EDMA3_RM_getCCRegister (EDMA3_RM_Handle hEdmaResMgr, + unsigned int regOffset, + unsigned int *regValue); + + + +/**\fn EDMA3_RM_Result EDMA3_RM_waitAndClearTcc (EDMA3_RM_Handle + * hEdmaResMgr, unsigned int tccNo) + * \brief Wait for a transfer completion interrupt to occur and clear it. + * + * This is a blocking function that returns when the IPR/IPRH bit corresponding + * to the tccNo specified, is SET. It clears the corresponding bit while + * returning also. + * + * This function waits for the specific bit indefinitely in a tight loop, with + * out any delay in between. USE IT CAUTIOUSLY. + * + * \param hEdmaResMgr [IN] Handle to the previously opened Resource + * Manager Instance. + * \param tccNo [IN] TCC, specific to which the function + * waits on a IPR/IPRH bit. + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + * + * \note This function is re-entrant for different tccNo. + * + */ +EDMA3_RM_Result EDMA3_RM_waitAndClearTcc (EDMA3_RM_Handle hEdmaResMgr, + unsigned int tccNo); + + + + +/**\fn EDMA3_RM_Result EDMA3_RM_checkAndClearTcc (EDMA3_RM_Handle + * hEdmaResMgr, unsigned int tccNo, + * unsigned short *tccStatus) + * \brief Returns the status of a previously initiated transfer. + * + * This is a non-blocking function that returns the status of a previously + * initiated transfer, based on the IPR/IPRH bit. This bit corresponds to + * the tccNo specified by the user. It clears the corresponding bit, if SET, + * while returning also. + * + * \param hEdmaResMgr [IN] Handle to the previously opened Resource + * Manager Instance. + * \param tccNo [IN] TCC, specific to which the function + * checks the status of the IPR/IPRH bit. + * \param tccStatus [IN/OUT] Status of the transfer is returned here. + * Returns "TRUE" if the transfer has + * completed (IPR/IPRH bit SET), + * "FALSE" if the transfer has not + * completed successfully (IPR/IPRH bit + * NOT SET). + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + * + * \note This function is re-entrant for different tccNo. + */ +EDMA3_RM_Result EDMA3_RM_checkAndClearTcc (EDMA3_RM_Handle hEdmaResMgr, + unsigned int tccNo, + unsigned short *tccStatus); + + + + +/**\fn EDMA3_RM_Result EDMA3_RM_setPaRAM (EDMA3_RM_Handle hEdmaResMgr, + * EDMA3_RM_ResDesc *lChObj, + * const EDMA3_RM_PaRAMRegs *newPaRAM) + * \brief Copy the user specified PaRAM Set onto the PaRAM Set + * associated with the logical channel (DMA/QDMA/Link). + * + * This API takes a PaRAM Set as input and copies it onto the actual PaRAM Set + * associated with the logical channel. OPT field of the PaRAM Set is written + * first and the CCNT field is written last. + * + * Caution: It should be used carefully when programming the QDMA channels whose + * trigger words are not CCNT field. + * + * \param hEdmaResMgr [IN] Handle to the previously opened Resource + * Manager Instance. + * \param lChObj [IN] Logical Channel object for which new + * PaRAM set is specified. User should pass + * the resource type and id in this object. + * \param newPaRAM [IN] PaRAM set to be copied onto existing one + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + * + * \note This function is re-entrant for unique lChObj values. It is non- + * re-entrant for same lChObj value. + */ +EDMA3_RM_Result EDMA3_RM_setPaRAM (EDMA3_RM_Handle hEdmaResMgr, + EDMA3_RM_ResDesc *lChObj, + const EDMA3_RM_PaRAMRegs *newPaRAM); + + + +/**\fn EDMA3_RM_Result EDMA3_RM_getPaRAM (EDMA3_RM_Handle hEdmaResMgr, + * EDMA3_RM_ResDesc *lChObj, + * EDMA3_RM_PaRAMRegs *currPaRAM) + * \brief Retrieve existing PaRAM set associated with specified logical + * channel (DMA/QDMA/Link). + * + * \param hEdmaResMgr [IN] Handle to the previously opened Resource + * Manager Instance. + * \param lChObj [IN] Logical Channel object for which the + * PaRAM set is requested. User should pass + * the resource type and id in this object. + * \param currPaRAM [IN/OUT] User gets the existing PaRAM here. + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + * + * \note This function is re-entrant. + */ +EDMA3_RM_Result EDMA3_RM_getPaRAM (EDMA3_RM_Handle hEdmaResMgr, + EDMA3_RM_ResDesc *lChObj, + EDMA3_RM_PaRAMRegs *currPaRAM); + + + +/**\fn EDMA3_RM_Result EDMA3_RM_getPaRAMPhyAddr(EDMA3_RM_Handle + * hEdmaResMgr, EDMA3_RM_ResDesc *lChObj, + * unsigned int *paramPhyAddr) + * \brief Get the PaRAM Set Physical Address associated with a logical channel + * + * This function returns the PaRAM Set Phy Address (unsigned 32 bits). + * The returned address could be used by the advanced users to program the + * PaRAM Set directly without using any APIs. + * + * Least significant 16 bits of this address could be used to program + * the LINK field in the PaRAM Set. + * Users which program the LINK field directly SHOULD use this API + * to get the associated PaRAM Set address with the LINK channel. + * + * \param hEdmaResMgr [IN] Handle to the previously opened Resource + * Manager Instance. + * \param lChObj [IN] Logical Channel object for which the + * PaRAM set physical address is required. + * User should pass the resource type and + * id in this object. + * \param paramPhyAddr [IN/OUT] PaRAM Set physical address is returned + * here. + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + * + * \note This function is re-entrant. + */ +EDMA3_RM_Result EDMA3_RM_getPaRAMPhyAddr(EDMA3_RM_Handle hEdmaResMgr, + EDMA3_RM_ResDesc *lChObj, + unsigned int *paramPhyAddr); + + +/**\fn EDMA3_RM_Result EDMA3_RM_getBaseAddress (EDMA3_RM_Handle + * hEdmaResMgr, EDMA3_RM_Cntrlr_PhyAddr controllerId, + * unsigned int *phyAddress) + * \brief Get the Channel Controller or Transfer Controller (n) Physical + * Address. + * + * \param hEdmaResMgr [IN] Handle to the previously opened Resource + * Manager Instance. + * \param controllerId [IN] Channel Controller or Transfer + * Controller (n) for which the physical + * address is required. + * \param phyAddress [IN/OUT] Physical address is returned here. + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + * + * \note This function is re-entrant. + */ +EDMA3_RM_Result EDMA3_RM_getBaseAddress (EDMA3_RM_Handle hEdmaResMgr, + EDMA3_RM_Cntrlr_PhyAddr controllerId, + unsigned int *phyAddress); + + + +/**\fn EDMA3_RM_Result EDMA3_RM_getGblConfigParams (unsigned int phyCtrllerInstId, + * EDMA3_RM_GblConfigParams *gblCfgParams) + * \brief Get the SoC specific configuration structure for the EDMA3 Hardware. + * + * This API is used to fetch the global SoC specific configuration structure + * for the EDMA3 Hardware. It is useful for the user who has not passed + * this information during EDMA3_RM_create() and taken the default configuration + * coming along with the package. + * + * \param phyCtrllerInstId [IN] EDMA3 Controller Instance Id + * (Hardware instance id, starting from 0). + * \param gblCfgParams [IN/OUT] SoC specific configuration structure for the + * EDMA3 Hardware will be returned here. + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + * + * \note This function is re-entrant. + */ +EDMA3_RM_Result EDMA3_RM_getGblConfigParams (unsigned int phyCtrllerInstId, + EDMA3_RM_GblConfigParams *gblCfgParams); + + + +/**\fn EDMA3_RM_Result EDMA3_RM_getInstanceInitCfg (EDMA3_RM_Handle hEdmaResMgr, + * EDMA3_RM_InstanceInitConfig *instanceInitConfig) + * \brief Get the RM Instance specific configuration structure for different + * EDMA3 resources' usage (owned resources, reserved resources etc). + * + * This API is used to fetch the Resource Manager Instance specific configuration + * structure, for a specific shadow region. It is useful for the user who has not passed + * this information during EDMA3_RM_opn() and taken the default configuration + * coming along with the package. EDMA3 resources, owned and reserved by this RM + * instance, will be returned from this API. + * + * \param hEdmaResMgr [IN] Handle to the previously opened Resource + * Manager Instance. + * \param instanceInitConfig [IN/OUT] RM Instance specific configuration + * structure will be returned here. + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + * + * \note This function is re-entrant. + */ +EDMA3_RM_Result EDMA3_RM_getInstanceInitCfg (EDMA3_RM_Handle hEdmaResMgr, + EDMA3_RM_InstanceInitConfig *instanceInitConfig); + + +/**\enum EDMA3_RM_IoctlCmd + * \brief EDMA3 Resource Manager IOCTL commands + */ +typedef enum +{ + /* Min IOCTL */ + EDMA3_RM_IOCTL_MIN_IOCTL = 0, + + /** + * PaRAM Sets will be cleared OR will not be cleared + * during allocation, depending upon this option. + * + * For e.g., + * To clear the PaRAM Sets during allocation, + * cmdArg = (void *)1; + * + * To NOT clear the PaRAM Sets during allocation, + * cmdArg = (void *)0; + * + * For all other values, it will return error. + * + * By default, PaRAM Sets will be cleared during allocation. + * + * Note: Since this enum can change the behavior how the resources are + * initialized during their allocation, user is adviced to not use this + * command while allocating the resources. User should first change the + * behavior of resources' initialization and then should use start + * allocating resources. + */ + EDMA3_RM_IOCTL_SET_PARAM_CLEAR_OPTION, + + /** + * To check whether PaRAM Sets will be cleared or not + * during allocation. + * If the value read is '1', it means that PaRAM Sets are getting cleared + * during allocation. + * If the value read is '0', it means that PaRAM Sets are NOT getting cleared + * during allocation. + * + * For e.g., + * unsigned int *isParamClearingDone = (unsigned int *)cmdArg; + * (*isParamClearingDone) = paramClearingRequired; + */ + EDMA3_RM_IOCTL_GET_PARAM_CLEAR_OPTION, + + /** + * Global EDMA3 registers (DCHMAP/QCHMAP) and PaRAM Sets will be modified + * OR will not be modified during EDMA3_RM_allocLogicalChannel (), depending + * upon this option. + * + * For e.g., + * To modify the Registers or PaRAM Sets during allocation, + * cmdArg = (void *)1; + * + * To NOT modify the Registers or PaRAM Sets during allocation, + * cmdArg = (void *)0; + * + * For all other values, it will return error. + * + * By default, Registers or PaRAM Sets will be programmed during allocation. + * + * Note: Since this enum can change the behavior how the resources are + * initialized during their allocation, user is adviced to not use this + * command while allocating the resources. User should first change the + * behavior of resources' initialization and then should use start + * allocating resources. + */ + EDMA3_RM_IOCTL_SET_GBL_REG_MODIFY_OPTION, + + /** + * To check whether Global EDMA3 registers (DCHMAP/QCHMAP) and PaRAM Sets + * will be programmed or not during allocation (EDMA3_RM_allocLogicalChannel ()). + * If the value read is '1', it means that the registers/PaRAMs are getting programmed + * during allocation. + * If the value read is '0', it means that the registers/PaRAMs are NOT getting programmed + * during allocation. + * + * For e.g., + * unsigned int *isParamClearingDone = (unsigned int *)cmdArg; + * (*isParamClearingDone) = paramClearingRequired; + */ + EDMA3_RM_IOCTL_GET_GBL_REG_MODIFY_OPTION, + + /* Max IOCTLs */ + EDMA3_RM_IOCTL_MAX_IOCTL +} EDMA3_RM_IoctlCmd; + + +/** + * \brief EDMA3 Resource Manager IOCTL + * + * This function provides IOCTL functionality for EDMA3 Resource Manager + * + * \param hEdmaResMgr [IN] Handle to the previously opened Resource + * Manager Instance. + * \param cmd [IN] IOCTL command to be performed + * \param cmdArg [IN/OUT] IOCTL command argument (if any) + * \param param [IN/OUT] Device/Cmd specific argument. + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + * + * \note For 'EDMA3_RM_IOCTL_GET_PARAM_CLEAR_OPTION', this function is re-entrant. + * For 'EDMA3_RM_IOCTL_SET_PARAM_CLEAR_OPTION', this function is re-entrant for + * different Resource Manager Instances (handles). + */ +EDMA3_RM_Result EDMA3_RM_Ioctl( + EDMA3_RM_Handle hEdmaResMgr, + EDMA3_RM_IoctlCmd cmd, + void *cmdArg, + void *param + ); + + +/* @} Edma3ResMgr */ + +/* @} Edma3RMMain */ + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif /* _EDMA3_RM_H_ */ diff --git a/packages/ti/sdo/edma3/rm/package.bld b/packages/ti/sdo/edma3/rm/package.bld new file mode 100644 index 0000000..4fb17cd --- /dev/null +++ b/packages/ti/sdo/edma3/rm/package.bld @@ -0,0 +1,79 @@ +/* +* Copyright 2006 by Texas Instruments Incorporated. +* +* All rights reserved. Property of Texas Instruments Incorporated. +* Restricted rights to use, duplicate or disclose this code are +* granted through contract. +* +*/ + +var Build = xdc.useModule('xdc.bld.BuildEnvironment'); +var Pkg = xdc.useModule('xdc.bld.PackageContents'); + +var objListDA830 = [ + /* The configuration file. */ + "src/edma3_da830_cfg.c", + /* Common file. */ + "src/edma3resmgr.c", + /* File defining internal data structures. */ + "src/edma3_rm_gbl_data.c", +]; + +var objList = [ + objListDA830, +]; + +/* Platforms supported */ +var plat_supported = [ + 'ti.platforms.evmDA830', + ]; + +/* Directories for each platform */ +var dir = [ + 'da830/', + ]; + +for each (var targ in Build.targets) +{ + for each (var plat in targ.platforms) + { + var lib = "lib/"; + var bool = 0; + + for (var i = 0; i < plat_supported.length; i++) + { + if (java.lang.String(plat).equals(plat_supported[i])) + { + /* Choose the selected platform */ + lib = lib + dir[i]; + bool = 1; + break; + } + } + + if (bool == 0) + throw new Error('Unexpected value in "platform" parameter') + + Pkg.addLibrary(lib + "Debug/" + Pkg.name, targ, + { defs:"", profile: "debug"} + ).addObjects(objList[i]); + Pkg.addLibrary(lib + "Release/" + Pkg.name, targ, + { defs:"", profile: "release"} + ).addObjects(objList[i]); + } +} + + +Pkg.otherFiles=[ + 'docs', + 'lib/da830/Debug/ti.sdo.edma3.rm.a674', + 'lib/da830/Release/ti.sdo.edma3.rm.a674', + 'src', + 'edma3_common.h', + 'edma3_rm.h', + 'package.bld', + 'package.xs', + 'RM.xdc', + 'RM.xdt', +]; + diff --git a/packages/ti/sdo/edma3/rm/package.xdc b/packages/ti/sdo/edma3/rm/package.xdc new file mode 100644 index 0000000..be3cca3 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/package.xdc @@ -0,0 +1,17 @@ +/* + * ======== package.xdc ======== + * + */ + +/* + * List the packages to be included in the bundle. The 'requires' + * statements must come before the 'package' statement. + */ + + +/*! + * ======== ti.sdo.edma3.rm ======== + */ +package ti.sdo.edma3.rm [2, 00, 00] { + module RM; +} diff --git a/packages/ti/sdo/edma3/rm/package.xs b/packages/ti/sdo/edma3/rm/package.xs new file mode 100644 index 0000000..6bbbe1d --- /dev/null +++ b/packages/ti/sdo/edma3/rm/package.xs @@ -0,0 +1,59 @@ +/* + * ======== package.xs ======== + * + */ + +/* + * ======== getLibs ======== + */ +function getLibs(prog) +{ + var bool = 0; + + print ("Inside EDMA3 RM getLibs"); + + /* Prepare variables to form the library path within this package */ + var name = "ti.sdo.edma3.rm.a674"; + var lib = "lib/"; + + /* Devices supported */ + var devices = [ + 'TMS320DA830', + ]; + + /* Directories for each platform */ + var dir = [ + 'da830/', + ]; + + for (var i = 0; i < devices.length; i++) + { + if (java.lang.String(Program.cpu.deviceName).equals(devices[i])) + { + /* Choose the selected platform and build the complete name. */ + lib = lib + dir[i]; + bool = 1; + break; + } + } + + if (bool == 0) + throw new Error('Unexpected value in "platform" parameter') + + switch (this.profile) { + case 'debug': + /* enable debug build for debug profile only */ + lib = lib + "Debug/" + name; + break; + + default: + /* release profile for everything else */ + lib = lib + "Release/" + name; + } + + print(" will link with " + this.$name + ":" + lib); + + /* return the library name */ + return (lib); +} + diff --git a/packages/ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h b/packages/ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h new file mode 100644 index 0000000..fb4ff1e --- /dev/null +++ b/packages/ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h @@ -0,0 +1,125 @@ +/******************************************************************************* +**+--------------------------------------------------------------------------+** +**| **** |** +**| **** |** +**| ******o*** |** +**| ********_///_**** |** +**| ***** /_//_/ **** |** +**| ** ** (__/ **** |** +**| ********* |** +**| **** |** +**| *** |** +**| |** +**| Copyright (c) 1998-2006 Texas Instruments Incorporated |** +**| ALL RIGHTS RESERVED |** +**| |** +**| Permission is hereby granted to licensees of Texas Instruments |** +**| Incorporated (TI) products to use this computer program for the sole |** +**| purpose of implementing a licensee product based on TI products. |** +**| No other rights to reproduce, use, or disseminate this computer |** +**| program, whether in part or in whole, are granted. |** +**| |** +**| TI makes no representation or warranties with respect to the |** +**| performance of this computer program, and specifically disclaims |** +**| any responsibility for any damages, special or consequential, |** +**| connected with the use of this program. |** +**| |** +**+--------------------------------------------------------------------------+** +*******************************************************************************/ + +/** \file bios6_edma3_rm_sample.h + + \brief Header file for the Demo application for the EDMA3 Resource Manager. + + (C) Copyright 2006, Texas Instruments, Inc + + \version 1.0 Anuj Aggarwal - Created + 1.1 Anuj Aggarwal - Made the sample app generic + - Removed redundant arguments + from Cache-related APIs + - Added new function for Poll mode + testing + + */ + +#ifndef _BIOS6_EDMA3_RM_SAMPLE_H_ +#define _BIOS6_EDMA3_RM_SAMPLE_H_ + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* To enable debug traces in the EDMA3 sample app */ +#define EDMA3_DEBUG_PRINT + +#ifdef EDMA3_DEBUG_PRINT +#include +#define EDMA3_DEBUG_PRINTF printf +#endif /* EDMA3_DEBUG_PRINT */ + +/** + * \brief SoC specific TC related information. Specified in the sample + * configuration file (bios_edma3_sample_cfg.c). + */ +extern unsigned int numEdma3Tc; +extern unsigned int ccXferCompInt; +extern unsigned int ccErrorInt; +extern unsigned int tcErrorInt[8]; + +extern unsigned int hwIntXferComp; +extern unsigned int hwIntCcErr; +extern unsigned int hwIntTcErr; + +EDMA3_RM_Result edma3init(); +EDMA3_RM_Result edma3deinit(); + + +/** + * Counting Semaphore related functions (OS dependent) should be + * called/implemented by the application. A handle to the semaphore + * is required while opening the driver/resource manager instance. + */ + +/** + * \brief EDMA3 OS Semaphore Create + * + * This function creates a counting semaphore with specified + * attributes and initial value. It should be used to create a semaphore + * with initial value as '1'. The semaphore is then passed by the user + * to the EDMA3 RM for proper sharing of resources. + * \param initVal [IN] is initial value for semaphore + * \param attrs [IN] is the semaphore attributes ex: Fifo type + * \param hSem [OUT] is location to recieve the handle to just created + * semaphore + * \return EDMA3_RM_SOK if succesful, else a suitable error code. + */ +EDMA3_RM_Result edma3OsSemCreate(int initVal, + const Semaphore_Params *semParams, + EDMA3_OS_Sem_Handle *hSem); + + + +/** + * \brief EDMA3 OS Semaphore Delete + * + * This function deletes or removes the specified semaphore + * from the system. Associated dynamically allocated memory + * if any is also freed up. + * \warning OsSEM services run in client context and not in a thread + * of their own. If there exist threads pended on a semaphore + * that is being deleted, results are undefined. + * \param hSem [IN] handle to the semaphore to be deleted + * \return EDMA3_RM_SOK if succesful else a suitable error code + */ +EDMA3_RM_Result edma3OsSemDelete(EDMA3_OS_Sem_Handle hSem); + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + diff --git a/packages/ti/sdo/edma3/rm/sample/package.bld b/packages/ti/sdo/edma3/rm/sample/package.bld new file mode 100644 index 0000000..1fafc5c --- /dev/null +++ b/packages/ti/sdo/edma3/rm/sample/package.bld @@ -0,0 +1,68 @@ +/* +* Copyright 2006 by Texas Instruments Incorporated. +* +* All rights reserved. Property of Texas Instruments Incorporated. +* Restricted rights to use, duplicate or disclose this code are +* granted through contract. +* +*/ + +var Build = xdc.useModule('xdc.bld.BuildEnvironment'); +var Pkg = xdc.useModule('xdc.bld.PackageContents'); + +var objListDA830 = [ + "src/bios6_edma3_rm_sample_da830_cfg.c", + "src/bios6_edma3_rm_sample_cs.c", + "src/bios6_edma3_rm_sample_init.c", +]; + +var objList = [ + objListDA830, +]; + +/* Platforms supported */ +var plat_supported = [ + 'ti.platforms.evmDA830', + ]; + +/* Directories for each platform */ +var dir = [ + 'da830/', + ]; + +for each (var targ in Build.targets) +{ + for each (var plat in targ.platforms) + { + var lib = "lib/"; + var bool = 0; + + for (var i = 0; i < plat_supported.length; i++) + { + if (java.lang.String(plat).equals(plat_supported[i])) + { + /* Choose the selected platform */ + lib = lib + dir[i]; + bool = 1; + break; + } + } + + if (bool == 0) + throw new Error('Unexpected value in "platform" parameter') + + Pkg.addLibrary(lib + "Debug/" + Pkg.name, targ, { profile: "debug"}).addObjects(objList[i]); + Pkg.addLibrary(lib + "Release/" + Pkg.name, targ, { profile: "release"}).addObjects(objList[i]); + } +} + + +Pkg.otherFiles=[ + 'lib/da830/Debug/ti.sdo.edma3.rm.sample.a674', + 'lib/da830/Release/ti.sdo.edma3.rm.sample.a674', + 'src', + 'bios6_edma3_rm_sample.h', + 'package.bld', + 'package.xs', +]; + diff --git a/packages/ti/sdo/edma3/rm/sample/package.xdc b/packages/ti/sdo/edma3/rm/sample/package.xdc new file mode 100644 index 0000000..ff96493 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/sample/package.xdc @@ -0,0 +1,17 @@ +/* + * ======== package.xdc ======== + * + */ + +/* + * List the packages to be included in the bundle. The 'requires' + * statements must come before the 'package' statement. + */ +requires ti.sdo.edma3.rm; + + +/*! + * ======== ti.sdo.edma3.rm.sample ======== + */ +package ti.sdo.edma3.rm.sample [2, 00, 00] { +} diff --git a/packages/ti/sdo/edma3/rm/sample/package.xs b/packages/ti/sdo/edma3/rm/sample/package.xs new file mode 100644 index 0000000..20559e0 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/sample/package.xs @@ -0,0 +1,59 @@ +/* + * ======== package.xs ======== + * + */ + +/* + * ======== getLibs ======== + */ +function getLibs(prog) +{ + var bool = 0; + + print ("Inside EDMA3 RM Sample App getLibs"); + + /* Prepare variables to form the library path within this package */ + var name = "ti.sdo.edma3.rm.sample.a674"; + var lib = "lib/"; + + /* Devices supported */ + var devices = [ + 'TMS320DA830', + ]; + + /* Directories for each platform */ + var dir = [ + 'da830/', + ]; + + for (var i = 0; i < devices.length; i++) + { + if (java.lang.String(Program.cpu.deviceName).equals(devices[i])) + { + /* Choose the selected platform */ + lib = lib + dir[i]; + bool = 1; + break; + } + } + + if (bool == 0) + throw new Error('Unexpected value in "platform" parameter') + + switch (this.profile) { + case 'debug': + /* enable debug build for debug profile only */ + lib = lib + "Debug/" + name; + break; + + default: + /* release profile for everything else */ + lib = lib + "Release/" + name; + } + + print(" will link with " + this.$name + ":" + lib); + + /* return the library name */ + return (lib); +} + diff --git a/packages/ti/sdo/edma3/rm/sample/src/bios6_edma3_rm_sample_cs.c b/packages/ti/sdo/edma3/rm/sample/src/bios6_edma3_rm_sample_cs.c new file mode 100644 index 0000000..45e932c --- /dev/null +++ b/packages/ti/sdo/edma3/rm/sample/src/bios6_edma3_rm_sample_cs.c @@ -0,0 +1,332 @@ +/******************************************************************************* +**+--------------------------------------------------------------------------+** +**| **** |** +**| **** |** +**| ******o*** |** +**| ********_///_**** |** +**| ***** /_//_/ **** |** +**| ** ** (__/ **** |** +**| ********* |** +**| **** |** +**| *** |** +**| |** +**| Copyright (c) 1998-2006 Texas Instruments Incorporated |** +**| ALL RIGHTS RESERVED |** +**| |** +**| Permission is hereby granted to licensees of Texas Instruments |** +**| Incorporated (TI) products to use this computer program for the sole |** +**| purpose of implementing a licensee product based on TI products. |** +**| No other rights to reproduce, use, or disseminate this computer |** +**| program, whether in part or in whole, are granted. |** +**| |** +**| TI makes no representation or warranties with respect to the |** +**| performance of this computer program, and specifically disclaims |** +**| any responsibility for any damages, special or consequential, |** +**| connected with the use of this program. |** +**| |** +**+--------------------------------------------------------------------------+** +*******************************************************************************/ + +/** \file bios6_edma3_rm_sample_cs.c + + \brief Sample functions showing the implementation of Critical section + entry/exit routines and various semaphore related routines (all OS + depenedent). These implementations MUST be provided by the user / + application, using the EDMA3 Resource Manager, for its + correct functioning. + + (C) Copyright 2006, Texas Instruments, Inc + + \version 1.0 Anuj Aggarwal - Created + + */ + +#include +#include +#include +#include + +#include + + + +/** + * \brief EDMA3 OS Protect Entry + * + * This function saves the current state of protection in 'intState' + * variable passed by caller, if the protection level is + * EDMA3_OS_PROTECT_INTERRUPT. It then applies the requested level of + * protection. + * For EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION and + * EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR, variable 'intState' is ignored, + * and the requested interrupt is disabled. + * For EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR, '*intState' specifies the + * Transfer Controller number whose interrupt needs to be disabled. + * + * \param level is numeric identifier of the desired degree of protection. + * \param intState is memory location where current state of protection is + * saved for future use while restoring it via edma3OsProtectExit() (Only + * for EDMA3_OS_PROTECT_INTERRUPT protection level). + * \return None + */ +void edma3OsProtectEntry (int level, unsigned int *intState) + { + if (((level == EDMA3_OS_PROTECT_INTERRUPT) + || (level == EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR)) + && (intState == NULL)) + { + return; + } + else + { + switch (level) + { + /* Disable all (global) interrupts */ + case EDMA3_OS_PROTECT_INTERRUPT : + *intState = Hwi_disable(); + break; + + /* Disable scheduler */ + case EDMA3_OS_PROTECT_SCHEDULER : + Task_disable(); + break; + + /* Disable EDMA3 transfer completion interrupt only */ + case EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION : + EventCombiner_disableEvent(ccXferCompInt); + break; + + /* Disable EDMA3 CC error interrupt only */ + case EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR : + EventCombiner_disableEvent(ccErrorInt); + break; + + /* Disable EDMA3 TC error interrupt only */ + case EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR : + switch (*intState) + { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + /* Fall through... */ + /* Disable the corresponding interrupt */ + EventCombiner_disableEvent(tcErrorInt[*intState]); + break; + + default: + break; + } + + break; + + default: + break; + } + } + } + + +/** + * \brief EDMA3 OS Protect Exit + * + * This function undoes the protection enforced to original state + * as is specified by the variable 'intState' passed, if the protection + * level is EDMA3_OS_PROTECT_INTERRUPT. + * For EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION and + * EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR, variable 'intState' is ignored, + * and the requested interrupt is enabled. + * For EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR, 'intState' specifies the + * Transfer Controller number whose interrupt needs to be enabled. + * \param level is numeric identifier of the desired degree of protection. + * \param intState is original state of protection at time when the + * corresponding edma3OsProtectEntry() was called (Only + * for EDMA3_OS_PROTECT_INTERRUPT protection level). + * \return None + */ +void edma3OsProtectExit (int level, unsigned int intState) + { + switch (level) + { + /* Enable all (global) interrupts */ + case EDMA3_OS_PROTECT_INTERRUPT : + Hwi_restore(intState); + break; + + /* Enable scheduler */ + case EDMA3_OS_PROTECT_SCHEDULER : + Task_enable(); + break; + + /* Enable EDMA3 transfer completion interrupt only */ + case EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION : + EventCombiner_enableEvent(ccXferCompInt); + break; + + /* Enable EDMA3 CC error interrupt only */ + case EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR : + EventCombiner_enableEvent(ccErrorInt); + break; + + /* Enable EDMA3 TC error interrupt only */ + case EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR : + switch (intState) + { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + /* Fall through... */ + /* Enable the corresponding interrupt */ + EventCombiner_enableEvent(tcErrorInt[intState]); + break; + + default: + break; + } + + break; + + default: + break; + } + } + + +/** + * Counting Semaphore related functions (OS dependent) should be + * called/implemented by the application. A handle to the semaphore + * is required while opening the resource manager instance. + */ + +/** + * \brief EDMA3 OS Semaphore Create + * + * This function creates a counting semaphore with specified + * attributes and initial value. It should be used to create a semaphore + * with initial value as '1'. The semaphore is then passed by the user + * to the EDMA3 RM for proper sharing of resources. + * \param initVal [IN] is initial value for semaphore + * \param semParams [IN] is the semaphore attributes. + * \param hSem [OUT] is location to recieve the handle to just created + * semaphore + * \return EDMA3_RM_SOK if succesful, else a suitable error code. + */ +EDMA3_RM_Result edma3OsSemCreate(int initVal, + const Semaphore_Params *semParams, + EDMA3_OS_Sem_Handle *hSem) + { + EDMA3_RM_Result semCreateResult = EDMA3_RM_SOK; + + if(NULL == hSem) + { + semCreateResult = EDMA3_RM_E_INVALID_PARAM; + } + else + { + *hSem = (EDMA3_OS_Sem_Handle)Semaphore_create(initVal, semParams, NULL); + if ( (*hSem) == NULL ) + { + semCreateResult = EDMA3_RM_E_SEMAPHORE; + } + } + + return semCreateResult; + } + + +/** + * \brief EDMA3 OS Semaphore Delete + * + * This function deletes or removes the specified semaphore + * from the system. Associated dynamically allocated memory + * if any is also freed up. + * \param hSem [IN] handle to the semaphore to be deleted + * \return EDMA3_RM_SOK if succesful else a suitable error code + */ +EDMA3_RM_Result edma3OsSemDelete(EDMA3_OS_Sem_Handle hSem) + { + EDMA3_RM_Result semDeleteResult = EDMA3_RM_SOK; + + if(NULL == hSem) + { + semDeleteResult = EDMA3_RM_E_INVALID_PARAM; + } + else + { + Semaphore_delete(hSem); + } + + return semDeleteResult; + } + + +/** + * \brief EDMA3 OS Semaphore Take + * + * This function takes a semaphore token if available. + * If a semaphore is unavailable, it blocks currently + * running thread in wait (for specified duration) for + * a free semaphore. + * \param hSem [IN] is the handle of the specified semaphore + * \param mSecTimeout [IN] is wait time in milliseconds + * \return EDMA3_RM_Result if successful else a suitable error code + */ +EDMA3_RM_Result edma3OsSemTake(EDMA3_OS_Sem_Handle hSem, int mSecTimeout) + { + EDMA3_RM_Result semTakeResult = EDMA3_RM_SOK; + unsigned short semPendResult; + + if(NULL == hSem) + { + semTakeResult = EDMA3_RM_E_INVALID_PARAM; + } + else + { + semPendResult = Semaphore_pend(hSem, mSecTimeout); + if (semPendResult == FALSE) + { + semTakeResult = EDMA3_RM_E_SEMAPHORE; + } + } + + return semTakeResult; + } + + +/** + * \brief EDMA3 OS Semaphore Give + * + * This function gives or relinquishes an already + * acquired semaphore token + * \param hSem [IN] is the handle of the specified semaphore + * \return EDMA3_RM_Result if successful else a suitable error code + */ +EDMA3_RM_Result edma3OsSemGive(EDMA3_OS_Sem_Handle hSem) + { + EDMA3_RM_Result semGiveResult = EDMA3_RM_SOK; + + if(NULL == hSem) + { + semGiveResult = EDMA3_RM_E_INVALID_PARAM; + } + else + { + Semaphore_post(hSem); + } + + return semGiveResult; + } + + + + + diff --git a/packages/ti/sdo/edma3/rm/sample/src/bios6_edma3_rm_sample_da830_cfg.c b/packages/ti/sdo/edma3/rm/sample/src/bios6_edma3_rm_sample_da830_cfg.c new file mode 100644 index 0000000..2e07836 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/sample/src/bios6_edma3_rm_sample_da830_cfg.c @@ -0,0 +1,396 @@ +/******************************************************************************* +**+--------------------------------------------------------------------------+** +**| **** |** +**| **** |** +**| ******o*** |** +**| ********_///_**** |** +**| ***** /_//_/ **** |** +**| ** ** (__/ **** |** +**| ********* |** +**| **** |** +**| *** |** +**| |** +**| Copyright (c) 1998-2006 Texas Instruments Incorporated |** +**| ALL RIGHTS RESERVED |** +**| |** +**| Permission is hereby granted to licensees of Texas Instruments |** +**| Incorporated (TI) products to use this computer program for the sole |** +**| purpose of implementing a licensee product based on TI products. |** +**| No other rights to reproduce, use, or disseminate this computer |** +**| program, whether in part or in whole, are granted. |** +**| |** +**| TI makes no representation or warranties with respect to the |** +**| performance of this computer program, and specifically disclaims |** +**| any responsibility for any damages, special or consequential, |** +**| connected with the use of this program. |** +**| |** +**+--------------------------------------------------------------------------+** +*******************************************************************************/ + +/** \file bios6_edma3_rm_sample_da830_cfg.c + + \brief SoC specific EDMA3 hardware related information like number of + transfer controllers, various interrupt ids etc. It is used while + interrupts enabling / disabling. It needs to be ported for different + SoCs. + + (C) Copyright 2008, Texas Instruments, Inc + + \version 1.0 Anuj Aggarwal - Created + + */ + +#include + + +/* DA830 Specific EDMA3 Information */ + +/** Number of Event Queues available */ +#define EDMA3_NUM_EVTQUE (2u) + +/** Number of Transfer Controllers available */ +#define EDMA3_NUM_TC (2u) + +/** Interrupt no. for Transfer Completion */ +#define EDMA3_CC_XFER_COMPLETION_INT (8u) + +/** Interrupt no. for CC Error */ +#define EDMA3_CC_ERROR_INT (56u) + +/** Interrupt no. for TCs Error */ +#define EDMA3_TC0_ERROR_INT (57u) +#define EDMA3_TC1_ERROR_INT (58u) +#define EDMA3_TC2_ERROR_INT (0u) +#define EDMA3_TC3_ERROR_INT (0u) +#define EDMA3_TC4_ERROR_INT (0u) +#define EDMA3_TC5_ERROR_INT (0u) +#define EDMA3_TC6_ERROR_INT (0u) +#define EDMA3_TC7_ERROR_INT (0u) + +/** +* EDMA3 interrupts (transfer completion, CC error etc.) correspond to different +* ECM events (SoC specific). These ECM events come +* under ECM block XXX (handling those specific ECM events). Normally, block +* 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events +* 32-63 and so on. This ECM block XXX (or interrupt selection number XXX) +* is mapped to a specific HWI_INT YYY in the tcf file. +* Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding +* to transfer completion interrupt. +* Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding +* to CC error interrupts. +* Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding +* to TC error interrupts. +*/ +#define EDMA3_HWI_INT_XFER_COMP (7u) +#define EDMA3_HWI_INT_CC_ERR (8u) +#define EDMA3_HWI_INT_TC_ERR (8u) + + +/** + * \brief Mapping of DMA channels 0-31 to Hardware Events from + * various peripherals, which use EDMA for data transfer. + * All channels need not be mapped, some can be free also. + * 1: Mapped + * 0: Not mapped + * + * This mapping will be used to allocate DMA channels when user passes + * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory + * copy). The same mapping is used to allocate the TCC when user passes + * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy). + * + * To allocate more DMA channels or TCCs, one has to modify the event mapping. + */ + /* 31 0 */ +#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0 (0xCF3FFFFFu) + +/** + * \brief Mapping of DMA channels 32-63 to Hardware Events from + * various peripherals, which use EDMA for data transfer. + * All channels need not be mapped, some can be free also. + * 1: Mapped + * 0: Not mapped + * + * This mapping will be used to allocate DMA channels when user passes + * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory + * copy). The same mapping is used to allocate the TCC when user passes + * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy). + * + * To allocate more DMA channels or TCCs, one has to modify the event mapping. + */ +/* DMA channels 32-63 DOES NOT exist in DA830. */ +#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1 (0x0u) + +/* Variable which will be used internally for referring number of Event Queues. */ +unsigned int numEdma3EvtQue = EDMA3_NUM_EVTQUE; + +/* Variable which will be used internally for referring number of TCs. */ +unsigned int numEdma3Tc = EDMA3_NUM_TC; + +/** + * Variable which will be used internally for referring transfer completion + * interrupt. + */ +unsigned int ccXferCompInt = EDMA3_CC_XFER_COMPLETION_INT; + +/** + * Variable which will be used internally for referring channel controller's + * error interrupt. + */ +unsigned int ccErrorInt = EDMA3_CC_ERROR_INT; + +/** + * Variable which will be used internally for referring transfer controllers' + * error interrupts. + */ +unsigned int tcErrorInt[8] = { + EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT, + EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT, + EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT, + EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT + }; + +/** + * Variables which will be used internally for referring the hardware interrupt + * for various EDMA3 interrupts. + */ +unsigned int hwIntXferComp = EDMA3_HWI_INT_XFER_COMP; +unsigned int hwIntCcErr = EDMA3_HWI_INT_CC_ERR; +unsigned int hwIntTcErr = EDMA3_HWI_INT_TC_ERR; + + +/* Driver Object Initialization Configuration */ +EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams = + { + /** Total number of DMA Channels supported by the EDMA3 Controller */ + 32u, + /** Total number of QDMA Channels supported by the EDMA3 Controller */ + 8u, + /** Total number of TCCs supported by the EDMA3 Controller */ + 32u, + /** Total number of PaRAM Sets supported by the EDMA3 Controller */ + 128u, + /** Total number of Event Queues in the EDMA3 Controller */ + 2u, + /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */ + 2u, + /** Number of Regions on this EDMA3 controller */ + 4u, + + /** + * \brief Channel mapping existence + * A value of 0 (No channel mapping) implies that there is fixed association + * for a channel number to a parameter entry number or, in other words, + * PaRAM entry n corresponds to channel n. + */ + 0u, + + /** Existence of memory protection feature */ + 0u, + + /** Global Register Region of CC Registers */ + (void *)0x01C00000u, + /** Transfer Controller (TC) Registers */ + { + (void *)0x01C08000u, + (void *)0x01C08400u, + (void *)NULL, + (void *)NULL, + (void *)NULL, + (void *)NULL, + (void *)NULL, + (void *)NULL + }, + /** Interrupt no. for Transfer Completion */ + EDMA3_CC_XFER_COMPLETION_INT, + /** Interrupt no. for CC Error */ + EDMA3_CC_ERROR_INT, + /** Interrupt no. for TCs Error */ + { + EDMA3_TC0_ERROR_INT, + EDMA3_TC1_ERROR_INT, + EDMA3_TC2_ERROR_INT, + EDMA3_TC3_ERROR_INT, + EDMA3_TC4_ERROR_INT, + EDMA3_TC5_ERROR_INT, + EDMA3_TC6_ERROR_INT, + EDMA3_TC7_ERROR_INT + }, + + /** + * \brief EDMA3 TC priority setting + * + * User can program the priority of the Event Queues + * at a system-wide level. This means that the user can set the + * priority of an IO initiated by either of the TCs (Transfer Controllers) + * relative to IO initiated by the other bus masters on the + * device (ARM, DSP, USB, etc) + */ + { + 0u, + 1u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u + }, + /** + * \brief To Configure the Threshold level of number of events + * that can be queued up in the Event queues. EDMA3CC error register + * (CCERR) will indicate whether or not at any instant of time the + * number of events queued up in any of the event queues exceeds + * or equals the threshold/watermark value that is set + * in the queue watermark threshold register (QWMTHRA). + */ + { + 16u, + 16u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u + }, + + /** + * \brief To Configure the Default Burst Size (DBS) of TCs. + * An optimally-sized command is defined by the transfer controller + * default burst size (DBS). Different TCs can have different + * DBS values. It is defined in Bytes. + */ + { + 16u, + 16u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u + }, + + /** + * \brief Mapping from each DMA channel to a Parameter RAM set, + * if it exists, otherwise of no use. + */ + { + 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u, + 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u, + 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u, + 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u, + /* DMA channels 32-63 DOES NOT exist in DA830. */ + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS + }, + + /** + * \brief Mapping from each DMA channel to a TCC. This specific + * TCC code will be returned when the transfer is completed + * on the mapped channel. + */ + { + 0u, 1u, 2u, 3u, + 4u, 5u, 6u, 7u, + 8u, 9u, 10u, 11u, + 12u, 13u, 14u, 15u, + 16u, 17u, 18u, 19u, + 20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, + 24u, 25u, 26u, 27u, + EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, 30, 31, + /* DMA channels 32-63 DOES NOT exist in DA830. */ + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC + }, + + /** + * \brief Mapping of DMA channels to Hardware Events from + * various peripherals, which use EDMA for data transfer. + * All channels need not be mapped, some can be free also. + */ + { + EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0, + EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1 + } + }; + + +/* Driver Instance Initialization Configuration */ +EDMA3_RM_InstanceInitConfig sampleInstInitConfig = + { + /* Resources owned by Region 1 */ + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0xFFFFFFFFu, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x000000FFu}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0xFFFFFFFFu, 0x00000000u}, + + /* Resources reserved by Region 1 */ + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* resvdDmaChannels */ + /* 31 0 */ + {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0, + /* 63 32 */ + EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 */ + {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0, + /* 63 32 */ + EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1} + }; + + +/* End of File */ + + diff --git a/packages/ti/sdo/edma3/rm/sample/src/bios6_edma3_rm_sample_init.c b/packages/ti/sdo/edma3/rm/sample/src/bios6_edma3_rm_sample_init.c new file mode 100644 index 0000000..5db46b3 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/sample/src/bios6_edma3_rm_sample_init.c @@ -0,0 +1,318 @@ +/******************************************************************************* +**+--------------------------------------------------------------------------+** +**| **** |** +**| **** |** +**| ******o*** |** +**| ********_///_**** |** +**| ***** /_//_/ **** |** +**| ** ** (__/ **** |** +**| ********* |** +**| **** |** +**| *** |** +**| |** +**| Copyright (c) 1998-2006 Texas Instruments Incorporated |** +**| ALL RIGHTS RESERVED |** +**| |** +**| Permission is hereby granted to licensees of Texas Instruments |** +**| Incorporated (TI) products to use this computer program for the sole |** +**| purpose of implementing a licensee product based on TI products. |** +**| No other rights to reproduce, use, or disseminate this computer |** +**| program, whether in part or in whole, are granted. |** +**| |** +**| TI makes no representation or warranties with respect to the |** +**| performance of this computer program, and specifically disclaims |** +**| any responsibility for any damages, special or consequential, |** +**| connected with the use of this program. |** +**| |** +**+--------------------------------------------------------------------------+** +*******************************************************************************/ + +/** \file bios6_edma3_rm_sample_init.c + + \brief Sample Initialization for the EDMA3 RM for BIOS 6 based + applications. It should be MANDATORILY done once before EDMA3 usage. + + (C) Copyright 2006, Texas Instruments, Inc + + \version 1.0 Anuj Aggarwal - Created + + */ + +#include +#include +#include + +#include + +/** @brief EDMA3 RM Handle, used to call all the RM APIs */ +EDMA3_RM_Handle hEdmaResMgr = NULL; + +/** @brief EDMA3 RM Instance specific Semaphore handle */ +static EDMA3_OS_Sem_Handle rmSemHandle = NULL; + + +/** + * EDMA3 TC ISRs which need to be registered with the underlying OS by the user + * (Not all TC error ISRs need to be registered, register only for the + * available Transfer Controllers). + */ +void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) = + { + &lisrEdma3TC0ErrHandler0, + &lisrEdma3TC1ErrHandler0, + &lisrEdma3TC2ErrHandler0, + &lisrEdma3TC3ErrHandler0, + &lisrEdma3TC4ErrHandler0, + &lisrEdma3TC5ErrHandler0, + &lisrEdma3TC6ErrHandler0, + &lisrEdma3TC7ErrHandler0, + }; + + +/** To Register the ISRs with the underlying OS, if required. */ +static void registerEdma3Interrupts (void); +/** To Unregister the ISRs with the underlying OS, if previously registered. */ +static void unregisterEdma3Interrupts (void); + +/* External Global Configuration Structure */ +extern EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams; + +/* External Instance Specific Configuration Structure */ +extern EDMA3_RM_InstanceInitConfig sampleInstInitConfig; + + +/** + * \brief EDMA3 Initialization + * + * This function initializes the EDMA3 RM and registers the + * interrupt handlers. + * + * \return EDMA3_RM_SOK if success, else error code + */ + EDMA3_RM_Result edma3init (void) + { + unsigned int edma3InstanceId = 0; + EDMA3_RM_Param initParam; + EDMA3_RM_Result edma3Result = EDMA3_RM_SOK; + Semaphore_Params semParams; + EDMA3_RM_MiscParam miscParam; + + if (NULL == hEdmaResMgr) + { + /* Configuration structure for the RM */ + initParam.regionId = (EDMA3_RM_RegionId)1u; + initParam.isMaster = TRUE; + initParam.rmInstInitConfig = &sampleInstInitConfig; + initParam.rmSemHandle = NULL; + initParam.regionInitEnable = TRUE; + initParam.gblerrCbParams.gblerrCb = (EDMA3_RM_GblErrCallback)NULL; + initParam.gblerrCbParams.gblerrData = (void *)NULL; + + miscParam.isSlave = FALSE; + + /* Create EDMA3 RM Object first. */ + edma3Result = EDMA3_RM_create(edma3InstanceId, + (EDMA3_RM_GblConfigParams *)&sampleEdma3GblCfgParams, + (void *)&miscParam); + + if (edma3Result != EDMA3_RM_SOK) + { +#ifdef EDMA3_RM_DEBUG + EDMA3_RM_PRINTF("edma3init: EDMA3_RM_create FAILED\r\n"); +#endif + } + else + { + /** + * RM Object created successfully. + * Create a semaphore now for RM instance. + */ + Semaphore_Params_init(&semParams); + + edma3Result = edma3OsSemCreate(1, &semParams, &initParam.rmSemHandle ); + if (edma3Result != EDMA3_RM_SOK) + { +#ifdef EDMA3_RM_DEBUG + EDMA3_RM_PRINTF("edma3init: edma3OsSemCreate FAILED\r\n"); +#endif + } + else + { + /* Save the semaphore handle for future use */ + rmSemHandle = initParam.rmSemHandle; + + /* Open the RM Instance */ + hEdmaResMgr = EDMA3_RM_open (edma3InstanceId, (EDMA3_RM_Param *)&initParam, &edma3Result); + + if(NULL == hEdmaResMgr) + { +#ifdef EDMA3_RM_DEBUG + EDMA3_RM_PRINTF("edma3init: EDMA3_RM_open FAILED\r\n"); +#endif + } + else + { + /** + * Register Interrupt Handlers for various interrupts + * like transfer completion interrupt, CC error + * interrupt, TC error interrupts etc, if required. + */ + registerEdma3Interrupts(); + } + } + } + } + else + { + /* EDMA3 RM already initialized, no need to do that again. */ +#ifdef EDMA3_RM_DEBUG + EDMA3_RM_PRINTF("edma3init: EDMA3 RM Already Initialized...Init failed\r\n"); +#endif + edma3Result = EDMA3_RM_E_INVALID_STATE; + } + + return edma3Result; + } + + +/** To Register the ISRs with the underlying OS, if required. */ +static void registerEdma3Interrupts (void) + { + static UInt32 cookie = 0; + unsigned int numTc = 0; + + /* Disabling the global interrupts */ + cookie = Hwi_disable(); + + /* Enable the Xfer Completion Event Interrupt */ + EventCombiner_dispatchPlug(ccXferCompInt, (EventCombiner_FuncPtr)(&lisrEdma3ComplHandler0), + NULL, 0); + EventCombiner_enableEvent(ccXferCompInt); + + /* Enable the CC Error Event Interrupt */ + EventCombiner_dispatchPlug(ccErrorInt, (EventCombiner_FuncPtr)(&lisrEdma3CCErrHandler0), + NULL, 0); + EventCombiner_enableEvent(ccErrorInt); + + /* Enable the TC Error Event Interrupt, according to the number of TCs. */ + while (numTc < numEdma3Tc) + { + EventCombiner_dispatchPlug(tcErrorInt[numTc], + (EventCombiner_FuncPtr)(ptrEdma3TcIsrHandler[numTc]), + NULL, 0); + EventCombiner_enableEvent(tcErrorInt[numTc]); + numTc++; + } + + + /** + * Enabling the HWI_ID. + * EDMA3 interrupts (transfer completion, CC error etc.) + * correspond to different ECM events (SoC specific). These ECM events come + * under ECM block XXX (handling those specific ECM events). Normally, block + * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events + * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX) + * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this + * mapped HWI_INT YYY, one should use the corresponding bitmask in the + * API C64_enableIER(), in which the YYY bit is SET. + */ + Hwi_enableInterrupt(hwIntXferComp); + Hwi_enableInterrupt(hwIntCcErr); + Hwi_enableInterrupt(hwIntTcErr); + + /* Restore interrupts */ + Hwi_restore(cookie); + } + + +/** + * \brief EDMA3 De-initialization + * + * This function removes the EDMA3 RM Instance and unregisters the + * interrupt handlers. It also deletes the RM Object. + * + * \return EDMA3_RM_SOK if success, else error code + */ + EDMA3_RM_Result edma3deinit (void) + { + unsigned int edmaInstanceId = 0; + EDMA3_RM_Result edma3Result = EDMA3_RM_SOK; + + /* Unregister Interrupt Handlers first */ + unregisterEdma3Interrupts(); + + /* Delete the semaphore */ + edma3Result = edma3OsSemDelete (rmSemHandle); + if (EDMA3_RM_SOK != edma3Result ) + { +#ifdef EDMA3_RM_DEBUG + EDMA3_RM_PRINTF("edma3deinit: edma3OsSemDelete FAILED\r\n"); +#endif + } + else + { + /* Make the semaphore handle as NULL. */ + rmSemHandle = NULL; + + /* Now, close the EDMA3 RM Instance */ + edma3Result = EDMA3_RM_close (hEdmaResMgr, NULL); + if (EDMA3_RM_SOK != edma3Result ) + { +#ifdef EDMA3_RM_DEBUG + EDMA3_RM_PRINTF("edma3deinit: EDMA3_RM_close FAILED\r\n"); +#endif + } + else + { + /* Make the RM handle as NULL. */ + hEdmaResMgr = NULL; + + /* Now, delete the EDMA3 RM Object */ + edma3Result = EDMA3_RM_delete (edmaInstanceId, NULL); + if (EDMA3_RM_SOK != edma3Result ) + { +#ifdef EDMA3_RM_DEBUG + EDMA3_RM_PRINTF("edma3deinit: EDMA3_RM_delete FAILED\r\n"); +#endif + } + else + { +#ifdef EDMA3_RM_DEBUG + EDMA3_RM_PRINTF("edma3deinit: EDMA3 Deinitialization" \ + " Completed...\r\n"); +#endif + } + } + } + + return edma3Result; + } + + +/** To Unregister the ISRs with the underlying OS, if previously registered. */ +static void unregisterEdma3Interrupts (void) + { + static UInt32 cookie = 0; + unsigned int numTc = 0; + + /* Disabling the global interrupts */ + cookie = Hwi_disable(); + + /* Disable the Xfer Completion Event Interrupt */ + EventCombiner_disableEvent(ccXferCompInt); + + /* Disable the CC Error Event Interrupt */ + EventCombiner_disableEvent(ccErrorInt); + + /* Enable the TC Error Event Interrupt, according to the number of TCs. */ + while (numTc < numEdma3Tc) + { + EventCombiner_disableEvent(tcErrorInt[numTc]); + numTc++; + } + + /* Restore interrupts */ + Hwi_restore(cookie); + } + +/* End of File */ diff --git a/packages/ti/sdo/edma3/rm/src/edma3_da830_cfg.c b/packages/ti/sdo/edma3/rm/src/edma3_da830_cfg.c new file mode 100644 index 0000000..f19f31f --- /dev/null +++ b/packages/ti/sdo/edma3/rm/src/edma3_da830_cfg.c @@ -0,0 +1,529 @@ +/****************************************************************************** +**+-------------------------------------------------------------------------+** +**| **** |** +**| **** |** +**| ******o*** |** +**| ********_///_**** |** +**| ***** /_//_/ **** |** +**| ** ** (__/ **** |** +**| ********* |** +**| **** |** +**| *** |** +**| |** +**| Copyright (c) 1998-2006 Texas Instruments Incorporated |** +**| ALL RIGHTS RESERVED |** +**| |** +**| Permission is hereby granted to licensees of Texas Instruments |** +**| Incorporated (TI) products to use this computer program for the sole |** +**| purpose of implementing a licensee product based on TI products. |** +**| No other rights to reproduce, use, or disseminate this computer |** +**| program, whether in part or in whole, are granted. |** +**| |** +**| TI makes no representation or warranties with respect to the |** +**| performance of this computer program, and specifically disclaims |** +**| any responsibility for any damages, special or consequential, |** +**| connected with the use of this program. |** +**| |** +**+-------------------------------------------------------------------------+** +******************************************************************************/ + +/** \file edma3_da830_cfg.c + * \brief EDMA3 Driver Adaptation Configuration File (Soc Specific) for DA8xx + * platform. + * + * This file contains configuration data for adaptation of EDMA3 RM + * + * (C) Copyright 2008, Texas Instruments, Inc + * + * \version 0.1 Anuj Aggarwal - Created + */ + +#include + +/** Total number of DMA Channels supported by the EDMA3 Controller */ +#define NUM_DMA_CHANNELS (32u) +/** Total number of QDMA Channels supported by the EDMA3 Controller */ +#define NUM_QDMA_CHANNELS (8u) +/** Total number of TCCs supported by the EDMA3 Controller */ +#define NUM_TCC (32u) +/** Total number of PaRAM Sets supported by the EDMA3 Controller */ +#define NUM_PARAM_SETS (128u) +/** Total number of Event Queues in the EDMA3 Controller */ +#define NUM_EVENT_QUEUE (2u) +/** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */ +#define NUM_TC (2u) +/** Number of Regions on this EDMA3 controller */ +#define NUM_REGION (4u) + +/** + * \brief Channel mapping existence + * A value of 0 (No channel mapping) implies that there is fixed association + * for a channel number to a parameter entry number or, in other words, + * PaRAM entry n corresponds to channel n. + */ +#define CHANNEL_MAPPING_EXISTENCE (0u) +/** Existence of memory protection feature */ +#define MEM_PROTECTION_EXISTENCE (0u) + +/** Global Register Region of CC Registers */ +#define CC_BASE_ADDRESS (0x01C00000u) +/** Transfer Controller 0 Registers */ +#define TC0_BASE_ADDRESS (0x01C08000u) +/** Transfer Controller 1 Registers */ +#define TC1_BASE_ADDRESS (0x01C08400u) +/** Transfer Controller 2 Registers */ +#define TC2_BASE_ADDRESS NULL +/** Transfer Controller 3 Registers */ +#define TC3_BASE_ADDRESS NULL +/** Transfer Controller 4 Registers */ +#define TC4_BASE_ADDRESS NULL +/** Transfer Controller 5 Registers */ +#define TC5_BASE_ADDRESS NULL +/** Transfer Controller 6 Registers */ +#define TC6_BASE_ADDRESS NULL +/** Transfer Controller 7 Registers */ +#define TC7_BASE_ADDRESS NULL + +/** Interrupt no. for Transfer Completion */ +#define XFER_COMPLETION_INT (8u) +/** Interrupt no. for CC Error */ +#define CC_ERROR_INT (56u) +/** Interrupt no. for TC 0 Error */ +#define TC0_ERROR_INT (57u) +/** Interrupt no. for TC 1 Error */ +#define TC1_ERROR_INT (58u) +/** Interrupt no. for TC 2 Error */ +#define TC2_ERROR_INT (0u) +/** Interrupt no. for TC 3 Error */ +#define TC3_ERROR_INT (0u) +/** Interrupt no. for TC 4 Error */ +#define TC4_ERROR_INT (0u) +/** Interrupt no. for TC 5 Error */ +#define TC5_ERROR_INT (0u) +/** Interrupt no. for TC 6 Error */ +#define TC6_ERROR_INT (0u) +/** Interrupt no. for TC 7 Error */ +#define TC7_ERROR_INT (0u) + +/** + * \brief Mapping of DMA channels 0-31 to Hardware Events from + * various peripherals, which use EDMA for data transfer. + * All channels need not be mapped, some can be free also. + * 1: Mapped + * 0: Not mapped + * + * This mapping will be used to allocate DMA channels when user passes + * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory + * copy). The same mapping is used to allocate the TCC when user passes + * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy). + * + * To allocate more DMA channels or TCCs, one has to modify the event mapping. + */ + /* 31 0 */ +#define DMA_CHANNEL_TO_EVENT_MAPPING_0 (0xCF3FFFFFu) +/** + * EDMA channels 22, 23, 28 & 29 which correspond to GPIO bank interrupts will + * be used for memory-to-memory data transfers, since there are no free dma + * channels. + */ + + +/** + * \brief Mapping of DMA channels 32-63 to Hardware Events from + * various peripherals, which use EDMA for data transfer. + * All channels need not be mapped, some can be free also. + * 1: Mapped + * 0: Not mapped + * + * This mapping will be used to allocate DMA channels when user passes + * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory + * copy). The same mapping is used to allocate the TCC when user passes + * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy). + * + * To allocate more DMA channels or TCCs, one has to modify the event mapping. + */ +/* DMA channels 32-63 DOES NOT exist in DA830. */ +#define DMA_CHANNEL_TO_EVENT_MAPPING_1 (0x0u) + + +EDMA3_RM_GblConfigParams edma3GblCfgParams [EDMA3_MAX_EDMA3_INSTANCES] = +{ + { + /** Total number of DMA Channels supported by the EDMA3 Controller */ + NUM_DMA_CHANNELS, + /** Total number of QDMA Channels supported by the EDMA3 Controller */ + NUM_QDMA_CHANNELS, + /** Total number of TCCs supported by the EDMA3 Controller */ + NUM_TCC, + /** Total number of PaRAM Sets supported by the EDMA3 Controller */ + NUM_PARAM_SETS, + /** Total number of Event Queues in the EDMA3 Controller */ + NUM_EVENT_QUEUE, + /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */ + NUM_TC, + /** Number of Regions on this EDMA3 controller */ + NUM_REGION, + + /** + * \brief Channel mapping existence + * A value of 0 (No channel mapping) implies that there is fixed association + * for a channel number to a parameter entry number or, in other words, + * PaRAM entry n corresponds to channel n. + */ + CHANNEL_MAPPING_EXISTENCE, + + /** Existence of memory protection feature */ + MEM_PROTECTION_EXISTENCE, + + /** Global Register Region of CC Registers */ + (void *)(CC_BASE_ADDRESS), + /** Transfer Controller (TC) Registers */ + { + (void *)(TC0_BASE_ADDRESS), + (void *)(TC1_BASE_ADDRESS), + (void *)(TC2_BASE_ADDRESS), + (void *)(TC3_BASE_ADDRESS), + (void *)(TC4_BASE_ADDRESS), + (void *)(TC5_BASE_ADDRESS), + (void *)(TC6_BASE_ADDRESS), + (void *)(TC7_BASE_ADDRESS) + }, + /** Interrupt no. for Transfer Completion */ + XFER_COMPLETION_INT, + /** Interrupt no. for CC Error */ + CC_ERROR_INT, + /** Interrupt no. for TCs Error */ + { + TC0_ERROR_INT, + TC1_ERROR_INT, + TC2_ERROR_INT, + TC3_ERROR_INT, + TC4_ERROR_INT, + TC5_ERROR_INT, + TC6_ERROR_INT, + TC7_ERROR_INT + }, + + /** + * \brief EDMA3 TC priority setting + * + * User can program the priority of the Event Queues + * at a system-wide level. This means that the user can set the + * priority of an IO initiated by either of the TCs (Transfer Controllers) + * relative to IO initiated by the other bus masters on the + * device (ARM, DSP, USB, etc) + */ + { + 0u, + 1u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u + }, + /** + * \brief To Configure the Threshold level of number of events + * that can be queued up in the Event queues. EDMA3CC error register + * (CCERR) will indicate whether or not at any instant of time the + * number of events queued up in any of the event queues exceeds + * or equals the threshold/watermark value that is set + * in the queue watermark threshold register (QWMTHRA). + */ + { + 16u, + 16u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u + }, + + /** + * \brief To Configure the Default Burst Size (DBS) of TCs. + * An optimally-sized command is defined by the transfer controller + * default burst size (DBS). Different TCs can have different + * DBS values. It is defined in Bytes. + */ + { + 16u, + 16u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u + }, + + /** + * \brief Mapping from each DMA channel to a Parameter RAM set, + * if it exists, otherwise of no use. + */ + { + 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u, + 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u, + 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u, + 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u, + /* DMA channels 32-63 DOES NOT exist in DA830. */ + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS, + EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS + }, + + /** + * \brief Mapping from each DMA channel to a TCC. This specific + * TCC code will be returned when the transfer is completed + * on the mapped channel. + */ + { + 0u, 1u, 2u, 3u, + 4u, 5u, 6u, 7u, + 8u, 9u, 10u, 11u, + 12u, 13u, 14u, 15u, + 16u, 17u, 18u, 19u, + 20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, + 24u, 25u, 26u, 27u, + EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, 30, 31, + /* DMA channels 32-63 DOES NOT exist in DA830. */ + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, + EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC + }, + + /** + * \brief Mapping of DMA channels to Hardware Events from + * various peripherals, which use EDMA for data transfer. + * All channels need not be mapped, some can be free also. + */ + { + DMA_CHANNEL_TO_EVENT_MAPPING_0, + DMA_CHANNEL_TO_EVENT_MAPPING_1 + } + } +}; + + +/* Default RM Instance Initialization Configuration */ +EDMA3_RM_InstanceInitConfig defInstInitConfig [EDMA3_MAX_EDMA3_INSTANCES][NUM_REGION] = +{ + { + { + /* Resources owned by Region 0 */ + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* Resources reserved by Region 0 */ + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + { + /* Resources owned by Region 1 */ + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0xFFFFFFFFu, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x000000FFu}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0xFFFFFFFFu, 0x00000000u}, + + /* Resources reserved by Region 1 */ + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1}, + }, + + { + /* Resources owned by Region 2 */ + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* Resources reserved by Region 2 */ + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + { + /* Resources owned by Region 3 */ + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* Resources reserved by Region 3 */ + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + } + } +}; + +/* End of File */ + + + diff --git a/packages/ti/sdo/edma3/rm/src/edma3_log.h b/packages/ti/sdo/edma3/rm/src/edma3_log.h new file mode 100644 index 0000000..999c65d --- /dev/null +++ b/packages/ti/sdo/edma3/rm/src/edma3_log.h @@ -0,0 +1,233 @@ +/******************************************************************************* +**+--------------------------------------------------------------------------+** +**| **** |** +**| **** |** +**| ******o*** |** +**| ********_///_**** |** +**| ***** /_//_/ **** |** +**| ** ** (__/ **** |** +**| ********* |** +**| **** |** +**| *** |** +**| |** +**| Copyright (c) 1998-2006 Texas Instruments Incorporated |** +**| ALL RIGHTS RESERVED |** +**| |** +**| Permission is hereby granted to licensees of Texas Instruments |** +**| Incorporated (TI) products to use this computer program for the sole |** +**| purpose of implementing a licensee product based on TI products. |** +**| No other rights to reproduce, use, or disseminate this computer |** +**| program, whether in part or in whole, are granted. |** +**| |** +**| TI makes no representation or warranties with respect to the |** +**| performance of this computer program, and specifically disclaims |** +**| any responsibility for any damages, special or consequential, |** +**| connected with the use of this program. |** +**| |** +**+--------------------------------------------------------------------------+** +*******************************************************************************/ + + +/** \file edma3_log.h + \brief EDMA3 logging/tracing service + + This file contains interface for EDMA3 error/event/message logging and + tracing service. + + (C) Copyright 2006, Texas Instruments, Inc + + \author EDMA3 Architecture Team + + \version 1.0 Anant Gole Created + */ + + +#ifndef _EDMA3_LOG_H_ +#define _EDMA3_LOG_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \defgroup EDMA3 Log Service + * + * EDMA3 error/event/message logging/tracing service + */ +/*@{*/ + +/* + Note : This header file is used to BIOS logs only. For porting purposes this + file need to replace EDMA3_LOG_EVENT macro. + + This header file uses log format as defined by Socrates Instrumentation. + Any change in the file will result in incorrect interpretation by Socrates Tool. + + BIOS Log Format +------------------------------------------------------------------------------- +| TimeStamp | Sequence # | Event # | Event Descriptor | Data1 | Data2 | Data3 | +| (2 words) | by BIOS | by BIOS | | | | | +------------------------------------------------------------------------------- + +LogBuffer: A single log buffer called DVTEvent_Log will be used for all event logs +TimeStamp: Automatically inserted by BIOS Log_Printf4. +Sequence #: Automatically inserted by BIOS Log_Printf4. This is used to detect data loss. +Event: Name to uniquely identify event. This is the name that will be used in the visualization. + (Limitation: RTA requires the name to be a static global) +Event Descriptor: The Event Descriptor is created using the EDMA3_DVT_DESC Macro. + This Macro is of the following format (see tables below for EventType and ArgType): + EDMA3_DVT_DESC(EventType, Arg1Type, Arg2Type, Arg3Type) + +Note: Event # is generated by BIOS based on unique String provided as input to "Log_Printf4". +This string is extracted by Sorcates via the map file. + +Note: +1. Only three pieces of data can be included in any log +2. Data needs to be included in the same order as in table. + i.e. if logging INITIATOR, SIZE and CORR then INITIATOR + must be in arg1, CORR in arg2 and SIZE in arg3 + +Example: + +ISRx() +{ + Log_Printf4(&DVTEvent_Log, "ISR1", EDMA3_DVT_DESC(EDMA3_DVT_INT_eSTART, EDMA3_DVT_dNONE, EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)) + : + : + Log_Printf4(&DVTEvent_Log, "ISR1", EDMA3_DVT_DESC(EDMA3_DVT_INT_eEND, EDMA3_DVT_dSIZE, EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE), sizeof(Buffer)) +} + + +*/ +extern far LOG_Obj DVTEvent_Log; +typedef enum +{ + EDMA3_DVT_eINT , /* Interrupt Event. Use this only is logging + that the interrupt occurred. Use INT_START/END + if tracking the entry and exit of interrupt */ + EDMA3_DVT_eINT_START, /* Enter Interrupt service routine */ + + EDMA3_DVT_eINT_END, /* Exit Interrupt service routine */ + + EDMA3_DVT_eFUNC, /* Interrupt Event. Use this only is logging that + the function was called. Use FUNC_START/END if + tracking the entry and exit of function */ + EDMA3_DVT_eFUNC_START, /* Enter function service routine */ + + EDMA3_DVT_eFUNC_END, /* Exit function service routine */ + + EDMA3_DVT_ePACKET_START, /* Start of a Packet */ + + EDMA3_DVT_ePACKET_END, /* End of a Packet */ + + EDMA3_DVT_eDATA_SND, /* An event that has a free running counter value + associated with it */ + EDMA3_DVT_eDATA_SND_START, /* A COUNTER Event that has a corresponding + ENDCOUNTER event */ + EDMA3_DVT_eDATA_SND_END, /* End of a STARTCOUNTER event */ + + EDMA3_DVT_eDATA_RCV, /* An Event that has a value associated with it */ + + EDMA3_DVT_eRCV_START, /* A VALUE event that has a corresponding ENDVALUE + event */ + EDMA3_DVT_eRCV_END, /* End of a STARTVALUE event */ + + EDMA3_DVT_eSMPL_COUNTER, /* Sample some free running counter */ + + EDMA3_DVT_eEVENT, /* Events not explicitly defined above */ + + EDMA3_DVT_eEVENT_START, /* Start of an Event not mentioned in the above list */ + + EDMA3_DVT_eEVENT_END /* End of an Event not mentioned in the above list */ + +} EDMA3_logEventType; + +typedef enum +{ + EDMA3_DVT_dNONE , /* No Data */ + + EDMA3_DVT_dINST, /* ID for this instance of the driver. This is necessary + if separate analysis is required for different instances + of a multiple instance driver. */ + EDMA3_DVT_dINITIATOR, /* ID of the component that initiated this driver request */ + + EDMA3_DVT_dMSG_ID, /* Use to correlate START and END events. This is not + necessary if events are sequenced, i.e. no more than + 1 START is pending at any given time. */ + EDMA3_DVT_dCOUNTER, /* Value of a free running counter */ + + EDMA3_DVT_dSIZE_BYTES, /* Size in number of bytes */ + + EDMA3_DVT_dSIZE_WORDS, /* Size in number of words */ + + EDMA3_DVT_dPADD, /* Program Address */ + + EDMA3_DVT_dDADD, /* Data address */ + + EDMA3_DVT_dDATA, /* Some Data */ + + EDMA3_DVT_dPACKET_ID, /* Packet ID */ + + EDMA3_DVT_dCHANNEL_ID /* Channel ID */ + +} EDMA3_logDataDesc; + + +#define ARG1(arg1) (arg1 << 8) +#define ARG2(arg2) (arg2 << 16) +#define ARG3(arg3) (arg3 << 24) + +#define EDMA3_DVT_DESC(event, arg1, arg2, arg3) (event | ARG1(arg1) | ARG2(arg2) | ARG3(arg3)) + +/* + * EDMA3 Event Log Macro + * + * Macro to log the event + */ +#define EDMA3_LOG_EVENT LOG_printf4 + + +/* Examples : For instrumenting a driver which is working in interrupt mode. + +Driver Write Function: + + Drv_Write(...) + { + EDMA3_LOG_EVENT(hLog, "DRV", EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, EDMA3_DVT_dNONE, EDMA3_DVT_dNONE, EDMA3_DVT_dNONE)); + EDMA3_LOG_EVENT(hLog, "DRV", EDMA3_DVT_DESC(EDMA3_DVT_ePACKET_START, EDMA3_DVT_dPACKET_ID, EDMA3_DVT_dNONE, EDMA3_DVT_dNONE), packetId); + + . + . + EDMA3_LOG_EVENT(hLog, "DRV", EDMA3_DVT_DESC(EDMA3_DVT_eDATA_SND_START, EDMA3_DVT_dNONE, EDMA3_DVT_dNONE, EDMA3_DVT_dNONE)); + . + . + . + + EDMA3_LOG_EVENT(hLog, "DRV", EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, EDMA3_DVT_dSIZE_BYTES, EDMA3_DVT_dNONE, EDMA3_DVT_dNONE), Data Transferred); + } + +Note: In case the driver is asychronous, then the FUNC_END event will be placed before calling + the completion call back. + + + DRV_ISR(...) + { + Case: Intermediate Transfer complete + EDMA3_LOG_EVENT(hLog, "DRV", EDMA3_DVT_DESC(EDMA3_DVT_eDATA_SND_END, EDMA3_DVT_dSIZE_BYTES, EDMA3_DVT_dNONE, EDMA3_DVT_dNONE), Data written to Hardware); + + case: More Data Pending + EDMA3_LOG_EVENT(hLog, "DRV", EDMA3_DVT_DESC(EDMA3_DVT_eDATA_SND_START, EDMA3_DVT_dNONE, EDMA3_DVT_dNONE, EDMA3_DVT_dNONE)); + } +*/ +/*@}*/ + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif /* _EDMA3_LOG_H_ */ diff --git a/packages/ti/sdo/edma3/rm/src/edma3_rl_cc.h b/packages/ti/sdo/edma3/rm/src/edma3_rl_cc.h new file mode 100644 index 0000000..f85f00b --- /dev/null +++ b/packages/ti/sdo/edma3/rm/src/edma3_rl_cc.h @@ -0,0 +1,8055 @@ +/****************************************************************************** +**+-------------------------------------------------------------------------+** +**| **** |** +**| **** |** +**| ******o*** |** +**| ********_///_**** |** +**| ***** /_//_/ **** |** +**| ** ** (__/ **** |** +**| ********* |** +**| **** |** +**| *** |** +**| |** +**| Copyright (c) 1998-2006 Texas Instruments Incorporated |** +**| ALL RIGHTS RESERVED |** +**| |** +**| Permission is hereby granted to licensees of Texas Instruments |** +**| Incorporated (TI) products to use this computer program for the sole |** +**| purpose of implementing a licensee product based on TI products. |** +**| No other rights to reproduce, use, or disseminate this computer |** +**| program, whether in part or in whole, are granted. |** +**| |** +**| TI makes no representation or warranties with respect to the |** +**| performance of this computer program, and specifically disclaims |** +**| any responsibility for any damages, special or consequential, |** +**| connected with the use of this program. |** +**| |** +**+-------------------------------------------------------------------------+** +******************************************************************************/ + +/** \file edma3_rl_cc.h + \brief EDMA3 Channel Controller Register Desciption. + + This file contains the register layer for the EDMA3 Channel Controller. + + (C) Copyright 2006, Texas Instruments, Inc + + \version + 1.0 Anuj Aggarwal - Created + + */ + +#ifndef _EDMA3_RL_CC_H_ +#define _EDMA3_RL_CC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************\ +* Register Overlay Structure for DRA +\**************************************************************************/ +typedef struct { + volatile unsigned int DRAE; + volatile unsigned int DRAEH; +} EDMA3_CCRL_DraRegs; + +/**************************************************************************\ +* Register Overlay Structure for QUEEVTENTRY +\**************************************************************************/ +typedef struct { + volatile unsigned int QUEEVT_ENTRY; +} EDMA3_CCRL_QueevtentryRegs; + +/**************************************************************************\ +* Register Overlay Structure for SHADOW +\**************************************************************************/ +typedef struct { + volatile unsigned int ER; + volatile unsigned int ERH; + volatile unsigned int ECR; + volatile unsigned int ECRH; + volatile unsigned int ESR; + volatile unsigned int ESRH; + volatile unsigned int CER; + volatile unsigned int CERH; + volatile unsigned int EER; + volatile unsigned int EERH; + volatile unsigned int EECR; + volatile unsigned int EECRH; + volatile unsigned int EESR; + volatile unsigned int EESRH; + volatile unsigned int SER; + volatile unsigned int SERH; + volatile unsigned int SECR; + volatile unsigned int SECRH; + volatile unsigned char RSVD0[8]; + volatile unsigned int IER; + volatile unsigned int IERH; + volatile unsigned int IECR; + volatile unsigned int IECRH; + volatile unsigned int IESR; + volatile unsigned int IESRH; + volatile unsigned int IPR; + volatile unsigned int IPRH; + volatile unsigned int ICR; + volatile unsigned int ICRH; + volatile unsigned int IEVAL; + volatile unsigned char RSVD1[4]; + volatile unsigned int QER; + volatile unsigned int QEER; + volatile unsigned int QEECR; + volatile unsigned int QEESR; + volatile unsigned int QSER; + volatile unsigned int QSECR; + volatile unsigned char RSVD2[360]; +} EDMA3_CCRL_ShadowRegs; + +typedef volatile EDMA3_CCRL_ShadowRegs *EDMA3_CCRL_ShadowRegsOvly; + +/**************************************************************************\ +* Register Overlay Structure for PARAMENTRY +\**************************************************************************/ +typedef struct { + volatile unsigned int OPT; + volatile unsigned int SRC; + volatile unsigned int A_B_CNT; + volatile unsigned int DST; + volatile unsigned int SRC_DST_BIDX; + volatile unsigned int LINK_BCNTRLD; + volatile unsigned int SRC_DST_CIDX; + volatile unsigned int CCNT; +} EDMA3_CCRL_ParamentryRegs; +typedef volatile EDMA3_CCRL_ParamentryRegs *EDMA3_CCRL_ParamentryRegsOvly; + +/**************************************************************************\ +* Register Overlay Structure +\**************************************************************************/ +typedef struct { + volatile unsigned int REV; + volatile unsigned int CCCFG; + volatile unsigned char RSVD0[248]; + volatile unsigned int DCHMAP[64]; + volatile unsigned int QCHMAP[8]; + volatile unsigned char RSVD1[32]; + volatile unsigned int DMAQNUM[8]; + volatile unsigned int QDMAQNUM; + volatile unsigned char RSVD2[28]; + volatile unsigned int QUETCMAP; + volatile unsigned int QUEPRI; + volatile unsigned char RSVD3[120]; + volatile unsigned int EMR; + volatile unsigned int EMRH; + volatile unsigned int EMCR; + volatile unsigned int EMCRH; + volatile unsigned int QEMR; + volatile unsigned int QEMCR; + volatile unsigned int CCERR; + volatile unsigned int CCERRCLR; + volatile unsigned int EEVAL; + volatile unsigned char RSVD4[28]; + EDMA3_CCRL_DraRegs DRA[8]; + volatile unsigned int QRAE[8]; + volatile unsigned char RSVD5[96]; + EDMA3_CCRL_QueevtentryRegs QUEEVTENTRY[8][16]; + volatile unsigned int QSTAT[8]; + volatile unsigned int QWMTHRA; + volatile unsigned int QWMTHRB; + volatile unsigned char RSVD6[24]; + volatile unsigned int CCSTAT; + volatile unsigned char RSVD7[188]; + volatile unsigned int AETCTL; + volatile unsigned int AETSTAT; + volatile unsigned int AETCMD; + volatile unsigned char RSVD8[244]; + volatile unsigned int MPFAR; + volatile unsigned int MPFSR; + volatile unsigned int MPFCR; + volatile unsigned int MPPAG; + volatile unsigned int MPPA[8]; + volatile unsigned char RSVD9[2000]; + volatile unsigned int ER; + volatile unsigned int ERH; + volatile unsigned int ECR; + volatile unsigned int ECRH; + volatile unsigned int ESR; + volatile unsigned int ESRH; + volatile unsigned int CER; + volatile unsigned int CERH; + volatile unsigned int EER; + volatile unsigned int EERH; + volatile unsigned int EECR; + volatile unsigned int EECRH; + volatile unsigned int EESR; + volatile unsigned int EESRH; + volatile unsigned int SER; + volatile unsigned int SERH; + volatile unsigned int SECR; + volatile unsigned int SECRH; + volatile unsigned char RSVD10[8]; + volatile unsigned int IER; + volatile unsigned int IERH; + volatile unsigned int IECR; + volatile unsigned int IECRH; + volatile unsigned int IESR; + volatile unsigned int IESRH; + volatile unsigned int IPR; + volatile unsigned int IPRH; + volatile unsigned int ICR; + volatile unsigned int ICRH; + volatile unsigned int IEVAL; + volatile unsigned char RSVD11[4]; + volatile unsigned int QER; + volatile unsigned int QEER; + volatile unsigned int QEECR; + volatile unsigned int QEESR; + volatile unsigned int QSER; + volatile unsigned int QSECR; + volatile unsigned char RSVD12[3944]; + EDMA3_CCRL_ShadowRegs SHADOW[8]; + volatile unsigned char RSVD13[4096]; + EDMA3_CCRL_ParamentryRegs PARAMENTRY[512]; +} EDMA3_CCRL_Regs; + +typedef volatile EDMA3_CCRL_Regs *EDMA3_CCRL_RegsOvly; + + +/**************************************************************************\ +* Field Definition Macros +\**************************************************************************/ + +/* REV */ + +#define EDMA3_CCRL_REV_TYPE_MASK (0x00FF0000u) +#define EDMA3_CCRL_REV_TYPE_SHIFT (0x00000010u) +#define EDMA3_CCRL_REV_TYPE_RESETVAL (0x00000007u) + +#define EDMA3_CCRL_REV_CLASS_MASK (0x0000FF00u) +#define EDMA3_CCRL_REV_CLASS_SHIFT (0x00000008u) +#define EDMA3_CCRL_REV_CLASS_RESETVAL (0x00000004u) + +#define EDMA3_CCRL_REV_RESERVED_MASK (0x000000FFu) +#define EDMA3_CCRL_REV_RESERVED_SHIFT (0x00000000u) +#define EDMA3_CCRL_REV_RESERVED_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_REV_RESETVAL (0x00070400u) + +/* CCCFG */ + +#define EDMA3_CCRL_CCCFG_MP_EXIST_MASK (0x02000000u) +#define EDMA3_CCRL_CCCFG_MP_EXIST_SHIFT (0x00000019u) +#define EDMA3_CCRL_CCCFG_MP_EXIST_RESETVAL (0x00000000u) + +/*----MP_EXIST Tokens----*/ +#define EDMA3_CCRL_CCCFG_MP_EXIST_NONE (0x00000000u) +#define EDMA3_CCRL_CCCFG_MP_EXIST_INCLUDED (0x00000001u) + +#define EDMA3_CCRL_CCCFG_CHMAP_EXIST_MASK (0x01000000u) +#define EDMA3_CCRL_CCCFG_CHMAP_EXIST_SHIFT (0x00000018u) +#define EDMA3_CCRL_CCCFG_CHMAP_EXIST_RESETVAL (0x00000000u) + +/*----CHMAP_EXIST Tokens----*/ +#define EDMA3_CCRL_CCCFG_CHMAP_EXIST_NONE (0x00000000u) +#define EDMA3_CCRL_CCCFG_CHMAP_EXIST_INCLUDED (0x00000001u) + +#define EDMA3_CCRL_CCCFG_NUM_REGN_MASK (0x00300000u) +#define EDMA3_CCRL_CCCFG_NUM_REGN_SHIFT (0x00000014u) +#define EDMA3_CCRL_CCCFG_NUM_REGN_RESETVAL (0x00000000u) + +/*----NUM_REGN Tokens----*/ +#define EDMA3_CCRL_CCCFG_NUM_REGN_0 (0x00000000u) +#define EDMA3_CCRL_CCCFG_NUM_REGN_2 (0x00000001u) +#define EDMA3_CCRL_CCCFG_NUM_REGN_4 (0x00000002u) +#define EDMA3_CCRL_CCCFG_NUM_REGN_8 (0x00000003u) + +#define EDMA3_CCRL_CCCFG_NUM_TC_MASK (0x00070000u) +#define EDMA3_CCRL_CCCFG_NUM_TC_SHIFT (0x00000010u) +#define EDMA3_CCRL_CCCFG_NUM_TC_RESETVAL (0x00000000u) + +/*----NUM_TC Tokens----*/ +#define EDMA3_CCRL_CCCFG_NUM_TC_1 (0x00000000u) +#define EDMA3_CCRL_CCCFG_NUM_TC_2 (0x00000001u) +#define EDMA3_CCRL_CCCFG_NUM_TC_3 (0x00000002u) +#define EDMA3_CCRL_CCCFG_NUM_TC_4 (0x00000003u) +#define EDMA3_CCRL_CCCFG_NUM_TC_5 (0x00000004u) +#define EDMA3_CCRL_CCCFG_NUM_TC_6 (0x00000005u) +#define EDMA3_CCRL_CCCFG_NUM_TC_7 (0x00000006u) +#define EDMA3_CCRL_CCCFG_NUM_TC_8 (0x00000007u) + +#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_MASK (0x00007000u) +#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_RESETVAL (0x00000000u) + +/*----NUM_PAENTRY Tokens----*/ +#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_16 (0x00000000u) +#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_32 (0x00000001u) +#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_64 (0x00000002u) +#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_128 (0x00000003u) +#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_256 (0x00000004u) +#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_512 (0x00000005u) + +#define EDMA3_CCRL_CCCFG_NUM_INTCH_MASK (0x00000700u) +#define EDMA3_CCRL_CCCFG_NUM_INTCH_SHIFT (0x00000008u) +#define EDMA3_CCRL_CCCFG_NUM_INTCH_RESETVAL (0x00000000u) + +/*----NUM_INTCH Tokens----*/ +#define EDMA3_CCRL_CCCFG_NUM_INTCH_8 (0x00000001u) +#define EDMA3_CCRL_CCCFG_NUM_INTCH_16 (0x00000002u) +#define EDMA3_CCRL_CCCFG_NUM_INTCH_32 (0x00000003u) +#define EDMA3_CCRL_CCCFG_NUM_INTCH_64 (0x00000004u) + +#define EDMA3_CCRL_CCCFG_NUM_QDMACH_MASK (0x00000070u) +#define EDMA3_CCRL_CCCFG_NUM_QDMACH_SHIFT (0x00000004u) +#define EDMA3_CCRL_CCCFG_NUM_QDMACH_RESETVAL (0x00000000u) + +/*----NUM_QDMACH Tokens----*/ +#define EDMA3_CCRL_CCCFG_NUM_QDMACH_NONE (0x00000000u) +#define EDMA3_CCRL_CCCFG_NUM_QDMACH_2 (0x00000001u) +#define EDMA3_CCRL_CCCFG_NUM_QDMACH_4 (0x00000002u) +#define EDMA3_CCRL_CCCFG_NUM_QDMACH_6 (0x00000003u) +#define EDMA3_CCRL_CCCFG_NUM_QDMACH_8 (0x00000004u) + +#define EDMA3_CCRL_CCCFG_NUM_DMACH_MASK (0x00000007u) +#define EDMA3_CCRL_CCCFG_NUM_DMACH_SHIFT (0x00000000u) +#define EDMA3_CCRL_CCCFG_NUM_DMACH_RESETVAL (0x00000000u) + +/*----NUM_DMACH Tokens----*/ +#define EDMA3_CCRL_CCCFG_NUM_DMACH_NONE (0x00000000u) +#define EDMA3_CCRL_CCCFG_NUM_DMACH_4 (0x00000001u) +#define EDMA3_CCRL_CCCFG_NUM_DMACH_8 (0x00000002u) +#define EDMA3_CCRL_CCCFG_NUM_DMACH_16 (0x00000003u) +#define EDMA3_CCRL_CCCFG_NUM_DMACH_32 (0x00000004u) +#define EDMA3_CCRL_CCCFG_NUM_DMACH_64 (0x00000005u) + +#define EDMA3_CCRL_CCCFG_RESETVAL (0x00000000u) + +/* DCHMAP */ + +#define EDMA3_CCRL_DCHMAP_PAENTRY_MASK (0x00003FE0u) +#define EDMA3_CCRL_DCHMAP_PAENTRY_SHIFT (0x00000005u) +#define EDMA3_CCRL_DCHMAP_PAENTRY_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DCHMAP_RESETVAL (0x00000000u) + +/* QCHMAP */ + +#define EDMA3_CCRL_QCHMAP_PAENTRY_MASK (0x00003FE0u) +#define EDMA3_CCRL_QCHMAP_PAENTRY_SHIFT (0x00000005u) +#define EDMA3_CCRL_QCHMAP_PAENTRY_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QCHMAP_TRWORD_MASK (0x0000001Cu) +#define EDMA3_CCRL_QCHMAP_TRWORD_SHIFT (0x00000002u) +#define EDMA3_CCRL_QCHMAP_TRWORD_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QCHMAP_RESETVAL (0x00000000u) + +/* DMAQNUM */ + +#define EDMA3_CCRL_DMAQNUM_E7_MASK (0x70000000u) +#define EDMA3_CCRL_DMAQNUM_E7_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_DMAQNUM_E7_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DMAQNUM_E6_MASK (0x07000000u) +#define EDMA3_CCRL_DMAQNUM_E6_SHIFT (0x00000018u) +#define EDMA3_CCRL_DMAQNUM_E6_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DMAQNUM_E5_MASK (0x00700000u) +#define EDMA3_CCRL_DMAQNUM_E5_SHIFT (0x00000014u) +#define EDMA3_CCRL_DMAQNUM_E5_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DMAQNUM_E4_MASK (0x00070000u) +#define EDMA3_CCRL_DMAQNUM_E4_SHIFT (0x00000010u) +#define EDMA3_CCRL_DMAQNUM_E4_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DMAQNUM_E3_MASK (0x00007000u) +#define EDMA3_CCRL_DMAQNUM_E3_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_DMAQNUM_E3_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DMAQNUM_E2_MASK (0x00000700u) +#define EDMA3_CCRL_DMAQNUM_E2_SHIFT (0x00000008u) +#define EDMA3_CCRL_DMAQNUM_E2_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DMAQNUM_E1_MASK (0x00000070u) +#define EDMA3_CCRL_DMAQNUM_E1_SHIFT (0x00000004u) +#define EDMA3_CCRL_DMAQNUM_E1_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DMAQNUM_E0_MASK (0x00000007u) +#define EDMA3_CCRL_DMAQNUM_E0_SHIFT (0x00000000u) +#define EDMA3_CCRL_DMAQNUM_E0_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DMAQNUM_RESETVAL (0x00000000u) + +/* QDMAQNUM */ + +#define EDMA3_CCRL_QDMAQNUM_E7_MASK (0x70000000u) +#define EDMA3_CCRL_QDMAQNUM_E7_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_QDMAQNUM_E7_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QDMAQNUM_E6_MASK (0x07000000u) +#define EDMA3_CCRL_QDMAQNUM_E6_SHIFT (0x00000018u) +#define EDMA3_CCRL_QDMAQNUM_E6_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QDMAQNUM_E5_MASK (0x00700000u) +#define EDMA3_CCRL_QDMAQNUM_E5_SHIFT (0x00000014u) +#define EDMA3_CCRL_QDMAQNUM_E5_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QDMAQNUM_E4_MASK (0x00070000u) +#define EDMA3_CCRL_QDMAQNUM_E4_SHIFT (0x00000010u) +#define EDMA3_CCRL_QDMAQNUM_E4_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QDMAQNUM_E3_MASK (0x00007000u) +#define EDMA3_CCRL_QDMAQNUM_E3_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_QDMAQNUM_E3_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QDMAQNUM_E2_MASK (0x00000700u) +#define EDMA3_CCRL_QDMAQNUM_E2_SHIFT (0x00000008u) +#define EDMA3_CCRL_QDMAQNUM_E2_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QDMAQNUM_E1_MASK (0x00000070u) +#define EDMA3_CCRL_QDMAQNUM_E1_SHIFT (0x00000004u) +#define EDMA3_CCRL_QDMAQNUM_E1_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QDMAQNUM_E0_MASK (0x00000007u) +#define EDMA3_CCRL_QDMAQNUM_E0_SHIFT (0x00000000u) +#define EDMA3_CCRL_QDMAQNUM_E0_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QDMAQNUM_RESETVAL (0x00000000u) + +/* QUETCMAP */ + +#define EDMA3_CCRL_QUETCMAP_TCNUMQ7_MASK (0x70000000u) +#define EDMA3_CCRL_QUETCMAP_TCNUMQ7_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_QUETCMAP_TCNUMQ7_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QUETCMAP_TCNUMQ6_MASK (0x07000000u) +#define EDMA3_CCRL_QUETCMAP_TCNUMQ6_SHIFT (0x00000018u) +#define EDMA3_CCRL_QUETCMAP_TCNUMQ6_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QUETCMAP_TCNUMQ5_MASK (0x00700000u) +#define EDMA3_CCRL_QUETCMAP_TCNUMQ5_SHIFT (0x00000014u) +#define EDMA3_CCRL_QUETCMAP_TCNUMQ5_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QUETCMAP_TCNUMQ4_MASK (0x00070000u) +#define EDMA3_CCRL_QUETCMAP_TCNUMQ4_SHIFT (0x00000010u) +#define EDMA3_CCRL_QUETCMAP_TCNUMQ4_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QUETCMAP_TCNUMQ3_MASK (0x00007000u) +#define EDMA3_CCRL_QUETCMAP_TCNUMQ3_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_QUETCMAP_TCNUMQ3_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QUETCMAP_TCNUMQ2_MASK (0x00000700u) +#define EDMA3_CCRL_QUETCMAP_TCNUMQ2_SHIFT (0x00000008u) +#define EDMA3_CCRL_QUETCMAP_TCNUMQ2_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QUETCMAP_TCNUMQ1_MASK (0x00000070u) +#define EDMA3_CCRL_QUETCMAP_TCNUMQ1_SHIFT (0x00000004u) +#define EDMA3_CCRL_QUETCMAP_TCNUMQ1_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QUETCMAP_TCNUMQ0_MASK (0x00000007u) +#define EDMA3_CCRL_QUETCMAP_TCNUMQ0_SHIFT (0x00000000u) +#define EDMA3_CCRL_QUETCMAP_TCNUMQ0_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QUETCMAP_RESETVAL (0x00000000u) + +/* QUEPRI */ + +#define EDMA3_CCRL_QUEPRI_PRIQ7_MASK (0x70000000u) +#define EDMA3_CCRL_QUEPRI_PRIQ7_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_QUEPRI_PRIQ7_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QUEPRI_PRIQ6_MASK (0x07000000u) +#define EDMA3_CCRL_QUEPRI_PRIQ6_SHIFT (0x00000018u) +#define EDMA3_CCRL_QUEPRI_PRIQ6_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QUEPRI_PRIQ5_MASK (0x00700000u) +#define EDMA3_CCRL_QUEPRI_PRIQ5_SHIFT (0x00000014u) +#define EDMA3_CCRL_QUEPRI_PRIQ5_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QUEPRI_PRIQ4_MASK (0x00070000u) +#define EDMA3_CCRL_QUEPRI_PRIQ4_SHIFT (0x00000010u) +#define EDMA3_CCRL_QUEPRI_PRIQ4_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QUEPRI_PRIQ3_MASK (0x00007000u) +#define EDMA3_CCRL_QUEPRI_PRIQ3_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_QUEPRI_PRIQ3_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QUEPRI_PRIQ2_MASK (0x00000700u) +#define EDMA3_CCRL_QUEPRI_PRIQ2_SHIFT (0x00000008u) +#define EDMA3_CCRL_QUEPRI_PRIQ2_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QUEPRI_PRIQ1_MASK (0x00000070u) +#define EDMA3_CCRL_QUEPRI_PRIQ1_SHIFT (0x00000004u) +#define EDMA3_CCRL_QUEPRI_PRIQ1_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QUEPRI_PRIQ0_MASK (0x00000007u) +#define EDMA3_CCRL_QUEPRI_PRIQ0_SHIFT (0x00000000u) +#define EDMA3_CCRL_QUEPRI_PRIQ0_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QUEPRI_RESETVAL (0x00000000u) + +/* EMR */ + +#define EDMA3_CCRL_EMR_E31_MASK (0x80000000u) +#define EDMA3_CCRL_EMR_E31_SHIFT (0x0000001Fu) +#define EDMA3_CCRL_EMR_E31_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMR_E30_MASK (0x40000000u) +#define EDMA3_CCRL_EMR_E30_SHIFT (0x0000001Eu) +#define EDMA3_CCRL_EMR_E30_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMR_E29_MASK (0x20000000u) +#define EDMA3_CCRL_EMR_E29_SHIFT (0x0000001Du) +#define EDMA3_CCRL_EMR_E29_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMR_E28_MASK (0x10000000u) +#define EDMA3_CCRL_EMR_E28_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_EMR_E28_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMR_E27_MASK (0x08000000u) +#define EDMA3_CCRL_EMR_E27_SHIFT (0x0000001Bu) +#define EDMA3_CCRL_EMR_E27_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMR_E26_MASK (0x04000000u) +#define EDMA3_CCRL_EMR_E26_SHIFT (0x0000001Au) +#define EDMA3_CCRL_EMR_E26_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMR_E25_MASK (0x02000000u) +#define EDMA3_CCRL_EMR_E25_SHIFT (0x00000019u) +#define EDMA3_CCRL_EMR_E25_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMR_E24_MASK (0x01000000u) +#define EDMA3_CCRL_EMR_E24_SHIFT (0x00000018u) +#define EDMA3_CCRL_EMR_E24_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMR_E23_MASK (0x00800000u) +#define EDMA3_CCRL_EMR_E23_SHIFT (0x00000017u) +#define EDMA3_CCRL_EMR_E23_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMR_E22_MASK (0x00400000u) +#define EDMA3_CCRL_EMR_E22_SHIFT (0x00000016u) +#define EDMA3_CCRL_EMR_E22_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMR_E21_MASK (0x00200000u) +#define EDMA3_CCRL_EMR_E21_SHIFT (0x00000015u) +#define EDMA3_CCRL_EMR_E21_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMR_E20_MASK (0x00100000u) +#define EDMA3_CCRL_EMR_E20_SHIFT (0x00000014u) +#define EDMA3_CCRL_EMR_E20_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMR_E19_MASK (0x00080000u) +#define EDMA3_CCRL_EMR_E19_SHIFT (0x00000013u) +#define EDMA3_CCRL_EMR_E19_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMR_E18_MASK (0x00040000u) +#define EDMA3_CCRL_EMR_E18_SHIFT (0x00000012u) +#define EDMA3_CCRL_EMR_E18_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMR_E17_MASK (0x00020000u) +#define EDMA3_CCRL_EMR_E17_SHIFT (0x00000011u) +#define EDMA3_CCRL_EMR_E17_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMR_E16_MASK (0x00010000u) +#define EDMA3_CCRL_EMR_E16_SHIFT (0x00000010u) +#define EDMA3_CCRL_EMR_E16_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMR_E15_MASK (0x00008000u) +#define EDMA3_CCRL_EMR_E15_SHIFT (0x0000000Fu) +#define EDMA3_CCRL_EMR_E15_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMR_E14_MASK (0x00004000u) +#define EDMA3_CCRL_EMR_E14_SHIFT (0x0000000Eu) +#define EDMA3_CCRL_EMR_E14_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMR_E13_MASK (0x00002000u) +#define EDMA3_CCRL_EMR_E13_SHIFT (0x0000000Du) +#define EDMA3_CCRL_EMR_E13_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMR_E12_MASK (0x00001000u) +#define EDMA3_CCRL_EMR_E12_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_EMR_E12_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMR_E11_MASK (0x00000800u) +#define EDMA3_CCRL_EMR_E11_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_EMR_E11_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMR_E10_MASK (0x00000400u) +#define EDMA3_CCRL_EMR_E10_SHIFT (0x0000000Au) +#define EDMA3_CCRL_EMR_E10_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMR_E9_MASK (0x00000200u) +#define EDMA3_CCRL_EMR_E9_SHIFT (0x00000009u) +#define EDMA3_CCRL_EMR_E9_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMR_E8_MASK (0x00000100u) +#define EDMA3_CCRL_EMR_E8_SHIFT (0x00000008u) +#define EDMA3_CCRL_EMR_E8_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMR_E7_MASK (0x00000080u) +#define EDMA3_CCRL_EMR_E7_SHIFT (0x00000007u) +#define EDMA3_CCRL_EMR_E7_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMR_E6_MASK (0x00000040u) +#define EDMA3_CCRL_EMR_E6_SHIFT (0x00000006u) +#define EDMA3_CCRL_EMR_E6_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMR_E5_MASK (0x00000020u) +#define EDMA3_CCRL_EMR_E5_SHIFT (0x00000005u) +#define EDMA3_CCRL_EMR_E5_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMR_E4_MASK (0x00000010u) +#define EDMA3_CCRL_EMR_E4_SHIFT (0x00000004u) +#define EDMA3_CCRL_EMR_E4_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMR_E3_MASK (0x00000008u) +#define EDMA3_CCRL_EMR_E3_SHIFT (0x00000003u) +#define EDMA3_CCRL_EMR_E3_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMR_E2_MASK (0x00000004u) +#define EDMA3_CCRL_EMR_E2_SHIFT (0x00000002u) +#define EDMA3_CCRL_EMR_E2_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMR_E1_MASK (0x00000002u) +#define EDMA3_CCRL_EMR_E1_SHIFT (0x00000001u) +#define EDMA3_CCRL_EMR_E1_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMR_E0_MASK (0x00000001u) +#define EDMA3_CCRL_EMR_E0_SHIFT (0x00000000u) +#define EDMA3_CCRL_EMR_E0_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMR_RESETVAL (0x00000000u) + +/* EMRH */ + +#define EDMA3_CCRL_EMRH_E63_MASK (0x80000000u) +#define EDMA3_CCRL_EMRH_E63_SHIFT (0x0000001Fu) +#define EDMA3_CCRL_EMRH_E63_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMRH_E62_MASK (0x40000000u) +#define EDMA3_CCRL_EMRH_E62_SHIFT (0x0000001Eu) +#define EDMA3_CCRL_EMRH_E62_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMRH_E61_MASK (0x20000000u) +#define EDMA3_CCRL_EMRH_E61_SHIFT (0x0000001Du) +#define EDMA3_CCRL_EMRH_E61_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMRH_E60_MASK (0x10000000u) +#define EDMA3_CCRL_EMRH_E60_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_EMRH_E60_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMRH_E59_MASK (0x08000000u) +#define EDMA3_CCRL_EMRH_E59_SHIFT (0x0000001Bu) +#define EDMA3_CCRL_EMRH_E59_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMRH_E58_MASK (0x04000000u) +#define EDMA3_CCRL_EMRH_E58_SHIFT (0x0000001Au) +#define EDMA3_CCRL_EMRH_E58_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMRH_E57_MASK (0x02000000u) +#define EDMA3_CCRL_EMRH_E57_SHIFT (0x00000019u) +#define EDMA3_CCRL_EMRH_E57_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMRH_E56_MASK (0x01000000u) +#define EDMA3_CCRL_EMRH_E56_SHIFT (0x00000018u) +#define EDMA3_CCRL_EMRH_E56_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMRH_E55_MASK (0x00800000u) +#define EDMA3_CCRL_EMRH_E55_SHIFT (0x00000017u) +#define EDMA3_CCRL_EMRH_E55_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMRH_E54_MASK (0x00400000u) +#define EDMA3_CCRL_EMRH_E54_SHIFT (0x00000016u) +#define EDMA3_CCRL_EMRH_E54_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMRH_E53_MASK (0x00200000u) +#define EDMA3_CCRL_EMRH_E53_SHIFT (0x00000015u) +#define EDMA3_CCRL_EMRH_E53_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMRH_E52_MASK (0x00100000u) +#define EDMA3_CCRL_EMRH_E52_SHIFT (0x00000014u) +#define EDMA3_CCRL_EMRH_E52_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMRH_E51_MASK (0x00080000u) +#define EDMA3_CCRL_EMRH_E51_SHIFT (0x00000013u) +#define EDMA3_CCRL_EMRH_E51_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMRH_E50_MASK (0x00040000u) +#define EDMA3_CCRL_EMRH_E50_SHIFT (0x00000012u) +#define EDMA3_CCRL_EMRH_E50_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMRH_E49_MASK (0x00020000u) +#define EDMA3_CCRL_EMRH_E49_SHIFT (0x00000011u) +#define EDMA3_CCRL_EMRH_E49_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMRH_E48_MASK (0x00010000u) +#define EDMA3_CCRL_EMRH_E48_SHIFT (0x00000010u) +#define EDMA3_CCRL_EMRH_E48_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMRH_E47_MASK (0x00008000u) +#define EDMA3_CCRL_EMRH_E47_SHIFT (0x0000000Fu) +#define EDMA3_CCRL_EMRH_E47_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMRH_E46_MASK (0x00004000u) +#define EDMA3_CCRL_EMRH_E46_SHIFT (0x0000000Eu) +#define EDMA3_CCRL_EMRH_E46_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMRH_E45_MASK (0x00002000u) +#define EDMA3_CCRL_EMRH_E45_SHIFT (0x0000000Du) +#define EDMA3_CCRL_EMRH_E45_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMRH_E44_MASK (0x00001000u) +#define EDMA3_CCRL_EMRH_E44_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_EMRH_E44_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMRH_E43_MASK (0x00000800u) +#define EDMA3_CCRL_EMRH_E43_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_EMRH_E43_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMRH_E42_MASK (0x00000400u) +#define EDMA3_CCRL_EMRH_E42_SHIFT (0x0000000Au) +#define EDMA3_CCRL_EMRH_E42_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMRH_E41_MASK (0x00000200u) +#define EDMA3_CCRL_EMRH_E41_SHIFT (0x00000009u) +#define EDMA3_CCRL_EMRH_E41_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMRH_E40_MASK (0x00000100u) +#define EDMA3_CCRL_EMRH_E40_SHIFT (0x00000008u) +#define EDMA3_CCRL_EMRH_E40_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMRH_E39_MASK (0x00000080u) +#define EDMA3_CCRL_EMRH_E39_SHIFT (0x00000007u) +#define EDMA3_CCRL_EMRH_E39_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMRH_E38_MASK (0x00000040u) +#define EDMA3_CCRL_EMRH_E38_SHIFT (0x00000006u) +#define EDMA3_CCRL_EMRH_E38_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMRH_E37_MASK (0x00000020u) +#define EDMA3_CCRL_EMRH_E37_SHIFT (0x00000005u) +#define EDMA3_CCRL_EMRH_E37_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMRH_E36_MASK (0x00000010u) +#define EDMA3_CCRL_EMRH_E36_SHIFT (0x00000004u) +#define EDMA3_CCRL_EMRH_E36_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMRH_E35_MASK (0x00000008u) +#define EDMA3_CCRL_EMRH_E35_SHIFT (0x00000003u) +#define EDMA3_CCRL_EMRH_E35_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMRH_E34_MASK (0x00000004u) +#define EDMA3_CCRL_EMRH_E34_SHIFT (0x00000002u) +#define EDMA3_CCRL_EMRH_E34_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMRH_E33_MASK (0x00000002u) +#define EDMA3_CCRL_EMRH_E33_SHIFT (0x00000001u) +#define EDMA3_CCRL_EMRH_E33_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMRH_E32_MASK (0x00000001u) +#define EDMA3_CCRL_EMRH_E32_SHIFT (0x00000000u) +#define EDMA3_CCRL_EMRH_E32_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMRH_RESETVAL (0x00000000u) + +/* EMCR */ + +#define EDMA3_CCRL_EMCR_E31_MASK (0x80000000u) +#define EDMA3_CCRL_EMCR_E31_SHIFT (0x0000001Fu) +#define EDMA3_CCRL_EMCR_E31_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCR_E30_MASK (0x40000000u) +#define EDMA3_CCRL_EMCR_E30_SHIFT (0x0000001Eu) +#define EDMA3_CCRL_EMCR_E30_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCR_E29_MASK (0x20000000u) +#define EDMA3_CCRL_EMCR_E29_SHIFT (0x0000001Du) +#define EDMA3_CCRL_EMCR_E29_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCR_E28_MASK (0x10000000u) +#define EDMA3_CCRL_EMCR_E28_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_EMCR_E28_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCR_E27_MASK (0x08000000u) +#define EDMA3_CCRL_EMCR_E27_SHIFT (0x0000001Bu) +#define EDMA3_CCRL_EMCR_E27_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCR_E26_MASK (0x04000000u) +#define EDMA3_CCRL_EMCR_E26_SHIFT (0x0000001Au) +#define EDMA3_CCRL_EMCR_E26_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCR_E25_MASK (0x02000000u) +#define EDMA3_CCRL_EMCR_E25_SHIFT (0x00000019u) +#define EDMA3_CCRL_EMCR_E25_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCR_E24_MASK (0x01000000u) +#define EDMA3_CCRL_EMCR_E24_SHIFT (0x00000018u) +#define EDMA3_CCRL_EMCR_E24_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCR_E23_MASK (0x00800000u) +#define EDMA3_CCRL_EMCR_E23_SHIFT (0x00000017u) +#define EDMA3_CCRL_EMCR_E23_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCR_E22_MASK (0x00400000u) +#define EDMA3_CCRL_EMCR_E22_SHIFT (0x00000016u) +#define EDMA3_CCRL_EMCR_E22_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCR_E21_MASK (0x00200000u) +#define EDMA3_CCRL_EMCR_E21_SHIFT (0x00000015u) +#define EDMA3_CCRL_EMCR_E21_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCR_E20_MASK (0x00100000u) +#define EDMA3_CCRL_EMCR_E20_SHIFT (0x00000014u) +#define EDMA3_CCRL_EMCR_E20_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCR_E19_MASK (0x00080000u) +#define EDMA3_CCRL_EMCR_E19_SHIFT (0x00000013u) +#define EDMA3_CCRL_EMCR_E19_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCR_E18_MASK (0x00040000u) +#define EDMA3_CCRL_EMCR_E18_SHIFT (0x00000012u) +#define EDMA3_CCRL_EMCR_E18_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCR_E17_MASK (0x00020000u) +#define EDMA3_CCRL_EMCR_E17_SHIFT (0x00000011u) +#define EDMA3_CCRL_EMCR_E17_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCR_E16_MASK (0x00010000u) +#define EDMA3_CCRL_EMCR_E16_SHIFT (0x00000010u) +#define EDMA3_CCRL_EMCR_E16_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCR_E15_MASK (0x00008000u) +#define EDMA3_CCRL_EMCR_E15_SHIFT (0x0000000Fu) +#define EDMA3_CCRL_EMCR_E15_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCR_E14_MASK (0x00004000u) +#define EDMA3_CCRL_EMCR_E14_SHIFT (0x0000000Eu) +#define EDMA3_CCRL_EMCR_E14_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCR_E13_MASK (0x00002000u) +#define EDMA3_CCRL_EMCR_E13_SHIFT (0x0000000Du) +#define EDMA3_CCRL_EMCR_E13_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCR_E12_MASK (0x00001000u) +#define EDMA3_CCRL_EMCR_E12_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_EMCR_E12_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCR_E11_MASK (0x00000800u) +#define EDMA3_CCRL_EMCR_E11_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_EMCR_E11_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCR_E10_MASK (0x00000400u) +#define EDMA3_CCRL_EMCR_E10_SHIFT (0x0000000Au) +#define EDMA3_CCRL_EMCR_E10_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCR_E9_MASK (0x00000200u) +#define EDMA3_CCRL_EMCR_E9_SHIFT (0x00000009u) +#define EDMA3_CCRL_EMCR_E9_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCR_E8_MASK (0x00000100u) +#define EDMA3_CCRL_EMCR_E8_SHIFT (0x00000008u) +#define EDMA3_CCRL_EMCR_E8_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCR_E7_MASK (0x00000080u) +#define EDMA3_CCRL_EMCR_E7_SHIFT (0x00000007u) +#define EDMA3_CCRL_EMCR_E7_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCR_E6_MASK (0x00000040u) +#define EDMA3_CCRL_EMCR_E6_SHIFT (0x00000006u) +#define EDMA3_CCRL_EMCR_E6_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCR_E5_MASK (0x00000020u) +#define EDMA3_CCRL_EMCR_E5_SHIFT (0x00000005u) +#define EDMA3_CCRL_EMCR_E5_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCR_E4_MASK (0x00000010u) +#define EDMA3_CCRL_EMCR_E4_SHIFT (0x00000004u) +#define EDMA3_CCRL_EMCR_E4_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCR_E3_MASK (0x00000008u) +#define EDMA3_CCRL_EMCR_E3_SHIFT (0x00000003u) +#define EDMA3_CCRL_EMCR_E3_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCR_E2_MASK (0x00000004u) +#define EDMA3_CCRL_EMCR_E2_SHIFT (0x00000002u) +#define EDMA3_CCRL_EMCR_E2_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCR_E1_MASK (0x00000002u) +#define EDMA3_CCRL_EMCR_E1_SHIFT (0x00000001u) +#define EDMA3_CCRL_EMCR_E1_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCR_E0_MASK (0x00000001u) +#define EDMA3_CCRL_EMCR_E0_SHIFT (0x00000000u) +#define EDMA3_CCRL_EMCR_E0_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCR_RESETVAL (0x00000000u) + +/* EMCRH */ + +#define EDMA3_CCRL_EMCRH_E63_MASK (0x80000000u) +#define EDMA3_CCRL_EMCRH_E63_SHIFT (0x0000001Fu) +#define EDMA3_CCRL_EMCRH_E63_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCRH_E62_MASK (0x40000000u) +#define EDMA3_CCRL_EMCRH_E62_SHIFT (0x0000001Eu) +#define EDMA3_CCRL_EMCRH_E62_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCRH_E61_MASK (0x20000000u) +#define EDMA3_CCRL_EMCRH_E61_SHIFT (0x0000001Du) +#define EDMA3_CCRL_EMCRH_E61_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCRH_E60_MASK (0x10000000u) +#define EDMA3_CCRL_EMCRH_E60_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_EMCRH_E60_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCRH_E59_MASK (0x08000000u) +#define EDMA3_CCRL_EMCRH_E59_SHIFT (0x0000001Bu) +#define EDMA3_CCRL_EMCRH_E59_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCRH_E58_MASK (0x04000000u) +#define EDMA3_CCRL_EMCRH_E58_SHIFT (0x0000001Au) +#define EDMA3_CCRL_EMCRH_E58_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCRH_E57_MASK (0x02000000u) +#define EDMA3_CCRL_EMCRH_E57_SHIFT (0x00000019u) +#define EDMA3_CCRL_EMCRH_E57_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCRH_E56_MASK (0x01000000u) +#define EDMA3_CCRL_EMCRH_E56_SHIFT (0x00000018u) +#define EDMA3_CCRL_EMCRH_E56_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCRH_E55_MASK (0x00800000u) +#define EDMA3_CCRL_EMCRH_E55_SHIFT (0x00000017u) +#define EDMA3_CCRL_EMCRH_E55_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCRH_E54_MASK (0x00400000u) +#define EDMA3_CCRL_EMCRH_E54_SHIFT (0x00000016u) +#define EDMA3_CCRL_EMCRH_E54_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCRH_E53_MASK (0x00200000u) +#define EDMA3_CCRL_EMCRH_E53_SHIFT (0x00000015u) +#define EDMA3_CCRL_EMCRH_E53_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCRH_E52_MASK (0x00100000u) +#define EDMA3_CCRL_EMCRH_E52_SHIFT (0x00000014u) +#define EDMA3_CCRL_EMCRH_E52_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCRH_E51_MASK (0x00080000u) +#define EDMA3_CCRL_EMCRH_E51_SHIFT (0x00000013u) +#define EDMA3_CCRL_EMCRH_E51_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCRH_E50_MASK (0x00040000u) +#define EDMA3_CCRL_EMCRH_E50_SHIFT (0x00000012u) +#define EDMA3_CCRL_EMCRH_E50_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCRH_E49_MASK (0x00020000u) +#define EDMA3_CCRL_EMCRH_E49_SHIFT (0x00000011u) +#define EDMA3_CCRL_EMCRH_E49_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCRH_E48_MASK (0x00010000u) +#define EDMA3_CCRL_EMCRH_E48_SHIFT (0x00000010u) +#define EDMA3_CCRL_EMCRH_E48_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCRH_E47_MASK (0x00008000u) +#define EDMA3_CCRL_EMCRH_E47_SHIFT (0x0000000Fu) +#define EDMA3_CCRL_EMCRH_E47_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCRH_E46_MASK (0x00004000u) +#define EDMA3_CCRL_EMCRH_E46_SHIFT (0x0000000Eu) +#define EDMA3_CCRL_EMCRH_E46_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCRH_E45_MASK (0x00002000u) +#define EDMA3_CCRL_EMCRH_E45_SHIFT (0x0000000Du) +#define EDMA3_CCRL_EMCRH_E45_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCRH_E44_MASK (0x00001000u) +#define EDMA3_CCRL_EMCRH_E44_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_EMCRH_E44_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCRH_E43_MASK (0x00000800u) +#define EDMA3_CCRL_EMCRH_E43_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_EMCRH_E43_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCRH_E42_MASK (0x00000400u) +#define EDMA3_CCRL_EMCRH_E42_SHIFT (0x0000000Au) +#define EDMA3_CCRL_EMCRH_E42_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCRH_E41_MASK (0x00000200u) +#define EDMA3_CCRL_EMCRH_E41_SHIFT (0x00000009u) +#define EDMA3_CCRL_EMCRH_E41_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCRH_E40_MASK (0x00000100u) +#define EDMA3_CCRL_EMCRH_E40_SHIFT (0x00000008u) +#define EDMA3_CCRL_EMCRH_E40_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCRH_E39_MASK (0x00000080u) +#define EDMA3_CCRL_EMCRH_E39_SHIFT (0x00000007u) +#define EDMA3_CCRL_EMCRH_E39_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCRH_E38_MASK (0x00000040u) +#define EDMA3_CCRL_EMCRH_E38_SHIFT (0x00000006u) +#define EDMA3_CCRL_EMCRH_E38_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCRH_E37_MASK (0x00000020u) +#define EDMA3_CCRL_EMCRH_E37_SHIFT (0x00000005u) +#define EDMA3_CCRL_EMCRH_E37_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCRH_E36_MASK (0x00000010u) +#define EDMA3_CCRL_EMCRH_E36_SHIFT (0x00000004u) +#define EDMA3_CCRL_EMCRH_E36_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCRH_E35_MASK (0x00000008u) +#define EDMA3_CCRL_EMCRH_E35_SHIFT (0x00000003u) +#define EDMA3_CCRL_EMCRH_E35_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCRH_E34_MASK (0x00000004u) +#define EDMA3_CCRL_EMCRH_E34_SHIFT (0x00000002u) +#define EDMA3_CCRL_EMCRH_E34_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCRH_E33_MASK (0x00000002u) +#define EDMA3_CCRL_EMCRH_E33_SHIFT (0x00000001u) +#define EDMA3_CCRL_EMCRH_E33_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCRH_E32_MASK (0x00000001u) +#define EDMA3_CCRL_EMCRH_E32_SHIFT (0x00000000u) +#define EDMA3_CCRL_EMCRH_E32_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EMCRH_RESETVAL (0x00000000u) + +/* QEMR */ + +#define EDMA3_CCRL_QEMR_E7_MASK (0x00000080u) +#define EDMA3_CCRL_QEMR_E7_SHIFT (0x00000007u) +#define EDMA3_CCRL_QEMR_E7_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QEMR_E6_MASK (0x00000040u) +#define EDMA3_CCRL_QEMR_E6_SHIFT (0x00000006u) +#define EDMA3_CCRL_QEMR_E6_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QEMR_E5_MASK (0x00000020u) +#define EDMA3_CCRL_QEMR_E5_SHIFT (0x00000005u) +#define EDMA3_CCRL_QEMR_E5_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QEMR_E4_MASK (0x00000010u) +#define EDMA3_CCRL_QEMR_E4_SHIFT (0x00000004u) +#define EDMA3_CCRL_QEMR_E4_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QEMR_E3_MASK (0x00000008u) +#define EDMA3_CCRL_QEMR_E3_SHIFT (0x00000003u) +#define EDMA3_CCRL_QEMR_E3_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QEMR_E2_MASK (0x00000004u) +#define EDMA3_CCRL_QEMR_E2_SHIFT (0x00000002u) +#define EDMA3_CCRL_QEMR_E2_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QEMR_E1_MASK (0x00000002u) +#define EDMA3_CCRL_QEMR_E1_SHIFT (0x00000001u) +#define EDMA3_CCRL_QEMR_E1_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QEMR_E0_MASK (0x00000001u) +#define EDMA3_CCRL_QEMR_E0_SHIFT (0x00000000u) +#define EDMA3_CCRL_QEMR_E0_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QEMR_RESETVAL (0x00000000u) + +/* QEMCR */ + +#define EDMA3_CCRL_QEMCR_E7_MASK (0x00000080u) +#define EDMA3_CCRL_QEMCR_E7_SHIFT (0x00000007u) +#define EDMA3_CCRL_QEMCR_E7_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QEMCR_E6_MASK (0x00000040u) +#define EDMA3_CCRL_QEMCR_E6_SHIFT (0x00000006u) +#define EDMA3_CCRL_QEMCR_E6_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QEMCR_E5_MASK (0x00000020u) +#define EDMA3_CCRL_QEMCR_E5_SHIFT (0x00000005u) +#define EDMA3_CCRL_QEMCR_E5_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QEMCR_E4_MASK (0x00000010u) +#define EDMA3_CCRL_QEMCR_E4_SHIFT (0x00000004u) +#define EDMA3_CCRL_QEMCR_E4_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QEMCR_E3_MASK (0x00000008u) +#define EDMA3_CCRL_QEMCR_E3_SHIFT (0x00000003u) +#define EDMA3_CCRL_QEMCR_E3_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QEMCR_E2_MASK (0x00000004u) +#define EDMA3_CCRL_QEMCR_E2_SHIFT (0x00000002u) +#define EDMA3_CCRL_QEMCR_E2_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QEMCR_E1_MASK (0x00000002u) +#define EDMA3_CCRL_QEMCR_E1_SHIFT (0x00000001u) +#define EDMA3_CCRL_QEMCR_E1_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QEMCR_E0_MASK (0x00000001u) +#define EDMA3_CCRL_QEMCR_E0_SHIFT (0x00000000u) +#define EDMA3_CCRL_QEMCR_E0_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QEMCR_RESETVAL (0x00000000u) + +/* CCERR */ + +#define EDMA3_CCRL_CCERR_TCCERR_MASK (0x00010000u) +#define EDMA3_CCRL_CCERR_TCCERR_SHIFT (0x00000010u) +#define EDMA3_CCRL_CCERR_TCCERR_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CCERR_QTHRXCD7_MASK (0x00000080u) +#define EDMA3_CCRL_CCERR_QTHRXCD7_SHIFT (0x00000007u) +#define EDMA3_CCRL_CCERR_QTHRXCD7_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CCERR_QTHRXCD6_MASK (0x00000040u) +#define EDMA3_CCRL_CCERR_QTHRXCD6_SHIFT (0x00000006u) +#define EDMA3_CCRL_CCERR_QTHRXCD6_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CCERR_QTHRXCD5_MASK (0x00000020u) +#define EDMA3_CCRL_CCERR_QTHRXCD5_SHIFT (0x00000005u) +#define EDMA3_CCRL_CCERR_QTHRXCD5_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CCERR_QTHRXCD4_MASK (0x00000010u) +#define EDMA3_CCRL_CCERR_QTHRXCD4_SHIFT (0x00000004u) +#define EDMA3_CCRL_CCERR_QTHRXCD4_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CCERR_QTHRXCD3_MASK (0x00000008u) +#define EDMA3_CCRL_CCERR_QTHRXCD3_SHIFT (0x00000003u) +#define EDMA3_CCRL_CCERR_QTHRXCD3_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CCERR_QTHRXCD2_MASK (0x00000004u) +#define EDMA3_CCRL_CCERR_QTHRXCD2_SHIFT (0x00000002u) +#define EDMA3_CCRL_CCERR_QTHRXCD2_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CCERR_QTHRXCD1_MASK (0x00000002u) +#define EDMA3_CCRL_CCERR_QTHRXCD1_SHIFT (0x00000001u) +#define EDMA3_CCRL_CCERR_QTHRXCD1_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CCERR_QTHRXCD0_MASK (0x00000001u) +#define EDMA3_CCRL_CCERR_QTHRXCD0_SHIFT (0x00000000u) +#define EDMA3_CCRL_CCERR_QTHRXCD0_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CCERR_RESETVAL (0x00000000u) + +/* CCERRCLR */ + +#define EDMA3_CCRL_CCERRCLR_TCCERR_MASK (0x00010000u) +#define EDMA3_CCRL_CCERRCLR_TCCERR_SHIFT (0x00000010u) +#define EDMA3_CCRL_CCERRCLR_TCCERR_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CCERRCLR_QTHRXCD7_MASK (0x00000080u) +#define EDMA3_CCRL_CCERRCLR_QTHRXCD7_SHIFT (0x00000007u) +#define EDMA3_CCRL_CCERRCLR_QTHRXCD7_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CCERRCLR_QTHRXCD6_MASK (0x00000040u) +#define EDMA3_CCRL_CCERRCLR_QTHRXCD6_SHIFT (0x00000006u) +#define EDMA3_CCRL_CCERRCLR_QTHRXCD6_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CCERRCLR_QTHRXCD5_MASK (0x00000020u) +#define EDMA3_CCRL_CCERRCLR_QTHRXCD5_SHIFT (0x00000005u) +#define EDMA3_CCRL_CCERRCLR_QTHRXCD5_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CCERRCLR_QTHRXCD4_MASK (0x00000010u) +#define EDMA3_CCRL_CCERRCLR_QTHRXCD4_SHIFT (0x00000004u) +#define EDMA3_CCRL_CCERRCLR_QTHRXCD4_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CCERRCLR_QTHRXCD3_MASK (0x00000008u) +#define EDMA3_CCRL_CCERRCLR_QTHRXCD3_SHIFT (0x00000003u) +#define EDMA3_CCRL_CCERRCLR_QTHRXCD3_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CCERRCLR_QTHRXCD2_MASK (0x00000004u) +#define EDMA3_CCRL_CCERRCLR_QTHRXCD2_SHIFT (0x00000002u) +#define EDMA3_CCRL_CCERRCLR_QTHRXCD2_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CCERRCLR_QTHRXCD1_MASK (0x00000002u) +#define EDMA3_CCRL_CCERRCLR_QTHRXCD1_SHIFT (0x00000001u) +#define EDMA3_CCRL_CCERRCLR_QTHRXCD1_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CCERRCLR_QTHRXCD0_MASK (0x00000001u) +#define EDMA3_CCRL_CCERRCLR_QTHRXCD0_SHIFT (0x00000000u) +#define EDMA3_CCRL_CCERRCLR_QTHRXCD0_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CCERRCLR_RESETVAL (0x00000000u) + +/* EEVAL */ + +#define EDMA3_CCRL_EEVAL_SET_MASK (0x00000002u) +#define EDMA3_CCRL_EEVAL_SET_SHIFT (0x00000001u) +#define EDMA3_CCRL_EEVAL_SET_RESETVAL (0x00000000u) + +/*----SET Tokens----*/ +#define EDMA3_CCRL_EEVAL_SET_SET (0x00000001u) + +#define EDMA3_CCRL_EEVAL_EVAL_MASK (0x00000001u) +#define EDMA3_CCRL_EEVAL_EVAL_SHIFT (0x00000000u) +#define EDMA3_CCRL_EEVAL_EVAL_RESETVAL (0x00000000u) + +/*----EVAL Tokens----*/ +#define EDMA3_CCRL_EEVAL_EVAL_EVAL (0x00000001u) + +#define EDMA3_CCRL_EEVAL_RESETVAL (0x00000000u) + +/* DRAE */ + +#define EDMA3_CCRL_DRAE_E31_MASK (0x80000000u) +#define EDMA3_CCRL_DRAE_E31_SHIFT (0x0000001Fu) +#define EDMA3_CCRL_DRAE_E31_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAE_E30_MASK (0x40000000u) +#define EDMA3_CCRL_DRAE_E30_SHIFT (0x0000001Eu) +#define EDMA3_CCRL_DRAE_E30_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAE_E29_MASK (0x20000000u) +#define EDMA3_CCRL_DRAE_E29_SHIFT (0x0000001Du) +#define EDMA3_CCRL_DRAE_E29_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAE_E28_MASK (0x10000000u) +#define EDMA3_CCRL_DRAE_E28_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_DRAE_E28_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAE_E27_MASK (0x08000000u) +#define EDMA3_CCRL_DRAE_E27_SHIFT (0x0000001Bu) +#define EDMA3_CCRL_DRAE_E27_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAE_E26_MASK (0x04000000u) +#define EDMA3_CCRL_DRAE_E26_SHIFT (0x0000001Au) +#define EDMA3_CCRL_DRAE_E26_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAE_E25_MASK (0x02000000u) +#define EDMA3_CCRL_DRAE_E25_SHIFT (0x00000019u) +#define EDMA3_CCRL_DRAE_E25_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAE_E24_MASK (0x01000000u) +#define EDMA3_CCRL_DRAE_E24_SHIFT (0x00000018u) +#define EDMA3_CCRL_DRAE_E24_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAE_E23_MASK (0x00800000u) +#define EDMA3_CCRL_DRAE_E23_SHIFT (0x00000017u) +#define EDMA3_CCRL_DRAE_E23_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAE_E22_MASK (0x00400000u) +#define EDMA3_CCRL_DRAE_E22_SHIFT (0x00000016u) +#define EDMA3_CCRL_DRAE_E22_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAE_E21_MASK (0x00200000u) +#define EDMA3_CCRL_DRAE_E21_SHIFT (0x00000015u) +#define EDMA3_CCRL_DRAE_E21_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAE_E20_MASK (0x00100000u) +#define EDMA3_CCRL_DRAE_E20_SHIFT (0x00000014u) +#define EDMA3_CCRL_DRAE_E20_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAE_E19_MASK (0x00080000u) +#define EDMA3_CCRL_DRAE_E19_SHIFT (0x00000013u) +#define EDMA3_CCRL_DRAE_E19_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAE_E18_MASK (0x00040000u) +#define EDMA3_CCRL_DRAE_E18_SHIFT (0x00000012u) +#define EDMA3_CCRL_DRAE_E18_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAE_E17_MASK (0x00020000u) +#define EDMA3_CCRL_DRAE_E17_SHIFT (0x00000011u) +#define EDMA3_CCRL_DRAE_E17_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAE_E16_MASK (0x00010000u) +#define EDMA3_CCRL_DRAE_E16_SHIFT (0x00000010u) +#define EDMA3_CCRL_DRAE_E16_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAE_E15_MASK (0x00008000u) +#define EDMA3_CCRL_DRAE_E15_SHIFT (0x0000000Fu) +#define EDMA3_CCRL_DRAE_E15_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAE_E14_MASK (0x00004000u) +#define EDMA3_CCRL_DRAE_E14_SHIFT (0x0000000Eu) +#define EDMA3_CCRL_DRAE_E14_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAE_E13_MASK (0x00002000u) +#define EDMA3_CCRL_DRAE_E13_SHIFT (0x0000000Du) +#define EDMA3_CCRL_DRAE_E13_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAE_E12_MASK (0x00001000u) +#define EDMA3_CCRL_DRAE_E12_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_DRAE_E12_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAE_E11_MASK (0x00000800u) +#define EDMA3_CCRL_DRAE_E11_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_DRAE_E11_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAE_E10_MASK (0x00000400u) +#define EDMA3_CCRL_DRAE_E10_SHIFT (0x0000000Au) +#define EDMA3_CCRL_DRAE_E10_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAE_E9_MASK (0x00000200u) +#define EDMA3_CCRL_DRAE_E9_SHIFT (0x00000009u) +#define EDMA3_CCRL_DRAE_E9_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAE_E8_MASK (0x00000100u) +#define EDMA3_CCRL_DRAE_E8_SHIFT (0x00000008u) +#define EDMA3_CCRL_DRAE_E8_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAE_E7_MASK (0x00000080u) +#define EDMA3_CCRL_DRAE_E7_SHIFT (0x00000007u) +#define EDMA3_CCRL_DRAE_E7_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAE_E6_MASK (0x00000040u) +#define EDMA3_CCRL_DRAE_E6_SHIFT (0x00000006u) +#define EDMA3_CCRL_DRAE_E6_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAE_E5_MASK (0x00000020u) +#define EDMA3_CCRL_DRAE_E5_SHIFT (0x00000005u) +#define EDMA3_CCRL_DRAE_E5_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAE_E4_MASK (0x00000010u) +#define EDMA3_CCRL_DRAE_E4_SHIFT (0x00000004u) +#define EDMA3_CCRL_DRAE_E4_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAE_E3_MASK (0x00000008u) +#define EDMA3_CCRL_DRAE_E3_SHIFT (0x00000003u) +#define EDMA3_CCRL_DRAE_E3_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAE_E2_MASK (0x00000004u) +#define EDMA3_CCRL_DRAE_E2_SHIFT (0x00000002u) +#define EDMA3_CCRL_DRAE_E2_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAE_E1_MASK (0x00000002u) +#define EDMA3_CCRL_DRAE_E1_SHIFT (0x00000001u) +#define EDMA3_CCRL_DRAE_E1_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAE_E0_MASK (0x00000001u) +#define EDMA3_CCRL_DRAE_E0_SHIFT (0x00000000u) +#define EDMA3_CCRL_DRAE_E0_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAE_RESETVAL (0x00000000u) + +/* DRAEH */ + +#define EDMA3_CCRL_DRAEH_E63_MASK (0x80000000u) +#define EDMA3_CCRL_DRAEH_E63_SHIFT (0x0000001Fu) +#define EDMA3_CCRL_DRAEH_E63_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAEH_E62_MASK (0x40000000u) +#define EDMA3_CCRL_DRAEH_E62_SHIFT (0x0000001Eu) +#define EDMA3_CCRL_DRAEH_E62_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAEH_E61_MASK (0x20000000u) +#define EDMA3_CCRL_DRAEH_E61_SHIFT (0x0000001Du) +#define EDMA3_CCRL_DRAEH_E61_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAEH_E60_MASK (0x10000000u) +#define EDMA3_CCRL_DRAEH_E60_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_DRAEH_E60_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAEH_E59_MASK (0x08000000u) +#define EDMA3_CCRL_DRAEH_E59_SHIFT (0x0000001Bu) +#define EDMA3_CCRL_DRAEH_E59_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAEH_E58_MASK (0x04000000u) +#define EDMA3_CCRL_DRAEH_E58_SHIFT (0x0000001Au) +#define EDMA3_CCRL_DRAEH_E58_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAEH_E57_MASK (0x02000000u) +#define EDMA3_CCRL_DRAEH_E57_SHIFT (0x00000019u) +#define EDMA3_CCRL_DRAEH_E57_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAEH_E56_MASK (0x01000000u) +#define EDMA3_CCRL_DRAEH_E56_SHIFT (0x00000018u) +#define EDMA3_CCRL_DRAEH_E56_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAEH_E55_MASK (0x00800000u) +#define EDMA3_CCRL_DRAEH_E55_SHIFT (0x00000017u) +#define EDMA3_CCRL_DRAEH_E55_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAEH_E54_MASK (0x00400000u) +#define EDMA3_CCRL_DRAEH_E54_SHIFT (0x00000016u) +#define EDMA3_CCRL_DRAEH_E54_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAEH_E53_MASK (0x00200000u) +#define EDMA3_CCRL_DRAEH_E53_SHIFT (0x00000015u) +#define EDMA3_CCRL_DRAEH_E53_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAEH_E52_MASK (0x00100000u) +#define EDMA3_CCRL_DRAEH_E52_SHIFT (0x00000014u) +#define EDMA3_CCRL_DRAEH_E52_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAEH_E51_MASK (0x00080000u) +#define EDMA3_CCRL_DRAEH_E51_SHIFT (0x00000013u) +#define EDMA3_CCRL_DRAEH_E51_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAEH_E50_MASK (0x00040000u) +#define EDMA3_CCRL_DRAEH_E50_SHIFT (0x00000012u) +#define EDMA3_CCRL_DRAEH_E50_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAEH_E49_MASK (0x00020000u) +#define EDMA3_CCRL_DRAEH_E49_SHIFT (0x00000011u) +#define EDMA3_CCRL_DRAEH_E49_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAEH_E48_MASK (0x00010000u) +#define EDMA3_CCRL_DRAEH_E48_SHIFT (0x00000010u) +#define EDMA3_CCRL_DRAEH_E48_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAEH_E47_MASK (0x00008000u) +#define EDMA3_CCRL_DRAEH_E47_SHIFT (0x0000000Fu) +#define EDMA3_CCRL_DRAEH_E47_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAEH_E46_MASK (0x00004000u) +#define EDMA3_CCRL_DRAEH_E46_SHIFT (0x0000000Eu) +#define EDMA3_CCRL_DRAEH_E46_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAEH_E45_MASK (0x00002000u) +#define EDMA3_CCRL_DRAEH_E45_SHIFT (0x0000000Du) +#define EDMA3_CCRL_DRAEH_E45_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAEH_E44_MASK (0x00001000u) +#define EDMA3_CCRL_DRAEH_E44_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_DRAEH_E44_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAEH_E43_MASK (0x00000800u) +#define EDMA3_CCRL_DRAEH_E43_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_DRAEH_E43_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAEH_E42_MASK (0x00000400u) +#define EDMA3_CCRL_DRAEH_E42_SHIFT (0x0000000Au) +#define EDMA3_CCRL_DRAEH_E42_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAEH_E41_MASK (0x00000200u) +#define EDMA3_CCRL_DRAEH_E41_SHIFT (0x00000009u) +#define EDMA3_CCRL_DRAEH_E41_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAEH_E40_MASK (0x00000100u) +#define EDMA3_CCRL_DRAEH_E40_SHIFT (0x00000008u) +#define EDMA3_CCRL_DRAEH_E40_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAEH_E39_MASK (0x00000080u) +#define EDMA3_CCRL_DRAEH_E39_SHIFT (0x00000007u) +#define EDMA3_CCRL_DRAEH_E39_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAEH_E38_MASK (0x00000040u) +#define EDMA3_CCRL_DRAEH_E38_SHIFT (0x00000006u) +#define EDMA3_CCRL_DRAEH_E38_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAEH_E37_MASK (0x00000020u) +#define EDMA3_CCRL_DRAEH_E37_SHIFT (0x00000005u) +#define EDMA3_CCRL_DRAEH_E37_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAEH_E36_MASK (0x00000010u) +#define EDMA3_CCRL_DRAEH_E36_SHIFT (0x00000004u) +#define EDMA3_CCRL_DRAEH_E36_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAEH_E35_MASK (0x00000008u) +#define EDMA3_CCRL_DRAEH_E35_SHIFT (0x00000003u) +#define EDMA3_CCRL_DRAEH_E35_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAEH_E34_MASK (0x00000004u) +#define EDMA3_CCRL_DRAEH_E34_SHIFT (0x00000002u) +#define EDMA3_CCRL_DRAEH_E34_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAEH_E33_MASK (0x00000002u) +#define EDMA3_CCRL_DRAEH_E33_SHIFT (0x00000001u) +#define EDMA3_CCRL_DRAEH_E33_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAEH_E32_MASK (0x00000001u) +#define EDMA3_CCRL_DRAEH_E32_SHIFT (0x00000000u) +#define EDMA3_CCRL_DRAEH_E32_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DRAEH_RESETVAL (0x00000000u) + +/* QRAE */ + +#define EDMA3_CCRL_QRAE_E7_MASK (0x00000080u) +#define EDMA3_CCRL_QRAE_E7_SHIFT (0x00000007u) +#define EDMA3_CCRL_QRAE_E7_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QRAE_E6_MASK (0x00000080u) +#define EDMA3_CCRL_QRAE_E6_SHIFT (0x00000007u) +#define EDMA3_CCRL_QRAE_E6_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QRAE_E5_MASK (0x00000080u) +#define EDMA3_CCRL_QRAE_E5_SHIFT (0x00000007u) +#define EDMA3_CCRL_QRAE_E5_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QRAE_E4_MASK (0x00000080u) +#define EDMA3_CCRL_QRAE_E4_SHIFT (0x00000007u) +#define EDMA3_CCRL_QRAE_E4_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QRAE_E3_MASK (0x00000080u) +#define EDMA3_CCRL_QRAE_E3_SHIFT (0x00000007u) +#define EDMA3_CCRL_QRAE_E3_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QRAE_E2_MASK (0x00000080u) +#define EDMA3_CCRL_QRAE_E2_SHIFT (0x00000007u) +#define EDMA3_CCRL_QRAE_E2_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QRAE_E1_MASK (0x00000080u) +#define EDMA3_CCRL_QRAE_E1_SHIFT (0x00000007u) +#define EDMA3_CCRL_QRAE_E1_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QRAE_E0_MASK (0x00000080u) +#define EDMA3_CCRL_QRAE_E0_SHIFT (0x00000007u) +#define EDMA3_CCRL_QRAE_E0_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QRAE_RESERVED_MASK (0x0000007Fu) +#define EDMA3_CCRL_QRAE_RESERVED_SHIFT (0x00000000u) +#define EDMA3_CCRL_QRAE_RESERVED_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QRAE_RESETVAL (0x00000000u) + +/* QUEEVT_ENTRY */ + +#define EDMA3_CCRL_QUEEVT_ENTRY_RESV_MASK (0xFFFFFF00u) +#define EDMA3_CCRL_QUEEVT_ENTRY_RESV_SHIFT (0x00000008u) +#define EDMA3_CCRL_QUEEVT_ENTRY_RESV_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QUEEVT_ENTRY_EVT_SRC_MASK (0x000000C0u) +#define EDMA3_CCRL_QUEEVT_ENTRY_EVT_SRC_SHIFT (0x00000006u) +#define EDMA3_CCRL_QUEEVT_ENTRY_EVT_SRC_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QUEEVT_ENTRY_EVT_MASK (0x0000003Fu) +#define EDMA3_CCRL_QUEEVT_ENTRY_EVT_SHIFT (0x00000000u) +#define EDMA3_CCRL_QUEEVT_ENTRY_EVT_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QUEEVT_ENTRY_RESETVAL (0x00000000u) + +/* QSTAT */ + +#define EDMA3_CCRL_QSTAT_THRXD_MASK (0x01000000u) +#define EDMA3_CCRL_QSTAT_THRXD_SHIFT (0x00000018u) +#define EDMA3_CCRL_QSTAT_THRXD_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QSTAT_RESERVED_MASK (0x00600000u) +#define EDMA3_CCRL_QSTAT_RESERVED_SHIFT (0x00000015u) +#define EDMA3_CCRL_QSTAT_RESERVED_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QSTAT_WM_MASK (0x001F0000u) +#define EDMA3_CCRL_QSTAT_WM_SHIFT (0x00000010u) +#define EDMA3_CCRL_QSTAT_WM_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QSTAT_NUMVAL_MASK (0x00001F00u) +#define EDMA3_CCRL_QSTAT_NUMVAL_SHIFT (0x00000008u) +#define EDMA3_CCRL_QSTAT_NUMVAL_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QSTAT_STRTPTR_MASK (0x0000000Fu) +#define EDMA3_CCRL_QSTAT_STRTPTR_SHIFT (0x00000000u) +#define EDMA3_CCRL_QSTAT_STRTPTR_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QSTAT_RESETVAL (0x00000000u) + +/* QWMTHRA */ + +#define EDMA3_CCRL_QWMTHRA_Q3_MASK (0x1F000000u) +#define EDMA3_CCRL_QWMTHRA_Q3_SHIFT (0x00000018u) +#define EDMA3_CCRL_QWMTHRA_Q3_RESETVAL (0x00000010u) + +#define EDMA3_CCRL_QWMTHRA_Q2_MASK (0x001F0000u) +#define EDMA3_CCRL_QWMTHRA_Q2_SHIFT (0x00000010u) +#define EDMA3_CCRL_QWMTHRA_Q2_RESETVAL (0x00000010u) + +#define EDMA3_CCRL_QWMTHRA_Q1_MASK (0x00001F00u) +#define EDMA3_CCRL_QWMTHRA_Q1_SHIFT (0x00000008u) +#define EDMA3_CCRL_QWMTHRA_Q1_RESETVAL (0x00000010u) + +#define EDMA3_CCRL_QWMTHRA_Q0_MASK (0x0000001Fu) +#define EDMA3_CCRL_QWMTHRA_Q0_SHIFT (0x00000000u) +#define EDMA3_CCRL_QWMTHRA_Q0_RESETVAL (0x00000010u) + +#define EDMA3_CCRL_QWMTHRA_RESETVAL (0x10101010u) + +/* QWMTHRB */ + +#define EDMA3_CCRL_QWMTHRB_Q7_MASK (0x1F000000u) +#define EDMA3_CCRL_QWMTHRB_Q7_SHIFT (0x00000018u) +#define EDMA3_CCRL_QWMTHRB_Q7_RESETVAL (0x00000010u) + +#define EDMA3_CCRL_QWMTHRB_Q6_MASK (0x001F0000u) +#define EDMA3_CCRL_QWMTHRB_Q6_SHIFT (0x00000010u) +#define EDMA3_CCRL_QWMTHRB_Q6_RESETVAL (0x00000010u) + +#define EDMA3_CCRL_QWMTHRB_Q5_MASK (0x00001F00u) +#define EDMA3_CCRL_QWMTHRB_Q5_SHIFT (0x00000008u) +#define EDMA3_CCRL_QWMTHRB_Q5_RESETVAL (0x00000010u) + +#define EDMA3_CCRL_QWMTHRB_Q4_MASK (0x0000001Fu) +#define EDMA3_CCRL_QWMTHRB_Q4_SHIFT (0x00000000u) +#define EDMA3_CCRL_QWMTHRB_Q4_RESETVAL (0x00000010u) + +#define EDMA3_CCRL_QWMTHRB_RESETVAL (0x10101010u) + +/* CCSTAT */ + +#define EDMA3_CCRL_CCSTAT_QUEACTV7_MASK (0x00800000u) +#define EDMA3_CCRL_CCSTAT_QUEACTV7_SHIFT (0x00000017u) +#define EDMA3_CCRL_CCSTAT_QUEACTV7_RESETVAL (0x00000000u) + +/*----QUEACTV7 Tokens----*/ +#define EDMA3_CCRL_CCSTAT_QUEACTV7_NONE (0x00000000u) +#define EDMA3_CCRL_CCSTAT_QUEACTV7_ACTIVE (0x00000001u) + +#define EDMA3_CCRL_CCSTAT_QUEACTV6_MASK (0x00400000u) +#define EDMA3_CCRL_CCSTAT_QUEACTV6_SHIFT (0x00000016u) +#define EDMA3_CCRL_CCSTAT_QUEACTV6_RESETVAL (0x00000000u) + +/*----QUEACTV6 Tokens----*/ +#define EDMA3_CCRL_CCSTAT_QUEACTV6_NONE (0x00000000u) +#define EDMA3_CCRL_CCSTAT_QUEACTV6_ACTIVE (0x00000001u) + +#define EDMA3_CCRL_CCSTAT_QUEACTV5_MASK (0x00200000u) +#define EDMA3_CCRL_CCSTAT_QUEACTV5_SHIFT (0x00000015u) +#define EDMA3_CCRL_CCSTAT_QUEACTV5_RESETVAL (0x00000000u) + +/*----QUEACTV5 Tokens----*/ +#define EDMA3_CCRL_CCSTAT_QUEACTV5_NONE (0x00000000u) +#define EDMA3_CCRL_CCSTAT_QUEACTV5_ACTIVE (0x00000001u) + +#define EDMA3_CCRL_CCSTAT_QUEACTV4_MASK (0x00100000u) +#define EDMA3_CCRL_CCSTAT_QUEACTV4_SHIFT (0x00000014u) +#define EDMA3_CCRL_CCSTAT_QUEACTV4_RESETVAL (0x00000000u) + +/*----QUEACTV4 Tokens----*/ +#define EDMA3_CCRL_CCSTAT_QUEACTV4_NONE (0x00000000u) +#define EDMA3_CCRL_CCSTAT_QUEACTV4_ACTIVE (0x00000001u) + +#define EDMA3_CCRL_CCSTAT_QUEACTV3_MASK (0x00080000u) +#define EDMA3_CCRL_CCSTAT_QUEACTV3_SHIFT (0x00000013u) +#define EDMA3_CCRL_CCSTAT_QUEACTV3_RESETVAL (0x00000000u) + +/*----QUEACTV3 Tokens----*/ +#define EDMA3_CCRL_CCSTAT_QUEACTV3_NONE (0x00000000u) +#define EDMA3_CCRL_CCSTAT_QUEACTV3_ACTIVE (0x00000001u) + +#define EDMA3_CCRL_CCSTAT_QUEACTV2_MASK (0x00040000u) +#define EDMA3_CCRL_CCSTAT_QUEACTV2_SHIFT (0x00000012u) +#define EDMA3_CCRL_CCSTAT_QUEACTV2_RESETVAL (0x00000000u) + +/*----QUEACTV2 Tokens----*/ +#define EDMA3_CCRL_CCSTAT_QUEACTV2_NONE (0x00000000u) +#define EDMA3_CCRL_CCSTAT_QUEACTV2_ACTIVE (0x00000001u) + +#define EDMA3_CCRL_CCSTAT_QUEACTV1_MASK (0x00020000u) +#define EDMA3_CCRL_CCSTAT_QUEACTV1_SHIFT (0x00000011u) +#define EDMA3_CCRL_CCSTAT_QUEACTV1_RESETVAL (0x00000000u) + +/*----QUEACTV1 Tokens----*/ +#define EDMA3_CCRL_CCSTAT_QUEACTV1_NONE (0x00000000u) +#define EDMA3_CCRL_CCSTAT_QUEACTV1_ACTIVE (0x00000001u) + +#define EDMA3_CCRL_CCSTAT_QUEACTV0_MASK (0x00010000u) +#define EDMA3_CCRL_CCSTAT_QUEACTV0_SHIFT (0x00000010u) +#define EDMA3_CCRL_CCSTAT_QUEACTV0_RESETVAL (0x00000000u) + +/*----QUEACTV0 Tokens----*/ +#define EDMA3_CCRL_CCSTAT_QUEACTV0_NONE (0x00000000u) +#define EDMA3_CCRL_CCSTAT_QUEACTV0_ACTIVE (0x00000001u) + +#define EDMA3_CCRL_CCSTAT_COMPACT_MASK (0x00003F00u) +#define EDMA3_CCRL_CCSTAT_COMPACT_SHIFT (0x00000008u) +#define EDMA3_CCRL_CCSTAT_COMPACT_RESETVAL (0x00000000u) + +/*----COMPACT Tokens----*/ +#define EDMA3_CCRL_CCSTAT_COMPACT_NONE (0x00000000u) + +#define EDMA3_CCRL_CCSTAT_ACTV_MASK (0x00000010u) +#define EDMA3_CCRL_CCSTAT_ACTV_SHIFT (0x00000004u) +#define EDMA3_CCRL_CCSTAT_ACTV_RESETVAL (0x00000000u) + +/*----ACTV Tokens----*/ +#define EDMA3_CCRL_CCSTAT_ACTV_IDLE (0x00000000u) +#define EDMA3_CCRL_CCSTAT_ACTV_BUSY (0x00000001u) + +#define EDMA3_CCRL_CCSTAT_TRACTV_MASK (0x00000004u) +#define EDMA3_CCRL_CCSTAT_TRACTV_SHIFT (0x00000002u) +#define EDMA3_CCRL_CCSTAT_TRACTV_RESETVAL (0x00000000u) + +/*----TRACTV Tokens----*/ +#define EDMA3_CCRL_CCSTAT_TRACTV_NONE (0x00000000u) +#define EDMA3_CCRL_CCSTAT_TRACTV_ACTIVE (0x00000001u) + +#define EDMA3_CCRL_CCSTAT_QEVTACTV_MASK (0x00000002u) +#define EDMA3_CCRL_CCSTAT_QEVTACTV_SHIFT (0x00000001u) +#define EDMA3_CCRL_CCSTAT_QEVTACTV_RESETVAL (0x00000000u) + +/*----QEVTACTV Tokens----*/ +#define EDMA3_CCRL_CCSTAT_QEVTACTV_NONE (0x00000000u) +#define EDMA3_CCRL_CCSTAT_QEVTACTV_ACTIVE (0x00000001u) + +#define EDMA3_CCRL_CCSTAT_EVTACTV_MASK (0x00000001u) +#define EDMA3_CCRL_CCSTAT_EVTACTV_SHIFT (0x00000000u) +#define EDMA3_CCRL_CCSTAT_EVTACTV_RESETVAL (0x00000000u) + +/*----EVTACTV Tokens----*/ +#define EDMA3_CCRL_CCSTAT_EVTACTV_NONE (0x00000000u) +#define EDMA3_CCRL_CCSTAT_EVTACTV_ACTIVE (0x00000001u) + +#define EDMA3_CCRL_CCSTAT_RESETVAL (0x00000000u) + +/* AETCTL */ + +#define EDMA3_CCRL_AETCTL_EN_MASK (0x80000000u) +#define EDMA3_CCRL_AETCTL_EN_SHIFT (0x0000001Fu) +#define EDMA3_CCRL_AETCTL_EN_RESETVAL (0x00000000u) + +/*----EN Tokens----*/ +#define EDMA3_CCRL_AETCTL_EN_DISABLE (0x00000000u) +#define EDMA3_CCRL_AETCTL_EN_ENABLE (0x00000001u) + +#define EDMA3_CCRL_AETCTL_ENDINT_MASK (0x00003F00u) +#define EDMA3_CCRL_AETCTL_ENDINT_SHIFT (0x00000008u) +#define EDMA3_CCRL_AETCTL_ENDINT_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_AETCTL_TYPE_MASK (0x00000040u) +#define EDMA3_CCRL_AETCTL_TYPE_SHIFT (0x00000006u) +#define EDMA3_CCRL_AETCTL_TYPE_RESETVAL (0x00000000u) + +/*----TYPE Tokens----*/ +#define EDMA3_CCRL_AETCTL_TYPE_DMA (0x00000000u) +#define EDMA3_CCRL_AETCTL_TYPE_QDMA (0x00000001u) + +#define EDMA3_CCRL_AETCTL_STRTEVT_MASK (0x0000003Fu) +#define EDMA3_CCRL_AETCTL_STRTEVT_SHIFT (0x00000000u) +#define EDMA3_CCRL_AETCTL_STRTEVT_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_AETCTL_RESETVAL (0x00000000u) + +/* AETSTAT */ + +#define EDMA3_CCRL_AETSTAT_STAT_MASK (0x00000001u) +#define EDMA3_CCRL_AETSTAT_STAT_SHIFT (0x00000000u) +#define EDMA3_CCRL_AETSTAT_STAT_RESETVAL (0x00000000u) + +/*----STAT Tokens----*/ +#define EDMA3_CCRL_AETSTAT_STAT_LOW (0x00000000u) +#define EDMA3_CCRL_AETSTAT_STAT_HIGH (0x00000001u) + +#define EDMA3_CCRL_AETSTAT_RESETVAL (0x00000000u) + +/* AETCMD */ + +#define EDMA3_CCRL_AETCMD_CLR_MASK (0x00000001u) +#define EDMA3_CCRL_AETCMD_CLR_SHIFT (0x00000000u) +#define EDMA3_CCRL_AETCMD_CLR_RESETVAL (0x00000000u) + +/*----CLR Tokens----*/ +#define EDMA3_CCRL_AETCMD_CLR_CLEAR (0x00000001u) + +#define EDMA3_CCRL_AETCMD_RESETVAL (0x00000000u) + +/* MPFAR */ + +#define EDMA3_CCRL_MPFAR_FADDR_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_MPFAR_FADDR_SHIFT (0x00000000u) +#define EDMA3_CCRL_MPFAR_FADDR_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_MPFAR_RESETVAL (0x00000000u) + +/* MPFSR */ + +#define EDMA3_CCRL_MPFSR_FID_MASK (0x00001E00u) +#define EDMA3_CCRL_MPFSR_FID_SHIFT (0x00000009u) +#define EDMA3_CCRL_MPFSR_FID_RESETVAL (0x00000009u) + +#define EDMA3_CCRL_MPFSR_SECE_MASK (0x00000080u) +#define EDMA3_CCRL_MPFSR_SECE_SHIFT (0x00000007u) +#define EDMA3_CCRL_MPFSR_SECE_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_MPFSR_SRE_MASK (0x00000020u) +#define EDMA3_CCRL_MPFSR_SRE_SHIFT (0x00000005u) +#define EDMA3_CCRL_MPFSR_SRE_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_MPFSR_SWE_MASK (0x00000010u) +#define EDMA3_CCRL_MPFSR_SWE_SHIFT (0x00000004u) +#define EDMA3_CCRL_MPFSR_SWE_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_MPFSR_SXE_MASK (0x00000008u) +#define EDMA3_CCRL_MPFSR_SXE_SHIFT (0x00000003u) +#define EDMA3_CCRL_MPFSR_SXE_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_MPFSR_URE_MASK (0x00000004u) +#define EDMA3_CCRL_MPFSR_URE_SHIFT (0x00000002u) +#define EDMA3_CCRL_MPFSR_URE_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_MPFSR_UWE_MASK (0x00000002u) +#define EDMA3_CCRL_MPFSR_UWE_SHIFT (0x00000001u) +#define EDMA3_CCRL_MPFSR_UWE_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_MPFSR_UXE_MASK (0x00000001u) +#define EDMA3_CCRL_MPFSR_UXE_SHIFT (0x00000000u) +#define EDMA3_CCRL_MPFSR_UXE_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_MPFSR_RESETVAL (0x00001200u) + +/* MPFCR */ + +#define EDMA3_CCRL_MPFCR_MPFCLR_MASK (0x00000001u) +#define EDMA3_CCRL_MPFCR_MPFCLR_SHIFT (0x00000000u) +#define EDMA3_CCRL_MPFCR_MPFCLR_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_MPFCR_RESETVAL (0x00000000u) + +/* MPPAG */ + +#define EDMA3_CCRL_MPPAG_AID5_MASK (0x00008000u) +#define EDMA3_CCRL_MPPAG_AID5_SHIFT (0x0000000Fu) +#define EDMA3_CCRL_MPPAG_AID5_RESETVAL (0x00000000u) + +/*----AID5 Tokens----*/ +#define EDMA3_CCRL_MPPAG_AID5_BLOCK (0x00000000u) +#define EDMA3_CCRL_MPPAG_AID5_PERMIT (0x00000001u) + +#define EDMA3_CCRL_MPPAG_AID4_MASK (0x00004000u) +#define EDMA3_CCRL_MPPAG_AID4_SHIFT (0x0000000Eu) +#define EDMA3_CCRL_MPPAG_AID4_RESETVAL (0x00000000u) + +/*----AID4 Tokens----*/ +#define EDMA3_CCRL_MPPAG_AID4_BLOCK (0x00000000u) +#define EDMA3_CCRL_MPPAG_AID4_PERMIT (0x00000001u) + +#define EDMA3_CCRL_MPPAG_AID3_MASK (0x00002000u) +#define EDMA3_CCRL_MPPAG_AID3_SHIFT (0x0000000Du) +#define EDMA3_CCRL_MPPAG_AID3_RESETVAL (0x00000000u) + +/*----AID3 Tokens----*/ +#define EDMA3_CCRL_MPPAG_AID3_BLOCK (0x00000000u) +#define EDMA3_CCRL_MPPAG_AID3_PERMIT (0x00000001u) + +#define EDMA3_CCRL_MPPAG_AID2_MASK (0x00001000u) +#define EDMA3_CCRL_MPPAG_AID2_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_MPPAG_AID2_RESETVAL (0x00000000u) + +/*----AID2 Tokens----*/ +#define EDMA3_CCRL_MPPAG_AID2_BLOCK (0x00000000u) +#define EDMA3_CCRL_MPPAG_AID2_PERMIT (0x00000001u) + +#define EDMA3_CCRL_MPPAG_AID1_MASK (0x00000800u) +#define EDMA3_CCRL_MPPAG_AID1_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_MPPAG_AID1_RESETVAL (0x00000000u) + +/*----AID1 Tokens----*/ +#define EDMA3_CCRL_MPPAG_AID1_BLOCK (0x00000000u) +#define EDMA3_CCRL_MPPAG_AID1_PERMIT (0x00000001u) + +#define EDMA3_CCRL_MPPAG_AID0_MASK (0x00000400u) +#define EDMA3_CCRL_MPPAG_AID0_SHIFT (0x0000000Au) +#define EDMA3_CCRL_MPPAG_AID0_RESETVAL (0x00000000u) + +/*----AID0 Tokens----*/ +#define EDMA3_CCRL_MPPAG_AID0_BLOCK (0x00000000u) +#define EDMA3_CCRL_MPPAG_AID0_PERMIT (0x00000001u) + +#define EDMA3_CCRL_MPPAG_EXT_MASK (0x00000200u) +#define EDMA3_CCRL_MPPAG_EXT_SHIFT (0x00000009u) +#define EDMA3_CCRL_MPPAG_EXT_RESETVAL (0x00000000u) + +/*----EXT Tokens----*/ +#define EDMA3_CCRL_MPPAG_EXT_BLOCK (0x00000000u) +#define EDMA3_CCRL_MPPAG_EXT_PERMIT (0x00000001u) + +#define EDMA3_CCRL_MPPAG_LCL_MASK (0x00000100u) +#define EDMA3_CCRL_MPPAG_LCL_SHIFT (0x00000008u) +#define EDMA3_CCRL_MPPAG_LCL_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_MPPAG_NS_MASK (0x00000080u) +#define EDMA3_CCRL_MPPAG_NS_SHIFT (0x00000007u) +#define EDMA3_CCRL_MPPAG_NS_RESETVAL (0x00000000u) + +/*----NS Tokens----*/ +#define EDMA3_CCRL_MPPAG_NS_SECURE (0x00000000u) +#define EDMA3_CCRL_MPPAG_NS_NONSECURE (0x00000001u) + +#define EDMA3_CCRL_MPPAG_EMU_MASK (0x00000040u) +#define EDMA3_CCRL_MPPAG_EMU_SHIFT (0x00000006u) +#define EDMA3_CCRL_MPPAG_EMU_RESETVAL (0x00000000u) + +/*----EMU Tokens----*/ +#define EDMA3_CCRL_MPPAG_EMU_BLOCK (0x00000000u) +#define EDMA3_CCRL_MPPAG_EMU_PERMIT (0x00000001u) + +#define EDMA3_CCRL_MPPAG_SR_MASK (0x00000020u) +#define EDMA3_CCRL_MPPAG_SR_SHIFT (0x00000005u) +#define EDMA3_CCRL_MPPAG_SR_RESETVAL (0x00000000u) + +/*----SR Tokens----*/ +#define EDMA3_CCRL_MPPAG_SR_BLOCK (0x00000000u) +#define EDMA3_CCRL_MPPAG_SR_PERMIT (0x00000001u) + +#define EDMA3_CCRL_MPPAG_SW_MASK (0x00000010u) +#define EDMA3_CCRL_MPPAG_SW_SHIFT (0x00000004u) +#define EDMA3_CCRL_MPPAG_SW_RESETVAL (0x00000000u) + +/*----SW Tokens----*/ +#define EDMA3_CCRL_MPPAG_SW_BLOCK (0x00000000u) +#define EDMA3_CCRL_MPPAG_SW_PERMIT (0x00000001u) + +#define EDMA3_CCRL_MPPAG_SX_MASK (0x00000008u) +#define EDMA3_CCRL_MPPAG_SX_SHIFT (0x00000003u) +#define EDMA3_CCRL_MPPAG_SX_RESETVAL (0x00000000u) + +/*----SX Tokens----*/ +#define EDMA3_CCRL_MPPAG_SX_BLOCK (0x00000000u) +#define EDMA3_CCRL_MPPAG_SX_PERMIT (0x00000001u) + +#define EDMA3_CCRL_MPPAG_UR_MASK (0x00000004u) +#define EDMA3_CCRL_MPPAG_UR_SHIFT (0x00000002u) +#define EDMA3_CCRL_MPPAG_UR_RESETVAL (0x00000000u) + +/*----UR Tokens----*/ +#define EDMA3_CCRL_MPPAG_UR_BLOCK (0x00000000u) +#define EDMA3_CCRL_MPPAG_UR_PERMIT (0x00000001u) + +#define EDMA3_CCRL_MPPAG_UW_MASK (0x00000002u) +#define EDMA3_CCRL_MPPAG_UW_SHIFT (0x00000001u) +#define EDMA3_CCRL_MPPAG_UW_RESETVAL (0x00000000u) + +/*----UW Tokens----*/ +#define EDMA3_CCRL_MPPAG_UW_BLOCK (0x00000000u) +#define EDMA3_CCRL_MPPAG_UW_PERMIT (0x00000001u) + +#define EDMA3_CCRL_MPPAG_UX_MASK (0x00000001u) +#define EDMA3_CCRL_MPPAG_UX_SHIFT (0x00000000u) +#define EDMA3_CCRL_MPPAG_UX_RESETVAL (0x00000000u) + +/*----UX Tokens----*/ +#define EDMA3_CCRL_MPPAG_UX_BLOCK (0x00000000u) +#define EDMA3_CCRL_MPPAG_UX_PERMIT (0x00000001u) + +#define EDMA3_CCRL_MPPAG_RESETVAL (0x00000000u) + +/* MPPA */ + +#define EDMA3_CCRL_MPPA_AID5_MASK (0x00008000u) +#define EDMA3_CCRL_MPPA_AID5_SHIFT (0x0000000Fu) +#define EDMA3_CCRL_MPPA_AID5_RESETVAL (0x00000000u) + +/*----AID5 Tokens----*/ +#define EDMA3_CCRL_MPPA_AID5_BLOCK (0x00000000u) +#define EDMA3_CCRL_MPPA_AID5_PERMIT (0x00000001u) + +#define EDMA3_CCRL_MPPA_AID4_MASK (0x00004000u) +#define EDMA3_CCRL_MPPA_AID4_SHIFT (0x0000000Eu) +#define EDMA3_CCRL_MPPA_AID4_RESETVAL (0x00000000u) + +/*----AID4 Tokens----*/ +#define EDMA3_CCRL_MPPA_AID4_BLOCK (0x00000000u) +#define EDMA3_CCRL_MPPA_AID4_PERMIT (0x00000001u) + +#define EDMA3_CCRL_MPPA_AID3_MASK (0x00002000u) +#define EDMA3_CCRL_MPPA_AID3_SHIFT (0x0000000Du) +#define EDMA3_CCRL_MPPA_AID3_RESETVAL (0x00000000u) + +/*----AID3 Tokens----*/ +#define EDMA3_CCRL_MPPA_AID3_BLOCK (0x00000000u) +#define EDMA3_CCRL_MPPA_AID3_PERMIT (0x00000001u) + +#define EDMA3_CCRL_MPPA_AID2_MASK (0x00001000u) +#define EDMA3_CCRL_MPPA_AID2_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_MPPA_AID2_RESETVAL (0x00000000u) + +/*----AID2 Tokens----*/ +#define EDMA3_CCRL_MPPA_AID2_BLOCK (0x00000000u) +#define EDMA3_CCRL_MPPA_AID2_PERMIT (0x00000001u) + +#define EDMA3_CCRL_MPPA_AID1_MASK (0x00000800u) +#define EDMA3_CCRL_MPPA_AID1_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_MPPA_AID1_RESETVAL (0x00000000u) + +/*----AID1 Tokens----*/ +#define EDMA3_CCRL_MPPA_AID1_BLOCK (0x00000000u) +#define EDMA3_CCRL_MPPA_AID1_PERMIT (0x00000001u) + +#define EDMA3_CCRL_MPPA_AID0_MASK (0x00000400u) +#define EDMA3_CCRL_MPPA_AID0_SHIFT (0x0000000Au) +#define EDMA3_CCRL_MPPA_AID0_RESETVAL (0x00000000u) + +/*----AID0 Tokens----*/ +#define EDMA3_CCRL_MPPA_AID0_BLOCK (0x00000000u) +#define EDMA3_CCRL_MPPA_AID0_PERMIT (0x00000001u) + +#define EDMA3_CCRL_MPPA_EXT_MASK (0x00000200u) +#define EDMA3_CCRL_MPPA_EXT_SHIFT (0x00000009u) +#define EDMA3_CCRL_MPPA_EXT_RESETVAL (0x00000000u) + +/*----EXT Tokens----*/ +#define EDMA3_CCRL_MPPA_EXT_BLOCK (0x00000000u) +#define EDMA3_CCRL_MPPA_EXT_PERMIT (0x00000001u) + +#define EDMA3_CCRL_MPPA_LCL_MASK (0x00000100u) +#define EDMA3_CCRL_MPPA_LCL_SHIFT (0x00000008u) +#define EDMA3_CCRL_MPPA_LCL_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_MPPA_NS_MASK (0x00000080u) +#define EDMA3_CCRL_MPPA_NS_SHIFT (0x00000007u) +#define EDMA3_CCRL_MPPA_NS_RESETVAL (0x00000000u) + +/*----NS Tokens----*/ +#define EDMA3_CCRL_MPPA_NS_SECURE (0x00000000u) +#define EDMA3_CCRL_MPPA_NS_NONSECURE (0x00000001u) + +#define EDMA3_CCRL_MPPA_EMU_MASK (0x00000040u) +#define EDMA3_CCRL_MPPA_EMU_SHIFT (0x00000006u) +#define EDMA3_CCRL_MPPA_EMU_RESETVAL (0x00000000u) + +/*----EMU Tokens----*/ +#define EDMA3_CCRL_MPPA_EMU_BLOCK (0x00000000u) +#define EDMA3_CCRL_MPPA_EMU_PERMIT (0x00000001u) + +#define EDMA3_CCRL_MPPA_SR_MASK (0x00000020u) +#define EDMA3_CCRL_MPPA_SR_SHIFT (0x00000005u) +#define EDMA3_CCRL_MPPA_SR_RESETVAL (0x00000000u) + +/*----SR Tokens----*/ +#define EDMA3_CCRL_MPPA_SR_BLOCK (0x00000000u) +#define EDMA3_CCRL_MPPA_SR_PERMIT (0x00000001u) + +#define EDMA3_CCRL_MPPA_SW_MASK (0x00000010u) +#define EDMA3_CCRL_MPPA_SW_SHIFT (0x00000004u) +#define EDMA3_CCRL_MPPA_SW_RESETVAL (0x00000000u) + +/*----SW Tokens----*/ +#define EDMA3_CCRL_MPPA_SW_BLOCK (0x00000000u) +#define EDMA3_CCRL_MPPA_SW_PERMIT (0x00000001u) + +#define EDMA3_CCRL_MPPA_SX_MASK (0x00000008u) +#define EDMA3_CCRL_MPPA_SX_SHIFT (0x00000003u) +#define EDMA3_CCRL_MPPA_SX_RESETVAL (0x00000000u) + +/*----SX Tokens----*/ +#define EDMA3_CCRL_MPPA_SX_BLOCK (0x00000000u) +#define EDMA3_CCRL_MPPA_SX_PERMIT (0x00000001u) + +#define EDMA3_CCRL_MPPA_UR_MASK (0x00000004u) +#define EDMA3_CCRL_MPPA_UR_SHIFT (0x00000002u) +#define EDMA3_CCRL_MPPA_UR_RESETVAL (0x00000000u) + +/*----UR Tokens----*/ +#define EDMA3_CCRL_MPPA_UR_BLOCK (0x00000000u) +#define EDMA3_CCRL_MPPA_UR_PERMIT (0x00000001u) + +#define EDMA3_CCRL_MPPA_UW_MASK (0x00000002u) +#define EDMA3_CCRL_MPPA_UW_SHIFT (0x00000001u) +#define EDMA3_CCRL_MPPA_UW_RESETVAL (0x00000000u) + +/*----UW Tokens----*/ +#define EDMA3_CCRL_MPPA_UW_BLOCK (0x00000000u) +#define EDMA3_CCRL_MPPA_UW_PERMIT (0x00000001u) + +#define EDMA3_CCRL_MPPA_UX_MASK (0x00000001u) +#define EDMA3_CCRL_MPPA_UX_SHIFT (0x00000000u) +#define EDMA3_CCRL_MPPA_UX_RESETVAL (0x00000000u) + +/*----UX Tokens----*/ +#define EDMA3_CCRL_MPPA_UX_BLOCK (0x00000000u) +#define EDMA3_CCRL_MPPA_UX_PERMIT (0x00000001u) + +#define EDMA3_CCRL_MPPA_RESETVAL (0x00000000u) + +/* ER */ + +#define EDMA3_CCRL_ER_E31_MASK (0x80000000u) +#define EDMA3_CCRL_ER_E31_SHIFT (0x0000001Fu) +#define EDMA3_CCRL_ER_E31_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ER_E30_MASK (0x40000000u) +#define EDMA3_CCRL_ER_E30_SHIFT (0x0000001Eu) +#define EDMA3_CCRL_ER_E30_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ER_E29_MASK (0x20000000u) +#define EDMA3_CCRL_ER_E29_SHIFT (0x0000001Du) +#define EDMA3_CCRL_ER_E29_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ER_E28_MASK (0x10000000u) +#define EDMA3_CCRL_ER_E28_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_ER_E28_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ER_E27_MASK (0x08000000u) +#define EDMA3_CCRL_ER_E27_SHIFT (0x0000001Bu) +#define EDMA3_CCRL_ER_E27_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ER_E26_MASK (0x04000000u) +#define EDMA3_CCRL_ER_E26_SHIFT (0x0000001Au) +#define EDMA3_CCRL_ER_E26_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ER_E25_MASK (0x02000000u) +#define EDMA3_CCRL_ER_E25_SHIFT (0x00000019u) +#define EDMA3_CCRL_ER_E25_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ER_E24_MASK (0x01000000u) +#define EDMA3_CCRL_ER_E24_SHIFT (0x00000018u) +#define EDMA3_CCRL_ER_E24_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ER_E23_MASK (0x00800000u) +#define EDMA3_CCRL_ER_E23_SHIFT (0x00000017u) +#define EDMA3_CCRL_ER_E23_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ER_E22_MASK (0x00400000u) +#define EDMA3_CCRL_ER_E22_SHIFT (0x00000016u) +#define EDMA3_CCRL_ER_E22_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ER_E21_MASK (0x00200000u) +#define EDMA3_CCRL_ER_E21_SHIFT (0x00000015u) +#define EDMA3_CCRL_ER_E21_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ER_E20_MASK (0x00100000u) +#define EDMA3_CCRL_ER_E20_SHIFT (0x00000014u) +#define EDMA3_CCRL_ER_E20_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ER_E19_MASK (0x00080000u) +#define EDMA3_CCRL_ER_E19_SHIFT (0x00000013u) +#define EDMA3_CCRL_ER_E19_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ER_E18_MASK (0x00040000u) +#define EDMA3_CCRL_ER_E18_SHIFT (0x00000012u) +#define EDMA3_CCRL_ER_E18_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ER_E17_MASK (0x00020000u) +#define EDMA3_CCRL_ER_E17_SHIFT (0x00000011u) +#define EDMA3_CCRL_ER_E17_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ER_E16_MASK (0x00010000u) +#define EDMA3_CCRL_ER_E16_SHIFT (0x00000010u) +#define EDMA3_CCRL_ER_E16_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ER_E15_MASK (0x00008000u) +#define EDMA3_CCRL_ER_E15_SHIFT (0x0000000Fu) +#define EDMA3_CCRL_ER_E15_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ER_E14_MASK (0x00004000u) +#define EDMA3_CCRL_ER_E14_SHIFT (0x0000000Eu) +#define EDMA3_CCRL_ER_E14_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ER_E13_MASK (0x00002000u) +#define EDMA3_CCRL_ER_E13_SHIFT (0x0000000Du) +#define EDMA3_CCRL_ER_E13_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ER_E12_MASK (0x00001000u) +#define EDMA3_CCRL_ER_E12_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_ER_E12_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ER_E11_MASK (0x00000800u) +#define EDMA3_CCRL_ER_E11_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_ER_E11_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ER_E10_MASK (0x00000400u) +#define EDMA3_CCRL_ER_E10_SHIFT (0x0000000Au) +#define EDMA3_CCRL_ER_E10_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ER_E9_MASK (0x00000200u) +#define EDMA3_CCRL_ER_E9_SHIFT (0x00000009u) +#define EDMA3_CCRL_ER_E9_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ER_E8_MASK (0x00000100u) +#define EDMA3_CCRL_ER_E8_SHIFT (0x00000008u) +#define EDMA3_CCRL_ER_E8_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ER_E7_MASK (0x00000080u) +#define EDMA3_CCRL_ER_E7_SHIFT (0x00000007u) +#define EDMA3_CCRL_ER_E7_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ER_E6_MASK (0x00000040u) +#define EDMA3_CCRL_ER_E6_SHIFT (0x00000006u) +#define EDMA3_CCRL_ER_E6_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ER_E5_MASK (0x00000020u) +#define EDMA3_CCRL_ER_E5_SHIFT (0x00000005u) +#define EDMA3_CCRL_ER_E5_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ER_E4_MASK (0x00000010u) +#define EDMA3_CCRL_ER_E4_SHIFT (0x00000004u) +#define EDMA3_CCRL_ER_E4_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ER_E3_MASK (0x00000008u) +#define EDMA3_CCRL_ER_E3_SHIFT (0x00000003u) +#define EDMA3_CCRL_ER_E3_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ER_E2_MASK (0x00000004u) +#define EDMA3_CCRL_ER_E2_SHIFT (0x00000002u) +#define EDMA3_CCRL_ER_E2_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ER_E1_MASK (0x00000002u) +#define EDMA3_CCRL_ER_E1_SHIFT (0x00000001u) +#define EDMA3_CCRL_ER_E1_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ER_E0_MASK (0x00000001u) +#define EDMA3_CCRL_ER_E0_SHIFT (0x00000000u) +#define EDMA3_CCRL_ER_E0_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ER_RESETVAL (0x00000000u) + +/* ERH */ + +#define EDMA3_CCRL_ERH_E63_MASK (0x80000000u) +#define EDMA3_CCRL_ERH_E63_SHIFT (0x0000001Fu) +#define EDMA3_CCRL_ERH_E63_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ERH_E62_MASK (0x40000000u) +#define EDMA3_CCRL_ERH_E62_SHIFT (0x0000001Eu) +#define EDMA3_CCRL_ERH_E62_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ERH_E61_MASK (0x20000000u) +#define EDMA3_CCRL_ERH_E61_SHIFT (0x0000001Du) +#define EDMA3_CCRL_ERH_E61_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ERH_E60_MASK (0x10000000u) +#define EDMA3_CCRL_ERH_E60_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_ERH_E60_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ERH_E59_MASK (0x08000000u) +#define EDMA3_CCRL_ERH_E59_SHIFT (0x0000001Bu) +#define EDMA3_CCRL_ERH_E59_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ERH_E58_MASK (0x04000000u) +#define EDMA3_CCRL_ERH_E58_SHIFT (0x0000001Au) +#define EDMA3_CCRL_ERH_E58_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ERH_E57_MASK (0x02000000u) +#define EDMA3_CCRL_ERH_E57_SHIFT (0x00000019u) +#define EDMA3_CCRL_ERH_E57_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ERH_E56_MASK (0x01000000u) +#define EDMA3_CCRL_ERH_E56_SHIFT (0x00000018u) +#define EDMA3_CCRL_ERH_E56_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ERH_E55_MASK (0x00800000u) +#define EDMA3_CCRL_ERH_E55_SHIFT (0x00000017u) +#define EDMA3_CCRL_ERH_E55_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ERH_E54_MASK (0x00400000u) +#define EDMA3_CCRL_ERH_E54_SHIFT (0x00000016u) +#define EDMA3_CCRL_ERH_E54_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ERH_E53_MASK (0x00200000u) +#define EDMA3_CCRL_ERH_E53_SHIFT (0x00000015u) +#define EDMA3_CCRL_ERH_E53_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ERH_E52_MASK (0x00100000u) +#define EDMA3_CCRL_ERH_E52_SHIFT (0x00000014u) +#define EDMA3_CCRL_ERH_E52_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ERH_E51_MASK (0x00080000u) +#define EDMA3_CCRL_ERH_E51_SHIFT (0x00000013u) +#define EDMA3_CCRL_ERH_E51_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ERH_E50_MASK (0x00040000u) +#define EDMA3_CCRL_ERH_E50_SHIFT (0x00000012u) +#define EDMA3_CCRL_ERH_E50_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ERH_E49_MASK (0x00020000u) +#define EDMA3_CCRL_ERH_E49_SHIFT (0x00000011u) +#define EDMA3_CCRL_ERH_E49_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ERH_E48_MASK (0x00010000u) +#define EDMA3_CCRL_ERH_E48_SHIFT (0x00000010u) +#define EDMA3_CCRL_ERH_E48_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ERH_E47_MASK (0x00008000u) +#define EDMA3_CCRL_ERH_E47_SHIFT (0x0000000Fu) +#define EDMA3_CCRL_ERH_E47_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ERH_E46_MASK (0x00004000u) +#define EDMA3_CCRL_ERH_E46_SHIFT (0x0000000Eu) +#define EDMA3_CCRL_ERH_E46_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ERH_E45_MASK (0x00002000u) +#define EDMA3_CCRL_ERH_E45_SHIFT (0x0000000Du) +#define EDMA3_CCRL_ERH_E45_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ERH_E44_MASK (0x00001000u) +#define EDMA3_CCRL_ERH_E44_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_ERH_E44_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ERH_E43_MASK (0x00000800u) +#define EDMA3_CCRL_ERH_E43_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_ERH_E43_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ERH_E42_MASK (0x00000400u) +#define EDMA3_CCRL_ERH_E42_SHIFT (0x0000000Au) +#define EDMA3_CCRL_ERH_E42_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ERH_E41_MASK (0x00000200u) +#define EDMA3_CCRL_ERH_E41_SHIFT (0x00000009u) +#define EDMA3_CCRL_ERH_E41_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ERH_E40_MASK (0x00000100u) +#define EDMA3_CCRL_ERH_E40_SHIFT (0x00000008u) +#define EDMA3_CCRL_ERH_E40_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ERH_E39_MASK (0x00000080u) +#define EDMA3_CCRL_ERH_E39_SHIFT (0x00000007u) +#define EDMA3_CCRL_ERH_E39_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ERH_E38_MASK (0x00000040u) +#define EDMA3_CCRL_ERH_E38_SHIFT (0x00000006u) +#define EDMA3_CCRL_ERH_E38_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ERH_E37_MASK (0x00000020u) +#define EDMA3_CCRL_ERH_E37_SHIFT (0x00000005u) +#define EDMA3_CCRL_ERH_E37_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ERH_E36_MASK (0x00000010u) +#define EDMA3_CCRL_ERH_E36_SHIFT (0x00000004u) +#define EDMA3_CCRL_ERH_E36_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ERH_E35_MASK (0x00000008u) +#define EDMA3_CCRL_ERH_E35_SHIFT (0x00000003u) +#define EDMA3_CCRL_ERH_E35_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ERH_E34_MASK (0x00000004u) +#define EDMA3_CCRL_ERH_E34_SHIFT (0x00000002u) +#define EDMA3_CCRL_ERH_E34_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ERH_E33_MASK (0x00000002u) +#define EDMA3_CCRL_ERH_E33_SHIFT (0x00000001u) +#define EDMA3_CCRL_ERH_E33_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ERH_E32_MASK (0x00000001u) +#define EDMA3_CCRL_ERH_E32_SHIFT (0x00000000u) +#define EDMA3_CCRL_ERH_E32_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ERH_RESETVAL (0x00000000u) + +/* ECR */ + +#define EDMA3_CCRL_ECR_E31_MASK (0x80000000u) +#define EDMA3_CCRL_ECR_E31_SHIFT (0x0000001Fu) +#define EDMA3_CCRL_ECR_E31_RESETVAL (0x00000000u) + +/*----E31 Tokens----*/ +#define EDMA3_CCRL_ECR_E31_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECR_E30_MASK (0x40000000u) +#define EDMA3_CCRL_ECR_E30_SHIFT (0x0000001Eu) +#define EDMA3_CCRL_ECR_E30_RESETVAL (0x00000000u) + +/*----E30 Tokens----*/ +#define EDMA3_CCRL_ECR_E30_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECR_E29_MASK (0x20000000u) +#define EDMA3_CCRL_ECR_E29_SHIFT (0x0000001Du) +#define EDMA3_CCRL_ECR_E29_RESETVAL (0x00000000u) + +/*----E29 Tokens----*/ +#define EDMA3_CCRL_ECR_E29_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECR_E28_MASK (0x10000000u) +#define EDMA3_CCRL_ECR_E28_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_ECR_E28_RESETVAL (0x00000000u) + +/*----E28 Tokens----*/ +#define EDMA3_CCRL_ECR_E28_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECR_E27_MASK (0x08000000u) +#define EDMA3_CCRL_ECR_E27_SHIFT (0x0000001Bu) +#define EDMA3_CCRL_ECR_E27_RESETVAL (0x00000000u) + +/*----E27 Tokens----*/ +#define EDMA3_CCRL_ECR_E27_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECR_E26_MASK (0x04000000u) +#define EDMA3_CCRL_ECR_E26_SHIFT (0x0000001Au) +#define EDMA3_CCRL_ECR_E26_RESETVAL (0x00000000u) + +/*----E26 Tokens----*/ +#define EDMA3_CCRL_ECR_E26_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECR_E25_MASK (0x02000000u) +#define EDMA3_CCRL_ECR_E25_SHIFT (0x00000019u) +#define EDMA3_CCRL_ECR_E25_RESETVAL (0x00000000u) + +/*----E25 Tokens----*/ +#define EDMA3_CCRL_ECR_E25_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECR_E24_MASK (0x01000000u) +#define EDMA3_CCRL_ECR_E24_SHIFT (0x00000018u) +#define EDMA3_CCRL_ECR_E24_RESETVAL (0x00000000u) + +/*----E24 Tokens----*/ +#define EDMA3_CCRL_ECR_E24_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECR_E23_MASK (0x00800000u) +#define EDMA3_CCRL_ECR_E23_SHIFT (0x00000017u) +#define EDMA3_CCRL_ECR_E23_RESETVAL (0x00000000u) + +/*----E23 Tokens----*/ +#define EDMA3_CCRL_ECR_E23_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECR_E22_MASK (0x00400000u) +#define EDMA3_CCRL_ECR_E22_SHIFT (0x00000016u) +#define EDMA3_CCRL_ECR_E22_RESETVAL (0x00000000u) + +/*----E22 Tokens----*/ +#define EDMA3_CCRL_ECR_E22_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECR_E21_MASK (0x00200000u) +#define EDMA3_CCRL_ECR_E21_SHIFT (0x00000015u) +#define EDMA3_CCRL_ECR_E21_RESETVAL (0x00000000u) + +/*----E21 Tokens----*/ +#define EDMA3_CCRL_ECR_E21_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECR_E20_MASK (0x00100000u) +#define EDMA3_CCRL_ECR_E20_SHIFT (0x00000014u) +#define EDMA3_CCRL_ECR_E20_RESETVAL (0x00000000u) + +/*----E20 Tokens----*/ +#define EDMA3_CCRL_ECR_E20_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECR_E19_MASK (0x00080000u) +#define EDMA3_CCRL_ECR_E19_SHIFT (0x00000013u) +#define EDMA3_CCRL_ECR_E19_RESETVAL (0x00000000u) + +/*----E19 Tokens----*/ +#define EDMA3_CCRL_ECR_E19_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECR_E18_MASK (0x00040000u) +#define EDMA3_CCRL_ECR_E18_SHIFT (0x00000012u) +#define EDMA3_CCRL_ECR_E18_RESETVAL (0x00000000u) + +/*----E18 Tokens----*/ +#define EDMA3_CCRL_ECR_E18_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECR_E17_MASK (0x00020000u) +#define EDMA3_CCRL_ECR_E17_SHIFT (0x00000011u) +#define EDMA3_CCRL_ECR_E17_RESETVAL (0x00000000u) + +/*----E17 Tokens----*/ +#define EDMA3_CCRL_ECR_E17_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECR_E16_MASK (0x00010000u) +#define EDMA3_CCRL_ECR_E16_SHIFT (0x00000010u) +#define EDMA3_CCRL_ECR_E16_RESETVAL (0x00000000u) + +/*----E16 Tokens----*/ +#define EDMA3_CCRL_ECR_E16_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECR_E15_MASK (0x00008000u) +#define EDMA3_CCRL_ECR_E15_SHIFT (0x0000000Fu) +#define EDMA3_CCRL_ECR_E15_RESETVAL (0x00000000u) + +/*----E15 Tokens----*/ +#define EDMA3_CCRL_ECR_E15_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECR_E14_MASK (0x00004000u) +#define EDMA3_CCRL_ECR_E14_SHIFT (0x0000000Eu) +#define EDMA3_CCRL_ECR_E14_RESETVAL (0x00000000u) + +/*----E14 Tokens----*/ +#define EDMA3_CCRL_ECR_E14_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECR_E13_MASK (0x00002000u) +#define EDMA3_CCRL_ECR_E13_SHIFT (0x0000000Du) +#define EDMA3_CCRL_ECR_E13_RESETVAL (0x00000000u) + +/*----E13 Tokens----*/ +#define EDMA3_CCRL_ECR_E13_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECR_E12_MASK (0x00001000u) +#define EDMA3_CCRL_ECR_E12_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_ECR_E12_RESETVAL (0x00000000u) + +/*----E12 Tokens----*/ +#define EDMA3_CCRL_ECR_E12_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECR_E11_MASK (0x00000800u) +#define EDMA3_CCRL_ECR_E11_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_ECR_E11_RESETVAL (0x00000000u) + +/*----E11 Tokens----*/ +#define EDMA3_CCRL_ECR_E11_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECR_E10_MASK (0x00000400u) +#define EDMA3_CCRL_ECR_E10_SHIFT (0x0000000Au) +#define EDMA3_CCRL_ECR_E10_RESETVAL (0x00000000u) + +/*----E10 Tokens----*/ +#define EDMA3_CCRL_ECR_E10_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECR_E9_MASK (0x00000200u) +#define EDMA3_CCRL_ECR_E9_SHIFT (0x00000009u) +#define EDMA3_CCRL_ECR_E9_RESETVAL (0x00000000u) + +/*----E9 Tokens----*/ +#define EDMA3_CCRL_ECR_E9_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECR_E8_MASK (0x00000100u) +#define EDMA3_CCRL_ECR_E8_SHIFT (0x00000008u) +#define EDMA3_CCRL_ECR_E8_RESETVAL (0x00000000u) + +/*----E8 Tokens----*/ +#define EDMA3_CCRL_ECR_E8_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECR_E7_MASK (0x00000080u) +#define EDMA3_CCRL_ECR_E7_SHIFT (0x00000007u) +#define EDMA3_CCRL_ECR_E7_RESETVAL (0x00000000u) + +/*----E7 Tokens----*/ +#define EDMA3_CCRL_ECR_E7_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECR_E6_MASK (0x00000040u) +#define EDMA3_CCRL_ECR_E6_SHIFT (0x00000006u) +#define EDMA3_CCRL_ECR_E6_RESETVAL (0x00000000u) + +/*----E6 Tokens----*/ +#define EDMA3_CCRL_ECR_E6_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECR_E5_MASK (0x00000020u) +#define EDMA3_CCRL_ECR_E5_SHIFT (0x00000005u) +#define EDMA3_CCRL_ECR_E5_RESETVAL (0x00000000u) + +/*----E5 Tokens----*/ +#define EDMA3_CCRL_ECR_E5_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECR_E4_MASK (0x00000010u) +#define EDMA3_CCRL_ECR_E4_SHIFT (0x00000004u) +#define EDMA3_CCRL_ECR_E4_RESETVAL (0x00000000u) + +/*----E4 Tokens----*/ +#define EDMA3_CCRL_ECR_E4_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECR_E3_MASK (0x00000008u) +#define EDMA3_CCRL_ECR_E3_SHIFT (0x00000003u) +#define EDMA3_CCRL_ECR_E3_RESETVAL (0x00000000u) + +/*----E3 Tokens----*/ +#define EDMA3_CCRL_ECR_E3_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECR_E2_MASK (0x00000004u) +#define EDMA3_CCRL_ECR_E2_SHIFT (0x00000002u) +#define EDMA3_CCRL_ECR_E2_RESETVAL (0x00000000u) + +/*----E2 Tokens----*/ +#define EDMA3_CCRL_ECR_E2_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECR_E1_MASK (0x00000002u) +#define EDMA3_CCRL_ECR_E1_SHIFT (0x00000001u) +#define EDMA3_CCRL_ECR_E1_RESETVAL (0x00000000u) + +/*----E1 Tokens----*/ +#define EDMA3_CCRL_ECR_E1_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECR_E0_MASK (0x00000001u) +#define EDMA3_CCRL_ECR_E0_SHIFT (0x00000000u) +#define EDMA3_CCRL_ECR_E0_RESETVAL (0x00000000u) + +/*----E0 Tokens----*/ +#define EDMA3_CCRL_ECR_E0_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECR_RESETVAL (0x00000000u) + +/* ECRH */ + +#define EDMA3_CCRL_ECRH_E63_MASK (0x80000000u) +#define EDMA3_CCRL_ECRH_E63_SHIFT (0x0000001Fu) +#define EDMA3_CCRL_ECRH_E63_RESETVAL (0x00000000u) + +/*----E63 Tokens----*/ +#define EDMA3_CCRL_ECRH_E63_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECRH_E62_MASK (0x40000000u) +#define EDMA3_CCRL_ECRH_E62_SHIFT (0x0000001Eu) +#define EDMA3_CCRL_ECRH_E62_RESETVAL (0x00000000u) + +/*----E62 Tokens----*/ +#define EDMA3_CCRL_ECRH_E62_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECRH_E61_MASK (0x20000000u) +#define EDMA3_CCRL_ECRH_E61_SHIFT (0x0000001Du) +#define EDMA3_CCRL_ECRH_E61_RESETVAL (0x00000000u) + +/*----E61 Tokens----*/ +#define EDMA3_CCRL_ECRH_E61_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECRH_E60_MASK (0x10000000u) +#define EDMA3_CCRL_ECRH_E60_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_ECRH_E60_RESETVAL (0x00000000u) + +/*----E60 Tokens----*/ +#define EDMA3_CCRL_ECRH_E60_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECRH_E59_MASK (0x08000000u) +#define EDMA3_CCRL_ECRH_E59_SHIFT (0x0000001Bu) +#define EDMA3_CCRL_ECRH_E59_RESETVAL (0x00000000u) + +/*----E59 Tokens----*/ +#define EDMA3_CCRL_ECRH_E59_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECRH_E58_MASK (0x04000000u) +#define EDMA3_CCRL_ECRH_E58_SHIFT (0x0000001Au) +#define EDMA3_CCRL_ECRH_E58_RESETVAL (0x00000000u) + +/*----E58 Tokens----*/ +#define EDMA3_CCRL_ECRH_E58_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECRH_E57_MASK (0x02000000u) +#define EDMA3_CCRL_ECRH_E57_SHIFT (0x00000019u) +#define EDMA3_CCRL_ECRH_E57_RESETVAL (0x00000000u) + +/*----E57 Tokens----*/ +#define EDMA3_CCRL_ECRH_E57_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECRH_E56_MASK (0x01000000u) +#define EDMA3_CCRL_ECRH_E56_SHIFT (0x00000018u) +#define EDMA3_CCRL_ECRH_E56_RESETVAL (0x00000000u) + +/*----E56 Tokens----*/ +#define EDMA3_CCRL_ECRH_E56_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECRH_E55_MASK (0x00800000u) +#define EDMA3_CCRL_ECRH_E55_SHIFT (0x00000017u) +#define EDMA3_CCRL_ECRH_E55_RESETVAL (0x00000000u) + +/*----E55 Tokens----*/ +#define EDMA3_CCRL_ECRH_E55_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECRH_E54_MASK (0x00400000u) +#define EDMA3_CCRL_ECRH_E54_SHIFT (0x00000016u) +#define EDMA3_CCRL_ECRH_E54_RESETVAL (0x00000000u) + +/*----E54 Tokens----*/ +#define EDMA3_CCRL_ECRH_E54_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECRH_E53_MASK (0x00200000u) +#define EDMA3_CCRL_ECRH_E53_SHIFT (0x00000015u) +#define EDMA3_CCRL_ECRH_E53_RESETVAL (0x00000000u) + +/*----E53 Tokens----*/ +#define EDMA3_CCRL_ECRH_E53_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECRH_E52_MASK (0x00100000u) +#define EDMA3_CCRL_ECRH_E52_SHIFT (0x00000014u) +#define EDMA3_CCRL_ECRH_E52_RESETVAL (0x00000000u) + +/*----E52 Tokens----*/ +#define EDMA3_CCRL_ECRH_E52_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECRH_E51_MASK (0x00080000u) +#define EDMA3_CCRL_ECRH_E51_SHIFT (0x00000013u) +#define EDMA3_CCRL_ECRH_E51_RESETVAL (0x00000000u) + +/*----E51 Tokens----*/ +#define EDMA3_CCRL_ECRH_E51_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECRH_E50_MASK (0x00040000u) +#define EDMA3_CCRL_ECRH_E50_SHIFT (0x00000012u) +#define EDMA3_CCRL_ECRH_E50_RESETVAL (0x00000000u) + +/*----E50 Tokens----*/ +#define EDMA3_CCRL_ECRH_E50_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECRH_E49_MASK (0x00020000u) +#define EDMA3_CCRL_ECRH_E49_SHIFT (0x00000011u) +#define EDMA3_CCRL_ECRH_E49_RESETVAL (0x00000000u) + +/*----E49 Tokens----*/ +#define EDMA3_CCRL_ECRH_E49_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECRH_E48_MASK (0x00010000u) +#define EDMA3_CCRL_ECRH_E48_SHIFT (0x00000010u) +#define EDMA3_CCRL_ECRH_E48_RESETVAL (0x00000000u) + +/*----E48 Tokens----*/ +#define EDMA3_CCRL_ECRH_E48_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECRH_E47_MASK (0x00008000u) +#define EDMA3_CCRL_ECRH_E47_SHIFT (0x0000000Fu) +#define EDMA3_CCRL_ECRH_E47_RESETVAL (0x00000000u) + +/*----E47 Tokens----*/ +#define EDMA3_CCRL_ECRH_E47_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECRH_E46_MASK (0x00004000u) +#define EDMA3_CCRL_ECRH_E46_SHIFT (0x0000000Eu) +#define EDMA3_CCRL_ECRH_E46_RESETVAL (0x00000000u) + +/*----E46 Tokens----*/ +#define EDMA3_CCRL_ECRH_E46_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECRH_E45_MASK (0x00002000u) +#define EDMA3_CCRL_ECRH_E45_SHIFT (0x0000000Du) +#define EDMA3_CCRL_ECRH_E45_RESETVAL (0x00000000u) + +/*----E45 Tokens----*/ +#define EDMA3_CCRL_ECRH_E45_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECRH_E44_MASK (0x00001000u) +#define EDMA3_CCRL_ECRH_E44_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_ECRH_E44_RESETVAL (0x00000000u) + +/*----E44 Tokens----*/ +#define EDMA3_CCRL_ECRH_E44_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECRH_E43_MASK (0x00000800u) +#define EDMA3_CCRL_ECRH_E43_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_ECRH_E43_RESETVAL (0x00000000u) + +/*----E43 Tokens----*/ +#define EDMA3_CCRL_ECRH_E43_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECRH_E42_MASK (0x00000400u) +#define EDMA3_CCRL_ECRH_E42_SHIFT (0x0000000Au) +#define EDMA3_CCRL_ECRH_E42_RESETVAL (0x00000000u) + +/*----E42 Tokens----*/ +#define EDMA3_CCRL_ECRH_E42_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECRH_E41_MASK (0x00000200u) +#define EDMA3_CCRL_ECRH_E41_SHIFT (0x00000009u) +#define EDMA3_CCRL_ECRH_E41_RESETVAL (0x00000000u) + +/*----E41 Tokens----*/ +#define EDMA3_CCRL_ECRH_E41_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECRH_E40_MASK (0x00000100u) +#define EDMA3_CCRL_ECRH_E40_SHIFT (0x00000008u) +#define EDMA3_CCRL_ECRH_E40_RESETVAL (0x00000000u) + +/*----E40 Tokens----*/ +#define EDMA3_CCRL_ECRH_E40_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECRH_E39_MASK (0x00000080u) +#define EDMA3_CCRL_ECRH_E39_SHIFT (0x00000007u) +#define EDMA3_CCRL_ECRH_E39_RESETVAL (0x00000000u) + +/*----E39 Tokens----*/ +#define EDMA3_CCRL_ECRH_E39_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECRH_E38_MASK (0x00000040u) +#define EDMA3_CCRL_ECRH_E38_SHIFT (0x00000006u) +#define EDMA3_CCRL_ECRH_E38_RESETVAL (0x00000000u) + +/*----E38 Tokens----*/ +#define EDMA3_CCRL_ECRH_E38_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECRH_E37_MASK (0x00000020u) +#define EDMA3_CCRL_ECRH_E37_SHIFT (0x00000005u) +#define EDMA3_CCRL_ECRH_E37_RESETVAL (0x00000000u) + +/*----E37 Tokens----*/ +#define EDMA3_CCRL_ECRH_E37_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECRH_E36_MASK (0x00000010u) +#define EDMA3_CCRL_ECRH_E36_SHIFT (0x00000004u) +#define EDMA3_CCRL_ECRH_E36_RESETVAL (0x00000000u) + +/*----E36 Tokens----*/ +#define EDMA3_CCRL_ECRH_E36_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECRH_E35_MASK (0x00000008u) +#define EDMA3_CCRL_ECRH_E35_SHIFT (0x00000003u) +#define EDMA3_CCRL_ECRH_E35_RESETVAL (0x00000000u) + +/*----E35 Tokens----*/ +#define EDMA3_CCRL_ECRH_E35_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECRH_E34_MASK (0x00000004u) +#define EDMA3_CCRL_ECRH_E34_SHIFT (0x00000002u) +#define EDMA3_CCRL_ECRH_E34_RESETVAL (0x00000000u) + +/*----E34 Tokens----*/ +#define EDMA3_CCRL_ECRH_E34_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECRH_E33_MASK (0x00000002u) +#define EDMA3_CCRL_ECRH_E33_SHIFT (0x00000001u) +#define EDMA3_CCRL_ECRH_E33_RESETVAL (0x00000000u) + +/*----E33 Tokens----*/ +#define EDMA3_CCRL_ECRH_E33_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECRH_E32_MASK (0x00000001u) +#define EDMA3_CCRL_ECRH_E32_SHIFT (0x00000000u) +#define EDMA3_CCRL_ECRH_E32_RESETVAL (0x00000000u) + +/*----E32 Tokens----*/ +#define EDMA3_CCRL_ECRH_E32_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ECRH_RESETVAL (0x00000000u) + +/* ESR */ + +#define EDMA3_CCRL_ESR_E31_MASK (0x80000000u) +#define EDMA3_CCRL_ESR_E31_SHIFT (0x0000001Fu) +#define EDMA3_CCRL_ESR_E31_RESETVAL (0x00000000u) + +/*----E31 Tokens----*/ +#define EDMA3_CCRL_ESR_E31_SET (0x00000001u) + +#define EDMA3_CCRL_ESR_E30_MASK (0x40000000u) +#define EDMA3_CCRL_ESR_E30_SHIFT (0x0000001Eu) +#define EDMA3_CCRL_ESR_E30_RESETVAL (0x00000000u) + +/*----E30 Tokens----*/ +#define EDMA3_CCRL_ESR_E30_SET (0x00000001u) + +#define EDMA3_CCRL_ESR_E29_MASK (0x20000000u) +#define EDMA3_CCRL_ESR_E29_SHIFT (0x0000001Du) +#define EDMA3_CCRL_ESR_E29_RESETVAL (0x00000000u) + +/*----E29 Tokens----*/ +#define EDMA3_CCRL_ESR_E29_SET (0x00000001u) + +#define EDMA3_CCRL_ESR_E28_MASK (0x10000000u) +#define EDMA3_CCRL_ESR_E28_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_ESR_E28_RESETVAL (0x00000000u) + +/*----E28 Tokens----*/ +#define EDMA3_CCRL_ESR_E28_SET (0x00000001u) + +#define EDMA3_CCRL_ESR_E27_MASK (0x08000000u) +#define EDMA3_CCRL_ESR_E27_SHIFT (0x0000001Bu) +#define EDMA3_CCRL_ESR_E27_RESETVAL (0x00000000u) + +/*----E27 Tokens----*/ +#define EDMA3_CCRL_ESR_E27_SET (0x00000001u) + +#define EDMA3_CCRL_ESR_E26_MASK (0x04000000u) +#define EDMA3_CCRL_ESR_E26_SHIFT (0x0000001Au) +#define EDMA3_CCRL_ESR_E26_RESETVAL (0x00000000u) + +/*----E26 Tokens----*/ +#define EDMA3_CCRL_ESR_E26_SET (0x00000001u) + +#define EDMA3_CCRL_ESR_E25_MASK (0x02000000u) +#define EDMA3_CCRL_ESR_E25_SHIFT (0x00000019u) +#define EDMA3_CCRL_ESR_E25_RESETVAL (0x00000000u) + +/*----E25 Tokens----*/ +#define EDMA3_CCRL_ESR_E25_SET (0x00000001u) + +#define EDMA3_CCRL_ESR_E24_MASK (0x01000000u) +#define EDMA3_CCRL_ESR_E24_SHIFT (0x00000018u) +#define EDMA3_CCRL_ESR_E24_RESETVAL (0x00000000u) + +/*----E24 Tokens----*/ +#define EDMA3_CCRL_ESR_E24_SET (0x00000001u) + +#define EDMA3_CCRL_ESR_E23_MASK (0x00800000u) +#define EDMA3_CCRL_ESR_E23_SHIFT (0x00000017u) +#define EDMA3_CCRL_ESR_E23_RESETVAL (0x00000000u) + +/*----E23 Tokens----*/ +#define EDMA3_CCRL_ESR_E23_SET (0x00000001u) + +#define EDMA3_CCRL_ESR_E22_MASK (0x00400000u) +#define EDMA3_CCRL_ESR_E22_SHIFT (0x00000016u) +#define EDMA3_CCRL_ESR_E22_RESETVAL (0x00000000u) + +/*----E22 Tokens----*/ +#define EDMA3_CCRL_ESR_E22_SET (0x00000001u) + +#define EDMA3_CCRL_ESR_E21_MASK (0x00200000u) +#define EDMA3_CCRL_ESR_E21_SHIFT (0x00000015u) +#define EDMA3_CCRL_ESR_E21_RESETVAL (0x00000000u) + +/*----E21 Tokens----*/ +#define EDMA3_CCRL_ESR_E21_SET (0x00000001u) + +#define EDMA3_CCRL_ESR_E20_MASK (0x00100000u) +#define EDMA3_CCRL_ESR_E20_SHIFT (0x00000014u) +#define EDMA3_CCRL_ESR_E20_RESETVAL (0x00000000u) + +/*----E20 Tokens----*/ +#define EDMA3_CCRL_ESR_E20_SET (0x00000001u) + +#define EDMA3_CCRL_ESR_E19_MASK (0x00080000u) +#define EDMA3_CCRL_ESR_E19_SHIFT (0x00000013u) +#define EDMA3_CCRL_ESR_E19_RESETVAL (0x00000000u) + +/*----E19 Tokens----*/ +#define EDMA3_CCRL_ESR_E19_SET (0x00000001u) + +#define EDMA3_CCRL_ESR_E18_MASK (0x00040000u) +#define EDMA3_CCRL_ESR_E18_SHIFT (0x00000012u) +#define EDMA3_CCRL_ESR_E18_RESETVAL (0x00000000u) + +/*----E18 Tokens----*/ +#define EDMA3_CCRL_ESR_E18_SET (0x00000001u) + +#define EDMA3_CCRL_ESR_E17_MASK (0x00020000u) +#define EDMA3_CCRL_ESR_E17_SHIFT (0x00000011u) +#define EDMA3_CCRL_ESR_E17_RESETVAL (0x00000000u) + +/*----E17 Tokens----*/ +#define EDMA3_CCRL_ESR_E17_SET (0x00000001u) + +#define EDMA3_CCRL_ESR_E16_MASK (0x00010000u) +#define EDMA3_CCRL_ESR_E16_SHIFT (0x00000010u) +#define EDMA3_CCRL_ESR_E16_RESETVAL (0x00000000u) + +/*----E16 Tokens----*/ +#define EDMA3_CCRL_ESR_E16_SET (0x00000001u) + +#define EDMA3_CCRL_ESR_E15_MASK (0x00008000u) +#define EDMA3_CCRL_ESR_E15_SHIFT (0x0000000Fu) +#define EDMA3_CCRL_ESR_E15_RESETVAL (0x00000000u) + +/*----E15 Tokens----*/ +#define EDMA3_CCRL_ESR_E15_SET (0x00000001u) + +#define EDMA3_CCRL_ESR_E14_MASK (0x00004000u) +#define EDMA3_CCRL_ESR_E14_SHIFT (0x0000000Eu) +#define EDMA3_CCRL_ESR_E14_RESETVAL (0x00000000u) + +/*----E14 Tokens----*/ +#define EDMA3_CCRL_ESR_E14_SET (0x00000001u) + +#define EDMA3_CCRL_ESR_E13_MASK (0x00002000u) +#define EDMA3_CCRL_ESR_E13_SHIFT (0x0000000Du) +#define EDMA3_CCRL_ESR_E13_RESETVAL (0x00000000u) + +/*----E13 Tokens----*/ +#define EDMA3_CCRL_ESR_E13_SET (0x00000001u) + +#define EDMA3_CCRL_ESR_E12_MASK (0x00001000u) +#define EDMA3_CCRL_ESR_E12_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_ESR_E12_RESETVAL (0x00000000u) + +/*----E12 Tokens----*/ +#define EDMA3_CCRL_ESR_E12_SET (0x00000001u) + +#define EDMA3_CCRL_ESR_E11_MASK (0x00000800u) +#define EDMA3_CCRL_ESR_E11_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_ESR_E11_RESETVAL (0x00000000u) + +/*----E11 Tokens----*/ +#define EDMA3_CCRL_ESR_E11_SET (0x00000001u) + +#define EDMA3_CCRL_ESR_E10_MASK (0x00000400u) +#define EDMA3_CCRL_ESR_E10_SHIFT (0x0000000Au) +#define EDMA3_CCRL_ESR_E10_RESETVAL (0x00000000u) + +/*----E10 Tokens----*/ +#define EDMA3_CCRL_ESR_E10_SET (0x00000001u) + +#define EDMA3_CCRL_ESR_E9_MASK (0x00000200u) +#define EDMA3_CCRL_ESR_E9_SHIFT (0x00000009u) +#define EDMA3_CCRL_ESR_E9_RESETVAL (0x00000000u) + +/*----E9 Tokens----*/ +#define EDMA3_CCRL_ESR_E9_SET (0x00000001u) + +#define EDMA3_CCRL_ESR_E8_MASK (0x00000100u) +#define EDMA3_CCRL_ESR_E8_SHIFT (0x00000008u) +#define EDMA3_CCRL_ESR_E8_RESETVAL (0x00000000u) + +/*----E8 Tokens----*/ +#define EDMA3_CCRL_ESR_E8_SET (0x00000001u) + +#define EDMA3_CCRL_ESR_E7_MASK (0x00000080u) +#define EDMA3_CCRL_ESR_E7_SHIFT (0x00000007u) +#define EDMA3_CCRL_ESR_E7_RESETVAL (0x00000000u) + +/*----E7 Tokens----*/ +#define EDMA3_CCRL_ESR_E7_SET (0x00000001u) + +#define EDMA3_CCRL_ESR_E6_MASK (0x00000040u) +#define EDMA3_CCRL_ESR_E6_SHIFT (0x00000006u) +#define EDMA3_CCRL_ESR_E6_RESETVAL (0x00000000u) + +/*----E6 Tokens----*/ +#define EDMA3_CCRL_ESR_E6_SET (0x00000001u) + +#define EDMA3_CCRL_ESR_E5_MASK (0x00000020u) +#define EDMA3_CCRL_ESR_E5_SHIFT (0x00000005u) +#define EDMA3_CCRL_ESR_E5_RESETVAL (0x00000000u) + +/*----E5 Tokens----*/ +#define EDMA3_CCRL_ESR_E5_SET (0x00000001u) + +#define EDMA3_CCRL_ESR_E4_MASK (0x00000010u) +#define EDMA3_CCRL_ESR_E4_SHIFT (0x00000004u) +#define EDMA3_CCRL_ESR_E4_RESETVAL (0x00000000u) + +/*----E4 Tokens----*/ +#define EDMA3_CCRL_ESR_E4_SET (0x00000001u) + +#define EDMA3_CCRL_ESR_E3_MASK (0x00000008u) +#define EDMA3_CCRL_ESR_E3_SHIFT (0x00000003u) +#define EDMA3_CCRL_ESR_E3_RESETVAL (0x00000000u) + +/*----E3 Tokens----*/ +#define EDMA3_CCRL_ESR_E3_SET (0x00000001u) + +#define EDMA3_CCRL_ESR_E2_MASK (0x00000004u) +#define EDMA3_CCRL_ESR_E2_SHIFT (0x00000002u) +#define EDMA3_CCRL_ESR_E2_RESETVAL (0x00000000u) + +/*----E2 Tokens----*/ +#define EDMA3_CCRL_ESR_E2_SET (0x00000001u) + +#define EDMA3_CCRL_ESR_E1_MASK (0x00000002u) +#define EDMA3_CCRL_ESR_E1_SHIFT (0x00000001u) +#define EDMA3_CCRL_ESR_E1_RESETVAL (0x00000000u) + +/*----E1 Tokens----*/ +#define EDMA3_CCRL_ESR_E1_SET (0x00000001u) + +#define EDMA3_CCRL_ESR_E0_MASK (0x00000001u) +#define EDMA3_CCRL_ESR_E0_SHIFT (0x00000000u) +#define EDMA3_CCRL_ESR_E0_RESETVAL (0x00000000u) + +/*----E0 Tokens----*/ +#define EDMA3_CCRL_ESR_E0_SET (0x00000001u) + +#define EDMA3_CCRL_ESR_RESETVAL (0x00000000u) + +/* ESRH */ + +#define EDMA3_CCRL_ESRH_E63_MASK (0x80000000u) +#define EDMA3_CCRL_ESRH_E63_SHIFT (0x0000001Fu) +#define EDMA3_CCRL_ESRH_E63_RESETVAL (0x00000000u) + +/*----E63 Tokens----*/ +#define EDMA3_CCRL_ESRH_E63_SET (0x00000001u) + +#define EDMA3_CCRL_ESRH_E62_MASK (0x40000000u) +#define EDMA3_CCRL_ESRH_E62_SHIFT (0x0000001Eu) +#define EDMA3_CCRL_ESRH_E62_RESETVAL (0x00000000u) + +/*----E62 Tokens----*/ +#define EDMA3_CCRL_ESRH_E62_SET (0x00000001u) + +#define EDMA3_CCRL_ESRH_E61_MASK (0x20000000u) +#define EDMA3_CCRL_ESRH_E61_SHIFT (0x0000001Du) +#define EDMA3_CCRL_ESRH_E61_RESETVAL (0x00000000u) + +/*----E61 Tokens----*/ +#define EDMA3_CCRL_ESRH_E61_SET (0x00000001u) + +#define EDMA3_CCRL_ESRH_E60_MASK (0x10000000u) +#define EDMA3_CCRL_ESRH_E60_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_ESRH_E60_RESETVAL (0x00000000u) + +/*----E60 Tokens----*/ +#define EDMA3_CCRL_ESRH_E60_SET (0x00000001u) + +#define EDMA3_CCRL_ESRH_E59_MASK (0x08000000u) +#define EDMA3_CCRL_ESRH_E59_SHIFT (0x0000001Bu) +#define EDMA3_CCRL_ESRH_E59_RESETVAL (0x00000000u) + +/*----E59 Tokens----*/ +#define EDMA3_CCRL_ESRH_E59_SET (0x00000001u) + +#define EDMA3_CCRL_ESRH_E58_MASK (0x04000000u) +#define EDMA3_CCRL_ESRH_E58_SHIFT (0x0000001Au) +#define EDMA3_CCRL_ESRH_E58_RESETVAL (0x00000000u) + +/*----E58 Tokens----*/ +#define EDMA3_CCRL_ESRH_E58_SET (0x00000001u) + +#define EDMA3_CCRL_ESRH_E57_MASK (0x02000000u) +#define EDMA3_CCRL_ESRH_E57_SHIFT (0x00000019u) +#define EDMA3_CCRL_ESRH_E57_RESETVAL (0x00000000u) + +/*----E57 Tokens----*/ +#define EDMA3_CCRL_ESRH_E57_SET (0x00000001u) + +#define EDMA3_CCRL_ESRH_E56_MASK (0x01000000u) +#define EDMA3_CCRL_ESRH_E56_SHIFT (0x00000018u) +#define EDMA3_CCRL_ESRH_E56_RESETVAL (0x00000000u) + +/*----E56 Tokens----*/ +#define EDMA3_CCRL_ESRH_E56_SET (0x00000001u) + +#define EDMA3_CCRL_ESRH_E55_MASK (0x00800000u) +#define EDMA3_CCRL_ESRH_E55_SHIFT (0x00000017u) +#define EDMA3_CCRL_ESRH_E55_RESETVAL (0x00000000u) + +/*----E55 Tokens----*/ +#define EDMA3_CCRL_ESRH_E55_SET (0x00000001u) + +#define EDMA3_CCRL_ESRH_E54_MASK (0x00400000u) +#define EDMA3_CCRL_ESRH_E54_SHIFT (0x00000016u) +#define EDMA3_CCRL_ESRH_E54_RESETVAL (0x00000000u) + +/*----E54 Tokens----*/ +#define EDMA3_CCRL_ESRH_E54_SET (0x00000001u) + +#define EDMA3_CCRL_ESRH_E53_MASK (0x00200000u) +#define EDMA3_CCRL_ESRH_E53_SHIFT (0x00000015u) +#define EDMA3_CCRL_ESRH_E53_RESETVAL (0x00000000u) + +/*----E53 Tokens----*/ +#define EDMA3_CCRL_ESRH_E53_SET (0x00000001u) + +#define EDMA3_CCRL_ESRH_E52_MASK (0x00100000u) +#define EDMA3_CCRL_ESRH_E52_SHIFT (0x00000014u) +#define EDMA3_CCRL_ESRH_E52_RESETVAL (0x00000000u) + +/*----E52 Tokens----*/ +#define EDMA3_CCRL_ESRH_E52_SET (0x00000001u) + +#define EDMA3_CCRL_ESRH_E51_MASK (0x00080000u) +#define EDMA3_CCRL_ESRH_E51_SHIFT (0x00000013u) +#define EDMA3_CCRL_ESRH_E51_RESETVAL (0x00000000u) + +/*----E51 Tokens----*/ +#define EDMA3_CCRL_ESRH_E51_SET (0x00000001u) + +#define EDMA3_CCRL_ESRH_E50_MASK (0x00040000u) +#define EDMA3_CCRL_ESRH_E50_SHIFT (0x00000012u) +#define EDMA3_CCRL_ESRH_E50_RESETVAL (0x00000000u) + +/*----E50 Tokens----*/ +#define EDMA3_CCRL_ESRH_E50_SET (0x00000001u) + +#define EDMA3_CCRL_ESRH_E49_MASK (0x00020000u) +#define EDMA3_CCRL_ESRH_E49_SHIFT (0x00000011u) +#define EDMA3_CCRL_ESRH_E49_RESETVAL (0x00000000u) + +/*----E49 Tokens----*/ +#define EDMA3_CCRL_ESRH_E49_SET (0x00000001u) + +#define EDMA3_CCRL_ESRH_E48_MASK (0x00010000u) +#define EDMA3_CCRL_ESRH_E48_SHIFT (0x00000010u) +#define EDMA3_CCRL_ESRH_E48_RESETVAL (0x00000000u) + +/*----E48 Tokens----*/ +#define EDMA3_CCRL_ESRH_E48_SET (0x00000001u) + +#define EDMA3_CCRL_ESRH_E47_MASK (0x00008000u) +#define EDMA3_CCRL_ESRH_E47_SHIFT (0x0000000Fu) +#define EDMA3_CCRL_ESRH_E47_RESETVAL (0x00000000u) + +/*----E47 Tokens----*/ +#define EDMA3_CCRL_ESRH_E47_SET (0x00000001u) + +#define EDMA3_CCRL_ESRH_E46_MASK (0x00004000u) +#define EDMA3_CCRL_ESRH_E46_SHIFT (0x0000000Eu) +#define EDMA3_CCRL_ESRH_E46_RESETVAL (0x00000000u) + +/*----E46 Tokens----*/ +#define EDMA3_CCRL_ESRH_E46_SET (0x00000001u) + +#define EDMA3_CCRL_ESRH_E45_MASK (0x00002000u) +#define EDMA3_CCRL_ESRH_E45_SHIFT (0x0000000Du) +#define EDMA3_CCRL_ESRH_E45_RESETVAL (0x00000000u) + +/*----E45 Tokens----*/ +#define EDMA3_CCRL_ESRH_E45_SET (0x00000001u) + +#define EDMA3_CCRL_ESRH_E44_MASK (0x00001000u) +#define EDMA3_CCRL_ESRH_E44_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_ESRH_E44_RESETVAL (0x00000000u) + +/*----E44 Tokens----*/ +#define EDMA3_CCRL_ESRH_E44_SET (0x00000001u) + +#define EDMA3_CCRL_ESRH_E43_MASK (0x00000800u) +#define EDMA3_CCRL_ESRH_E43_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_ESRH_E43_RESETVAL (0x00000000u) + +/*----E43 Tokens----*/ +#define EDMA3_CCRL_ESRH_E43_SET (0x00000001u) + +#define EDMA3_CCRL_ESRH_E42_MASK (0x00000400u) +#define EDMA3_CCRL_ESRH_E42_SHIFT (0x0000000Au) +#define EDMA3_CCRL_ESRH_E42_RESETVAL (0x00000000u) + +/*----E42 Tokens----*/ +#define EDMA3_CCRL_ESRH_E42_SET (0x00000001u) + +#define EDMA3_CCRL_ESRH_E41_MASK (0x00000200u) +#define EDMA3_CCRL_ESRH_E41_SHIFT (0x00000009u) +#define EDMA3_CCRL_ESRH_E41_RESETVAL (0x00000000u) + +/*----E41 Tokens----*/ +#define EDMA3_CCRL_ESRH_E41_SET (0x00000001u) + +#define EDMA3_CCRL_ESRH_E40_MASK (0x00000100u) +#define EDMA3_CCRL_ESRH_E40_SHIFT (0x00000008u) +#define EDMA3_CCRL_ESRH_E40_RESETVAL (0x00000000u) + +/*----E40 Tokens----*/ +#define EDMA3_CCRL_ESRH_E40_SET (0x00000001u) + +#define EDMA3_CCRL_ESRH_E39_MASK (0x00000080u) +#define EDMA3_CCRL_ESRH_E39_SHIFT (0x00000007u) +#define EDMA3_CCRL_ESRH_E39_RESETVAL (0x00000000u) + +/*----E39 Tokens----*/ +#define EDMA3_CCRL_ESRH_E39_SET (0x00000001u) + +#define EDMA3_CCRL_ESRH_E38_MASK (0x00000040u) +#define EDMA3_CCRL_ESRH_E38_SHIFT (0x00000006u) +#define EDMA3_CCRL_ESRH_E38_RESETVAL (0x00000000u) + +/*----E38 Tokens----*/ +#define EDMA3_CCRL_ESRH_E38_SET (0x00000001u) + +#define EDMA3_CCRL_ESRH_E37_MASK (0x00000020u) +#define EDMA3_CCRL_ESRH_E37_SHIFT (0x00000005u) +#define EDMA3_CCRL_ESRH_E37_RESETVAL (0x00000000u) + +/*----E37 Tokens----*/ +#define EDMA3_CCRL_ESRH_E37_SET (0x00000001u) + +#define EDMA3_CCRL_ESRH_E36_MASK (0x00000010u) +#define EDMA3_CCRL_ESRH_E36_SHIFT (0x00000004u) +#define EDMA3_CCRL_ESRH_E36_RESETVAL (0x00000000u) + +/*----E36 Tokens----*/ +#define EDMA3_CCRL_ESRH_E36_SET (0x00000001u) + +#define EDMA3_CCRL_ESRH_E35_MASK (0x00000008u) +#define EDMA3_CCRL_ESRH_E35_SHIFT (0x00000003u) +#define EDMA3_CCRL_ESRH_E35_RESETVAL (0x00000000u) + +/*----E35 Tokens----*/ +#define EDMA3_CCRL_ESRH_E35_SET (0x00000001u) + +#define EDMA3_CCRL_ESRH_E34_MASK (0x00000004u) +#define EDMA3_CCRL_ESRH_E34_SHIFT (0x00000002u) +#define EDMA3_CCRL_ESRH_E34_RESETVAL (0x00000000u) + +/*----E34 Tokens----*/ +#define EDMA3_CCRL_ESRH_E34_SET (0x00000001u) + +#define EDMA3_CCRL_ESRH_E33_MASK (0x00000002u) +#define EDMA3_CCRL_ESRH_E33_SHIFT (0x00000001u) +#define EDMA3_CCRL_ESRH_E33_RESETVAL (0x00000000u) + +/*----E33 Tokens----*/ +#define EDMA3_CCRL_ESRH_E33_SET (0x00000001u) + +#define EDMA3_CCRL_ESRH_E32_MASK (0x00000001u) +#define EDMA3_CCRL_ESRH_E32_SHIFT (0x00000000u) +#define EDMA3_CCRL_ESRH_E32_RESETVAL (0x00000000u) + +/*----E32 Tokens----*/ +#define EDMA3_CCRL_ESRH_E32_SET (0x00000001u) + +#define EDMA3_CCRL_ESRH_RESETVAL (0x00000000u) + +/* CER */ + +#define EDMA3_CCRL_CER_E31_MASK (0x80000000u) +#define EDMA3_CCRL_CER_E31_SHIFT (0x0000001Fu) +#define EDMA3_CCRL_CER_E31_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CER_E30_MASK (0x40000000u) +#define EDMA3_CCRL_CER_E30_SHIFT (0x0000001Eu) +#define EDMA3_CCRL_CER_E30_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CER_E29_MASK (0x20000000u) +#define EDMA3_CCRL_CER_E29_SHIFT (0x0000001Du) +#define EDMA3_CCRL_CER_E29_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CER_E28_MASK (0x10000000u) +#define EDMA3_CCRL_CER_E28_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_CER_E28_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CER_E27_MASK (0x08000000u) +#define EDMA3_CCRL_CER_E27_SHIFT (0x0000001Bu) +#define EDMA3_CCRL_CER_E27_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CER_E26_MASK (0x04000000u) +#define EDMA3_CCRL_CER_E26_SHIFT (0x0000001Au) +#define EDMA3_CCRL_CER_E26_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CER_E25_MASK (0x02000000u) +#define EDMA3_CCRL_CER_E25_SHIFT (0x00000019u) +#define EDMA3_CCRL_CER_E25_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CER_E24_MASK (0x01000000u) +#define EDMA3_CCRL_CER_E24_SHIFT (0x00000018u) +#define EDMA3_CCRL_CER_E24_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CER_E23_MASK (0x00800000u) +#define EDMA3_CCRL_CER_E23_SHIFT (0x00000017u) +#define EDMA3_CCRL_CER_E23_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CER_E22_MASK (0x00400000u) +#define EDMA3_CCRL_CER_E22_SHIFT (0x00000016u) +#define EDMA3_CCRL_CER_E22_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CER_E21_MASK (0x00200000u) +#define EDMA3_CCRL_CER_E21_SHIFT (0x00000015u) +#define EDMA3_CCRL_CER_E21_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CER_E20_MASK (0x00100000u) +#define EDMA3_CCRL_CER_E20_SHIFT (0x00000014u) +#define EDMA3_CCRL_CER_E20_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CER_E19_MASK (0x00080000u) +#define EDMA3_CCRL_CER_E19_SHIFT (0x00000013u) +#define EDMA3_CCRL_CER_E19_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CER_E18_MASK (0x00040000u) +#define EDMA3_CCRL_CER_E18_SHIFT (0x00000012u) +#define EDMA3_CCRL_CER_E18_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CER_E17_MASK (0x00020000u) +#define EDMA3_CCRL_CER_E17_SHIFT (0x00000011u) +#define EDMA3_CCRL_CER_E17_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CER_E16_MASK (0x00010000u) +#define EDMA3_CCRL_CER_E16_SHIFT (0x00000010u) +#define EDMA3_CCRL_CER_E16_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CER_E15_MASK (0x00008000u) +#define EDMA3_CCRL_CER_E15_SHIFT (0x0000000Fu) +#define EDMA3_CCRL_CER_E15_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CER_E14_MASK (0x00004000u) +#define EDMA3_CCRL_CER_E14_SHIFT (0x0000000Eu) +#define EDMA3_CCRL_CER_E14_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CER_E13_MASK (0x00002000u) +#define EDMA3_CCRL_CER_E13_SHIFT (0x0000000Du) +#define EDMA3_CCRL_CER_E13_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CER_E12_MASK (0x00001000u) +#define EDMA3_CCRL_CER_E12_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_CER_E12_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CER_E11_MASK (0x00000800u) +#define EDMA3_CCRL_CER_E11_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_CER_E11_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CER_E10_MASK (0x00000400u) +#define EDMA3_CCRL_CER_E10_SHIFT (0x0000000Au) +#define EDMA3_CCRL_CER_E10_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CER_E9_MASK (0x00000200u) +#define EDMA3_CCRL_CER_E9_SHIFT (0x00000009u) +#define EDMA3_CCRL_CER_E9_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CER_E8_MASK (0x00000100u) +#define EDMA3_CCRL_CER_E8_SHIFT (0x00000008u) +#define EDMA3_CCRL_CER_E8_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CER_E7_MASK (0x00000080u) +#define EDMA3_CCRL_CER_E7_SHIFT (0x00000007u) +#define EDMA3_CCRL_CER_E7_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CER_E6_MASK (0x00000040u) +#define EDMA3_CCRL_CER_E6_SHIFT (0x00000006u) +#define EDMA3_CCRL_CER_E6_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CER_E5_MASK (0x00000020u) +#define EDMA3_CCRL_CER_E5_SHIFT (0x00000005u) +#define EDMA3_CCRL_CER_E5_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CER_E4_MASK (0x00000010u) +#define EDMA3_CCRL_CER_E4_SHIFT (0x00000004u) +#define EDMA3_CCRL_CER_E4_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CER_E3_MASK (0x00000008u) +#define EDMA3_CCRL_CER_E3_SHIFT (0x00000003u) +#define EDMA3_CCRL_CER_E3_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CER_E2_MASK (0x00000004u) +#define EDMA3_CCRL_CER_E2_SHIFT (0x00000002u) +#define EDMA3_CCRL_CER_E2_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CER_E1_MASK (0x00000002u) +#define EDMA3_CCRL_CER_E1_SHIFT (0x00000001u) +#define EDMA3_CCRL_CER_E1_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CER_E0_MASK (0x00000001u) +#define EDMA3_CCRL_CER_E0_SHIFT (0x00000000u) +#define EDMA3_CCRL_CER_E0_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CER_RESETVAL (0x00000000u) + +/* CERH */ + +#define EDMA3_CCRL_CERH_E63_MASK (0x80000000u) +#define EDMA3_CCRL_CERH_E63_SHIFT (0x0000001Fu) +#define EDMA3_CCRL_CERH_E63_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CERH_E62_MASK (0x40000000u) +#define EDMA3_CCRL_CERH_E62_SHIFT (0x0000001Eu) +#define EDMA3_CCRL_CERH_E62_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CERH_E61_MASK (0x20000000u) +#define EDMA3_CCRL_CERH_E61_SHIFT (0x0000001Du) +#define EDMA3_CCRL_CERH_E61_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CERH_E60_MASK (0x10000000u) +#define EDMA3_CCRL_CERH_E60_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_CERH_E60_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CERH_E59_MASK (0x08000000u) +#define EDMA3_CCRL_CERH_E59_SHIFT (0x0000001Bu) +#define EDMA3_CCRL_CERH_E59_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CERH_E58_MASK (0x04000000u) +#define EDMA3_CCRL_CERH_E58_SHIFT (0x0000001Au) +#define EDMA3_CCRL_CERH_E58_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CERH_E57_MASK (0x02000000u) +#define EDMA3_CCRL_CERH_E57_SHIFT (0x00000019u) +#define EDMA3_CCRL_CERH_E57_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CERH_E56_MASK (0x01000000u) +#define EDMA3_CCRL_CERH_E56_SHIFT (0x00000018u) +#define EDMA3_CCRL_CERH_E56_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CERH_E55_MASK (0x00800000u) +#define EDMA3_CCRL_CERH_E55_SHIFT (0x00000017u) +#define EDMA3_CCRL_CERH_E55_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CERH_E54_MASK (0x00400000u) +#define EDMA3_CCRL_CERH_E54_SHIFT (0x00000016u) +#define EDMA3_CCRL_CERH_E54_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CERH_E53_MASK (0x00200000u) +#define EDMA3_CCRL_CERH_E53_SHIFT (0x00000015u) +#define EDMA3_CCRL_CERH_E53_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CERH_E52_MASK (0x00100000u) +#define EDMA3_CCRL_CERH_E52_SHIFT (0x00000014u) +#define EDMA3_CCRL_CERH_E52_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CERH_E51_MASK (0x00080000u) +#define EDMA3_CCRL_CERH_E51_SHIFT (0x00000013u) +#define EDMA3_CCRL_CERH_E51_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CERH_E50_MASK (0x00040000u) +#define EDMA3_CCRL_CERH_E50_SHIFT (0x00000012u) +#define EDMA3_CCRL_CERH_E50_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CERH_E49_MASK (0x00020000u) +#define EDMA3_CCRL_CERH_E49_SHIFT (0x00000011u) +#define EDMA3_CCRL_CERH_E49_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CERH_E48_MASK (0x00010000u) +#define EDMA3_CCRL_CERH_E48_SHIFT (0x00000010u) +#define EDMA3_CCRL_CERH_E48_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CERH_E47_MASK (0x00008000u) +#define EDMA3_CCRL_CERH_E47_SHIFT (0x0000000Fu) +#define EDMA3_CCRL_CERH_E47_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CERH_E46_MASK (0x00004000u) +#define EDMA3_CCRL_CERH_E46_SHIFT (0x0000000Eu) +#define EDMA3_CCRL_CERH_E46_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CERH_E45_MASK (0x00002000u) +#define EDMA3_CCRL_CERH_E45_SHIFT (0x0000000Du) +#define EDMA3_CCRL_CERH_E45_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CERH_E44_MASK (0x00001000u) +#define EDMA3_CCRL_CERH_E44_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_CERH_E44_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CERH_E43_MASK (0x00000800u) +#define EDMA3_CCRL_CERH_E43_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_CERH_E43_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CERH_E42_MASK (0x00000400u) +#define EDMA3_CCRL_CERH_E42_SHIFT (0x0000000Au) +#define EDMA3_CCRL_CERH_E42_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CERH_E41_MASK (0x00000200u) +#define EDMA3_CCRL_CERH_E41_SHIFT (0x00000009u) +#define EDMA3_CCRL_CERH_E41_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CERH_E40_MASK (0x00000100u) +#define EDMA3_CCRL_CERH_E40_SHIFT (0x00000008u) +#define EDMA3_CCRL_CERH_E40_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CERH_E39_MASK (0x00000080u) +#define EDMA3_CCRL_CERH_E39_SHIFT (0x00000007u) +#define EDMA3_CCRL_CERH_E39_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CERH_E38_MASK (0x00000040u) +#define EDMA3_CCRL_CERH_E38_SHIFT (0x00000006u) +#define EDMA3_CCRL_CERH_E38_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CERH_E37_MASK (0x00000020u) +#define EDMA3_CCRL_CERH_E37_SHIFT (0x00000005u) +#define EDMA3_CCRL_CERH_E37_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CERH_E36_MASK (0x00000010u) +#define EDMA3_CCRL_CERH_E36_SHIFT (0x00000004u) +#define EDMA3_CCRL_CERH_E36_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CERH_E35_MASK (0x00000008u) +#define EDMA3_CCRL_CERH_E35_SHIFT (0x00000003u) +#define EDMA3_CCRL_CERH_E35_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CERH_E34_MASK (0x00000004u) +#define EDMA3_CCRL_CERH_E34_SHIFT (0x00000002u) +#define EDMA3_CCRL_CERH_E34_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CERH_E33_MASK (0x00000002u) +#define EDMA3_CCRL_CERH_E33_SHIFT (0x00000001u) +#define EDMA3_CCRL_CERH_E33_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CERH_E32_MASK (0x00000001u) +#define EDMA3_CCRL_CERH_E32_SHIFT (0x00000000u) +#define EDMA3_CCRL_CERH_E32_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CERH_RESETVAL (0x00000000u) + +/* EER */ + +#define EDMA3_CCRL_EER_E31_MASK (0x80000000u) +#define EDMA3_CCRL_EER_E31_SHIFT (0x0000001Fu) +#define EDMA3_CCRL_EER_E31_RESETVAL (0x00000000u) + +/*----E31 Tokens----*/ +#define EDMA3_CCRL_EER_E31_ (0x00000001u) + +#define EDMA3_CCRL_EER_E30_MASK (0x40000000u) +#define EDMA3_CCRL_EER_E30_SHIFT (0x0000001Eu) +#define EDMA3_CCRL_EER_E30_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EER_E29_MASK (0x20000000u) +#define EDMA3_CCRL_EER_E29_SHIFT (0x0000001Du) +#define EDMA3_CCRL_EER_E29_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EER_E28_MASK (0x10000000u) +#define EDMA3_CCRL_EER_E28_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_EER_E28_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EER_E27_MASK (0x08000000u) +#define EDMA3_CCRL_EER_E27_SHIFT (0x0000001Bu) +#define EDMA3_CCRL_EER_E27_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EER_E26_MASK (0x04000000u) +#define EDMA3_CCRL_EER_E26_SHIFT (0x0000001Au) +#define EDMA3_CCRL_EER_E26_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EER_E25_MASK (0x02000000u) +#define EDMA3_CCRL_EER_E25_SHIFT (0x00000019u) +#define EDMA3_CCRL_EER_E25_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EER_E24_MASK (0x01000000u) +#define EDMA3_CCRL_EER_E24_SHIFT (0x00000018u) +#define EDMA3_CCRL_EER_E24_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EER_E23_MASK (0x00800000u) +#define EDMA3_CCRL_EER_E23_SHIFT (0x00000017u) +#define EDMA3_CCRL_EER_E23_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EER_E22_MASK (0x00400000u) +#define EDMA3_CCRL_EER_E22_SHIFT (0x00000016u) +#define EDMA3_CCRL_EER_E22_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EER_E21_MASK (0x00200000u) +#define EDMA3_CCRL_EER_E21_SHIFT (0x00000015u) +#define EDMA3_CCRL_EER_E21_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EER_E20_MASK (0x00100000u) +#define EDMA3_CCRL_EER_E20_SHIFT (0x00000014u) +#define EDMA3_CCRL_EER_E20_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EER_E19_MASK (0x00080000u) +#define EDMA3_CCRL_EER_E19_SHIFT (0x00000013u) +#define EDMA3_CCRL_EER_E19_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EER_E18_MASK (0x00040000u) +#define EDMA3_CCRL_EER_E18_SHIFT (0x00000012u) +#define EDMA3_CCRL_EER_E18_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EER_E17_MASK (0x00020000u) +#define EDMA3_CCRL_EER_E17_SHIFT (0x00000011u) +#define EDMA3_CCRL_EER_E17_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EER_E16_MASK (0x00010000u) +#define EDMA3_CCRL_EER_E16_SHIFT (0x00000010u) +#define EDMA3_CCRL_EER_E16_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EER_E15_MASK (0x00008000u) +#define EDMA3_CCRL_EER_E15_SHIFT (0x0000000Fu) +#define EDMA3_CCRL_EER_E15_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EER_E14_MASK (0x00004000u) +#define EDMA3_CCRL_EER_E14_SHIFT (0x0000000Eu) +#define EDMA3_CCRL_EER_E14_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EER_E13_MASK (0x00002000u) +#define EDMA3_CCRL_EER_E13_SHIFT (0x0000000Du) +#define EDMA3_CCRL_EER_E13_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EER_E12_MASK (0x00001000u) +#define EDMA3_CCRL_EER_E12_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_EER_E12_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EER_E11_MASK (0x00000800u) +#define EDMA3_CCRL_EER_E11_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_EER_E11_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EER_E10_MASK (0x00000400u) +#define EDMA3_CCRL_EER_E10_SHIFT (0x0000000Au) +#define EDMA3_CCRL_EER_E10_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EER_E9_MASK (0x00000200u) +#define EDMA3_CCRL_EER_E9_SHIFT (0x00000009u) +#define EDMA3_CCRL_EER_E9_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EER_E8_MASK (0x00000100u) +#define EDMA3_CCRL_EER_E8_SHIFT (0x00000008u) +#define EDMA3_CCRL_EER_E8_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EER_E7_MASK (0x00000080u) +#define EDMA3_CCRL_EER_E7_SHIFT (0x00000007u) +#define EDMA3_CCRL_EER_E7_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EER_E6_MASK (0x00000040u) +#define EDMA3_CCRL_EER_E6_SHIFT (0x00000006u) +#define EDMA3_CCRL_EER_E6_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EER_E5_MASK (0x00000020u) +#define EDMA3_CCRL_EER_E5_SHIFT (0x00000005u) +#define EDMA3_CCRL_EER_E5_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EER_E4_MASK (0x00000010u) +#define EDMA3_CCRL_EER_E4_SHIFT (0x00000004u) +#define EDMA3_CCRL_EER_E4_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EER_E3_MASK (0x00000008u) +#define EDMA3_CCRL_EER_E3_SHIFT (0x00000003u) +#define EDMA3_CCRL_EER_E3_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EER_E2_MASK (0x00000004u) +#define EDMA3_CCRL_EER_E2_SHIFT (0x00000002u) +#define EDMA3_CCRL_EER_E2_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EER_E1_MASK (0x00000002u) +#define EDMA3_CCRL_EER_E1_SHIFT (0x00000001u) +#define EDMA3_CCRL_EER_E1_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EER_E0_MASK (0x00000001u) +#define EDMA3_CCRL_EER_E0_SHIFT (0x00000000u) +#define EDMA3_CCRL_EER_E0_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EER_RESETVAL (0x00000000u) + +/* EERH */ + +#define EDMA3_CCRL_EERH_E63_MASK (0x80000000u) +#define EDMA3_CCRL_EERH_E63_SHIFT (0x0000001Fu) +#define EDMA3_CCRL_EERH_E63_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EERH_E62_MASK (0x40000000u) +#define EDMA3_CCRL_EERH_E62_SHIFT (0x0000001Eu) +#define EDMA3_CCRL_EERH_E62_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EERH_E61_MASK (0x20000000u) +#define EDMA3_CCRL_EERH_E61_SHIFT (0x0000001Du) +#define EDMA3_CCRL_EERH_E61_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EERH_E60_MASK (0x10000000u) +#define EDMA3_CCRL_EERH_E60_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_EERH_E60_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EERH_E59_MASK (0x08000000u) +#define EDMA3_CCRL_EERH_E59_SHIFT (0x0000001Bu) +#define EDMA3_CCRL_EERH_E59_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EERH_E58_MASK (0x04000000u) +#define EDMA3_CCRL_EERH_E58_SHIFT (0x0000001Au) +#define EDMA3_CCRL_EERH_E58_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EERH_E57_MASK (0x02000000u) +#define EDMA3_CCRL_EERH_E57_SHIFT (0x00000019u) +#define EDMA3_CCRL_EERH_E57_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EERH_E56_MASK (0x01000000u) +#define EDMA3_CCRL_EERH_E56_SHIFT (0x00000018u) +#define EDMA3_CCRL_EERH_E56_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EERH_E55_MASK (0x00800000u) +#define EDMA3_CCRL_EERH_E55_SHIFT (0x00000017u) +#define EDMA3_CCRL_EERH_E55_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EERH_E54_MASK (0x00400000u) +#define EDMA3_CCRL_EERH_E54_SHIFT (0x00000016u) +#define EDMA3_CCRL_EERH_E54_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EERH_E53_MASK (0x00200000u) +#define EDMA3_CCRL_EERH_E53_SHIFT (0x00000015u) +#define EDMA3_CCRL_EERH_E53_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EERH_E52_MASK (0x00100000u) +#define EDMA3_CCRL_EERH_E52_SHIFT (0x00000014u) +#define EDMA3_CCRL_EERH_E52_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EERH_E51_MASK (0x00080000u) +#define EDMA3_CCRL_EERH_E51_SHIFT (0x00000013u) +#define EDMA3_CCRL_EERH_E51_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EERH_E50_MASK (0x00040000u) +#define EDMA3_CCRL_EERH_E50_SHIFT (0x00000012u) +#define EDMA3_CCRL_EERH_E50_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EERH_E49_MASK (0x00020000u) +#define EDMA3_CCRL_EERH_E49_SHIFT (0x00000011u) +#define EDMA3_CCRL_EERH_E49_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EERH_E48_MASK (0x00010000u) +#define EDMA3_CCRL_EERH_E48_SHIFT (0x00000010u) +#define EDMA3_CCRL_EERH_E48_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EERH_E47_MASK (0x00008000u) +#define EDMA3_CCRL_EERH_E47_SHIFT (0x0000000Fu) +#define EDMA3_CCRL_EERH_E47_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EERH_E46_MASK (0x00004000u) +#define EDMA3_CCRL_EERH_E46_SHIFT (0x0000000Eu) +#define EDMA3_CCRL_EERH_E46_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EERH_E45_MASK (0x00002000u) +#define EDMA3_CCRL_EERH_E45_SHIFT (0x0000000Du) +#define EDMA3_CCRL_EERH_E45_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EERH_E44_MASK (0x00001000u) +#define EDMA3_CCRL_EERH_E44_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_EERH_E44_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EERH_E43_MASK (0x00000800u) +#define EDMA3_CCRL_EERH_E43_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_EERH_E43_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EERH_E42_MASK (0x00000400u) +#define EDMA3_CCRL_EERH_E42_SHIFT (0x0000000Au) +#define EDMA3_CCRL_EERH_E42_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EERH_E41_MASK (0x00000200u) +#define EDMA3_CCRL_EERH_E41_SHIFT (0x00000009u) +#define EDMA3_CCRL_EERH_E41_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EERH_E40_MASK (0x00000100u) +#define EDMA3_CCRL_EERH_E40_SHIFT (0x00000008u) +#define EDMA3_CCRL_EERH_E40_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EERH_E39_MASK (0x00000080u) +#define EDMA3_CCRL_EERH_E39_SHIFT (0x00000007u) +#define EDMA3_CCRL_EERH_E39_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EERH_E38_MASK (0x00000040u) +#define EDMA3_CCRL_EERH_E38_SHIFT (0x00000006u) +#define EDMA3_CCRL_EERH_E38_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EERH_E37_MASK (0x00000020u) +#define EDMA3_CCRL_EERH_E37_SHIFT (0x00000005u) +#define EDMA3_CCRL_EERH_E37_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EERH_E36_MASK (0x00000010u) +#define EDMA3_CCRL_EERH_E36_SHIFT (0x00000004u) +#define EDMA3_CCRL_EERH_E36_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EERH_E35_MASK (0x00000008u) +#define EDMA3_CCRL_EERH_E35_SHIFT (0x00000003u) +#define EDMA3_CCRL_EERH_E35_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EERH_E34_MASK (0x00000004u) +#define EDMA3_CCRL_EERH_E34_SHIFT (0x00000002u) +#define EDMA3_CCRL_EERH_E34_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EERH_E33_MASK (0x00000002u) +#define EDMA3_CCRL_EERH_E33_SHIFT (0x00000001u) +#define EDMA3_CCRL_EERH_E33_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EERH_E32_MASK (0x00000001u) +#define EDMA3_CCRL_EERH_E32_SHIFT (0x00000000u) +#define EDMA3_CCRL_EERH_E32_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EERH_RESETVAL (0x00000000u) + +/* EECR */ + +#define EDMA3_CCRL_EECR_E31_MASK (0x80000000u) +#define EDMA3_CCRL_EECR_E31_SHIFT (0x0000001Fu) +#define EDMA3_CCRL_EECR_E31_RESETVAL (0x00000000u) + +/*----E31 Tokens----*/ +#define EDMA3_CCRL_EECR_E31_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECR_E30_MASK (0x40000000u) +#define EDMA3_CCRL_EECR_E30_SHIFT (0x0000001Eu) +#define EDMA3_CCRL_EECR_E30_RESETVAL (0x00000000u) + +/*----E30 Tokens----*/ +#define EDMA3_CCRL_EECR_E30_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECR_E29_MASK (0x20000000u) +#define EDMA3_CCRL_EECR_E29_SHIFT (0x0000001Du) +#define EDMA3_CCRL_EECR_E29_RESETVAL (0x00000000u) + +/*----E29 Tokens----*/ +#define EDMA3_CCRL_EECR_E29_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECR_E28_MASK (0x10000000u) +#define EDMA3_CCRL_EECR_E28_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_EECR_E28_RESETVAL (0x00000000u) + +/*----E28 Tokens----*/ +#define EDMA3_CCRL_EECR_E28_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECR_E27_MASK (0x08000000u) +#define EDMA3_CCRL_EECR_E27_SHIFT (0x0000001Bu) +#define EDMA3_CCRL_EECR_E27_RESETVAL (0x00000000u) + +/*----E27 Tokens----*/ +#define EDMA3_CCRL_EECR_E27_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECR_E26_MASK (0x04000000u) +#define EDMA3_CCRL_EECR_E26_SHIFT (0x0000001Au) +#define EDMA3_CCRL_EECR_E26_RESETVAL (0x00000000u) + +/*----E26 Tokens----*/ +#define EDMA3_CCRL_EECR_E26_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECR_E25_MASK (0x02000000u) +#define EDMA3_CCRL_EECR_E25_SHIFT (0x00000019u) +#define EDMA3_CCRL_EECR_E25_RESETVAL (0x00000000u) + +/*----E25 Tokens----*/ +#define EDMA3_CCRL_EECR_E25_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECR_E24_MASK (0x01000000u) +#define EDMA3_CCRL_EECR_E24_SHIFT (0x00000018u) +#define EDMA3_CCRL_EECR_E24_RESETVAL (0x00000000u) + +/*----E24 Tokens----*/ +#define EDMA3_CCRL_EECR_E24_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECR_E23_MASK (0x00800000u) +#define EDMA3_CCRL_EECR_E23_SHIFT (0x00000017u) +#define EDMA3_CCRL_EECR_E23_RESETVAL (0x00000000u) + +/*----E23 Tokens----*/ +#define EDMA3_CCRL_EECR_E23_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECR_E22_MASK (0x00400000u) +#define EDMA3_CCRL_EECR_E22_SHIFT (0x00000016u) +#define EDMA3_CCRL_EECR_E22_RESETVAL (0x00000000u) + +/*----E22 Tokens----*/ +#define EDMA3_CCRL_EECR_E22_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECR_E21_MASK (0x00200000u) +#define EDMA3_CCRL_EECR_E21_SHIFT (0x00000015u) +#define EDMA3_CCRL_EECR_E21_RESETVAL (0x00000000u) + +/*----E21 Tokens----*/ +#define EDMA3_CCRL_EECR_E21_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECR_E20_MASK (0x00100000u) +#define EDMA3_CCRL_EECR_E20_SHIFT (0x00000014u) +#define EDMA3_CCRL_EECR_E20_RESETVAL (0x00000000u) + +/*----E20 Tokens----*/ +#define EDMA3_CCRL_EECR_E20_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECR_E19_MASK (0x00080000u) +#define EDMA3_CCRL_EECR_E19_SHIFT (0x00000013u) +#define EDMA3_CCRL_EECR_E19_RESETVAL (0x00000000u) + +/*----E19 Tokens----*/ +#define EDMA3_CCRL_EECR_E19_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECR_E18_MASK (0x00040000u) +#define EDMA3_CCRL_EECR_E18_SHIFT (0x00000012u) +#define EDMA3_CCRL_EECR_E18_RESETVAL (0x00000000u) + +/*----E18 Tokens----*/ +#define EDMA3_CCRL_EECR_E18_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECR_E17_MASK (0x00020000u) +#define EDMA3_CCRL_EECR_E17_SHIFT (0x00000011u) +#define EDMA3_CCRL_EECR_E17_RESETVAL (0x00000000u) + +/*----E17 Tokens----*/ +#define EDMA3_CCRL_EECR_E17_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECR_E16_MASK (0x00010000u) +#define EDMA3_CCRL_EECR_E16_SHIFT (0x00000010u) +#define EDMA3_CCRL_EECR_E16_RESETVAL (0x00000000u) + +/*----E16 Tokens----*/ +#define EDMA3_CCRL_EECR_E16_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECR_E15_MASK (0x00008000u) +#define EDMA3_CCRL_EECR_E15_SHIFT (0x0000000Fu) +#define EDMA3_CCRL_EECR_E15_RESETVAL (0x00000000u) + +/*----E15 Tokens----*/ +#define EDMA3_CCRL_EECR_E15_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECR_E14_MASK (0x00004000u) +#define EDMA3_CCRL_EECR_E14_SHIFT (0x0000000Eu) +#define EDMA3_CCRL_EECR_E14_RESETVAL (0x00000000u) + +/*----E14 Tokens----*/ +#define EDMA3_CCRL_EECR_E14_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECR_E13_MASK (0x00002000u) +#define EDMA3_CCRL_EECR_E13_SHIFT (0x0000000Du) +#define EDMA3_CCRL_EECR_E13_RESETVAL (0x00000000u) + +/*----E13 Tokens----*/ +#define EDMA3_CCRL_EECR_E13_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECR_E12_MASK (0x00001000u) +#define EDMA3_CCRL_EECR_E12_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_EECR_E12_RESETVAL (0x00000000u) + +/*----E12 Tokens----*/ +#define EDMA3_CCRL_EECR_E12_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECR_E11_MASK (0x00000800u) +#define EDMA3_CCRL_EECR_E11_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_EECR_E11_RESETVAL (0x00000000u) + +/*----E11 Tokens----*/ +#define EDMA3_CCRL_EECR_E11_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECR_E10_MASK (0x00000400u) +#define EDMA3_CCRL_EECR_E10_SHIFT (0x0000000Au) +#define EDMA3_CCRL_EECR_E10_RESETVAL (0x00000000u) + +/*----E10 Tokens----*/ +#define EDMA3_CCRL_EECR_E10_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECR_E9_MASK (0x00000200u) +#define EDMA3_CCRL_EECR_E9_SHIFT (0x00000009u) +#define EDMA3_CCRL_EECR_E9_RESETVAL (0x00000000u) + +/*----E9 Tokens----*/ +#define EDMA3_CCRL_EECR_E9_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECR_E8_MASK (0x00000100u) +#define EDMA3_CCRL_EECR_E8_SHIFT (0x00000008u) +#define EDMA3_CCRL_EECR_E8_RESETVAL (0x00000000u) + +/*----E8 Tokens----*/ +#define EDMA3_CCRL_EECR_E8_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECR_E7_MASK (0x00000080u) +#define EDMA3_CCRL_EECR_E7_SHIFT (0x00000007u) +#define EDMA3_CCRL_EECR_E7_RESETVAL (0x00000000u) + +/*----E7 Tokens----*/ +#define EDMA3_CCRL_EECR_E7_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECR_E6_MASK (0x00000040u) +#define EDMA3_CCRL_EECR_E6_SHIFT (0x00000006u) +#define EDMA3_CCRL_EECR_E6_RESETVAL (0x00000000u) + +/*----E6 Tokens----*/ +#define EDMA3_CCRL_EECR_E6_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECR_E5_MASK (0x00000020u) +#define EDMA3_CCRL_EECR_E5_SHIFT (0x00000005u) +#define EDMA3_CCRL_EECR_E5_RESETVAL (0x00000000u) + +/*----E5 Tokens----*/ +#define EDMA3_CCRL_EECR_E5_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECR_E4_MASK (0x00000010u) +#define EDMA3_CCRL_EECR_E4_SHIFT (0x00000004u) +#define EDMA3_CCRL_EECR_E4_RESETVAL (0x00000000u) + +/*----E4 Tokens----*/ +#define EDMA3_CCRL_EECR_E4_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECR_E3_MASK (0x00000008u) +#define EDMA3_CCRL_EECR_E3_SHIFT (0x00000003u) +#define EDMA3_CCRL_EECR_E3_RESETVAL (0x00000000u) + +/*----E3 Tokens----*/ +#define EDMA3_CCRL_EECR_E3_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECR_E2_MASK (0x00000004u) +#define EDMA3_CCRL_EECR_E2_SHIFT (0x00000002u) +#define EDMA3_CCRL_EECR_E2_RESETVAL (0x00000000u) + +/*----E2 Tokens----*/ +#define EDMA3_CCRL_EECR_E2_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECR_E1_MASK (0x00000002u) +#define EDMA3_CCRL_EECR_E1_SHIFT (0x00000001u) +#define EDMA3_CCRL_EECR_E1_RESETVAL (0x00000000u) + +/*----E1 Tokens----*/ +#define EDMA3_CCRL_EECR_E1_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECR_E0_MASK (0x00000001u) +#define EDMA3_CCRL_EECR_E0_SHIFT (0x00000000u) +#define EDMA3_CCRL_EECR_E0_RESETVAL (0x00000000u) + +/*----E0 Tokens----*/ +#define EDMA3_CCRL_EECR_E0_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECR_RESETVAL (0x00000000u) + +/* EECRH */ + +#define EDMA3_CCRL_EECRH_E63_MASK (0x80000000u) +#define EDMA3_CCRL_EECRH_E63_SHIFT (0x0000001Fu) +#define EDMA3_CCRL_EECRH_E63_RESETVAL (0x00000000u) + +/*----E63 Tokens----*/ +#define EDMA3_CCRL_EECRH_E63_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECRH_E62_MASK (0x40000000u) +#define EDMA3_CCRL_EECRH_E62_SHIFT (0x0000001Eu) +#define EDMA3_CCRL_EECRH_E62_RESETVAL (0x00000000u) + +/*----E62 Tokens----*/ +#define EDMA3_CCRL_EECRH_E62_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECRH_E61_MASK (0x20000000u) +#define EDMA3_CCRL_EECRH_E61_SHIFT (0x0000001Du) +#define EDMA3_CCRL_EECRH_E61_RESETVAL (0x00000000u) + +/*----E61 Tokens----*/ +#define EDMA3_CCRL_EECRH_E61_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECRH_E60_MASK (0x10000000u) +#define EDMA3_CCRL_EECRH_E60_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_EECRH_E60_RESETVAL (0x00000000u) + +/*----E60 Tokens----*/ +#define EDMA3_CCRL_EECRH_E60_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECRH_E59_MASK (0x08000000u) +#define EDMA3_CCRL_EECRH_E59_SHIFT (0x0000001Bu) +#define EDMA3_CCRL_EECRH_E59_RESETVAL (0x00000000u) + +/*----E59 Tokens----*/ +#define EDMA3_CCRL_EECRH_E59_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECRH_E58_MASK (0x04000000u) +#define EDMA3_CCRL_EECRH_E58_SHIFT (0x0000001Au) +#define EDMA3_CCRL_EECRH_E58_RESETVAL (0x00000000u) + +/*----E58 Tokens----*/ +#define EDMA3_CCRL_EECRH_E58_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECRH_E57_MASK (0x02000000u) +#define EDMA3_CCRL_EECRH_E57_SHIFT (0x00000019u) +#define EDMA3_CCRL_EECRH_E57_RESETVAL (0x00000000u) + +/*----E57 Tokens----*/ +#define EDMA3_CCRL_EECRH_E57_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECRH_E56_MASK (0x01000000u) +#define EDMA3_CCRL_EECRH_E56_SHIFT (0x00000018u) +#define EDMA3_CCRL_EECRH_E56_RESETVAL (0x00000000u) + +/*----E56 Tokens----*/ +#define EDMA3_CCRL_EECRH_E56_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECRH_E55_MASK (0x00800000u) +#define EDMA3_CCRL_EECRH_E55_SHIFT (0x00000017u) +#define EDMA3_CCRL_EECRH_E55_RESETVAL (0x00000000u) + +/*----E55 Tokens----*/ +#define EDMA3_CCRL_EECRH_E55_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECRH_E54_MASK (0x00400000u) +#define EDMA3_CCRL_EECRH_E54_SHIFT (0x00000016u) +#define EDMA3_CCRL_EECRH_E54_RESETVAL (0x00000000u) + +/*----E54 Tokens----*/ +#define EDMA3_CCRL_EECRH_E54_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECRH_E53_MASK (0x00200000u) +#define EDMA3_CCRL_EECRH_E53_SHIFT (0x00000015u) +#define EDMA3_CCRL_EECRH_E53_RESETVAL (0x00000000u) + +/*----E53 Tokens----*/ +#define EDMA3_CCRL_EECRH_E53_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECRH_E52_MASK (0x00100000u) +#define EDMA3_CCRL_EECRH_E52_SHIFT (0x00000014u) +#define EDMA3_CCRL_EECRH_E52_RESETVAL (0x00000000u) + +/*----E52 Tokens----*/ +#define EDMA3_CCRL_EECRH_E52_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECRH_E51_MASK (0x00080000u) +#define EDMA3_CCRL_EECRH_E51_SHIFT (0x00000013u) +#define EDMA3_CCRL_EECRH_E51_RESETVAL (0x00000000u) + +/*----E51 Tokens----*/ +#define EDMA3_CCRL_EECRH_E51_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECRH_E50_MASK (0x00040000u) +#define EDMA3_CCRL_EECRH_E50_SHIFT (0x00000012u) +#define EDMA3_CCRL_EECRH_E50_RESETVAL (0x00000000u) + +/*----E50 Tokens----*/ +#define EDMA3_CCRL_EECRH_E50_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECRH_E49_MASK (0x00020000u) +#define EDMA3_CCRL_EECRH_E49_SHIFT (0x00000011u) +#define EDMA3_CCRL_EECRH_E49_RESETVAL (0x00000000u) + +/*----E49 Tokens----*/ +#define EDMA3_CCRL_EECRH_E49_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECRH_E48_MASK (0x00010000u) +#define EDMA3_CCRL_EECRH_E48_SHIFT (0x00000010u) +#define EDMA3_CCRL_EECRH_E48_RESETVAL (0x00000000u) + +/*----E48 Tokens----*/ +#define EDMA3_CCRL_EECRH_E48_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECRH_E47_MASK (0x00008000u) +#define EDMA3_CCRL_EECRH_E47_SHIFT (0x0000000Fu) +#define EDMA3_CCRL_EECRH_E47_RESETVAL (0x00000000u) + +/*----E47 Tokens----*/ +#define EDMA3_CCRL_EECRH_E47_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECRH_E46_MASK (0x00004000u) +#define EDMA3_CCRL_EECRH_E46_SHIFT (0x0000000Eu) +#define EDMA3_CCRL_EECRH_E46_RESETVAL (0x00000000u) + +/*----E46 Tokens----*/ +#define EDMA3_CCRL_EECRH_E46_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECRH_E45_MASK (0x00002000u) +#define EDMA3_CCRL_EECRH_E45_SHIFT (0x0000000Du) +#define EDMA3_CCRL_EECRH_E45_RESETVAL (0x00000000u) + +/*----E45 Tokens----*/ +#define EDMA3_CCRL_EECRH_E45_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECRH_E44_MASK (0x00001000u) +#define EDMA3_CCRL_EECRH_E44_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_EECRH_E44_RESETVAL (0x00000000u) + +/*----E44 Tokens----*/ +#define EDMA3_CCRL_EECRH_E44_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECRH_E43_MASK (0x00000800u) +#define EDMA3_CCRL_EECRH_E43_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_EECRH_E43_RESETVAL (0x00000000u) + +/*----E43 Tokens----*/ +#define EDMA3_CCRL_EECRH_E43_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECRH_E42_MASK (0x00000400u) +#define EDMA3_CCRL_EECRH_E42_SHIFT (0x0000000Au) +#define EDMA3_CCRL_EECRH_E42_RESETVAL (0x00000000u) + +/*----E42 Tokens----*/ +#define EDMA3_CCRL_EECRH_E42_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECRH_E41_MASK (0x00000200u) +#define EDMA3_CCRL_EECRH_E41_SHIFT (0x00000009u) +#define EDMA3_CCRL_EECRH_E41_RESETVAL (0x00000000u) + +/*----E41 Tokens----*/ +#define EDMA3_CCRL_EECRH_E41_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECRH_E40_MASK (0x00000100u) +#define EDMA3_CCRL_EECRH_E40_SHIFT (0x00000008u) +#define EDMA3_CCRL_EECRH_E40_RESETVAL (0x00000000u) + +/*----E40 Tokens----*/ +#define EDMA3_CCRL_EECRH_E40_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECRH_E39_MASK (0x00000080u) +#define EDMA3_CCRL_EECRH_E39_SHIFT (0x00000007u) +#define EDMA3_CCRL_EECRH_E39_RESETVAL (0x00000000u) + +/*----E39 Tokens----*/ +#define EDMA3_CCRL_EECRH_E39_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECRH_E38_MASK (0x00000040u) +#define EDMA3_CCRL_EECRH_E38_SHIFT (0x00000006u) +#define EDMA3_CCRL_EECRH_E38_RESETVAL (0x00000000u) + +/*----E38 Tokens----*/ +#define EDMA3_CCRL_EECRH_E38_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECRH_E37_MASK (0x00000020u) +#define EDMA3_CCRL_EECRH_E37_SHIFT (0x00000005u) +#define EDMA3_CCRL_EECRH_E37_RESETVAL (0x00000000u) + +/*----E37 Tokens----*/ +#define EDMA3_CCRL_EECRH_E37_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECRH_E36_MASK (0x00000010u) +#define EDMA3_CCRL_EECRH_E36_SHIFT (0x00000004u) +#define EDMA3_CCRL_EECRH_E36_RESETVAL (0x00000000u) + +/*----E36 Tokens----*/ +#define EDMA3_CCRL_EECRH_E36_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECRH_E35_MASK (0x00000008u) +#define EDMA3_CCRL_EECRH_E35_SHIFT (0x00000003u) +#define EDMA3_CCRL_EECRH_E35_RESETVAL (0x00000000u) + +/*----E35 Tokens----*/ +#define EDMA3_CCRL_EECRH_E35_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECRH_E34_MASK (0x00000004u) +#define EDMA3_CCRL_EECRH_E34_SHIFT (0x00000002u) +#define EDMA3_CCRL_EECRH_E34_RESETVAL (0x00000000u) + +/*----E34 Tokens----*/ +#define EDMA3_CCRL_EECRH_E34_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECRH_E33_MASK (0x00000002u) +#define EDMA3_CCRL_EECRH_E33_SHIFT (0x00000001u) +#define EDMA3_CCRL_EECRH_E33_RESETVAL (0x00000000u) + +/*----E33 Tokens----*/ +#define EDMA3_CCRL_EECRH_E33_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECRH_E32_MASK (0x00000001u) +#define EDMA3_CCRL_EECRH_E32_SHIFT (0x00000000u) +#define EDMA3_CCRL_EECRH_E32_RESETVAL (0x00000000u) + +/*----E32 Tokens----*/ +#define EDMA3_CCRL_EECRH_E32_CLEAR (0x00000001u) + +#define EDMA3_CCRL_EECRH_RESETVAL (0x00000000u) + +/* EESR */ + +#define EDMA3_CCRL_EESR_E31_MASK (0x80000000u) +#define EDMA3_CCRL_EESR_E31_SHIFT (0x0000001Fu) +#define EDMA3_CCRL_EESR_E31_RESETVAL (0x00000000u) + +/*----E31 Tokens----*/ +#define EDMA3_CCRL_EESR_E31_SET (0x00000001u) + +#define EDMA3_CCRL_EESR_E30_MASK (0x40000000u) +#define EDMA3_CCRL_EESR_E30_SHIFT (0x0000001Eu) +#define EDMA3_CCRL_EESR_E30_RESETVAL (0x00000000u) + +/*----E30 Tokens----*/ +#define EDMA3_CCRL_EESR_E30_SET (0x00000001u) + +#define EDMA3_CCRL_EESR_E29_MASK (0x20000000u) +#define EDMA3_CCRL_EESR_E29_SHIFT (0x0000001Du) +#define EDMA3_CCRL_EESR_E29_RESETVAL (0x00000000u) + +/*----E29 Tokens----*/ +#define EDMA3_CCRL_EESR_E29_SET (0x00000001u) + +#define EDMA3_CCRL_EESR_E28_MASK (0x10000000u) +#define EDMA3_CCRL_EESR_E28_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_EESR_E28_RESETVAL (0x00000000u) + +/*----E28 Tokens----*/ +#define EDMA3_CCRL_EESR_E28_SET (0x00000001u) + +#define EDMA3_CCRL_EESR_E27_MASK (0x08000000u) +#define EDMA3_CCRL_EESR_E27_SHIFT (0x0000001Bu) +#define EDMA3_CCRL_EESR_E27_RESETVAL (0x00000000u) + +/*----E27 Tokens----*/ +#define EDMA3_CCRL_EESR_E27_SET (0x00000001u) + +#define EDMA3_CCRL_EESR_E26_MASK (0x04000000u) +#define EDMA3_CCRL_EESR_E26_SHIFT (0x0000001Au) +#define EDMA3_CCRL_EESR_E26_RESETVAL (0x00000000u) + +/*----E26 Tokens----*/ +#define EDMA3_CCRL_EESR_E26_SET (0x00000001u) + +#define EDMA3_CCRL_EESR_E25_MASK (0x02000000u) +#define EDMA3_CCRL_EESR_E25_SHIFT (0x00000019u) +#define EDMA3_CCRL_EESR_E25_RESETVAL (0x00000000u) + +/*----E25 Tokens----*/ +#define EDMA3_CCRL_EESR_E25_SET (0x00000001u) + +#define EDMA3_CCRL_EESR_E24_MASK (0x01000000u) +#define EDMA3_CCRL_EESR_E24_SHIFT (0x00000018u) +#define EDMA3_CCRL_EESR_E24_RESETVAL (0x00000000u) + +/*----E24 Tokens----*/ +#define EDMA3_CCRL_EESR_E24_SET (0x00000001u) + +#define EDMA3_CCRL_EESR_E23_MASK (0x00800000u) +#define EDMA3_CCRL_EESR_E23_SHIFT (0x00000017u) +#define EDMA3_CCRL_EESR_E23_RESETVAL (0x00000000u) + +/*----E23 Tokens----*/ +#define EDMA3_CCRL_EESR_E23_SET (0x00000001u) + +#define EDMA3_CCRL_EESR_E22_MASK (0x00400000u) +#define EDMA3_CCRL_EESR_E22_SHIFT (0x00000016u) +#define EDMA3_CCRL_EESR_E22_RESETVAL (0x00000000u) + +/*----E22 Tokens----*/ +#define EDMA3_CCRL_EESR_E22_SET (0x00000001u) + +#define EDMA3_CCRL_EESR_E21_MASK (0x00200000u) +#define EDMA3_CCRL_EESR_E21_SHIFT (0x00000015u) +#define EDMA3_CCRL_EESR_E21_RESETVAL (0x00000000u) + +/*----E21 Tokens----*/ +#define EDMA3_CCRL_EESR_E21_SET (0x00000001u) + +#define EDMA3_CCRL_EESR_E20_MASK (0x00100000u) +#define EDMA3_CCRL_EESR_E20_SHIFT (0x00000014u) +#define EDMA3_CCRL_EESR_E20_RESETVAL (0x00000000u) + +/*----E20 Tokens----*/ +#define EDMA3_CCRL_EESR_E20_SET (0x00000001u) + +#define EDMA3_CCRL_EESR_E19_MASK (0x00080000u) +#define EDMA3_CCRL_EESR_E19_SHIFT (0x00000013u) +#define EDMA3_CCRL_EESR_E19_RESETVAL (0x00000000u) + +/*----E19 Tokens----*/ +#define EDMA3_CCRL_EESR_E19_SET (0x00000001u) + +#define EDMA3_CCRL_EESR_E18_MASK (0x00040000u) +#define EDMA3_CCRL_EESR_E18_SHIFT (0x00000012u) +#define EDMA3_CCRL_EESR_E18_RESETVAL (0x00000000u) + +/*----E18 Tokens----*/ +#define EDMA3_CCRL_EESR_E18_SET (0x00000001u) + +#define EDMA3_CCRL_EESR_E17_MASK (0x00020000u) +#define EDMA3_CCRL_EESR_E17_SHIFT (0x00000011u) +#define EDMA3_CCRL_EESR_E17_RESETVAL (0x00000000u) + +/*----E17 Tokens----*/ +#define EDMA3_CCRL_EESR_E17_SET (0x00000001u) + +#define EDMA3_CCRL_EESR_E16_MASK (0x00010000u) +#define EDMA3_CCRL_EESR_E16_SHIFT (0x00000010u) +#define EDMA3_CCRL_EESR_E16_RESETVAL (0x00000000u) + +/*----E16 Tokens----*/ +#define EDMA3_CCRL_EESR_E16_SET (0x00000001u) + +#define EDMA3_CCRL_EESR_E15_MASK (0x00008000u) +#define EDMA3_CCRL_EESR_E15_SHIFT (0x0000000Fu) +#define EDMA3_CCRL_EESR_E15_RESETVAL (0x00000000u) + +/*----E15 Tokens----*/ +#define EDMA3_CCRL_EESR_E15_SET (0x00000001u) + +#define EDMA3_CCRL_EESR_E14_MASK (0x00004000u) +#define EDMA3_CCRL_EESR_E14_SHIFT (0x0000000Eu) +#define EDMA3_CCRL_EESR_E14_RESETVAL (0x00000000u) + +/*----E14 Tokens----*/ +#define EDMA3_CCRL_EESR_E14_SET (0x00000001u) + +#define EDMA3_CCRL_EESR_E13_MASK (0x00002000u) +#define EDMA3_CCRL_EESR_E13_SHIFT (0x0000000Du) +#define EDMA3_CCRL_EESR_E13_RESETVAL (0x00000000u) + +/*----E13 Tokens----*/ +#define EDMA3_CCRL_EESR_E13_SET (0x00000001u) + +#define EDMA3_CCRL_EESR_E12_MASK (0x00001000u) +#define EDMA3_CCRL_EESR_E12_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_EESR_E12_RESETVAL (0x00000000u) + +/*----E12 Tokens----*/ +#define EDMA3_CCRL_EESR_E12_SET (0x00000001u) + +#define EDMA3_CCRL_EESR_E11_MASK (0x00000800u) +#define EDMA3_CCRL_EESR_E11_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_EESR_E11_RESETVAL (0x00000000u) + +/*----E11 Tokens----*/ +#define EDMA3_CCRL_EESR_E11_SET (0x00000001u) + +#define EDMA3_CCRL_EESR_E10_MASK (0x00000400u) +#define EDMA3_CCRL_EESR_E10_SHIFT (0x0000000Au) +#define EDMA3_CCRL_EESR_E10_RESETVAL (0x00000000u) + +/*----E10 Tokens----*/ +#define EDMA3_CCRL_EESR_E10_SET (0x00000001u) + +#define EDMA3_CCRL_EESR_E9_MASK (0x00000200u) +#define EDMA3_CCRL_EESR_E9_SHIFT (0x00000009u) +#define EDMA3_CCRL_EESR_E9_RESETVAL (0x00000000u) + +/*----E9 Tokens----*/ +#define EDMA3_CCRL_EESR_E9_SET (0x00000001u) + +#define EDMA3_CCRL_EESR_E8_MASK (0x00000100u) +#define EDMA3_CCRL_EESR_E8_SHIFT (0x00000008u) +#define EDMA3_CCRL_EESR_E8_RESETVAL (0x00000000u) + +/*----E8 Tokens----*/ +#define EDMA3_CCRL_EESR_E8_SET (0x00000001u) + +#define EDMA3_CCRL_EESR_E7_MASK (0x00000080u) +#define EDMA3_CCRL_EESR_E7_SHIFT (0x00000007u) +#define EDMA3_CCRL_EESR_E7_RESETVAL (0x00000000u) + +/*----E7 Tokens----*/ +#define EDMA3_CCRL_EESR_E7_SET (0x00000001u) + +#define EDMA3_CCRL_EESR_E6_MASK (0x00000040u) +#define EDMA3_CCRL_EESR_E6_SHIFT (0x00000006u) +#define EDMA3_CCRL_EESR_E6_RESETVAL (0x00000000u) + +/*----E6 Tokens----*/ +#define EDMA3_CCRL_EESR_E6_SET (0x00000001u) + +#define EDMA3_CCRL_EESR_E5_MASK (0x00000020u) +#define EDMA3_CCRL_EESR_E5_SHIFT (0x00000005u) +#define EDMA3_CCRL_EESR_E5_RESETVAL (0x00000000u) + +/*----E5 Tokens----*/ +#define EDMA3_CCRL_EESR_E5_SET (0x00000001u) + +#define EDMA3_CCRL_EESR_E4_MASK (0x00000010u) +#define EDMA3_CCRL_EESR_E4_SHIFT (0x00000004u) +#define EDMA3_CCRL_EESR_E4_RESETVAL (0x00000000u) + +/*----E4 Tokens----*/ +#define EDMA3_CCRL_EESR_E4_SET (0x00000001u) + +#define EDMA3_CCRL_EESR_E3_MASK (0x00000008u) +#define EDMA3_CCRL_EESR_E3_SHIFT (0x00000003u) +#define EDMA3_CCRL_EESR_E3_RESETVAL (0x00000000u) + +/*----E3 Tokens----*/ +#define EDMA3_CCRL_EESR_E3_SET (0x00000001u) + +#define EDMA3_CCRL_EESR_E2_MASK (0x00000004u) +#define EDMA3_CCRL_EESR_E2_SHIFT (0x00000002u) +#define EDMA3_CCRL_EESR_E2_RESETVAL (0x00000000u) + +/*----E2 Tokens----*/ +#define EDMA3_CCRL_EESR_E2_SET (0x00000001u) + +#define EDMA3_CCRL_EESR_E1_MASK (0x00000002u) +#define EDMA3_CCRL_EESR_E1_SHIFT (0x00000001u) +#define EDMA3_CCRL_EESR_E1_RESETVAL (0x00000000u) + +/*----E1 Tokens----*/ +#define EDMA3_CCRL_EESR_E1_SET (0x00000001u) + +#define EDMA3_CCRL_EESR_E0_MASK (0x00000001u) +#define EDMA3_CCRL_EESR_E0_SHIFT (0x00000000u) +#define EDMA3_CCRL_EESR_E0_RESETVAL (0x00000000u) + +/*----E0 Tokens----*/ +#define EDMA3_CCRL_EESR_E0_SET (0x00000001u) + +#define EDMA3_CCRL_EESR_RESETVAL (0x00000000u) + +/* EESRH */ + +#define EDMA3_CCRL_EESRH_E63_MASK (0x80000000u) +#define EDMA3_CCRL_EESRH_E63_SHIFT (0x0000001Fu) +#define EDMA3_CCRL_EESRH_E63_RESETVAL (0x00000000u) + +/*----E63 Tokens----*/ +#define EDMA3_CCRL_EESRH_E63_SET (0x00000001u) + +#define EDMA3_CCRL_EESRH_E62_MASK (0x40000000u) +#define EDMA3_CCRL_EESRH_E62_SHIFT (0x0000001Eu) +#define EDMA3_CCRL_EESRH_E62_RESETVAL (0x00000000u) + +/*----E62 Tokens----*/ +#define EDMA3_CCRL_EESRH_E62_SET (0x00000001u) + +#define EDMA3_CCRL_EESRH_E61_MASK (0x20000000u) +#define EDMA3_CCRL_EESRH_E61_SHIFT (0x0000001Du) +#define EDMA3_CCRL_EESRH_E61_RESETVAL (0x00000000u) + +/*----E61 Tokens----*/ +#define EDMA3_CCRL_EESRH_E61_SET (0x00000001u) + +#define EDMA3_CCRL_EESRH_E60_MASK (0x10000000u) +#define EDMA3_CCRL_EESRH_E60_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_EESRH_E60_RESETVAL (0x00000000u) + +/*----E60 Tokens----*/ +#define EDMA3_CCRL_EESRH_E60_SET (0x00000001u) + +#define EDMA3_CCRL_EESRH_E59_MASK (0x08000000u) +#define EDMA3_CCRL_EESRH_E59_SHIFT (0x0000001Bu) +#define EDMA3_CCRL_EESRH_E59_RESETVAL (0x00000000u) + +/*----E59 Tokens----*/ +#define EDMA3_CCRL_EESRH_E59_SET (0x00000001u) + +#define EDMA3_CCRL_EESRH_E58_MASK (0x04000000u) +#define EDMA3_CCRL_EESRH_E58_SHIFT (0x0000001Au) +#define EDMA3_CCRL_EESRH_E58_RESETVAL (0x00000000u) + +/*----E58 Tokens----*/ +#define EDMA3_CCRL_EESRH_E58_SET (0x00000001u) + +#define EDMA3_CCRL_EESRH_E57_MASK (0x02000000u) +#define EDMA3_CCRL_EESRH_E57_SHIFT (0x00000019u) +#define EDMA3_CCRL_EESRH_E57_RESETVAL (0x00000000u) + +/*----E57 Tokens----*/ +#define EDMA3_CCRL_EESRH_E57_SET (0x00000001u) + +#define EDMA3_CCRL_EESRH_E56_MASK (0x01000000u) +#define EDMA3_CCRL_EESRH_E56_SHIFT (0x00000018u) +#define EDMA3_CCRL_EESRH_E56_RESETVAL (0x00000000u) + +/*----E56 Tokens----*/ +#define EDMA3_CCRL_EESRH_E56_SET (0x00000001u) + +#define EDMA3_CCRL_EESRH_E55_MASK (0x00800000u) +#define EDMA3_CCRL_EESRH_E55_SHIFT (0x00000017u) +#define EDMA3_CCRL_EESRH_E55_RESETVAL (0x00000000u) + +/*----E55 Tokens----*/ +#define EDMA3_CCRL_EESRH_E55_SET (0x00000001u) + +#define EDMA3_CCRL_EESRH_E54_MASK (0x00400000u) +#define EDMA3_CCRL_EESRH_E54_SHIFT (0x00000016u) +#define EDMA3_CCRL_EESRH_E54_RESETVAL (0x00000000u) + +/*----E54 Tokens----*/ +#define EDMA3_CCRL_EESRH_E54_SET (0x00000001u) + +#define EDMA3_CCRL_EESRH_E53_MASK (0x00200000u) +#define EDMA3_CCRL_EESRH_E53_SHIFT (0x00000015u) +#define EDMA3_CCRL_EESRH_E53_RESETVAL (0x00000000u) + +/*----E53 Tokens----*/ +#define EDMA3_CCRL_EESRH_E53_SET (0x00000001u) + +#define EDMA3_CCRL_EESRH_E52_MASK (0x00100000u) +#define EDMA3_CCRL_EESRH_E52_SHIFT (0x00000014u) +#define EDMA3_CCRL_EESRH_E52_RESETVAL (0x00000000u) + +/*----E52 Tokens----*/ +#define EDMA3_CCRL_EESRH_E52_SET (0x00000001u) + +#define EDMA3_CCRL_EESRH_E51_MASK (0x00080000u) +#define EDMA3_CCRL_EESRH_E51_SHIFT (0x00000013u) +#define EDMA3_CCRL_EESRH_E51_RESETVAL (0x00000000u) + +/*----E51 Tokens----*/ +#define EDMA3_CCRL_EESRH_E51_SET (0x00000001u) + +#define EDMA3_CCRL_EESRH_E50_MASK (0x00040000u) +#define EDMA3_CCRL_EESRH_E50_SHIFT (0x00000012u) +#define EDMA3_CCRL_EESRH_E50_RESETVAL (0x00000000u) + +/*----E50 Tokens----*/ +#define EDMA3_CCRL_EESRH_E50_SET (0x00000001u) + +#define EDMA3_CCRL_EESRH_E49_MASK (0x00020000u) +#define EDMA3_CCRL_EESRH_E49_SHIFT (0x00000011u) +#define EDMA3_CCRL_EESRH_E49_RESETVAL (0x00000000u) + +/*----E49 Tokens----*/ +#define EDMA3_CCRL_EESRH_E49_SET (0x00000001u) + +#define EDMA3_CCRL_EESRH_E48_MASK (0x00010000u) +#define EDMA3_CCRL_EESRH_E48_SHIFT (0x00000010u) +#define EDMA3_CCRL_EESRH_E48_RESETVAL (0x00000000u) + +/*----E48 Tokens----*/ +#define EDMA3_CCRL_EESRH_E48_SET (0x00000001u) + +#define EDMA3_CCRL_EESRH_E47_MASK (0x00008000u) +#define EDMA3_CCRL_EESRH_E47_SHIFT (0x0000000Fu) +#define EDMA3_CCRL_EESRH_E47_RESETVAL (0x00000000u) + +/*----E47 Tokens----*/ +#define EDMA3_CCRL_EESRH_E47_SET (0x00000001u) + +#define EDMA3_CCRL_EESRH_E46_MASK (0x00004000u) +#define EDMA3_CCRL_EESRH_E46_SHIFT (0x0000000Eu) +#define EDMA3_CCRL_EESRH_E46_RESETVAL (0x00000000u) + +/*----E46 Tokens----*/ +#define EDMA3_CCRL_EESRH_E46_SET (0x00000001u) + +#define EDMA3_CCRL_EESRH_E45_MASK (0x00002000u) +#define EDMA3_CCRL_EESRH_E45_SHIFT (0x0000000Du) +#define EDMA3_CCRL_EESRH_E45_RESETVAL (0x00000000u) + +/*----E45 Tokens----*/ +#define EDMA3_CCRL_EESRH_E45_SET (0x00000001u) + +#define EDMA3_CCRL_EESRH_E44_MASK (0x00001000u) +#define EDMA3_CCRL_EESRH_E44_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_EESRH_E44_RESETVAL (0x00000000u) + +/*----E44 Tokens----*/ +#define EDMA3_CCRL_EESRH_E44_SET (0x00000001u) + +#define EDMA3_CCRL_EESRH_E43_MASK (0x00000800u) +#define EDMA3_CCRL_EESRH_E43_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_EESRH_E43_RESETVAL (0x00000000u) + +/*----E43 Tokens----*/ +#define EDMA3_CCRL_EESRH_E43_SET (0x00000001u) + +#define EDMA3_CCRL_EESRH_E42_MASK (0x00000400u) +#define EDMA3_CCRL_EESRH_E42_SHIFT (0x0000000Au) +#define EDMA3_CCRL_EESRH_E42_RESETVAL (0x00000000u) + +/*----E42 Tokens----*/ +#define EDMA3_CCRL_EESRH_E42_SET (0x00000001u) + +#define EDMA3_CCRL_EESRH_E41_MASK (0x00000200u) +#define EDMA3_CCRL_EESRH_E41_SHIFT (0x00000009u) +#define EDMA3_CCRL_EESRH_E41_RESETVAL (0x00000000u) + +/*----E41 Tokens----*/ +#define EDMA3_CCRL_EESRH_E41_SET (0x00000001u) + +#define EDMA3_CCRL_EESRH_E40_MASK (0x00000100u) +#define EDMA3_CCRL_EESRH_E40_SHIFT (0x00000008u) +#define EDMA3_CCRL_EESRH_E40_RESETVAL (0x00000000u) + +/*----E40 Tokens----*/ +#define EDMA3_CCRL_EESRH_E40_SET (0x00000001u) + +#define EDMA3_CCRL_EESRH_E39_MASK (0x00000080u) +#define EDMA3_CCRL_EESRH_E39_SHIFT (0x00000007u) +#define EDMA3_CCRL_EESRH_E39_RESETVAL (0x00000000u) + +/*----E39 Tokens----*/ +#define EDMA3_CCRL_EESRH_E39_SET (0x00000001u) + +#define EDMA3_CCRL_EESRH_E38_MASK (0x00000040u) +#define EDMA3_CCRL_EESRH_E38_SHIFT (0x00000006u) +#define EDMA3_CCRL_EESRH_E38_RESETVAL (0x00000000u) + +/*----E38 Tokens----*/ +#define EDMA3_CCRL_EESRH_E38_SET (0x00000001u) + +#define EDMA3_CCRL_EESRH_E37_MASK (0x00000020u) +#define EDMA3_CCRL_EESRH_E37_SHIFT (0x00000005u) +#define EDMA3_CCRL_EESRH_E37_RESETVAL (0x00000000u) + +/*----E37 Tokens----*/ +#define EDMA3_CCRL_EESRH_E37_SET (0x00000001u) + +#define EDMA3_CCRL_EESRH_E36_MASK (0x00000010u) +#define EDMA3_CCRL_EESRH_E36_SHIFT (0x00000004u) +#define EDMA3_CCRL_EESRH_E36_RESETVAL (0x00000000u) + +/*----E36 Tokens----*/ +#define EDMA3_CCRL_EESRH_E36_SET (0x00000001u) + +#define EDMA3_CCRL_EESRH_E35_MASK (0x00000008u) +#define EDMA3_CCRL_EESRH_E35_SHIFT (0x00000003u) +#define EDMA3_CCRL_EESRH_E35_RESETVAL (0x00000000u) + +/*----E35 Tokens----*/ +#define EDMA3_CCRL_EESRH_E35_SET (0x00000001u) + +#define EDMA3_CCRL_EESRH_E34_MASK (0x00000004u) +#define EDMA3_CCRL_EESRH_E34_SHIFT (0x00000002u) +#define EDMA3_CCRL_EESRH_E34_RESETVAL (0x00000000u) + +/*----E34 Tokens----*/ +#define EDMA3_CCRL_EESRH_E34_SET (0x00000001u) + +#define EDMA3_CCRL_EESRH_E33_MASK (0x00000002u) +#define EDMA3_CCRL_EESRH_E33_SHIFT (0x00000001u) +#define EDMA3_CCRL_EESRH_E33_RESETVAL (0x00000000u) + +/*----E33 Tokens----*/ +#define EDMA3_CCRL_EESRH_E33_SET (0x00000001u) + +#define EDMA3_CCRL_EESRH_E32_MASK (0x00000001u) +#define EDMA3_CCRL_EESRH_E32_SHIFT (0x00000000u) +#define EDMA3_CCRL_EESRH_E32_RESETVAL (0x00000000u) + +/*----E32 Tokens----*/ +#define EDMA3_CCRL_EESRH_E32_SET (0x00000001u) + +#define EDMA3_CCRL_EESRH_RESETVAL (0x00000000u) + +/* SER */ + +#define EDMA3_CCRL_SER_E31_MASK (0x80000000u) +#define EDMA3_CCRL_SER_E31_SHIFT (0x0000001Fu) +#define EDMA3_CCRL_SER_E31_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SER_E30_MASK (0x40000000u) +#define EDMA3_CCRL_SER_E30_SHIFT (0x0000001Eu) +#define EDMA3_CCRL_SER_E30_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SER_E29_MASK (0x20000000u) +#define EDMA3_CCRL_SER_E29_SHIFT (0x0000001Du) +#define EDMA3_CCRL_SER_E29_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SER_E28_MASK (0x10000000u) +#define EDMA3_CCRL_SER_E28_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_SER_E28_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SER_E27_MASK (0x08000000u) +#define EDMA3_CCRL_SER_E27_SHIFT (0x0000001Bu) +#define EDMA3_CCRL_SER_E27_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SER_E26_MASK (0x04000000u) +#define EDMA3_CCRL_SER_E26_SHIFT (0x0000001Au) +#define EDMA3_CCRL_SER_E26_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SER_E25_MASK (0x02000000u) +#define EDMA3_CCRL_SER_E25_SHIFT (0x00000019u) +#define EDMA3_CCRL_SER_E25_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SER_E24_MASK (0x01000000u) +#define EDMA3_CCRL_SER_E24_SHIFT (0x00000018u) +#define EDMA3_CCRL_SER_E24_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SER_E23_MASK (0x00800000u) +#define EDMA3_CCRL_SER_E23_SHIFT (0x00000017u) +#define EDMA3_CCRL_SER_E23_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SER_E22_MASK (0x00400000u) +#define EDMA3_CCRL_SER_E22_SHIFT (0x00000016u) +#define EDMA3_CCRL_SER_E22_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SER_E21_MASK (0x00200000u) +#define EDMA3_CCRL_SER_E21_SHIFT (0x00000015u) +#define EDMA3_CCRL_SER_E21_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SER_E20_MASK (0x00100000u) +#define EDMA3_CCRL_SER_E20_SHIFT (0x00000014u) +#define EDMA3_CCRL_SER_E20_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SER_E19_MASK (0x00080000u) +#define EDMA3_CCRL_SER_E19_SHIFT (0x00000013u) +#define EDMA3_CCRL_SER_E19_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SER_E18_MASK (0x00040000u) +#define EDMA3_CCRL_SER_E18_SHIFT (0x00000012u) +#define EDMA3_CCRL_SER_E18_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SER_E17_MASK (0x00020000u) +#define EDMA3_CCRL_SER_E17_SHIFT (0x00000011u) +#define EDMA3_CCRL_SER_E17_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SER_E16_MASK (0x00010000u) +#define EDMA3_CCRL_SER_E16_SHIFT (0x00000010u) +#define EDMA3_CCRL_SER_E16_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SER_E15_MASK (0x00008000u) +#define EDMA3_CCRL_SER_E15_SHIFT (0x0000000Fu) +#define EDMA3_CCRL_SER_E15_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SER_E14_MASK (0x00004000u) +#define EDMA3_CCRL_SER_E14_SHIFT (0x0000000Eu) +#define EDMA3_CCRL_SER_E14_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SER_E13_MASK (0x00002000u) +#define EDMA3_CCRL_SER_E13_SHIFT (0x0000000Du) +#define EDMA3_CCRL_SER_E13_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SER_E12_MASK (0x00001000u) +#define EDMA3_CCRL_SER_E12_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_SER_E12_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SER_E11_MASK (0x00000800u) +#define EDMA3_CCRL_SER_E11_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_SER_E11_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SER_E10_MASK (0x00000400u) +#define EDMA3_CCRL_SER_E10_SHIFT (0x0000000Au) +#define EDMA3_CCRL_SER_E10_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SER_E9_MASK (0x00000200u) +#define EDMA3_CCRL_SER_E9_SHIFT (0x00000009u) +#define EDMA3_CCRL_SER_E9_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SER_E8_MASK (0x00000100u) +#define EDMA3_CCRL_SER_E8_SHIFT (0x00000008u) +#define EDMA3_CCRL_SER_E8_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SER_E7_MASK (0x00000080u) +#define EDMA3_CCRL_SER_E7_SHIFT (0x00000007u) +#define EDMA3_CCRL_SER_E7_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SER_E6_MASK (0x00000040u) +#define EDMA3_CCRL_SER_E6_SHIFT (0x00000006u) +#define EDMA3_CCRL_SER_E6_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SER_E5_MASK (0x00000020u) +#define EDMA3_CCRL_SER_E5_SHIFT (0x00000005u) +#define EDMA3_CCRL_SER_E5_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SER_E4_MASK (0x00000010u) +#define EDMA3_CCRL_SER_E4_SHIFT (0x00000004u) +#define EDMA3_CCRL_SER_E4_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SER_E3_MASK (0x00000008u) +#define EDMA3_CCRL_SER_E3_SHIFT (0x00000003u) +#define EDMA3_CCRL_SER_E3_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SER_E2_MASK (0x00000004u) +#define EDMA3_CCRL_SER_E2_SHIFT (0x00000002u) +#define EDMA3_CCRL_SER_E2_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SER_E1_MASK (0x00000002u) +#define EDMA3_CCRL_SER_E1_SHIFT (0x00000001u) +#define EDMA3_CCRL_SER_E1_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SER_E0_MASK (0x00000001u) +#define EDMA3_CCRL_SER_E0_SHIFT (0x00000000u) +#define EDMA3_CCRL_SER_E0_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SER_RESETVAL (0x00000000u) + +/* SERH */ + +#define EDMA3_CCRL_SERH_E63_MASK (0x80000000u) +#define EDMA3_CCRL_SERH_E63_SHIFT (0x0000001Fu) +#define EDMA3_CCRL_SERH_E63_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SERH_E62_MASK (0x40000000u) +#define EDMA3_CCRL_SERH_E62_SHIFT (0x0000001Eu) +#define EDMA3_CCRL_SERH_E62_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SERH_E61_MASK (0x20000000u) +#define EDMA3_CCRL_SERH_E61_SHIFT (0x0000001Du) +#define EDMA3_CCRL_SERH_E61_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SERH_E60_MASK (0x10000000u) +#define EDMA3_CCRL_SERH_E60_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_SERH_E60_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SERH_E59_MASK (0x08000000u) +#define EDMA3_CCRL_SERH_E59_SHIFT (0x0000001Bu) +#define EDMA3_CCRL_SERH_E59_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SERH_E58_MASK (0x04000000u) +#define EDMA3_CCRL_SERH_E58_SHIFT (0x0000001Au) +#define EDMA3_CCRL_SERH_E58_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SERH_E57_MASK (0x02000000u) +#define EDMA3_CCRL_SERH_E57_SHIFT (0x00000019u) +#define EDMA3_CCRL_SERH_E57_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SERH_E56_MASK (0x01000000u) +#define EDMA3_CCRL_SERH_E56_SHIFT (0x00000018u) +#define EDMA3_CCRL_SERH_E56_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SERH_E55_MASK (0x00800000u) +#define EDMA3_CCRL_SERH_E55_SHIFT (0x00000017u) +#define EDMA3_CCRL_SERH_E55_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SERH_E54_MASK (0x00400000u) +#define EDMA3_CCRL_SERH_E54_SHIFT (0x00000016u) +#define EDMA3_CCRL_SERH_E54_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SERH_E53_MASK (0x00200000u) +#define EDMA3_CCRL_SERH_E53_SHIFT (0x00000015u) +#define EDMA3_CCRL_SERH_E53_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SERH_E52_MASK (0x00100000u) +#define EDMA3_CCRL_SERH_E52_SHIFT (0x00000014u) +#define EDMA3_CCRL_SERH_E52_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SERH_E51_MASK (0x00080000u) +#define EDMA3_CCRL_SERH_E51_SHIFT (0x00000013u) +#define EDMA3_CCRL_SERH_E51_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SERH_E50_MASK (0x00040000u) +#define EDMA3_CCRL_SERH_E50_SHIFT (0x00000012u) +#define EDMA3_CCRL_SERH_E50_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SERH_E49_MASK (0x00020000u) +#define EDMA3_CCRL_SERH_E49_SHIFT (0x00000011u) +#define EDMA3_CCRL_SERH_E49_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SERH_E48_MASK (0x00010000u) +#define EDMA3_CCRL_SERH_E48_SHIFT (0x00000010u) +#define EDMA3_CCRL_SERH_E48_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SERH_E47_MASK (0x00008000u) +#define EDMA3_CCRL_SERH_E47_SHIFT (0x0000000Fu) +#define EDMA3_CCRL_SERH_E47_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SERH_E46_MASK (0x00004000u) +#define EDMA3_CCRL_SERH_E46_SHIFT (0x0000000Eu) +#define EDMA3_CCRL_SERH_E46_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SERH_E45_MASK (0x00002000u) +#define EDMA3_CCRL_SERH_E45_SHIFT (0x0000000Du) +#define EDMA3_CCRL_SERH_E45_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SERH_E44_MASK (0x00001000u) +#define EDMA3_CCRL_SERH_E44_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_SERH_E44_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SERH_E43_MASK (0x00000800u) +#define EDMA3_CCRL_SERH_E43_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_SERH_E43_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SERH_E42_MASK (0x00000400u) +#define EDMA3_CCRL_SERH_E42_SHIFT (0x0000000Au) +#define EDMA3_CCRL_SERH_E42_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SERH_E41_MASK (0x00000200u) +#define EDMA3_CCRL_SERH_E41_SHIFT (0x00000009u) +#define EDMA3_CCRL_SERH_E41_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SERH_E40_MASK (0x00000100u) +#define EDMA3_CCRL_SERH_E40_SHIFT (0x00000008u) +#define EDMA3_CCRL_SERH_E40_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SERH_E39_MASK (0x00000080u) +#define EDMA3_CCRL_SERH_E39_SHIFT (0x00000007u) +#define EDMA3_CCRL_SERH_E39_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SERH_E38_MASK (0x00000040u) +#define EDMA3_CCRL_SERH_E38_SHIFT (0x00000006u) +#define EDMA3_CCRL_SERH_E38_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SERH_E37_MASK (0x00000020u) +#define EDMA3_CCRL_SERH_E37_SHIFT (0x00000005u) +#define EDMA3_CCRL_SERH_E37_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SERH_E36_MASK (0x00000010u) +#define EDMA3_CCRL_SERH_E36_SHIFT (0x00000004u) +#define EDMA3_CCRL_SERH_E36_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SERH_E35_MASK (0x00000008u) +#define EDMA3_CCRL_SERH_E35_SHIFT (0x00000003u) +#define EDMA3_CCRL_SERH_E35_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SERH_E34_MASK (0x00000004u) +#define EDMA3_CCRL_SERH_E34_SHIFT (0x00000002u) +#define EDMA3_CCRL_SERH_E34_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SERH_E33_MASK (0x00000002u) +#define EDMA3_CCRL_SERH_E33_SHIFT (0x00000001u) +#define EDMA3_CCRL_SERH_E33_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SERH_E32_MASK (0x00000001u) +#define EDMA3_CCRL_SERH_E32_SHIFT (0x00000000u) +#define EDMA3_CCRL_SERH_E32_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SERH_RESETVAL (0x00000000u) + +/* SECR */ + +#define EDMA3_CCRL_SECR_E31_MASK (0x80000000u) +#define EDMA3_CCRL_SECR_E31_SHIFT (0x0000001Fu) +#define EDMA3_CCRL_SECR_E31_RESETVAL (0x00000000u) + +/*----E31 Tokens----*/ +#define EDMA3_CCRL_SECR_E31_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECR_E30_MASK (0x40000000u) +#define EDMA3_CCRL_SECR_E30_SHIFT (0x0000001Eu) +#define EDMA3_CCRL_SECR_E30_RESETVAL (0x00000000u) + +/*----E30 Tokens----*/ +#define EDMA3_CCRL_SECR_E30_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECR_E29_MASK (0x20000000u) +#define EDMA3_CCRL_SECR_E29_SHIFT (0x0000001Du) +#define EDMA3_CCRL_SECR_E29_RESETVAL (0x00000000u) + +/*----E29 Tokens----*/ +#define EDMA3_CCRL_SECR_E29_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECR_E28_MASK (0x10000000u) +#define EDMA3_CCRL_SECR_E28_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_SECR_E28_RESETVAL (0x00000000u) + +/*----E28 Tokens----*/ +#define EDMA3_CCRL_SECR_E28_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECR_E27_MASK (0x08000000u) +#define EDMA3_CCRL_SECR_E27_SHIFT (0x0000001Bu) +#define EDMA3_CCRL_SECR_E27_RESETVAL (0x00000000u) + +/*----E27 Tokens----*/ +#define EDMA3_CCRL_SECR_E27_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECR_E26_MASK (0x04000000u) +#define EDMA3_CCRL_SECR_E26_SHIFT (0x0000001Au) +#define EDMA3_CCRL_SECR_E26_RESETVAL (0x00000000u) + +/*----E26 Tokens----*/ +#define EDMA3_CCRL_SECR_E26_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECR_E25_MASK (0x02000000u) +#define EDMA3_CCRL_SECR_E25_SHIFT (0x00000019u) +#define EDMA3_CCRL_SECR_E25_RESETVAL (0x00000000u) + +/*----E25 Tokens----*/ +#define EDMA3_CCRL_SECR_E25_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECR_E24_MASK (0x01000000u) +#define EDMA3_CCRL_SECR_E24_SHIFT (0x00000018u) +#define EDMA3_CCRL_SECR_E24_RESETVAL (0x00000000u) + +/*----E24 Tokens----*/ +#define EDMA3_CCRL_SECR_E24_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECR_E23_MASK (0x00800000u) +#define EDMA3_CCRL_SECR_E23_SHIFT (0x00000017u) +#define EDMA3_CCRL_SECR_E23_RESETVAL (0x00000000u) + +/*----E23 Tokens----*/ +#define EDMA3_CCRL_SECR_E23_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECR_E22_MASK (0x00400000u) +#define EDMA3_CCRL_SECR_E22_SHIFT (0x00000016u) +#define EDMA3_CCRL_SECR_E22_RESETVAL (0x00000000u) + +/*----E22 Tokens----*/ +#define EDMA3_CCRL_SECR_E22_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECR_E21_MASK (0x00200000u) +#define EDMA3_CCRL_SECR_E21_SHIFT (0x00000015u) +#define EDMA3_CCRL_SECR_E21_RESETVAL (0x00000000u) + +/*----E21 Tokens----*/ +#define EDMA3_CCRL_SECR_E21_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECR_E20_MASK (0x00100000u) +#define EDMA3_CCRL_SECR_E20_SHIFT (0x00000014u) +#define EDMA3_CCRL_SECR_E20_RESETVAL (0x00000000u) + +/*----E20 Tokens----*/ +#define EDMA3_CCRL_SECR_E20_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECR_E19_MASK (0x00080000u) +#define EDMA3_CCRL_SECR_E19_SHIFT (0x00000013u) +#define EDMA3_CCRL_SECR_E19_RESETVAL (0x00000000u) + +/*----E19 Tokens----*/ +#define EDMA3_CCRL_SECR_E19_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECR_E18_MASK (0x00040000u) +#define EDMA3_CCRL_SECR_E18_SHIFT (0x00000012u) +#define EDMA3_CCRL_SECR_E18_RESETVAL (0x00000000u) + +/*----E18 Tokens----*/ +#define EDMA3_CCRL_SECR_E18_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECR_E17_MASK (0x00020000u) +#define EDMA3_CCRL_SECR_E17_SHIFT (0x00000011u) +#define EDMA3_CCRL_SECR_E17_RESETVAL (0x00000000u) + +/*----E17 Tokens----*/ +#define EDMA3_CCRL_SECR_E17_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECR_E16_MASK (0x00010000u) +#define EDMA3_CCRL_SECR_E16_SHIFT (0x00000010u) +#define EDMA3_CCRL_SECR_E16_RESETVAL (0x00000000u) + +/*----E16 Tokens----*/ +#define EDMA3_CCRL_SECR_E16_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECR_E15_MASK (0x00008000u) +#define EDMA3_CCRL_SECR_E15_SHIFT (0x0000000Fu) +#define EDMA3_CCRL_SECR_E15_RESETVAL (0x00000000u) + +/*----E15 Tokens----*/ +#define EDMA3_CCRL_SECR_E15_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECR_E14_MASK (0x00004000u) +#define EDMA3_CCRL_SECR_E14_SHIFT (0x0000000Eu) +#define EDMA3_CCRL_SECR_E14_RESETVAL (0x00000000u) + +/*----E14 Tokens----*/ +#define EDMA3_CCRL_SECR_E14_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECR_E13_MASK (0x00002000u) +#define EDMA3_CCRL_SECR_E13_SHIFT (0x0000000Du) +#define EDMA3_CCRL_SECR_E13_RESETVAL (0x00000000u) + +/*----E13 Tokens----*/ +#define EDMA3_CCRL_SECR_E13_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECR_E12_MASK (0x00001000u) +#define EDMA3_CCRL_SECR_E12_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_SECR_E12_RESETVAL (0x00000000u) + +/*----E12 Tokens----*/ +#define EDMA3_CCRL_SECR_E12_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECR_E11_MASK (0x00000800u) +#define EDMA3_CCRL_SECR_E11_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_SECR_E11_RESETVAL (0x00000000u) + +/*----E11 Tokens----*/ +#define EDMA3_CCRL_SECR_E11_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECR_E10_MASK (0x00000400u) +#define EDMA3_CCRL_SECR_E10_SHIFT (0x0000000Au) +#define EDMA3_CCRL_SECR_E10_RESETVAL (0x00000000u) + +/*----E10 Tokens----*/ +#define EDMA3_CCRL_SECR_E10_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECR_E9_MASK (0x00000200u) +#define EDMA3_CCRL_SECR_E9_SHIFT (0x00000009u) +#define EDMA3_CCRL_SECR_E9_RESETVAL (0x00000000u) + +/*----E9 Tokens----*/ +#define EDMA3_CCRL_SECR_E9_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECR_E8_MASK (0x00000100u) +#define EDMA3_CCRL_SECR_E8_SHIFT (0x00000008u) +#define EDMA3_CCRL_SECR_E8_RESETVAL (0x00000000u) + +/*----E8 Tokens----*/ +#define EDMA3_CCRL_SECR_E8_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECR_E7_MASK (0x00000080u) +#define EDMA3_CCRL_SECR_E7_SHIFT (0x00000007u) +#define EDMA3_CCRL_SECR_E7_RESETVAL (0x00000000u) + +/*----E7 Tokens----*/ +#define EDMA3_CCRL_SECR_E7_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECR_E6_MASK (0x00000040u) +#define EDMA3_CCRL_SECR_E6_SHIFT (0x00000006u) +#define EDMA3_CCRL_SECR_E6_RESETVAL (0x00000000u) + +/*----E6 Tokens----*/ +#define EDMA3_CCRL_SECR_E6_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECR_E5_MASK (0x00000020u) +#define EDMA3_CCRL_SECR_E5_SHIFT (0x00000005u) +#define EDMA3_CCRL_SECR_E5_RESETVAL (0x00000000u) + +/*----E5 Tokens----*/ +#define EDMA3_CCRL_SECR_E5_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECR_E4_MASK (0x00000010u) +#define EDMA3_CCRL_SECR_E4_SHIFT (0x00000004u) +#define EDMA3_CCRL_SECR_E4_RESETVAL (0x00000000u) + +/*----E4 Tokens----*/ +#define EDMA3_CCRL_SECR_E4_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECR_E3_MASK (0x00000008u) +#define EDMA3_CCRL_SECR_E3_SHIFT (0x00000003u) +#define EDMA3_CCRL_SECR_E3_RESETVAL (0x00000000u) + +/*----E3 Tokens----*/ +#define EDMA3_CCRL_SECR_E3_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECR_E2_MASK (0x00000004u) +#define EDMA3_CCRL_SECR_E2_SHIFT (0x00000002u) +#define EDMA3_CCRL_SECR_E2_RESETVAL (0x00000000u) + +/*----E2 Tokens----*/ +#define EDMA3_CCRL_SECR_E2_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECR_E1_MASK (0x00000002u) +#define EDMA3_CCRL_SECR_E1_SHIFT (0x00000001u) +#define EDMA3_CCRL_SECR_E1_RESETVAL (0x00000000u) + +/*----E1 Tokens----*/ +#define EDMA3_CCRL_SECR_E1_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECR_E0_MASK (0x00000001u) +#define EDMA3_CCRL_SECR_E0_SHIFT (0x00000000u) +#define EDMA3_CCRL_SECR_E0_RESETVAL (0x00000000u) + +/*----E0 Tokens----*/ +#define EDMA3_CCRL_SECR_E0_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECR_RESETVAL (0x00000000u) + +/* SECRH */ + +#define EDMA3_CCRL_SECRH_E63_MASK (0x80000000u) +#define EDMA3_CCRL_SECRH_E63_SHIFT (0x0000001Fu) +#define EDMA3_CCRL_SECRH_E63_RESETVAL (0x00000000u) + +/*----E63 Tokens----*/ +#define EDMA3_CCRL_SECRH_E63_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECRH_E62_MASK (0x40000000u) +#define EDMA3_CCRL_SECRH_E62_SHIFT (0x0000001Eu) +#define EDMA3_CCRL_SECRH_E62_RESETVAL (0x00000000u) + +/*----E62 Tokens----*/ +#define EDMA3_CCRL_SECRH_E62_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECRH_E61_MASK (0x20000000u) +#define EDMA3_CCRL_SECRH_E61_SHIFT (0x0000001Du) +#define EDMA3_CCRL_SECRH_E61_RESETVAL (0x00000000u) + +/*----E61 Tokens----*/ +#define EDMA3_CCRL_SECRH_E61_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECRH_E60_MASK (0x10000000u) +#define EDMA3_CCRL_SECRH_E60_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_SECRH_E60_RESETVAL (0x00000000u) + +/*----E60 Tokens----*/ +#define EDMA3_CCRL_SECRH_E60_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECRH_E59_MASK (0x08000000u) +#define EDMA3_CCRL_SECRH_E59_SHIFT (0x0000001Bu) +#define EDMA3_CCRL_SECRH_E59_RESETVAL (0x00000000u) + +/*----E59 Tokens----*/ +#define EDMA3_CCRL_SECRH_E59_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECRH_E58_MASK (0x04000000u) +#define EDMA3_CCRL_SECRH_E58_SHIFT (0x0000001Au) +#define EDMA3_CCRL_SECRH_E58_RESETVAL (0x00000000u) + +/*----E58 Tokens----*/ +#define EDMA3_CCRL_SECRH_E58_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECRH_E57_MASK (0x02000000u) +#define EDMA3_CCRL_SECRH_E57_SHIFT (0x00000019u) +#define EDMA3_CCRL_SECRH_E57_RESETVAL (0x00000000u) + +/*----E57 Tokens----*/ +#define EDMA3_CCRL_SECRH_E57_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECRH_E56_MASK (0x01000000u) +#define EDMA3_CCRL_SECRH_E56_SHIFT (0x00000018u) +#define EDMA3_CCRL_SECRH_E56_RESETVAL (0x00000000u) + +/*----E56 Tokens----*/ +#define EDMA3_CCRL_SECRH_E56_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECRH_E55_MASK (0x00800000u) +#define EDMA3_CCRL_SECRH_E55_SHIFT (0x00000017u) +#define EDMA3_CCRL_SECRH_E55_RESETVAL (0x00000000u) + +/*----E55 Tokens----*/ +#define EDMA3_CCRL_SECRH_E55_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECRH_E54_MASK (0x00400000u) +#define EDMA3_CCRL_SECRH_E54_SHIFT (0x00000016u) +#define EDMA3_CCRL_SECRH_E54_RESETVAL (0x00000000u) + +/*----E54 Tokens----*/ +#define EDMA3_CCRL_SECRH_E54_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECRH_E53_MASK (0x00200000u) +#define EDMA3_CCRL_SECRH_E53_SHIFT (0x00000015u) +#define EDMA3_CCRL_SECRH_E53_RESETVAL (0x00000000u) + +/*----E53 Tokens----*/ +#define EDMA3_CCRL_SECRH_E53_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECRH_E52_MASK (0x00100000u) +#define EDMA3_CCRL_SECRH_E52_SHIFT (0x00000014u) +#define EDMA3_CCRL_SECRH_E52_RESETVAL (0x00000000u) + +/*----E52 Tokens----*/ +#define EDMA3_CCRL_SECRH_E52_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECRH_E51_MASK (0x00080000u) +#define EDMA3_CCRL_SECRH_E51_SHIFT (0x00000013u) +#define EDMA3_CCRL_SECRH_E51_RESETVAL (0x00000000u) + +/*----E51 Tokens----*/ +#define EDMA3_CCRL_SECRH_E51_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECRH_E50_MASK (0x00040000u) +#define EDMA3_CCRL_SECRH_E50_SHIFT (0x00000012u) +#define EDMA3_CCRL_SECRH_E50_RESETVAL (0x00000000u) + +/*----E50 Tokens----*/ +#define EDMA3_CCRL_SECRH_E50_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECRH_E49_MASK (0x00020000u) +#define EDMA3_CCRL_SECRH_E49_SHIFT (0x00000011u) +#define EDMA3_CCRL_SECRH_E49_RESETVAL (0x00000000u) + +/*----E49 Tokens----*/ +#define EDMA3_CCRL_SECRH_E49_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECRH_E48_MASK (0x00010000u) +#define EDMA3_CCRL_SECRH_E48_SHIFT (0x00000010u) +#define EDMA3_CCRL_SECRH_E48_RESETVAL (0x00000000u) + +/*----E48 Tokens----*/ +#define EDMA3_CCRL_SECRH_E48_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECRH_E47_MASK (0x00008000u) +#define EDMA3_CCRL_SECRH_E47_SHIFT (0x0000000Fu) +#define EDMA3_CCRL_SECRH_E47_RESETVAL (0x00000000u) + +/*----E47 Tokens----*/ +#define EDMA3_CCRL_SECRH_E47_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECRH_E46_MASK (0x00004000u) +#define EDMA3_CCRL_SECRH_E46_SHIFT (0x0000000Eu) +#define EDMA3_CCRL_SECRH_E46_RESETVAL (0x00000000u) + +/*----E46 Tokens----*/ +#define EDMA3_CCRL_SECRH_E46_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECRH_E45_MASK (0x00002000u) +#define EDMA3_CCRL_SECRH_E45_SHIFT (0x0000000Du) +#define EDMA3_CCRL_SECRH_E45_RESETVAL (0x00000000u) + +/*----E45 Tokens----*/ +#define EDMA3_CCRL_SECRH_E45_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECRH_E44_MASK (0x00001000u) +#define EDMA3_CCRL_SECRH_E44_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_SECRH_E44_RESETVAL (0x00000000u) + +/*----E44 Tokens----*/ +#define EDMA3_CCRL_SECRH_E44_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECRH_E43_MASK (0x00000800u) +#define EDMA3_CCRL_SECRH_E43_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_SECRH_E43_RESETVAL (0x00000000u) + +/*----E43 Tokens----*/ +#define EDMA3_CCRL_SECRH_E43_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECRH_E42_MASK (0x00000400u) +#define EDMA3_CCRL_SECRH_E42_SHIFT (0x0000000Au) +#define EDMA3_CCRL_SECRH_E42_RESETVAL (0x00000000u) + +/*----E42 Tokens----*/ +#define EDMA3_CCRL_SECRH_E42_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECRH_E41_MASK (0x00000200u) +#define EDMA3_CCRL_SECRH_E41_SHIFT (0x00000009u) +#define EDMA3_CCRL_SECRH_E41_RESETVAL (0x00000000u) + +/*----E41 Tokens----*/ +#define EDMA3_CCRL_SECRH_E41_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECRH_E40_MASK (0x00000100u) +#define EDMA3_CCRL_SECRH_E40_SHIFT (0x00000008u) +#define EDMA3_CCRL_SECRH_E40_RESETVAL (0x00000000u) + +/*----E40 Tokens----*/ +#define EDMA3_CCRL_SECRH_E40_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECRH_E39_MASK (0x00000080u) +#define EDMA3_CCRL_SECRH_E39_SHIFT (0x00000007u) +#define EDMA3_CCRL_SECRH_E39_RESETVAL (0x00000000u) + +/*----E39 Tokens----*/ +#define EDMA3_CCRL_SECRH_E39_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECRH_E38_MASK (0x00000040u) +#define EDMA3_CCRL_SECRH_E38_SHIFT (0x00000006u) +#define EDMA3_CCRL_SECRH_E38_RESETVAL (0x00000000u) + +/*----E38 Tokens----*/ +#define EDMA3_CCRL_SECRH_E38_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECRH_E37_MASK (0x00000020u) +#define EDMA3_CCRL_SECRH_E37_SHIFT (0x00000005u) +#define EDMA3_CCRL_SECRH_E37_RESETVAL (0x00000000u) + +/*----E37 Tokens----*/ +#define EDMA3_CCRL_SECRH_E37_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECRH_E36_MASK (0x00000010u) +#define EDMA3_CCRL_SECRH_E36_SHIFT (0x00000004u) +#define EDMA3_CCRL_SECRH_E36_RESETVAL (0x00000000u) + +/*----E36 Tokens----*/ +#define EDMA3_CCRL_SECRH_E36_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECRH_E35_MASK (0x00000008u) +#define EDMA3_CCRL_SECRH_E35_SHIFT (0x00000003u) +#define EDMA3_CCRL_SECRH_E35_RESETVAL (0x00000000u) + +/*----E35 Tokens----*/ +#define EDMA3_CCRL_SECRH_E35_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECRH_E34_MASK (0x00000004u) +#define EDMA3_CCRL_SECRH_E34_SHIFT (0x00000002u) +#define EDMA3_CCRL_SECRH_E34_RESETVAL (0x00000000u) + +/*----E34 Tokens----*/ +#define EDMA3_CCRL_SECRH_E34_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECRH_E33_MASK (0x00000002u) +#define EDMA3_CCRL_SECRH_E33_SHIFT (0x00000001u) +#define EDMA3_CCRL_SECRH_E33_RESETVAL (0x00000000u) + +/*----E33 Tokens----*/ +#define EDMA3_CCRL_SECRH_E33_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECRH_E32_MASK (0x00000001u) +#define EDMA3_CCRL_SECRH_E32_SHIFT (0x00000000u) +#define EDMA3_CCRL_SECRH_E32_RESETVAL (0x00000000u) + +/*----E32 Tokens----*/ +#define EDMA3_CCRL_SECRH_E32_CLEAR (0x00000001u) + +#define EDMA3_CCRL_SECRH_RESETVAL (0x00000000u) + +/* IER */ + +#define EDMA3_CCRL_IER_I31_MASK (0x80000000u) +#define EDMA3_CCRL_IER_I31_SHIFT (0x0000001Fu) +#define EDMA3_CCRL_IER_I31_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IER_I30_MASK (0x40000000u) +#define EDMA3_CCRL_IER_I30_SHIFT (0x0000001Eu) +#define EDMA3_CCRL_IER_I30_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IER_I29_MASK (0x20000000u) +#define EDMA3_CCRL_IER_I29_SHIFT (0x0000001Du) +#define EDMA3_CCRL_IER_I29_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IER_I28_MASK (0x10000000u) +#define EDMA3_CCRL_IER_I28_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_IER_I28_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IER_I27_MASK (0x08000000u) +#define EDMA3_CCRL_IER_I27_SHIFT (0x0000001Bu) +#define EDMA3_CCRL_IER_I27_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IER_I26_MASK (0x04000000u) +#define EDMA3_CCRL_IER_I26_SHIFT (0x0000001Au) +#define EDMA3_CCRL_IER_I26_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IER_I25_MASK (0x02000000u) +#define EDMA3_CCRL_IER_I25_SHIFT (0x00000019u) +#define EDMA3_CCRL_IER_I25_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IER_I24_MASK (0x01000000u) +#define EDMA3_CCRL_IER_I24_SHIFT (0x00000018u) +#define EDMA3_CCRL_IER_I24_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IER_I23_MASK (0x00800000u) +#define EDMA3_CCRL_IER_I23_SHIFT (0x00000017u) +#define EDMA3_CCRL_IER_I23_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IER_I22_MASK (0x00400000u) +#define EDMA3_CCRL_IER_I22_SHIFT (0x00000016u) +#define EDMA3_CCRL_IER_I22_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IER_I21_MASK (0x00200000u) +#define EDMA3_CCRL_IER_I21_SHIFT (0x00000015u) +#define EDMA3_CCRL_IER_I21_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IER_I20_MASK (0x00100000u) +#define EDMA3_CCRL_IER_I20_SHIFT (0x00000014u) +#define EDMA3_CCRL_IER_I20_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IER_I19_MASK (0x00080000u) +#define EDMA3_CCRL_IER_I19_SHIFT (0x00000013u) +#define EDMA3_CCRL_IER_I19_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IER_I18_MASK (0x00040000u) +#define EDMA3_CCRL_IER_I18_SHIFT (0x00000012u) +#define EDMA3_CCRL_IER_I18_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IER_I17_MASK (0x00020000u) +#define EDMA3_CCRL_IER_I17_SHIFT (0x00000011u) +#define EDMA3_CCRL_IER_I17_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IER_I16_MASK (0x00010000u) +#define EDMA3_CCRL_IER_I16_SHIFT (0x00000010u) +#define EDMA3_CCRL_IER_I16_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IER_I15_MASK (0x00008000u) +#define EDMA3_CCRL_IER_I15_SHIFT (0x0000000Fu) +#define EDMA3_CCRL_IER_I15_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IER_I14_MASK (0x00004000u) +#define EDMA3_CCRL_IER_I14_SHIFT (0x0000000Eu) +#define EDMA3_CCRL_IER_I14_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IER_I13_MASK (0x00002000u) +#define EDMA3_CCRL_IER_I13_SHIFT (0x0000000Du) +#define EDMA3_CCRL_IER_I13_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IER_I12_MASK (0x00001000u) +#define EDMA3_CCRL_IER_I12_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_IER_I12_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IER_I11_MASK (0x00000800u) +#define EDMA3_CCRL_IER_I11_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_IER_I11_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IER_I10_MASK (0x00000400u) +#define EDMA3_CCRL_IER_I10_SHIFT (0x0000000Au) +#define EDMA3_CCRL_IER_I10_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IER_I9_MASK (0x00000200u) +#define EDMA3_CCRL_IER_I9_SHIFT (0x00000009u) +#define EDMA3_CCRL_IER_I9_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IER_I8_MASK (0x00000100u) +#define EDMA3_CCRL_IER_I8_SHIFT (0x00000008u) +#define EDMA3_CCRL_IER_I8_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IER_I7_MASK (0x00000080u) +#define EDMA3_CCRL_IER_I7_SHIFT (0x00000007u) +#define EDMA3_CCRL_IER_I7_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IER_I6_MASK (0x00000040u) +#define EDMA3_CCRL_IER_I6_SHIFT (0x00000006u) +#define EDMA3_CCRL_IER_I6_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IER_I5_MASK (0x00000020u) +#define EDMA3_CCRL_IER_I5_SHIFT (0x00000005u) +#define EDMA3_CCRL_IER_I5_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IER_I4_MASK (0x00000010u) +#define EDMA3_CCRL_IER_I4_SHIFT (0x00000004u) +#define EDMA3_CCRL_IER_I4_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IER_I3_MASK (0x00000008u) +#define EDMA3_CCRL_IER_I3_SHIFT (0x00000003u) +#define EDMA3_CCRL_IER_I3_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IER_I2_MASK (0x00000004u) +#define EDMA3_CCRL_IER_I2_SHIFT (0x00000002u) +#define EDMA3_CCRL_IER_I2_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IER_I1_MASK (0x00000002u) +#define EDMA3_CCRL_IER_I1_SHIFT (0x00000001u) +#define EDMA3_CCRL_IER_I1_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IER_I0_MASK (0x00000001u) +#define EDMA3_CCRL_IER_I0_SHIFT (0x00000000u) +#define EDMA3_CCRL_IER_I0_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IER_RESETVAL (0x00000000u) + +/* IERH */ + +#define EDMA3_CCRL_IERH_I63_MASK (0x80000000u) +#define EDMA3_CCRL_IERH_I63_SHIFT (0x0000001Fu) +#define EDMA3_CCRL_IERH_I63_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IERH_I62_MASK (0x40000000u) +#define EDMA3_CCRL_IERH_I62_SHIFT (0x0000001Eu) +#define EDMA3_CCRL_IERH_I62_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IERH_I61_MASK (0x20000000u) +#define EDMA3_CCRL_IERH_I61_SHIFT (0x0000001Du) +#define EDMA3_CCRL_IERH_I61_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IERH_I60_MASK (0x10000000u) +#define EDMA3_CCRL_IERH_I60_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_IERH_I60_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IERH_I59_MASK (0x08000000u) +#define EDMA3_CCRL_IERH_I59_SHIFT (0x0000001Bu) +#define EDMA3_CCRL_IERH_I59_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IERH_I58_MASK (0x04000000u) +#define EDMA3_CCRL_IERH_I58_SHIFT (0x0000001Au) +#define EDMA3_CCRL_IERH_I58_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IERH_I57_MASK (0x02000000u) +#define EDMA3_CCRL_IERH_I57_SHIFT (0x00000019u) +#define EDMA3_CCRL_IERH_I57_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IERH_I56_MASK (0x01000000u) +#define EDMA3_CCRL_IERH_I56_SHIFT (0x00000018u) +#define EDMA3_CCRL_IERH_I56_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IERH_I55_MASK (0x00800000u) +#define EDMA3_CCRL_IERH_I55_SHIFT (0x00000017u) +#define EDMA3_CCRL_IERH_I55_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IERH_I54_MASK (0x00400000u) +#define EDMA3_CCRL_IERH_I54_SHIFT (0x00000016u) +#define EDMA3_CCRL_IERH_I54_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IERH_I53_MASK (0x00200000u) +#define EDMA3_CCRL_IERH_I53_SHIFT (0x00000015u) +#define EDMA3_CCRL_IERH_I53_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IERH_I52_MASK (0x00100000u) +#define EDMA3_CCRL_IERH_I52_SHIFT (0x00000014u) +#define EDMA3_CCRL_IERH_I52_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IERH_I51_MASK (0x00080000u) +#define EDMA3_CCRL_IERH_I51_SHIFT (0x00000013u) +#define EDMA3_CCRL_IERH_I51_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IERH_I50_MASK (0x00040000u) +#define EDMA3_CCRL_IERH_I50_SHIFT (0x00000012u) +#define EDMA3_CCRL_IERH_I50_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IERH_I49_MASK (0x00020000u) +#define EDMA3_CCRL_IERH_I49_SHIFT (0x00000011u) +#define EDMA3_CCRL_IERH_I49_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IERH_I48_MASK (0x00010000u) +#define EDMA3_CCRL_IERH_I48_SHIFT (0x00000010u) +#define EDMA3_CCRL_IERH_I48_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IERH_I47_MASK (0x00008000u) +#define EDMA3_CCRL_IERH_I47_SHIFT (0x0000000Fu) +#define EDMA3_CCRL_IERH_I47_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IERH_I46_MASK (0x00004000u) +#define EDMA3_CCRL_IERH_I46_SHIFT (0x0000000Eu) +#define EDMA3_CCRL_IERH_I46_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IERH_I45_MASK (0x00002000u) +#define EDMA3_CCRL_IERH_I45_SHIFT (0x0000000Du) +#define EDMA3_CCRL_IERH_I45_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IERH_I44_MASK (0x00001000u) +#define EDMA3_CCRL_IERH_I44_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_IERH_I44_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IERH_I43_MASK (0x00000800u) +#define EDMA3_CCRL_IERH_I43_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_IERH_I43_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IERH_I42_MASK (0x00000400u) +#define EDMA3_CCRL_IERH_I42_SHIFT (0x0000000Au) +#define EDMA3_CCRL_IERH_I42_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IERH_I41_MASK (0x00000200u) +#define EDMA3_CCRL_IERH_I41_SHIFT (0x00000009u) +#define EDMA3_CCRL_IERH_I41_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IERH_I40_MASK (0x00000100u) +#define EDMA3_CCRL_IERH_I40_SHIFT (0x00000008u) +#define EDMA3_CCRL_IERH_I40_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IERH_I39_MASK (0x00000080u) +#define EDMA3_CCRL_IERH_I39_SHIFT (0x00000007u) +#define EDMA3_CCRL_IERH_I39_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IERH_I38_MASK (0x00000040u) +#define EDMA3_CCRL_IERH_I38_SHIFT (0x00000006u) +#define EDMA3_CCRL_IERH_I38_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IERH_I37_MASK (0x00000020u) +#define EDMA3_CCRL_IERH_I37_SHIFT (0x00000005u) +#define EDMA3_CCRL_IERH_I37_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IERH_I36_MASK (0x00000010u) +#define EDMA3_CCRL_IERH_I36_SHIFT (0x00000004u) +#define EDMA3_CCRL_IERH_I36_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IERH_I35_MASK (0x00000008u) +#define EDMA3_CCRL_IERH_I35_SHIFT (0x00000003u) +#define EDMA3_CCRL_IERH_I35_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IERH_I34_MASK (0x00000004u) +#define EDMA3_CCRL_IERH_I34_SHIFT (0x00000002u) +#define EDMA3_CCRL_IERH_I34_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IERH_I33_MASK (0x00000002u) +#define EDMA3_CCRL_IERH_I33_SHIFT (0x00000001u) +#define EDMA3_CCRL_IERH_I33_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IERH_I32_MASK (0x00000001u) +#define EDMA3_CCRL_IERH_I32_SHIFT (0x00000000u) +#define EDMA3_CCRL_IERH_I32_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IERH_RESETVAL (0x00000000u) + +/* IECR */ + +#define EDMA3_CCRL_IECR_I31_MASK (0x80000000u) +#define EDMA3_CCRL_IECR_I31_SHIFT (0x0000001Fu) +#define EDMA3_CCRL_IECR_I31_RESETVAL (0x00000000u) + +/*----I31 Tokens----*/ +#define EDMA3_CCRL_IECR_I31_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECR_I30_MASK (0x40000000u) +#define EDMA3_CCRL_IECR_I30_SHIFT (0x0000001Eu) +#define EDMA3_CCRL_IECR_I30_RESETVAL (0x00000000u) + +/*----I30 Tokens----*/ +#define EDMA3_CCRL_IECR_I30_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECR_I29_MASK (0x20000000u) +#define EDMA3_CCRL_IECR_I29_SHIFT (0x0000001Du) +#define EDMA3_CCRL_IECR_I29_RESETVAL (0x00000000u) + +/*----I29 Tokens----*/ +#define EDMA3_CCRL_IECR_I29_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECR_I28_MASK (0x10000000u) +#define EDMA3_CCRL_IECR_I28_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_IECR_I28_RESETVAL (0x00000000u) + +/*----I28 Tokens----*/ +#define EDMA3_CCRL_IECR_I28_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECR_I27_MASK (0x08000000u) +#define EDMA3_CCRL_IECR_I27_SHIFT (0x0000001Bu) +#define EDMA3_CCRL_IECR_I27_RESETVAL (0x00000000u) + +/*----I27 Tokens----*/ +#define EDMA3_CCRL_IECR_I27_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECR_I26_MASK (0x04000000u) +#define EDMA3_CCRL_IECR_I26_SHIFT (0x0000001Au) +#define EDMA3_CCRL_IECR_I26_RESETVAL (0x00000000u) + +/*----I26 Tokens----*/ +#define EDMA3_CCRL_IECR_I26_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECR_I25_MASK (0x02000000u) +#define EDMA3_CCRL_IECR_I25_SHIFT (0x00000019u) +#define EDMA3_CCRL_IECR_I25_RESETVAL (0x00000000u) + +/*----I25 Tokens----*/ +#define EDMA3_CCRL_IECR_I25_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECR_I24_MASK (0x01000000u) +#define EDMA3_CCRL_IECR_I24_SHIFT (0x00000018u) +#define EDMA3_CCRL_IECR_I24_RESETVAL (0x00000000u) + +/*----I24 Tokens----*/ +#define EDMA3_CCRL_IECR_I24_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECR_I23_MASK (0x00800000u) +#define EDMA3_CCRL_IECR_I23_SHIFT (0x00000017u) +#define EDMA3_CCRL_IECR_I23_RESETVAL (0x00000000u) + +/*----I23 Tokens----*/ +#define EDMA3_CCRL_IECR_I23_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECR_I22_MASK (0x00400000u) +#define EDMA3_CCRL_IECR_I22_SHIFT (0x00000016u) +#define EDMA3_CCRL_IECR_I22_RESETVAL (0x00000000u) + +/*----I22 Tokens----*/ +#define EDMA3_CCRL_IECR_I22_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECR_I21_MASK (0x00200000u) +#define EDMA3_CCRL_IECR_I21_SHIFT (0x00000015u) +#define EDMA3_CCRL_IECR_I21_RESETVAL (0x00000000u) + +/*----I21 Tokens----*/ +#define EDMA3_CCRL_IECR_I21_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECR_I20_MASK (0x00100000u) +#define EDMA3_CCRL_IECR_I20_SHIFT (0x00000014u) +#define EDMA3_CCRL_IECR_I20_RESETVAL (0x00000000u) + +/*----I20 Tokens----*/ +#define EDMA3_CCRL_IECR_I20_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECR_I19_MASK (0x00080000u) +#define EDMA3_CCRL_IECR_I19_SHIFT (0x00000013u) +#define EDMA3_CCRL_IECR_I19_RESETVAL (0x00000000u) + +/*----I19 Tokens----*/ +#define EDMA3_CCRL_IECR_I19_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECR_I18_MASK (0x00040000u) +#define EDMA3_CCRL_IECR_I18_SHIFT (0x00000012u) +#define EDMA3_CCRL_IECR_I18_RESETVAL (0x00000000u) + +/*----I18 Tokens----*/ +#define EDMA3_CCRL_IECR_I18_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECR_I17_MASK (0x00020000u) +#define EDMA3_CCRL_IECR_I17_SHIFT (0x00000011u) +#define EDMA3_CCRL_IECR_I17_RESETVAL (0x00000000u) + +/*----I17 Tokens----*/ +#define EDMA3_CCRL_IECR_I17_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECR_I16_MASK (0x00010000u) +#define EDMA3_CCRL_IECR_I16_SHIFT (0x00000010u) +#define EDMA3_CCRL_IECR_I16_RESETVAL (0x00000000u) + +/*----I16 Tokens----*/ +#define EDMA3_CCRL_IECR_I16_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECR_I15_MASK (0x00008000u) +#define EDMA3_CCRL_IECR_I15_SHIFT (0x0000000Fu) +#define EDMA3_CCRL_IECR_I15_RESETVAL (0x00000000u) + +/*----I15 Tokens----*/ +#define EDMA3_CCRL_IECR_I15_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECR_I14_MASK (0x00004000u) +#define EDMA3_CCRL_IECR_I14_SHIFT (0x0000000Eu) +#define EDMA3_CCRL_IECR_I14_RESETVAL (0x00000000u) + +/*----I14 Tokens----*/ +#define EDMA3_CCRL_IECR_I14_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECR_I13_MASK (0x00002000u) +#define EDMA3_CCRL_IECR_I13_SHIFT (0x0000000Du) +#define EDMA3_CCRL_IECR_I13_RESETVAL (0x00000000u) + +/*----I13 Tokens----*/ +#define EDMA3_CCRL_IECR_I13_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECR_I12_MASK (0x00001000u) +#define EDMA3_CCRL_IECR_I12_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_IECR_I12_RESETVAL (0x00000000u) + +/*----I12 Tokens----*/ +#define EDMA3_CCRL_IECR_I12_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECR_I11_MASK (0x00000800u) +#define EDMA3_CCRL_IECR_I11_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_IECR_I11_RESETVAL (0x00000000u) + +/*----I11 Tokens----*/ +#define EDMA3_CCRL_IECR_I11_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECR_I10_MASK (0x00000400u) +#define EDMA3_CCRL_IECR_I10_SHIFT (0x0000000Au) +#define EDMA3_CCRL_IECR_I10_RESETVAL (0x00000000u) + +/*----I10 Tokens----*/ +#define EDMA3_CCRL_IECR_I10_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECR_I9_MASK (0x00000200u) +#define EDMA3_CCRL_IECR_I9_SHIFT (0x00000009u) +#define EDMA3_CCRL_IECR_I9_RESETVAL (0x00000000u) + +/*----I9 Tokens----*/ +#define EDMA3_CCRL_IECR_I9_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECR_I8_MASK (0x00000100u) +#define EDMA3_CCRL_IECR_I8_SHIFT (0x00000008u) +#define EDMA3_CCRL_IECR_I8_RESETVAL (0x00000000u) + +/*----I8 Tokens----*/ +#define EDMA3_CCRL_IECR_I8_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECR_I7_MASK (0x00000080u) +#define EDMA3_CCRL_IECR_I7_SHIFT (0x00000007u) +#define EDMA3_CCRL_IECR_I7_RESETVAL (0x00000000u) + +/*----I7 Tokens----*/ +#define EDMA3_CCRL_IECR_I7_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECR_I6_MASK (0x00000040u) +#define EDMA3_CCRL_IECR_I6_SHIFT (0x00000006u) +#define EDMA3_CCRL_IECR_I6_RESETVAL (0x00000000u) + +/*----I6 Tokens----*/ +#define EDMA3_CCRL_IECR_I6_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECR_I5_MASK (0x00000020u) +#define EDMA3_CCRL_IECR_I5_SHIFT (0x00000005u) +#define EDMA3_CCRL_IECR_I5_RESETVAL (0x00000000u) + +/*----I5 Tokens----*/ +#define EDMA3_CCRL_IECR_I5_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECR_I4_MASK (0x00000010u) +#define EDMA3_CCRL_IECR_I4_SHIFT (0x00000004u) +#define EDMA3_CCRL_IECR_I4_RESETVAL (0x00000000u) + +/*----I4 Tokens----*/ +#define EDMA3_CCRL_IECR_I4_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECR_I3_MASK (0x00000008u) +#define EDMA3_CCRL_IECR_I3_SHIFT (0x00000003u) +#define EDMA3_CCRL_IECR_I3_RESETVAL (0x00000000u) + +/*----I3 Tokens----*/ +#define EDMA3_CCRL_IECR_I3_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECR_I2_MASK (0x00000004u) +#define EDMA3_CCRL_IECR_I2_SHIFT (0x00000002u) +#define EDMA3_CCRL_IECR_I2_RESETVAL (0x00000000u) + +/*----I2 Tokens----*/ +#define EDMA3_CCRL_IECR_I2_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECR_I1_MASK (0x00000002u) +#define EDMA3_CCRL_IECR_I1_SHIFT (0x00000001u) +#define EDMA3_CCRL_IECR_I1_RESETVAL (0x00000000u) + +/*----I1 Tokens----*/ +#define EDMA3_CCRL_IECR_I1_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECR_I0_MASK (0x00000001u) +#define EDMA3_CCRL_IECR_I0_SHIFT (0x00000000u) +#define EDMA3_CCRL_IECR_I0_RESETVAL (0x00000000u) + +/*----I0 Tokens----*/ +#define EDMA3_CCRL_IECR_I0_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECR_RESETVAL (0x00000000u) + +/* IECRH */ + +#define EDMA3_CCRL_IECRH_I63_MASK (0x80000000u) +#define EDMA3_CCRL_IECRH_I63_SHIFT (0x0000001Fu) +#define EDMA3_CCRL_IECRH_I63_RESETVAL (0x00000000u) + +/*----I63 Tokens----*/ +#define EDMA3_CCRL_IECRH_I63_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECRH_I62_MASK (0x40000000u) +#define EDMA3_CCRL_IECRH_I62_SHIFT (0x0000001Eu) +#define EDMA3_CCRL_IECRH_I62_RESETVAL (0x00000000u) + +/*----I62 Tokens----*/ +#define EDMA3_CCRL_IECRH_I62_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECRH_I61_MASK (0x20000000u) +#define EDMA3_CCRL_IECRH_I61_SHIFT (0x0000001Du) +#define EDMA3_CCRL_IECRH_I61_RESETVAL (0x00000000u) + +/*----I61 Tokens----*/ +#define EDMA3_CCRL_IECRH_I61_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECRH_I60_MASK (0x10000000u) +#define EDMA3_CCRL_IECRH_I60_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_IECRH_I60_RESETVAL (0x00000000u) + +/*----I60 Tokens----*/ +#define EDMA3_CCRL_IECRH_I60_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECRH_I59_MASK (0x08000000u) +#define EDMA3_CCRL_IECRH_I59_SHIFT (0x0000001Bu) +#define EDMA3_CCRL_IECRH_I59_RESETVAL (0x00000000u) + +/*----I59 Tokens----*/ +#define EDMA3_CCRL_IECRH_I59_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECRH_I58_MASK (0x04000000u) +#define EDMA3_CCRL_IECRH_I58_SHIFT (0x0000001Au) +#define EDMA3_CCRL_IECRH_I58_RESETVAL (0x00000000u) + +/*----I58 Tokens----*/ +#define EDMA3_CCRL_IECRH_I58_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECRH_I57_MASK (0x02000000u) +#define EDMA3_CCRL_IECRH_I57_SHIFT (0x00000019u) +#define EDMA3_CCRL_IECRH_I57_RESETVAL (0x00000000u) + +/*----I57 Tokens----*/ +#define EDMA3_CCRL_IECRH_I57_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECRH_I56_MASK (0x01000000u) +#define EDMA3_CCRL_IECRH_I56_SHIFT (0x00000018u) +#define EDMA3_CCRL_IECRH_I56_RESETVAL (0x00000000u) + +/*----I56 Tokens----*/ +#define EDMA3_CCRL_IECRH_I56_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECRH_I55_MASK (0x00800000u) +#define EDMA3_CCRL_IECRH_I55_SHIFT (0x00000017u) +#define EDMA3_CCRL_IECRH_I55_RESETVAL (0x00000000u) + +/*----I55 Tokens----*/ +#define EDMA3_CCRL_IECRH_I55_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECRH_I54_MASK (0x00400000u) +#define EDMA3_CCRL_IECRH_I54_SHIFT (0x00000016u) +#define EDMA3_CCRL_IECRH_I54_RESETVAL (0x00000000u) + +/*----I54 Tokens----*/ +#define EDMA3_CCRL_IECRH_I54_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECRH_I53_MASK (0x00200000u) +#define EDMA3_CCRL_IECRH_I53_SHIFT (0x00000015u) +#define EDMA3_CCRL_IECRH_I53_RESETVAL (0x00000000u) + +/*----I53 Tokens----*/ +#define EDMA3_CCRL_IECRH_I53_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECRH_I52_MASK (0x00100000u) +#define EDMA3_CCRL_IECRH_I52_SHIFT (0x00000014u) +#define EDMA3_CCRL_IECRH_I52_RESETVAL (0x00000000u) + +/*----I52 Tokens----*/ +#define EDMA3_CCRL_IECRH_I52_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECRH_I51_MASK (0x00080000u) +#define EDMA3_CCRL_IECRH_I51_SHIFT (0x00000013u) +#define EDMA3_CCRL_IECRH_I51_RESETVAL (0x00000000u) + +/*----I51 Tokens----*/ +#define EDMA3_CCRL_IECRH_I51_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECRH_I50_MASK (0x00040000u) +#define EDMA3_CCRL_IECRH_I50_SHIFT (0x00000012u) +#define EDMA3_CCRL_IECRH_I50_RESETVAL (0x00000000u) + +/*----I50 Tokens----*/ +#define EDMA3_CCRL_IECRH_I50_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECRH_I49_MASK (0x00020000u) +#define EDMA3_CCRL_IECRH_I49_SHIFT (0x00000011u) +#define EDMA3_CCRL_IECRH_I49_RESETVAL (0x00000000u) + +/*----I49 Tokens----*/ +#define EDMA3_CCRL_IECRH_I49_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECRH_I48_MASK (0x00010000u) +#define EDMA3_CCRL_IECRH_I48_SHIFT (0x00000010u) +#define EDMA3_CCRL_IECRH_I48_RESETVAL (0x00000000u) + +/*----I48 Tokens----*/ +#define EDMA3_CCRL_IECRH_I48_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECRH_I47_MASK (0x00008000u) +#define EDMA3_CCRL_IECRH_I47_SHIFT (0x0000000Fu) +#define EDMA3_CCRL_IECRH_I47_RESETVAL (0x00000000u) + +/*----I47 Tokens----*/ +#define EDMA3_CCRL_IECRH_I47_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECRH_I46_MASK (0x00004000u) +#define EDMA3_CCRL_IECRH_I46_SHIFT (0x0000000Eu) +#define EDMA3_CCRL_IECRH_I46_RESETVAL (0x00000000u) + +/*----I46 Tokens----*/ +#define EDMA3_CCRL_IECRH_I46_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECRH_I45_MASK (0x00002000u) +#define EDMA3_CCRL_IECRH_I45_SHIFT (0x0000000Du) +#define EDMA3_CCRL_IECRH_I45_RESETVAL (0x00000000u) + +/*----I45 Tokens----*/ +#define EDMA3_CCRL_IECRH_I45_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECRH_I44_MASK (0x00001000u) +#define EDMA3_CCRL_IECRH_I44_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_IECRH_I44_RESETVAL (0x00000000u) + +/*----I44 Tokens----*/ +#define EDMA3_CCRL_IECRH_I44_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECRH_I43_MASK (0x00000800u) +#define EDMA3_CCRL_IECRH_I43_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_IECRH_I43_RESETVAL (0x00000000u) + +/*----I43 Tokens----*/ +#define EDMA3_CCRL_IECRH_I43_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECRH_I42_MASK (0x00000400u) +#define EDMA3_CCRL_IECRH_I42_SHIFT (0x0000000Au) +#define EDMA3_CCRL_IECRH_I42_RESETVAL (0x00000000u) + +/*----I42 Tokens----*/ +#define EDMA3_CCRL_IECRH_I42_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECRH_I41_MASK (0x00000200u) +#define EDMA3_CCRL_IECRH_I41_SHIFT (0x00000009u) +#define EDMA3_CCRL_IECRH_I41_RESETVAL (0x00000000u) + +/*----I41 Tokens----*/ +#define EDMA3_CCRL_IECRH_I41_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECRH_I40_MASK (0x00000100u) +#define EDMA3_CCRL_IECRH_I40_SHIFT (0x00000008u) +#define EDMA3_CCRL_IECRH_I40_RESETVAL (0x00000000u) + +/*----I40 Tokens----*/ +#define EDMA3_CCRL_IECRH_I40_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECRH_I39_MASK (0x00000080u) +#define EDMA3_CCRL_IECRH_I39_SHIFT (0x00000007u) +#define EDMA3_CCRL_IECRH_I39_RESETVAL (0x00000000u) + +/*----I39 Tokens----*/ +#define EDMA3_CCRL_IECRH_I39_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECRH_I38_MASK (0x00000040u) +#define EDMA3_CCRL_IECRH_I38_SHIFT (0x00000006u) +#define EDMA3_CCRL_IECRH_I38_RESETVAL (0x00000000u) + +/*----I38 Tokens----*/ +#define EDMA3_CCRL_IECRH_I38_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECRH_I37_MASK (0x00000020u) +#define EDMA3_CCRL_IECRH_I37_SHIFT (0x00000005u) +#define EDMA3_CCRL_IECRH_I37_RESETVAL (0x00000000u) + +/*----I37 Tokens----*/ +#define EDMA3_CCRL_IECRH_I37_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECRH_I36_MASK (0x00000010u) +#define EDMA3_CCRL_IECRH_I36_SHIFT (0x00000004u) +#define EDMA3_CCRL_IECRH_I36_RESETVAL (0x00000000u) + +/*----I36 Tokens----*/ +#define EDMA3_CCRL_IECRH_I36_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECRH_I35_MASK (0x00000008u) +#define EDMA3_CCRL_IECRH_I35_SHIFT (0x00000003u) +#define EDMA3_CCRL_IECRH_I35_RESETVAL (0x00000000u) + +/*----I35 Tokens----*/ +#define EDMA3_CCRL_IECRH_I35_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECRH_I34_MASK (0x00000004u) +#define EDMA3_CCRL_IECRH_I34_SHIFT (0x00000002u) +#define EDMA3_CCRL_IECRH_I34_RESETVAL (0x00000000u) + +/*----I34 Tokens----*/ +#define EDMA3_CCRL_IECRH_I34_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECRH_I33_MASK (0x00000002u) +#define EDMA3_CCRL_IECRH_I33_SHIFT (0x00000001u) +#define EDMA3_CCRL_IECRH_I33_RESETVAL (0x00000000u) + +/*----I33 Tokens----*/ +#define EDMA3_CCRL_IECRH_I33_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECRH_I32_MASK (0x00000001u) +#define EDMA3_CCRL_IECRH_I32_SHIFT (0x00000000u) +#define EDMA3_CCRL_IECRH_I32_RESETVAL (0x00000000u) + +/*----I32 Tokens----*/ +#define EDMA3_CCRL_IECRH_I32_CLEAR (0x00000001u) + +#define EDMA3_CCRL_IECRH_RESETVAL (0x00000000u) + +/* IESR */ + +#define EDMA3_CCRL_IESR_I31_MASK (0x80000000u) +#define EDMA3_CCRL_IESR_I31_SHIFT (0x0000001Fu) +#define EDMA3_CCRL_IESR_I31_RESETVAL (0x00000000u) + +/*----I31 Tokens----*/ +#define EDMA3_CCRL_IESR_I31_SET (0x00000001u) + +#define EDMA3_CCRL_IESR_I30_MASK (0x40000000u) +#define EDMA3_CCRL_IESR_I30_SHIFT (0x0000001Eu) +#define EDMA3_CCRL_IESR_I30_RESETVAL (0x00000000u) + +/*----I30 Tokens----*/ +#define EDMA3_CCRL_IESR_I30_SET (0x00000001u) + +#define EDMA3_CCRL_IESR_I29_MASK (0x20000000u) +#define EDMA3_CCRL_IESR_I29_SHIFT (0x0000001Du) +#define EDMA3_CCRL_IESR_I29_RESETVAL (0x00000000u) + +/*----I29 Tokens----*/ +#define EDMA3_CCRL_IESR_I29_SET (0x00000001u) + +#define EDMA3_CCRL_IESR_I28_MASK (0x10000000u) +#define EDMA3_CCRL_IESR_I28_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_IESR_I28_RESETVAL (0x00000000u) + +/*----I28 Tokens----*/ +#define EDMA3_CCRL_IESR_I28_SET (0x00000001u) + +#define EDMA3_CCRL_IESR_I27_MASK (0x08000000u) +#define EDMA3_CCRL_IESR_I27_SHIFT (0x0000001Bu) +#define EDMA3_CCRL_IESR_I27_RESETVAL (0x00000000u) + +/*----I27 Tokens----*/ +#define EDMA3_CCRL_IESR_I27_SET (0x00000001u) + +#define EDMA3_CCRL_IESR_I26_MASK (0x04000000u) +#define EDMA3_CCRL_IESR_I26_SHIFT (0x0000001Au) +#define EDMA3_CCRL_IESR_I26_RESETVAL (0x00000000u) + +/*----I26 Tokens----*/ +#define EDMA3_CCRL_IESR_I26_SET (0x00000001u) + +#define EDMA3_CCRL_IESR_I25_MASK (0x02000000u) +#define EDMA3_CCRL_IESR_I25_SHIFT (0x00000019u) +#define EDMA3_CCRL_IESR_I25_RESETVAL (0x00000000u) + +/*----I25 Tokens----*/ +#define EDMA3_CCRL_IESR_I25_SET (0x00000001u) + +#define EDMA3_CCRL_IESR_I24_MASK (0x01000000u) +#define EDMA3_CCRL_IESR_I24_SHIFT (0x00000018u) +#define EDMA3_CCRL_IESR_I24_RESETVAL (0x00000000u) + +/*----I24 Tokens----*/ +#define EDMA3_CCRL_IESR_I24_SET (0x00000001u) + +#define EDMA3_CCRL_IESR_I23_MASK (0x00800000u) +#define EDMA3_CCRL_IESR_I23_SHIFT (0x00000017u) +#define EDMA3_CCRL_IESR_I23_RESETVAL (0x00000000u) + +/*----I23 Tokens----*/ +#define EDMA3_CCRL_IESR_I23_SET (0x00000001u) + +#define EDMA3_CCRL_IESR_I22_MASK (0x00400000u) +#define EDMA3_CCRL_IESR_I22_SHIFT (0x00000016u) +#define EDMA3_CCRL_IESR_I22_RESETVAL (0x00000000u) + +/*----I22 Tokens----*/ +#define EDMA3_CCRL_IESR_I22_SET (0x00000001u) + +#define EDMA3_CCRL_IESR_I21_MASK (0x00200000u) +#define EDMA3_CCRL_IESR_I21_SHIFT (0x00000015u) +#define EDMA3_CCRL_IESR_I21_RESETVAL (0x00000000u) + +/*----I21 Tokens----*/ +#define EDMA3_CCRL_IESR_I21_SET (0x00000001u) + +#define EDMA3_CCRL_IESR_I20_MASK (0x00100000u) +#define EDMA3_CCRL_IESR_I20_SHIFT (0x00000014u) +#define EDMA3_CCRL_IESR_I20_RESETVAL (0x00000000u) + +/*----I20 Tokens----*/ +#define EDMA3_CCRL_IESR_I20_SET (0x00000001u) + +#define EDMA3_CCRL_IESR_I19_MASK (0x00080000u) +#define EDMA3_CCRL_IESR_I19_SHIFT (0x00000013u) +#define EDMA3_CCRL_IESR_I19_RESETVAL (0x00000000u) + +/*----I19 Tokens----*/ +#define EDMA3_CCRL_IESR_I19_SET (0x00000001u) + +#define EDMA3_CCRL_IESR_I18_MASK (0x00040000u) +#define EDMA3_CCRL_IESR_I18_SHIFT (0x00000012u) +#define EDMA3_CCRL_IESR_I18_RESETVAL (0x00000000u) + +/*----I18 Tokens----*/ +#define EDMA3_CCRL_IESR_I18_SET (0x00000001u) + +#define EDMA3_CCRL_IESR_I17_MASK (0x00020000u) +#define EDMA3_CCRL_IESR_I17_SHIFT (0x00000011u) +#define EDMA3_CCRL_IESR_I17_RESETVAL (0x00000000u) + +/*----I17 Tokens----*/ +#define EDMA3_CCRL_IESR_I17_SET (0x00000001u) + +#define EDMA3_CCRL_IESR_I16_MASK (0x00010000u) +#define EDMA3_CCRL_IESR_I16_SHIFT (0x00000010u) +#define EDMA3_CCRL_IESR_I16_RESETVAL (0x00000000u) + +/*----I16 Tokens----*/ +#define EDMA3_CCRL_IESR_I16_SET (0x00000001u) + +#define EDMA3_CCRL_IESR_I15_MASK (0x00008000u) +#define EDMA3_CCRL_IESR_I15_SHIFT (0x0000000Fu) +#define EDMA3_CCRL_IESR_I15_RESETVAL (0x00000000u) + +/*----I15 Tokens----*/ +#define EDMA3_CCRL_IESR_I15_SET (0x00000001u) + +#define EDMA3_CCRL_IESR_I14_MASK (0x00004000u) +#define EDMA3_CCRL_IESR_I14_SHIFT (0x0000000Eu) +#define EDMA3_CCRL_IESR_I14_RESETVAL (0x00000000u) + +/*----I14 Tokens----*/ +#define EDMA3_CCRL_IESR_I14_SET (0x00000001u) + +#define EDMA3_CCRL_IESR_I13_MASK (0x00002000u) +#define EDMA3_CCRL_IESR_I13_SHIFT (0x0000000Du) +#define EDMA3_CCRL_IESR_I13_RESETVAL (0x00000000u) + +/*----I13 Tokens----*/ +#define EDMA3_CCRL_IESR_I13_SET (0x00000001u) + +#define EDMA3_CCRL_IESR_I12_MASK (0x00001000u) +#define EDMA3_CCRL_IESR_I12_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_IESR_I12_RESETVAL (0x00000000u) + +/*----I12 Tokens----*/ +#define EDMA3_CCRL_IESR_I12_SET (0x00000001u) + +#define EDMA3_CCRL_IESR_I11_MASK (0x00000800u) +#define EDMA3_CCRL_IESR_I11_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_IESR_I11_RESETVAL (0x00000000u) + +/*----I11 Tokens----*/ +#define EDMA3_CCRL_IESR_I11_SET (0x00000001u) + +#define EDMA3_CCRL_IESR_I10_MASK (0x00000400u) +#define EDMA3_CCRL_IESR_I10_SHIFT (0x0000000Au) +#define EDMA3_CCRL_IESR_I10_RESETVAL (0x00000000u) + +/*----I10 Tokens----*/ +#define EDMA3_CCRL_IESR_I10_SET (0x00000001u) + +#define EDMA3_CCRL_IESR_I9_MASK (0x00000200u) +#define EDMA3_CCRL_IESR_I9_SHIFT (0x00000009u) +#define EDMA3_CCRL_IESR_I9_RESETVAL (0x00000000u) + +/*----I9 Tokens----*/ +#define EDMA3_CCRL_IESR_I9_SET (0x00000001u) + +#define EDMA3_CCRL_IESR_I8_MASK (0x00000100u) +#define EDMA3_CCRL_IESR_I8_SHIFT (0x00000008u) +#define EDMA3_CCRL_IESR_I8_RESETVAL (0x00000000u) + +/*----I8 Tokens----*/ +#define EDMA3_CCRL_IESR_I8_SET (0x00000001u) + +#define EDMA3_CCRL_IESR_I7_MASK (0x00000080u) +#define EDMA3_CCRL_IESR_I7_SHIFT (0x00000007u) +#define EDMA3_CCRL_IESR_I7_RESETVAL (0x00000000u) + +/*----I7 Tokens----*/ +#define EDMA3_CCRL_IESR_I7_SET (0x00000001u) + +#define EDMA3_CCRL_IESR_I6_MASK (0x00000040u) +#define EDMA3_CCRL_IESR_I6_SHIFT (0x00000006u) +#define EDMA3_CCRL_IESR_I6_RESETVAL (0x00000000u) + +/*----I6 Tokens----*/ +#define EDMA3_CCRL_IESR_I6_SET (0x00000001u) + +#define EDMA3_CCRL_IESR_I5_MASK (0x00000020u) +#define EDMA3_CCRL_IESR_I5_SHIFT (0x00000005u) +#define EDMA3_CCRL_IESR_I5_RESETVAL (0x00000000u) + +/*----I5 Tokens----*/ +#define EDMA3_CCRL_IESR_I5_SET (0x00000001u) + +#define EDMA3_CCRL_IESR_I4_MASK (0x00000010u) +#define EDMA3_CCRL_IESR_I4_SHIFT (0x00000004u) +#define EDMA3_CCRL_IESR_I4_RESETVAL (0x00000000u) + +/*----I4 Tokens----*/ +#define EDMA3_CCRL_IESR_I4_SET (0x00000001u) + +#define EDMA3_CCRL_IESR_I3_MASK (0x00000008u) +#define EDMA3_CCRL_IESR_I3_SHIFT (0x00000003u) +#define EDMA3_CCRL_IESR_I3_RESETVAL (0x00000000u) + +/*----I3 Tokens----*/ +#define EDMA3_CCRL_IESR_I3_SET (0x00000001u) + +#define EDMA3_CCRL_IESR_I2_MASK (0x00000004u) +#define EDMA3_CCRL_IESR_I2_SHIFT (0x00000002u) +#define EDMA3_CCRL_IESR_I2_RESETVAL (0x00000000u) + +/*----I2 Tokens----*/ +#define EDMA3_CCRL_IESR_I2_SET (0x00000001u) + +#define EDMA3_CCRL_IESR_I1_MASK (0x00000002u) +#define EDMA3_CCRL_IESR_I1_SHIFT (0x00000001u) +#define EDMA3_CCRL_IESR_I1_RESETVAL (0x00000000u) + +/*----I1 Tokens----*/ +#define EDMA3_CCRL_IESR_I1_SET (0x00000001u) + +#define EDMA3_CCRL_IESR_I0_MASK (0x00000001u) +#define EDMA3_CCRL_IESR_I0_SHIFT (0x00000000u) +#define EDMA3_CCRL_IESR_I0_RESETVAL (0x00000000u) + +/*----I0 Tokens----*/ +#define EDMA3_CCRL_IESR_I0_SET (0x00000001u) + +#define EDMA3_CCRL_IESR_RESETVAL (0x00000000u) + +/* IESRH */ + +#define EDMA3_CCRL_IESRH_I63_MASK (0x80000000u) +#define EDMA3_CCRL_IESRH_I63_SHIFT (0x0000001Fu) +#define EDMA3_CCRL_IESRH_I63_RESETVAL (0x00000000u) + +/*----I63 Tokens----*/ +#define EDMA3_CCRL_IESRH_I63_SET (0x00000001u) + +#define EDMA3_CCRL_IESRH_I62_MASK (0x40000000u) +#define EDMA3_CCRL_IESRH_I62_SHIFT (0x0000001Eu) +#define EDMA3_CCRL_IESRH_I62_RESETVAL (0x00000000u) + +/*----I62 Tokens----*/ +#define EDMA3_CCRL_IESRH_I62_SET (0x00000001u) + +#define EDMA3_CCRL_IESRH_I61_MASK (0x20000000u) +#define EDMA3_CCRL_IESRH_I61_SHIFT (0x0000001Du) +#define EDMA3_CCRL_IESRH_I61_RESETVAL (0x00000000u) + +/*----I61 Tokens----*/ +#define EDMA3_CCRL_IESRH_I61_SET (0x00000001u) + +#define EDMA3_CCRL_IESRH_I60_MASK (0x10000000u) +#define EDMA3_CCRL_IESRH_I60_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_IESRH_I60_RESETVAL (0x00000000u) + +/*----I60 Tokens----*/ +#define EDMA3_CCRL_IESRH_I60_SET (0x00000001u) + +#define EDMA3_CCRL_IESRH_I59_MASK (0x08000000u) +#define EDMA3_CCRL_IESRH_I59_SHIFT (0x0000001Bu) +#define EDMA3_CCRL_IESRH_I59_RESETVAL (0x00000000u) + +/*----I59 Tokens----*/ +#define EDMA3_CCRL_IESRH_I59_SET (0x00000001u) + +#define EDMA3_CCRL_IESRH_I58_MASK (0x04000000u) +#define EDMA3_CCRL_IESRH_I58_SHIFT (0x0000001Au) +#define EDMA3_CCRL_IESRH_I58_RESETVAL (0x00000000u) + +/*----I58 Tokens----*/ +#define EDMA3_CCRL_IESRH_I58_SET (0x00000001u) + +#define EDMA3_CCRL_IESRH_I57_MASK (0x02000000u) +#define EDMA3_CCRL_IESRH_I57_SHIFT (0x00000019u) +#define EDMA3_CCRL_IESRH_I57_RESETVAL (0x00000000u) + +/*----I57 Tokens----*/ +#define EDMA3_CCRL_IESRH_I57_SET (0x00000001u) + +#define EDMA3_CCRL_IESRH_I56_MASK (0x01000000u) +#define EDMA3_CCRL_IESRH_I56_SHIFT (0x00000018u) +#define EDMA3_CCRL_IESRH_I56_RESETVAL (0x00000000u) + +/*----I56 Tokens----*/ +#define EDMA3_CCRL_IESRH_I56_SET (0x00000001u) + +#define EDMA3_CCRL_IESRH_I55_MASK (0x00800000u) +#define EDMA3_CCRL_IESRH_I55_SHIFT (0x00000017u) +#define EDMA3_CCRL_IESRH_I55_RESETVAL (0x00000000u) + +/*----I55 Tokens----*/ +#define EDMA3_CCRL_IESRH_I55_SET (0x00000001u) + +#define EDMA3_CCRL_IESRH_I54_MASK (0x00400000u) +#define EDMA3_CCRL_IESRH_I54_SHIFT (0x00000016u) +#define EDMA3_CCRL_IESRH_I54_RESETVAL (0x00000000u) + +/*----I54 Tokens----*/ +#define EDMA3_CCRL_IESRH_I54_SET (0x00000001u) + +#define EDMA3_CCRL_IESRH_I53_MASK (0x00200000u) +#define EDMA3_CCRL_IESRH_I53_SHIFT (0x00000015u) +#define EDMA3_CCRL_IESRH_I53_RESETVAL (0x00000000u) + +/*----I53 Tokens----*/ +#define EDMA3_CCRL_IESRH_I53_SET (0x00000001u) + +#define EDMA3_CCRL_IESRH_I52_MASK (0x00100000u) +#define EDMA3_CCRL_IESRH_I52_SHIFT (0x00000014u) +#define EDMA3_CCRL_IESRH_I52_RESETVAL (0x00000000u) + +/*----I52 Tokens----*/ +#define EDMA3_CCRL_IESRH_I52_SET (0x00000001u) + +#define EDMA3_CCRL_IESRH_I51_MASK (0x00080000u) +#define EDMA3_CCRL_IESRH_I51_SHIFT (0x00000013u) +#define EDMA3_CCRL_IESRH_I51_RESETVAL (0x00000000u) + +/*----I51 Tokens----*/ +#define EDMA3_CCRL_IESRH_I51_SET (0x00000001u) + +#define EDMA3_CCRL_IESRH_I50_MASK (0x00040000u) +#define EDMA3_CCRL_IESRH_I50_SHIFT (0x00000012u) +#define EDMA3_CCRL_IESRH_I50_RESETVAL (0x00000000u) + +/*----I50 Tokens----*/ +#define EDMA3_CCRL_IESRH_I50_SET (0x00000001u) + +#define EDMA3_CCRL_IESRH_I49_MASK (0x00020000u) +#define EDMA3_CCRL_IESRH_I49_SHIFT (0x00000011u) +#define EDMA3_CCRL_IESRH_I49_RESETVAL (0x00000000u) + +/*----I49 Tokens----*/ +#define EDMA3_CCRL_IESRH_I49_SET (0x00000001u) + +#define EDMA3_CCRL_IESRH_I48_MASK (0x00010000u) +#define EDMA3_CCRL_IESRH_I48_SHIFT (0x00000010u) +#define EDMA3_CCRL_IESRH_I48_RESETVAL (0x00000000u) + +/*----I48 Tokens----*/ +#define EDMA3_CCRL_IESRH_I48_SET (0x00000001u) + +#define EDMA3_CCRL_IESRH_I47_MASK (0x00008000u) +#define EDMA3_CCRL_IESRH_I47_SHIFT (0x0000000Fu) +#define EDMA3_CCRL_IESRH_I47_RESETVAL (0x00000000u) + +/*----I47 Tokens----*/ +#define EDMA3_CCRL_IESRH_I47_SET (0x00000001u) + +#define EDMA3_CCRL_IESRH_I46_MASK (0x00004000u) +#define EDMA3_CCRL_IESRH_I46_SHIFT (0x0000000Eu) +#define EDMA3_CCRL_IESRH_I46_RESETVAL (0x00000000u) + +/*----I46 Tokens----*/ +#define EDMA3_CCRL_IESRH_I46_SET (0x00000001u) + +#define EDMA3_CCRL_IESRH_I45_MASK (0x00002000u) +#define EDMA3_CCRL_IESRH_I45_SHIFT (0x0000000Du) +#define EDMA3_CCRL_IESRH_I45_RESETVAL (0x00000000u) + +/*----I45 Tokens----*/ +#define EDMA3_CCRL_IESRH_I45_SET (0x00000001u) + +#define EDMA3_CCRL_IESRH_I44_MASK (0x00001000u) +#define EDMA3_CCRL_IESRH_I44_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_IESRH_I44_RESETVAL (0x00000000u) + +/*----I44 Tokens----*/ +#define EDMA3_CCRL_IESRH_I44_SET (0x00000001u) + +#define EDMA3_CCRL_IESRH_I43_MASK (0x00000800u) +#define EDMA3_CCRL_IESRH_I43_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_IESRH_I43_RESETVAL (0x00000000u) + +/*----I43 Tokens----*/ +#define EDMA3_CCRL_IESRH_I43_SET (0x00000001u) + +#define EDMA3_CCRL_IESRH_I42_MASK (0x00000400u) +#define EDMA3_CCRL_IESRH_I42_SHIFT (0x0000000Au) +#define EDMA3_CCRL_IESRH_I42_RESETVAL (0x00000000u) + +/*----I42 Tokens----*/ +#define EDMA3_CCRL_IESRH_I42_SET (0x00000001u) + +#define EDMA3_CCRL_IESRH_I41_MASK (0x00000200u) +#define EDMA3_CCRL_IESRH_I41_SHIFT (0x00000009u) +#define EDMA3_CCRL_IESRH_I41_RESETVAL (0x00000000u) + +/*----I41 Tokens----*/ +#define EDMA3_CCRL_IESRH_I41_SET (0x00000001u) + +#define EDMA3_CCRL_IESRH_I40_MASK (0x00000100u) +#define EDMA3_CCRL_IESRH_I40_SHIFT (0x00000008u) +#define EDMA3_CCRL_IESRH_I40_RESETVAL (0x00000000u) + +/*----I40 Tokens----*/ +#define EDMA3_CCRL_IESRH_I40_SET (0x00000001u) + +#define EDMA3_CCRL_IESRH_I39_MASK (0x00000080u) +#define EDMA3_CCRL_IESRH_I39_SHIFT (0x00000007u) +#define EDMA3_CCRL_IESRH_I39_RESETVAL (0x00000000u) + +/*----I39 Tokens----*/ +#define EDMA3_CCRL_IESRH_I39_SET (0x00000001u) + +#define EDMA3_CCRL_IESRH_I38_MASK (0x00000040u) +#define EDMA3_CCRL_IESRH_I38_SHIFT (0x00000006u) +#define EDMA3_CCRL_IESRH_I38_RESETVAL (0x00000000u) + +/*----I38 Tokens----*/ +#define EDMA3_CCRL_IESRH_I38_SET (0x00000001u) + +#define EDMA3_CCRL_IESRH_I37_MASK (0x00000020u) +#define EDMA3_CCRL_IESRH_I37_SHIFT (0x00000005u) +#define EDMA3_CCRL_IESRH_I37_RESETVAL (0x00000000u) + +/*----I37 Tokens----*/ +#define EDMA3_CCRL_IESRH_I37_SET (0x00000001u) + +#define EDMA3_CCRL_IESRH_I36_MASK (0x00000010u) +#define EDMA3_CCRL_IESRH_I36_SHIFT (0x00000004u) +#define EDMA3_CCRL_IESRH_I36_RESETVAL (0x00000000u) + +/*----I36 Tokens----*/ +#define EDMA3_CCRL_IESRH_I36_SET (0x00000001u) + +#define EDMA3_CCRL_IESRH_I35_MASK (0x00000008u) +#define EDMA3_CCRL_IESRH_I35_SHIFT (0x00000003u) +#define EDMA3_CCRL_IESRH_I35_RESETVAL (0x00000000u) + +/*----I35 Tokens----*/ +#define EDMA3_CCRL_IESRH_I35_SET (0x00000001u) + +#define EDMA3_CCRL_IESRH_I34_MASK (0x00000004u) +#define EDMA3_CCRL_IESRH_I34_SHIFT (0x00000002u) +#define EDMA3_CCRL_IESRH_I34_RESETVAL (0x00000000u) + +/*----I34 Tokens----*/ +#define EDMA3_CCRL_IESRH_I34_SET (0x00000001u) + +#define EDMA3_CCRL_IESRH_I33_MASK (0x00000002u) +#define EDMA3_CCRL_IESRH_I33_SHIFT (0x00000001u) +#define EDMA3_CCRL_IESRH_I33_RESETVAL (0x00000000u) + +/*----I33 Tokens----*/ +#define EDMA3_CCRL_IESRH_I33_SET (0x00000001u) + +#define EDMA3_CCRL_IESRH_I32_MASK (0x00000001u) +#define EDMA3_CCRL_IESRH_I32_SHIFT (0x00000000u) +#define EDMA3_CCRL_IESRH_I32_RESETVAL (0x00000000u) + +/*----I32 Tokens----*/ +#define EDMA3_CCRL_IESRH_I32_SET (0x00000001u) + +#define EDMA3_CCRL_IESRH_RESETVAL (0x00000000u) + +/* IPR */ + +#define EDMA3_CCRL_IPR_I31_MASK (0x80000000u) +#define EDMA3_CCRL_IPR_I31_SHIFT (0x0000001Fu) +#define EDMA3_CCRL_IPR_I31_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPR_I30_MASK (0x40000000u) +#define EDMA3_CCRL_IPR_I30_SHIFT (0x0000001Eu) +#define EDMA3_CCRL_IPR_I30_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPR_I29_MASK (0x20000000u) +#define EDMA3_CCRL_IPR_I29_SHIFT (0x0000001Du) +#define EDMA3_CCRL_IPR_I29_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPR_I28_MASK (0x10000000u) +#define EDMA3_CCRL_IPR_I28_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_IPR_I28_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPR_I27_MASK (0x08000000u) +#define EDMA3_CCRL_IPR_I27_SHIFT (0x0000001Bu) +#define EDMA3_CCRL_IPR_I27_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPR_I26_MASK (0x04000000u) +#define EDMA3_CCRL_IPR_I26_SHIFT (0x0000001Au) +#define EDMA3_CCRL_IPR_I26_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPR_I25_MASK (0x02000000u) +#define EDMA3_CCRL_IPR_I25_SHIFT (0x00000019u) +#define EDMA3_CCRL_IPR_I25_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPR_I24_MASK (0x01000000u) +#define EDMA3_CCRL_IPR_I24_SHIFT (0x00000018u) +#define EDMA3_CCRL_IPR_I24_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPR_I23_MASK (0x00800000u) +#define EDMA3_CCRL_IPR_I23_SHIFT (0x00000017u) +#define EDMA3_CCRL_IPR_I23_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPR_I22_MASK (0x00400000u) +#define EDMA3_CCRL_IPR_I22_SHIFT (0x00000016u) +#define EDMA3_CCRL_IPR_I22_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPR_I21_MASK (0x00200000u) +#define EDMA3_CCRL_IPR_I21_SHIFT (0x00000015u) +#define EDMA3_CCRL_IPR_I21_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPR_I20_MASK (0x00100000u) +#define EDMA3_CCRL_IPR_I20_SHIFT (0x00000014u) +#define EDMA3_CCRL_IPR_I20_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPR_I19_MASK (0x00080000u) +#define EDMA3_CCRL_IPR_I19_SHIFT (0x00000013u) +#define EDMA3_CCRL_IPR_I19_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPR_I18_MASK (0x00040000u) +#define EDMA3_CCRL_IPR_I18_SHIFT (0x00000012u) +#define EDMA3_CCRL_IPR_I18_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPR_I17_MASK (0x00020000u) +#define EDMA3_CCRL_IPR_I17_SHIFT (0x00000011u) +#define EDMA3_CCRL_IPR_I17_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPR_I16_MASK (0x00010000u) +#define EDMA3_CCRL_IPR_I16_SHIFT (0x00000010u) +#define EDMA3_CCRL_IPR_I16_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPR_I15_MASK (0x00008000u) +#define EDMA3_CCRL_IPR_I15_SHIFT (0x0000000Fu) +#define EDMA3_CCRL_IPR_I15_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPR_I14_MASK (0x00004000u) +#define EDMA3_CCRL_IPR_I14_SHIFT (0x0000000Eu) +#define EDMA3_CCRL_IPR_I14_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPR_I13_MASK (0x00002000u) +#define EDMA3_CCRL_IPR_I13_SHIFT (0x0000000Du) +#define EDMA3_CCRL_IPR_I13_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPR_I12_MASK (0x00001000u) +#define EDMA3_CCRL_IPR_I12_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_IPR_I12_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPR_I11_MASK (0x00000800u) +#define EDMA3_CCRL_IPR_I11_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_IPR_I11_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPR_I10_MASK (0x00000400u) +#define EDMA3_CCRL_IPR_I10_SHIFT (0x0000000Au) +#define EDMA3_CCRL_IPR_I10_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPR_I9_MASK (0x00000200u) +#define EDMA3_CCRL_IPR_I9_SHIFT (0x00000009u) +#define EDMA3_CCRL_IPR_I9_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPR_I8_MASK (0x00000100u) +#define EDMA3_CCRL_IPR_I8_SHIFT (0x00000008u) +#define EDMA3_CCRL_IPR_I8_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPR_I7_MASK (0x00000080u) +#define EDMA3_CCRL_IPR_I7_SHIFT (0x00000007u) +#define EDMA3_CCRL_IPR_I7_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPR_I6_MASK (0x00000040u) +#define EDMA3_CCRL_IPR_I6_SHIFT (0x00000006u) +#define EDMA3_CCRL_IPR_I6_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPR_I5_MASK (0x00000020u) +#define EDMA3_CCRL_IPR_I5_SHIFT (0x00000005u) +#define EDMA3_CCRL_IPR_I5_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPR_I4_MASK (0x00000010u) +#define EDMA3_CCRL_IPR_I4_SHIFT (0x00000004u) +#define EDMA3_CCRL_IPR_I4_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPR_I3_MASK (0x00000008u) +#define EDMA3_CCRL_IPR_I3_SHIFT (0x00000003u) +#define EDMA3_CCRL_IPR_I3_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPR_I2_MASK (0x00000004u) +#define EDMA3_CCRL_IPR_I2_SHIFT (0x00000002u) +#define EDMA3_CCRL_IPR_I2_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPR_I1_MASK (0x00000002u) +#define EDMA3_CCRL_IPR_I1_SHIFT (0x00000001u) +#define EDMA3_CCRL_IPR_I1_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPR_I0_MASK (0x00000001u) +#define EDMA3_CCRL_IPR_I0_SHIFT (0x00000000u) +#define EDMA3_CCRL_IPR_I0_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPR_RESETVAL (0x00000000u) + +/* IPRH */ + +#define EDMA3_CCRL_IPRH_I63_MASK (0x80000000u) +#define EDMA3_CCRL_IPRH_I63_SHIFT (0x0000001Fu) +#define EDMA3_CCRL_IPRH_I63_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPRH_I62_MASK (0x40000000u) +#define EDMA3_CCRL_IPRH_I62_SHIFT (0x0000001Eu) +#define EDMA3_CCRL_IPRH_I62_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPRH_I61_MASK (0x20000000u) +#define EDMA3_CCRL_IPRH_I61_SHIFT (0x0000001Du) +#define EDMA3_CCRL_IPRH_I61_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPRH_I60_MASK (0x10000000u) +#define EDMA3_CCRL_IPRH_I60_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_IPRH_I60_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPRH_I59_MASK (0x08000000u) +#define EDMA3_CCRL_IPRH_I59_SHIFT (0x0000001Bu) +#define EDMA3_CCRL_IPRH_I59_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPRH_I58_MASK (0x04000000u) +#define EDMA3_CCRL_IPRH_I58_SHIFT (0x0000001Au) +#define EDMA3_CCRL_IPRH_I58_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPRH_I57_MASK (0x02000000u) +#define EDMA3_CCRL_IPRH_I57_SHIFT (0x00000019u) +#define EDMA3_CCRL_IPRH_I57_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPRH_I56_MASK (0x01000000u) +#define EDMA3_CCRL_IPRH_I56_SHIFT (0x00000018u) +#define EDMA3_CCRL_IPRH_I56_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPRH_I55_MASK (0x00800000u) +#define EDMA3_CCRL_IPRH_I55_SHIFT (0x00000017u) +#define EDMA3_CCRL_IPRH_I55_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPRH_I54_MASK (0x00400000u) +#define EDMA3_CCRL_IPRH_I54_SHIFT (0x00000016u) +#define EDMA3_CCRL_IPRH_I54_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPRH_I53_MASK (0x00200000u) +#define EDMA3_CCRL_IPRH_I53_SHIFT (0x00000015u) +#define EDMA3_CCRL_IPRH_I53_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPRH_I52_MASK (0x00100000u) +#define EDMA3_CCRL_IPRH_I52_SHIFT (0x00000014u) +#define EDMA3_CCRL_IPRH_I52_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPRH_I51_MASK (0x00080000u) +#define EDMA3_CCRL_IPRH_I51_SHIFT (0x00000013u) +#define EDMA3_CCRL_IPRH_I51_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPRH_I50_MASK (0x00040000u) +#define EDMA3_CCRL_IPRH_I50_SHIFT (0x00000012u) +#define EDMA3_CCRL_IPRH_I50_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPRH_I49_MASK (0x00020000u) +#define EDMA3_CCRL_IPRH_I49_SHIFT (0x00000011u) +#define EDMA3_CCRL_IPRH_I49_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPRH_I48_MASK (0x00010000u) +#define EDMA3_CCRL_IPRH_I48_SHIFT (0x00000010u) +#define EDMA3_CCRL_IPRH_I48_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPRH_I47_MASK (0x00008000u) +#define EDMA3_CCRL_IPRH_I47_SHIFT (0x0000000Fu) +#define EDMA3_CCRL_IPRH_I47_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPRH_I46_MASK (0x00004000u) +#define EDMA3_CCRL_IPRH_I46_SHIFT (0x0000000Eu) +#define EDMA3_CCRL_IPRH_I46_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPRH_I45_MASK (0x00002000u) +#define EDMA3_CCRL_IPRH_I45_SHIFT (0x0000000Du) +#define EDMA3_CCRL_IPRH_I45_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPRH_I44_MASK (0x00001000u) +#define EDMA3_CCRL_IPRH_I44_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_IPRH_I44_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPRH_I43_MASK (0x00000800u) +#define EDMA3_CCRL_IPRH_I43_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_IPRH_I43_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPRH_I42_MASK (0x00000400u) +#define EDMA3_CCRL_IPRH_I42_SHIFT (0x0000000Au) +#define EDMA3_CCRL_IPRH_I42_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPRH_I41_MASK (0x00000200u) +#define EDMA3_CCRL_IPRH_I41_SHIFT (0x00000009u) +#define EDMA3_CCRL_IPRH_I41_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPRH_I40_MASK (0x00000100u) +#define EDMA3_CCRL_IPRH_I40_SHIFT (0x00000008u) +#define EDMA3_CCRL_IPRH_I40_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPRH_I39_MASK (0x00000080u) +#define EDMA3_CCRL_IPRH_I39_SHIFT (0x00000007u) +#define EDMA3_CCRL_IPRH_I39_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPRH_I38_MASK (0x00000040u) +#define EDMA3_CCRL_IPRH_I38_SHIFT (0x00000006u) +#define EDMA3_CCRL_IPRH_I38_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPRH_I37_MASK (0x00000020u) +#define EDMA3_CCRL_IPRH_I37_SHIFT (0x00000005u) +#define EDMA3_CCRL_IPRH_I37_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPRH_I36_MASK (0x00000010u) +#define EDMA3_CCRL_IPRH_I36_SHIFT (0x00000004u) +#define EDMA3_CCRL_IPRH_I36_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPRH_I35_MASK (0x00000008u) +#define EDMA3_CCRL_IPRH_I35_SHIFT (0x00000003u) +#define EDMA3_CCRL_IPRH_I35_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPRH_I34_MASK (0x00000004u) +#define EDMA3_CCRL_IPRH_I34_SHIFT (0x00000002u) +#define EDMA3_CCRL_IPRH_I34_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPRH_I33_MASK (0x00000002u) +#define EDMA3_CCRL_IPRH_I33_SHIFT (0x00000001u) +#define EDMA3_CCRL_IPRH_I33_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPRH_I32_MASK (0x00000001u) +#define EDMA3_CCRL_IPRH_I32_SHIFT (0x00000000u) +#define EDMA3_CCRL_IPRH_I32_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPRH_RESETVAL (0x00000000u) + +/* ICR */ + +#define EDMA3_CCRL_ICR_I31_MASK (0x80000000u) +#define EDMA3_CCRL_ICR_I31_SHIFT (0x0000001Fu) +#define EDMA3_CCRL_ICR_I31_RESETVAL (0x00000000u) + +/*----I31 Tokens----*/ +#define EDMA3_CCRL_ICR_I31_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICR_I30_MASK (0x40000000u) +#define EDMA3_CCRL_ICR_I30_SHIFT (0x0000001Eu) +#define EDMA3_CCRL_ICR_I30_RESETVAL (0x00000000u) + +/*----I30 Tokens----*/ +#define EDMA3_CCRL_ICR_I30_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICR_I29_MASK (0x20000000u) +#define EDMA3_CCRL_ICR_I29_SHIFT (0x0000001Du) +#define EDMA3_CCRL_ICR_I29_RESETVAL (0x00000000u) + +/*----I29 Tokens----*/ +#define EDMA3_CCRL_ICR_I29_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICR_I28_MASK (0x10000000u) +#define EDMA3_CCRL_ICR_I28_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_ICR_I28_RESETVAL (0x00000000u) + +/*----I28 Tokens----*/ +#define EDMA3_CCRL_ICR_I28_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICR_I27_MASK (0x08000000u) +#define EDMA3_CCRL_ICR_I27_SHIFT (0x0000001Bu) +#define EDMA3_CCRL_ICR_I27_RESETVAL (0x00000000u) + +/*----I27 Tokens----*/ +#define EDMA3_CCRL_ICR_I27_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICR_I26_MASK (0x04000000u) +#define EDMA3_CCRL_ICR_I26_SHIFT (0x0000001Au) +#define EDMA3_CCRL_ICR_I26_RESETVAL (0x00000000u) + +/*----I26 Tokens----*/ +#define EDMA3_CCRL_ICR_I26_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICR_I25_MASK (0x02000000u) +#define EDMA3_CCRL_ICR_I25_SHIFT (0x00000019u) +#define EDMA3_CCRL_ICR_I25_RESETVAL (0x00000000u) + +/*----I25 Tokens----*/ +#define EDMA3_CCRL_ICR_I25_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICR_I24_MASK (0x01000000u) +#define EDMA3_CCRL_ICR_I24_SHIFT (0x00000018u) +#define EDMA3_CCRL_ICR_I24_RESETVAL (0x00000000u) + +/*----I24 Tokens----*/ +#define EDMA3_CCRL_ICR_I24_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICR_I23_MASK (0x00800000u) +#define EDMA3_CCRL_ICR_I23_SHIFT (0x00000017u) +#define EDMA3_CCRL_ICR_I23_RESETVAL (0x00000000u) + +/*----I23 Tokens----*/ +#define EDMA3_CCRL_ICR_I23_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICR_I22_MASK (0x00400000u) +#define EDMA3_CCRL_ICR_I22_SHIFT (0x00000016u) +#define EDMA3_CCRL_ICR_I22_RESETVAL (0x00000000u) + +/*----I22 Tokens----*/ +#define EDMA3_CCRL_ICR_I22_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICR_I21_MASK (0x00200000u) +#define EDMA3_CCRL_ICR_I21_SHIFT (0x00000015u) +#define EDMA3_CCRL_ICR_I21_RESETVAL (0x00000000u) + +/*----I21 Tokens----*/ +#define EDMA3_CCRL_ICR_I21_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICR_I20_MASK (0x00100000u) +#define EDMA3_CCRL_ICR_I20_SHIFT (0x00000014u) +#define EDMA3_CCRL_ICR_I20_RESETVAL (0x00000000u) + +/*----I20 Tokens----*/ +#define EDMA3_CCRL_ICR_I20_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICR_I19_MASK (0x00080000u) +#define EDMA3_CCRL_ICR_I19_SHIFT (0x00000013u) +#define EDMA3_CCRL_ICR_I19_RESETVAL (0x00000000u) + +/*----I19 Tokens----*/ +#define EDMA3_CCRL_ICR_I19_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICR_I18_MASK (0x00040000u) +#define EDMA3_CCRL_ICR_I18_SHIFT (0x00000012u) +#define EDMA3_CCRL_ICR_I18_RESETVAL (0x00000000u) + +/*----I18 Tokens----*/ +#define EDMA3_CCRL_ICR_I18_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICR_I17_MASK (0x00020000u) +#define EDMA3_CCRL_ICR_I17_SHIFT (0x00000011u) +#define EDMA3_CCRL_ICR_I17_RESETVAL (0x00000000u) + +/*----I17 Tokens----*/ +#define EDMA3_CCRL_ICR_I17_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICR_I16_MASK (0x00010000u) +#define EDMA3_CCRL_ICR_I16_SHIFT (0x00000010u) +#define EDMA3_CCRL_ICR_I16_RESETVAL (0x00000000u) + +/*----I16 Tokens----*/ +#define EDMA3_CCRL_ICR_I16_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICR_I15_MASK (0x00008000u) +#define EDMA3_CCRL_ICR_I15_SHIFT (0x0000000Fu) +#define EDMA3_CCRL_ICR_I15_RESETVAL (0x00000000u) + +/*----I15 Tokens----*/ +#define EDMA3_CCRL_ICR_I15_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICR_I14_MASK (0x00004000u) +#define EDMA3_CCRL_ICR_I14_SHIFT (0x0000000Eu) +#define EDMA3_CCRL_ICR_I14_RESETVAL (0x00000000u) + +/*----I14 Tokens----*/ +#define EDMA3_CCRL_ICR_I14_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICR_I13_MASK (0x00002000u) +#define EDMA3_CCRL_ICR_I13_SHIFT (0x0000000Du) +#define EDMA3_CCRL_ICR_I13_RESETVAL (0x00000000u) + +/*----I13 Tokens----*/ +#define EDMA3_CCRL_ICR_I13_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICR_I12_MASK (0x00001000u) +#define EDMA3_CCRL_ICR_I12_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_ICR_I12_RESETVAL (0x00000000u) + +/*----I12 Tokens----*/ +#define EDMA3_CCRL_ICR_I12_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICR_I11_MASK (0x00000800u) +#define EDMA3_CCRL_ICR_I11_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_ICR_I11_RESETVAL (0x00000000u) + +/*----I11 Tokens----*/ +#define EDMA3_CCRL_ICR_I11_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICR_I10_MASK (0x00000400u) +#define EDMA3_CCRL_ICR_I10_SHIFT (0x0000000Au) +#define EDMA3_CCRL_ICR_I10_RESETVAL (0x00000000u) + +/*----I10 Tokens----*/ +#define EDMA3_CCRL_ICR_I10_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICR_I9_MASK (0x00000200u) +#define EDMA3_CCRL_ICR_I9_SHIFT (0x00000009u) +#define EDMA3_CCRL_ICR_I9_RESETVAL (0x00000000u) + +/*----I9 Tokens----*/ +#define EDMA3_CCRL_ICR_I9_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICR_I8_MASK (0x00000100u) +#define EDMA3_CCRL_ICR_I8_SHIFT (0x00000008u) +#define EDMA3_CCRL_ICR_I8_RESETVAL (0x00000000u) + +/*----I8 Tokens----*/ +#define EDMA3_CCRL_ICR_I8_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICR_I7_MASK (0x00000080u) +#define EDMA3_CCRL_ICR_I7_SHIFT (0x00000007u) +#define EDMA3_CCRL_ICR_I7_RESETVAL (0x00000000u) + +/*----I7 Tokens----*/ +#define EDMA3_CCRL_ICR_I7_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICR_I6_MASK (0x00000040u) +#define EDMA3_CCRL_ICR_I6_SHIFT (0x00000006u) +#define EDMA3_CCRL_ICR_I6_RESETVAL (0x00000000u) + +/*----I6 Tokens----*/ +#define EDMA3_CCRL_ICR_I6_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICR_I5_MASK (0x00000020u) +#define EDMA3_CCRL_ICR_I5_SHIFT (0x00000005u) +#define EDMA3_CCRL_ICR_I5_RESETVAL (0x00000000u) + +/*----I5 Tokens----*/ +#define EDMA3_CCRL_ICR_I5_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICR_I4_MASK (0x00000010u) +#define EDMA3_CCRL_ICR_I4_SHIFT (0x00000004u) +#define EDMA3_CCRL_ICR_I4_RESETVAL (0x00000000u) + +/*----I4 Tokens----*/ +#define EDMA3_CCRL_ICR_I4_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICR_I3_MASK (0x00000008u) +#define EDMA3_CCRL_ICR_I3_SHIFT (0x00000003u) +#define EDMA3_CCRL_ICR_I3_RESETVAL (0x00000000u) + +/*----I3 Tokens----*/ +#define EDMA3_CCRL_ICR_I3_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICR_I2_MASK (0x00000004u) +#define EDMA3_CCRL_ICR_I2_SHIFT (0x00000002u) +#define EDMA3_CCRL_ICR_I2_RESETVAL (0x00000000u) + +/*----I2 Tokens----*/ +#define EDMA3_CCRL_ICR_I2_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICR_I1_MASK (0x00000002u) +#define EDMA3_CCRL_ICR_I1_SHIFT (0x00000001u) +#define EDMA3_CCRL_ICR_I1_RESETVAL (0x00000000u) + +/*----I1 Tokens----*/ +#define EDMA3_CCRL_ICR_I1_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICR_I0_MASK (0x00000001u) +#define EDMA3_CCRL_ICR_I0_SHIFT (0x00000000u) +#define EDMA3_CCRL_ICR_I0_RESETVAL (0x00000000u) + +/*----I0 Tokens----*/ +#define EDMA3_CCRL_ICR_I0_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICR_RESETVAL (0x00000000u) + +/* ICRH */ + +#define EDMA3_CCRL_ICRH_I63_MASK (0x80000000u) +#define EDMA3_CCRL_ICRH_I63_SHIFT (0x0000001Fu) +#define EDMA3_CCRL_ICRH_I63_RESETVAL (0x00000000u) + +/*----I63 Tokens----*/ +#define EDMA3_CCRL_ICRH_I63_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICRH_I62_MASK (0x40000000u) +#define EDMA3_CCRL_ICRH_I62_SHIFT (0x0000001Eu) +#define EDMA3_CCRL_ICRH_I62_RESETVAL (0x00000000u) + +/*----I62 Tokens----*/ +#define EDMA3_CCRL_ICRH_I62_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICRH_I61_MASK (0x20000000u) +#define EDMA3_CCRL_ICRH_I61_SHIFT (0x0000001Du) +#define EDMA3_CCRL_ICRH_I61_RESETVAL (0x00000000u) + +/*----I61 Tokens----*/ +#define EDMA3_CCRL_ICRH_I61_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICRH_I60_MASK (0x10000000u) +#define EDMA3_CCRL_ICRH_I60_SHIFT (0x0000001Cu) +#define EDMA3_CCRL_ICRH_I60_RESETVAL (0x00000000u) + +/*----I60 Tokens----*/ +#define EDMA3_CCRL_ICRH_I60_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICRH_I59_MASK (0x08000000u) +#define EDMA3_CCRL_ICRH_I59_SHIFT (0x0000001Bu) +#define EDMA3_CCRL_ICRH_I59_RESETVAL (0x00000000u) + +/*----I59 Tokens----*/ +#define EDMA3_CCRL_ICRH_I59_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICRH_I58_MASK (0x04000000u) +#define EDMA3_CCRL_ICRH_I58_SHIFT (0x0000001Au) +#define EDMA3_CCRL_ICRH_I58_RESETVAL (0x00000000u) + +/*----I58 Tokens----*/ +#define EDMA3_CCRL_ICRH_I58_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICRH_I57_MASK (0x02000000u) +#define EDMA3_CCRL_ICRH_I57_SHIFT (0x00000019u) +#define EDMA3_CCRL_ICRH_I57_RESETVAL (0x00000000u) + +/*----I57 Tokens----*/ +#define EDMA3_CCRL_ICRH_I57_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICRH_I56_MASK (0x01000000u) +#define EDMA3_CCRL_ICRH_I56_SHIFT (0x00000018u) +#define EDMA3_CCRL_ICRH_I56_RESETVAL (0x00000000u) + +/*----I56 Tokens----*/ +#define EDMA3_CCRL_ICRH_I56_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICRH_I55_MASK (0x00800000u) +#define EDMA3_CCRL_ICRH_I55_SHIFT (0x00000017u) +#define EDMA3_CCRL_ICRH_I55_RESETVAL (0x00000000u) + +/*----I55 Tokens----*/ +#define EDMA3_CCRL_ICRH_I55_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICRH_I54_MASK (0x00400000u) +#define EDMA3_CCRL_ICRH_I54_SHIFT (0x00000016u) +#define EDMA3_CCRL_ICRH_I54_RESETVAL (0x00000000u) + +/*----I54 Tokens----*/ +#define EDMA3_CCRL_ICRH_I54_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICRH_I53_MASK (0x00200000u) +#define EDMA3_CCRL_ICRH_I53_SHIFT (0x00000015u) +#define EDMA3_CCRL_ICRH_I53_RESETVAL (0x00000000u) + +/*----I53 Tokens----*/ +#define EDMA3_CCRL_ICRH_I53_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICRH_I52_MASK (0x00100000u) +#define EDMA3_CCRL_ICRH_I52_SHIFT (0x00000014u) +#define EDMA3_CCRL_ICRH_I52_RESETVAL (0x00000000u) + +/*----I52 Tokens----*/ +#define EDMA3_CCRL_ICRH_I52_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICRH_I51_MASK (0x00080000u) +#define EDMA3_CCRL_ICRH_I51_SHIFT (0x00000013u) +#define EDMA3_CCRL_ICRH_I51_RESETVAL (0x00000000u) + +/*----I51 Tokens----*/ +#define EDMA3_CCRL_ICRH_I51_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICRH_I50_MASK (0x00040000u) +#define EDMA3_CCRL_ICRH_I50_SHIFT (0x00000012u) +#define EDMA3_CCRL_ICRH_I50_RESETVAL (0x00000000u) + +/*----I50 Tokens----*/ +#define EDMA3_CCRL_ICRH_I50_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICRH_I49_MASK (0x00020000u) +#define EDMA3_CCRL_ICRH_I49_SHIFT (0x00000011u) +#define EDMA3_CCRL_ICRH_I49_RESETVAL (0x00000000u) + +/*----I49 Tokens----*/ +#define EDMA3_CCRL_ICRH_I49_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICRH_I48_MASK (0x00010000u) +#define EDMA3_CCRL_ICRH_I48_SHIFT (0x00000010u) +#define EDMA3_CCRL_ICRH_I48_RESETVAL (0x00000000u) + +/*----I48 Tokens----*/ +#define EDMA3_CCRL_ICRH_I48_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICRH_I47_MASK (0x00008000u) +#define EDMA3_CCRL_ICRH_I47_SHIFT (0x0000000Fu) +#define EDMA3_CCRL_ICRH_I47_RESETVAL (0x00000000u) + +/*----I47 Tokens----*/ +#define EDMA3_CCRL_ICRH_I47_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICRH_I46_MASK (0x00004000u) +#define EDMA3_CCRL_ICRH_I46_SHIFT (0x0000000Eu) +#define EDMA3_CCRL_ICRH_I46_RESETVAL (0x00000000u) + +/*----I46 Tokens----*/ +#define EDMA3_CCRL_ICRH_I46_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICRH_I45_MASK (0x00002000u) +#define EDMA3_CCRL_ICRH_I45_SHIFT (0x0000000Du) +#define EDMA3_CCRL_ICRH_I45_RESETVAL (0x00000000u) + +/*----I45 Tokens----*/ +#define EDMA3_CCRL_ICRH_I45_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICRH_I44_MASK (0x00001000u) +#define EDMA3_CCRL_ICRH_I44_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_ICRH_I44_RESETVAL (0x00000000u) + +/*----I44 Tokens----*/ +#define EDMA3_CCRL_ICRH_I44_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICRH_I43_MASK (0x00000800u) +#define EDMA3_CCRL_ICRH_I43_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_ICRH_I43_RESETVAL (0x00000000u) + +/*----I43 Tokens----*/ +#define EDMA3_CCRL_ICRH_I43_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICRH_I42_MASK (0x00000400u) +#define EDMA3_CCRL_ICRH_I42_SHIFT (0x0000000Au) +#define EDMA3_CCRL_ICRH_I42_RESETVAL (0x00000000u) + +/*----I42 Tokens----*/ +#define EDMA3_CCRL_ICRH_I42_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICRH_I41_MASK (0x00000200u) +#define EDMA3_CCRL_ICRH_I41_SHIFT (0x00000009u) +#define EDMA3_CCRL_ICRH_I41_RESETVAL (0x00000000u) + +/*----I41 Tokens----*/ +#define EDMA3_CCRL_ICRH_I41_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICRH_I40_MASK (0x00000100u) +#define EDMA3_CCRL_ICRH_I40_SHIFT (0x00000008u) +#define EDMA3_CCRL_ICRH_I40_RESETVAL (0x00000000u) + +/*----I40 Tokens----*/ +#define EDMA3_CCRL_ICRH_I40_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICRH_I39_MASK (0x00000080u) +#define EDMA3_CCRL_ICRH_I39_SHIFT (0x00000007u) +#define EDMA3_CCRL_ICRH_I39_RESETVAL (0x00000000u) + +/*----I39 Tokens----*/ +#define EDMA3_CCRL_ICRH_I39_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICRH_I38_MASK (0x00000040u) +#define EDMA3_CCRL_ICRH_I38_SHIFT (0x00000006u) +#define EDMA3_CCRL_ICRH_I38_RESETVAL (0x00000000u) + +/*----I38 Tokens----*/ +#define EDMA3_CCRL_ICRH_I38_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICRH_I37_MASK (0x00000020u) +#define EDMA3_CCRL_ICRH_I37_SHIFT (0x00000005u) +#define EDMA3_CCRL_ICRH_I37_RESETVAL (0x00000000u) + +/*----I37 Tokens----*/ +#define EDMA3_CCRL_ICRH_I37_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICRH_I36_MASK (0x00000010u) +#define EDMA3_CCRL_ICRH_I36_SHIFT (0x00000004u) +#define EDMA3_CCRL_ICRH_I36_RESETVAL (0x00000000u) + +/*----I36 Tokens----*/ +#define EDMA3_CCRL_ICRH_I36_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICRH_I35_MASK (0x00000008u) +#define EDMA3_CCRL_ICRH_I35_SHIFT (0x00000003u) +#define EDMA3_CCRL_ICRH_I35_RESETVAL (0x00000000u) + +/*----I35 Tokens----*/ +#define EDMA3_CCRL_ICRH_I35_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICRH_I34_MASK (0x00000004u) +#define EDMA3_CCRL_ICRH_I34_SHIFT (0x00000002u) +#define EDMA3_CCRL_ICRH_I34_RESETVAL (0x00000000u) + +/*----I34 Tokens----*/ +#define EDMA3_CCRL_ICRH_I34_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICRH_I33_MASK (0x00000002u) +#define EDMA3_CCRL_ICRH_I33_SHIFT (0x00000001u) +#define EDMA3_CCRL_ICRH_I33_RESETVAL (0x00000000u) + +/*----I33 Tokens----*/ +#define EDMA3_CCRL_ICRH_I33_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICRH_I32_MASK (0x00000001u) +#define EDMA3_CCRL_ICRH_I32_SHIFT (0x00000000u) +#define EDMA3_CCRL_ICRH_I32_RESETVAL (0x00000000u) + +/*----I32 Tokens----*/ +#define EDMA3_CCRL_ICRH_I32_CLEAR (0x00000001u) + +#define EDMA3_CCRL_ICRH_RESETVAL (0x00000000u) + +/* IEVAL */ + +#define EDMA3_CCRL_IEVAL_SET_MASK (0x00000002u) +#define EDMA3_CCRL_IEVAL_SET_SHIFT (0x00000001u) +#define EDMA3_CCRL_IEVAL_SET_RESETVAL (0x00000000u) + +/*----SET Tokens----*/ +#define EDMA3_CCRL_IEVAL_SET_SET (0x00000001u) + +#define EDMA3_CCRL_IEVAL_EVAL_MASK (0x00000001u) +#define EDMA3_CCRL_IEVAL_EVAL_SHIFT (0x00000000u) +#define EDMA3_CCRL_IEVAL_EVAL_RESETVAL (0x00000000u) + +/*----EVAL Tokens----*/ +#define EDMA3_CCRL_IEVAL_EVAL_EVAL (0x00000001u) + +#define EDMA3_CCRL_IEVAL_RESETVAL (0x00000000u) + +/* QER */ + +#define EDMA3_CCRL_QER_E7_MASK (0x00000080u) +#define EDMA3_CCRL_QER_E7_SHIFT (0x00000007u) +#define EDMA3_CCRL_QER_E7_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QER_E6_MASK (0x00000040u) +#define EDMA3_CCRL_QER_E6_SHIFT (0x00000006u) +#define EDMA3_CCRL_QER_E6_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QER_E5_MASK (0x00000020u) +#define EDMA3_CCRL_QER_E5_SHIFT (0x00000005u) +#define EDMA3_CCRL_QER_E5_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QER_E4_MASK (0x00000010u) +#define EDMA3_CCRL_QER_E4_SHIFT (0x00000004u) +#define EDMA3_CCRL_QER_E4_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QER_E3_MASK (0x00000008u) +#define EDMA3_CCRL_QER_E3_SHIFT (0x00000003u) +#define EDMA3_CCRL_QER_E3_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QER_E2_MASK (0x00000004u) +#define EDMA3_CCRL_QER_E2_SHIFT (0x00000002u) +#define EDMA3_CCRL_QER_E2_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QER_E1_MASK (0x00000002u) +#define EDMA3_CCRL_QER_E1_SHIFT (0x00000001u) +#define EDMA3_CCRL_QER_E1_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QER_E0_MASK (0x00000001u) +#define EDMA3_CCRL_QER_E0_SHIFT (0x00000000u) +#define EDMA3_CCRL_QER_E0_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QER_RESETVAL (0x00000000u) + +/* QEER */ + +#define EDMA3_CCRL_QEER_E7_MASK (0x00000080u) +#define EDMA3_CCRL_QEER_E7_SHIFT (0x00000007u) +#define EDMA3_CCRL_QEER_E7_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QEER_E6_MASK (0x00000040u) +#define EDMA3_CCRL_QEER_E6_SHIFT (0x00000006u) +#define EDMA3_CCRL_QEER_E6_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QEER_E5_MASK (0x00000020u) +#define EDMA3_CCRL_QEER_E5_SHIFT (0x00000005u) +#define EDMA3_CCRL_QEER_E5_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QEER_E4_MASK (0x00000010u) +#define EDMA3_CCRL_QEER_E4_SHIFT (0x00000004u) +#define EDMA3_CCRL_QEER_E4_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QEER_E3_MASK (0x00000008u) +#define EDMA3_CCRL_QEER_E3_SHIFT (0x00000003u) +#define EDMA3_CCRL_QEER_E3_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QEER_E2_MASK (0x00000004u) +#define EDMA3_CCRL_QEER_E2_SHIFT (0x00000002u) +#define EDMA3_CCRL_QEER_E2_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QEER_E1_MASK (0x00000002u) +#define EDMA3_CCRL_QEER_E1_SHIFT (0x00000001u) +#define EDMA3_CCRL_QEER_E1_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QEER_E0_MASK (0x00000001u) +#define EDMA3_CCRL_QEER_E0_SHIFT (0x00000000u) +#define EDMA3_CCRL_QEER_E0_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QEER_RESETVAL (0x00000000u) + +/* QEECR */ + +#define EDMA3_CCRL_QEECR_E7_MASK (0x00000080u) +#define EDMA3_CCRL_QEECR_E7_SHIFT (0x00000007u) +#define EDMA3_CCRL_QEECR_E7_RESETVAL (0x00000000u) + +/*----E7 Tokens----*/ +#define EDMA3_CCRL_QEECR_E7_CLEAR (0x00000001u) + +#define EDMA3_CCRL_QEECR_E6_MASK (0x00000040u) +#define EDMA3_CCRL_QEECR_E6_SHIFT (0x00000006u) +#define EDMA3_CCRL_QEECR_E6_RESETVAL (0x00000000u) + +/*----E6 Tokens----*/ +#define EDMA3_CCRL_QEECR_E6_CLEAR (0x00000001u) + +#define EDMA3_CCRL_QEECR_E5_MASK (0x00000020u) +#define EDMA3_CCRL_QEECR_E5_SHIFT (0x00000005u) +#define EDMA3_CCRL_QEECR_E5_RESETVAL (0x00000000u) + +/*----E5 Tokens----*/ +#define EDMA3_CCRL_QEECR_E5_CLEAR (0x00000001u) + +#define EDMA3_CCRL_QEECR_E4_MASK (0x00000010u) +#define EDMA3_CCRL_QEECR_E4_SHIFT (0x00000004u) +#define EDMA3_CCRL_QEECR_E4_RESETVAL (0x00000000u) + +/*----E4 Tokens----*/ +#define EDMA3_CCRL_QEECR_E4_CLEAR (0x00000001u) + +#define EDMA3_CCRL_QEECR_E3_MASK (0x00000008u) +#define EDMA3_CCRL_QEECR_E3_SHIFT (0x00000003u) +#define EDMA3_CCRL_QEECR_E3_RESETVAL (0x00000000u) + +/*----E3 Tokens----*/ +#define EDMA3_CCRL_QEECR_E3_CLEAR (0x00000001u) + +#define EDMA3_CCRL_QEECR_E2_MASK (0x00000004u) +#define EDMA3_CCRL_QEECR_E2_SHIFT (0x00000002u) +#define EDMA3_CCRL_QEECR_E2_RESETVAL (0x00000000u) + +/*----E2 Tokens----*/ +#define EDMA3_CCRL_QEECR_E2_CLEAR (0x00000001u) + +#define EDMA3_CCRL_QEECR_E1_MASK (0x00000002u) +#define EDMA3_CCRL_QEECR_E1_SHIFT (0x00000001u) +#define EDMA3_CCRL_QEECR_E1_RESETVAL (0x00000000u) + +/*----E1 Tokens----*/ +#define EDMA3_CCRL_QEECR_E1_CLEAR (0x00000001u) + +#define EDMA3_CCRL_QEECR_E0_MASK (0x00000001u) +#define EDMA3_CCRL_QEECR_E0_SHIFT (0x00000000u) +#define EDMA3_CCRL_QEECR_E0_RESETVAL (0x00000000u) + +/*----E0 Tokens----*/ +#define EDMA3_CCRL_QEECR_E0_CLEAR (0x00000001u) + +#define EDMA3_CCRL_QEECR_RESETVAL (0x00000000u) + +/* QEESR */ + +#define EDMA3_CCRL_QEESR_E7_MASK (0x00000080u) +#define EDMA3_CCRL_QEESR_E7_SHIFT (0x00000007u) +#define EDMA3_CCRL_QEESR_E7_RESETVAL (0x00000000u) + +/*----E7 Tokens----*/ +#define EDMA3_CCRL_QEESR_E7_SET (0x00000001u) + +#define EDMA3_CCRL_QEESR_E6_MASK (0x00000040u) +#define EDMA3_CCRL_QEESR_E6_SHIFT (0x00000006u) +#define EDMA3_CCRL_QEESR_E6_RESETVAL (0x00000000u) + +/*----E6 Tokens----*/ +#define EDMA3_CCRL_QEESR_E6_SET (0x00000001u) + +#define EDMA3_CCRL_QEESR_E5_MASK (0x00000020u) +#define EDMA3_CCRL_QEESR_E5_SHIFT (0x00000005u) +#define EDMA3_CCRL_QEESR_E5_RESETVAL (0x00000000u) + +/*----E5 Tokens----*/ +#define EDMA3_CCRL_QEESR_E5_SET (0x00000001u) + +#define EDMA3_CCRL_QEESR_E4_MASK (0x00000010u) +#define EDMA3_CCRL_QEESR_E4_SHIFT (0x00000004u) +#define EDMA3_CCRL_QEESR_E4_RESETVAL (0x00000000u) + +/*----E4 Tokens----*/ +#define EDMA3_CCRL_QEESR_E4_SET (0x00000001u) + +#define EDMA3_CCRL_QEESR_E3_MASK (0x00000008u) +#define EDMA3_CCRL_QEESR_E3_SHIFT (0x00000003u) +#define EDMA3_CCRL_QEESR_E3_RESETVAL (0x00000000u) + +/*----E3 Tokens----*/ +#define EDMA3_CCRL_QEESR_E3_SET (0x00000001u) + +#define EDMA3_CCRL_QEESR_E2_MASK (0x00000004u) +#define EDMA3_CCRL_QEESR_E2_SHIFT (0x00000002u) +#define EDMA3_CCRL_QEESR_E2_RESETVAL (0x00000000u) + +/*----E2 Tokens----*/ +#define EDMA3_CCRL_QEESR_E2_SET (0x00000001u) + +#define EDMA3_CCRL_QEESR_E1_MASK (0x00000002u) +#define EDMA3_CCRL_QEESR_E1_SHIFT (0x00000001u) +#define EDMA3_CCRL_QEESR_E1_RESETVAL (0x00000000u) + +/*----E1 Tokens----*/ +#define EDMA3_CCRL_QEESR_E1_SET (0x00000001u) + +#define EDMA3_CCRL_QEESR_E0_MASK (0x00000001u) +#define EDMA3_CCRL_QEESR_E0_SHIFT (0x00000000u) +#define EDMA3_CCRL_QEESR_E0_RESETVAL (0x00000000u) + +/*----E0 Tokens----*/ +#define EDMA3_CCRL_QEESR_E0_SET (0x00000001u) + +#define EDMA3_CCRL_QEESR_RESETVAL (0x00000000u) + +/* QSER */ + +#define EDMA3_CCRL_QSER_E7_MASK (0x00000080u) +#define EDMA3_CCRL_QSER_E7_SHIFT (0x00000007u) +#define EDMA3_CCRL_QSER_E7_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QSER_E6_MASK (0x00000040u) +#define EDMA3_CCRL_QSER_E6_SHIFT (0x00000006u) +#define EDMA3_CCRL_QSER_E6_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QSER_E5_MASK (0x00000020u) +#define EDMA3_CCRL_QSER_E5_SHIFT (0x00000005u) +#define EDMA3_CCRL_QSER_E5_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QSER_E4_MASK (0x00000010u) +#define EDMA3_CCRL_QSER_E4_SHIFT (0x00000004u) +#define EDMA3_CCRL_QSER_E4_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QSER_E3_MASK (0x00000008u) +#define EDMA3_CCRL_QSER_E3_SHIFT (0x00000003u) +#define EDMA3_CCRL_QSER_E3_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QSER_E2_MASK (0x00000004u) +#define EDMA3_CCRL_QSER_E2_SHIFT (0x00000002u) +#define EDMA3_CCRL_QSER_E2_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QSER_E1_MASK (0x00000002u) +#define EDMA3_CCRL_QSER_E1_SHIFT (0x00000001u) +#define EDMA3_CCRL_QSER_E1_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QSER_E0_MASK (0x00000001u) +#define EDMA3_CCRL_QSER_E0_SHIFT (0x00000000u) +#define EDMA3_CCRL_QSER_E0_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QSER_RESETVAL (0x00000000u) + +/* QSECR */ + +#define EDMA3_CCRL_QSECR_E7_MASK (0x00000080u) +#define EDMA3_CCRL_QSECR_E7_SHIFT (0x00000007u) +#define EDMA3_CCRL_QSECR_E7_RESETVAL (0x00000000u) + +/*----E7 Tokens----*/ +#define EDMA3_CCRL_QSECR_E7_CLEAR (0x00000001u) + +#define EDMA3_CCRL_QSECR_E6_MASK (0x00000040u) +#define EDMA3_CCRL_QSECR_E6_SHIFT (0x00000006u) +#define EDMA3_CCRL_QSECR_E6_RESETVAL (0x00000000u) + +/*----E6 Tokens----*/ +#define EDMA3_CCRL_QSECR_E6_CLEAR (0x00000001u) + +#define EDMA3_CCRL_QSECR_E5_MASK (0x00000020u) +#define EDMA3_CCRL_QSECR_E5_SHIFT (0x00000005u) +#define EDMA3_CCRL_QSECR_E5_RESETVAL (0x00000000u) + +/*----E5 Tokens----*/ +#define EDMA3_CCRL_QSECR_E5_CLEAR (0x00000001u) + +#define EDMA3_CCRL_QSECR_E4_MASK (0x00000010u) +#define EDMA3_CCRL_QSECR_E4_SHIFT (0x00000004u) +#define EDMA3_CCRL_QSECR_E4_RESETVAL (0x00000000u) + +/*----E4 Tokens----*/ +#define EDMA3_CCRL_QSECR_E4_CLEAR (0x00000001u) + +#define EDMA3_CCRL_QSECR_E3_MASK (0x00000008u) +#define EDMA3_CCRL_QSECR_E3_SHIFT (0x00000003u) +#define EDMA3_CCRL_QSECR_E3_RESETVAL (0x00000000u) + +/*----E3 Tokens----*/ +#define EDMA3_CCRL_QSECR_E3_CLEAR (0x00000001u) + +#define EDMA3_CCRL_QSECR_E2_MASK (0x00000004u) +#define EDMA3_CCRL_QSECR_E2_SHIFT (0x00000002u) +#define EDMA3_CCRL_QSECR_E2_RESETVAL (0x00000000u) + +/*----E2 Tokens----*/ +#define EDMA3_CCRL_QSECR_E2_CLEAR (0x00000001u) + +#define EDMA3_CCRL_QSECR_E1_MASK (0x00000002u) +#define EDMA3_CCRL_QSECR_E1_SHIFT (0x00000001u) +#define EDMA3_CCRL_QSECR_E1_RESETVAL (0x00000000u) + +/*----E1 Tokens----*/ +#define EDMA3_CCRL_QSECR_E1_CLEAR (0x00000001u) + +#define EDMA3_CCRL_QSECR_E0_MASK (0x00000001u) +#define EDMA3_CCRL_QSECR_E0_SHIFT (0x00000000u) +#define EDMA3_CCRL_QSECR_E0_RESETVAL (0x00000000u) + +/*----E0 Tokens----*/ +#define EDMA3_CCRL_QSECR_E0_CLEAR (0x00000001u) + +#define EDMA3_CCRL_QSECR_RESETVAL (0x00000000u) + +/* OPT */ + +#define EDMA3_CCRL_OPT_PRIV_MASK (0x80000000u) +#define EDMA3_CCRL_OPT_PRIV_SHIFT (0x0000001Fu) +#define EDMA3_CCRL_OPT_PRIV_RESETVAL (0x00000000u) + +/*----PRIV Tokens----*/ +#define EDMA3_CCRL_OPT_PRIV_USER (0x00000000u) +#define EDMA3_CCRL_OPT_PRIV_SUPERVISOR (0x00000001u) + +#define EDMA3_CCRL_OPT_SECURE_MASK (0x40000000u) +#define EDMA3_CCRL_OPT_SECURE_SHIFT (0x0000001Eu) +#define EDMA3_CCRL_OPT_SECURE_RESETVAL (0x00000000u) + +/*----SECURE Tokens----*/ +#define EDMA3_CCRL_OPT_SECURE_SECURE (0x00000000u) +#define EDMA3_CCRL_OPT_SECURE_NONSECURE (0x00000001u) + +#define EDMA3_CCRL_OPT_PRIVID_MASK (0x0F000000u) +#define EDMA3_CCRL_OPT_PRIVID_SHIFT (0x00000018u) +#define EDMA3_CCRL_OPT_PRIVID_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_OPT_ITCCHEN_MASK (0x00800000u) +#define EDMA3_CCRL_OPT_ITCCHEN_SHIFT (0x00000017u) +#define EDMA3_CCRL_OPT_ITCCHEN_RESETVAL (0x00000000u) + +/*----ITCCHEN Tokens----*/ +#define EDMA3_CCRL_OPT_ITCCHEN_DISABLE (0x00000000u) +#define EDMA3_CCRL_OPT_ITCCHEN_ENABLE (0x00000001u) + +#define EDMA3_CCRL_OPT_TCCHEN_MASK (0x00400000u) +#define EDMA3_CCRL_OPT_TCCHEN_SHIFT (0x00000016u) +#define EDMA3_CCRL_OPT_TCCHEN_RESETVAL (0x00000000u) + +/*----TCCHEN Tokens----*/ +#define EDMA3_CCRL_OPT_TCCHEN_DISABLE (0x00000000u) +#define EDMA3_CCRL_OPT_TCCHEN_ENABLE (0x00000001u) + +#define EDMA3_CCRL_OPT_ITCINTEN_MASK (0x00200000u) +#define EDMA3_CCRL_OPT_ITCINTEN_SHIFT (0x00000015u) +#define EDMA3_CCRL_OPT_ITCINTEN_RESETVAL (0x00000000u) + +/*----ITCINTEN Tokens----*/ +#define EDMA3_CCRL_OPT_ITCINTEN_DISABLE (0x00000000u) +#define EDMA3_CCRL_OPT_ITCINTEN_ENABLE (0x00000001u) + +#define EDMA3_CCRL_OPT_TCINTEN_MASK (0x00100000u) +#define EDMA3_CCRL_OPT_TCINTEN_SHIFT (0x00000014u) +#define EDMA3_CCRL_OPT_TCINTEN_RESETVAL (0x00000000u) + +/*----TCINTEN Tokens----*/ +#define EDMA3_CCRL_OPT_TCINTEN_DISABLE (0x00000000u) +#define EDMA3_CCRL_OPT_TCINTEN_ENABLE (0x00000001u) + +#define EDMA3_CCRL_OPT_WIMODE_MASK (0x00080000u) +#define EDMA3_CCRL_OPT_WIMODE_SHIFT (0x00000013u) +#define EDMA3_CCRL_OPT_WIMODE_RESETVAL (0x00000000u) + +/*----WIMODE Tokens----*/ +#define EDMA3_CCRL_OPT_WIMODE_NORMAL (0x00000000u) +#define EDMA3_CCRL_OPT_WIMODE_WI (0x00000001u) + +#define EDMA3_CCRL_OPT_TCC_MASK (0x0003F000u) +#define EDMA3_CCRL_OPT_TCC_SHIFT (0x0000000Cu) +#define EDMA3_CCRL_OPT_TCC_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_OPT_TCCMODE_MASK (0x00000800u) +#define EDMA3_CCRL_OPT_TCCMODE_SHIFT (0x0000000Bu) +#define EDMA3_CCRL_OPT_TCCMODE_RESETVAL (0x00000000u) + +/*----TCCMODE Tokens----*/ +#define EDMA3_CCRL_OPT_TCCMODE_NORMAL (0x00000000u) +#define EDMA3_CCRL_OPT_TCCMODE_EARLY (0x00000001u) + +#define EDMA3_CCRL_OPT_FWID_MASK (0x00000700u) +#define EDMA3_CCRL_OPT_FWID_SHIFT (0x00000008u) +#define EDMA3_CCRL_OPT_FWID_RESETVAL (0x00000000u) + +/*----FWID Tokens----*/ +#define EDMA3_CCRL_OPT_FWID_8 (0x00000000u) +#define EDMA3_CCRL_OPT_FWID_16 (0x00000001u) +#define EDMA3_CCRL_OPT_FWID_32 (0x00000002u) +#define EDMA3_CCRL_OPT_FWID_64 (0x00000003u) +#define EDMA3_CCRL_OPT_FWID_128 (0x00000004u) +#define EDMA3_CCRL_OPT_FWID_256 (0x00000005u) + +#define EDMA3_CCRL_OPT_STATIC_MASK (0x00000008u) +#define EDMA3_CCRL_OPT_STATIC_SHIFT (0x00000003u) +#define EDMA3_CCRL_OPT_STATIC_RESETVAL (0x00000000u) + +/*----STATIC Tokens----*/ +#define EDMA3_CCRL_OPT_STATIC_NORMAL (0x00000000u) +#define EDMA3_CCRL_OPT_STATIC_STATIC (0x00000001u) + +#define EDMA3_CCRL_OPT_SYNCDIM_MASK (0x00000004u) +#define EDMA3_CCRL_OPT_SYNCDIM_SHIFT (0x00000002u) +#define EDMA3_CCRL_OPT_SYNCDIM_RESETVAL (0x00000000u) + +/*----SYNCDIM Tokens----*/ +#define EDMA3_CCRL_OPT_SYNCDIM_ASYNC (0x00000000u) +#define EDMA3_CCRL_OPT_SYNCDIM_ABSYNC (0x00000001u) + +#define EDMA3_CCRL_OPT_DAM_MASK (0x00000002u) +#define EDMA3_CCRL_OPT_DAM_SHIFT (0x00000001u) +#define EDMA3_CCRL_OPT_DAM_RESETVAL (0x00000000u) + +/*----DAM Tokens----*/ +#define EDMA3_CCRL_OPT_DAM_INCR (0x00000000u) +#define EDMA3_CCRL_OPT_DAM_FIFO (0x00000001u) + +#define EDMA3_CCRL_OPT_SAM_MASK (0x00000001u) +#define EDMA3_CCRL_OPT_SAM_SHIFT (0x00000000u) +#define EDMA3_CCRL_OPT_SAM_RESETVAL (0x00000000u) + +/*----SAM Tokens----*/ +#define EDMA3_CCRL_OPT_SAM_INCR (0x00000000u) +#define EDMA3_CCRL_OPT_SAM_FIFO (0x00000001u) + +#define EDMA3_CCRL_OPT_RESETVAL (0x00000000u) + +/* SRC */ + +#define EDMA3_CCRL_SRC_SRC_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_SRC_SRC_SHIFT (0x00000000u) +#define EDMA3_CCRL_SRC_SRC_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SRC_RESETVAL (0x00000000u) + +/* A_B_CNT */ + +#define EDMA3_CCRL_A_B_CNT_BCNT_MASK (0xFFFF0000u) +#define EDMA3_CCRL_A_B_CNT_BCNT_SHIFT (0x00000010u) +#define EDMA3_CCRL_A_B_CNT_BCNT_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_A_B_CNT_ACNT_MASK (0x0000FFFFu) +#define EDMA3_CCRL_A_B_CNT_ACNT_SHIFT (0x00000000u) +#define EDMA3_CCRL_A_B_CNT_ACNT_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_A_B_CNT_RESETVAL (0x00000000u) + +/* DST */ + +#define EDMA3_CCRL_DST_DST_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_DST_DST_SHIFT (0x00000000u) +#define EDMA3_CCRL_DST_DST_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_DST_RESETVAL (0x00000000u) + +/* SRC_DST_BIDX */ + +#define EDMA3_CCRL_SRC_DST_BIDX_DSTBIDX_MASK (0xFFFF0000u) +#define EDMA3_CCRL_SRC_DST_BIDX_DSTBIDX_SHIFT (0x00000010u) +#define EDMA3_CCRL_SRC_DST_BIDX_DSTBIDX_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SRC_DST_BIDX_SRCBIDX_MASK (0x0000FFFFu) +#define EDMA3_CCRL_SRC_DST_BIDX_SRCBIDX_SHIFT (0x00000000u) +#define EDMA3_CCRL_SRC_DST_BIDX_SRCBIDX_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SRC_DST_BIDX_RESETVAL (0x00000000u) + +/* LINK_BCNTRLD */ + +#define EDMA3_CCRL_LINK_BCNTRLD_BCNTRLD_MASK (0xFFFF0000u) +#define EDMA3_CCRL_LINK_BCNTRLD_BCNTRLD_SHIFT (0x00000010u) +#define EDMA3_CCRL_LINK_BCNTRLD_BCNTRLD_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_LINK_BCNTRLD_LINK_MASK (0x0000FFFFu) +#define EDMA3_CCRL_LINK_BCNTRLD_LINK_SHIFT (0x00000000u) +#define EDMA3_CCRL_LINK_BCNTRLD_LINK_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_LINK_BCNTRLD_RESETVAL (0x00000000u) + +/* SRC_DST_CIDX */ + +#define EDMA3_CCRL_SRC_DST_CIDX_DSTCIDX_MASK (0xFFFF0000u) +#define EDMA3_CCRL_SRC_DST_CIDX_DSTCIDX_SHIFT (0x00000010u) +#define EDMA3_CCRL_SRC_DST_CIDX_DSTCIDX_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SRC_DST_CIDX_SRCCIDX_MASK (0x0000FFFFu) +#define EDMA3_CCRL_SRC_DST_CIDX_SRCCIDX_SHIFT (0x00000000u) +#define EDMA3_CCRL_SRC_DST_CIDX_SRCCIDX_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SRC_DST_CIDX_RESETVAL (0x00000000u) + +/* CCNT */ + +#define EDMA3_CCRL_CCNT_CCNT_MASK (0x0000FFFFu) +#define EDMA3_CCRL_CCNT_CCNT_SHIFT (0x00000000u) +#define EDMA3_CCRL_CCNT_CCNT_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CCNT_RESETVAL (0x00000000u) + +/* ER */ + +#define EDMA3_CCRL_ER_REG_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_ER_REG_SHIFT (0x00000000u) +#define EDMA3_CCRL_ER_REG_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ER_RESETVAL (0x00000000u) + +/* ERH */ + +#define EDMA3_CCRL_ERH_REG_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_ERH_REG_SHIFT (0x00000000u) +#define EDMA3_CCRL_ERH_REG_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ERH_RESETVAL (0x00000000u) + +/* ECR */ + +#define EDMA3_CCRL_ECR_REG_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_ECR_REG_SHIFT (0x00000000u) +#define EDMA3_CCRL_ECR_REG_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ECR_RESETVAL (0x00000000u) + +/* ECRH */ + +#define EDMA3_CCRL_ECRH_REG_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_ECRH_REG_SHIFT (0x00000000u) +#define EDMA3_CCRL_ECRH_REG_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ECRH_RESETVAL (0x00000000u) + +/* ESR */ + +#define EDMA3_CCRL_ESR_REG_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_ESR_REG_SHIFT (0x00000000u) +#define EDMA3_CCRL_ESR_REG_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ESR_RESETVAL (0x00000000u) + +/* ESRH */ + +#define EDMA3_CCRL_ESRH_REG_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_ESRH_REG_SHIFT (0x00000000u) +#define EDMA3_CCRL_ESRH_REG_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ESRH_RESETVAL (0x00000000u) + +/* CER */ + +#define EDMA3_CCRL_CER_REG_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_CER_REG_SHIFT (0x00000000u) +#define EDMA3_CCRL_CER_REG_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CER_RESETVAL (0x00000000u) + +/* CERH */ + +#define EDMA3_CCRL_CERH_REG_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_CERH_REG_SHIFT (0x00000000u) +#define EDMA3_CCRL_CERH_REG_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_CERH_RESETVAL (0x00000000u) + +/* EER */ + +#define EDMA3_CCRL_EER_REG_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_EER_REG_SHIFT (0x00000000u) +#define EDMA3_CCRL_EER_REG_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EER_RESETVAL (0x00000000u) + +/* EERH */ + +#define EDMA3_CCRL_EERH_REG_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_EERH_REG_SHIFT (0x00000000u) +#define EDMA3_CCRL_EERH_REG_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EERH_RESETVAL (0x00000000u) + +/* EECR */ + +#define EDMA3_CCRL_EECR_REG_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_EECR_REG_SHIFT (0x00000000u) +#define EDMA3_CCRL_EECR_REG_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EECR_RESETVAL (0x00000000u) + +/* EECRH */ + +#define EDMA3_CCRL_EECRH_REG_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_EECRH_REG_SHIFT (0x00000000u) +#define EDMA3_CCRL_EECRH_REG_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EECRH_RESETVAL (0x00000000u) + +/* EESR */ + +#define EDMA3_CCRL_EESR_REG_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_EESR_REG_SHIFT (0x00000000u) +#define EDMA3_CCRL_EESR_REG_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EESR_RESETVAL (0x00000000u) + +/* EESRH */ + +#define EDMA3_CCRL_EESRH_REG_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_EESRH_REG_SHIFT (0x00000000u) +#define EDMA3_CCRL_EESRH_REG_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_EESRH_RESETVAL (0x00000000u) + +/* SER */ + +#define EDMA3_CCRL_SER_REG_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_SER_REG_SHIFT (0x00000000u) +#define EDMA3_CCRL_SER_REG_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SER_RESETVAL (0x00000000u) + +/* SERH */ + +#define EDMA3_CCRL_SERH_REG_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_SERH_REG_SHIFT (0x00000000u) +#define EDMA3_CCRL_SERH_REG_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SERH_RESETVAL (0x00000000u) + +/* SECR */ + +#define EDMA3_CCRL_SECR_REG_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_SECR_REG_SHIFT (0x00000000u) +#define EDMA3_CCRL_SECR_REG_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SECR_RESETVAL (0x00000000u) + +/* SECRH */ + +#define EDMA3_CCRL_SECRH_REG_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_SECRH_REG_SHIFT (0x00000000u) +#define EDMA3_CCRL_SECRH_REG_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_SECRH_RESETVAL (0x00000000u) + +/* IER */ + +#define EDMA3_CCRL_IER_REG_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_IER_REG_SHIFT (0x00000000u) +#define EDMA3_CCRL_IER_REG_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IER_RESETVAL (0x00000000u) + +/* IERH */ + +#define EDMA3_CCRL_IERH_REG_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_IERH_REG_SHIFT (0x00000000u) +#define EDMA3_CCRL_IERH_REG_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IERH_RESETVAL (0x00000000u) + +/* IECR */ + +#define EDMA3_CCRL_IECR_REG_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_IECR_REG_SHIFT (0x00000000u) +#define EDMA3_CCRL_IECR_REG_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IECR_RESETVAL (0x00000000u) + +/* IECRH */ + +#define EDMA3_CCRL_IECRH_REG_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_IECRH_REG_SHIFT (0x00000000u) +#define EDMA3_CCRL_IECRH_REG_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IECRH_RESETVAL (0x00000000u) + +/* IESR */ + +#define EDMA3_CCRL_IESR_REG_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_IESR_REG_SHIFT (0x00000000u) +#define EDMA3_CCRL_IESR_REG_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IESR_RESETVAL (0x00000000u) + +/* IESRH */ + +#define EDMA3_CCRL_IESRH_REG_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_IESRH_REG_SHIFT (0x00000000u) +#define EDMA3_CCRL_IESRH_REG_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IESRH_RESETVAL (0x00000000u) + +/* IPR */ + +#define EDMA3_CCRL_IPR_REG_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_IPR_REG_SHIFT (0x00000000u) +#define EDMA3_CCRL_IPR_REG_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPR_RESETVAL (0x00000000u) + +/* IPRH */ + +#define EDMA3_CCRL_IPRH_REG_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_IPRH_REG_SHIFT (0x00000000u) +#define EDMA3_CCRL_IPRH_REG_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IPRH_RESETVAL (0x00000000u) + +/* ICR */ + +#define EDMA3_CCRL_ICR_REG_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_ICR_REG_SHIFT (0x00000000u) +#define EDMA3_CCRL_ICR_REG_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ICR_RESETVAL (0x00000000u) + +/* ICRH */ + +#define EDMA3_CCRL_ICRH_REG_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_ICRH_REG_SHIFT (0x00000000u) +#define EDMA3_CCRL_ICRH_REG_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_ICRH_RESETVAL (0x00000000u) + +/* IEVAL */ + +#define EDMA3_CCRL_IEVAL_REG_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_IEVAL_REG_SHIFT (0x00000000u) +#define EDMA3_CCRL_IEVAL_REG_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_IEVAL_RESETVAL (0x00000000u) + +/* QER */ + +#define EDMA3_CCRL_QER_REG_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_QER_REG_SHIFT (0x00000000u) +#define EDMA3_CCRL_QER_REG_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QER_RESETVAL (0x00000000u) + +/* QEER */ + +#define EDMA3_CCRL_QEER_REG_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_QEER_REG_SHIFT (0x00000000u) +#define EDMA3_CCRL_QEER_REG_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QEER_RESETVAL (0x00000000u) + +/* QEECR */ + +#define EDMA3_CCRL_QEECR_REG_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_QEECR_REG_SHIFT (0x00000000u) +#define EDMA3_CCRL_QEECR_REG_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QEECR_RESETVAL (0x00000000u) + +/* QEESR */ + +#define EDMA3_CCRL_QEESR_REG_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_QEESR_REG_SHIFT (0x00000000u) +#define EDMA3_CCRL_QEESR_REG_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QEESR_RESETVAL (0x00000000u) + +/* QSER */ + +#define EDMA3_CCRL_QSER_REG_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_QSER_REG_SHIFT (0x00000000u) +#define EDMA3_CCRL_QSER_REG_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QSER_RESETVAL (0x00000000u) + +/* QSECR */ + +#define EDMA3_CCRL_QSECR_REG_MASK (0xFFFFFFFFu) +#define EDMA3_CCRL_QSECR_REG_SHIFT (0x00000000u) +#define EDMA3_CCRL_QSECR_REG_RESETVAL (0x00000000u) + +#define EDMA3_CCRL_QSECR_RESETVAL (0x00000000u) + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif /* _EDMA3_RL_CC_H_ */ diff --git a/packages/ti/sdo/edma3/rm/src/edma3_rl_tc.h b/packages/ti/sdo/edma3/rm/src/edma3_rl_tc.h new file mode 100644 index 0000000..3fa5eff --- /dev/null +++ b/packages/ti/sdo/edma3/rm/src/edma3_rl_tc.h @@ -0,0 +1,806 @@ +/****************************************************************************** +**+-------------------------------------------------------------------------+** +**| **** |** +**| **** |** +**| ******o*** |** +**| ********_///_**** |** +**| ***** /_//_/ **** |** +**| ** ** (__/ **** |** +**| ********* |** +**| **** |** +**| *** |** +**| |** +**| Copyright (c) 1998-2006 Texas Instruments Incorporated |** +**| ALL RIGHTS RESERVED |** +**| |** +**| Permission is hereby granted to licensees of Texas Instruments |** +**| Incorporated (TI) products to use this computer program for the sole |** +**| purpose of implementing a licensee product based on TI products. |** +**| No other rights to reproduce, use, or disseminate this computer |** +**| program, whether in part or in whole, are granted. |** +**| |** +**| TI makes no representation or warranties with respect to the |** +**| performance of this computer program, and specifically disclaims |** +**| any responsibility for any damages, special or consequential, |** +**| connected with the use of this program. |** +**| |** +**+-------------------------------------------------------------------------+** +******************************************************************************/ + +/** \file edma3_rl_tc.h + \brief EDMA3 Transfer Controller Register Desciption. + + This file contains the register layer for the EDMA3 Transfer Controller. + + (C) Copyright 2006, Texas Instruments, Inc + + \version + 1.0 Anuj Aggarwal - Created + + */ + +#ifndef _EDMA3_RL_TC_H_ +#define _EDMA3_RL_TC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************\ +* Register Overlay Structure for DFIREG +\**************************************************************************/ +typedef struct { + volatile unsigned int DFOPT; + volatile unsigned int DFSRC; + volatile unsigned int DFCNT; + volatile unsigned int DFDST; + volatile unsigned int DFBIDX; + volatile unsigned int DFMPPRXY; + volatile unsigned char RSVD0[40]; +} EDMA3_TCRL_DfiregRegs; + +/**************************************************************************\ +* Register Overlay Structure +\**************************************************************************/ +typedef struct { + volatile unsigned int REV; + volatile unsigned int TCCFG; + volatile unsigned char RSVD0[248]; + volatile unsigned int TCSTAT; + volatile unsigned int INTSTAT; + volatile unsigned int INTEN; + volatile unsigned int INTCLR; + volatile unsigned int INTCMD; + volatile unsigned char RSVD1[12]; + volatile unsigned int ERRSTAT; + volatile unsigned int ERREN; + volatile unsigned int ERRCLR; + volatile unsigned int ERRDET; + volatile unsigned int ERRCMD; + volatile unsigned char RSVD2[12]; + volatile unsigned int RDRATE; + volatile unsigned char RSVD3[188]; + volatile unsigned int POPT; + volatile unsigned int PSRC; + volatile unsigned int PCNT; + volatile unsigned int PDST; + volatile unsigned int PBIDX; + volatile unsigned int PMPPRXY; + volatile unsigned char RSVD4[40]; + volatile unsigned int SAOPT; + volatile unsigned int SASRC; + volatile unsigned int SACNT; + volatile unsigned int SADST; + volatile unsigned int SABIDX; + volatile unsigned int SAMPPRXY; + volatile unsigned int SACNTRLD; + volatile unsigned int SASRCBREF; + volatile unsigned int SADSTBREF; + volatile unsigned char RSVD5[28]; + volatile unsigned int DFCNTRLD; + volatile unsigned int DFSRCBREF; + volatile unsigned int DFDSTBREF; + volatile unsigned char RSVD6[116]; + EDMA3_TCRL_DfiregRegs DFIREG[4]; +} EDMA3_TCRL_Regs; + +/**************************************************************************\ +* Field Definition Macros +\**************************************************************************/ + +/* REV */ + +#define EDMA3_TCRL_REV_TYPE_MASK (0x00FF0000u) +#define EDMA3_TCRL_REV_TYPE_SHIFT (0x00000010u) +#define EDMA3_TCRL_REV_TYPE_RESETVAL (0x00000006u) + +#define EDMA3_TCRL_REV_CLASS_MASK (0x0000FF00u) +#define EDMA3_TCRL_REV_CLASS_SHIFT (0x00000008u) +#define EDMA3_TCRL_REV_CLASS_RESETVAL (0x00000004u) + +#define EDMA3_TCRL_REV_REV_MASK (0x000000FFu) +#define EDMA3_TCRL_REV_REV_SHIFT (0x00000000u) +#define EDMA3_TCRL_REV_REV_RESETVAL (0x00000001u) + +#define EDMA3_TCRL_REV_RESETVAL (0x00060401u) + +/* TCCFG */ + +#define EDMA3_TCRL_TCCFG_DREGDEPTH_MASK (0x00000300u) +#define EDMA3_TCRL_TCCFG_DREGDEPTH_SHIFT (0x00000008u) +#define EDMA3_TCRL_TCCFG_DREGDEPTH_RESETVAL (0x00000000u) + +/*----DREGDEPTH Tokens----*/ +#define EDMA3_TCRL_TCCFG_DREGDEPTH_1ENTRY (0x00000000u) +#define EDMA3_TCRL_TCCFG_DREGDEPTH_2ENTRY (0x00000001u) +#define EDMA3_TCRL_TCCFG_DREGDEPTH_4ENTRY (0x00000002u) + +#define EDMA3_TCRL_TCCFG_BUSWIDTH_MASK (0x00000030u) +#define EDMA3_TCRL_TCCFG_BUSWIDTH_SHIFT (0x00000004u) +#define EDMA3_TCRL_TCCFG_BUSWIDTH_RESETVAL (0x00000000u) + +/*----BUSWIDTH Tokens----*/ +#define EDMA3_TCRL_TCCFG_BUSWIDTH_32BIT (0x00000000u) +#define EDMA3_TCRL_TCCFG_BUSWIDTH_64BIY (0x00000001u) +#define EDMA3_TCRL_TCCFG_BUSWIDTH_128BIT (0x00000002u) + +#define EDMA3_TCRL_TCCFG_FIFOSIZE_MASK (0x00000007u) +#define EDMA3_TCRL_TCCFG_FIFOSIZE_SHIFT (0x00000000u) +#define EDMA3_TCRL_TCCFG_FIFOSIZE_RESETVAL (0x00000000u) + +/*----FIFOSIZE Tokens----*/ +#define EDMA3_TCRL_TCCFG_FIFOSIZE_32BYTE (0x00000000u) +#define EDMA3_TCRL_TCCFG_FIFOSIZE_64BYTE (0x00000001u) +#define EDMA3_TCRL_TCCFG_FIFOSIZE_128BYTE (0x00000002u) +#define EDMA3_TCRL_TCCFG_FIFOSIZE_256BYTE (0x00000003u) +#define EDMA3_TCRL_TCCFG_FIFOSIZE_512BYTE (0x00000004u) + +#define EDMA3_TCRL_TCCFG_RESETVAL (0x00000000u) + +/* TCSTAT */ + +#define EDMA3_TCRL_TCSTAT_DFSTRT_MASK (0x00003000u) +#define EDMA3_TCRL_TCSTAT_DFSTRT_SHIFT (0x0000000Cu) +#define EDMA3_TCRL_TCSTAT_DFSTRT_RESETVAL (0x00000000u) + +#define EDMA3_TCRL_TCSTAT_ATCV_MASK (0x00000100u) +#define EDMA3_TCRL_TCSTAT_ATCV_SHIFT (0x00000008u) +#define EDMA3_TCRL_TCSTAT_ATCV_RESETVAL (0x00000000u) + +/*----ATCV Tokens----*/ +#define EDMA3_TCRL_TCSTAT_ATCV_IDLE (0x00000000u) +#define EDMA3_TCRL_TCSTAT_ATCV_BUSY (0x00000001u) + +#define EDMA3_TCRL_TCSTAT_DSTACT_MASK (0x00000070u) +#define EDMA3_TCRL_TCSTAT_DSTACT_SHIFT (0x00000004u) +#define EDMA3_TCRL_TCSTAT_DSTACT_RESETVAL (0x00000000u) + +/*----DSTACT Tokens----*/ +#define EDMA3_TCRL_TCSTAT_DSTACT_EMPTY (0x00000000u) +#define EDMA3_TCRL_TCSTAT_DSTACT_1TR (0x00000001u) +#define EDMA3_TCRL_TCSTAT_DSTACT_2TR (0x00000002u) +#define EDMA3_TCRL_TCSTAT_DSTACT_3TR (0x00000003u) +#define EDMA3_TCRL_TCSTAT_DSTACT_4TR (0x00000004u) + +#define EDMA3_TCRL_TCSTAT_WSACTV_MASK (0x00000004u) +#define EDMA3_TCRL_TCSTAT_WSACTV_SHIFT (0x00000002u) +#define EDMA3_TCRL_TCSTAT_WSACTV_RESETVAL (0x00000000u) + +/*----WSACTV Tokens----*/ +#define EDMA3_TCRL_TCSTAT_WSACTV_NONE (0x00000000u) +#define EDMA3_TCRL_TCSTAT_WSACTV_PEND (0x00000001u) + +#define EDMA3_TCRL_TCSTAT_SRCACTV_MASK (0x00000002u) +#define EDMA3_TCRL_TCSTAT_SRCACTV_SHIFT (0x00000001u) +#define EDMA3_TCRL_TCSTAT_SRCACTV_RESETVAL (0x00000000u) + +/*----SRCACTV Tokens----*/ +#define EDMA3_TCRL_TCSTAT_SRCACTV_IDLE (0x00000000u) +#define EDMA3_TCRL_TCSTAT_SRCACTV_BUSY (0x00000001u) + +#define EDMA3_TCRL_TCSTAT_PROGBUSY_MASK (0x00000001u) +#define EDMA3_TCRL_TCSTAT_PROGBUSY_SHIFT (0x00000000u) +#define EDMA3_TCRL_TCSTAT_PROGBUSY_RESETVAL (0x00000000u) + +/*----PROGBUSY Tokens----*/ +#define EDMA3_TCRL_TCSTAT_PROGBUSY_IDLE (0x00000000u) +#define EDMA3_TCRL_TCSTAT_PROGBUSY_BUSY (0x00000001u) + +#define EDMA3_TCRL_TCSTAT_RESETVAL (0x00000000u) + +/* INTSTAT */ + +#define EDMA3_TCRL_INTSTAT_TRDONE_MASK (0x00000002u) +#define EDMA3_TCRL_INTSTAT_TRDONE_SHIFT (0x00000001u) +#define EDMA3_TCRL_INTSTAT_TRDONE_RESETVAL (0x00000000u) + +/*----TRDONE Tokens----*/ +#define EDMA3_TCRL_INTSTAT_TRDONE_NONE (0x00000000u) +#define EDMA3_TCRL_INTSTAT_TRDONE_DONE (0x00000001u) + +#define EDMA3_TCRL_INTSTAT_PROGEMPTY_MASK (0x00000001u) +#define EDMA3_TCRL_INTSTAT_PROGEMPTY_SHIFT (0x00000000u) +#define EDMA3_TCRL_INTSTAT_PROGEMPTY_RESETVAL (0x00000000u) + +/*----PROGEMPTY Tokens----*/ +#define EDMA3_TCRL_INTSTAT_PROGEMPTY_NONE (0x00000000u) +#define EDMA3_TCRL_INTSTAT_PROGEMPTY_EMPTY (0x00000001u) + +#define EDMA3_TCRL_INTSTAT_RESETVAL (0x00000000u) + +/* INTEN */ + +#define EDMA3_TCRL_INTEN_TRDONE_MASK (0x00000002u) +#define EDMA3_TCRL_INTEN_TRDONE_SHIFT (0x00000001u) +#define EDMA3_TCRL_INTEN_TRDONE_RESETVAL (0x00000000u) + +/*----TRDONE Tokens----*/ +#define EDMA3_TCRL_INTEN_TRDONE_DISABLE (0x00000000u) +#define EDMA3_TCRL_INTEN_TRDONE_ENABLE (0x00000001u) + +#define EDMA3_TCRL_INTEN_PROGEMPTY_MASK (0x00000001u) +#define EDMA3_TCRL_INTEN_PROGEMPTY_SHIFT (0x00000000u) +#define EDMA3_TCRL_INTEN_PROGEMPTY_RESETVAL (0x00000000u) + +/*----PROGEMPTY Tokens----*/ +#define EDMA3_TCRL_INTEN_PROGEMPTY_DISABLE (0x00000000u) +#define EDMA3_TCRL_INTEN_PROGEMPTY_ENABLE (0x00000001u) + +#define EDMA3_TCRL_INTEN_RESETVAL (0x00000000u) + +/* INTCLR */ + +#define EDMA3_TCRL_INTCLR_TRDONE_MASK (0x00000002u) +#define EDMA3_TCRL_INTCLR_TRDONE_SHIFT (0x00000001u) +#define EDMA3_TCRL_INTCLR_TRDONE_RESETVAL (0x00000000u) + +/*----TRDONE Tokens----*/ +#define EDMA3_TCRL_INTCLR_TRDONE_CLEAR (0x00000001u) + +#define EDMA3_TCRL_INTCLR_PROGEMPTY_MASK (0x00000001u) +#define EDMA3_TCRL_INTCLR_PROGEMPTY_SHIFT (0x00000000u) +#define EDMA3_TCRL_INTCLR_PROGEMPTY_RESETVAL (0x00000000u) + +/*----PROGEMPTY Tokens----*/ +#define EDMA3_TCRL_INTCLR_PROGEMPTY_CLEAR (0x00000001u) + +#define EDMA3_TCRL_INTCLR_RESETVAL (0x00000000u) + +/* INTCMD */ + +#define EDMA3_TCRL_INTCMD_SET_MASK (0x00000002u) +#define EDMA3_TCRL_INTCMD_SET_SHIFT (0x00000001u) +#define EDMA3_TCRL_INTCMD_SET_RESETVAL (0x00000000u) + +/*----SET Tokens----*/ +#define EDMA3_TCRL_INTCMD_SET_SET (0x00000001u) + +#define EDMA3_TCRL_INTCMD_EVAL_MASK (0x00000001u) +#define EDMA3_TCRL_INTCMD_EVAL_SHIFT (0x00000000u) +#define EDMA3_TCRL_INTCMD_EVAL_RESETVAL (0x00000000u) + +/*----EVAL Tokens----*/ +#define EDMA3_TCRL_INTCMD_EVAL_EVAL (0x00000001u) + +#define EDMA3_TCRL_INTCMD_RESETVAL (0x00000000u) + +/* ERRSTAT */ + +#define EDMA3_TCRL_ERRSTAT_MMRAERR_MASK (0x00000008u) +#define EDMA3_TCRL_ERRSTAT_MMRAERR_SHIFT (0x00000003u) +#define EDMA3_TCRL_ERRSTAT_MMRAERR_RESETVAL (0x00000000u) + +/*----MMRAERR Tokens----*/ +#define EDMA3_TCRL_ERRSTAT_MMRAERR_NONE (0x00000000u) +#define EDMA3_TCRL_ERRSTAT_MMRAERR_ERROR (0x00000001u) + +#define EDMA3_TCRL_ERRSTAT_TRERR_MASK (0x00000004u) +#define EDMA3_TCRL_ERRSTAT_TRERR_SHIFT (0x00000002u) +#define EDMA3_TCRL_ERRSTAT_TRERR_RESETVAL (0x00000000u) + +/*----TRERR Tokens----*/ +#define EDMA3_TCRL_ERRSTAT_TRERR_NONE (0x00000000u) +#define EDMA3_TCRL_ERRSTAT_TRERR_ERROR (0x00000001u) + +#define EDMA3_TCRL_ERRSTAT_BUSERR_MASK (0x00000001u) +#define EDMA3_TCRL_ERRSTAT_BUSERR_SHIFT (0x00000000u) +#define EDMA3_TCRL_ERRSTAT_BUSERR_RESETVAL (0x00000000u) + +/*----BUSERR Tokens----*/ +#define EDMA3_TCRL_ERRSTAT_BUSERR_NONE (0x00000000u) +#define EDMA3_TCRL_ERRSTAT_BUSERR_ERROR (0x00000001u) + +#define EDMA3_TCRL_ERRSTAT_RESETVAL (0x00000000u) + +/* ERREN */ + +#define EDMA3_TCRL_ERREN_MMRAERR_MASK (0x00000008u) +#define EDMA3_TCRL_ERREN_MMRAERR_SHIFT (0x00000003u) +#define EDMA3_TCRL_ERREN_MMRAERR_RESETVAL (0x00000000u) + +/*----MMRAERR Tokens----*/ +#define EDMA3_TCRL_ERREN_MMRAERR_ENABLE (0x00000001u) +#define EDMA3_TCRL_ERREN_MMRAERR_DISABLE (0x00000000u) + +#define EDMA3_TCRL_ERREN_TRERR_MASK (0x00000004u) +#define EDMA3_TCRL_ERREN_TRERR_SHIFT (0x00000002u) +#define EDMA3_TCRL_ERREN_TRERR_RESETVAL (0x00000000u) + +/*----TRERR Tokens----*/ +#define EDMA3_TCRL_ERREN_TRERR_ENABLE (0x00000001u) +#define EDMA3_TCRL_ERREN_TRERR_DISABLE (0x00000000u) + +#define EDMA3_TCRL_ERREN_BUSERR_MASK (0x00000001u) +#define EDMA3_TCRL_ERREN_BUSERR_SHIFT (0x00000000u) +#define EDMA3_TCRL_ERREN_BUSERR_RESETVAL (0x00000000u) + +/*----BUSERR Tokens----*/ +#define EDMA3_TCRL_ERREN_BUSERR_ENABLE (0x00000001u) +#define EDMA3_TCRL_ERREN_BUSERR_DISABLE (0x00000000u) + +#define EDMA3_TCRL_ERREN_RESETVAL (0x00000000u) + +/* ERRCLR */ + +#define EDMA3_TCRL_ERRCLR_MMRAERR_MASK (0x00000008u) +#define EDMA3_TCRL_ERRCLR_MMRAERR_SHIFT (0x00000003u) +#define EDMA3_TCRL_ERRCLR_MMRAERR_RESETVAL (0x00000000u) + +/*----MMRAERR Tokens----*/ +#define EDMA3_TCRL_ERRCLR_MMRAERR_CLEAR (0x00000001u) + +#define EDMA3_TCRL_ERRCLR_TRERR_MASK (0x00000004u) +#define EDMA3_TCRL_ERRCLR_TRERR_SHIFT (0x00000002u) +#define EDMA3_TCRL_ERRCLR_TRERR_RESETVAL (0x00000000u) + +/*----TRERR Tokens----*/ +#define EDMA3_TCRL_ERRCLR_TRERR_CLEAR (0x00000001u) + +#define EDMA3_TCRL_ERRCLR_BUSERR_MASK (0x00000001u) +#define EDMA3_TCRL_ERRCLR_BUSERR_SHIFT (0x00000000u) +#define EDMA3_TCRL_ERRCLR_BUSERR_RESETVAL (0x00000000u) + +/*----BUSERR Tokens----*/ +#define EDMA3_TCRL_ERRCLR_BUSERR_CLEAR (0x00000001u) + +#define EDMA3_TCRL_ERRCLR_RESETVAL (0x00000000u) + +/* ERRDET */ + +#define EDMA3_TCRL_ERRDET_TCCHEN_MASK (0x00020000u) +#define EDMA3_TCRL_ERRDET_TCCHEN_SHIFT (0x00000011u) +#define EDMA3_TCRL_ERRDET_TCCHEN_RESETVAL (0x00000000u) + +#define EDMA3_TCRL_ERRDET_TCINTEN_MASK (0x00010000u) +#define EDMA3_TCRL_ERRDET_TCINTEN_SHIFT (0x00000010u) +#define EDMA3_TCRL_ERRDET_TCINTEN_RESETVAL (0x00000000u) + +#define EDMA3_TCRL_ERRDET_TCC_MASK (0x00003F00u) +#define EDMA3_TCRL_ERRDET_TCC_SHIFT (0x00000008u) +#define EDMA3_TCRL_ERRDET_TCC_RESETVAL (0x00000000u) + +#define EDMA3_TCRL_ERRDET_STAT_MASK (0x0000000Fu) +#define EDMA3_TCRL_ERRDET_STAT_SHIFT (0x00000000u) +#define EDMA3_TCRL_ERRDET_STAT_RESETVAL (0x00000000u) + +/*----STAT Tokens----*/ +#define EDMA3_TCRL_ERRDET_STAT_NONE (0x00000000u) +#define EDMA3_TCRL_ERRDET_STAT_READ_ADDRESS (0x00000001u) +#define EDMA3_TCRL_ERRDET_STAT_READ_PRIVILEGE (0x00000002u) +#define EDMA3_TCRL_ERRDET_STAT_READ_TIMEOUT (0x00000003u) +#define EDMA3_TCRL_ERRDET_STAT_READ_DATA (0x00000004u) +#define EDMA3_TCRL_ERRDET_STAT_READ_EXCLUSIVE (0x00000007u) +#define EDMA3_TCRL_ERRDET_STAT_WRITE_ADDRESS (0x00000009u) +#define EDMA3_TCRL_ERRDET_STAT_WRITE_PRIVILEGE (0x0000000Au) +#define EDMA3_TCRL_ERRDET_STAT_WRITE_TIMEOUT (0x0000000Bu) +#define EDMA3_TCRL_ERRDET_STAT_WRITE_DATA (0x0000000Cu) +#define EDMA3_TCRL_ERRDET_STAT_WRITE_EXCLUSIVE (0x0000000Fu) + +#define EDMA3_TCRL_ERRDET_RESETVAL (0x00000000u) + +/* ERRCMD */ + +#define EDMA3_TCRL_ERRCMD_SET_MASK (0x00000002u) +#define EDMA3_TCRL_ERRCMD_SET_SHIFT (0x00000001u) +#define EDMA3_TCRL_ERRCMD_SET_RESETVAL (0x00000000u) + +/*----SET Tokens----*/ +#define EDMA3_TCRL_ERRCMD_SET_SET (0x00000001u) + +#define EDMA3_TCRL_ERRCMD_EVAL_MASK (0x00000001u) +#define EDMA3_TCRL_ERRCMD_EVAL_SHIFT (0x00000000u) +#define EDMA3_TCRL_ERRCMD_EVAL_RESETVAL (0x00000000u) + +/*----EVAL Tokens----*/ +#define EDMA3_TCRL_ERRCMD_EVAL_EVAL (0x00000001u) + +#define EDMA3_TCRL_ERRCMD_RESETVAL (0x00000000u) + +/* RDRATE */ + +#define EDMA3_TCRL_RDRATE_RDRATE_MASK (0x00000007u) +#define EDMA3_TCRL_RDRATE_RDRATE_SHIFT (0x00000000u) +#define EDMA3_TCRL_RDRATE_RDRATE_RESETVAL (0x00000000u) + +/*----RDRATE Tokens----*/ +#define EDMA3_TCRL_RDRATE_RDRATE_AFAP (0x00000000u) +#define EDMA3_TCRL_RDRATE_RDRATE_4CYCLE (0x00000001u) +#define EDMA3_TCRL_RDRATE_RDRATE_8CYCLE (0x00000002u) +#define EDMA3_TCRL_RDRATE_RDRATE_16CYCLE (0x00000003u) +#define EDMA3_TCRL_RDRATE_RDRATE_32CYCLE (0x00000004u) + +#define EDMA3_TCRL_RDRATE_RESETVAL (0x00000000u) + +/* POPT */ + +#define EDMA3_TCRL_POPT_TCCHEN_MASK (0x00400000u) +#define EDMA3_TCRL_POPT_TCCHEN_SHIFT (0x00000016u) +#define EDMA3_TCRL_POPT_TCCHEN_RESETVAL (0x00000000u) + +/*----TCCHEN Tokens----*/ +#define EDMA3_TCRL_POPT_TCCHEN_DISABLE (0x00000000u) +#define EDMA3_TCRL_POPT_TCCHEN_ENABLE (0x00000001u) + +#define EDMA3_TCRL_POPT_TCINTEN_MASK (0x00100000u) +#define EDMA3_TCRL_POPT_TCINTEN_SHIFT (0x00000014u) +#define EDMA3_TCRL_POPT_TCINTEN_RESETVAL (0x00000000u) + +/*----TCINTEN Tokens----*/ +#define EDMA3_TCRL_POPT_TCINTEN_DISABLE (0x00000000u) +#define EDMA3_TCRL_POPT_TCINTEN_ENABLE (0x00000001u) + +#define EDMA3_TCRL_POPT_TCC_MASK (0x0003F000u) +#define EDMA3_TCRL_POPT_TCC_SHIFT (0x0000000Cu) +#define EDMA3_TCRL_POPT_TCC_RESETVAL (0x00000000u) + +#define EDMA3_TCRL_POPT_FWID_MASK (0x00000700u) +#define EDMA3_TCRL_POPT_FWID_SHIFT (0x00000008u) +#define EDMA3_TCRL_POPT_FWID_RESETVAL (0x00000000u) + +/*----FWID Tokens----*/ +#define EDMA3_TCRL_POPT_FWID_8BIT (0x00000000u) +#define EDMA3_TCRL_POPT_FWID_16BIT (0x00000001u) +#define EDMA3_TCRL_POPT_FWID_32BIT (0x00000002u) +#define EDMA3_TCRL_POPT_FWID_64BIT (0x00000003u) +#define EDMA3_TCRL_POPT_FWID_128BIT (0x00000004u) +#define EDMA3_TCRL_POPT_FWID_256BIT (0x00000005u) + +#define EDMA3_TCRL_POPT_PRI_MASK (0x00000070u) +#define EDMA3_TCRL_POPT_PRI_SHIFT (0x00000004u) +#define EDMA3_TCRL_POPT_PRI_RESETVAL (0x00000000u) + +#define EDMA3_TCRL_POPT_DAM_MASK (0x00000002u) +#define EDMA3_TCRL_POPT_DAM_SHIFT (0x00000001u) +#define EDMA3_TCRL_POPT_DAM_RESETVAL (0x00000000u) + +/*----DAM Tokens----*/ +#define EDMA3_TCRL_POPT_DAM_INCR (0x00000000u) +#define EDMA3_TCRL_POPT_DAM_FIFO (0x00000001u) + +#define EDMA3_TCRL_POPT_SAM_MASK (0x00000001u) +#define EDMA3_TCRL_POPT_SAM_SHIFT (0x00000000u) +#define EDMA3_TCRL_POPT_SAM_RESETVAL (0x00000000u) + +/*----SAM Tokens----*/ +#define EDMA3_TCRL_POPT_SAM_INCR (0x00000000u) +#define EDMA3_TCRL_POPT_SAM_FIFO (0x00000001u) + +#define EDMA3_TCRL_POPT_RESETVAL (0x00000000u) + +/* PSRC */ + +#define EDMA3_TCRL_PSRC_SADDR_MASK (0xFFFFFFFFu) +#define EDMA3_TCRL_PSRC_SADDR_SHIFT (0x00000000u) +#define EDMA3_TCRL_PSRC_SADDR_RESETVAL (0x00000000u) + +#define EDMA3_TCRL_PSRC_RESETVAL (0x00000000u) + +/* PCNT */ + +#define EDMA3_TCRL_PCNT_BCNT_MASK (0xFFFF0000u) +#define EDMA3_TCRL_PCNT_BCNT_SHIFT (0x00000010u) +#define EDMA3_TCRL_PCNT_BCNT_RESETVAL (0x00000000u) + +#define EDMA3_TCRL_PCNT_ACNT_MASK (0x0000FFFFu) +#define EDMA3_TCRL_PCNT_ACNT_SHIFT (0x00000000u) +#define EDMA3_TCRL_PCNT_ACNT_RESETVAL (0x00000000u) + +#define EDMA3_TCRL_PCNT_RESETVAL (0x00000000u) + +/* PDST */ + +#define EDMA3_TCRL_PDST_DADDR_MASK (0xFFFFFFFFu) +#define EDMA3_TCRL_PDST_DADDR_SHIFT (0x00000000u) +#define EDMA3_TCRL_PDST_DADDR_RESETVAL (0x00000000u) + +#define EDMA3_TCRL_PDST_RESETVAL (0x00000000u) + +/* PBIDX */ + +#define EDMA3_TCRL_PBIDX_DBIDX_MASK (0xFFFF0000u) +#define EDMA3_TCRL_PBIDX_DBIDX_SHIFT (0x00000010u) +#define EDMA3_TCRL_PBIDX_DBIDX_RESETVAL (0x00000000u) + +#define EDMA3_TCRL_PBIDX_SBIDX_MASK (0x0000FFFFu) +#define EDMA3_TCRL_PBIDX_SBIDX_SHIFT (0x00000000u) +#define EDMA3_TCRL_PBIDX_SBIDX_RESETVAL (0x00000000u) + +#define EDMA3_TCRL_PBIDX_RESETVAL (0x00000000u) + +/* PMPPRXY */ + +#define EDMA3_TCRL_PMPPRXY_PRIV_MASK (0x00000100u) +#define EDMA3_TCRL_PMPPRXY_PRIV_SHIFT (0x00000008u) +#define EDMA3_TCRL_PMPPRXY_PRIV_RESETVAL (0x00000000u) + +/*----PRIV Tokens----*/ +#define EDMA3_TCRL_PMPPRXY_PRIV_USER (0x00000000u) +#define EDMA3_TCRL_PMPPRXY_PRIV_SUPERVISOR (0x00000001u) + +#define EDMA3_TCRL_PMPPRXY_PRIVID_MASK (0x0000000Fu) +#define EDMA3_TCRL_PMPPRXY_PRIVID_SHIFT (0x00000000u) +#define EDMA3_TCRL_PMPPRXY_PRIVID_RESETVAL (0x00000000u) + +#define EDMA3_TCRL_PMPPRXY_RESETVAL (0x00000000u) + +/* SAOPT */ + +#define EDMA3_TCRL_SAOPT_TCCHEN_MASK (0x00400000u) +#define EDMA3_TCRL_SAOPT_TCCHEN_SHIFT (0x00000016u) +#define EDMA3_TCRL_SAOPT_TCCHEN_RESETVAL (0x00000000u) + +/*----TCCHEN Tokens----*/ +#define EDMA3_TCRL_SAOPT_TCCHEN_DISABLE (0x00000000u) +#define EDMA3_TCRL_SAOPT_TCCHEN_ENABLE (0x00000001u) + +#define EDMA3_TCRL_SAOPT_TCINTEN_MASK (0x00100000u) +#define EDMA3_TCRL_SAOPT_TCINTEN_SHIFT (0x00000014u) +#define EDMA3_TCRL_SAOPT_TCINTEN_RESETVAL (0x00000000u) + +/*----TCINTEN Tokens----*/ +#define EDMA3_TCRL_SAOPT_TCINTEN_DISABLE (0x00000000u) +#define EDMA3_TCRL_SAOPT_TCINTEN_ENABLE (0x00000001u) + +#define EDMA3_TCRL_SAOPT_TCC_MASK (0x0003F000u) +#define EDMA3_TCRL_SAOPT_TCC_SHIFT (0x0000000Cu) +#define EDMA3_TCRL_SAOPT_TCC_RESETVAL (0x00000000u) + +#define EDMA3_TCRL_SAOPT_FWID_MASK (0x00000700u) +#define EDMA3_TCRL_SAOPT_FWID_SHIFT (0x00000008u) +#define EDMA3_TCRL_SAOPT_FWID_RESETVAL (0x00000000u) + +/*----FWID Tokens----*/ +#define EDMA3_TCRL_SAOPT_FWID_8BIT (0x00000000u) +#define EDMA3_TCRL_SAOPT_FWID_16BIT (0x00000001u) +#define EDMA3_TCRL_SAOPT_FWID_32BIT (0x00000002u) +#define EDMA3_TCRL_SAOPT_FWID_64BIT (0x00000003u) +#define EDMA3_TCRL_SAOPT_FWID_128BIT (0x00000004u) +#define EDMA3_TCRL_SAOPT_FWID_256BIT (0x00000005u) + +#define EDMA3_TCRL_SAOPT_PRI_MASK (0x00000070u) +#define EDMA3_TCRL_SAOPT_PRI_SHIFT (0x00000004u) +#define EDMA3_TCRL_SAOPT_PRI_RESETVAL (0x00000000u) + +#define EDMA3_TCRL_SAOPT_DAM_MASK (0x00000002u) +#define EDMA3_TCRL_SAOPT_DAM_SHIFT (0x00000001u) +#define EDMA3_TCRL_SAOPT_DAM_RESETVAL (0x00000000u) + +/*----DAM Tokens----*/ +#define EDMA3_TCRL_SAOPT_DAM_INCR (0x00000000u) +#define EDMA3_TCRL_SAOPT_DAM_FIFO (0x00000001u) + +#define EDMA3_TCRL_SAOPT_SAM_MASK (0x00000001u) +#define EDMA3_TCRL_SAOPT_SAM_SHIFT (0x00000000u) +#define EDMA3_TCRL_SAOPT_SAM_RESETVAL (0x00000000u) + +/*----SAM Tokens----*/ +#define EDMA3_TCRL_SAOPT_SAM_INCR (0x00000000u) +#define EDMA3_TCRL_SAOPT_SAM_FIFO (0x00000001u) + +#define EDMA3_TCRL_SAOPT_RESETVAL (0x00000000u) + +/* SASRC */ + +#define EDMA3_TCRL_SASRC_SADDR_MASK (0xFFFFFFFFu) +#define EDMA3_TCRL_SASRC_SADDR_SHIFT (0x00000000u) +#define EDMA3_TCRL_SASRC_SADDR_RESETVAL (0x00000000u) + +#define EDMA3_TCRL_SASRC_RESETVAL (0x00000000u) + +/* SACNT */ + +#define EDMA3_TCRL_SACNT_BCNT_MASK (0xFFFF0000u) +#define EDMA3_TCRL_SACNT_BCNT_SHIFT (0x00000010u) +#define EDMA3_TCRL_SACNT_BCNT_RESETVAL (0x00000000u) + +#define EDMA3_TCRL_SACNT_ACNT_MASK (0x0000FFFFu) +#define EDMA3_TCRL_SACNT_ACNT_SHIFT (0x00000000u) +#define EDMA3_TCRL_SACNT_ACNT_RESETVAL (0x00000000u) + +#define EDMA3_TCRL_SACNT_RESETVAL (0x00000000u) + +/* SADST */ + +#define EDMA3_TCRL_SADST_RESETVAL (0x00000000u) + +/* SABIDX */ + +#define EDMA3_TCRL_SABIDX_DBIDX_MASK (0xFFFF0000u) +#define EDMA3_TCRL_SABIDX_DBIDX_SHIFT (0x00000010u) +#define EDMA3_TCRL_SABIDX_DBIDX_RESETVAL (0x00000000u) + +#define EDMA3_TCRL_SABIDX_SBIDX_MASK (0x0000FFFFu) +#define EDMA3_TCRL_SABIDX_SBIDX_SHIFT (0x00000000u) +#define EDMA3_TCRL_SABIDX_SBIDX_RESETVAL (0x00000000u) + +#define EDMA3_TCRL_SABIDX_RESETVAL (0x00000000u) + +/* SAMPPRXY */ + +#define EDMA3_TCRL_SAMPPRXY_PRIV_MASK (0x00000100u) +#define EDMA3_TCRL_SAMPPRXY_PRIV_SHIFT (0x00000008u) +#define EDMA3_TCRL_SAMPPRXY_PRIV_RESETVAL (0x00000000u) + +/*----PRIV Tokens----*/ +#define EDMA3_TCRL_SAMPPRXY_PRIV_USER (0x00000000u) +#define EDMA3_TCRL_SAMPPRXY_PRIV_SUPERVISOR (0x00000001u) + +#define EDMA3_TCRL_SAMPPRXY_PRIVID_MASK (0x0000000Fu) +#define EDMA3_TCRL_SAMPPRXY_PRIVID_SHIFT (0x00000000u) +#define EDMA3_TCRL_SAMPPRXY_PRIVID_RESETVAL (0x00000000u) + +#define EDMA3_TCRL_SAMPPRXY_RESETVAL (0x00000000u) + +/* SACNTRLD */ + +#define EDMA3_TCRL_SACNTRLD_ACNTRLD_MASK (0x0000FFFFu) +#define EDMA3_TCRL_SACNTRLD_ACNTRLD_SHIFT (0x00000000u) +#define EDMA3_TCRL_SACNTRLD_ACNTRLD_RESETVAL (0x00000000u) + +#define EDMA3_TCRL_SACNTRLD_RESETVAL (0x00000000u) + +/* SASRCBREF */ + +#define EDMA3_TCRL_SASRCBREF_SADDRBREFG_MASK (0xFFFFFFFFu) +#define EDMA3_TCRL_SASRCBREF_SADDRBREFG_SHIFT (0x00000000u) +#define EDMA3_TCRL_SASRCBREF_SADDRBREFG_RESETVAL (0x00000000u) + +#define EDMA3_TCRL_SASRCBREF_RESETVAL (0x00000000u) + +/* SADSTBREF */ + +#define EDMA3_TCRL_SADSTBREF_RESETVAL (0x00000000u) + +/* DFCNTRLD */ + +#define EDMA3_TCRL_DFCNTRLD_ACNTRLD_MASK (0x0000FFFFu) +#define EDMA3_TCRL_DFCNTRLD_ACNTRLD_SHIFT (0x00000000u) +#define EDMA3_TCRL_DFCNTRLD_ACNTRLD_RESETVAL (0x00000000u) + +#define EDMA3_TCRL_DFCNTRLD_RESETVAL (0x00000000u) + +/* DFSRCBREF */ + +#define EDMA3_TCRL_DFSRCBREF_RESETVAL (0x00000000u) + +/* DFDSTBREF */ + +#define EDMA3_TCRL_DFDSTBREF_DADDRBREF_MASK (0xFFFFFFFFu) +#define EDMA3_TCRL_DFDSTBREF_DADDRBREF_SHIFT (0x00000000u) +#define EDMA3_TCRL_DFDSTBREF_DADDRBREF_RESETVAL (0x00000000u) + +#define EDMA3_TCRL_DFDSTBREF_RESETVAL (0x00000000u) + +/* DFOPT */ + +#define EDMA3_TCRL_DFOPT_TCCHEN_MASK (0x00400000u) +#define EDMA3_TCRL_DFOPT_TCCHEN_SHIFT (0x00000016u) +#define EDMA3_TCRL_DFOPT_TCCHEN_RESETVAL (0x00000000u) + +/*----TCCHEN Tokens----*/ +#define EDMA3_TCRL_DFOPT_TCCHEN_DISABLE (0x00000000u) +#define EDMA3_TCRL_DFOPT_TCCHEN_ENABLE (0x00000001u) + +#define EDMA3_TCRL_DFOPT_TCINTEN_MASK (0x00100000u) +#define EDMA3_TCRL_DFOPT_TCINTEN_SHIFT (0x00000014u) +#define EDMA3_TCRL_DFOPT_TCINTEN_RESETVAL (0x00000000u) + +/*----TCINTEN Tokens----*/ +#define EDMA3_TCRL_DFOPT_TCINTEN_DISABLE (0x00000000u) +#define EDMA3_TCRL_DFOPT_TCINTEN_ENABLE (0x00000001u) + +#define EDMA3_TCRL_DFOPT_TCC_MASK (0x0003F000u) +#define EDMA3_TCRL_DFOPT_TCC_SHIFT (0x0000000Cu) +#define EDMA3_TCRL_DFOPT_TCC_RESETVAL (0x00000000u) + +#define EDMA3_TCRL_DFOPT_FWID_MASK (0x00000700u) +#define EDMA3_TCRL_DFOPT_FWID_SHIFT (0x00000008u) +#define EDMA3_TCRL_DFOPT_FWID_RESETVAL (0x00000000u) + +/*----FWID Tokens----*/ +#define EDMA3_TCRL_DFOPT_FWID_8BIT (0x00000000u) +#define EDMA3_TCRL_DFOPT_FWID_16BIT (0x00000001u) +#define EDMA3_TCRL_DFOPT_FWID_32BIT (0x00000002u) +#define EDMA3_TCRL_DFOPT_FWID_64BIT (0x00000003u) +#define EDMA3_TCRL_DFOPT_FWID_128BIT (0x00000004u) +#define EDMA3_TCRL_DFOPT_FWID_256BIT (0x00000005u) + +#define EDMA3_TCRL_DFOPT_PRI_MASK (0x00000070u) +#define EDMA3_TCRL_DFOPT_PRI_SHIFT (0x00000004u) +#define EDMA3_TCRL_DFOPT_PRI_RESETVAL (0x00000000u) + +#define EDMA3_TCRL_DFOPT_DAM_MASK (0x00000002u) +#define EDMA3_TCRL_DFOPT_DAM_SHIFT (0x00000001u) +#define EDMA3_TCRL_DFOPT_DAM_RESETVAL (0x00000000u) + +/*----DAM Tokens----*/ +#define EDMA3_TCRL_DFOPT_DAM_INCR (0x00000000u) +#define EDMA3_TCRL_DFOPT_DAM_FIFO (0x00000001u) + +#define EDMA3_TCRL_DFOPT_SAM_MASK (0x00000001u) +#define EDMA3_TCRL_DFOPT_SAM_SHIFT (0x00000000u) +#define EDMA3_TCRL_DFOPT_SAM_RESETVAL (0x00000000u) + +/*----SAM Tokens----*/ +#define EDMA3_TCRL_DFOPT_SAM_INCR (0x00000000u) +#define EDMA3_TCRL_DFOPT_SAM_FIFO (0x00000001u) + +#define EDMA3_TCRL_DFOPT_RESETVAL (0x00000000u) + +/* DFSRC */ + +#define EDMA3_TCRL_DFSRC_RESETVAL (0x00000000u) + +/* DFCNT */ + +#define EDMA3_TCRL_DFCNT_BCNT_MASK (0xFFFF0000u) +#define EDMA3_TCRL_DFCNT_BCNT_SHIFT (0x00000010u) +#define EDMA3_TCRL_DFCNT_BCNT_RESETVAL (0x00000000u) + +#define EDMA3_TCRL_DFCNT_ACNT_MASK (0x0000FFFFu) +#define EDMA3_TCRL_DFCNT_ACNT_SHIFT (0x00000000u) +#define EDMA3_TCRL_DFCNT_ACNT_RESETVAL (0x00000000u) + +#define EDMA3_TCRL_DFCNT_RESETVAL (0x00000000u) + +/* DFDST */ + +#define EDMA3_TCRL_DFDST_DADDR_MASK (0xFFFFFFFFu) +#define EDMA3_TCRL_DFDST_DADDR_SHIFT (0x00000000u) +#define EDMA3_TCRL_DFDST_DADDR_RESETVAL (0x00000000u) + +#define EDMA3_TCRL_DFDST_RESETVAL (0x00000000u) + +/* DFBIDX */ + +#define EDMA3_TCRL_DFBIDX_DBIDX_MASK (0xFFFF0000u) +#define EDMA3_TCRL_DFBIDX_DBIDX_SHIFT (0x00000010u) +#define EDMA3_TCRL_DFBIDX_DBIDX_RESETVAL (0x00000000u) + +#define EDMA3_TCRL_DFBIDX_SBIDX_MASK (0x0000FFFFu) +#define EDMA3_TCRL_DFBIDX_SBIDX_SHIFT (0x00000000u) +#define EDMA3_TCRL_DFBIDX_SBIDX_RESETVAL (0x00000000u) + +#define EDMA3_TCRL_DFBIDX_RESETVAL (0x00000000u) + +/* DFMPPRXY */ + +#define EDMA3_TCRL_DFMPPRXY_PRIV_MASK (0x00000100u) +#define EDMA3_TCRL_DFMPPRXY_PRIV_SHIFT (0x00000008u) +#define EDMA3_TCRL_DFMPPRXY_PRIV_RESETVAL (0x00000000u) + +/*----PRIV Tokens----*/ +#define EDMA3_TCRL_DFMPPRXY_PRIV_USER (0x00000000u) +#define EDMA3_TCRL_DFMPPRXY_PRIV_SUPERVISOR (0x00000001u) + +#define EDMA3_TCRL_DFMPPRXY_PRIVID_MASK (0x0000000Fu) +#define EDMA3_TCRL_DFMPPRXY_PRIVID_SHIFT (0x00000000u) +#define EDMA3_TCRL_DFMPPRXY_PRIVID_RESETVAL (0x00000000u) + +#define EDMA3_TCRL_DFMPPRXY_RESETVAL (0x00000000u) + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif /* _EDMA3_RL_TC_H_ */ diff --git a/packages/ti/sdo/edma3/rm/src/edma3_rm_gbl_data.c b/packages/ti/sdo/edma3/rm/src/edma3_rm_gbl_data.c new file mode 100644 index 0000000..69da8d7 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/src/edma3_rm_gbl_data.c @@ -0,0 +1,85 @@ +/****************************************************************************** +**+-------------------------------------------------------------------------+** +**| **** |** +**| **** |** +**| ******o*** |** +**| ********_///_**** |** +**| ***** /_//_/ **** |** +**| ** ** (__/ **** |** +**| ********* |** +**| **** |** +**| *** |** +**| |** +**| Copyright (c) 1998-2006 Texas Instruments Incorporated |** +**| ALL RIGHTS RESERVED |** +**| |** +**| Permission is hereby granted to licensees of Texas Instruments |** +**| Incorporated (TI) products to use this computer program for the sole |** +**| purpose of implementing a licensee product based on TI products. |** +**| No other rights to reproduce, use, or disseminate this computer |** +**| program, whether in part or in whole, are granted. |** +**| |** +**| TI makes no representation or warranties with respect to the |** +**| performance of this computer program, and specifically disclaims |** +**| any responsibility for any damages, special or consequential, |** +**| connected with the use of this program. |** +**| |** +**+-------------------------------------------------------------------------+** +******************************************************************************/ + +/** \file edma3_rm_gbl_data.c + \brief Source file for the Resource Manager, for internal + data structures. + + (C) Copyright 2006, Texas Instruments, Inc + + \version + 0.1.0 Anuj Aggarwal - Created + + */ + +/* Resource Manager Internal Header Files */ +#include + +/** + * Maximum Resource Manager Instances supported by the EDMA3 Package. + * USE THE SAME VALUE FOR BOTH THE #DEFINE AND CONST UNSIGNED INT BELOW. + */ +/* This #define is needed for array declarations. */ +#define MAX_EDMA3_RM_INSTANCES (8u) +/* This const is required to access this constant in other header files */ +const unsigned int EDMA3_MAX_RM_INSTANCES = 8u; + +/** + * \brief Region Specific Configuration structure for + * EDMA3 controller, to provide region specific Information. + * + * This configuration info can also be provided by the user at run-time, + * while calling EDMA3_RM_open (). If not provided at run-time, + * this info will be taken from the config file "edma3__cfg.c", + * for the specified platform. + */ +EDMA3_RM_InstanceInitConfig userInstInitConfigArray[EDMA3_MAX_EDMA3_INSTANCES][MAX_EDMA3_RM_INSTANCES]; + + +/** + * Handles of EDMA3 Resource Manager Instances. + * + * Used to maintain information of the EDMA3 RM Instances + * for each HW controller. + * There could be a maximum of EDMA3_MAX_RM_INSTANCES instances per + * EDMA3 HW. + */ +EDMA3_RM_Instance resMgrInstanceArray[EDMA3_MAX_EDMA3_INSTANCES][MAX_EDMA3_RM_INSTANCES]; + +/* These pointers will be used to refer the above mentioned arrays. */ +EDMA3_RM_Instance *resMgrInstance = (EDMA3_RM_Instance *)resMgrInstanceArray; +EDMA3_RM_InstanceInitConfig *userInitConfig = (EDMA3_RM_InstanceInitConfig *)userInstInitConfigArray; + +/* Pointer to the above mentioned 2-D arrays, used for address calculation purpose */ +EDMA3_RM_Instance *ptrRMIArray = (EDMA3_RM_Instance *)resMgrInstanceArray; +EDMA3_RM_InstanceInitConfig *ptrInitCfgArray = (EDMA3_RM_InstanceInitConfig *)userInstInitConfigArray; + + + + diff --git a/packages/ti/sdo/edma3/rm/src/edma3resmgr.c b/packages/ti/sdo/edma3/rm/src/edma3resmgr.c new file mode 100644 index 0000000..c7f97cc --- /dev/null +++ b/packages/ti/sdo/edma3/rm/src/edma3resmgr.c @@ -0,0 +1,7310 @@ +/******************************************************************************* +**+--------------------------------------------------------------------------+** +**| **** |** +**| **** |** +**| ******o*** |** +**| ********_///_**** |** +**| ***** /_//_/ **** |** +**| ** ** (__/ **** |** +**| ********* |** +**| **** |** +**| *** |** +**| |** +**| Copyright (c) 1998-2006 Texas Instruments Incorporated |** +**| ALL RIGHTS RESERVED |** +**| |** +**| Permission is hereby granted to licensees of Texas Instruments |** +**| Incorporated (TI) products to use this computer program for the sole |** +**| purpose of implementing a licensee product based on TI products. |** +**| No other rights to reproduce, use, or disseminate this computer |** +**| program, whether in part or in whole, are granted. |** +**| |** +**| TI makes no representation or warranties with respect to the |** +**| performance of this computer program, and specifically disclaims |** +**| any responsibility for any damages, special or consequential, |** +**| connected with the use of this program. |** +**| |** +**+--------------------------------------------------------------------------+** +*******************************************************************************/ + +/** \file edma3resmgr.c + \brief EDMA3 Controller Resource Manager Interface Implementation + + This file contains Resource Manager Implementation for the EDMA3 Controller. + + (C) Copyright 2006, Texas Instruments, Inc + + \version 0.0.1 Purushotam Kumar - Created + 0.1.0 Joseph Fernandez - Made generic + - Added documentation + - Moved SoC specific defines + to SoC specific header. + 0.2.0 Anuj Aggarwal - Modified it for EDMA3 package + - Added multiple instances + capability + 0.2.1 Anuj Aggarwal - Modified it for more run time + configuration. + - Made EDMA3 package OS + independent. + 0.2.2 Anuj Aggarwal - Critical section handling code + modification. Uses semaphore and + interrupts disabling mechanism + for resource sharing. + 0.3.0 Anuj Aggarwal - Renamed EDMA3_DVR to EDMA3_DRV + - IPR bit clearing in RM ISR + issue fixed. + - Sample application made generic + 0.3.1 Anuj Aggarwal - Added DMA/QDMA Channel to TCC + mapping, to fix QDMA missed + event issue. + 0.3.2 Anuj Aggarwal - Added support for POLL mode + - Added a new API to modify the + CC Register. + 1.0.0 Anuj Aggarwal - Fixed resource allocation related + bugs. + 1.0.0.1 Anuj Aggarwal - Fixed spurious missed event + generation related bug. + 1.0.0.2 Anuj Aggarwal - Made the EDMA3 package RTSC + compliant. + 1.0.0.3 Anuj Aggarwal - Changed the directory structure + as per RTSC standard. + 1.01.00.01 Anuj Aggarwal - a) Added new APIs to allocate + logical channels + b) Created EDMA3 config files + for different platforms + c) Misc changes + 1.02.00.01 Anuj Aggarwal - a) Added DM6467 support + b) Fixed some MRs + 1.03.00.01 Anuj Aggarwal - a) Added non-RTSC PJT files + b) IOCTL Interface added. + c) Fixed some MRs. + 1.04 Anuj Aggarwal - a) Added new IOCTLs and APIs. + b) Number of maximum Resource + Manager Instances is configurable. + c) Header files modified to have + extern "C" declarations. + + */ + +/* Resource Manager Internal Header Files */ +#include + +/* Instrumentation Header File */ +#ifdef EDMA3_INSTRUMENTATION_ENABLED +#include +#endif + +/* For assert() */ +/** + * Define NDEBUG to ignore assert(). + * NDEBUG should be defined before including assert.h header file. + */ +#include + + +/* Global Defines, need to re-compile if values are changed */ +/*---------------------------------------------------------------------------*/ +/** + * \brief EDMA3 Resource Manager behaviour of clearing CC ERROR interrupts. + * This macro controls the driver to enable/disable clearing of error + * status of all channels. + * + * On disabling this (with value 0x0), the channels owned by the region + * is cleared and its expected that some other entity is responsible for + * clearing the error status for channels not owned. + * + * Its recomended that this flag is a positive value, to ensure that + * error flags are cleared for all the channels. + */ +#define EDMA3_RM_RES_CLEAR_ERROR_STATUS_FOR_ALL_CHANNELS (TRUE) + +/** + * \brief EDMA3 Resource Manager retry count to check the pending interrupts inside ISR. + * This macro controls the driver to check the pending interrupt for + * 'n' number of times. + * Minumum value is 1. + */ +#define EDMA3_RM_COMPL_HANDLER_RETRY_COUNT (10u) + +/** + * \brief EDMA3 Resource Manager retry count to check the pending CC Error Interrupt inside ISR + * This macro controls the driver to check the pending CC Error + * interrupt for 'n' number of times. + * Minumum value is 1. + */ +#define EDMA3_RM_CCERR_HANDLER_RETRY_COUNT (10u) + + + +/* Externel Variables */ +/*---------------------------------------------------------------------------*/ +/** + * Maximum Resource Manager Instances supported by the EDMA3 Package. + */ +extern const unsigned int EDMA3_MAX_RM_INSTANCES; + + +/** + * \brief Static Configuration structure for EDMA3 + * controller, to provide Global SoC specific Information. + * + * This configuration info can also be provided by the user at run-time, + * while calling EDMA3_RM_create (). If not provided at run-time, + * this info will be taken from the config file "edma3__cfg.c", + * for the specified platform. + */ +extern EDMA3_RM_GblConfigParams edma3GblCfgParams [EDMA3_MAX_EDMA3_INSTANCES]; + +/** + * \brief Default Static Region Specific Configuration structure for + * EDMA3 controller, to provide region specific Information. + */ +extern EDMA3_RM_InstanceInitConfig defInstInitConfig [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS]; + + +/** + * \brief Region Specific Configuration structure for + * EDMA3 controller, to provide region specific Information. + * + * This configuration info can also be provided by the user at run-time, + * while calling EDMA3_RM_open (). If not provided at run-time, + * this info will be taken from the config file "edma3__cfg.c", + * for the specified platform. + */ +extern EDMA3_RM_InstanceInitConfig *userInitConfig; +extern EDMA3_RM_InstanceInitConfig *ptrInitCfgArray; + + +/** + * Handles of EDMA3 Resource Manager Instances. + * + * Used to maintain information of the EDMA3 RM Instances + * for each HW controller. + * There could be a maximum of EDMA3_MAX_RM_INSTANCES instances per + * EDMA3 HW. + */ +extern EDMA3_RM_Instance *resMgrInstance; +extern EDMA3_RM_Instance *ptrRMIArray; + + + +/* Globals */ +/*---------------------------------------------------------------------------*/ +/** + * \brief EDMA3 Resource Manager Objects, tied to each EDMA3 HW Controller. + * + * Typically one RM object will cater to one EDMA3 HW controller + * and will have all the global config information. + */ +EDMA3_RM_Obj resMgrObj[EDMA3_MAX_EDMA3_INSTANCES]; + + +/** + * Global Array to store the mapping between DMA channels and Interrupt + * channels i.e. TCCs. + * DMA channel X can use any TCC Y. Transfer completion + * interrupt will occur on the TCC Y (IPR/IPRH Register, bit Y), but error + * interrupt will occur on DMA channel X (EMR/EMRH register, bit X). In that + * scenario, this DMA channel <-> TCC mapping will be used to point to + * the correct callback function. + */ +static unsigned int edma3DmaChTccMapping [EDMA3_MAX_DMA_CH]; + + +/** + * Global Array to store the mapping between QDMA channels and Interrupt + * channels i.e. TCCs. + * QDMA channel X can use any TCC Y. Transfer completion + * interrupt will occur on the TCC Y (IPR/IPRH Register, bit Y), but error + * interrupt will occur on QDMA channel X (QEMR register, bit X). In that + * scenario, this QDMA channel <-> TCC mapping will be used to point to + * the correct callback function. + */ +static unsigned int edma3QdmaChTccMapping [EDMA3_MAX_QDMA_CH]; + + +/** + * Global Array to maintain the Callback details registered + * against a particular TCC. Used to call the callback + * functions linked to the particular channel. + */ +static EDMA3_RM_TccCallbackParams edma3IntrParams [EDMA3_MAX_TCC]; + + +/** edma3RegionId will be updated ONCE using the parameter regionId passed to + * the EDMA3_RM_open() function, for the Master RM instance (one who + * configures the Global Registers). + * This global variable will be used within the Interrupt handlers to know + * which shadow region registers to access. All other interrupts coming + * from other shadow regions will not be handled. + */ +static EDMA3_RM_RegionId edma3RegionId = EDMA3_MAX_REGIONS; + +/** masterExists will be updated when the Master RM Instance modifies the + * Global EDMA3 configuration registers. It is used to prevent any other + * Master RM Instance creation. + */ +static unsigned short masterExists = FALSE; + +/** + * Number of PaRAM Sets actually present on the SoC. This will be updated + * while creating the Resource Manager Object. + */ +unsigned int edma3NumPaRAMSets = EDMA3_MAX_PARAM_SETS; + + +/** + * The list of Interrupt Channels which get allocated while requesting the + * TCC. It will be used while checking the IPR/IPRH bits in the RM ISR. + */ +static unsigned int allocatedTCCs[2u] = {0x0u, 0x0u}; + + +/** + * Arrays ownDmaChannels[], resvdDmaChannels and avlblDmaChannels will be ANDed + * and stored in this array. It will be referenced in + * EDMA3_RM_allocContiguousResource () to look for contiguous resources. + */ +static unsigned int contiguousDmaRes[EDMA3_MAX_DMA_CHAN_DWRDS] = {0x0u, 0x0u}; + +/** + * Arrays ownDmaChannels[], resvdDmaChannels and avlblDmaChannels will be ANDed + * and stored in this array. It will be referenced in + * EDMA3_RM_allocContiguousResource () to look for contiguous resources. + */ +static unsigned int contiguousQdmaRes[EDMA3_MAX_QDMA_CHAN_DWRDS] = {0x0u}; + +/** + * Arrays ownDmaChannels[], resvdDmaChannels and avlblDmaChannels will be ANDed + * and stored in this array. It will be referenced in + * EDMA3_RM_allocContiguousResource () to look for contiguous resources. + */ +static unsigned int contiguousTccRes[EDMA3_MAX_TCC_DWRDS] = {0x0u, 0x0u}; + +/** + * Arrays ownDmaChannels[], resvdDmaChannels and avlblDmaChannels will be ANDed + * and stored in this array. It will be referenced in + * EDMA3_RM_allocContiguousResource () to look for contiguous resources. + */ +static unsigned int contiguousParamRes[EDMA3_MAX_PARAM_DWRDS]; + + +/** + * \brief Resources bound to a Channel + * + * When a request for a channel is made, the resources PaRAM Set and TCC + * get bound to that channel. This information is needed internally by the + * resource manager, when a request is made to free the channel, + * to free up the channel-associated resources. + */ +static EDMA3_RM_ChBoundResources edma3RmChBoundRes [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_LOGICAL_CH]; + + + +/*---------------------------------------------------------------------------*/ + +/* Local functions prototypes */ +/*---------------------------------------------------------------------------*/ +/** EDMA3 Instance 0 Completion Handler Interrupt Service Routine */ +void lisrEdma3ComplHandler0(unsigned int arg); +/** EDMA3 Instance 0 CC Error Interrupt Service Routine */ +void lisrEdma3CCErrHandler0(unsigned int arg); +/** + * EDMA3 Instance 0 TC[0-7] Error Interrupt Service Routines + * for a maximum of 8 TCs (Transfer Controllers). + */ +void lisrEdma3TC0ErrHandler0(unsigned int arg); +void lisrEdma3TC1ErrHandler0(unsigned int arg); +void lisrEdma3TC2ErrHandler0(unsigned int arg); +void lisrEdma3TC3ErrHandler0(unsigned int arg); +void lisrEdma3TC4ErrHandler0(unsigned int arg); +void lisrEdma3TC5ErrHandler0(unsigned int arg); +void lisrEdma3TC6ErrHandler0(unsigned int arg); +void lisrEdma3TC7ErrHandler0(unsigned int arg); + + +/** Interrupt Handler for the Transfer Completion interrupt */ +static void edma3ComplHandler (const EDMA3_RM_Obj *rmObj); +/** Interrupt Handler for the Channel Controller Error interrupt */ +static void edma3CCErrHandler (const EDMA3_RM_Obj *rmObj); +/** Interrupt Handler for the Transfer Controller Error interrupt */ +static void edma3TCErrHandler (const EDMA3_RM_Obj *rmObj, unsigned int tcNum); + + +/** Local MemSet function */ +void edma3MemSet(void *dst, unsigned char data, unsigned int len); +/** Local MemCpy function */ +void edma3MemCpy(void *dst, const void *src, unsigned int len); + +/** Initialization of the Global region registers of the EDMA3 Controller */ +static void edma3GlobalRegionInit (unsigned int phyCtrllerInstId); +/** Initialization of the Shadow region registers of the EDMA3 Controller */ +static void edma3ShadowRegionInit (const EDMA3_RM_Instance *pRMInstance); + + + +/* Internal functions for contiguous resource allocation */ +/** + * Finds a particular bit ('0' or '1') in the particular word from 'start'. + * If found, returns the position, else return -1. + */ +static int findBitInWord (int source, unsigned int start, unsigned short bit); + +/** + * Finds a particular bit ('0' or '1') in the specified resources' array + * from 'start' to 'end'. If found, returns the position, else return -1. + */ +static int findBit (EDMA3_RM_ResType resType, + unsigned int start, + unsigned int end, + unsigned short bit); + +/** + * If successful, this function returns EDMA3_RM_SOK and the position + * of first available resource in 'positionRes'. Else returns error. + */ +static EDMA3_RM_Result allocAnyContigRes(EDMA3_RM_ResType resType, + unsigned int numResources, + unsigned int *positionRes); + +/** + * Starting from 'firstResIdObj', this function makes the next 'numResources' + * Resources non-available for future. Also, it does some global resisters' + * setting also. + */ +static EDMA3_RM_Result gblChngAllocContigRes(EDMA3_RM_Instance *rmInstance, + const EDMA3_RM_ResDesc *firstResIdObj, + unsigned int numResources); + +/*---------------------------------------------------------------------------*/ + +/**\fn EDMA3_RM_Result EDMA3_RM_create (unsigned int phyCtrllerInstId, + * const EDMA3_RM_GblConfigParams *gblCfgParams, + * const void *miscParam) + * \brief Create EDMA3 Resource Manager Object + * + * This API is used to create the EDMA3 Resource Manager Object. It should be + * called only ONCE for each EDMA3 hardware instance. + * + * Init-time Configuration structure for EDMA3 hardware is provided to pass the + * SoC specific information. This configuration information could be provided + * by the user at init-time. In case user doesn't provide it, this information + * could be taken from the SoC specific configuration file + * edma3__cfg.c, in case it is available. + * + * This API clears the error specific registers (EMCR/EMCRh, QEMCR, CCERRCLR) + * and sets the TCs priorities and Event Queues' watermark levels, if the 'miscParam' + * argument is NULL. User can avoid these registers' programming (in some specific + * use cases) by SETTING the 'isSlave' field of 'EDMA3_RM_MiscParam' configuration + * structure and passing this structure as the third argument (miscParam). + * + * After successful completion of this API, Resource Manager Object's state + * changes to EDMA3_RM_CREATED from EDMA3_RM_DELETED. + * + * \param phyCtrllerInstId [IN] EDMA3 Controller Instance Id + * (Hardware instance id, starting from 0). + * \param gblCfgParams [IN] SoC specific configuration structure for the + * EDMA3 Hardware. + * \param miscParam [IN] Misc configuration options provided in the + * structure 'EDMA3_RM_MiscParam'. + * For default options, user can pass NULL + * in this argument. + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + */ +EDMA3_RM_Result EDMA3_RM_create (unsigned int phyCtrllerInstId, + const EDMA3_RM_GblConfigParams *gblCfgParams, + const void *miscParam) + { + unsigned int count = 0u; + EDMA3_RM_Result result = EDMA3_RM_SOK; + /** + * Used to reset the Internal EDMA3 Resource Manager Data Structures for the first time. + */ + static unsigned short rmInitDone = FALSE; + const EDMA3_RM_MiscParam *miscOpt = (const EDMA3_RM_MiscParam *)miscParam; + + /** + * We are NOT checking 'gblCfgParams' for NULL. + * If user has passed NULL, default config info will be + * taken from config file. + * 'param' is also not being checked because it could be + * NULL also. + */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_RM_PARAM_CHECK_DISABLE + if (phyCtrllerInstId >= EDMA3_MAX_EDMA3_INSTANCES) + { + result = EDMA3_RM_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_RM_SOK == result) + { + /* Initialize the global variables for the first time */ + if (FALSE == rmInitDone) + { + edma3MemSet((void *)&(resMgrObj[count]) , 0x00u, + sizeof(resMgrObj)); + rmInitDone = TRUE; + } + + /* Initialization has been done */ + if (resMgrObj[phyCtrllerInstId].state != EDMA3_RM_DELETED) + { + result = EDMA3_RM_E_OBJ_NOT_DELETED; + } + else + { + /** + * Check whether user has passed the Global Config Info. + * If yes, copy it to the driver data structures. Else, use the + * info from the config file edma3Cfg.c + */ + if (NULL == gblCfgParams) + { + /* Take info from the specific config file */ + edma3MemCpy((void *)(&resMgrObj[phyCtrllerInstId].gblCfgParams), + (const void *)(&edma3GblCfgParams[phyCtrllerInstId]), + sizeof (EDMA3_RM_GblConfigParams)); + } + else + { + /* User passed the info, save it in the RM object first */ + edma3MemCpy((void *)(&resMgrObj[phyCtrllerInstId].gblCfgParams), + (const void *)(gblCfgParams), + sizeof (EDMA3_RM_GblConfigParams)); + } + + + /** + * Check whether DMA channel to PaRAM Set mapping exists or not. + * If it does not exist, set the mapping array as 1-to-1 mapped. + */ + if (FALSE == resMgrObj[phyCtrllerInstId].gblCfgParams.dmaChPaRAMMapExists) + { + for (count = 0u; count < resMgrObj[phyCtrllerInstId].gblCfgParams.numDmaChannels; count++) + { + resMgrObj[phyCtrllerInstId].gblCfgParams.dmaChannelPaRAMMap[count] = count; + } + } + + + /** + * Update the actual number of PaRAM sets. + */ + edma3NumPaRAMSets = resMgrObj[phyCtrllerInstId].gblCfgParams.numPaRAMSets; + + resMgrObj[phyCtrllerInstId].phyCtrllerInstId = phyCtrllerInstId; + resMgrObj[phyCtrllerInstId].state = EDMA3_RM_CREATED; + resMgrObj[phyCtrllerInstId].numOpens = 0u; + + /* Make all the RM instances for this EDMA3 HW NULL */ + for (count = 0u; count < EDMA3_MAX_RM_INSTANCES; count++) + { + edma3MemSet((void *)((EDMA3_RM_Instance *)(ptrRMIArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + count), + 0x00u, + sizeof(EDMA3_RM_Instance)); + + /* Also make this data structure NULL */ + edma3MemSet((void *)((EDMA3_RM_InstanceInitConfig *)(ptrInitCfgArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + count), + 0x00u, + sizeof(EDMA3_RM_InstanceInitConfig)); + } + + /* Initialize the global edma3DmaChTccMapping array with EDMA3_MAX_TCC */ + for ( count = 0u; + count < resMgrObj[phyCtrllerInstId].gblCfgParams.numDmaChannels; + count++ + ) + { + edma3DmaChTccMapping[count] = EDMA3_MAX_TCC; + } + + /* Initialize the global edma3QdmaChTccMapping array with EDMA3_MAX_TCC */ + for ( count = 0u; + count < resMgrObj[phyCtrllerInstId].gblCfgParams.numQdmaChannels; + count++ + ) + { + edma3QdmaChTccMapping[count] = EDMA3_MAX_TCC; + } + + /* Make the global edma3IntrParams array for interrupts NULL */ + edma3MemSet((void *)(&(edma3IntrParams[0u])), 0x00u, + sizeof(edma3IntrParams)); + + + /* Reset edma3RmChBoundRes Array*/ + for (count = 0u; count < EDMA3_MAX_LOGICAL_CH; count++) + { + edma3RmChBoundRes[phyCtrllerInstId][count].paRAMId = -1; + edma3RmChBoundRes[phyCtrllerInstId][count].tcc = EDMA3_MAX_TCC; + } + + /* Make the contiguousParamRes array NULL */ + edma3MemSet((void *)(&(contiguousParamRes[0u])), 0x00u, + sizeof(contiguousParamRes)); + + + /** + * Check the misc configuration options structure. + * Check whether the global registers' initialization + * is required or not. + * It is required ONLY if RM is running on the Master Processor. + */ + if (NULL != miscOpt) + { + if (miscOpt->isSlave == FALSE) + { + /* It is a master. */ + edma3GlobalRegionInit(phyCtrllerInstId); + } + } + else + { + /* By default, global registers will be initialized. */ + edma3GlobalRegionInit(phyCtrllerInstId); + } + } + } + + return result; + } + + + +/**\fn EDMA3_RM_Result EDMA3_RM_delete (unsigned int phyCtrllerInstId, + * const void *param) + * \brief Delete EDMA3 Resource Manager Object + * + * This API is used to delete the EDMA3 RM Object. It should be called + * once for each EDMA3 hardware instance, ONLY after closing all the + * previously opened EDMA3 RM Instances. + * + * After successful completion of this API, Resource Manager Object's state + * changes to EDMA3_RM_DELETED. + * + * \param phyCtrllerInstId [IN] EDMA3 Phy Controller Instance Id (Hardware + * instance id, starting from 0). + * \param param [IN] For possible future use. + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + */ +EDMA3_RM_Result EDMA3_RM_delete (unsigned int phyCtrllerInstId, + const void *param) + { + EDMA3_RM_Result result = EDMA3_RM_SOK; + + /* If parameter checking is enabled... */ +#ifndef EDMA3_RM_PARAM_CHECK_DISABLE + if (phyCtrllerInstId >= EDMA3_MAX_EDMA3_INSTANCES) + { + result = EDMA3_RM_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_RM_SOK == result) + { + /*to remove CCS remark: parameter "param" was never referenced */ + (void)param; + + /** + * If number of RM Instances is 0, then state should be + * EDMA3_RM_CLOSED OR EDMA3_RM_CREATED. + */ + if ((NULL == resMgrObj[phyCtrllerInstId].numOpens) + && ((resMgrObj[phyCtrllerInstId].state != EDMA3_RM_CLOSED) + && (resMgrObj[phyCtrllerInstId].state != EDMA3_RM_CREATED))) + { + result = EDMA3_RM_E_OBJ_NOT_CLOSED; + } + else + { + /** + * If number of RM Instances is NOT 0, then this function + * SHOULD NOT be called by anybody. + */ + if (NULL != resMgrObj[phyCtrllerInstId].numOpens) + { + result = EDMA3_RM_E_INVALID_STATE; + } + else + { + /** Change state to EDMA3_RM_DELETED */ + resMgrObj[phyCtrllerInstId].state = EDMA3_RM_DELETED; + + /* Reset the Allocated TCCs Array also. */ + allocatedTCCs[0u] = 0x0u; + allocatedTCCs[1u] = 0x0u; + + /* Also, reset the RM Object Global Config Info */ + edma3MemSet((void *)&(resMgrObj[phyCtrllerInstId].gblCfgParams), + 0x00u, + sizeof(EDMA3_RM_GblConfigParams)); + } + } + } + + return result; + } + + +/**\fn EDMA3_RM_Handle EDMA3_RM_open (unsigned int phyCtrllerInstId, + * const EDMA3_RM_Param *initParam, + * EDMA3_RM_Result *errorCode) + * \brief Open EDMA3 Resource Manager Instance + * + * This API is used to open an EDMA3 Resource Manager Instance. It could be + * called multiple times, for each possible EDMA3 shadow region. Maximum + * EDMA3_MAX_RM_INSTANCES instances are allowed for each EDMA3 hardware + * instance. + * + * Also, only ONE Master Resource Manager Instance is permitted. This master + * instance (and hence the region to which it belongs) will only receive the + * EDMA3 interrupts, if enabled. + * + * User could pass the instance specific configuration structure + * (initParam->rmInstInitConfig) as a part of the 'initParam' structure, + * during init-time. In case user doesn't provide it, this information could + * be taken from the SoC specific configuration file edma3__cfg.c, + * in case it is available. + * + * \param phyCtrllerInstId [IN] EDMA3 Controller Instance Id (Hardware + * instance id, starting from 0). + * \param initParam [IN] Used to Initialize the Resource Manager + * Instance (Master or Slave). + * \param errorCode [OUT] Error code while opening RM instance. + * + * \return Handle to the opened Resource Manager instance Or NULL in case of + * error. + * + * \note This function disables the global interrupts (by calling API + * edma3OsProtectEntry with protection level + * EDMA3_OS_PROTECT_INTERRUPT) while modifying the global RM data + * structures, to make it re-entrant. + */ +EDMA3_RM_Handle EDMA3_RM_open (unsigned int phyCtrllerInstId, + const EDMA3_RM_Param *initParam, + EDMA3_RM_Result *errorCode) + { + unsigned int intState = 0u; + unsigned int resMgrIdx = 0u; + EDMA3_RM_Result result = EDMA3_RM_SOK; + EDMA3_RM_Obj *rmObj = NULL; + EDMA3_RM_Instance *rmInstance = NULL; + EDMA3_RM_Instance *temp_ptr_rm_inst = NULL; + EDMA3_RM_Handle retVal = NULL; + unsigned int dmaChDwrds = 0u; + unsigned int paramSetDwrds = 0u; + unsigned int tccDwrds = 0u; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + unsigned int mappedPaRAMId; + + /* If parameter checking is enabled... */ +#ifndef EDMA3_RM_PARAM_CHECK_DISABLE + if (((initParam == NULL) + || (phyCtrllerInstId >= EDMA3_MAX_EDMA3_INSTANCES)) + || (errorCode == NULL)) + { + result = EDMA3_RM_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_RM_SOK == result) + { + /* Check whether the semaphore handle is null or not */ + if (NULL == initParam->rmSemHandle) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + else + { + rmObj = &resMgrObj[phyCtrllerInstId]; + if ( + (NULL == rmObj) + || (initParam->regionId >= + resMgrObj[phyCtrllerInstId].gblCfgParams.numRegions) + ) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + else + { + edma3OsProtectEntry (EDMA3_OS_PROTECT_INTERRUPT, &intState); + + /** Check state of RM Object. + * If no RM instance is opened and this is the first one, + * then state should be created/closed. + */ + if ((rmObj->numOpens == NULL) && + ((rmObj->state != EDMA3_RM_CREATED) && + (rmObj->state != EDMA3_RM_CLOSED))) + { + result = EDMA3_RM_E_INVALID_STATE; + edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT, intState); + } + else + { + /** + * If num of instances opened is more than 0 and less than + * max allowed, then state should be opened. + */ + if (((rmObj->numOpens > 0) && + (rmObj->numOpens < EDMA3_MAX_RM_INSTANCES)) + && (rmObj->state != EDMA3_RM_OPENED)) + { + result = EDMA3_RM_E_INVALID_STATE; + edma3OsProtectExit(EDMA3_OS_PROTECT_INTERRUPT,intState); + } + else + { + /* Check if max opens have passed */ + if (rmObj->numOpens >= EDMA3_MAX_RM_INSTANCES) + { + result = EDMA3_RM_E_MAX_RM_INST_OPENED; + edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT, + intState); + } + } + } + } + } + } + + if (EDMA3_RM_SOK == result) + { + /* + * Check whether the RM instance is Master or not. + * If it is master, check whether a master already exists + * or not. There should NOT be more than 1 master. + * Return error code if master already exists + */ + if ((TRUE == masterExists) && (TRUE == initParam->isMaster)) + { + /* No two masters should exist, return error */ + result = EDMA3_RM_E_RM_MASTER_ALREADY_EXISTS; + edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT, intState); + } + else + { + /* Create Res Mgr Instance */ + for (resMgrIdx = 0u; resMgrIdx < EDMA3_MAX_RM_INSTANCES; resMgrIdx++) + { + temp_ptr_rm_inst = ((EDMA3_RM_Instance *)(ptrRMIArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + resMgrIdx); + + if (NULL != temp_ptr_rm_inst) + { + if (NULL == temp_ptr_rm_inst->pResMgrObjHandle) + { + /* Handle to the EDMA3 HW Object */ + temp_ptr_rm_inst->pResMgrObjHandle = rmObj; + /* Handle of the Res Mgr Instance */ + rmInstance = temp_ptr_rm_inst; + + /* Also make this data structure NULL, just for safety. */ + edma3MemSet((void *)((EDMA3_RM_InstanceInitConfig *)(ptrInitCfgArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + resMgrIdx), + 0x00u, + sizeof(EDMA3_RM_InstanceInitConfig)); + + break; + } + } + } + + /* Check whether a RM instance has been created or not */ + if (NULL == rmInstance) + { + result = EDMA3_RM_E_MAX_RM_INST_OPENED; + edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT, intState); + } + else + { + /* Copy the InitPaRAM first */ + edma3MemCpy((void *)(&rmInstance->initParam), + (const void *)(initParam), + sizeof (EDMA3_RM_Param)); + + if (rmObj->gblCfgParams.globalRegs != NULL) + { + globalRegs = (volatile EDMA3_CCRL_Regs *) + (rmObj->gblCfgParams.globalRegs); + rmInstance->shadowRegs = (EDMA3_CCRL_ShadowRegs *) + &(globalRegs->SHADOW[rmInstance->initParam.regionId]); + + /* copy the instance specific semaphore handle */ + rmInstance->initParam.rmSemHandle = initParam->rmSemHandle; + + /** + * Check whether user has passed information about resources + * owned and reserved by this instance. This is region specific + * information. If he has not passed, dafault static config info will be taken + * from the config file edma3Cfg.c, according to the regionId specified. + * + * resMgrIdx specifies the RM instance number created just now. + * Use it to populate the userInitConfig []. + */ + if (NULL == initParam->rmInstInitConfig) + { + /* Take the info from the specific config file */ + edma3MemCpy((void *)((EDMA3_RM_InstanceInitConfig *)(ptrInitCfgArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + resMgrIdx), + (const void *)(&defInstInitConfig[phyCtrllerInstId][initParam->regionId]), + sizeof (EDMA3_RM_InstanceInitConfig)); + } + else + { + /* User has passed the region specific info. */ + edma3MemCpy((void *)((EDMA3_RM_InstanceInitConfig *)(ptrInitCfgArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + resMgrIdx), + (const void *)(initParam->rmInstInitConfig), + sizeof (EDMA3_RM_InstanceInitConfig)); + } + + rmInstance->initParam.rmInstInitConfig = + ((EDMA3_RM_InstanceInitConfig *)(ptrInitCfgArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + resMgrIdx); + + dmaChDwrds = rmObj->gblCfgParams.numDmaChannels / 32u; + paramSetDwrds = rmObj->gblCfgParams.numPaRAMSets / 32u; + tccDwrds = rmObj->gblCfgParams.numTccs / 32u; + + for (resMgrIdx = 0u; resMgrIdx < dmaChDwrds; ++resMgrIdx) + { + rmInstance->avlblDmaChannels[resMgrIdx] + = rmInstance->initParam.rmInstInitConfig->ownDmaChannels[resMgrIdx]; + } + + rmInstance->avlblQdmaChannels[0u] + = rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[0u]; + + for (resMgrIdx = 0u; resMgrIdx < paramSetDwrds; ++resMgrIdx) + { + rmInstance->avlblPaRAMSets[resMgrIdx] + = rmInstance->initParam.rmInstInitConfig->ownPaRAMSets[resMgrIdx]; + } + + for (resMgrIdx = 0u; resMgrIdx < tccDwrds; ++resMgrIdx) + { + rmInstance->avlblTccs [resMgrIdx] + = rmInstance->initParam.rmInstInitConfig->ownTccs[resMgrIdx]; + } + + /* + * If mapping exists b/w DMA channel and PaRAM set (i.e. programmable), + * then mark those PaRAM sets which are mapped to some specific + * DMA channels as RESERVED. If NO mapping (ie ch 0 is tied to PaRAM 0, + * ch 1 is tied to PaRAM 1), mark all as RESERVED. + */ + if (rmObj->gblCfgParams.dmaChPaRAMMapExists == TRUE) + { + /* Mapping Exists */ + for (resMgrIdx = 0u; resMgrIdx < rmObj->gblCfgParams.numDmaChannels; ++resMgrIdx) + { + mappedPaRAMId = rmObj->gblCfgParams.dmaChannelPaRAMMap[resMgrIdx]; + if (mappedPaRAMId != EDMA3_RM_CH_NO_PARAM_MAP) + { + /* Channel is mapped to a particular PaRAM Set, mark it as Reserved. */ + rmInstance->initParam.rmInstInitConfig->resvdPaRAMSets[mappedPaRAMId/32u] |= (1u<<(mappedPaRAMId%32u)); + } + } + } + else + { + /* Mapping Doesnot Exist, PaRAM Sets are 1-to-1 mapped, mark all as Reserved */ + for (resMgrIdx = 0u; resMgrIdx < dmaChDwrds; ++resMgrIdx) + { + rmInstance->initParam.rmInstInitConfig->resvdPaRAMSets[resMgrIdx] = 0xFFFFFFFFu; + } + } + + /* + * If the EDMA RM instance is MASTER (ie. initParam->isMaster + * is TRUE), save the region ID. + * Only this shadow region will receive the + * EDMA3 interrupts, if enabled. + */ + if (TRUE == initParam->isMaster) + { + /* Store the region id to use it in the ISRs */ + edma3RegionId = rmInstance->initParam.regionId; + masterExists = TRUE; + } + + if (TRUE == initParam->regionInitEnable) + { + edma3ShadowRegionInit (rmInstance); + } + + /** + * By default, PaRAM Sets allocated using this RM Instance + * will get cleared during their allocation. + * User can stop their clearing by calling specific IOCTL + * command. + */ + rmInstance->paramInitRequired = TRUE; + + + /** + * By default, during the EDMA3_RM_allocLogicalChannel (), + * global EDMA3 registers (DCHMAP/QCHMAP) and the allocated + * PaRAM Set will be programmed accordingly, for users using this + * RM Instance. + * User can stop their pre-programming by calling + * EDMA3_RM_IOCTL_SET_GBL_REG_MODIFY_OPTION + * IOCTL command. + */ + rmInstance->regModificationRequired = TRUE; + + + if (EDMA3_RM_SOK == result) + { + rmObj->state = EDMA3_RM_OPENED; + /* Increase the Instance count */ + resMgrObj[phyCtrllerInstId].numOpens++; + retVal = rmInstance; + } + } + else + { + result = EDMA3_RM_E_INVALID_PARAM; + } + + edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT, intState); + } + } + } + + *errorCode = result; + return (EDMA3_RM_Handle)retVal; + } + + +/**\fn EDMA3_RM_Result EDMA3_RM_close (EDMA3_RM_Handle hEdmaResMgr, + * const void *param) + * \brief Close EDMA3 Resource Manager Instance + * + * This API is used to close a previously opened EDMA3 RM Instance. + * + * \param hEdmaResMgr [IN] Handle to the previously opened Resource + * Manager Instance. + * \param param [IN] For possible future use. + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + * + * \note This function disables the global interrupts (by calling API + * edma3OsProtectEntry with protection level + * EDMA3_OS_PROTECT_INTERRUPT) while modifying the global RM data + * structures, to make it re-entrant. + */ +EDMA3_RM_Result EDMA3_RM_close (EDMA3_RM_Handle hEdmaResMgr, + const void *param) + { + EDMA3_RM_Result result = EDMA3_RM_SOK; + unsigned int intState = 0u; + unsigned int resMgrIdx = 0u; + EDMA3_RM_Obj *rmObj = NULL; + EDMA3_RM_Instance *rmInstance = NULL; + unsigned int dmaChDwrds; + unsigned int paramSetDwrds; + unsigned int tccDwrds; + + /*to remove CCS remark: parameter "param" was never referenced */ + (void)param; + + /* If parameter checking is enabled... */ +#ifndef EDMA3_RM_PARAM_CHECK_DISABLE + if (NULL == hEdmaResMgr) + { + result = EDMA3_RM_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_RM_SOK == result) + { + rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr; + rmObj = rmInstance->pResMgrObjHandle; + + if (rmObj == NULL) + { + result = (EDMA3_RM_E_INVALID_PARAM); + } + else + { + /* Check state of driver, state should be opened */ + if (rmObj->state != EDMA3_RM_OPENED) + { + result = (EDMA3_RM_E_OBJ_NOT_OPENED); + } + else + { + dmaChDwrds = rmObj->gblCfgParams.numDmaChannels / 32u; + paramSetDwrds = rmObj->gblCfgParams.numPaRAMSets / 32u; + tccDwrds = rmObj->gblCfgParams.numTccs / 32u; + + /* Set the instance config as NULL*/ + for (resMgrIdx = 0u; resMgrIdx < dmaChDwrds; ++resMgrIdx) + { + rmInstance->avlblDmaChannels[resMgrIdx] = 0x0u; + } + for (resMgrIdx = 0u; resMgrIdx < paramSetDwrds; ++resMgrIdx) + { + rmInstance->avlblPaRAMSets[resMgrIdx] = 0x0u; + } + rmInstance->avlblQdmaChannels[0u] = 0x0u; + for (resMgrIdx = 0u; resMgrIdx < tccDwrds; ++resMgrIdx) + { + rmInstance->avlblTccs[resMgrIdx] = 0x0u; + } + + /** + * If this is the Master Instance, reset the static variable + * 'masterExists'. + */ + if (TRUE == rmInstance->initParam.isMaster) + { + masterExists = FALSE; + edma3RegionId = EDMA3_MAX_REGIONS; + } + + /* Reset the Initparam for this RM Instance */ + edma3MemSet((void *)&(rmInstance->initParam) , 0x00u, + sizeof(EDMA3_RM_Param)); + + /* Critical section starts */ + edma3OsProtectEntry (EDMA3_OS_PROTECT_INTERRUPT, &intState); + + /* Decrease the Number of Opens */ + --rmObj->numOpens; + if (NULL == rmObj->numOpens) + { + edma3MemSet((void *)&(edma3RmChBoundRes[rmObj->phyCtrllerInstId]), 0x00u, + sizeof(edma3RmChBoundRes)); + + rmObj->state = EDMA3_RM_CLOSED; + } + + /* Critical section ends */ + edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT, intState); + + rmInstance->pResMgrObjHandle = NULL; + rmInstance->shadowRegs = NULL; + rmInstance = NULL; + } + } + } + + return result; + } + + +/**\fn EDMA3_RM_Result EDMA3_RM_allocResource (EDMA3_RM_Handle hEdmaResMgr, + * EDMA3_RM_ResDesc *resObj) + * \brief This API is used to allocate specified EDMA3 Resources like + * DMA/QDMA channel, PaRAM Set or TCC. + * + * Note: To free the resources allocated by this API, user should call + * EDMA3_RM_freeResource () ONLY to de-allocate all the allocated resources. + * + * User can either request a specific resource by passing the resource id + * in 'resObj->resId' OR request ANY available resource of the type + * 'resObj->type'. + * + * ANY types of resources are those resources when user doesn't care about the + * actual resource allocated; user just wants a resource of the type specified. + * One use-case is to perform memory-to-memory data transfer operation. This + * operation can be performed using any available DMA or QDMA channel. + * User doesn't need any specific channel for the same. + * + * To allocate a specific resource, first this API checks whether that resource + * is OWNED by the Resource Manager instance. Then it checks the current + * availability of that resource. + * + * To allocate ANY available resource, this API tries to allocate a resource + * from the pool of (owned && non_reserved && available_right_now) resources. + * + * After allocating a DMA/QDMA channel or TCC, the same resource is enabled in + * the shadow region specific register (DRAE/DRAEH/QRAE). + * + * Allocated PaRAM Set is initialized to NULL before this API returns if user + * has requested for one. + * + * \param hEdmaResMgr [IN] Handle to the previously opened Resource + * Manager Instance. + * \param resObj [IN/OUT] Handle to the resource descriptor + * object, which needs to be allocated. + * In case user passes a specific resource + * Id, resObj value is left unchanged. + * In case user requests ANY available + * resource, the allocated resource id is + * returned in resObj. + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + * + * \note This function acquires a RM Instance specific semaphore + * to prevent simultaneous access to the global pool of resources. + * It is re-entrant, but should not be called from the user callback + * function (ISR context). + */ +EDMA3_RM_Result EDMA3_RM_allocResource(EDMA3_RM_Handle hEdmaResMgr, + EDMA3_RM_ResDesc *resObj) + { + EDMA3_RM_Instance *rmInstance = NULL; + EDMA3_RM_Obj *rmObj = NULL; + EDMA3_RM_Result result = EDMA3_RM_SOK; + EDMA3_RM_Result semResult = EDMA3_RM_SOK; + unsigned int avlblIdx = 0u; + unsigned int resIdClr = 0x0; + unsigned int resIdSet = 0x0; + unsigned int resId; + volatile EDMA3_CCRL_Regs *gblRegs = NULL; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_RM_PARAM_CHECK_DISABLE + if ((hEdmaResMgr == NULL) || (resObj == NULL)) + { + result = (EDMA3_RM_E_INVALID_PARAM); + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_RM_SOK == result) + { + rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr; + rmObj = rmInstance->pResMgrObjHandle; + + if ((rmObj == NULL) || + (rmObj->gblCfgParams.globalRegs == NULL)) + { + result = (EDMA3_RM_E_INVALID_PARAM); + } + else + { + gblRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs); + + resId = resObj->resId; + + resIdClr = (unsigned int)(~(1u << (resId%32u))); + resIdSet = (1u << (resId%32u)); + + /** + * Take the instance specific semaphore, to prevent simultaneous + * access to the shared resources. + */ + semResult = edma3OsSemTake(rmInstance->initParam.rmSemHandle, + EDMA3_OSSEM_NO_TIMEOUT); + if (EDMA3_RM_SOK == semResult) + { + switch (resObj->type) + { + case EDMA3_RM_RES_DMA_CHANNEL : + { + if (resId == EDMA3_RM_RES_ANY) + { + for (avlblIdx=0u; + avlblIdx < + rmObj->gblCfgParams.numDmaChannels; + ++avlblIdx) + { + if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[avlblIdx/32u]) + & + (rmInstance->avlblDmaChannels[avlblIdx/32u]) + & + ~(rmInstance->initParam.rmInstInitConfig->resvdDmaChannels[avlblIdx/32u]) + & + (1u << (avlblIdx%32u))) != FALSE) + { + /* + * Match found. + * A resource which is owned by this instance of the + * Resource Manager and which is presently available + * and which has not been reserved - is found. + */ + resObj->resId = avlblIdx; + /* + * Mark the 'match found' resource as "Not Available" + * for future requests + */ + rmInstance->avlblDmaChannels[avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u))); + + /** + * Check if the register modification flag is + * set or not. + */ + if (TRUE == rmInstance->regModificationRequired) + { + /** + * Enable the DMA channel in the + * DRAE/DRAEH registers also. + */ + if (avlblIdx < 32u) + { + gblRegs->DRA[rmInstance->initParam.regionId].DRAE + |= (0x1u << avlblIdx); + } + else + { + gblRegs->DRA[rmInstance->initParam.regionId].DRAEH + |= (0x1u << (avlblIdx - 32u)); + } + } + + result = EDMA3_RM_SOK; + break; + } + } + /* + * If none of the owned resources of this type is available + * then report "All Resources of this type not available" error + */ + if (avlblIdx == rmObj->gblCfgParams.numDmaChannels) + { + result = EDMA3_RM_E_ALL_RES_NOT_AVAILABLE; + } + } + else + { + if (resId < rmObj->gblCfgParams.numDmaChannels) + { + /* + * Check if specified resource is owned + * by this instance of the resource manager + */ + if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[resId/32u])&(resIdSet))!=FALSE) + { + /* Now check if specified resource is available presently*/ + if (((rmInstance->avlblDmaChannels[resId/32u])&(resIdSet))!=FALSE) + { + /* + * Mark the specified channel as "Not Available" + * for future requests + */ + rmInstance->avlblDmaChannels[resId/32u] &= resIdClr; + + /** + * Check if the register modification flag is + * set or not. + */ + if (TRUE == rmInstance->regModificationRequired) + { + if (resId < 32u) + { + rmInstance->shadowRegs->EECR = (1UL << resId); + + /** + * Enable the DMA channel in the + * DRAE registers also. + */ + gblRegs->DRA[rmInstance->initParam.regionId].DRAE + |= (0x1u << resId); + } + else + { + rmInstance->shadowRegs->EECRH = (1UL << resId); + + /** + * Enable the DMA channel in the + * DRAEH registers also. + */ + gblRegs->DRA[rmInstance->initParam.regionId].DRAEH + |= (0x1u << (resId - 32u)); + } + } + + result = EDMA3_RM_SOK; + } + else + { + /* Specified resource is owned but is already booked */ + result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE; + } + } + else + { + /* + * Specified resource is not owned by this instance + * of the Resource Manager + */ + result = EDMA3_RM_E_RES_NOT_OWNED; + } + } + else + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + } + break; + + case EDMA3_RM_RES_QDMA_CHANNEL : + { + if (resId == EDMA3_RM_RES_ANY) + { + for (avlblIdx=0u; avlblIdxgblCfgParams.numQdmaChannels; ++avlblIdx) + { + if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[avlblIdx/32u]) + & + (rmInstance->avlblQdmaChannels[avlblIdx/32u]) + & + ~(rmInstance->initParam.rmInstInitConfig->resvdQdmaChannels[avlblIdx/32u]) + & + (1u << (avlblIdx%32u))) != FALSE) + { + resObj->resId = avlblIdx; + rmInstance->avlblQdmaChannels[avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u))); + + /** + * Check if the register modification flag is + * set or not. + */ + if (TRUE == rmInstance->regModificationRequired) + { + /** + * Enable the QDMA channel in the + * QRAE register also. + */ + gblRegs->QRAE[rmInstance->initParam.regionId] + |= (0x1u << avlblIdx); + } + + result = EDMA3_RM_SOK; + break; + } + } + /* + * If none of the owned resources of this type is available + * then report "All Resources of this type not available" error + */ + if (avlblIdx == rmObj->gblCfgParams.numQdmaChannels) + { + result = EDMA3_RM_E_ALL_RES_NOT_AVAILABLE; + } + } + else + { + if (resId < rmObj->gblCfgParams.numQdmaChannels) + { + if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels [resId/32u])&(resIdSet))!=FALSE) + { + if (((rmInstance->avlblQdmaChannels [resId/32u])&(resIdSet))!=FALSE) + { + rmInstance->avlblQdmaChannels [resId/32u] &= resIdClr; + + /** + * Check if the register modification flag is + * set or not. + */ + if (TRUE == rmInstance->regModificationRequired) + { + /** + * Enable the QDMA channel in the + * QRAE register also. + */ + gblRegs->QRAE[rmInstance->initParam.regionId] + |= (0x1u << resId); + } + + result = EDMA3_RM_SOK; + } + else + { + /* Specified resource is owned but is already booked */ + result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE; + } + } + else + { + /* + * Specified resource is not owned by this instance + * of the Resource Manager + */ + result = EDMA3_RM_E_RES_NOT_OWNED; + } + } + else + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + } + break; + + case EDMA3_RM_RES_TCC : + { + if (resId == EDMA3_RM_RES_ANY) + { + for (avlblIdx=0u; avlblIdxgblCfgParams.numTccs; ++avlblIdx) + { + if (((rmInstance->initParam.rmInstInitConfig->ownTccs [avlblIdx/32u]) + & (rmInstance->avlblTccs [avlblIdx/32u]) + & ~(rmInstance->initParam.rmInstInitConfig->resvdTccs [avlblIdx/32u]) + & (1u << (avlblIdx%32u)))!=FALSE) + { + resObj->resId = avlblIdx; + rmInstance->avlblTccs [avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u))); + + /** + * Check if the register modification flag is + * set or not. + */ + if (TRUE == rmInstance->regModificationRequired) + { + /** + * Enable the Interrupt channel in the + * DRAE/DRAEH registers also. + * Also, If the region id coming from this + * RM instance is same as the Master RM + * Instance's region id, only then we will be + * getting the interrupts on the same side. + * So save the TCC in the allocatedTCCs[] array. + */ + if (avlblIdx < 32u) + { + gblRegs->DRA[rmInstance->initParam.regionId].DRAE + |= (0x1u << avlblIdx); + + /** + * Do not modify this global array if the register + * modificatio flag is not set. + * Reason being is based on this flag, the IPR/ICR + * or error bit is cleared in the completion or + * error handler ISR. + */ + if (edma3RegionId == rmInstance->initParam.regionId) + { + allocatedTCCs[0u] |= (0x1u << avlblIdx); + } + } + else + { + gblRegs->DRA[rmInstance->initParam.regionId].DRAEH + |= (0x1u << (avlblIdx - 32u)); + + /** + * Do not modify this global array if the register + * modificatio flag is not set. + * Reason being is based on this flag, the IPR/ICR + * or error bit is cleared in the completion or + * error handler ISR. + */ + if (edma3RegionId == rmInstance->initParam.regionId) + { + allocatedTCCs[1u] |= (0x1u << (avlblIdx - 32u)); + } + } + } + + + result = EDMA3_RM_SOK; + break; + } + } + /* + * If none of the owned resources of this type is available + * then report "All Resources of this type not available" error + */ + if ( avlblIdx == rmObj->gblCfgParams.numTccs) + { + result = EDMA3_RM_E_ALL_RES_NOT_AVAILABLE; + } + } + else + { + if (resId < rmObj->gblCfgParams.numTccs) + { + if (((rmInstance->initParam.rmInstInitConfig->ownTccs [resId/32u])&(resIdSet))!=FALSE) + { + if (((rmInstance->avlblTccs [resId/32u])&(resIdSet))!=FALSE) + { + rmInstance->avlblTccs [resId/32u] &= resIdClr; + + /** + * Check if the register modification flag is + * set or not. + */ + if (TRUE == rmInstance->regModificationRequired) + { + /** + * Enable the Interrupt channel in the + * DRAE/DRAEH registers also. + * Also, If the region id coming from this + * RM instance is same as the Master RM + * Instance's region id, only then we will be + * getting the interrupts on the same side. + * So save the TCC in the allocatedTCCs[] array. + */ + if (resId < 32u) + { + gblRegs->DRA[rmInstance->initParam.regionId].DRAE + |= (0x1u << resId); + + /** + * Do not modify this global array if the register + * modificatio flag is not set. + * Reason being is based on this flag, the IPR/ICR + * or error bit is cleared in the completion or + * error handler ISR. + */ + if (edma3RegionId == rmInstance->initParam.regionId) + { + allocatedTCCs[0u] |= (0x1u << resId); + } + } + else + { + gblRegs->DRA[rmInstance->initParam.regionId].DRAEH + |= (0x1u << (resId - 32u)); + + /** + * Do not modify this global array if the register + * modificatio flag is not set. + * Reason being is based on this flag, the IPR/ICR + * or error bit is cleared in the completion or + * error handler ISR. + */ + if (edma3RegionId == rmInstance->initParam.regionId) + { + allocatedTCCs[1u] |= (0x1u << (resId - 32u)); + } + } + } + + result = EDMA3_RM_SOK; + } + else + { + /* Specified resource is owned but is already booked */ + result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE; + } + } + else + { + /* + * Specified resource is not owned by this instance + * of the Resource Manager + */ + result = EDMA3_RM_E_RES_NOT_OWNED; + } + } + else + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + } + break; + + case EDMA3_RM_RES_PARAM_SET : + { + if (resId == EDMA3_RM_RES_ANY) + { + for (avlblIdx=0u; avlblIdxgblCfgParams.numPaRAMSets; ++avlblIdx) + { + if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets [avlblIdx/32u]) + & + (rmInstance->avlblPaRAMSets [avlblIdx/32u]) + & + ~(rmInstance->initParam.rmInstInitConfig->resvdPaRAMSets [avlblIdx/32u]) + & + (1u << (avlblIdx%32u)))!=FALSE) + { + resObj->resId = avlblIdx; + rmInstance->avlblPaRAMSets [avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u))); + + /** + * Also, make the actual PARAM Set NULL, checking the flag + * whether it is required or not. + */ + if ((TRUE == rmInstance->regModificationRequired) + && (TRUE == rmInstance->paramInitRequired)) + { + edma3MemSet((void *)(&gblRegs->PARAMENTRY[avlblIdx]), + 0x00u, + sizeof(gblRegs->PARAMENTRY[avlblIdx])); + } + + result = EDMA3_RM_SOK; + break; + } + } + /* + * If none of the owned resources of this type is available + * then report "All Resources of this type not available" error + */ + if ( avlblIdx == rmObj->gblCfgParams.numPaRAMSets) + { + result = EDMA3_RM_E_ALL_RES_NOT_AVAILABLE; + } + } + else + { + if (resId < rmObj->gblCfgParams.numPaRAMSets) + { + if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets [resId/32u])&(resIdSet))!=FALSE) + { + if (((rmInstance->avlblPaRAMSets [resId/32u])&(resIdSet)) !=FALSE) + { + rmInstance->avlblPaRAMSets [resId/32u] &= resIdClr; + + /** + * Also, make the actual PARAM Set NULL, checking the flag + * whether it is required or not. + */ + if ((TRUE == rmInstance->regModificationRequired) + && (TRUE == rmInstance->paramInitRequired)) + { + edma3MemSet((void *)(&gblRegs->PARAMENTRY[resId]), + 0x00u, + sizeof(gblRegs->PARAMENTRY[resId])); + } + + result = EDMA3_RM_SOK; + } + else + { + /* Specified resource is owned but is already booked */ + result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE; + } + } + else + { + /* + * Specified resource is not owned by this instance + * of the Resource Manager + */ + result = EDMA3_RM_E_RES_NOT_OWNED; + } + } + else + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + } + break; + + default: + result = EDMA3_RM_E_INVALID_PARAM; + break; + } + + /* Return the semaphore back */ + semResult = edma3OsSemGive(rmInstance->initParam.rmSemHandle); + } + } + } + + /** + * Check the Resource Allocation Result 'result' first. If Resource + * Allocation has resulted in an error, return it (having more priority than + * semResult. + * Else, return semResult. + */ + if (EDMA3_RM_SOK == result) + { + /** + * Resource Allocation successful, return semResult for returning + * semaphore. + */ + result = semResult; + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + + +/**\fn EDMA3_RM_Result EDMA3_RM_freeResource(EDMA3_RM_Handle hEdmaResMgr, + * const EDMA3_RM_ResDesc *resObj) + * \brief This API is used to free previously allocated EDMA3 Resources like + * DMA/QDMA channel, PaRAM Set or TCC. + * + * To free a specific resource, first this API checks whether that resource is + * OWNED by the Resource Manager Instance. Then it checks whether that resource + * has been allocated by the Resource Manager instance or not. + * + * After freeing a DMA/QDMA channel or TCC, the same resource is disabled in + * the shadow region specific register (DRAE/DRAEH/QRAE). + * + * \param hEdmaResMgr [IN] Handle to the previously opened Resource + * Manager Instance. + * \param resObj [IN] Handle to the resource descriptor + * object, which needs to be freed. + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + * + * \note This function disables the global interrupts to prevent + * simultaneous access to the global pool of resources. + * It is re-entrant. + */ +EDMA3_RM_Result EDMA3_RM_freeResource(EDMA3_RM_Handle hEdmaResMgr, + const EDMA3_RM_ResDesc *resObj) + { + unsigned int intState; + EDMA3_RM_Instance *rmInstance = NULL; + EDMA3_RM_Obj *rmObj = NULL; + EDMA3_RM_Result result = EDMA3_RM_SOK; + unsigned int resId; + unsigned int resIdSet = 0x0; + volatile EDMA3_CCRL_Regs *gblRegs = NULL; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_RM_PARAM_CHECK_DISABLE + if ((hEdmaResMgr == NULL) || (resObj == NULL)) + { + result = EDMA3_RM_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_RM_SOK == result) + { + rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr; + rmObj = rmInstance->pResMgrObjHandle; + + if ((rmObj == NULL) || + (rmObj->gblCfgParams.globalRegs == NULL)) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + else + { + gblRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs); + + resId = resObj->resId; + + resIdSet = 1u << (resId%32u); + + edma3OsProtectEntry (EDMA3_OS_PROTECT_INTERRUPT, &intState); + + if (EDMA3_RM_SOK == result) + { + switch (resObj->type) + { + case EDMA3_RM_RES_DMA_CHANNEL : + { + if (resId < rmObj->gblCfgParams.numDmaChannels) + { + if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels [resId/32u]) & (resIdSet))!=FALSE) + { + if (((~(rmInstance->avlblDmaChannels[resId/32u]))&(resIdSet))!=FALSE) + { + /* + * Mark the specified channel as "Available" + * for future requests + */ + rmInstance->avlblDmaChannels[resId/32u] |= resIdSet; + + /** + * Check if the register modification flag is + * set or not. + */ + if (TRUE == rmInstance->regModificationRequired) + { + /** + * DMA Channel is freed. + * Reset the bit specific to the DMA channel + * in the DRAE/DRAEH register also. + */ + if (resId < 32u) + { + gblRegs->DRA[rmInstance->initParam.regionId].DRAE + &= (~(0x1u << resId)); + } + else + { + gblRegs->DRA[rmInstance->initParam.regionId].DRAEH + &= (~(0x1u << (resId-32u))); + } + } + + result = EDMA3_RM_SOK; + } + else + { + result = EDMA3_RM_E_RES_ALREADY_FREE; + } + } + else + { + /* + * Specified resource is not owned by this instance + * of the Resource Manager + */ + result = EDMA3_RM_E_RES_NOT_OWNED; + } + } + else + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + break; + + case EDMA3_RM_RES_QDMA_CHANNEL : + { + if (resId < rmObj->gblCfgParams.numQdmaChannels) + { + if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels [resId/32u]) & (resIdSet))!=FALSE) + { + if (((~(rmInstance->avlblQdmaChannels [resId/32u])) & (resIdSet))!=FALSE) + { + rmInstance->avlblQdmaChannels [resId/32u] |= resIdSet; + + /** + * Check if the register modification flag is + * set or not. + */ + if (TRUE == rmInstance->regModificationRequired) + { + /** + * QDMA Channel is freed. + * Reset the bit specific to the QDMA channel + * in the QRAE register also. + */ + gblRegs->QRAE[rmInstance->initParam.regionId] + &= (~(0x1u << resId)); + } + + result = EDMA3_RM_SOK; + } + else + { + result = EDMA3_RM_E_RES_ALREADY_FREE; + } + } + else + { + /* + * Specified resource is not owned by this instance + * of the Resource Manager + */ + result = EDMA3_RM_E_RES_NOT_OWNED; + } + } + else + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + break; + + case EDMA3_RM_RES_TCC : + { + if (resId < rmObj->gblCfgParams.numTccs) + { + if (((rmInstance->initParam.rmInstInitConfig->ownTccs [resId/32u]) & (resIdSet))!=FALSE) + { + if (((~(rmInstance->avlblTccs [resId/32u])) & (resIdSet))!=FALSE) + { + rmInstance->avlblTccs [resId/32u] |= resIdSet; + + /** + * Check if the register modification flag is + * set or not. + */ + if (TRUE == rmInstance->regModificationRequired) + { + /** + * Interrupt Channel is freed. + * Reset the bit specific to the Interrupt + * channel in the DRAE/DRAEH register also. + * Also, if we have earlier saved this + * TCC in allocatedTCCs[] array, + * remove it from there too. + */ + if (resId < 32u) + { + gblRegs->DRA[rmInstance->initParam.regionId].DRAE + &= (~(0x1u << resId)); + + if (edma3RegionId == rmInstance->initParam.regionId) + { + allocatedTCCs[0u] &= (~(0x1u << resId)); + } + } + else + { + gblRegs->DRA[rmInstance->initParam.regionId].DRAEH + &= (~(0x1u << (resId-32u))); + + if (edma3RegionId == rmInstance->initParam.regionId) + { + allocatedTCCs[1u] &= (~(0x1u << (resId -32u))); + } + } + } + + result = EDMA3_RM_SOK; + } + else + { + result = EDMA3_RM_E_RES_ALREADY_FREE; + } + } + else + { + /* + * Specified resource is not owned by this instance + * of the Resource Manager + */ + result = EDMA3_RM_E_RES_NOT_OWNED; + } + } + else + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + break; + + case EDMA3_RM_RES_PARAM_SET : + { + if (resId < rmObj->gblCfgParams.numPaRAMSets) + { + if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets [resId/32u])&(resIdSet))!=FALSE) + { + if (((~(rmInstance->avlblPaRAMSets [resId/32u]))&(resIdSet))!=FALSE) + { + rmInstance->avlblPaRAMSets [resId/32u] |= resIdSet; + + result = EDMA3_RM_SOK; + } + else + { + result = EDMA3_RM_E_RES_ALREADY_FREE; + } + } + else + { + /* + * Specified resource is not owned by this instance + * of the Resource Manager + */ + result = EDMA3_RM_E_RES_NOT_OWNED; + } + } + else + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + break; + + default: + result = EDMA3_RM_E_INVALID_PARAM; + break; + } + + } + + edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT, intState); + } + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + + +/** + * \fn EDMA3_RM_Result EDMA3_RM_allocLogicalChannel(EDMA3_RM_Handle + * hEdmaResMgr, EDMA3_RM_ResDesc *lChObj, + * unsigned int *pParam, unsigned int *pTcc) + * \brief Request a DMA/QDMA/Link channel. + * + * This API is used to allocate a logical channel (DMA/QDMA/Link) along with + * the associated resources. For DMA and QDMA channels, TCC and PaRAM Set are + * also allocated along with the requested channel. For Link channel, ONLY a + * PaRAM Set is allocated. + * + * Note: To free the logical channel allocated by this API, user should call + * EDMA3_RM_freeLogicalChannel () ONLY to de-allocate all the allocated resources + * and remove certain mappings. + * + * User can request a specific logical channel by passing the channel id in + * 'lChObj->resId' and channel type in 'lChObj->type'. Note that the channel + * id is the same as the actual resource id. For e.g. in the case of QDMA + * channels, valid channel ids are from 0 to 7 only. + * + * User can also request ANY available logical channel of the type + * 'lChObj->type' by specifying 'lChObj->resId' as: + * a) EDMA3_RM_DMA_CHANNEL_ANY: For DMA channels + * b) EDMA3_RM_QDMA_CHANNEL_ANY: For QDMA channels, and + * c) EDMA3_RM_PARAM_ANY: For Link channels. Normally user should use this + * value to request link channels (PaRAM Sets used for linking purpose + * only), unless he wants to use some specific link channels (PaRAM Sets) + * which is also allowed. + * + * This API internally uses EDMA3_RM_allocResource () to allocate the desired + * resources (DMA/QDMA channel, PaRAM Set and TCC). + * + * For DMA/QDMA channels, after allocating all the EDMA3 resources, this API + * sets the TCC field of the OPT PaRAM Word with the allocated TCC. + * + * For DMA channel, it also sets the DCHMAP register, if required. + * + * For QDMA channel, it sets the QCHMAP register and CCNT as trigger word and + * enables the QDMA channel by writing to the QEESR register. + * + * \param hEdmaResMgr [IN] Handle to the previously opened Resource + * Manager Instance. + * \param lChObj [IN/OUT] Handle to the requested logical channel + * object, which needs to be allocated. + * It could be a specific logical channel + * or ANY available logical channel of the + * requested type. + * In case user passes a specific resource + * Id, lChObj value is left unchanged. In + * case user requests ANY available + * resource, the allocated resource id is + * returned in lChObj->resId. + * + * \param pParam [IN/OUT] PaRAM Set for a particular logical + * (DMA/QDMA) channel. Not used if user + * requested for a Link channel. + * In case user passes a specific PaRAM + * Set value, pParam value is left + * unchanged. In case user requests ANY + * available PaRAM Set, the allocated one + * is returned in pParam. + * + * \param pTcc [IN/OUT] TCC for a particular logical (DMA/QDMA) + * channel. Not used if user requested for + * a Link channel. + * In case user passes a specific TCC + * value, pTcc value is left unchanged. + * In case user requests ANY available TCC, + * the allocated one is returned in pTcc + * + * \return EDMA3_RM_SOK or EDMA_RM Error Code + * + * \note This function internally calls EDMA3_RM_allocResource (), which + * acquires a RM Instance specific semaphore to prevent simultaneous + * access to the global pool of resources. It is re-entrant for unique + * logical channel values, but SHOULD NOT be called from the user + * callback function (ISR context). + */ +EDMA3_RM_Result EDMA3_RM_allocLogicalChannel(EDMA3_RM_Handle hEdmaResMgr, + EDMA3_RM_ResDesc *lChObj, + unsigned int *pParam, + unsigned int *pTcc) + { + EDMA3_RM_ResDesc *chObj; + EDMA3_RM_ResDesc resObj; + EDMA3_RM_Result result = EDMA3_RM_SOK; + EDMA3_RM_Instance *rmInstance = NULL; + EDMA3_RM_Obj *rmObj = NULL; + unsigned int mappedPaRAMId=0u; + unsigned int mappedTcc = EDMA3_RM_CH_NO_TCC_MAP; + int paRAMId = (int)EDMA3_RM_RES_ANY; + volatile EDMA3_CCRL_Regs *gblRegs = NULL; + unsigned int qdmaChId = EDMA3_MAX_PARAM_SETS; + + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_RM_PARAM_CHECK_DISABLE + if ((lChObj == NULL) || (hEdmaResMgr == NULL)) + { + result = EDMA3_RM_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_RM_SOK == result) + { + chObj = lChObj; + + if ((chObj->type == EDMA3_RM_RES_DMA_CHANNEL) + || (chObj->type == EDMA3_RM_RES_QDMA_CHANNEL)) + { + /** + * If the request is for a DMA or QDMA channel, check the + * pParam and pTcc objects also. + * For the Link channel request, they could be NULL. + */ + /* If parameter checking is enabled... */ +#ifndef EDMA3_RM_PARAM_CHECK_DISABLE + if ((pParam == NULL) || (pTcc == NULL)) + { + result = EDMA3_RM_E_INVALID_PARAM; + } +#endif + } + } + + if (result == EDMA3_RM_SOK) + { + rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr; + + if (rmInstance == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + + if (result == EDMA3_RM_SOK) + { + rmObj = rmInstance->pResMgrObjHandle; + + if (rmObj == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + else + { + if (rmObj->gblCfgParams.globalRegs == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + } + + if (result == EDMA3_RM_SOK) + { + gblRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs); + + switch (chObj->type) + { + case EDMA3_RM_RES_DMA_CHANNEL: + { + if ((chObj->resId == EDMA3_RM_DMA_CHANNEL_ANY) + || (chObj->resId == EDMA3_RM_RES_ANY)) + { + /* Request for ANY DMA channel. */ + resObj.type = EDMA3_RM_RES_DMA_CHANNEL; + resObj.resId = EDMA3_RM_RES_ANY; + result = EDMA3_RM_allocResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj); + + if (result == EDMA3_RM_SOK) + { + /* DMA channel allocated successfully. */ + chObj->resId = resObj.resId; + + /** + * Check the PaRAM Set user has specified for this DMA channel. + * Two cases exist: + * a) DCHMAP exists: Any PaRAM Set can be used + * b) DCHMAP does not exist: Should not be possible + * only if the channel allocated (ANY) and PaRAM requested + * are same. + */ + if ((*pParam) == EDMA3_RM_PARAM_ANY) + { + /* User specified ANY PaRAM Set; Check the mapping. */ + mappedPaRAMId = rmObj->gblCfgParams.dmaChannelPaRAMMap[resObj.resId]; + if (mappedPaRAMId != EDMA3_RM_CH_NO_PARAM_MAP) + { + /** If some PaRAM set is statically mapped to the returned + * channel number, use that. + */ + paRAMId = (int)mappedPaRAMId; + } + } + else + { + /* User specified some PaRAM Set; check that can be used or not. */ + if (TRUE == rmObj->gblCfgParams.dmaChPaRAMMapExists) + { + paRAMId = (int)(*pParam); + } + else + { + /** + * Channel mapping does not exist. If the PaRAM Set requested + * is the same as dma channel allocated (coincidentally), it is fine. + * Else return error. + */ + if ((*pParam) != (resObj.resId)) + { + result = EDMA3_RM_E_INVALID_PARAM; + + /** + * Free the previously allocated DMA channel also. + */ + EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj); + } + else + { + paRAMId = (int)(*pParam); + } + } + } + + mappedTcc = rmObj->gblCfgParams.dmaChannelTccMap[resObj.resId]; + } + } + else + { + if (chObj->resId <= EDMA3_RM_DMA_CH_MAX_VAL) + { + /* Request for a specific DMA channel */ + resObj.type = EDMA3_RM_RES_DMA_CHANNEL; + resObj.resId = chObj->resId; + result = EDMA3_RM_allocResource(hEdmaResMgr, + (EDMA3_RM_ResDesc *)&resObj); + + if (result == EDMA3_RM_SOK) + { + /** + * Check the PaRAM Set user has specified for this DMA channel. + * Two cases exist: + * a) DCHMAP exists: Any PaRAM Set can be used + * b) DCHMAP does not exist: Should not be possible + * only if the channel allocated (ANY) and PaRAM requested + * are same. + */ + if ((*pParam) == EDMA3_RM_PARAM_ANY) + { + /* User specified ANY PaRAM Set; Check the mapping. */ + mappedPaRAMId = rmObj->gblCfgParams.dmaChannelPaRAMMap[resObj.resId]; + if (mappedPaRAMId != EDMA3_RM_CH_NO_PARAM_MAP) + { + /** If some PaRAM set is statically mapped to the returned + * channel number, use that. + */ + paRAMId = (int)mappedPaRAMId; + } + } + else + { + /* User specified some PaRAM Set; check that can be used or not. */ + if (TRUE == rmObj->gblCfgParams.dmaChPaRAMMapExists) + { + paRAMId = (int)(*pParam); + } + else + { + /** + * Channel mapping does not exist. If the PaRAM Set requested + * is the same as dma channel allocated (coincidentally), it is fine. + * Else return error. + */ + if ((*pParam) != (resObj.resId)) + { + result = EDMA3_RM_E_INVALID_PARAM; + + /** + * Free the previously allocated DMA channel also. + */ + EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj); + } + else + { + paRAMId = (int)(*pParam); + } + } + } + + mappedTcc = rmObj->gblCfgParams.dmaChannelTccMap[chObj->resId]; + } + } + else + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + } + break; + + + case EDMA3_RM_RES_QDMA_CHANNEL: + { + if ((chObj->resId == EDMA3_RM_QDMA_CHANNEL_ANY) + || (chObj->resId == EDMA3_RM_RES_ANY)) + { + /* First request for any available QDMA channel */ + resObj.type = EDMA3_RM_RES_QDMA_CHANNEL; + resObj.resId = EDMA3_RM_RES_ANY; + result = EDMA3_RM_allocResource(hEdmaResMgr, + (EDMA3_RM_ResDesc *)&resObj); + + if (result == EDMA3_RM_SOK) + { + /* Return the actual QDMA channel id. */ + chObj->resId = resObj.resId; + + /* Save the Logical-QDMA channel id for future use. */ + qdmaChId = resObj.resId + EDMA3_RM_QDMA_CH_MIN_VAL; + + /** + * Check the PaRAM Set user has specified for this QDMA channel. + * If he has specified any particular PaRAM Set, use that. + */ + if ((*pParam) != EDMA3_RM_PARAM_ANY) + { + /* User specified ANY PaRAM Set; Check the mapping. */ + paRAMId = (int)(*pParam); + } + } + } + else + { + if (chObj->resId < EDMA3_MAX_QDMA_CH) + { + /* Request for a specific QDMA channel */ + resObj.type = EDMA3_RM_RES_QDMA_CHANNEL; + resObj.resId = chObj->resId; + result = EDMA3_RM_allocResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj); + + if (result == EDMA3_RM_SOK) + { + /* Save the Logical-QDMA channel id for future use. */ + qdmaChId = chObj->resId + EDMA3_RM_QDMA_CH_MIN_VAL; + + /** + * Check the PaRAM Set user has specified for this QDMA channel. + * If he has specified any particular PaRAM Set, use that. + */ + if ((*pParam) != EDMA3_RM_PARAM_ANY) + { + /* User specified ANY PaRAM Set; Check the mapping. */ + paRAMId = (int)(*pParam); + } + } + } + else + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + } + break; + + case EDMA3_RM_RES_PARAM_SET: + { + /* Request for a LINK channel. */ + if ((chObj->resId == EDMA3_RM_PARAM_ANY) + || (chObj->resId == EDMA3_RM_RES_ANY)) + { + /* Request for ANY LINK channel. */ + paRAMId = (int)EDMA3_RM_RES_ANY; + } + else + { + if (chObj->resId < edma3NumPaRAMSets) + { + /* Request for a Specific LINK channel. */ + paRAMId = (int)(chObj->resId); + } + else + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + + if (result == EDMA3_RM_SOK) + { + /* Try to allocate the link channel */ + resObj.type = EDMA3_RM_RES_PARAM_SET; + resObj.resId = (unsigned int)paRAMId; + result = EDMA3_RM_allocResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj); + + if (result == EDMA3_RM_SOK) + { + unsigned int linkCh = EDMA3_RM_LINK_CH_MIN_VAL; + + /* Return the actual PaRAM Id. */ + chObj->resId = resObj.resId; + + /* + * Search for the next Link channel place-holder available, + * starting from EDMA3_RM_LINK_CH_MIN_VAL. + * It will be used for future operations on the Link channel. + */ + while ((edma3RmChBoundRes[rmObj->phyCtrllerInstId][linkCh].paRAMId != -1) + && (linkCh <= EDMA3_RM_LINK_CH_MAX_VAL)) + { + /* Move to the next place-holder. */ + linkCh++; + } + + /* Verify the returned handle, it should lie in the correct range */ + if (linkCh > EDMA3_RM_LINK_CH_MAX_VAL) + { + result = EDMA3_RM_E_INVALID_PARAM; + + /* Free the PaRAM Set now. */ + resObj.type = EDMA3_RM_RES_PARAM_SET; + resObj.resId = chObj->resId; + result = EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj); + } + else + { + /* Save the PaRAM Id for the Link Channel. */ + edma3RmChBoundRes[rmObj->phyCtrllerInstId][linkCh].paRAMId = (int)(chObj->resId); + + /** + * Remove any linking. Before doing that, check + * whether it is permitted or not. + */ + if (TRUE == rmInstance->regModificationRequired) + { + *((&gblRegs->PARAMENTRY[chObj->resId].OPT) + + (unsigned int)EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD) = 0xFFFFu; + } + } + } + } + } + break; + + default: + result = EDMA3_RM_E_INVALID_PARAM; + } + } + + + if (result == EDMA3_RM_SOK) + { + /** + * For DMA/QDMA channels, we still have to allocate more resources like + * TCC, PaRAM Set etc. + * For Link channel, only the PaRAMSet is required and that has been + * allocated so no further operations required. + */ + + /* Further resources' allocation for DMA channel. */ + if (chObj->type == EDMA3_RM_RES_DMA_CHANNEL) + { + /* First allocate a PaRAM Set */ + resObj.type = EDMA3_RM_RES_PARAM_SET; + /* Use the saved param id now. */ + resObj.resId = (unsigned int)paRAMId; + result = EDMA3_RM_allocResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj); + if (result == EDMA3_RM_SOK) + { + /** + * PaRAM Set allocation succeeded. + * Save the PaRAM Set first. + */ + *pParam = resObj.resId; + edma3RmChBoundRes[rmObj->phyCtrllerInstId][chObj->resId].paRAMId = (int)(resObj.resId); + + /* Allocate the TCC now. */ + resObj.type = EDMA3_RM_RES_TCC; + if ((*pTcc) == EDMA3_RM_TCC_ANY) + { + if (mappedTcc == EDMA3_RM_CH_NO_TCC_MAP) + { + resObj.resId = EDMA3_RM_RES_ANY; + } + else + { + resObj.resId = mappedTcc; + } + } + else + { + resObj.resId = *pTcc; + } + + result = EDMA3_RM_allocResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj); + if (result == EDMA3_RM_SOK) + { + /* TCC allocation succeeded. Save it first. */ + *pTcc = resObj.resId; + edma3RmChBoundRes[rmObj->phyCtrllerInstId][chObj->resId].tcc = resObj.resId; + + /** + * Check first whether the global registers and the allocated + * PaRAM Set can be modified or not. If yes, do the needful. + * Else leave this for the user. + */ + if (TRUE == rmInstance->regModificationRequired) + { + /* Set TCC of the allocated Param Set. */ + gblRegs->PARAMENTRY[*pParam].OPT &= EDMA3_RM_OPT_TCC_CLR_MASK; + gblRegs->PARAMENTRY[*pParam].OPT |= EDMA3_RM_OPT_TCC_SET_MASK(*pTcc); + + /** + * Do the mapping between DMA channel and PaRAM Set. + * Do this for the EDMA3 Controllers which have a register for mapping + * DMA Channel to a particular PaRAM Set. + */ + if (TRUE == rmObj->gblCfgParams.dmaChPaRAMMapExists) + { + gblRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs); + + /* Map Parameter RAM Set Number for specified channelId */ + gblRegs->DCHMAP[chObj->resId] &= EDMA3_RM_DCH_PARAM_CLR_MASK; + gblRegs->DCHMAP[chObj->resId] |= EDMA3_RM_DCH_PARAM_SET_MASK(*pParam); + } + + /* Remove any linking */ + *((&gblRegs->PARAMENTRY[*pParam].OPT) + + (unsigned int)EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD) = 0xFFFFu; + } + } + else + { + /** + * TCC allocation failed, free the previously allocated + * PaRAM Set and DMA channel. + */ + resObj.type = EDMA3_RM_RES_PARAM_SET; + resObj.resId = *pParam; + EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj); + + /* Reset the book-keeping data structure also. */ + edma3RmChBoundRes[rmObj->phyCtrllerInstId][chObj->resId].paRAMId = -1; + + resObj.type = chObj->type; + resObj.resId = chObj->resId; + EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj); + } + } + else + { + /** + * PaRAM Set allocation failed, free the previously allocated + * DMA channel also. + */ + resObj.type = chObj->type; + resObj.resId = chObj->resId; + EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj); + } + } + + + /* Further resources' allocation for QDMA channel. */ + if (chObj->type == EDMA3_RM_RES_QDMA_CHANNEL) + { + /* First allocate a PaRAM Set */ + resObj.type = EDMA3_RM_RES_PARAM_SET; + /* Use the saved param id now. */ + resObj.resId = (unsigned int)paRAMId; + result = EDMA3_RM_allocResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj); + if (result == EDMA3_RM_SOK) + { + /** + * PaRAM Set allocation succeeded. + * Save the PaRAM Set first. + */ + *pParam = resObj.resId; + edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].paRAMId = (int)(resObj.resId); + + /* Allocate the TCC now. */ + resObj.type = EDMA3_RM_RES_TCC; + if ((*pTcc) == EDMA3_RM_TCC_ANY) + { + if (mappedTcc == EDMA3_RM_CH_NO_TCC_MAP) + { + resObj.resId = EDMA3_RM_RES_ANY; + } + else + { + resObj.resId = mappedTcc; + } + } + else + { + resObj.resId = *pTcc; + } + + result = EDMA3_RM_allocResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj); + if (result == EDMA3_RM_SOK) + { + /* TCC allocation succeeded. Save it first. */ + *pTcc = resObj.resId; + edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].tcc = resObj.resId; + + /** + * Check first whether the global registers and the allocated + * PaRAM Set can be modified or not. If yes, do the needful. + * Else leave this for the user. + */ + if (TRUE == rmInstance->regModificationRequired) + { + /* Set TCC of the allocated Param Set. */ + gblRegs->PARAMENTRY[*pParam].OPT &= EDMA3_RM_OPT_TCC_CLR_MASK; + gblRegs->PARAMENTRY[*pParam].OPT |= EDMA3_RM_OPT_TCC_SET_MASK(*pTcc); + + /* Do the mapping between QDMA channel and PaRAM Set. */ + /* Map Parameter RAM Set Number for specified channelId */ + gblRegs->QCHMAP[chObj->resId] + &= EDMA3_RM_QCH_PARAM_CLR_MASK; + gblRegs->QCHMAP[chObj->resId] + |= EDMA3_RM_QCH_PARAM_SET_MASK(*pParam); + + /* Set the Trigger Word */ + gblRegs->QCHMAP[chObj->resId] + &= EDMA3_RM_QCH_TRWORD_CLR_MASK; + gblRegs->QCHMAP[chObj->resId] + |= EDMA3_RM_QCH_TRWORD_SET_MASK(EDMA3_RM_QDMA_TRIG_DEFAULT); + + /* Remove any linking */ + *((&gblRegs->PARAMENTRY[*pParam].OPT) + + (unsigned int)EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD) = 0xFFFFu; + + /* Enable the transfer also. */ + rmInstance->shadowRegs->QEESR = (1u << chObj->resId); + } + } + else + { + /** + * TCC allocation failed, free the previously allocated + * PaRAM Set and QDMA channel. + */ + resObj.type = EDMA3_RM_RES_PARAM_SET; + resObj.resId = *pParam; + EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj); + + /* Reset the book-keeping data structure also. */ + edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].paRAMId = -1; + + resObj.type = chObj->type; + resObj.resId = chObj->resId; + EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj); + } + } + else + { + /** + * PaRAM Set allocation failed, free the previously allocated + * QDMA channel also. + */ + resObj.type = chObj->type; + resObj.resId = chObj->resId; + EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj); + } + } + } + + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + + return result; + } + + +/** \fn EDMA3_RM_Result EDMA3_RM_freeLogicalChannel (EDMA3_RM_Handle + * hEdmaResMgr, EDMA3_RM_ResDesc *lChObj) + * \brief This API is used to free the specified channel (DMA/QDMA/Link) and + * its associated resources (PaRAM Set, TCC etc). + * + * This API internally uses EDMA3_RM_freeResource () to free the desired + * resources. + * + * For DMA/QDMA channels, it also clears the DCHMAP/QCHMAP registers + * + * \param hEdmaResMgr [IN] Handle to the previously opened Resource + * Manager Instance. + * \param lChObj [IN] Handle to the logical channel object, + * which needs to be freed + * + * \return EDMA3_RM_SOK or EDMA_RM Error Code + * + * \note This is a re-entrant function which internally calls + * EDMA3_RM_freeResource () for resource de-allocation. + */ +EDMA3_RM_Result EDMA3_RM_freeLogicalChannel (EDMA3_RM_Handle hEdmaResMgr, + EDMA3_RM_ResDesc *lChObj) + { + EDMA3_RM_ResDesc *chObj; + EDMA3_RM_ResDesc resObj; + EDMA3_RM_Result result = EDMA3_RM_SOK; + EDMA3_RM_Instance *rmInstance = NULL; + EDMA3_RM_Obj *rmObj = NULL; + int paRAMId; + unsigned int tcc; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + unsigned int qdmaChId; + unsigned int dmaChId; + EDMA3_RM_InstanceInitConfig *rmConfig = NULL; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + + /* If parameter checking is enabled... */ +#ifndef EDMA3_RM_PARAM_CHECK_DISABLE + if ((lChObj == NULL) || (hEdmaResMgr == NULL)) + { + result = (EDMA3_RM_E_INVALID_PARAM); + } +#endif + + /* Check if the parameters are OK. */ + if (result == EDMA3_RM_SOK) + { + chObj = lChObj; + + rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr; + + if (rmInstance == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + + if (result == EDMA3_RM_SOK) + { + rmConfig = rmInstance->initParam.rmInstInitConfig; + rmObj = rmInstance->pResMgrObjHandle; + + if (rmObj == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + else + { + if (rmObj->gblCfgParams.globalRegs == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + else + { + globalRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs); + } + } + } + + + if (result == EDMA3_RM_SOK) + { + switch (chObj->type) + { + case EDMA3_RM_RES_DMA_CHANNEL: + { + /* Save the DMA channel first. */ + dmaChId = chObj->resId; + + /** + * Validate DMA channel id first. + * It should be a valid channel id. + */ + if (dmaChId >= EDMA3_MAX_DMA_CH) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + + /* It should be owned and allocated by this RM only. */ + if (result == EDMA3_RM_SOK) + { + if (((rmConfig->ownDmaChannels[dmaChId/32u]) + & + (~(rmInstance->avlblDmaChannels[dmaChId/32u])) + & + (1u << (dmaChId%32u))) != FALSE) + { + /** Perfectly valid channel id. + * Clear some channel specific registers, if it is permitted. + */ + if (TRUE == rmInstance->regModificationRequired) + { + if (dmaChId < 32u) + { + if((rmInstance->shadowRegs->SER & (1u<shadowRegs->SECR = (1u<EMR & (1u<EMCR = (1u<shadowRegs->SERH & (1u<<(dmaChId-32u)))!=FALSE) + { + rmInstance->shadowRegs->SECRH = (1u<<(dmaChId-32u)); + } + if((globalRegs->EMRH & (1u<<(dmaChId-32u)))!=FALSE) + { + globalRegs->EMCRH = (1u<<(dmaChId-32u)); + } + } + + /* Clear DCHMAP register also. */ + if (TRUE == rmObj->gblCfgParams.dmaChPaRAMMapExists) + { + globalRegs->DCHMAP[dmaChId] &= + EDMA3_RM_DCH_PARAM_CLR_MASK; + } + } + + /* Free the PaRAM Set Now. */ + paRAMId = edma3RmChBoundRes[rmObj->phyCtrllerInstId][dmaChId].paRAMId; + resObj.type = EDMA3_RM_RES_PARAM_SET; + resObj.resId = (unsigned int)paRAMId; + result = EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj); + } + else + { + /* Channel id has some problem. */ + result = EDMA3_RM_E_INVALID_PARAM; + } + } + + + if (result == EDMA3_RM_SOK) + { + /* PaRAM Set Freed */ + edma3RmChBoundRes[rmObj->phyCtrllerInstId][dmaChId].paRAMId = -1; + + /* Free the TCC */ + tcc = edma3RmChBoundRes[rmObj->phyCtrllerInstId][dmaChId].tcc; + resObj.type = EDMA3_RM_RES_TCC; + resObj.resId = tcc; + result = EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj); + } + + if (result == EDMA3_RM_SOK) + { + /* TCC Freed */ + edma3RmChBoundRes[rmObj->phyCtrllerInstId][dmaChId].tcc = EDMA3_MAX_TCC; + + /** + * Try to free the DMA Channel now. DMA Channel should + * be freed only in the end because while freeing, DRAE + * registers will be RESET. + * After that, no shadow region specific DMA channel + * register can be modified. So reset that DRAE register + * ONLY in the end. + */ + resObj.type = EDMA3_RM_RES_DMA_CHANNEL; + resObj.resId = dmaChId; + result = EDMA3_RM_freeResource(hEdmaResMgr, + (EDMA3_RM_ResDesc *)&resObj); + } + } + break; + + + case EDMA3_RM_RES_QDMA_CHANNEL: + { + /** + * Calculate QDMA Logical Channel Id first. + * User has given the actual QDMA channel id. + * So we have to convert it to make the logical + * QDMA channel id first. + */ + qdmaChId = chObj->resId + EDMA3_RM_QDMA_CH_MIN_VAL; + + /** + * Validate QDMA channel id first. + * It should be a valid channel id. + */ + if (chObj->resId >= EDMA3_MAX_QDMA_CH) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + + /* It should be owned and allocated by this RM only. */ + if (result == EDMA3_RM_SOK) + { + if (((rmConfig->ownQdmaChannels[0u]) + & + (~(rmInstance->avlblQdmaChannels[0u])) + & + (1u << chObj->resId)) != FALSE) + { + /** Perfectly valid channel id. + * Clear some channel specific registers, if + * it is permitted. + */ + if (TRUE == rmInstance->regModificationRequired) + { + rmInstance->shadowRegs->QEECR = (1u<resId); + + if((globalRegs->QEMR & (1u<resId))!=FALSE) + { + globalRegs->QEMCR = (1u<resId); + } + + /* Unmap PARAM Set Number for specified channelId */ + globalRegs->QCHMAP[chObj->resId] &= + EDMA3_RM_QCH_PARAM_CLR_MASK; + + /* Reset the Trigger Word */ + globalRegs->QCHMAP[chObj->resId] &= + EDMA3_RM_QCH_TRWORD_CLR_MASK; + } + + /* Free the PaRAM Set now */ + paRAMId = edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].paRAMId; + resObj.type = EDMA3_RM_RES_PARAM_SET; + resObj.resId = (int)paRAMId; + result = EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj); + } + else + { + /* Channel id has some problem. */ + result = EDMA3_RM_E_INVALID_PARAM; + } + } + + + if (result == EDMA3_RM_SOK) + { + /* PaRAM Set Freed */ + edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].paRAMId = -1; + + /* Free the TCC */ + tcc = edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].tcc; + resObj.type = EDMA3_RM_RES_TCC; + resObj.resId = tcc; + result = EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj); + } + + if (result == EDMA3_RM_SOK) + { + /* TCC Freed */ + edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].tcc = EDMA3_MAX_TCC; + + /** + * Try to free the QDMA Channel now. QDMA Channel should + * be freed only in the end because while freeing, QRAE + * registers will be RESET. + * After that, no shadow region specific QDMA channel + * register can be modified. So reset that QDRAE register + * ONLY in the end. + */ + resObj.type = EDMA3_RM_RES_QDMA_CHANNEL; + resObj.resId = chObj->resId; + result = EDMA3_RM_freeResource(hEdmaResMgr, + (EDMA3_RM_ResDesc *)&resObj); + } + } + break; + + + case EDMA3_RM_RES_PARAM_SET: + { + /* Link Channel */ + if (chObj->resId < edma3NumPaRAMSets) + { + resObj.type = EDMA3_RM_RES_PARAM_SET; + resObj.resId = chObj->resId; + + result = EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj); + if (result == EDMA3_RM_SOK) + { + /* PaRAM Set freed successfully. */ + unsigned int linkCh = EDMA3_RM_LINK_CH_MIN_VAL; + + /* Reset the Logical-Link channel */ + /* Search for the Logical-Link channel first */ + for (linkCh = EDMA3_RM_LINK_CH_MIN_VAL; + linkCh < EDMA3_RM_LINK_CH_MAX_VAL; + linkCh++) + { + if (edma3RmChBoundRes[rmObj->phyCtrllerInstId][linkCh].paRAMId == chObj->resId) + { + edma3RmChBoundRes[rmObj->phyCtrllerInstId][linkCh].paRAMId = -1; + break; + } + } + } + } + else + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + break; + + default: + result = EDMA3_RM_E_INVALID_PARAM; + } + } + + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + + +/**\fn EDMA3_RM_Result EDMA3_RM_mapEdmaChannel (EDMA3_RM_Handle + * hEdmaResMgr, unsigned int channelId, unsigned int paRAMId) + * \brief Bind the resources DMA Channel and PaRAM Set. Both the DMA channel + * and the PaRAM set should be previously allocated. If they are not, + * this API will result in error. + * + * This API sets the DCHMAP register for a specific DMA channel. This register + * is used to specify the PaRAM Set associated with that particular DMA Channel. + * + * \param hEdmaResMgr [IN] Handle to the previously opened Resource + * Manager Instance. + * \param channelId [IN] Previously allocated DMA Channel on which + * Transfer will occur. + * \param paRAMId [IN] Previously allocated PaRAM Set which + * needs to be associated with the dma channel. + * + * \return EDMA3_RM_SOK or EDMA_RM Error Code + * + * \note This API is useful only for the EDMA3 Controllers which have a + * register for mapping a DMA Channel to a particular PaRAM Set + * (DCHMAP register). + * On platforms where this feature is not supported, this API + * returns error code: EDMA3_RM_E_FEATURE_UNSUPPORTED. + * This function is re-entrant for unique channelId. It is + * non-re-entrant for same channelId values. + */ +EDMA3_RM_Result EDMA3_RM_mapEdmaChannel (EDMA3_RM_Handle hEdmaResMgr, + unsigned int channelId, + unsigned int paRAMId) + { + EDMA3_RM_Instance *rmInstance = NULL; + EDMA3_RM_Obj *rmObj = NULL; + EDMA3_RM_Result result = EDMA3_RM_SOK; + volatile EDMA3_CCRL_Regs *gblRegs = NULL; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_RM_PARAM_CHECK_DISABLE + if (hEdmaResMgr == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } +#endif + + if (result == EDMA3_RM_SOK) + { + rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr; + + if (rmInstance == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + + if (result == EDMA3_RM_SOK) + { + rmObj = rmInstance->pResMgrObjHandle; + + if (rmObj == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + else + { + if (rmObj->gblCfgParams.globalRegs == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + } + + if (result == EDMA3_RM_SOK) + { + gblRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs); + + /* If parameter checking is enabled... */ +#ifndef EDMA3_RM_PARAM_CHECK_DISABLE + if ((paRAMId >= rmObj->gblCfgParams.numPaRAMSets) + || (channelId >= rmObj->gblCfgParams.numDmaChannels)) + { + result = EDMA3_RM_E_INVALID_PARAM; + } +#endif + } + + /* DMA channel and PaRAM Set should be previously allocated. */ + if (result == EDMA3_RM_SOK) + { + if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[channelId/32u]) + & + (~(rmInstance->avlblDmaChannels[channelId/32u])) + & + (1u << (channelId%32u))) != FALSE) + { + /* DMA channel allocated, check for the PaRAM Set */ + if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets[paRAMId/32u]) + & + (~(rmInstance->avlblPaRAMSets[paRAMId/32u])) + & + (1u << (paRAMId%32u))) == FALSE) + { + /* PaRAM Set NOT allocated, return error */ + result = EDMA3_RM_E_RES_NOT_ALLOCATED; + } + } + else + { + /* DMA channel NOT allocated, return error */ + result = EDMA3_RM_E_RES_NOT_ALLOCATED; + } + } + + + if (result == EDMA3_RM_SOK) + { + /* Map the Dma Channel to the PaRAM Set corresponding to paramId */ + /** + * Do this for the EDMA3 Controllers which have a register for mapping + * DMA Channel to a particular PaRAM Set. So check + * dmaChPaRAMMapExists first. + */ + if (TRUE == rmObj->gblCfgParams.dmaChPaRAMMapExists) + { + /* Map Parameter RAM Set Number for specified channelId */ + gblRegs->DCHMAP[channelId] &= EDMA3_RM_DCH_PARAM_CLR_MASK; + gblRegs->DCHMAP[channelId] |= EDMA3_RM_DCH_PARAM_SET_MASK(paRAMId); + } + else + { + /* Feature NOT supported on the current platform, return error. */ + result = EDMA3_RM_E_FEATURE_UNSUPPORTED; + } + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + + + +/**\fn EDMA3_RM_Result EDMA3_RM_mapQdmaChannel (EDMA3_RM_Handle + * hEdmaResMgr, unsigned int channelId, + * unsigned int paRAMId, + * EDMA3_RM_QdmaTrigWord trigWord) + * \brief Bind the resources QDMA Channel and PaRAM Set. Also, Set the + * trigger word for the QDMA channel. Both the QDMA channel and the PaRAM set + * should be previously allocated. If they are not, this API will result in error. + * + * This API sets the QCHMAP register for a specific QDMA channel. This register + * is used to specify the PaRAM Set associated with that particular QDMA + * Channel along with the trigger word. + * + * \param hEdmaResMgr [IN] Handle to the previously opened Resource + * Manager Instance. + * \param channelId [IN] Previously allocated QDMA Channel on which + * Transfer will occur. + * \param paRAMId [IN] Previously allocated PaRAM Set, which needs to + * be associated with channelId + * \param trigWord [IN] The Trigger Word for the channel. + * Trigger Word is the word in the PaRAM + * Register Set which - when written to by CPU + * -will start the QDMA transfer automatically + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + * + * \note This function is re-entrant for unique channelId. It is non-re-entrant + * for same channelId values. + */ +EDMA3_RM_Result EDMA3_RM_mapQdmaChannel (EDMA3_RM_Handle hEdmaResMgr, + unsigned int channelId, + unsigned int paRAMId, + EDMA3_RM_QdmaTrigWord trigWord) + { + EDMA3_RM_Instance *rmInstance = NULL; + EDMA3_RM_Obj *rmObj = NULL; + EDMA3_RM_Result result = EDMA3_RM_SOK; + volatile EDMA3_CCRL_Regs *gblRegs = NULL; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_RM_PARAM_CHECK_DISABLE + if ((hEdmaResMgr == NULL) + || ((trigWord < EDMA3_RM_QDMA_TRIG_OPT) + || (trigWord > EDMA3_RM_QDMA_TRIG_CCNT))) + { + result = EDMA3_RM_E_INVALID_PARAM; + } +#endif + + if (result == EDMA3_RM_SOK) + { + rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr; + + if (rmInstance == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + + if (result == EDMA3_RM_SOK) + { + rmObj = rmInstance->pResMgrObjHandle; + + if (rmObj == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + else + { + if (rmObj->gblCfgParams.globalRegs == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + } + + if (result == EDMA3_RM_SOK) + { + gblRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs); + + /* If parameter checking is enabled... */ +#ifndef EDMA3_RM_PARAM_CHECK_DISABLE + if ((paRAMId >= rmObj->gblCfgParams.numPaRAMSets) + || (channelId >= rmObj->gblCfgParams.numQdmaChannels)) + { + result = EDMA3_RM_E_INVALID_PARAM; + } +#endif + } + + /* QDMA channel and PaRAM Set should be previously allocated. */ + if (result == EDMA3_RM_SOK) + { + if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[channelId/32u]) + & + (~(rmInstance->avlblQdmaChannels[channelId/32u])) + & + (1u << (channelId%32u))) != FALSE) + { + /* QDMA channel allocated, check for the PaRAM Set */ + if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets[paRAMId/32u]) + & + (~(rmInstance->avlblPaRAMSets[paRAMId/32u])) + & + (1u << (paRAMId%32u))) == FALSE) + { + /* PaRAM Set NOT allocated, return error */ + result = EDMA3_RM_E_RES_NOT_ALLOCATED; + } + } + else + { + /* QDMA channel NOT allocated, return error */ + result = EDMA3_RM_E_RES_NOT_ALLOCATED; + } + } + + if (result == EDMA3_RM_SOK) + { + /* Map Parameter RAM Set Number for specified channelId */ + gblRegs->QCHMAP[channelId] &= EDMA3_RM_QCH_PARAM_CLR_MASK; + gblRegs->QCHMAP[channelId] |= EDMA3_RM_QCH_PARAM_SET_MASK(paRAMId); + + /* Set the Trigger Word */ + gblRegs->QCHMAP[channelId] &= EDMA3_RM_QCH_TRWORD_CLR_MASK; + gblRegs->QCHMAP[channelId] |= EDMA3_RM_QCH_TRWORD_SET_MASK(trigWord); + } + + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + + +/** + * \fn EDMA3_RM_Result EDMA3_RM_registerTccCb(EDMA3_RM_Handle hEdmaResMgr, + * const EDMA3_RM_ResDesc *channelObj, unsigned int tcc, + * EDMA3_RM_TccCallback tccCb, void *cbData); + * \brief Register Interrupt / Completion Handler for a given TCC. + * + * This function enables the interrupts in IESR/IESRH, only if the callback + * function provided by the user is NON-NULL. Moreover, if a call-back function + * is already registered against that TCC, the API fails with the error code + * EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED. For a NULL callback function, + * this API returns error. + * + * \param hEdmaResMgr [IN] Handle to the previously opened + * EDMA3 Resource Manager Instance + * \param channelObj [IN] Channel ID and type (DMA or QDMA + * Channel), allocated earlier, and + * corresponding to which a callback + * function needs to be registered + * against the associated TCC. + * \param tcc [IN] TCC against which the handler needs to + * be registered. + * \param tccCb [IN] The Callback function to be registered + * against the TCC. + * \param cbData [IN] Callback data to be passed while calling + * the callback function. + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + * + * \note This function is re-entrant for unique tcc values. It is non- + * re-entrant for same tcc value. + */ +EDMA3_RM_Result EDMA3_RM_registerTccCb(EDMA3_RM_Handle hEdmaResMgr, + const EDMA3_RM_ResDesc *channelObj, + unsigned int tcc, + EDMA3_RM_TccCallback tccCb, + void *cbData) + { + EDMA3_RM_Instance *rmInstance = NULL; + EDMA3_RM_Obj *rmObj = NULL; + EDMA3_RM_Result result = EDMA3_RM_SOK; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_RM_PARAM_CHECK_DISABLE + if ((NULL == hEdmaResMgr) || (NULL == channelObj)) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + + /* Callback function should NOT be NULL */ + if (NULL == tccCb) + { + result = EDMA3_RM_E_INVALID_PARAM; + } +#endif + + if (result == EDMA3_RM_SOK) + { + rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr; + rmObj = rmInstance->pResMgrObjHandle; + + if (rmObj == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + + /* If parameter checking is enabled... */ +#ifndef EDMA3_RM_PARAM_CHECK_DISABLE + if ((EDMA3_RM_SOK == result) && (tcc >= rmObj->gblCfgParams.numTccs)) + { + result = EDMA3_RM_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_RM_SOK == result) + { + /* Check whether the callback has already registered. */ + if (NULL != edma3IntrParams[tcc].tccCb) + { + result = EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED; + } + else + { + /* Store the mapping b/w DMA/QDMA channel and TCC first. */ + if (channelObj->type == EDMA3_RM_RES_DMA_CHANNEL) + { + /* DMA channel */ + if (channelObj->resId < rmObj->gblCfgParams.numDmaChannels) + { + /* Save the TCC */ + edma3DmaChTccMapping[channelObj->resId] = tcc; + } + else + { + /* Error!!! */ + result = EDMA3_RM_E_INVALID_PARAM; + } + } + else + { + if (channelObj->type == EDMA3_RM_RES_QDMA_CHANNEL) + { + /* QDMA channel */ + if (channelObj->resId < rmObj->gblCfgParams.numQdmaChannels) + { + /* Save the TCC */ + edma3QdmaChTccMapping[channelObj->resId] = tcc; + } + else + { + /* Error!!! */ + result = EDMA3_RM_E_INVALID_PARAM; + } + } + else + { + /* Error!!! */ + result = EDMA3_RM_E_INVALID_PARAM; + } + } + } + + if (EDMA3_RM_SOK == result) + { + /** + * Enable the interrupts in IESR/IESRH, only if the Callback + * function is NOT NULL. + */ + if (tcc < 32u) + { + rmInstance->shadowRegs->IESR = (1UL << tcc); + } + else + { + rmInstance->shadowRegs->IESRH = (1UL << (tcc-32u)); + } + + /* Save the callback functions also */ + edma3IntrParams[tcc].cbData = cbData; + edma3IntrParams[tcc].tccCb = tccCb; + } + } + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + + + +/** + * \fn EDMA3_RM_Result EDMA3_RM_unregisterTccCb(EDMA3_RM_Handle + * hEdmaResMgr, const EDMA3_RM_ResDesc *channelObj); + * \brief Unregister the previously registered callback function against a + * DMA/QDMA channel. + * + * This function unregisters the previously registered callback function against + * a DMA/QDMA channel by removing any stored callback function. Moreover, it + * clears the interrupt enable register (IESR/IESRH) by writing to the IECR/ + * IECRH register, for the TCC associated with that particular channel. + * + * \param hEdmaResMgr [IN] Handle to the previously opened + * EDMA3 Resource Manager Instance + * \param channelObj [IN] Channel ID and type, allocated earlier + * (DMA or QDMA Channel ONLY), and + * corresponding to which a TCC is there. + * Against that TCC, the callback needs + * to be un-registered. + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code. + * + * \note This function is re-entrant for unique (channelObj->type + + * channelObj->resId) combination. It is non-re-entrant for same + * channelObj Resource. + */ +EDMA3_RM_Result EDMA3_RM_unregisterTccCb(EDMA3_RM_Handle hEdmaResMgr, + const EDMA3_RM_ResDesc *channelObj) + { + EDMA3_RM_Instance *rmInstance = NULL; + EDMA3_RM_Obj *rmObj = NULL; + EDMA3_RM_Result result = EDMA3_RM_SOK; + unsigned int mappedTcc = EDMA3_MAX_TCC; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_RM_PARAM_CHECK_DISABLE + if ((NULL == hEdmaResMgr) || (NULL == channelObj)) + { + result = EDMA3_RM_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_RM_SOK == result) + { + rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr; + rmObj = rmInstance->pResMgrObjHandle; + + if (rmObj == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + else + { + if (channelObj->type == EDMA3_RM_RES_DMA_CHANNEL) + { + /* DMA channel */ + if (channelObj->resId < rmObj->gblCfgParams.numDmaChannels) + { + /* Save the mapped TCC */ + mappedTcc = edma3DmaChTccMapping[channelObj->resId]; + + /* Remove the mapping now. */ + edma3DmaChTccMapping[channelObj->resId] = EDMA3_MAX_TCC; + } + else + { + /* Error!!! */ + result = EDMA3_RM_E_INVALID_PARAM; + } + } + else + { + if (channelObj->type == EDMA3_RM_RES_QDMA_CHANNEL) + { + /* QDMA channel */ + if (channelObj->resId < rmObj->gblCfgParams.numQdmaChannels) + { + /* Save the mapped TCC */ + mappedTcc = edma3QdmaChTccMapping[channelObj->resId]; + + /* Remove the mapping now. */ + edma3QdmaChTccMapping[channelObj->resId] = EDMA3_MAX_TCC; + } + else + { + /* Error!!! */ + result = EDMA3_RM_E_INVALID_PARAM; + } + } + else + { + /* Error!!! */ + result = EDMA3_RM_E_INVALID_PARAM; + } + } + + if (EDMA3_RM_SOK == result) + { + /* Remove the callback function too */ + if (mappedTcc < 32u) + { + rmInstance->shadowRegs->IECR = (1UL << mappedTcc); + } + else + { + rmInstance->shadowRegs->IECRH = (1UL << (mappedTcc-32u)); + } + + edma3IntrParams[mappedTcc].cbData = NULL; + edma3IntrParams[mappedTcc].tccCb = NULL; + } + } + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + +/**\fn EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle + * hEdmaResMgr, EDMA3_RM_ResDesc *firstResIdObj, + * unsigned int numResources) + * \brief Allocate a contiguous region of specified EDMA3 Resource + * like DMA channel, QDMA channel, PaRAM Set or TCC. + * + * This API is used to allocate a contiguous region of specified EDMA3 + * Resources like DMA channel, QDMA channel, PaRAM Set or TCC. + * + * User can specify a particular resource Id to start with and go up to the + * number of resources requested. The specific resource id to start from could + * be passed in 'firstResIdObject->resId' and the number of resources requested + * in 'numResources'. + * + * User can also request ANY available resource(s) of the type + * 'firstResIdObject->type' by specifying 'firstResIdObject->resId' as + * EDMA3_RM_RES_ANY. + * + * ANY types of resources are those resources when user doesn't care about the + * actual resource allocated; user just wants a resource of the type specified. + * One use-case is to perform memory-to-memory data transfer operation. This + * operation can be performed using any available DMA or QDMA channel. User + * doesn't need any specific channel for the same. + * + * To allocate specific contiguous resources, first this API checks whether + * those requested resources are OWNED by the Resource Manager instance. Then + * it checks the current availability of those resources. + * + * To allocate ANY available contiguous resources, this API tries to allocate + * resources from the pool of (owned && non_reserved && available_right_now) + * resources. + * + * After allocating DMA/QDMA channels or TCCs, the same resources are enabled in + * the shadow region specific register (DRAE/DRAEH/QRAE). Allocated PaRAM Sets + * are initialized to NULL before this API returns. + * + * \param hEdmaResMgr [IN] Handle to the previously opened Resource + * Manager Instance. + * \param firstResIdObj [IN] Handle to the first resource descriptor + * object, which needs to be allocated. + * firstResIdObject->resId could be a valid + * resource id in case user wants to + * allocate specific resources OR it could + * be EDMA3_RM_RES_ANY in case user wants + * only the required number of resources + * and doesn't care about which resources + * were allocated. + * \param numResources [IN] Number of contiguous resources user + * wants to allocate. + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + * + * \note This function acquires a RM Instance specific semaphore + * to prevent simultaneous access to the global pool of resources. + * It is re-entrant, but should not be called from the user callback + * function (ISR context). + */ +EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr, + EDMA3_RM_ResDesc *firstResIdObj, + unsigned int numResources) + { + EDMA3_RM_Instance *rmInstance = NULL; + EDMA3_RM_Obj *rmObj = NULL; + EDMA3_RM_Result result = EDMA3_RM_SOK; + EDMA3_RM_ResDesc *resObj = NULL; + unsigned int resAllocIdx = 0u; + unsigned int firstResId; + unsigned int lastResId = 0u; + unsigned int maxNumResources = 0u; + EDMA3_RM_Result semResult = EDMA3_RM_SOK; + unsigned int resIdClr = 0x0; + unsigned int resIdSet = 0x0; + volatile EDMA3_CCRL_Regs *gblRegs = NULL; + unsigned int i = 0u; + unsigned int position = 0u; + + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + + /* If parameter checking is enabled... */ +#ifndef EDMA3_RM_PARAM_CHECK_DISABLE + if ((hEdmaResMgr == NULL) || (firstResIdObj == NULL)) + { + result = EDMA3_RM_E_INVALID_PARAM; + } +#endif + + if (EDMA3_RM_SOK == result) + { + rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr; + if (rmInstance == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + + if (EDMA3_RM_SOK == result) + { + rmObj = rmInstance->pResMgrObjHandle; + + if (rmObj == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + + if (EDMA3_RM_SOK == result) + { + gblRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs); + + if (rmInstance->initParam.rmSemHandle == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + + if (EDMA3_RM_SOK == result) + { + resObj = firstResIdObj; + if (resObj != NULL) + { + firstResId = resObj->resId; + } + + switch (resObj->type) + { + case EDMA3_RM_RES_DMA_CHANNEL : + maxNumResources = rmObj->gblCfgParams.numDmaChannels; + break; + case EDMA3_RM_RES_QDMA_CHANNEL : + maxNumResources = rmObj->gblCfgParams.numQdmaChannels; + break; + case EDMA3_RM_RES_TCC : + maxNumResources = rmObj->gblCfgParams.numTccs; + break; + case EDMA3_RM_RES_PARAM_SET : + maxNumResources = rmObj->gblCfgParams.numPaRAMSets; + break; + default: + result = EDMA3_RM_E_INVALID_PARAM; + break; + } + } + + + if (EDMA3_RM_SOK == result) + { + /* First resource id (firstResId) can be a valid Resource ID as well as + * 'EDMA3_RM_RES_ANY', in case user does not want to + * start from a specific resource. For eg, user allocating link channels. + */ + if (firstResId != EDMA3_RM_RES_ANY) + { + /* User want specific resources. */ + lastResId = firstResId + numResources; + + if (((firstResId >= maxNumResources) || (firstResId > lastResId)) + || (lastResId > maxNumResources)) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + else + { + /* (firstResId == EDMA3_RM_RES_ANY) + * So just check whether the number of resources + * requested does not cross the limit. + */ + if (numResources > maxNumResources) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + } + + + if (result == EDMA3_RM_SOK) + { + /* Now try to allocate resources for the first case */ + if (firstResId != EDMA3_RM_RES_ANY) + { + /* Request for specific resources */ + + /** + * Take the instance specific semaphore, to prevent simultaneous + * access to the shared resources. + */ + semResult = edma3OsSemTake(rmInstance->initParam.rmSemHandle, + EDMA3_OSSEM_NO_TIMEOUT); + + if (EDMA3_RM_SOK == semResult) + { + switch (resObj->type) + { + case EDMA3_RM_RES_DMA_CHANNEL : + { + for (resAllocIdx = firstResId; resAllocIdx < lastResId; ++resAllocIdx) + { + resIdClr = (unsigned int)(~(1u << (resAllocIdx%32u))); + resIdSet = (1u << (resAllocIdx%32u)); + + /* Check whether it is owned or not */ + if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[resAllocIdx/32u])&(resIdSet)) != FALSE) + { + /* Now check if specified resource is available presently*/ + if (((rmInstance->avlblDmaChannels[resAllocIdx/32u])&(resIdSet)) != FALSE) + { + /* + * Mark the specified resource as "Not Available" + * for future requests + */ + rmInstance->avlblDmaChannels[resAllocIdx/32u] &= resIdClr; + + if (resAllocIdx < 32u) + { + rmInstance->shadowRegs->EECR = (1UL << resAllocIdx); + + /** + * Enable the DMA channel in the + * DRAE registers also. + */ + gblRegs->DRA[rmInstance->initParam.regionId].DRAE + |= (0x1u << resAllocIdx); + } + else + { + rmInstance->shadowRegs->EECRH = (1UL << (resAllocIdx - 32u)); + + /** + * Enable the DMA channel in the + * DRAEH registers also. + */ + gblRegs->DRA[rmInstance->initParam.regionId].DRAEH + |= (0x1u << (resAllocIdx - 32u)); + } + + result = EDMA3_RM_SOK; + } + else + { + /* Specified resource is owned but is already booked */ + result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE; + break; + } + } + else + { + /* + * Specified resource is not owned by this instance + * of the Resource Manager + */ + result = EDMA3_RM_E_RES_NOT_OWNED; + break; + } + } + + break; + } + + case EDMA3_RM_RES_QDMA_CHANNEL: + { + for (resAllocIdx = firstResId; resAllocIdx < lastResId; ++resAllocIdx) + { + resIdClr = (unsigned int)(~(1u << resAllocIdx)); + resIdSet = (1u << resAllocIdx); + + /* Check whether it is owned or not */ + if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[0u])&(resIdSet))!=FALSE) + { + /* Now check if specified resource is available presently*/ + if (((rmInstance->avlblQdmaChannels[0u])&(resIdSet))!=FALSE) + { + /* + * Mark the specified resource as "Not Available" + * for future requests + */ + rmInstance->avlblQdmaChannels[0u] &= resIdClr; + + /** + * Enable the QDMA channel in the + * QRAE register also. + */ + gblRegs->QRAE[rmInstance->initParam.regionId] + |= (0x1u << resAllocIdx); + + result = EDMA3_RM_SOK; + } + else + { + /* Specified resource is owned but is already booked */ + result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE; + break; + } + } + else + { + /* + * Specified resource is not owned by this instance + * of the Resource Manager + */ + result = EDMA3_RM_E_RES_NOT_OWNED; + break; + } + } + + break; + } + + case EDMA3_RM_RES_TCC: + { + for (resAllocIdx = firstResId; resAllocIdx < lastResId; ++resAllocIdx) + { + resIdClr = (unsigned int)(~(1u << (resAllocIdx%32u))); + resIdSet = (1u << (resAllocIdx%32u)); + + /* Check whether it is owned or not */ + if (((rmInstance->initParam.rmInstInitConfig->ownTccs[resAllocIdx/32u])&(resIdSet))!=FALSE) + { + /* Now check if specified resource is available presently*/ + if (((rmInstance->avlblTccs[resAllocIdx/32u])&(resIdSet))!=FALSE) + { + /* + * Mark the specified resource as "Not Available" + * for future requests + */ + rmInstance->avlblTccs[resAllocIdx/32u] &= resIdClr; + + /** + * Enable the Interrupt channel in the + * DRAE/DRAEH registers also. + * Also, If the region id coming from this + * RM instance is same as the Master RM + * Instance's region id, only then we will be + * getting the interrupts on the same side. + * So save the TCC in the allocatedTCCs[] array. + */ + if (resAllocIdx < 32u) + { + gblRegs->DRA[rmInstance->initParam.regionId].DRAE + |= (0x1u << resAllocIdx); + + if (edma3RegionId == rmInstance->initParam.regionId) + { + allocatedTCCs[0u] |= (0x1u << resAllocIdx); + } + } + else + { + gblRegs->DRA[rmInstance->initParam.regionId].DRAEH + |= (0x1u << (resAllocIdx - 32u)); + + if (edma3RegionId == rmInstance->initParam.regionId) + { + allocatedTCCs[1u] |= (0x1u << (resAllocIdx - 32u)); + } + } + + result = EDMA3_RM_SOK; + } + else + { + /* Specified resource is owned but is already booked */ + result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE; + break; + } + } + else + { + /* + * Specified resource is not owned by this instance + * of the Resource Manager + */ + result = EDMA3_RM_E_RES_NOT_OWNED; + break; + } + } + + break; + } + + case EDMA3_RM_RES_PARAM_SET: + { + for (resAllocIdx = firstResId; resAllocIdx < lastResId; ++resAllocIdx) + { + resIdClr = (unsigned int)(~(1u << (resAllocIdx%32u))); + resIdSet = (1u << (resAllocIdx%32u)); + + /* Check whether it is owned or not */ + if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets[resAllocIdx/32u])&(resIdSet))!=FALSE) + { + /* Now check if specified resource is available presently*/ + if (((rmInstance->avlblPaRAMSets[resAllocIdx/32u])&(resIdSet))!=FALSE) + { + /* + * Mark the specified resource as "Not Available" + * for future requests + */ + rmInstance->avlblPaRAMSets[resAllocIdx/32u] &= resIdClr; + + /** + * Also, make the actual PARAM Set NULL, checking the flag + * whether it is required or not. + */ + if (TRUE == rmInstance->paramInitRequired) + { + edma3MemSet((void *)(&gblRegs->PARAMENTRY[resAllocIdx]), + 0x00u, + sizeof(gblRegs->PARAMENTRY[resAllocIdx])); + } + + result = EDMA3_RM_SOK; + } + else + { + /* Specified resource is owned but is already booked */ + result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE; + break; + } + } + else + { + /* + * Specified resource is not owned by this instance + * of the Resource Manager + */ + result = EDMA3_RM_E_RES_NOT_OWNED; + break; + } + } + + break; + } + + default: + { + result = EDMA3_RM_E_INVALID_PARAM; + break; + } + } + + /* resource allocation completed, release the semaphore first */ + semResult = edma3OsSemGive(rmInstance->initParam.rmSemHandle); + } + + } + else + { + /* (firstResId == EDMA3_RM_RES_ANY) */ + /** + * Take the instance specific semaphore, to prevent simultaneous + * access to the shared resources. + */ + semResult = edma3OsSemTake(rmInstance->initParam.rmSemHandle, + EDMA3_OSSEM_NO_TIMEOUT); + + if (EDMA3_RM_SOK == semResult) + { + /** + * We have to search three different arrays, namely ownedResoures, + * avlblResources and resvdResources, to find the 'common' contiguous + * resources. For this, take an 'AND' of all three arrays in one single + * array and use your algorithm on that array. + */ + switch (resObj->type) + { + case EDMA3_RM_RES_DMA_CHANNEL: + { + /* AND all the arrays to look into */ + contiguousDmaRes[0u] = ((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[0u] + & rmInstance->avlblDmaChannels[0u]) + & (~(rmInstance->initParam.rmInstInitConfig->resvdDmaChannels[0u])) + ); + contiguousDmaRes[1u] = ((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[1u] + & rmInstance->avlblDmaChannels[1u]) + & (~(rmInstance->initParam.rmInstInitConfig->resvdDmaChannels[1u])) + ); + } + break; + + case EDMA3_RM_RES_QDMA_CHANNEL: + { + /* AND all the arrays to look into */ + contiguousQdmaRes[0u] = ((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[0u] + & rmInstance->avlblQdmaChannels[0u]) + & (~(rmInstance->initParam.rmInstInitConfig->resvdQdmaChannels[0u])) + ); + } + break; + + case EDMA3_RM_RES_TCC: + { + /* AND all the arrays to look into */ + contiguousTccRes[0u] = ((rmInstance->initParam.rmInstInitConfig->ownTccs[0u] + & rmInstance->avlblTccs[0u]) + & (~(rmInstance->initParam.rmInstInitConfig->resvdTccs[0u])) + ); + contiguousTccRes[1u] = ((rmInstance->initParam.rmInstInitConfig->ownTccs[1u] + & rmInstance->avlblTccs[1u]) + & (~(rmInstance->initParam.rmInstInitConfig->resvdTccs[1u])) + ); + } + break; + + case EDMA3_RM_RES_PARAM_SET: + { + /* AND all the arrays to look into */ + for (i = 0u; i < (maxNumResources/32u); ++i) + { + contiguousParamRes[i] = ((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets[i] + & rmInstance->avlblPaRAMSets[i]) + & (~(rmInstance->initParam.rmInstInitConfig->resvdPaRAMSets[i])) + ); + } + } + break; + + default: + { + result = EDMA3_RM_E_INVALID_PARAM; + } + break; + } + + if (EDMA3_RM_SOK == result) + { + /** + * Try to allocate 'numResources' contiguous resources + * of type RES_ANY. + */ + result = allocAnyContigRes (resObj->type, numResources, &position); + + /** + * If result != EDMA3_RM_SOK, resource allocation failed. + * Else resources successfully allocated. + */ + if (result == EDMA3_RM_SOK) + { + /* Update the first resource id with the position returned. */ + resObj->resId = position; + + /* + * Do some further changes in the book-keeping + * data structures and global registers accordingly. + */ + result = gblChngAllocContigRes(rmInstance, resObj, numResources); + } + } + + /* resource allocation completed, release the semaphore first */ + semResult = edma3OsSemGive(rmInstance->initParam.rmSemHandle); + } + } + } + + + /** + * Check the Resource Allocation Result 'result' first. If Resource + * Allocation has resulted in an error, return it (having more priority than + * semResult. Else, return semResult. + */ + if (EDMA3_RM_SOK == result) + { + /** + * Resource Allocation successful, return semResult for returning + * semaphore. + */ + result = semResult; + } + + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + + +/** + * \fn EDMA3_RM_Result EDMA3_RM_freeContiguousResource(EDMA3_RM_Handle + * hEdmaResMgr, EDMA3_RM_ResDesc *firstResIdObj, + * unsigned int numResources) + * \brief Free a contiguous region of specified EDMA3 Resource + * like DMA channel, QDMA channel, PaRAM Set or TCC, previously allocated. + * + * This API frees a contiguous region of specified EDMA3 Resources + * like DMA channel, QDMA channel, PaRAM Set or TCC, which have been previously + * allocated. In case of an error during the freeing of any specific resource, + * user can check the 'firstResIdObj' object to know the last resource id + * whose freeing has failed. In case of success, there is no need to check this + * object. + * + * \param hEdmaResMgr [IN] Handle to the previously opened + * Resource Manager Instance. + * \param firstResIdObj [IN/OUT] Handle to the first resource + * descriptor object, which needs to be + * freed. In case of an error while + * freeing any particular resource, + * the last resource id whose freeing has + * failed is returned in this resource + * descriptor object. + * \param numResources [IN] Number of contiguous resources allocated + * previously which user wants to release + * + * \note This is a re-entrant function which internally calls + * EDMA3_RM_freeResource() for resource de-allocation. + */ +EDMA3_RM_Result EDMA3_RM_freeContiguousResource(EDMA3_RM_Handle hEdmaResMgr, + EDMA3_RM_ResDesc *firstResIdObj, + unsigned int numResources) + { + EDMA3_RM_Instance *rmInstance = NULL; + EDMA3_RM_Obj *rmObj = NULL; + EDMA3_RM_Result result = EDMA3_RM_SOK; + EDMA3_RM_ResDesc *resObj; + unsigned int resFreeIdx = 0u; + unsigned int firstResId; + unsigned int lastResId; + unsigned int maxNumResources = 0u; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_RM_PARAM_CHECK_DISABLE + if ((hEdmaResMgr == NULL) || (firstResIdObj == NULL)) + { + result = EDMA3_RM_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_RM_SOK == result) + { + rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr; + rmObj = rmInstance->pResMgrObjHandle; + + if (rmObj == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + else + { + resObj = firstResIdObj; + if (resObj != NULL) + { + firstResId = resObj->resId; + lastResId = firstResId + (numResources - 1u); + } + + switch (resObj->type) + { + case EDMA3_RM_RES_DMA_CHANNEL : + maxNumResources = rmObj->gblCfgParams.numDmaChannels; + break; + case EDMA3_RM_RES_QDMA_CHANNEL : + maxNumResources = rmObj->gblCfgParams.numQdmaChannels; + break; + case EDMA3_RM_RES_TCC : + maxNumResources = rmObj->gblCfgParams.numTccs; + break; + case EDMA3_RM_RES_PARAM_SET : + maxNumResources = rmObj->gblCfgParams.numPaRAMSets; + break; + default: + result = EDMA3_RM_E_INVALID_PARAM; + break; + } + + if (result == EDMA3_RM_SOK) + { + if ((firstResId > lastResId) || (lastResId >= maxNumResources)) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + else + { + for (resFreeIdx = firstResId; resFreeIdx <= lastResId; ++resFreeIdx) + { + resObj->resId = resFreeIdx; + result = EDMA3_RM_freeResource(rmInstance, resObj); + + if (result != EDMA3_RM_SOK) + { + break; + } + } + } + } + } + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + + + +/**\fn EDMA3_RM_Result EDMA3_RM_setCCRegister (EDMA3_RM_Handle hEdmaResMgr, + * unsigned int regOffset, + * unsigned int newRegValue) + * \brief Set the Channel Controller (CC) Register value + * + * \param hEdmaResMgr [IN] Handle to the previously opened Resource + * Manager Instance. + * \param regOffset [IN] CC Register offset whose value needs to be + * set. It should be word-aligned. + * \param newRegValue [IN] New CC Register Value + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + * + * \note This function is non re-entrant for users using the same + * Resource Manager handle. + * Before modifying a register, it tries to acquire a semaphore + * (RM instance specific), to protect simultaneous + * modification of the same register by two different users. + * After the successful change, it releases the semaphore. + * For users using different RM handles, this function is re-entrant. + */ +EDMA3_RM_Result EDMA3_RM_setCCRegister (EDMA3_RM_Handle hEdmaResMgr, + unsigned int regOffset, + unsigned int newRegValue) + { + EDMA3_RM_Result result = EDMA3_RM_SOK; + EDMA3_RM_Instance *rmInstance = NULL; + EDMA3_RM_Obj *rmObj = NULL; + volatile unsigned int regPhyAddr = 0x0u; + + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + + /* If parameter checking is enabled... */ +#ifndef EDMA3_RM_PARAM_CHECK_DISABLE + if ((hEdmaResMgr == NULL) || ((regOffset % 4u) != 0)) + { + result = (EDMA3_RM_E_INVALID_PARAM); + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_RM_SOK == result) + { + rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr; + rmObj = rmInstance->pResMgrObjHandle; + + if (rmObj == NULL) + { + result = (EDMA3_RM_E_INVALID_PARAM); + } + else + { + if (rmObj->gblCfgParams.globalRegs != NULL) + { + /** + * Take the instance specific semaphore, to prevent simultaneous + * access to the shared resources. + */ + result = edma3OsSemTake(rmInstance->initParam.rmSemHandle, + EDMA3_OSSEM_NO_TIMEOUT); + + if (EDMA3_RM_SOK == result) + { + /* Semaphore taken successfully, modify the registers. */ + regPhyAddr = (unsigned int)(rmObj->gblCfgParams.globalRegs) + regOffset; + + *(unsigned int *)regPhyAddr = newRegValue; + + /* Return the semaphore back */ + result = edma3OsSemGive(rmInstance->initParam.rmSemHandle); + } + } + } + } + + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + + return result; + } + + + + +/**\fn EDMA3_RM_Result EDMA3_RM_getCCRegister (EDMA3_RM_Handle hEdmaResMgr, + * unsigned int regOffset, + * unsigned int *regValue) + * \brief Get the Channel Controller (CC) Register value + * + * \param hEdmaResMgr [IN] Handle to the previously opened Resource + * Manager Instance. + * \param regOffset [IN] CC Register offset whose value is + * needed. It should be word-aligned. + * \param regValue [IN/OUT] Fetched CC Register Value + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + * + * \note This function is re-entrant. + */ +EDMA3_RM_Result EDMA3_RM_getCCRegister (EDMA3_RM_Handle hEdmaResMgr, + unsigned int regOffset, + unsigned int *regValue) + { + EDMA3_RM_Result result = EDMA3_RM_SOK; + EDMA3_RM_Instance *rmInstance = NULL; + EDMA3_RM_Obj *rmObj = NULL; + volatile unsigned int regPhyAddr = 0x0u; + + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + + /* If parameter checking is enabled... */ +#ifndef EDMA3_RM_PARAM_CHECK_DISABLE + if (((hEdmaResMgr == NULL) || (regValue == NULL)) + || ((regOffset % 4u) != 0)) + { + result = (EDMA3_RM_E_INVALID_PARAM); + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_RM_SOK == result) + { + rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr; + rmObj = rmInstance->pResMgrObjHandle; + + if (rmObj == NULL) + { + result = (EDMA3_RM_E_INVALID_PARAM); + } + else + { + if (rmObj->gblCfgParams.globalRegs != NULL) + { + regPhyAddr = (unsigned int)(rmObj->gblCfgParams.globalRegs) + regOffset; + + *regValue = *(unsigned int *)regPhyAddr; + } + } + } + + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + + return result; + } + + + +/**\fn EDMA3_RM_Result EDMA3_RM_waitAndClearTcc (EDMA3_RM_Handle + * hEdmaResMgr, unsigned int tccNo) + * \brief Wait for a transfer completion interrupt to occur and clear it. + * + * This is a blocking function that returns when the IPR/IPRH bit corresponding + * to the tccNo specified, is SET. It clears the corresponding bit while + * returning also. + * + * This function waits for the specific bit indefinitely in a tight loop, with + * out any delay in between. USE IT CAUTIOUSLY. + * + * \param hEdmaResMgr [IN] Handle to the previously opened Resource + * Manager Instance. + * \param tccNo [IN] TCC, specific to which the function + * waits on a IPR/IPRH bit. + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + * + * \note This function is re-entrant for different tccNo. + * + */ +EDMA3_RM_Result EDMA3_RM_waitAndClearTcc (EDMA3_RM_Handle hEdmaResMgr, + unsigned int tccNo) + { + EDMA3_RM_Result result = EDMA3_RM_SOK; + EDMA3_RM_Instance *rmInstance = NULL; + EDMA3_RM_Obj *rmObj = NULL; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + volatile EDMA3_CCRL_ShadowRegs *shadowRegs = NULL; + unsigned int tccBitMask = 0x0u; + + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + + /* If parameter checking is enabled... */ +#ifndef EDMA3_RM_PARAM_CHECK_DISABLE + if (hEdmaResMgr == NULL) + { + result = (EDMA3_RM_E_INVALID_PARAM); + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_RM_SOK == result) + { + rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr; + rmObj = rmInstance->pResMgrObjHandle; + + if ((rmObj == NULL) || (rmObj->gblCfgParams.globalRegs == NULL)) + { + result = (EDMA3_RM_E_INVALID_PARAM); + } + else + { + /* If parameter checking is enabled... */ +#ifndef EDMA3_RM_PARAM_CHECK_DISABLE + if (tccNo >= rmObj->gblCfgParams.numTccs) + { + result = (EDMA3_RM_E_INVALID_PARAM); + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_RM_SOK == result) + { + globalRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs); + shadowRegs = (volatile EDMA3_CCRL_ShadowRegs *) + (&globalRegs->SHADOW[rmInstance->initParam.regionId]); + + + if (shadowRegs != NULL) + { + if(tccNo < 32u) + { + tccBitMask = (1u << tccNo); + + /* Check the status of the IPR[tccNo] bit. */ + while (FALSE == (shadowRegs->IPR & tccBitMask)) + { + /* Transfer not yet completed, bit not SET */ + } + + /** + * Bit found SET, transfer is completed, + * clear the pending interrupt and return. + */ + shadowRegs->ICR = tccBitMask; + } + else + { + tccBitMask = (1u << (tccNo - 32u)); + + /* Check the status of the IPRH[tccNo-32] bit. */ + while (FALSE == (shadowRegs->IPRH & tccBitMask)) + { + /* Transfer not yet completed, bit not SET */ + } + + /** + * Bit found SET, transfer is completed, + * clear the pending interrupt and return. + */ + shadowRegs->ICRH = tccBitMask; + } + } + } + } + } + + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + + return result; + } + + + + +/**\fn EDMA3_RM_Result EDMA3_RM_checkAndClearTcc (EDMA3_RM_Handle + * hEdmaResMgr, unsigned int tccNo, + * unsigned short *tccStatus) + * \brief Returns the status of a previously initiated transfer. + * + * This is a non-blocking function that returns the status of a previously + * initiated transfer, based on the IPR/IPRH bit. This bit corresponds to + * the tccNo specified by the user. It clears the corresponding bit, if SET, + * while returning also. + * + * \param hEdmaResMgr [IN] Handle to the previously opened Resource + * Manager Instance. + * \param tccNo [IN] TCC, specific to which the function + * checks the status of the IPR/IPRH bit. + * \param tccStatus [IN/OUT] Status of the transfer is returned here. + * Returns "TRUE" if the transfer has + * completed (IPR/IPRH bit SET), + * "FALSE" if the transfer has not + * completed successfully (IPR/IPRH bit + * NOT SET). + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + * + * \note This function is re-entrant for different tccNo. + */ +EDMA3_RM_Result EDMA3_RM_checkAndClearTcc (EDMA3_RM_Handle hEdmaResMgr, + unsigned int tccNo, + unsigned short *tccStatus) + { + EDMA3_RM_Result result = EDMA3_RM_SOK; + EDMA3_RM_Instance *rmInstance = NULL; + EDMA3_RM_Obj *rmObj = NULL; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + volatile EDMA3_CCRL_ShadowRegs *shadowRegs = NULL; + unsigned int tccBitMask = 0x0u; + + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + + /* If parameter checking is enabled... */ +#ifndef EDMA3_RM_PARAM_CHECK_DISABLE + if ((hEdmaResMgr == NULL) || (tccStatus == NULL)) + { + result = (EDMA3_RM_E_INVALID_PARAM); + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_RM_SOK == result) + { + rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr; + rmObj = rmInstance->pResMgrObjHandle; + + if ((rmObj == NULL) || (rmObj->gblCfgParams.globalRegs == NULL)) + { + result = (EDMA3_RM_E_INVALID_PARAM); + } + else + { + /* If parameter checking is enabled... */ +#ifndef EDMA3_RM_PARAM_CHECK_DISABLE + if (tccNo >= rmObj->gblCfgParams.numTccs) + { + result = (EDMA3_RM_E_INVALID_PARAM); + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_RM_SOK == result) + { + globalRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs); + shadowRegs = (volatile EDMA3_CCRL_ShadowRegs *) + (&globalRegs->SHADOW[rmInstance->initParam.regionId]); + + /* Reset the tccStatus */ + *tccStatus = FALSE; + + if (shadowRegs != NULL) + { + if(tccNo < 32u) + { + tccBitMask = (1u << tccNo); + + /* Check the status of the IPR[tccNo] bit. */ + if ((shadowRegs->IPR & tccBitMask) != FALSE) + { + /* Transfer completed, bit found SET */ + *tccStatus = TRUE; + + /* Clear the pending interrupt also. */ + shadowRegs->ICR = tccBitMask; + } + } + else + { + tccBitMask = (1u << (tccNo - 32u)); + + /* Check the status of the IPRH[tccNo-32] bit. */ + if ((shadowRegs->IPRH & tccBitMask) != FALSE) + { + /* Transfer completed, bit found SET */ + *tccStatus = TRUE; + + /* Clear the pending interrupt also. */ + shadowRegs->ICRH = tccBitMask; + } + } + } + } + } + } + + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + + return result; + } + + + +/**\fn EDMA3_RM_Result EDMA3_RM_setPaRAM (EDMA3_RM_Handle hEdmaResMgr, + * EDMA3_RM_ResDesc *lChObj, + * const EDMA3_RM_PaRAMRegs *newPaRAM) + * \brief Copy the user specified PaRAM Set onto the PaRAM Set + * associated with the logical channel (DMA/QDMA/Link). + * + * This API takes a PaRAM Set as input and copies it onto the actual PaRAM Set + * associated with the logical channel. OPT field of the PaRAM Set is written + * first and the CCNT field is written last. + * + * Caution: It should be used carefully when programming the QDMA channels whose + * trigger words are not CCNT field. + * + * \param hEdmaResMgr [IN] Handle to the previously opened Resource + * Manager Instance. + * \param lChObj [IN] Logical Channel object for which new + * PaRAM set is specified. User should pass + * the resource type and id in this object. + * \param newPaRAM [IN] PaRAM set to be copied onto existing one + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + * + * \note This function is re-entrant for unique lChObj values. It is non- + * re-entrant for same lChObj value. + */ +EDMA3_RM_Result EDMA3_RM_setPaRAM (EDMA3_RM_Handle hEdmaResMgr, + EDMA3_RM_ResDesc *lChObj, + const EDMA3_RM_PaRAMRegs *newPaRAM) + { + EDMA3_RM_Result result = EDMA3_RM_SOK; + EDMA3_RM_Instance *rmInstance = NULL; + EDMA3_RM_Obj *rmObj = NULL; + int paRAMId = 0u; + unsigned int qdmaChId = 0u; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_RM_PARAM_CHECK_DISABLE + if (hEdmaResMgr == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + + if ((lChObj == NULL) || (newPaRAM == NULL)) + { + result = EDMA3_RM_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (result == EDMA3_RM_SOK) + { + rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr; + + if (rmInstance == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + + if (result == EDMA3_RM_SOK) + { + rmObj = rmInstance->pResMgrObjHandle; + + if (rmObj == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + else + { + if (rmObj->gblCfgParams.globalRegs == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + } + + + if (result == EDMA3_RM_SOK) + { + globalRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs); + + switch (lChObj->type) + { + case EDMA3_RM_RES_DMA_CHANNEL: + { + if (lChObj->resId <= EDMA3_RM_DMA_CH_MAX_VAL) + { + paRAMId = edma3RmChBoundRes[rmObj->phyCtrllerInstId][lChObj->resId].paRAMId; + } + else + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + break; + + case EDMA3_RM_RES_QDMA_CHANNEL: + { + if (lChObj->resId < EDMA3_MAX_QDMA_CH) + { + qdmaChId = lChObj->resId + EDMA3_RM_QDMA_CH_MIN_VAL; + paRAMId = edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].paRAMId; + } + else + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + break; + + case EDMA3_RM_RES_PARAM_SET: + { + if (lChObj->resId < edma3NumPaRAMSets) + { + /** + * User has passed the actual param set value here. + * Use this value only + */ + paRAMId = (int)(lChObj->resId); + } + else + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + break; + + default: + result = EDMA3_RM_E_INVALID_PARAM; + } + } + + + if (result == EDMA3_RM_SOK) + { + /* Check the param id first. */ + if ((paRAMId != -1) && ((unsigned int)paRAMId < edma3NumPaRAMSets)) + { + /* Set the PaRAM Set now. */ + edma3MemCpy ((void *)(&(globalRegs->PARAMENTRY[paRAMId].OPT)), + (const void *)newPaRAM, + sizeof(EDMA3_CCRL_ParamentryRegs)); + } + else + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + + +/**\fn EDMA3_RM_Result EDMA3_RM_getPaRAM (EDMA3_RM_Handle hEdmaResMgr, + * EDMA3_RM_ResDesc *lChObj, + * EDMA3_RM_PaRAMRegs *currPaRAM) + * \brief Retrieve existing PaRAM set associated with specified logical + * channel (DMA/QDMA/Link). + * + * \param hEdmaResMgr [IN] Handle to the previously opened Resource + * Manager Instance. + * \param lChObj [IN] Logical Channel object for which the + * PaRAM set is requested. User should pass + * the resource type and id in this object. + * \param currPaRAM [IN/OUT] User gets the existing PaRAM here. + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + * + * \note This function is re-entrant. + */ +EDMA3_RM_Result EDMA3_RM_getPaRAM (EDMA3_RM_Handle hEdmaResMgr, + EDMA3_RM_ResDesc *lChObj, + EDMA3_RM_PaRAMRegs *currPaRAM) + { + EDMA3_RM_Result result = EDMA3_RM_SOK; + EDMA3_RM_Instance *rmInstance = NULL; + EDMA3_RM_Obj *rmObj = NULL; + int paRAMId = 0u; + unsigned int qdmaChId = 0u; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_RM_PARAM_CHECK_DISABLE + if (hEdmaResMgr == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + + if ((lChObj == NULL) || (currPaRAM == NULL)) + { + result = EDMA3_RM_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (result == EDMA3_RM_SOK) + { + rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr; + + if (rmInstance == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + + if (result == EDMA3_RM_SOK) + { + rmObj = rmInstance->pResMgrObjHandle; + + if (rmObj == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + else + { + if (rmObj->gblCfgParams.globalRegs == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + } + + if (result == EDMA3_RM_SOK) + { + globalRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs); + + switch (lChObj->type) + { + case EDMA3_RM_RES_DMA_CHANNEL: + { + if (lChObj->resId <= EDMA3_RM_DMA_CH_MAX_VAL) + { + paRAMId = edma3RmChBoundRes[rmObj->phyCtrllerInstId][lChObj->resId].paRAMId; + } + else + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + break; + + case EDMA3_RM_RES_QDMA_CHANNEL: + { + if (lChObj->resId < EDMA3_MAX_QDMA_CH) + { + qdmaChId = lChObj->resId + EDMA3_RM_QDMA_CH_MIN_VAL; + paRAMId = edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].paRAMId; + } + else + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + break; + + case EDMA3_RM_RES_PARAM_SET: + { + if (lChObj->resId < edma3NumPaRAMSets) + { + /** + * User has passed the actual param set value here. + * Use this value only + */ + paRAMId = (int)(lChObj->resId); + } + else + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + break; + + default: + result = EDMA3_RM_E_INVALID_PARAM; + } + } + + + if (result == EDMA3_RM_SOK) + { + /* Check the param id first. */ + if ((paRAMId != -1) && (paRAMId < edma3NumPaRAMSets)) + { + /* Get the PaRAM Set now. */ + edma3MemCpy ((void *)currPaRAM , + (const void *)(&(globalRegs->PARAMENTRY [paRAMId].OPT)), + sizeof(EDMA3_CCRL_ParamentryRegs)); + } + else + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + + return result; + } + + +/**\fn EDMA3_RM_Result EDMA3_RM_getPaRAMPhyAddr(EDMA3_RM_Handle + * hEdmaResMgr, EDMA3_RM_ResDesc *lChObj, + * unsigned int *paramPhyAddr) + * \brief Get the PaRAM Set Physical Address associated with a logical channel + * + * This function returns the PaRAM Set Phy Address (unsigned 32 bits). + * The returned address could be used by the advanced users to program the + * PaRAM Set directly without using any APIs. + * + * Least significant 16 bits of this address could be used to program + * the LINK field in the PaRAM Set. + * Users which program the LINK field directly SHOULD use this API + * to get the associated PaRAM Set address with the LINK channel. + * + * \param hEdmaResMgr [IN] Handle to the previously opened Resource + * Manager Instance. + * \param lChObj [IN] Logical Channel object for which the + * PaRAM set physical address is required. + * User should pass the resource type and + * id in this object. + * \param paramPhyAddr [IN/OUT] PaRAM Set physical address is returned + * here. + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + * + * \note This function is re-entrant. + */ +EDMA3_RM_Result EDMA3_RM_getPaRAMPhyAddr(EDMA3_RM_Handle hEdmaResMgr, + EDMA3_RM_ResDesc *lChObj, + unsigned int *paramPhyAddr) + { + EDMA3_RM_Result result = EDMA3_RM_SOK; + EDMA3_RM_Instance *rmInstance = NULL; + EDMA3_RM_Obj *rmObj = NULL; + int paRAMId = 0u; + unsigned int qdmaChId = 0u; + volatile EDMA3_CCRL_Regs *globalRegs = NULL; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + + /* If parameter checking is enabled... */ +#ifndef EDMA3_RM_PARAM_CHECK_DISABLE + if (hEdmaResMgr == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + + if ((lChObj == NULL) || (paramPhyAddr == NULL)) + { + result = EDMA3_RM_E_INVALID_PARAM; + } +#endif + + if (result == EDMA3_RM_SOK) + { + rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr; + + if (rmInstance == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + + if (result == EDMA3_RM_SOK) + { + rmObj = rmInstance->pResMgrObjHandle; + + if (rmObj == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + else + { + if (rmObj->gblCfgParams.globalRegs == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + } + + if (result == EDMA3_RM_SOK) + { + globalRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs); + + switch (lChObj->type) + { + case EDMA3_RM_RES_DMA_CHANNEL: + { + if (lChObj->resId <= EDMA3_RM_DMA_CH_MAX_VAL) + { + paRAMId = edma3RmChBoundRes[rmObj->phyCtrllerInstId][lChObj->resId].paRAMId; + } + else + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + break; + + case EDMA3_RM_RES_QDMA_CHANNEL: + { + if (lChObj->resId < EDMA3_MAX_QDMA_CH) + { + qdmaChId = lChObj->resId + EDMA3_RM_QDMA_CH_MIN_VAL; + paRAMId = edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].paRAMId; + } + else + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + break; + + case EDMA3_RM_RES_PARAM_SET: + { + if (lChObj->resId < edma3NumPaRAMSets) + { + /** + * User has passed the actual param set value here. + * Use this value only + */ + paRAMId = (int)(lChObj->resId); + } + else + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + break; + + default: + result = EDMA3_RM_E_INVALID_PARAM; + } + } + + + + if (result == EDMA3_RM_SOK) + { + /* Check the param id first. */ + if ((paRAMId != -1) && (paRAMId < edma3NumPaRAMSets)) + { + /* Get the PaRAM Set Address now. */ + *paramPhyAddr = (unsigned int)(&(globalRegs->PARAMENTRY [paRAMId].OPT)); + } + else + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + +/**\fn EDMA3_RM_Result EDMA3_RM_getBaseAddress (EDMA3_RM_Handle + * hEdmaResMgr, EDMA3_RM_Cntrlr_PhyAddr controllerId, + * unsigned int *phyAddress) + * \brief Get the Channel Controller or Transfer Controller (n) Physical + * Address. + * + * \param hEdmaResMgr [IN] Handle to the previously opened Resource + * Manager Instance. + * \param controllerId [IN] Channel Controller or Transfer + * Controller (n) for which the physical + * address is required. + * \param phyAddress [IN/OUT] Physical address is returned here. + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + * + * \note This function is re-entrant. + */ +EDMA3_RM_Result EDMA3_RM_getBaseAddress (EDMA3_RM_Handle hEdmaResMgr, + EDMA3_RM_Cntrlr_PhyAddr controllerId, + unsigned int *phyAddress) + { + EDMA3_RM_Result result = EDMA3_RM_SOK; + EDMA3_RM_Instance *rmInstance = NULL; + EDMA3_RM_Obj *rmObj = NULL; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + + /* If parameter checking is enabled... */ +#ifndef EDMA3_RM_PARAM_CHECK_DISABLE + if ((hEdmaResMgr == NULL) || (phyAddress == NULL)) + { + result = EDMA3_RM_E_INVALID_PARAM; + } +#endif + + if (result == EDMA3_RM_SOK) + { + rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr; + + if (rmInstance == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + + if (result == EDMA3_RM_SOK) + { + rmObj = rmInstance->pResMgrObjHandle; + + if (rmObj == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + + if (result == EDMA3_RM_SOK) + { + /* If parameter checking is enabled... */ +#ifndef EDMA3_RM_PARAM_CHECK_DISABLE + /* Verify the 'controllerId' */ + if ((controllerId < ((EDMA3_RM_Cntrlr_PhyAddr)(EDMA3_RM_CC_PHY_ADDR))) + || (controllerId > (EDMA3_RM_Cntrlr_PhyAddr)(rmObj->gblCfgParams.numTcs))) + { + /* Invalid controllerId */ + result = EDMA3_RM_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_RM_SOK == result) + { + if (controllerId == EDMA3_RM_CC_PHY_ADDR) + { + /* EDMA3 Channel Controller Address */ + *phyAddress = (unsigned int)(rmObj->gblCfgParams.globalRegs); + } + else + { + /** + * Since the TCs enum start from 1, and TCs start from 0, + * subtract 1 from the enum to get the actual address. + */ + *phyAddress = (unsigned int)(rmObj->gblCfgParams.tcRegs[controllerId-1u]); + } + } + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + + + +/**\fn EDMA3_RM_Result EDMA3_RM_getGblConfigParams (unsigned int phyCtrllerInstId, + * EDMA3_RM_GblConfigParams *gblCfgParams) + * \brief Get the SoC specific configuration structure for the EDMA3 Hardware. + * + * This API is used to fetch the global SoC specific configuration structure + * for the EDMA3 Hardware. It is useful for the user who has not passed + * this information during EDMA3_RM_create() and taken the default configuration + * coming along with the package. + * + * \param phyCtrllerInstId [IN] EDMA3 Controller Instance Id + * (Hardware instance id, starting from 0). + * \param gblCfgParams [IN/OUT] SoC specific configuration structure for the + * EDMA3 Hardware will be returned here. + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + * + * \note This function is re-entrant. + */ +EDMA3_RM_Result EDMA3_RM_getGblConfigParams ( + unsigned int phyCtrllerInstId, + EDMA3_RM_GblConfigParams *gblCfgParams) + { + EDMA3_RM_Result result = EDMA3_RM_SOK; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_RM_PARAM_CHECK_DISABLE + if ((phyCtrllerInstId >= EDMA3_MAX_EDMA3_INSTANCES) + || (NULL == gblCfgParams)) + { + result = EDMA3_RM_E_INVALID_PARAM; + } +#endif + + if (EDMA3_RM_SOK == result) + { + /* Return the previously saved global config information for the EDMA3 HW */ + edma3MemCpy((void *)(gblCfgParams), + (const void *)(&resMgrObj[phyCtrllerInstId].gblCfgParams), + sizeof (EDMA3_RM_GblConfigParams)); + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + + +/**\fn EDMA3_RM_Result EDMA3_RM_getInstanceInitCfg (EDMA3_RM_Handle hEdmaResMgr, + * EDMA3_RM_InstanceInitConfig *instanceInitConfig) + * \brief Get the RM Instance specific configuration structure for different + * EDMA3 resources' usage (owned resources, reserved resources etc). + * + * This API is used to fetch the Resource Manager Instance specific configuration + * structure, for a specific shadow region. It is useful for the user who has not passed + * this information during EDMA3_RM_opn() and taken the default configuration + * coming along with the package. EDMA3 resources, owned and reserved by this RM + * instance, will be returned from this API. + * + * \param hEdmaResMgr [IN] Handle to the previously opened Resource + * Manager Instance. + * \param instanceInitConfig [IN/OUT] RM Instance specific configuration + * structure will be returned here. + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + * + * \note This function is re-entrant. + */ +EDMA3_RM_Result EDMA3_RM_getInstanceInitCfg ( + EDMA3_RM_Handle hEdmaResMgr, + EDMA3_RM_InstanceInitConfig *instanceInitConfig) + { + EDMA3_RM_Result result = EDMA3_RM_SOK; + EDMA3_RM_Instance *rmInstance = NULL; + EDMA3_RM_Obj *rmObj = NULL; + unsigned int resMgrIdx = 0u; + unsigned int hwId; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_RM_PARAM_CHECK_DISABLE + if ((hEdmaResMgr == NULL) || (instanceInitConfig == NULL)) + { + result = EDMA3_RM_E_INVALID_PARAM; + } +#endif + + if (result == EDMA3_RM_SOK) + { + rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr; + + if (rmInstance == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + + if (result == EDMA3_RM_SOK) + { + rmObj = rmInstance->pResMgrObjHandle; + + if (rmObj == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + + if (result == EDMA3_RM_SOK) + { + hwId = rmObj->phyCtrllerInstId; + + for (resMgrIdx = 0u; resMgrIdx < EDMA3_MAX_RM_INSTANCES; resMgrIdx++) + { + if (rmInstance == ((EDMA3_RM_Instance *)(ptrRMIArray) + + (hwId*EDMA3_MAX_RM_INSTANCES) + + resMgrIdx)) + { + /* RM Id found. Return the specific config info to the user. */ + edma3MemCpy((void *)(instanceInitConfig), + (const void *)((EDMA3_RM_InstanceInitConfig *)(ptrInitCfgArray) + + (hwId*EDMA3_MAX_RM_INSTANCES) + + resMgrIdx), + sizeof (EDMA3_RM_InstanceInitConfig)); + break; + } + } + + if (EDMA3_MAX_RM_INSTANCES == resMgrIdx) + { + /* RM Id not found, report error... */ + result = EDMA3_RM_E_INVALID_PARAM; + } + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + } + + + +/** + * \brief EDMA3 Resource Manager IOCTL + * + * This function provides IOCTL functionality for EDMA3 Resource Manager + * + * \param hEdmaResMgr [IN] Handle to the previously opened Resource + * Manager Instance. + * \param cmd [IN] IOCTL command to be performed + * \param cmdArg [IN/OUT] IOCTL command argument (if any) + * \param param [IN/OUT] Device/Cmd specific argument + * + * \return EDMA3_RM_SOK or EDMA3_RM Error Code + */ +EDMA3_RM_Result EDMA3_RM_Ioctl( + EDMA3_RM_Handle hEdmaResMgr, + EDMA3_RM_IoctlCmd cmd, + void *cmdArg, + void *param + ) + { + EDMA3_RM_Result result = EDMA3_RM_SOK; + EDMA3_RM_Instance *rmInstance = NULL; + unsigned int paramInitRequired = 0xFFu; + unsigned int regModificationRequired = 0xFFu; + unsigned int *ret_val = NULL; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + /* If parameter checking is enabled... */ +#ifndef EDMA3_RM_PARAM_CHECK_DISABLE + if (hEdmaResMgr == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + + if ((cmd <= EDMA3_RM_IOCTL_MIN_IOCTL) + || (cmd >= EDMA3_RM_IOCTL_MAX_IOCTL)) + { + result = EDMA3_RM_E_INVALID_PARAM; + } +#endif + + if (result == EDMA3_RM_SOK) + { + rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr; + + if (rmInstance == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + + /* To remove CCS warnings */ + (void)param; + + if (result == EDMA3_RM_SOK) + { + switch (cmd) + { + case EDMA3_RM_IOCTL_SET_PARAM_CLEAR_OPTION: + { + paramInitRequired = (unsigned int)cmdArg; + + /* If parameter checking is enabled... */ +#ifndef EDMA3_RM_PARAM_CHECK_DISABLE + if ((paramInitRequired != 0u) + && (paramInitRequired != 1u)) + { + result = EDMA3_RM_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_RM_SOK == result) + { + /* Set/Reset the flag which is being used to do the PaRAM clearing. */ + rmInstance->paramInitRequired = paramInitRequired; + } + + break; + } + + case EDMA3_RM_IOCTL_GET_PARAM_CLEAR_OPTION: + { + /* If parameter checking is enabled... */ +#ifndef EDMA3_RM_PARAM_CHECK_DISABLE + if (NULL == cmdArg) + { + result = EDMA3_RM_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_RM_SOK == result) + { + ret_val = (unsigned int *)cmdArg; + + /* Get the flag which is being used to do the PaRAM clearing. */ + *ret_val = rmInstance->paramInitRequired; + } + + break; + } + + case EDMA3_RM_IOCTL_SET_GBL_REG_MODIFY_OPTION: + { + regModificationRequired = (unsigned int)cmdArg; + + /* If parameter checking is enabled... */ +#ifndef EDMA3_RM_PARAM_CHECK_DISABLE + if ((regModificationRequired == 0u) + || (regModificationRequired == 1u)) + { + /* All other values are invalid. */ + result = EDMA3_RM_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_RM_SOK == result) + { + /** + * Set/Reset the flag which is being used to do the global + * registers and PaRAM modification. + */ + rmInstance->regModificationRequired = regModificationRequired; + } + + break; + } + + case EDMA3_RM_IOCTL_GET_GBL_REG_MODIFY_OPTION: + { + /* If parameter checking is enabled... */ +#ifndef EDMA3_RM_PARAM_CHECK_DISABLE + if (NULL == cmdArg) + { + result = EDMA3_RM_E_INVALID_PARAM; + } +#endif + + /* Check if the parameters are OK. */ + if (EDMA3_RM_SOK == result) + { + ret_val = (unsigned int *)cmdArg; + + /** + * Get the flag which is being used to do the global + * registers and PaRAM modification. + */ + *ret_val = rmInstance->regModificationRequired; + } + + break; + } + + default: + /* Hey dude! you passed invalid IOCTL cmd */ + result = EDMA3_RM_E_INVALID_PARAM; + + } + } + + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END, + EDMA3_DVT_dCOUNTER, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + return result; + + } + + + +/** + * edma3ComplHandler + * \brief Interrupt handler for successful transfer completion. + * + * \note This function first disables its own interrupt to make it non- + * entrant. Later, after calling all the callback functions, it + * re-enables its own interrupt. + * + * \return None. + */ +static void edma3ComplHandler (const EDMA3_RM_Obj *rmObj) + { + unsigned int Cnt; + volatile EDMA3_CCRL_Regs *ptrEdmaccRegs = NULL; + volatile EDMA3_CCRL_ShadowRegs *shadowRegs = NULL; + volatile unsigned int pendingIrqs; + unsigned int indexl; + unsigned int indexh; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eINT_START, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + assert (NULL != rmObj); + + ptrEdmaccRegs = + (volatile EDMA3_CCRL_Regs *)rmObj->gblCfgParams.globalRegs; + if (ptrEdmaccRegs != NULL) + { + shadowRegs = (volatile EDMA3_CCRL_ShadowRegs *) + (&ptrEdmaccRegs->SHADOW[edma3RegionId]); + } + + Cnt = 0u; + pendingIrqs = 0u; + indexl = 1u; + indexh = 1u; + + if((shadowRegs->IPR !=0 ) || (shadowRegs->IPRH !=0 )) + { + /** + * Since an interrupt has found, we have to make sure that this + * interrupt (TCC) belongs to the TCCs allocated by us only. + * It might happen that someone else, who is using EDMA3 also, + * is the owner of this interrupt channel i.e. the TCC. + * For this, use the allocatedTCCs[], to check which all interrupt + * channels are owned by the EDMA3 RM Instances. + */ + + edma3OsProtectEntry (EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION, NULL); + + /* Loop for EDMA3_RM_COMPL_HANDLER_RETRY_COUNT number of time, + breaks when no pending interrupt is found */ + while ((Cnt < EDMA3_RM_COMPL_HANDLER_RETRY_COUNT) + && ((indexl != 0u) || (indexh != 0u))) + { + indexl = 0u; + pendingIrqs = shadowRegs->IPR; + + /** + * Choose interrupts coming from our allocated TCCs + * and MASK remaining ones. + */ + pendingIrqs = (pendingIrqs & allocatedTCCs[0u]); + + while (pendingIrqs) + { + /*Process all the pending interrupts*/ + if((pendingIrqs & 1u) == TRUE) + { + /** + * If the user has not given any callback function + * while requesting the TCC, its TCC specific bit + * in the IPR register will NOT be cleared. + */ + if(edma3IntrParams[indexl].tccCb != NULL) + { + /* here write to ICR to clear the corresponding IPR bits*/ + shadowRegs->ICR = (1u << indexl); + + edma3IntrParams[indexl].tccCb (indexl, + EDMA3_RM_XFER_COMPLETE, + edma3IntrParams[indexl].cbData); + } + } + ++indexl; + pendingIrqs >>= 1u; + } + + indexh = 0u; + pendingIrqs = shadowRegs->IPRH; + + /** + * Choose interrupts coming from our allocated TCCs + * and MASK remaining ones. + */ + pendingIrqs = (pendingIrqs & allocatedTCCs[1u]); + + while (pendingIrqs) + { + /*Process all the pending interrupts*/ + if((pendingIrqs & 1u)==TRUE) + { + /** + * If the user has not given any callback function + * while requesting the TCC, its TCC specific bit + * in the IPRH register will NOT be cleared. + */ + if(edma3IntrParams[32u+indexh].tccCb!=NULL) + { + /* here write to ICR to clear the corresponding IPR bits*/ + shadowRegs->ICRH = (1u << indexh); + + edma3IntrParams[32u+indexh].tccCb(32u+indexh, + EDMA3_RM_XFER_COMPLETE, + edma3IntrParams[32u+indexh].cbData); + } + } + ++indexh; + pendingIrqs >>= 1u; + } + + Cnt++; + } + + indexl = (shadowRegs->IPR & allocatedTCCs[0u]); + indexh = (shadowRegs->IPRH & allocatedTCCs[1u]); + + if((indexl !=0 ) || (indexh !=0 )) + { + shadowRegs->IEVAL=0x1u; + } + + edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION, NULL); + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3", + EDMA3_DVT_DESC(EDMA3_DVT_eINT_END, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + } + +/* ARGSUSED */ +void lisrEdma3ComplHandler0(unsigned int arg) + { + /* Invoke Completion Handler ISR */ + edma3ComplHandler(&resMgrObj[0]); + } + + +/** + * \brief Interrupt handler for Channel Controller Error. + * + * \note This function first disables its own interrupt to make it non- + * entrant. Later, after calling all the callback functions, it + * re-enables its own interrupt. + * + * \return None. + */ +static void edma3CCErrHandler(const EDMA3_RM_Obj *rmObj) + { + unsigned int Cnt = 0u; + unsigned int resMgrInstIdx = 0u; + volatile EDMA3_CCRL_Regs *ptrEdmaccRegs = NULL; + volatile EDMA3_CCRL_ShadowRegs *shadowRegs = NULL; + volatile unsigned int pendingIrqs; + unsigned int index; + unsigned int evtqueNum; + EDMA3_RM_Instance *rm_instance = NULL; + unsigned int hwId; + unsigned int num_rm_instances_opened; + EDMA3_RM_Instance *rmInstance = NULL; + unsigned int ownedDmaError = 0; + unsigned int ownedDmaHError = 0; + unsigned int ownedQdmaError = 0; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3_CCERR", + EDMA3_DVT_DESC(EDMA3_DVT_eINT_START, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + assert (rmObj != NULL); + + ptrEdmaccRegs = (volatile EDMA3_CCRL_Regs *)rmObj->gblCfgParams.globalRegs; + if (ptrEdmaccRegs != NULL) + { + shadowRegs = (volatile EDMA3_CCRL_ShadowRegs *)&ptrEdmaccRegs->SHADOW[edma3RegionId]; + hwId = rmObj->phyCtrllerInstId; + rmInstance = ((EDMA3_RM_Instance *)(ptrRMIArray) + + ((rmObj->phyCtrllerInstId)*EDMA3_MAX_RM_INSTANCES) + + edma3RegionId); + + pendingIrqs = 0u; + index = 1u; + + if(((ptrEdmaccRegs->EMR != 0 ) + || (ptrEdmaccRegs->EMRH != 0 )) + || ((ptrEdmaccRegs->QEMR != 0) + || (ptrEdmaccRegs->CCERR != 0))) + { + edma3OsProtectEntry (EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR, NULL); + + /* Loop for EDMA3_RM_CCERR_HANDLER_RETRY_COUNT number of time, + breaks when no pending interrupt is found */ + while ((Cnt < EDMA3_RM_CCERR_HANDLER_RETRY_COUNT) + && (index != 0u)) + { + index = 0u; + pendingIrqs = ptrEdmaccRegs->EMR; + + while (pendingIrqs) + { + /*Process all the pending interrupts*/ + if((pendingIrqs & 1u)==TRUE) + { + unsigned int mappedTcc = 0u; + + /** + * Using the 'index' value (basically the DMA + * channel), fetch the corresponding TCC + * value, mapped to this DMA channel. + */ + mappedTcc = edma3DmaChTccMapping[index]; + + /** + * Ensure that the mapped tcc is valid and the call + * back is not NULL + */ + if (mappedTcc < EDMA3_MAX_TCC) + { + /** + * TCC owned and allocated by RM. + * Write to EMCR to clear the corresponding EMR bits. + */ + ptrEdmaccRegs->EMCR = (1u<SECR = (1u<EMCR = (1u<SECR = (1u<>= 1u; + } + + index = 0u; + pendingIrqs = ptrEdmaccRegs->EMRH; + while (pendingIrqs) + { + /*Process all the pending interrupts*/ + if((pendingIrqs & 1u)==TRUE) + { + unsigned int mappedTcc = 0u; + + /** + * Using the 'index' value (basically the DMA + * channel), fetch the corresponding TCC + * value, mapped to this DMA channel. + */ + mappedTcc = edma3DmaChTccMapping[32u+index]; + + /** + * Ensure that the mapped tcc is valid and the call + * back is not NULL + */ + if (mappedTcc < EDMA3_MAX_TCC) + { + /** + * TCC owned and allocated by RM. + * Write to EMCR to clear the corresponding EMR bits. + */ + ptrEdmaccRegs->EMCRH = (1u<SECRH = (1u<EMCRH = (1u<SECRH = (1u<>= 1u; + } + + index = 0u; + pendingIrqs = ptrEdmaccRegs->QEMR; + while (pendingIrqs) + { + /*Process all the pending interrupts*/ + if((pendingIrqs & 1u)==TRUE) + { + unsigned int mappedTcc = 0u; + + /** + * Using the 'index' value (basically the QDMA + * channel), fetch the corresponding TCC + * value, mapped to this QDMA channel. + */ + mappedTcc = edma3QdmaChTccMapping[index]; + + if (mappedTcc < EDMA3_MAX_TCC) + { + /* here write to QEMCR to clear the corresponding QEMR bits*/ + ptrEdmaccRegs->QEMCR = (1u<QSECR = (1u<QEMCR = (1u<QSECR = (1u<>= 1u; + } + + index = 0u; + pendingIrqs = ptrEdmaccRegs->CCERR; + if (pendingIrqs!=NULL) + { + /* Process all the pending CC error interrupts. */ + + /* Queue threshold error for different event queues.*/ + for (evtqueNum = 0u; evtqueNum < rmObj->gblCfgParams.numEvtQueue; evtqueNum++) + { + if((pendingIrqs & (1u << evtqueNum)) != NULL) + { + /** + * Queue threshold error for queue 'evtqueNum' raised. + * Inform all the RM instances working on this region + * about the error by calling their global callback functions. + */ + num_rm_instances_opened = resMgrObj[hwId].numOpens; + for (resMgrInstIdx = 0u; num_rm_instances_opened; ++resMgrInstIdx) + { + /* Check whether the RM instance opened working on this region */ + rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (hwId*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx); + if (NULL != rm_instance) + { + if (rm_instance->initParam.regionId == edma3RegionId) + { + /* Region id matches, call the callback function */ + if (rm_instance->initParam.gblerrCbParams.gblerrCb != NULL) + { + rm_instance->initParam.gblerrCbParams.gblerrCb( + EDMA3_RM_E_CC_QUE_THRES_EXCEED, + evtqueNum, + rm_instance->initParam.gblerrCbParams.gblerrData); + } + } + } + + /* Check next opened instance */ + num_rm_instances_opened--; + } + + /* Clear the error interrupt. */ + ptrEdmaccRegs->CCERRCLR = (1u << evtqueNum); + } + } + + + /* Transfer completion code error. */ + if ((pendingIrqs & (1 << EDMA3_CCRL_CCERR_TCCERR_SHIFT))!=NULL) + { + /** + * Transfer completion code error raised. + * Inform all the RM instances working on this region + * about the error by calling their global callback functions. + */ + num_rm_instances_opened = resMgrObj[hwId].numOpens; + for (resMgrInstIdx = 0u; num_rm_instances_opened; ++resMgrInstIdx) + { + /* Check whether the RM instance opened working on this region */ + rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (hwId*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx); + if (NULL != rm_instance) + { + if (rm_instance->initParam.regionId == edma3RegionId) + { + /* Region id matches, call the callback function */ + if (rm_instance->initParam.gblerrCbParams.gblerrCb != NULL) + { + rm_instance->initParam.gblerrCbParams.gblerrCb( + EDMA3_RM_E_CC_TCC, + NULL, + rm_instance->initParam.gblerrCbParams.gblerrData); + } + } + } + + /* Check next opened instance */ + num_rm_instances_opened--; + } + + ptrEdmaccRegs->CCERRCLR = (1<EMR; + ownedDmaHError = ptrEdmaccRegs->EMRH; + ownedQdmaError = ptrEdmaccRegs->QEMR; +#else + /* Check ONLY owned error bits. */ + ownedDmaError = (ptrEdmaccRegs->EMR & rmInstance->initParam.rmInstInitConfig->ownDmaChannels[0u]); + ownedDmaHError = (ptrEdmaccRegs->EMRH & rmInstance->initParam.rmInstInitConfig->ownDmaChannels[1u]); + ownedQdmaError = (ptrEdmaccRegs->QEMR & rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[0u]); +#endif + + if (((ownedDmaError != 0 ) || (ownedDmaHError != 0 )) + || ((ownedQdmaError != 0) || (ptrEdmaccRegs->CCERR != 0))) + { + ptrEdmaccRegs->EEVAL=0x1u; + } + + edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR, NULL); + } + } + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3_CCERR", + EDMA3_DVT_DESC(EDMA3_DVT_eINT_END, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + } + +/* ARGSUSED */ +void lisrEdma3CCErrHandler0(unsigned int arg) + { + /* Invoke CC Error Handler ISR */ + edma3CCErrHandler(&resMgrObj[0]); + } + + + +/** + * \brief Interrupt handler for Transfer Controller Error. + * + * \note This function first disables its own interrupt to make it non- + * entrant. Later, after calling all the callback functions, it + * re-enables its own interrupt. + * + * \return None. + */ +static void edma3TCErrHandler (const EDMA3_RM_Obj *rmObj, unsigned int tcNum) + { + volatile EDMA3_TCRL_Regs *tcRegs = NULL; + unsigned int tcMemErrRdWr = 0u; + unsigned int resMgrInstIdx = 0u; + EDMA3_RM_Instance *rm_instance = NULL; + unsigned int hwId; + unsigned int num_rm_instances_opened; + +#ifdef EDMA3_INSTRUMENTATION_ENABLED + EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3_TCERR", + EDMA3_DVT_DESC(EDMA3_DVT_eINT_START, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE, + EDMA3_DVT_dNONE)); +#endif /* EDMA3_INSTRUMENTATION_ENABLED */ + + assert ((rmObj != NULL) && (tcNum < rmObj->gblCfgParams.numTcs)); + + if (rmObj->gblCfgParams.tcRegs[tcNum] != NULL) + { + tcRegs = (volatile EDMA3_TCRL_Regs *)(rmObj->gblCfgParams.tcRegs[tcNum]); + hwId = rmObj->phyCtrllerInstId; + } + + if (tcRegs != NULL) + { + if(tcRegs->ERRSTAT != 0) + { + edma3OsProtectEntry (EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR, &tcNum); + + if((tcRegs->ERRSTAT & (1 << EDMA3_TCRL_ERRSTAT_BUSERR_SHIFT))!=NULL) + { + /* Bus error event. */ + /** + * EDMA3TC has detected an error at source or destination + * address. Error information can be read from the error + * details register (ERRDET). + */ + tcMemErrRdWr = tcRegs->ERRDET & (EDMA3_TCRL_ERRDET_STAT_MASK); + if ((tcMemErrRdWr > 0u) && (tcMemErrRdWr < 8u)) + { + /** + * Inform all the RM instances working on this region + * about the error by calling their global callback functions. + */ + num_rm_instances_opened = resMgrObj[hwId].numOpens; + for (resMgrInstIdx = 0u; num_rm_instances_opened; ++resMgrInstIdx) + { + /* Check whether the RM instance opened working on this region */ + rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (hwId*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx); + if (NULL != rm_instance) + { + if (rm_instance->initParam.regionId == edma3RegionId) + { + /* Region id matches, call the callback function */ + if (rm_instance->initParam.gblerrCbParams.gblerrCb != NULL) + { + rm_instance->initParam.gblerrCbParams.gblerrCb( + EDMA3_RM_E_TC_MEM_LOCATION_READ_ERROR, + tcNum, + rm_instance->initParam.gblerrCbParams.gblerrData); + } + } + } + + /* Check next opened instance */ + num_rm_instances_opened--; + } + } + else + { + if ((tcMemErrRdWr >= 8u) && (tcMemErrRdWr <= 0xFu)) + { + /** + * Inform all the RM instances working on this region + * about the error by calling their global callback functions. + */ + num_rm_instances_opened = resMgrObj[hwId].numOpens; + for (resMgrInstIdx = 0u; num_rm_instances_opened; ++resMgrInstIdx) + { + /* Check whether the RM instance opened working on this region */ + rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (hwId*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx); + if (NULL != rm_instance) + { + if (rm_instance->initParam.regionId == edma3RegionId) + { + /* Region id matches, call the callback function */ + if (rm_instance->initParam.gblerrCbParams.gblerrCb != NULL) + { + rm_instance->initParam.gblerrCbParams.gblerrCb( + EDMA3_RM_E_TC_MEM_LOCATION_WRITE_ERROR, + tcNum, + rm_instance->initParam.gblerrCbParams.gblerrData); + } + } + } + + /* Check next opened instance */ + num_rm_instances_opened--; + } + } + } + tcRegs->ERRCLR = (1<ERRSTAT & (1 << EDMA3_TCRL_ERRSTAT_TRERR_SHIFT))!=NULL) + { + num_rm_instances_opened = resMgrObj[hwId].numOpens; + for (resMgrInstIdx = 0u; num_rm_instances_opened; ++resMgrInstIdx) + { + /* Check whether the RM instance opened working on this region */ + rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (hwId*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx); + if (NULL != rm_instance) + { + if (rm_instance->initParam.regionId == edma3RegionId) + { + /* Region id matches, call the callback function */ + if (rm_instance->initParam.gblerrCbParams.gblerrCb != NULL) + { + rm_instance->initParam.gblerrCbParams.gblerrCb( + EDMA3_RM_E_TC_TR_ERROR, + tcNum, + rm_instance->initParam.gblerrCbParams.gblerrData); + } + } + } + + /* Check next opened instance */ + num_rm_instances_opened--; + } + + tcRegs->ERRCLR = (1<ERRSTAT & (1 << EDMA3_TCRL_ERRSTAT_MMRAERR_SHIFT))!=NULL) + { + num_rm_instances_opened = resMgrObj[hwId].numOpens; + for (resMgrInstIdx = 0u; num_rm_instances_opened; ++resMgrInstIdx) + { + /* Check whether the RM instance opened working on this region */ + rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (hwId*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx); + if (NULL != rm_instance) + { + if (rm_instance->initParam.regionId == edma3RegionId) + { + /* Region id matches, call the callback function */ + if (rm_instance->initParam.gblerrCbParams.gblerrCb != NULL) + { + rm_instance->initParam.gblerrCbParams.gblerrCb( + EDMA3_RM_E_TC_INVALID_ADDR, + tcNum, + rm_instance->initParam.gblerrCbParams.gblerrData); + } + } + } + + /* Check next opened instance */ + num_rm_instances_opened--; + } + + tcRegs->ERRCLR = (1<EMCR = EDMA3_RM_SET_ALL_BITS; + ptrEdmaccRegs->EMCRH = EDMA3_RM_SET_ALL_BITS; + ptrEdmaccRegs->QEMCR = EDMA3_RM_SET_ALL_BITS; + + /* + * Set all Instance-wide EDMA3 parameters (not channel-specific) + */ + + /** + * Set TC Priority among system-wide bus-masters and Queue + * Watermark Level + */ + while (evtQNum < + resMgrObj[phyCtrllerInstId].gblCfgParams.numEvtQueue) + { + ptrEdmaccRegs->QUEPRI &= EDMA3_RM_QUEPRI_CLR_MASK(evtQNum); + ptrEdmaccRegs->QUEPRI |= EDMA3_RM_QUEPRI_SET_MASK(evtQNum, + resMgrObj[phyCtrllerInstId].gblCfgParams.evtQPri[evtQNum]); + + ptrEdmaccRegs->QWMTHRA |= EDMA3_RM_QUEWMTHR_SET_MASK(evtQNum, + resMgrObj[phyCtrllerInstId].gblCfgParams.evtQueueWaterMarkLvl[evtQNum]); + + evtQNum++; + } + + /* Clear CCERR register */ + ptrEdmaccRegs ->CCERRCLR = 0xFFFFu; + } + + return; + } + + + + +/** Initialization of the Shadow region registers of the EDMA3 Controller */ +static void edma3ShadowRegionInit (const EDMA3_RM_Instance *pRMInstance) + { + unsigned int intState = 0u; + volatile EDMA3_CCRL_Regs *ptrEdmaccRegs = NULL; + volatile EDMA3_CCRL_ShadowRegs *ptrEdmaShadowRegs = NULL; + unsigned int phyCtrllerInstId; + unsigned int regionId; + const EDMA3_RM_InstanceInitConfig *rmInstInitConfig = pRMInstance->initParam.rmInstInitConfig; + + assert (pRMInstance != NULL); + + if (rmInstInitConfig != NULL) + { + phyCtrllerInstId = pRMInstance->pResMgrObjHandle->phyCtrllerInstId; + regionId = pRMInstance->initParam.regionId; + + ptrEdmaccRegs = (volatile EDMA3_CCRL_Regs *) + (resMgrObj[phyCtrllerInstId].gblCfgParams.globalRegs); + + if (ptrEdmaccRegs != NULL) + { + ptrEdmaShadowRegs = (volatile EDMA3_CCRL_ShadowRegs *) + (&ptrEdmaccRegs->SHADOW[regionId]); + + ptrEdmaShadowRegs->ECR = (rmInstInitConfig->ownDmaChannels[0u] + | rmInstInitConfig->ownTccs[0u]); + ptrEdmaShadowRegs->ECRH = (rmInstInitConfig->ownDmaChannels[1u] + | rmInstInitConfig->ownTccs[1u]); + ptrEdmaShadowRegs->EECR = (rmInstInitConfig->ownDmaChannels[0u] + | rmInstInitConfig->ownTccs[0u]); + ptrEdmaShadowRegs->SECR = (rmInstInitConfig->ownDmaChannels[0u] + | rmInstInitConfig->ownTccs[0u]); + ptrEdmaShadowRegs->SECRH = (rmInstInitConfig->ownDmaChannels[1u] + | rmInstInitConfig->ownTccs[1u]); + ptrEdmaShadowRegs->EECR = (rmInstInitConfig->ownDmaChannels[0u] + | rmInstInitConfig->ownTccs[0u]); + ptrEdmaShadowRegs->EECRH = (rmInstInitConfig->ownDmaChannels[1u] + | rmInstInitConfig->ownTccs[1u]); + + ptrEdmaShadowRegs->QEECR = rmInstInitConfig->ownQdmaChannels[0u]; + + ptrEdmaShadowRegs->IECR = (rmInstInitConfig->ownDmaChannels[0u] + | rmInstInitConfig->ownTccs[0u]); + ptrEdmaShadowRegs->IECRH = (rmInstInitConfig->ownDmaChannels[1u] + | rmInstInitConfig->ownTccs[1u]); + ptrEdmaShadowRegs->ICR = (rmInstInitConfig->ownDmaChannels[0u] + | rmInstInitConfig->ownTccs[0u]); + ptrEdmaShadowRegs->ICRH = (rmInstInitConfig->ownDmaChannels[1u] + | rmInstInitConfig->ownTccs[1u]); + + ptrEdmaShadowRegs->QSECR = rmInstInitConfig->ownQdmaChannels[0u]; + + /* + * Set all EDMA3 Resource<->Region mapping parameters + */ + + /* 1. Dma Channel (and TCC) <-> Region */ +#ifdef EDMA3_RM_DEBUG + EDMA3_RM_PRINTF("DRAE=%x\r\n",ptrEdmaccRegs->DRA[regionId].DRAE); + EDMA3_RM_PRINTF("DRAEH=%x\r\n",ptrEdmaccRegs->DRA[regionId].DRAEH); +#endif + + edma3OsProtectEntry (EDMA3_OS_PROTECT_INTERRUPT, &intState); + ptrEdmaccRegs->DRA[regionId].DRAE = 0u; + ptrEdmaccRegs->DRA[regionId].DRAEH = 0u; + edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT, intState); + +#ifdef EDMA3_RM_DEBUG + EDMA3_RM_PRINTF("DRAE=%x\r\n",ptrEdmaccRegs->DRA[regionId].DRAE); + EDMA3_RM_PRINTF("DRAEH=%x\r\n",ptrEdmaccRegs->DRA[regionId].DRAEH); +#endif + + /* 2. Qdma Channel <-> Region */ +#ifdef EDMA3_RM_DEBUG + EDMA3_RM_PRINTF("QRAE=%x\r\n",ptrEdmaccRegs->QRAE[regionId]); +#endif + + edma3OsProtectEntry (EDMA3_OS_PROTECT_INTERRUPT, &intState); + ptrEdmaccRegs->QRAE[regionId] = 0u; + edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT, intState); + +#ifdef EDMA3_RM_DEBUG + EDMA3_RM_PRINTF("QRAE=%x\r\n",ptrEdmaccRegs->QRAE[regionId]); +#endif + + } + } + + return; + } + + + +/** Local MemSet function */ +void edma3MemSet(void *dst, unsigned char data, unsigned int len) + { + unsigned int i=0u; + unsigned char *ds=NULL; + + assert (dst != NULL); + + ds = (unsigned char *)dst; + + for( i=0;i>= (start%32u); + + while ((found==0u) && (source!=0)) + { + if ((source & 0x1) == 0x1) + { + /* 1 */ + found++; + } + else + { + /* 0 */ + source >>= 1; + position++; + } + } + + } + break; + + case 0: + { + source >>= (start%32u); + iterations_left = 32u - (start%32u); + + while ((found==0u) && (iterations_left>0u)) + { + if ((source & 0x1) == 0x1) + { + /* 1 */ + source >>= 1; + position++; + iterations_left--; + } + else + { + /* 0 */ + found++; + } + } + } + break; + + default: + break; + } + + return (found ? (int)position : -1); + } + + +/** + * Finds a particular bit ('0' or '1') in the specified resources' array + * from 'start' to 'end'. If found, returns the position, else return -1. + */ +static int findBit (EDMA3_RM_ResType resType, + unsigned int start, + unsigned int end, + unsigned short bit) + { + int position = -1; + unsigned int start_index = start / 32u; + unsigned int end_index = end / 32u; + int i; + unsigned int *resPtr = 0x0; + int ret = -1; + EDMA3_RM_Result result = EDMA3_RM_SOK; + + assert (start <= end); + + /** + * job is to find 'bit' in an array[start_index:end_index] + * algo used: + * first search in array[start_index] + * then search in array[start_index + 1 : end_index - 1] + * then search in array[end_index] + */ + switch (resType) + { + case EDMA3_RM_RES_DMA_CHANNEL: + resPtr = &contiguousDmaRes[0]; + break; + + case EDMA3_RM_RES_QDMA_CHANNEL: + resPtr = &contiguousQdmaRes[0]; + break; + + case EDMA3_RM_RES_TCC: + resPtr = &contiguousTccRes[0]; + break; + + case EDMA3_RM_RES_PARAM_SET: + resPtr = &contiguousParamRes[0]; + break; + + default: + result = EDMA3_RM_E_INVALID_PARAM; + break; + } + + if (EDMA3_RM_SOK == result) + { + switch (bit) + { + case 1: + { + /* Find '1' in first word. */ + position = findBitInWord (resPtr[start_index], start, 1u); + + if (position != -1) + { + ret = position; + } + else + { + /* '1' NOT found, look into other words. */ + for (i = (int)(start_index + 1u); i <= (int)(end_index - 1u); i++) + { + position = findBitInWord (resPtr[i], 0u, 1u); + if (position != -1) + { + /* '1' Found... */ + ret = (position + (i*32)); + break; + } + } + + /* First check whether we have found '1' or not. */ + if (ret == -1) + { + /* Still not found, look in the last word. */ + position = findBitInWord(resPtr[end_index], 0u, 1u); + if (position != -1) + { + /* Finally got it. */ + ret = (position + (end_index*32u)); + } + else + { + /* Sorry, could not find it, return -1. */ + ret = -1; + } + } + } + } + break; + + case 0: + { + /* Find '0' in first word. */ + position = findBitInWord(resPtr[start_index], start, 0u); + if (position != -1) + { + ret = position; + } + else + { + /* '0' NOT found, look into other words. */ + for (i = (start_index + 1u); i <= (end_index - 1u); i++) + { + position = findBitInWord(resPtr[i], 0u, 0u); + if (position != -1) + { + /* '0' found... */ + ret = (position + (i*32)); + break; + } + } + + /* First check whether we have found '0' or not. */ + if (ret == -1) + { + position = findBitInWord(resPtr[end_index], 0u, 0u); + if (position != -1) + { + /* Finally got it. */ + ret = (position + (end_index*32u)); + } + else + { + /* Sorry, could not find it, return -1. */ + ret = -1; + } + } + } + } + break; + + default: + break; + } + } + + + + return ((ret >= start) ? ret : -1); +} + + + +/** + * If successful, this function returns EDMA3_RM_SOK and the position + * of first available resource in 'positionRes'. Else returns error. + */ +static EDMA3_RM_Result allocAnyContigRes(EDMA3_RM_ResType resType, + unsigned int numResources, + unsigned int *positionRes) + { + unsigned short found = 0u; + int first_one, next_zero; + unsigned int num_available; + int ret = -1; + unsigned int start = 0; + unsigned int end; + EDMA3_RM_Result result = EDMA3_RM_SOK; + + assert (positionRes != NULL); + + switch (resType) + { + case EDMA3_RM_RES_DMA_CHANNEL: + end = EDMA3_MAX_DMA_CH - 1u; + break; + + case EDMA3_RM_RES_QDMA_CHANNEL: + end = EDMA3_MAX_QDMA_CH - 1u; + break; + + case EDMA3_RM_RES_TCC: + end = EDMA3_MAX_TCC - 1u; + break; + + case EDMA3_RM_RES_PARAM_SET: + end = edma3NumPaRAMSets - 1u; + break; + + default: + result = EDMA3_RM_E_INVALID_PARAM; + break; + } + + if (result == EDMA3_RM_SOK) + { + /** + * Algorithm used for finding N contiguous resources. + * In the resources' array, '1' means available and '0' means + * not-available. + * Step a) Find first '1' starting from 'start'. If successful, + * store it in first_one, else return error. + * Step b) Find first '0' starting from (first_one+1) to 'end'. + * If successful, store returned value in next_zero. If '0' could + * not be located, it means all the resources are available. + * Store 'end' (i.e. the last resource id) in next_zero. + * Step c) Count the number of contiguous resources available + * by subtracting first_one from next_zero. + * Step d) If result < N, do the whole process again untill you + * reach end. Else you have found enough resources, return success. + */ + while((found == 0) && (((end-start)+1u) >= numResources)) + { + /* Find first '1' starting from 'start' till 'end'. */ + first_one = findBit (resType, start, end, 1u); + if (first_one != -1) + { + /* Got first 1, search for first '0' now. */ + next_zero = findBit (resType, first_one+1, end, 0u); + if (next_zero == -1) + { + /* Unable to find next zero, all 1' are there */ + next_zero = end + 1u; + } + + /* check no of resources available */ + num_available = next_zero - first_one; + if (num_available >= numResources) + { + /* hurrah..., we have found enough resources. */ + found = 1u; + ret = first_one; + } + else + { + /* Not enough resources, try again */ + start = next_zero + 1; + } + } + else + { + /* do nothing, first 1 is not there, return. */ + break; + } + } + } + + + if (result == EDMA3_RM_SOK) + { + if (found == 1u) + { + /* required resources found, retrun the first available res id. */ + *positionRes = (unsigned int)ret; + } + else + { + /* No resources allocated */ + result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE; + } + } + + return result; + } + + + +/** + * Starting from 'firstResIdObj', this function makes the next 'numResources' + * Resources non-available for future. Also, it does some global resisters' + * setting also. + */ +static EDMA3_RM_Result gblChngAllocContigRes(EDMA3_RM_Instance *rmInstance, + const EDMA3_RM_ResDesc *firstResIdObj, + unsigned int numResources) + { + EDMA3_RM_Result result = EDMA3_RM_SOK; + volatile EDMA3_CCRL_Regs *gblRegs = NULL; + EDMA3_RM_Obj *rmObj = NULL; + unsigned int avlblIdx = 0u; + unsigned int firstResId=0u; + unsigned int lastResId=0u; + + assert ((rmInstance != NULL) && (firstResIdObj != NULL)); + + rmObj = rmInstance->pResMgrObjHandle; + + if (rmObj == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + + if (EDMA3_RM_SOK == result) + { + gblRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs); + + if (gblRegs == NULL) + { + result = EDMA3_RM_E_INVALID_PARAM; + } + } + + if (result == EDMA3_RM_SOK) + { + switch (firstResIdObj->type) + { + case EDMA3_RM_RES_DMA_CHANNEL: + { + firstResId = firstResIdObj->resId; + lastResId = firstResId + (numResources - 1u); + + for (avlblIdx=firstResId; avlblIdx <= lastResId; ++avlblIdx) + { + rmInstance->avlblDmaChannels[avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u))); + + /** + * Enable the DMA channel in the DRAE/DRAEH registers also. + */ + if (avlblIdx < 32u) + { + gblRegs->DRA[rmInstance->initParam.regionId].DRAE + |= (0x1u << avlblIdx); + } + else + { + gblRegs->DRA[rmInstance->initParam.regionId].DRAEH + |= (0x1u << (avlblIdx - 32u)); + } + } + } + break; + + case EDMA3_RM_RES_QDMA_CHANNEL: + { + firstResId = firstResIdObj->resId; + lastResId = firstResId + (numResources - 1u); + + for (avlblIdx=firstResId; avlblIdx <= lastResId; ++avlblIdx) + { + rmInstance->avlblQdmaChannels[avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u))); + + /** + * Enable the QDMA channel in the QRAE register also. + */ + gblRegs->QRAE[rmInstance->initParam.regionId] + |= (0x1u << avlblIdx); + } + } + break; + + case EDMA3_RM_RES_TCC: + { + firstResId = firstResIdObj->resId; + lastResId = firstResId + (numResources - 1u); + + for (avlblIdx=firstResId; avlblIdx <= lastResId; ++avlblIdx) + { + rmInstance->avlblTccs[avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u))); + + /** + * Enable the Interrupt channel in the DRAE/DRAEH registers. + * Also, If the region id coming from this + * RM instance is same as the Master RM + * Instance's region id, only then we will be + * getting the interrupts on the same side. + * So save the TCC in the allocatedTCCs[] array. + */ + if (avlblIdx < 32u) + { + gblRegs->DRA[rmInstance->initParam.regionId].DRAE + |= (0x1u << avlblIdx); + + if (edma3RegionId == rmInstance->initParam.regionId) + { + allocatedTCCs[0u] |= (0x1u << avlblIdx); + } + } + else + { + gblRegs->DRA[rmInstance->initParam.regionId].DRAEH + |= (0x1u << (avlblIdx - 32u)); + + if (edma3RegionId == rmInstance->initParam.regionId) + { + allocatedTCCs[1u] |= (0x1u << (avlblIdx - 32u)); + } + } + } + } + break; + + case EDMA3_RM_RES_PARAM_SET: + { + firstResId = firstResIdObj->resId; + lastResId = firstResId + (numResources - 1u); + + for (avlblIdx=firstResId; avlblIdx <= lastResId; ++avlblIdx) + { + rmInstance->avlblPaRAMSets [avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u))); + + /** + * Also, make the actual PARAM Set NULL, checking the flag + * whether it is required or not. + */ + if (TRUE == rmInstance->paramInitRequired) + { + edma3MemSet((void *)(&gblRegs->PARAMENTRY[avlblIdx]), + 0x00u, + sizeof(gblRegs->PARAMENTRY[avlblIdx])); + } + } + } + break; + + default: + result = EDMA3_RM_E_INVALID_PARAM; + break; + } + } + + + return result; + } + +/* Resource Manager Internal functions - End */ + +/* End of File */ diff --git a/packages/ti/sdo/edma3/rm/src/edma3resmgr.h b/packages/ti/sdo/edma3/rm/src/edma3resmgr.h new file mode 100644 index 0000000..a6393d0 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/src/edma3resmgr.h @@ -0,0 +1,352 @@ +/******************************************************************************* +**+--------------------------------------------------------------------------+** +**| **** |** +**| **** |** +**| ******o*** |** +**| ********_///_**** |** +**| ***** /_//_/ **** |** +**| ** ** (__/ **** |** +**| ********* |** +**| **** |** +**| *** |** +**| |** +**| Copyright (c) 1998-2006 Texas Instruments Incorporated |** +**| ALL RIGHTS RESERVED |** +**| |** +**| Permission is hereby granted to licensees of Texas Instruments |** +**| Incorporated (TI) products to use this computer program for the sole |** +**| purpose of implementing a licensee product based on TI products. |** +**| No other rights to reproduce, use, or disseminate this computer |** +**| program, whether in part or in whole, are granted. |** +**| |** +**| TI makes no representation or warranties with respect to the |** +**| performance of this computer program, and specifically disclaims |** +**| any responsibility for any damages, special or consequential, |** +**| connected with the use of this program. |** +**| |** +**+--------------------------------------------------------------------------+** +*******************************************************************************/ + +/** \file edma3resmgr.h + \brief EDMA3 Resource Manager Internal header file. + + This file contains implementation specific details used by the RM internally + + (C) Copyright 2006, Texas Instruments, Inc + + \version 0.1.0 Joseph Fernandez - Created + 0.2.0 Anuj Aggarwal - Modified it for EDMA3 package + - Added multiple instances + capability + 0.2.1 Anuj Aggarwal - Modified it for more run time + configuration. + - Made EDMA3 package OS + independent. + 0.2.2 Anuj Aggarwal - Critical section handling code + modification. Uses semaphore and + interrupts disabling mechanism + for resource sharing. + 0.3.0 Anuj Aggarwal - Renamed EDMA3_DVR to EDMA3_DRV + - IPR bit clearing in RM ISR + issue fixed. + - Sample application made generic + 0.3.1 Anuj Aggarwal - Added DMA/QDMA Channel to TCC + mapping, to fix QDMA missed + event issue. + 0.3.2 Anuj Aggarwal - Added support for POLL mode + - Added a new API to modify the + CC Register. + 1.0.0 Anuj Aggarwal - Fixed resource allocation related + bugs. + 1.0.0.1 Anuj Aggarwal - Fixed spurious missed event + generation related bug. + 1.0.0.2 Anuj Aggarwal - Made the EDMA3 package RTSC + compliant. + 1.0.0.3 Anuj Aggarwal - Changed the directory structure + as per RTSC standard. + 1.01.00.01 Anuj Aggarwal - a) Added new APIs to allocate + logical channels + b) Created EDMA3 config files + for different platforms + c) Misc changes + 1.02.00.01 Anuj Aggarwal - a) Added DM6467 support + b) Fixed some MRs + 1.03.00.01 Anuj Aggarwal - a) Added non-RTSC PJT files + b) IOCTL Interface added. + c) Fixed some MRs. + 1.04 Anuj Aggarwal - a) Added new IOCTLs and APIs. + b) Number of maximum Resource + Manager Instances is configurable. + c) Header files modified to have + extern "C" declarations. + + + */ + +#ifndef _EDMA3_RES_MGR_H_ +#define _EDMA3_RES_MGR_H_ + + +/** Include Resource Manager header file */ +#include + +/* For the EDMA3 Register Layer functionality. */ +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Number of PaRAM Sets actually present on the SoC. This will be updated + * while creating the Resource Manager Object. + */ +extern unsigned int edma3NumPaRAMSets; + + +/** Define for setting all bits of the EDMA3 Controller Registers */ +#define EDMA3_RM_SET_ALL_BITS (0xFFFFFFFFu) + +/* Other Mask defines */ +/** DCHMAP-PaRAMEntry bitfield Clear */ +#define EDMA3_RM_DCH_PARAM_CLR_MASK (~EDMA3_CCRL_DCHMAP_PAENTRY_MASK) +/** DCHMAP-PaRAMEntry bitfield Set */ +#define EDMA3_RM_DCH_PARAM_SET_MASK(paRAMId) (((EDMA3_CCRL_DCHMAP_PAENTRY_MASK >> EDMA3_CCRL_DCHMAP_PAENTRY_SHIFT) & (paRAMId)) << EDMA3_CCRL_DCHMAP_PAENTRY_SHIFT) +/** QCHMAP-PaRAMEntry bitfield Clear */ +#define EDMA3_RM_QCH_PARAM_CLR_MASK (~EDMA3_CCRL_QCHMAP_PAENTRY_MASK) +/** QCHMAP-PaRAMEntry bitfield Set */ +#define EDMA3_RM_QCH_PARAM_SET_MASK(paRAMId) (((EDMA3_CCRL_QCHMAP_PAENTRY_MASK >> EDMA3_CCRL_QCHMAP_PAENTRY_SHIFT) & (paRAMId)) << EDMA3_CCRL_QCHMAP_PAENTRY_SHIFT) +/** QCHMAP-TrigWord bitfield Clear */ +#define EDMA3_RM_QCH_TRWORD_CLR_MASK (~EDMA3_CCRL_QCHMAP_TRWORD_MASK) +/** QCHMAP-TrigWord bitfield Set */ +#define EDMA3_RM_QCH_TRWORD_SET_MASK(paRAMId) (((EDMA3_CCRL_QCHMAP_TRWORD_MASK >> EDMA3_CCRL_QCHMAP_TRWORD_SHIFT) & (paRAMId)) << EDMA3_CCRL_QCHMAP_TRWORD_SHIFT) +/** QUEPRI bits Clear */ +#define EDMA3_RM_QUEPRI_CLR_MASK(queNum) (~(EDMA3_CCRL_QUEPRI_PRIQ0_MASK << ((queNum) * EDMA3_CCRL_QUEPRI_PRIQ1_SHIFT))) +/** QUEPRI bits Set */ +#define EDMA3_RM_QUEPRI_SET_MASK(queNum,quePri) ((EDMA3_CCRL_QUEPRI_PRIQ0_MASK & (quePri)) << ((queNum) * EDMA3_CCRL_QUEPRI_PRIQ1_SHIFT)) +/** QUEWMTHR bits Clear */ +#define EDMA3_RM_QUEWMTHR_CLR_MASK(queNum) (~(EDMA3_CCRL_QWMTHRA_Q0_MASK << ((queNum) * EDMA3_CCRL_QWMTHRA_Q1_SHIFT))) +/** QUEWMTHR bits Set */ +#define EDMA3_RM_QUEWMTHR_SET_MASK(queNum,queThr) ((EDMA3_CCRL_QWMTHRA_Q0_MASK & (queThr)) << ((queNum) * EDMA3_CCRL_QWMTHRA_Q1_SHIFT)) + +/** OPT-TCC bitfield Clear */ +#define EDMA3_RM_OPT_TCC_CLR_MASK (~EDMA3_CCRL_OPT_TCC_MASK) +/** OPT-TCC bitfield Set */ +#define EDMA3_RM_OPT_TCC_SET_MASK(tcc) (((EDMA3_CCRL_OPT_TCC_MASK >> EDMA3_CCRL_OPT_TCC_SHIFT) & (tcc)) << EDMA3_CCRL_OPT_TCC_SHIFT) + +/** PaRAM Set Entry for Link and B count Reload field */ +#define EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD (5u) + + +/** + * \defgroup Edma3ResMgrInt Internal Interface Definition for Resource Manager + * + * Documentation of the Internal Interface of Resource Manager + * + * @{ + */ + + +/** + * \defgroup Edma3ResMgrIntObjMaint Object Maintenance + * + * Maintenance of the EDMA3 Resource Manager Object + * + * @{ + */ + + +/** To maintain the state of the EDMA3 Resource Manager Object */ +typedef enum { + /** Object deleted */ + EDMA3_RM_DELETED = 0, + /** Obect Created */ + EDMA3_RM_CREATED = 1, + /** Object Opened */ + EDMA3_RM_OPENED = 2, + /** Object Closed */ + EDMA3_RM_CLOSED = 3 +} EDMA3_RM_ObjState; + + + +/** + * \defgroup Edma3RMIntBoundVals Boundary Values + * + * Boundary Values for Logical Channel Ranges + * + * @{ + */ +/** Max of DMA Channels */ +#define EDMA3_RM_DMA_CH_MAX_VAL (EDMA3_MAX_DMA_CH - 1u) + +/** Min of Link Channels */ +#define EDMA3_RM_LINK_CH_MIN_VAL (EDMA3_MAX_DMA_CH) + +/** Max of Link Channels */ +#define EDMA3_RM_LINK_CH_MAX_VAL (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS - 1u) + +/** Min of QDMA Channels */ +#define EDMA3_RM_QDMA_CH_MIN_VAL (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS) + +/** Max of QDMA Channels */ +#define EDMA3_RM_QDMA_CH_MAX_VAL (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS + EDMA3_MAX_QDMA_CH - 1u) + +/** Max of Logical Channels */ +#define EDMA3_RM_LOG_CH_MAX_VAL (EDMA3_RM_QDMA_CH_MAX_VAL) + + + +/* @} Edma3RMIntBoundVals */ + + + + + +/** + * \brief EDMA3 Hardware Instance Configuration Structure. + * + * Used to maintain information of the EDMA3 HW configuration. + * One such storage exists for each instance of the EDMA 3 HW. + */ +typedef struct + { + /** HW Instance Id of the EDMA3 Controller */ + unsigned int phyCtrllerInstId; + + /** State information of the Resource Manager object */ + EDMA3_RM_ObjState state; + + /** Number of active opens of RM Instances */ + unsigned int numOpens; + + /** + * \brief Init-time Configuration structure for EDMA3 + * controller, to provide Global SoC specific Information. + * + * This configuration will can be provided by the user at run-time, + * while calling EDMA3_RM_create(). + */ + EDMA3_RM_GblConfigParams gblCfgParams; + + } EDMA3_RM_Obj; + + +/** + * \brief EDMA3 RM Instance Specific Configuration Structure. + * + * Used to maintain information of the EDMA3 Res Mgr instances. + * One such storage exists for each instance of the EDMA3 Res Mgr. + * + * Maximum EDMA3_MAX_RM_INSTANCES instances are allowed for + * each EDMA3 hardware instance, for same or different shadow regions. + */ +typedef struct + { + /** + * Configuration such as region id, IsMaster, Callback function + * This configuration is passed to the "Open" API. + * For a single EDMA3 HW controller, there can be EDMA3_MAX_REGIONS + * different instances tied to different regions. + */ + EDMA3_RM_Param initParam; + + /** Pointer to appropriate Shadow Register region of CC Registers */ + EDMA3_CCRL_ShadowRegs *shadowRegs; + + /** + * Pointer to the EDMA3 RM Object (HW specific) + * opened by RM instance. + */ + EDMA3_RM_Obj *pResMgrObjHandle; + + /** Available DMA Channels to the RM Instance */ + unsigned int avlblDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS]; + + /** Available QDMA Channels to the RM Instance */ + unsigned int avlblQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS]; + + /** Available PaRAM Sets to the RM Instance */ + unsigned int avlblPaRAMSets[EDMA3_MAX_PARAM_DWRDS]; + + /** Available TCCs to the RM Instance */ + unsigned int avlblTccs[EDMA3_MAX_TCC_DWRDS]; + + /** + * Sometimes, PaRAM clearing is not required for some particular RM + * Instances. In that case, PaRAM Sets allocated will NOT be cleared before + * allocating to any particular user. It is the responsibility of user + * to program it accordingly, without assuming anything for a specific + * field because the PaRAM Set might contain junk values. Not programming + * it fully might result in erroneous behavior. + * On the other hand, RM instances can also use this variable to get the + * PaRAM Sets cleared before allocating them to the specific user. + * User can program only the selected fields in this case. + * + * Value '0' : PaRAM Sets will NOT be cleared during their allocation. + * Value '1' : PaRAM Sets will be cleared during their allocation. + * + * This value can be modified using the IOCTL commands. + */ + unsigned int paramInitRequired; + + /** + * Sometimes, global EDMA3 registers (DCHMAP/QCHMAP) and PaRAM Sets should + * not be modified during EDMA3_RM_allocLogicalChannel (), for some particular RM + * Instances. In that case, it is the responsibility of user + * to program them accordingly, when needed, without assuming anything because + * they might contain junk values. Not programming + * the registers/PaRAMs fully might result in erroneous behavior. + * On the other hand, RM instances can also use this variable to get the + * global registers and PaRAM Sets minimally programmed before allocating them to + * the specific user. + * User can program only the remaining fields in this case. + * + * Value '0' : EDMA3 registers (DCHMAP/QCHMAP) and PaRAM Sets will NOT be programmed during their allocation. + * Value '1' : EDMA3 registers (DCHMAP/QCHMAP) and PaRAM Sets will be programmed during their allocation. + * + * This value can be modified using the IOCTL commands. + */ + unsigned int regModificationRequired; + + }EDMA3_RM_Instance; + +/* @} Edma3ResMgrIntObjMaint */ + + +/** + * \brief EDMA3 Channel-Bound resources. + * + * Used to maintain information of the EDMA3 resources + * (specifically Parameter RAM set and TCC), bound to the + * particular channel within EDMA3_RM_allocLogicalChannel (). + */ +typedef struct { + /** PaRAM Set number associated with the particular channel */ + int paRAMId; + + /** TCC associated with the particular channel */ + unsigned int tcc; +} EDMA3_RM_ChBoundResources; + + +/** + * \brief TCC Callback - Caters to channel specific status reporting. + */ +typedef struct { + /** Callback function */ + EDMA3_RM_TccCallback tccCb; + + /** Callback data, passed to the Callback function */ + void *cbData; +} EDMA3_RM_TccCallbackParams; + + +/* @} Edma3ResMgrInt */ + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif /* _EDMA3_RES_MGR_H_ */ diff --git a/release_notes_edma3_lld_02_00_00.html b/release_notes_edma3_lld_02_00_00.html new file mode 100644 index 0000000..99ae295 --- /dev/null +++ b/release_notes_edma3_lld_02_00_00.html @@ -0,0 +1,431 @@ + + + + + +EDMA3 LLD 02.00.00 Release Notes + + + + + + + + + + + + + + +
+ Texas Instruments + + Technology for Innovators(tm) +
+ +

EDMA3 LLD 02.00.00 Release Notes

+ +

Oct 16, 2008

+ +

+This EDMA3 Low Level Driver Release is targeted to the users (device drivers +and applications) for submitting and synchronizing with EDMA3 based DMA transfers. +This release supports DA830 platform, on DSP/BIOS 6 side. Porting instructions +are also provided to use the package for different platforms and Operating +Systems. +

+ +

+Introduction, +Documentation, +What's New, +Upgrade Info, +Device Support, +Compatibility Information, +Validation Info, +Known Issues, +Examples, +Version Information, +Technical Support +

+ +
+ + +

Introduction

+ +

+EDMA3 LLD is a single product package containing the following stand-alone +software components: +

+ +
    +
  • + EDMA3 Resource Manager - TI mandated library for all EDMA3 peripheral + users to acquire and configure EDMA3 hardware resources (DMA/QDMA channels, + PaRAM Sets, TCCs etc.) and DMA Interrupt Service Routines. +
    • + +
  • + EDMA3 Driver - Functional library providing APIs for programming, + scheduling and synchronizing with EDMA transfers and many more. +
    • +
+ +

+EDMA3 Resource Manager can be used independently whereas the EDMA3 Driver requires +the Resource Manager services internally. +

+ +

+EDMA3 LLD (both Resource Manager and the Driver) is a platform independent package. +Hence it can be used across multiple platforms. Porting instructions are provided + for both the components to do the same. +

+ +

+It is also an OS-agnostic package and thus can be used across multiple operating +systems. OS-adaptation layer needs to be provided by the user (in case it is needed) +for OS customization. Instructions to do the same are also provided along with +the package. +

+ +

+The Low Level Driver has already been ported (DSP/BIOS Operating Systems) +and tested on various platforms mentioned below. Sample initialization libraries, +which configure the EDMA3 hardware and provide the necessary OS abstraction layer, +are also a part of the package. These libraries are available both for the EDMA3 +Resource Manager and EDMA3 Driver. These could be used for proper +initialization of the software component(s) along with the OS adaptation layer +for the same. +

+ +

+The Low Level Driver consists of the following packages: +

+ +
    +
  • + ti.sdo.edma3.rm - EDMA3 Resource Manager. +
    • +
  • + ti.sdo.edma3.rm.sample - Sample initialization library / OS + abstraction layer for the Resource Manager. +
    • +
  • + ti.sdo.edma3.drv - EDMA3 Driver. +
    • +
  • + ti.sdo.edma3.drv.sample - Sample initialization library / OS + abstraction layer for the Driver. +
    • +
+ + + +

Documentation

+ +

The following documentation is available:

+ + + +
+ + +

What's New

+ +

+This is the first release of the EDMA3 Low Level Driver for BIOS 6 based +platforms. +

+ +
+ + +

Upgrade Information

+ +

+The EDMA3 LLD packages are available in the "packages/" subdirectory of the product. +If you have a previous release of the EDMA3 LLD product, you can install this +release next to it, and modify your application and/or server builds to use this +newer release. +

+ +
+ + +

Device Support

+ +

+This release supports and has been tested on the following devices: +

+ +
    +
  • + DA830 EVM: +
      +
    • C67x DSP/BIOS
      • +
    +
    • +
+ +
+ + +

Compatibility Information

+ +

Compatibility Key Definitions

+ +

+Compatibility keys are intentionally independent of Marketing product numbers +and are intended to: +

+ +
    +
  1. + Enable tooling to identify incompatibilities between components, and +
    2. +
  2. + Convey a level of compatibility between different releases to set end user expectations. +
    3. +
+ +

+Compatibility keys are composed of 3 comma-delimited numbers - M, S, R - where: +

+ +
    +
  • + M = Major. A difference in M indicates a break in compatibility. +
    • +
  • + S = Source. A difference in S indicates source compatibility. That is, + the user's source doesn't require change, but does require rebuilding. +
    • +
  • + R = Radix. A difference in R indicates an introduction of new features, + but compatibility with previous interfaces has not broken. If libraries are + provided by the package, an application must re-link with the new libraries, + but not rebuild from source. +
    • +
+ +
+ + +

Validation

+ +

+This release was built and validated against using the following components: +

+ +
    +
  • CCS 4.0.0.8.3
    • +
  • C6x Code Generation Tools version 6.1.5
    • +
  • DSP/BIOS 6.10
    • +
  • XDC Tools 3.10.02
    • +
+ +

+This release was validated in the following configurations: +

+ +
    +
  • + DA830 EVM: +
      +
    • C67x DSP/BIOS
      • +
    +
    • +
+ +
+ + +

Known Issues

+ +

+The following are known issues with the current EDMA3 LLD release: +

+ +

Pre-built instrumented libraries for DA830 not provided initially.

+ +

Pre-built instrumented EDMA3 libraries for DA830 will not be provided +initially. XDC does not support the same and hence the limitation. See IR# +SDOCM00036738 for more details. +

+ +

EDMA3 hardware doesn’t work properly in FIFO mode with all the controllers.

+ +

Very few peripherals support EDMA3 FIFO mode. EMIF controller doesn't support +the same. So EDMA3 CANNOT be used in FIFO mode for doing a memory-to-memory data +transfers, EDMA3 being configured in the FIFO mode. Applications trying to use +EDMA3 in FIFO mode should first check their respective peripheral-controller +document for this mode support. +

+ +
+ + +

Examples

+ +

+EDMA3 LLD sample initialization libraries / OS abstraction layers (for different +platforms) are located in: +

+ +
    +
  • + For Resource Manager: They could be located in + edma3_lld_02_00_00_XX\packages\ti\sdo\edma3\rm\sample\lib + folder. +
    • + +
  • + For EDMA3 Driver: They could be located in + edma3_lld_02_00_00_XX\packages\ti\sdo\edma3\drv\sample\lib + folder. +
    • +
+ +

+EDMA3 LLD stand-alone applications (for different platforms) are located in: +

+ +
    +
  • + EDMA3 Driver: They could be located in + edma3_lld_02_00_00_XX\examples\edma3_driver\ + folder. +
    • +
+ +
    +
  • + CSL2.x DAT Reference Implementation: It could be located in + edma3_lld_02_00_00_XX\examples\CSL2_DAT_DEMO\ + folder. +
    • +
+ +
+ + +

Version Information

+ +

+This product's version follows a version format, M.mm.pp.bb, where +M is a 2 digit major number, +mm is 2 digit minor number, +pp is a 2 digit patch number, and +b is an unrestricted set of digits used as an incrementing build counter. +

+ +

+To support multiple side-by-side installations of the product, the product +version is encoded in the top level directory, ex. edma3_lld_02_00_00_XX. +

+ +

Subsequent releases of patch upgrades will be identified by the patch number, +ex. EDMA3 LLD 02.00.01 with directory edma3_lld_02_00_01_YY. Typically, these +patches only include critical bug fixes. +

+ +
+ + +

Technical Support

+ +

+For technical support, contact softwaresupport@ti.com +

+ +
+ +

+Last updated: Oct 16, 2008 +

+ + -- 2.39.2

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is: +# TAG = value [value, ...] +# For lists items can also be appended using: +# TAG += value [value, ...] +# Values that contain spaces should be placed between quotes (" ") + +#--------------------------------------------------------------------------- +# Project related configuration options +#--------------------------------------------------------------------------- + +# This tag specifies the encoding used for all characters in the config file +# that follow. The default is UTF-8 which is also the encoding used for all +# text before the first occurrence of this tag. Doxygen uses libiconv (or the +# iconv built into libc) for the transcoding. See +# http://www.gnu.org/software/libiconv for the list of possible encodings. + +DOXYFILE_ENCODING = UTF-8 + +# The PROJECT_NAME tag is a single word (or a sequence of words surrounded +# by quotes) that should identify the project. + +PROJECT_NAME = "EDMA3 Resource Manager" + +# The PROJECT_NUMBER tag can be used to enter a project or revision number. +# This could be handy for archiving the generated documentation or +# if some version control system is used. + +PROJECT_NUMBER = + +# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) +# base path where the generated documentation will be put. +# If a relative path is entered, it will be relative to the location +# where doxygen was started. If left blank the current directory will be used. + +OUTPUT_DIRECTORY = . + +# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create +# 4096 sub-directories (in 2 levels) under the output directory of each output +# format and will distribute the generated files over these directories. +# Enabling this option can be useful when feeding doxygen a huge amount of +# source files, where putting all generated files in the same directory would +# otherwise cause performance problems for the file system. + +CREATE_SUBDIRS = NO + +# The OUTPUT_LANGUAGE tag is used to specify the language in which all +# documentation generated by doxygen is written. Doxygen will use this +# information to generate all constant output in the proper language. +# The default language is English, other supported languages are: +# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, +# Croatian, Czech, Danish, Dutch, Farsi, Finnish, French, German, Greek, +# Hungarian, Italian, Japanese, Japanese-en (Japanese with English messages), +# Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, Polish, +# Portuguese, Romanian, Russian, Serbian, Slovak, Slovene, Spanish, Swedish, +# and Ukrainian. + +OUTPUT_LANGUAGE = English + +# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will +# include brief member descriptions after the members that are listed in +# the file and class documentation (similar to JavaDoc). +# Set to NO to disable this. + +BRIEF_MEMBER_DESC = YES + +# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend +# the brief description of a member or function before the detailed description. +# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the +# brief descriptions will be completely suppressed. + +REPEAT_BRIEF = YES + +# This tag implements a quasi-intelligent brief description abbreviator +# that is used to form the text in various listings. Each string +# in this list, if found as the leading text of the brief description, will be +# stripped from the text and the result after processing the whole list, is +# used as the annotated text. Otherwise, the brief description is used as-is. +# If left blank, the following values are used ("$name" is automatically +# replaced with the name of the entity): "The $name class" "The $name widget" +# "The $name file" "is" "provides" "specifies" "contains" +# "represents" "a" "an" "the" + +ABBREVIATE_BRIEF = + +# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then +# Doxygen will generate a detailed section even if there is only a brief +# description. + +ALWAYS_DETAILED_SEC = NO + +# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all +# inherited members of a class in the documentation of that class as if those +# members were ordinary class members. Constructors, destructors and assignment +# operators of the base classes will not be shown. + +INLINE_INHERITED_MEMB = NO + +# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full +# path before files name in the file list and in the header files. If set +# to NO the shortest path that makes the file name unique will be used. + +FULL_PATH_NAMES = NO + +# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag +# can be used to strip a user-defined part of the path. Stripping is +# only done if one of the specified strings matches the left-hand part of +# the path. The tag can be used to show relative paths in the file list. +# If left blank the directory from which doxygen is run is used as the +# path to strip. + +STRIP_FROM_PATH = + +# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of +# the path mentioned in the documentation of a class, which tells +# the reader which header file to include in order to use a class. +# If left blank only the name of the header file containing the class +# definition is used. Otherwise one should specify the include paths that +# are normally passed to the compiler using the -I flag. + +STRIP_FROM_INC_PATH = + +# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter +# (but less readable) file names. This can be useful is your file systems +# doesn't support long names like on DOS, Mac, or CD-ROM. + +SHORT_NAMES = NO + +# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen +# will interpret the first line (until the first dot) of a JavaDoc-style +# comment as the brief description. If set to NO, the JavaDoc +# comments will behave just like regular Qt-style comments +# (thus requiring an explicit @brief command for a brief description.) + +JAVADOC_AUTOBRIEF = NO + +# If the QT_AUTOBRIEF tag is set to YES then Doxygen will +# interpret the first line (until the first dot) of a Qt-style +# comment as the brief description. If set to NO, the comments +# will behave just like regular Qt-style comments (thus requiring +# an explicit \brief command for a brief description.) + +QT_AUTOBRIEF = NO + +# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen +# treat a multi-line C++ special comment block (i.e. a block of //! or /// +# comments) as a brief description. This used to be the default behaviour. +# The new default is to treat a multi-line C++ comment block as a detailed +# description. Set this tag to YES if you prefer the old behaviour instead. + +MULTILINE_CPP_IS_BRIEF = NO + +# If the DETAILS_AT_TOP tag is set to YES then Doxygen +# will output the detailed description near the top, like JavaDoc. +# If set to NO, the detailed description appears after the member +# documentation. + +DETAILS_AT_TOP = NO + +# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented +# member inherits the documentation from any documented member that it +# re-implements. + +INHERIT_DOCS = YES + +# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce +# a new page for each member. If set to NO, the documentation of a member will +# be part of the file/class/namespace that contains it. + +SEPARATE_MEMBER_PAGES = NO + +# The TAB_SIZE tag can be used to set the number of spaces in a tab. +# Doxygen uses this value to replace tabs by spaces in code fragments. + +TAB_SIZE = 4 + +# This tag can be used to specify a number of aliases that acts +# as commands in the documentation. An alias has the form "name=value". +# For example adding "sideeffect=\par Side Effects:\n" will allow you to +# put the command \sideeffect (or @sideeffect) in the documentation, which +# will result in a user-defined paragraph with heading "Side Effects:". +# You can put \n's in the value part of an alias to insert newlines. + +ALIASES = + +# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C +# sources only. Doxygen will then generate output that is more tailored for C. +# For instance, some of the names that are used will be different. The list +# of all members will be omitted, etc. + +OPTIMIZE_OUTPUT_FOR_C = YES + +# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java +# sources only. Doxygen will then generate output that is more tailored for +# Java. For instance, namespaces will be presented as packages, qualified +# scopes will look different, etc. + +OPTIMIZE_OUTPUT_JAVA = NO + +# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran +# sources only. Doxygen will then generate output that is more tailored for +# Fortran. + +OPTIMIZE_FOR_FORTRAN = NO + +# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL +# sources. Doxygen will then generate output that is tailored for +# VHDL. + +OPTIMIZE_OUTPUT_VHDL = NO + +# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want +# to include (a tag file for) the STL sources as input, then you should +# set this tag to YES in order to let doxygen match functions declarations and +# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. +# func(std::string) {}). This also make the inheritance and collaboration +# diagrams that involve STL classes more complete and accurate. + +BUILTIN_STL_SUPPORT = NO + +# If you use Microsoft's C++/CLI language, you should set this option to YES to +# enable parsing support. + +CPP_CLI_SUPPORT = NO + +# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. +# Doxygen will parse them like normal C++ but will assume all classes use public +# instead of private inheritance when no explicit protection keyword is present. + +SIP_SUPPORT = NO + +# For Microsoft's IDL there are propget and propput attributes to indicate getter +# and setter methods for a property. Setting this option to YES (the default) +# will make doxygen to replace the get and set methods by a property in the +# documentation. This will only work if the methods are indeed getting or +# setting a simple type. If this is not the case, or you want to show the +# methods anyway, you should set this option to NO. + +IDL_PROPERTY_SUPPORT = YES + +# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC +# tag is set to YES, then doxygen will reuse the documentation of the first +# member in the group (if any) for the other members of the group. By default +# all members of a group must be documented explicitly. + +DISTRIBUTE_GROUP_DOC = NO + +# Set the SUBGROUPING tag to YES (the default) to allow class member groups of +# the same type (for instance a group of public functions) to be put as a +# subgroup of that type (e.g. under the Public Functions section). Set it to +# NO to prevent subgrouping. Alternatively, this can be done per class using +# the \nosubgrouping command. + +SUBGROUPING = YES + +# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum +# is documented as struct, union, or enum with the name of the typedef. So +# typedef struct TypeS {} TypeT, will appear in the documentation as a struct +# with name TypeT. When disabled the typedef will appear as a member of a file, +# namespace, or class. And the struct will be named TypeS. This can typically +# be useful for C code in case the coding convention dictates that all compound +# types are typedef'ed and only the typedef is referenced, never the tag name. + +TYPEDEF_HIDES_STRUCT = NO + +#--------------------------------------------------------------------------- +# Build related configuration options +#--------------------------------------------------------------------------- + +# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in +# documentation are documented, even if no documentation was available. +# Private class members and static file members will be hidden unless +# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES + +EXTRACT_ALL = NO + +# If the EXTRACT_PRIVATE tag is set to YES all private members of a class +# will be included in the documentation. + +EXTRACT_PRIVATE = NO + +# If the EXTRACT_STATIC tag is set to YES all static members of a file +# will be included in the documentation. + +EXTRACT_STATIC = YES + +# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) +# defined locally in source files will be included in the documentation. +# If set to NO only classes defined in header files are included. + +EXTRACT_LOCAL_CLASSES = YES + +# This flag is only useful for Objective-C code. When set to YES local +# methods, which are defined in the implementation section but not in +# the interface are included in the documentation. +# If set to NO (the default) only methods in the interface are included. + +EXTRACT_LOCAL_METHODS = NO + +# If this flag is set to YES, the members of anonymous namespaces will be +# extracted and appear in the documentation as a namespace called +# 'anonymous_namespace{file}', where file will be replaced with the base +# name of the file that contains the anonymous namespace. By default +# anonymous namespace are hidden. + +EXTRACT_ANON_NSPACES = NO + +# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all +# undocumented members of documented classes, files or namespaces. +# If set to NO (the default) these members will be included in the +# various overviews, but no documentation section is generated. +# This option has no effect if EXTRACT_ALL is enabled. + +HIDE_UNDOC_MEMBERS = NO + +# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all +# undocumented classes that are normally visible in the class hierarchy. +# If set to NO (the default) these classes will be included in the various +# overviews. This option has no effect if EXTRACT_ALL is enabled. + +HIDE_UNDOC_CLASSES = NO + +# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all +# friend (class|struct|union) declarations. +# If set to NO (the default) these declarations will be included in the +# documentation. + +HIDE_FRIEND_COMPOUNDS = NO + +# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any +# documentation blocks found inside the body of a function. +# If set to NO (the default) these blocks will be appended to the +# function's detailed documentation block. + +HIDE_IN_BODY_DOCS = NO + +# The INTERNAL_DOCS tag determines if documentation +# that is typed after a \internal command is included. If the tag is set +# to NO (the default) then the documentation will be excluded. +# Set it to YES to include the internal documentation. + +INTERNAL_DOCS = NO + +# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate +# file names in lower-case letters. If set to YES upper-case letters are also +# allowed. This is useful if you have classes or files whose names only differ +# in case and if your file system supports case sensitive file names. Windows +# and Mac users are advised to set this option to NO. + +CASE_SENSE_NAMES = YES + +# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen +# will show members with their full class and namespace scopes in the +# documentation. If set to YES the scope will be hidden. + +HIDE_SCOPE_NAMES = NO + +# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen +# will put a list of the files that are included by a file in the documentation +# of that file. + +SHOW_INCLUDE_FILES = YES + +# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] +# is inserted in the documentation for inline members. + +INLINE_INFO = YES + +# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen +# will sort the (detailed) documentation of file and class members +# alphabetically by member name. If set to NO the members will appear in +# declaration order. + +SORT_MEMBER_DOCS = YES + +# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the +# brief documentation of file, namespace and class members alphabetically +# by member name. If set to NO (the default) the members will appear in +# declaration order. + +SORT_BRIEF_DOCS = NO + +# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the +# hierarchy of group names into alphabetical order. If set to NO (the default) +# the group names will appear in their defined order. + +SORT_GROUP_NAMES = NO + +# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be +# sorted by fully-qualified names, including namespaces. If set to +# NO (the default), the class list will be sorted only by class name, +# not including the namespace part. +# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. +# Note: This option applies only to the class list, not to the +# alphabetical list. + +SORT_BY_SCOPE_NAME = NO + +# The GENERATE_TODOLIST tag can be used to enable (YES) or +# disable (NO) the todo list. This list is created by putting \todo +# commands in the documentation. + +GENERATE_TODOLIST = YES + +# The GENERATE_TESTLIST tag can be used to enable (YES) or +# disable (NO) the test list. This list is created by putting \test +# commands in the documentation. + +GENERATE_TESTLIST = YES + +# The GENERATE_BUGLIST tag can be used to enable (YES) or +# disable (NO) the bug list. This list is created by putting \bug +# commands in the documentation. + +GENERATE_BUGLIST = YES + +# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or +# disable (NO) the deprecated list. This list is created by putting +# \deprecated commands in the documentation. + +GENERATE_DEPRECATEDLIST= YES + +# The ENABLED_SECTIONS tag can be used to enable conditional +# documentation sections, marked by \if sectionname ... \endif. + +ENABLED_SECTIONS = + +# The MAX_INITIALIZER_LINES tag determines the maximum number of lines +# the initial value of a variable or define consists of for it to appear in +# the documentation. If the initializer consists of more lines than specified +# here it will be hidden. Use a value of 0 to hide initializers completely. +# The appearance of the initializer of individual variables and defines in the +# documentation can be controlled using \showinitializer or \hideinitializer +# command in the documentation regardless of this setting. + +MAX_INITIALIZER_LINES = 30 + +# Set the SHOW_USED_FILES tag to NO to disable the list of files generated +# at the bottom of the documentation of classes and structs. If set to YES the +# list will mention the files that were used to generate the documentation. + +SHOW_USED_FILES = YES + +# If the sources in your project are distributed over multiple directories +# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy +# in the documentation. The default is NO. + +SHOW_DIRECTORIES = NO + +# Set the SHOW_FILES tag to NO to disable the generation of the Files page. +# This will remove the Files entry from the Quick Index and from the +# Folder Tree View (if specified). The default is YES. + +SHOW_FILES = YES + +# Set the SHOW_NAMESPACES tag to NO to disable the generation of the +# Namespaces page. This will remove the Namespaces entry from the Quick Index +# and from the Folder Tree View (if specified). The default is YES. + +SHOW_NAMESPACES = YES + +# The FILE_VERSION_FILTER tag can be used to specify a program or script that +# doxygen should invoke to get the current version for each file (typically from +# the version control system). Doxygen will invoke the program by executing (via +# popen()) the command , where is the value of +# the FILE_VERSION_FILTER tag, and is the name of an input file +# provided by doxygen. Whatever the program writes to standard output +# is used as the file version. See the manual for examples. + +FILE_VERSION_FILTER = + +#--------------------------------------------------------------------------- +# configuration options related to warning and progress messages +#--------------------------------------------------------------------------- + +# The QUIET tag can be used to turn on/off the messages that are generated +# by doxygen. Possible values are YES and NO. If left blank NO is used. + +QUIET = NO + +# The WARNINGS tag can be used to turn on/off the warning messages that are +# generated by doxygen. Possible values are YES and NO. If left blank +# NO is used. + +WARNINGS = YES + +# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings +# for undocumented members. If EXTRACT_ALL is set to YES then this flag will +# automatically be disabled. + +WARN_IF_UNDOCUMENTED = YES + +# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for +# potential errors in the documentation, such as not documenting some +# parameters in a documented function, or documenting parameters that +# don't exist or using markup commands wrongly. + +WARN_IF_DOC_ERROR = YES + +# This WARN_NO_PARAMDOC option can be abled to get warnings for +# functions that are documented, but have no documentation for their parameters +# or return value. If set to NO (the default) doxygen will only warn about +# wrong or incomplete parameter documentation, but not about the absence of +# documentation. + +WARN_NO_PARAMDOC = NO + +# The WARN_FORMAT tag determines the format of the warning messages that +# doxygen can produce. The string should contain the $file, $line, and $text +# tags, which will be replaced by the file and line number from which the +# warning originated and the warning text. Optionally the format may contain +# $version, which will be replaced by the version of the file (if it could +# be obtained via FILE_VERSION_FILTER) + +WARN_FORMAT = "$file:$line: $text" + +# The WARN_LOGFILE tag can be used to specify a file to which warning +# and error messages should be written. If left blank the output is written +# to stderr. + +WARN_LOGFILE = + +#--------------------------------------------------------------------------- +# configuration options related to the input files +#--------------------------------------------------------------------------- + +# The INPUT tag can be used to specify the files and/or directories that contain +# documented source files. You may enter file names like "myfile.cpp" or +# directories like "/usr/src/myproject". Separate the files or directories +# with spaces. + +INPUT = ..\edma3_common.h \ + ..\edma3_rm.h \ + ..\src\ + +# This tag can be used to specify the character encoding of the source files +# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is +# also the default input encoding. Doxygen uses libiconv (or the iconv built +# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for +# the list of possible encodings. + +INPUT_ENCODING = UTF-8 + +# If the value of the INPUT tag contains directories, you can use the +# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp +# and *.h) to filter out the source-files in the directories. If left +# blank the following patterns are tested: +# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx +# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 + +FILE_PATTERNS = + +# The RECURSIVE tag can be used to turn specify whether or not subdirectories +# should be searched for input files as well. Possible values are YES and NO. +# If left blank NO is used. + +RECURSIVE = YES + +# The EXCLUDE tag can be used to specify files and/or directories that should +# excluded from the INPUT source files. This way you can easily exclude a +# subdirectory from a directory tree whose root is specified with the INPUT tag. + +EXCLUDE = + +# The EXCLUDE_SYMLINKS tag can be used select whether or not files or +# directories that are symbolic links (a Unix filesystem feature) are excluded +# from the input. + +EXCLUDE_SYMLINKS = NO + +# If the value of the INPUT tag contains directories, you can use the +# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude +# certain files from those directories. Note that the wildcards are matched +# against the file with absolute path, so to exclude all test directories +# for example use the pattern */test/* + +EXCLUDE_PATTERNS = + +# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names +# (namespaces, classes, functions, etc.) that should be excluded from the +# output. The symbol name can be a fully qualified name, a word, or if the +# wildcard * is used, a substring. Examples: ANamespace, AClass, +# AClass::ANamespace, ANamespace::*Test + +EXCLUDE_SYMBOLS = + +# The EXAMPLE_PATH tag can be used to specify one or more files or +# directories that contain example code fragments that are included (see +# the \include command). + +EXAMPLE_PATH = + +# If the value of the EXAMPLE_PATH tag contains directories, you can use the +# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp +# and *.h) to filter out the source-files in the directories. If left +# blank all files are included. + +EXAMPLE_PATTERNS = + +# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be +# searched for input files to be used with the \include or \dontinclude +# commands irrespective of the value of the RECURSIVE tag. +# Possible values are YES and NO. If left blank NO is used. + +EXAMPLE_RECURSIVE = NO + +# The IMAGE_PATH tag can be used to specify one or more files or +# directories that contain image that are included in the documentation (see +# the \image command). + +IMAGE_PATH = + +# The INPUT_FILTER tag can be used to specify a program that doxygen should +# invoke to filter for each input file. Doxygen will invoke the filter program +# by executing (via popen()) the command , where +# is the value of the INPUT_FILTER tag, and is the name of an +# input file. Doxygen will then use the output that the filter program writes +# to standard output. If FILTER_PATTERNS is specified, this tag will be +# ignored. + +INPUT_FILTER = + +# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern +# basis. Doxygen will compare the file name with each pattern and apply the +# filter if there is a match. The filters are a list of the form: +# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further +# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER +# is applied to all files. + +FILTER_PATTERNS = + +# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using +# INPUT_FILTER) will be used to filter the input files when producing source +# files to browse (i.e. when SOURCE_BROWSER is set to YES). + +FILTER_SOURCE_FILES = NO + +#--------------------------------------------------------------------------- +# configuration options related to source browsing +#--------------------------------------------------------------------------- + +# If the SOURCE_BROWSER tag is set to YES then a list of source files will +# be generated. Documented entities will be cross-referenced with these sources. +# Note: To get rid of all source code in the generated output, make sure also +# VERBATIM_HEADERS is set to NO. + +SOURCE_BROWSER = NO + +# Setting the INLINE_SOURCES tag to YES will include the body +# of functions and classes directly in the documentation. + +INLINE_SOURCES = NO + +# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct +# doxygen to hide any special comment blocks from generated source code +# fragments. Normal C and C++ comments will always remain visible. + +STRIP_CODE_COMMENTS = YES + +# If the REFERENCED_BY_RELATION tag is set to YES +# then for each documented function all documented +# functions referencing it will be listed. + +REFERENCED_BY_RELATION = YES + +# If the REFERENCES_RELATION tag is set to YES +# then for each documented function all documented entities +# called/used by that function will be listed. + +REFERENCES_RELATION = YES + +# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) +# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from +# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will +# link to the source code. Otherwise they will link to the documentstion. + +REFERENCES_LINK_SOURCE = YES + +# If the USE_HTAGS tag is set to YES then the references to source code +# will point to the HTML generated by the htags(1) tool instead of doxygen +# built-in source browser. The htags tool is part of GNU's global source +# tagging system (see http://www.gnu.org/software/global/global.html). You +# will need version 4.8.6 or higher. + +USE_HTAGS = NO + +# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen +# will generate a verbatim copy of the header file for each class for +# which an include is specified. Set to NO to disable this. + +VERBATIM_HEADERS = YES + +#--------------------------------------------------------------------------- +# configuration options related to the alphabetical class index +#--------------------------------------------------------------------------- + +# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index +# of all compounds will be generated. Enable this if the project +# contains a lot of classes, structs, unions or interfaces. + +ALPHABETICAL_INDEX = YES + +# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then +# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns +# in which this list will be split (can be a number in the range [1..20]) + +COLS_IN_ALPHA_INDEX = 4 + +# In case all classes in a project start with a common prefix, all +# classes will be put under the same header in the alphabetical index. +# The IGNORE_PREFIX tag can be used to specify one or more prefixes that +# should be ignored while generating the index headers. + +IGNORE_PREFIX = + +#--------------------------------------------------------------------------- +# configuration options related to the HTML output +#--------------------------------------------------------------------------- + +# If the GENERATE_HTML tag is set to YES (the default) Doxygen will +# generate HTML output. + +GENERATE_HTML = YES + +# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `html' will be used as the default path. + +HTML_OUTPUT = html + +# The HTML_FILE_EXTENSION tag can be used to specify the file extension for +# each generated HTML page (for example: .htm,.php,.asp). If it is left blank +# doxygen will generate files with .html extension. + +HTML_FILE_EXTENSION = .html + +# The HTML_HEADER tag can be used to specify a personal HTML header for +# each generated HTML page. If it is left blank doxygen will generate a +# standard header. + +HTML_HEADER = + +# The HTML_FOOTER tag can be used to specify a personal HTML footer for +# each generated HTML page. If it is left blank doxygen will generate a +# standard footer. + +HTML_FOOTER = + +# The HTML_STYLESHEET tag can be used to specify a user-defined cascading +# style sheet that is used by each HTML page. It can be used to +# fine-tune the look of the HTML output. If the tag is left blank doxygen +# will generate a default style sheet. Note that doxygen will try to copy +# the style sheet file to the HTML output directory, so don't put your own +# stylesheet in the HTML output directory as well, or it will be erased! + +HTML_STYLESHEET = + +# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, +# files or namespaces will be aligned in HTML using tables. If set to +# NO a bullet list will be used. + +HTML_ALIGN_MEMBERS = YES + +# If the GENERATE_HTMLHELP tag is set to YES, additional index files +# will be generated that can be used as input for tools like the +# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) +# of the generated HTML documentation. + +GENERATE_HTMLHELP = YES + +# If the GENERATE_DOCSET tag is set to YES, additional index files +# will be generated that can be used as input for Apple's Xcode 3 +# integrated development environment, introduced with OSX 10.5 (Leopard). +# To create a documentation set, doxygen will generate a Makefile in the +# HTML output directory. Running make will produce the docset in that +# directory and running "make install" will install the docset in +# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find +# it at startup. + +GENERATE_DOCSET = NO + +# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the +# feed. A documentation feed provides an umbrella under which multiple +# documentation sets from a single provider (such as a company or product suite) +# can be grouped. + +DOCSET_FEEDNAME = "Doxygen generated docs" + +# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that +# should uniquely identify the documentation set bundle. This should be a +# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen +# will append .docset to the name. + +DOCSET_BUNDLE_ID = org.doxygen.Project + +# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML +# documentation will contain sections that can be hidden and shown after the +# page has loaded. For this to work a browser that supports +# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox +# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). + +HTML_DYNAMIC_SECTIONS = NO + +# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can +# be used to specify the file name of the resulting .chm file. You +# can add a path in front of the file if the result should not be +# written to the html output directory. + +CHM_FILE = ..\EDMA3_Resource_Manager.chm + +# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can +# be used to specify the location (absolute path including file name) of +# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run +# the HTML help compiler on the generated index.hhp. + +HHC_LOCATION = "C:\Program Files\HTML Help Workshop\hhc.exe" + +# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag +# controls if a separate .chi index file is generated (YES) or that +# it should be included in the master .chm file (NO). + +GENERATE_CHI = NO + +# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING +# is used to encode HtmlHelp index (hhk), content (hhc) and project file +# content. + +CHM_INDEX_ENCODING = + +# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag +# controls whether a binary table of contents is generated (YES) or a +# normal table of contents (NO) in the .chm file. + +BINARY_TOC = NO + +# The TOC_EXPAND flag can be set to YES to add extra items for group members +# to the contents of the HTML help documentation and to the tree view. + +TOC_EXPAND = NO + +# The DISABLE_INDEX tag can be used to turn on/off the condensed index at +# top of each HTML page. The value NO (the default) enables the index and +# the value YES disables it. + +DISABLE_INDEX = NO + +# This tag can be used to set the number of enum values (range [1..20]) +# that doxygen will group on one line in the generated HTML documentation. + +ENUM_VALUES_PER_LINE = 1 + +# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index +# structure should be generated to display hierarchical information. +# If the tag value is set to FRAME, a side panel will be generated +# containing a tree-like index structure (just like the one that +# is generated for HTML Help). For this to work a browser that supports +# JavaScript, DHTML, CSS and frames is required (for instance Mozilla 1.0+, +# Netscape 6.0+, Internet explorer 5.0+, or Konqueror). Windows users are +# probably better off using the HTML help feature. Other possible values +# for this tag are: HIERARCHIES, which will generate the Groups, Directories, +# and Class Hiererachy pages using a tree view instead of an ordered list; +# ALL, which combines the behavior of FRAME and HIERARCHIES; and NONE, which +# disables this behavior completely. For backwards compatibility with previous +# releases of Doxygen, the values YES and NO are equivalent to FRAME and NONE +# respectively. + +GENERATE_TREEVIEW = NO + +# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be +# used to set the initial width (in pixels) of the frame in which the tree +# is shown. + +TREEVIEW_WIDTH = 250 + +# Use this tag to change the font size of Latex formulas included +# as images in the HTML documentation. The default is 10. Note that +# when you change the font size after a successful doxygen run you need +# to manually remove any form_*.png images from the HTML output directory +# to force them to be regenerated. + +FORMULA_FONTSIZE = 10 + +#--------------------------------------------------------------------------- +# configuration options related to the LaTeX output +#--------------------------------------------------------------------------- + +# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will +# generate Latex output. + +GENERATE_LATEX = NO + +# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `latex' will be used as the default path. + +LATEX_OUTPUT = latex + +# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be +# invoked. If left blank `latex' will be used as the default command name. + +LATEX_CMD_NAME = latex + +# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to +# generate index for LaTeX. If left blank `makeindex' will be used as the +# default command name. + +MAKEINDEX_CMD_NAME = makeindex + +# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact +# LaTeX documents. This may be useful for small projects and may help to +# save some trees in general. + +COMPACT_LATEX = NO + +# The PAPER_TYPE tag can be used to set the paper type that is used +# by the printer. Possible values are: a4, a4wide, letter, legal and +# executive. If left blank a4wide will be used. + +PAPER_TYPE = a4wide + +# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX +# packages that should be included in the LaTeX output. + +EXTRA_PACKAGES = + +# The LATEX_HEADER tag can be used to specify a personal LaTeX header for +# the generated latex document. The header should contain everything until +# the first chapter. If it is left blank doxygen will generate a +# standard header. Notice: only use this tag if you know what you are doing! + +LATEX_HEADER = + +# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated +# is prepared for conversion to pdf (using ps2pdf). The pdf file will +# contain links (just like the HTML output) instead of page references +# This makes the output suitable for online browsing using a pdf viewer. + +PDF_HYPERLINKS = NO + +# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of +# plain latex in the generated Makefile. Set this option to YES to get a +# higher quality PDF documentation. + +USE_PDFLATEX = NO + +# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. +# command to the generated LaTeX files. This will instruct LaTeX to keep +# running if errors occur, instead of asking the user for help. +# This option is also used when generating formulas in HTML. + +LATEX_BATCHMODE = NO + +# If LATEX_HIDE_INDICES is set to YES then doxygen will not +# include the index chapters (such as File Index, Compound Index, etc.) +# in the output. + +LATEX_HIDE_INDICES = NO + +#--------------------------------------------------------------------------- +# configuration options related to the RTF output +#--------------------------------------------------------------------------- + +# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output +# The RTF output is optimized for Word 97 and may not look very pretty with +# other RTF readers or editors. + +GENERATE_RTF = YES + +# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `rtf' will be used as the default path. + +RTF_OUTPUT = rtf + +# If the COMPACT_RTF tag is set to YES Doxygen generates more compact +# RTF documents. This may be useful for small projects and may help to +# save some trees in general. + +COMPACT_RTF = NO + +# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated +# will contain hyperlink fields. The RTF file will +# contain links (just like the HTML output) instead of page references. +# This makes the output suitable for online browsing using WORD or other +# programs which support those fields. +# Note: wordpad (write) and others do not support links. + +RTF_HYPERLINKS = NO + +# Load stylesheet definitions from file. Syntax is similar to doxygen's +# config file, i.e. a series of assignments. You only have to provide +# replacements, missing definitions are set to their default value. + +RTF_STYLESHEET_FILE = + +# Set optional variables used in the generation of an rtf document. +# Syntax is similar to doxygen's config file. + +RTF_EXTENSIONS_FILE = ..\EDMA3_Resource_Manager.rtf + +#--------------------------------------------------------------------------- +# configuration options related to the man page output +#--------------------------------------------------------------------------- + +# If the GENERATE_MAN tag is set to YES (the default) Doxygen will +# generate man pages + +GENERATE_MAN = NO + +# The MAN_OUTPUT tag is used to specify where the man pages will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `man' will be used as the default path. + +MAN_OUTPUT = man + +# The MAN_EXTENSION tag determines the extension that is added to +# the generated man pages (default is the subroutine's section .3) + +MAN_EXTENSION = .3 + +# If the MAN_LINKS tag is set to YES and Doxygen generates man output, +# then it will generate one additional man file for each entity +# documented in the real man page(s). These additional files +# only source the real man page, but without them the man command +# would be unable to find the correct page. The default is NO. + +MAN_LINKS = NO + +#--------------------------------------------------------------------------- +# configuration options related to the XML output +#--------------------------------------------------------------------------- + +# If the GENERATE_XML tag is set to YES Doxygen will +# generate an XML file that captures the structure of +# the code including all documentation. + +GENERATE_XML = NO + +# The XML_OUTPUT tag is used to specify where the XML pages will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `xml' will be used as the default path. + +XML_OUTPUT = xml + +# The XML_SCHEMA tag can be used to specify an XML schema, +# which can be used by a validating XML parser to check the +# syntax of the XML files. + +XML_SCHEMA = + +# The XML_DTD tag can be used to specify an XML DTD, +# which can be used by a validating XML parser to check the +# syntax of the XML files. + +XML_DTD = + +# If the XML_PROGRAMLISTING tag is set to YES Doxygen will +# dump the program listings (including syntax highlighting +# and cross-referencing information) to the XML output. Note that +# enabling this will significantly increase the size of the XML output. + +XML_PROGRAMLISTING = YES + +#--------------------------------------------------------------------------- +# configuration options for the AutoGen Definitions output +#--------------------------------------------------------------------------- + +# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will +# generate an AutoGen Definitions (see autogen.sf.net) file +# that captures the structure of the code including all +# documentation. Note that this feature is still experimental +# and incomplete at the moment. + +GENERATE_AUTOGEN_DEF = NO + +#--------------------------------------------------------------------------- +# configuration options related to the Perl module output +#--------------------------------------------------------------------------- + +# If the GENERATE_PERLMOD tag is set to YES Doxygen will +# generate a Perl module file that captures the structure of +# the code including all documentation. Note that this +# feature is still experimental and incomplete at the +# moment. + +GENERATE_PERLMOD = NO + +# If the PERLMOD_LATEX tag is set to YES Doxygen will generate +# the necessary Makefile rules, Perl scripts and LaTeX code to be able +# to generate PDF and DVI output from the Perl module output. + +PERLMOD_LATEX = NO + +# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be +# nicely formatted so it can be parsed by a human reader. This is useful +# if you want to understand what is going on. On the other hand, if this +# tag is set to NO the size of the Perl module output will be much smaller +# and Perl will parse it just the same. + +PERLMOD_PRETTY = YES + +# The names of the make variables in the generated doxyrules.make file +# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. +# This is useful so different doxyrules.make files included by the same +# Makefile don't overwrite each other's variables. + +PERLMOD_MAKEVAR_PREFIX = + +#--------------------------------------------------------------------------- +# Configuration options related to the preprocessor +#--------------------------------------------------------------------------- + +# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will +# evaluate all C-preprocessor directives found in the sources and include +# files. + +ENABLE_PREPROCESSING = YES + +# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro +# names in the source code. If set to NO (the default) only conditional +# compilation will be performed. Macro expansion can be done in a controlled +# way by setting EXPAND_ONLY_PREDEF to YES. + +MACRO_EXPANSION = NO + +# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES +# then the macro expansion is limited to the macros specified with the +# PREDEFINED and EXPAND_AS_DEFINED tags. + +EXPAND_ONLY_PREDEF = NO + +# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files +# in the INCLUDE_PATH (see below) will be search if a #include is found. + +SEARCH_INCLUDES = YES + +# The INCLUDE_PATH tag can be used to specify one or more directories that +# contain include files that are not input files but should be processed by +# the preprocessor. + +INCLUDE_PATH = + +# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard +# patterns (like *.h and *.hpp) to filter out the header-files in the +# directories. If left blank, the patterns specified with FILE_PATTERNS will +# be used. + +INCLUDE_FILE_PATTERNS = + +# The PREDEFINED tag can be used to specify one or more macro names that +# are defined before the preprocessor is started (similar to the -D option of +# gcc). The argument of the tag is a list of macros of the form: name +# or name=definition (no spaces). If the definition and the = are +# omitted =1 is assumed. To prevent a macro definition from being +# undefined via #undef or recursively expanded use the := operator +# instead of the = operator. + +PREDEFINED = + +# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then +# this tag can be used to specify a list of macro names that should be expanded. +# The macro definition that is found in the sources will be used. +# Use the PREDEFINED tag if you want to use a different macro definition. + +EXPAND_AS_DEFINED = + +# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then +# doxygen's preprocessor will remove all function-like macros that are alone +# on a line, have an all uppercase name, and do not end with a semicolon. Such +# function macros are typically used for boiler-plate code, and will confuse +# the parser if not removed. + +SKIP_FUNCTION_MACROS = YES + +#--------------------------------------------------------------------------- +# Configuration::additions related to external references +#--------------------------------------------------------------------------- + +# The TAGFILES option can be used to specify one or more tagfiles. +# Optionally an initial location of the external documentation +# can be added for each tagfile. The format of a tag file without +# this location is as follows: +# TAGFILES = file1 file2 ... +# Adding location for the tag files is done as follows: +# TAGFILES = file1=loc1 "file2 = loc2" ... +# where "loc1" and "loc2" can be relative or absolute paths or +# URLs. If a location is present for each tag, the installdox tool +# does not have to be run to correct the links. +# Note that each tag file must have a unique name +# (where the name does NOT include the path) +# If a tag file is not located in the directory in which doxygen +# is run, you must also specify the path to the tagfile here. + +TAGFILES = + +# When a file name is specified after GENERATE_TAGFILE, doxygen will create +# a tag file that is based on the input files it reads. + +GENERATE_TAGFILE = + +# If the ALLEXTERNALS tag is set to YES all external classes will be listed +# in the class index. If set to NO only the inherited external classes +# will be listed. + +ALLEXTERNALS = NO + +# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed +# in the modules index. If set to NO, only the current project's groups will +# be listed. + +EXTERNAL_GROUPS = YES + +# The PERL_PATH should be the absolute path and name of the perl script +# interpreter (i.e. the result of `which perl'). + +PERL_PATH = /usr/bin/perl + +#--------------------------------------------------------------------------- +# Configuration options related to the dot tool +#--------------------------------------------------------------------------- + +# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will +# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base +# or super classes. Setting the tag to NO turns the diagrams off. Note that +# this option is superseded by the HAVE_DOT option below. This is only a +# fallback. It is recommended to install and use dot, since it yields more +# powerful graphs. + +CLASS_DIAGRAMS = YES + +# You can define message sequence charts within doxygen comments using the \msc +# command. Doxygen will then run the mscgen tool (see +# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the +# documentation. The MSCGEN_PATH tag allows you to specify the directory where +# the mscgen tool resides. If left empty the tool is assumed to be found in the +# default search path. + +MSCGEN_PATH = + +# If set to YES, the inheritance and collaboration graphs will hide +# inheritance and usage relations if the target is undocumented +# or is not a class. + +HIDE_UNDOC_RELATIONS = YES + +# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is +# available from the path. This tool is part of Graphviz, a graph visualization +# toolkit from AT&T and Lucent Bell Labs. The other options in this section +# have no effect if this option is set to NO (the default) + +HAVE_DOT = NO + +# By default doxygen will write a font called FreeSans.ttf to the output +# directory and reference it in all dot files that doxygen generates. This +# font does not include all possible unicode characters however, so when you need +# these (or just want a differently looking font) you can specify the font name +# using DOT_FONTNAME. You need need to make sure dot is able to find the font, +# which can be done by putting it in a standard location or by setting the +# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory +# containing the font. + +DOT_FONTNAME = FreeSans + +# By default doxygen will tell dot to use the output directory to look for the +# FreeSans.ttf font (which doxygen will put there itself). If you specify a +# different font using DOT_FONTNAME you can set the path where dot +# can find it using this tag. + +DOT_FONTPATH = + +# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for each documented class showing the direct and +# indirect inheritance relations. Setting this tag to YES will force the +# the CLASS_DIAGRAMS tag to NO. + +CLASS_GRAPH = YES + +# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for each documented class showing the direct and +# indirect implementation dependencies (inheritance, containment, and +# class references variables) of the class with other documented classes. + +COLLABORATION_GRAPH = YES + +# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for groups, showing the direct groups dependencies + +GROUP_GRAPHS = YES + +# If the UML_LOOK tag is set to YES doxygen will generate inheritance and +# collaboration diagrams in a style similar to the OMG's Unified Modeling +# Language. + +UML_LOOK = NO + +# If set to YES, the inheritance and collaboration graphs will show the +# relations between templates and their instances. + +TEMPLATE_RELATIONS = NO + +# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT +# tags are set to YES then doxygen will generate a graph for each documented +# file showing the direct and indirect include dependencies of the file with +# other documented files. + +INCLUDE_GRAPH = YES + +# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and +# HAVE_DOT tags are set to YES then doxygen will generate a graph for each +# documented header file showing the documented files that directly or +# indirectly include this file. + +INCLUDED_BY_GRAPH = YES + +# If the CALL_GRAPH and HAVE_DOT options are set to YES then +# doxygen will generate a call dependency graph for every global function +# or class method. Note that enabling this option will significantly increase +# the time of a run. So in most cases it will be better to enable call graphs +# for selected functions only using the \callgraph command. + +CALL_GRAPH = NO + +# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then +# doxygen will generate a caller dependency graph for every global function +# or class method. Note that enabling this option will significantly increase +# the time of a run. So in most cases it will be better to enable caller +# graphs for selected functions only using the \callergraph command. + +CALLER_GRAPH = NO + +# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen +# will graphical hierarchy of all classes instead of a textual one. + +GRAPHICAL_HIERARCHY = YES + +# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES +# then doxygen will show the dependencies a directory has on other directories +# in a graphical way. The dependency relations are determined by the #include +# relations between the files in the directories. + +DIRECTORY_GRAPH = YES + +# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images +# generated by dot. Possible values are png, jpg, or gif +# If left blank png will be used. + +DOT_IMAGE_FORMAT = png + +# The tag DOT_PATH can be used to specify the path where the dot tool can be +# found. If left blank, it is assumed the dot tool can be found in the path. + +DOT_PATH = + +# The DOTFILE_DIRS tag can be used to specify one or more directories that +# contain dot files that are included in the documentation (see the +# \dotfile command). + +DOTFILE_DIRS = + +# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of +# nodes that will be shown in the graph. If the number of nodes in a graph +# becomes larger than this value, doxygen will truncate the graph, which is +# visualized by representing a node as a red box. Note that doxygen if the +# number of direct children of the root node in a graph is already larger than +# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note +# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. + +DOT_GRAPH_MAX_NODES = 50 + +# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the +# graphs generated by dot. A depth value of 3 means that only nodes reachable +# from the root by following a path via at most 3 edges will be shown. Nodes +# that lay further from the root node will be omitted. Note that setting this +# option to 1 or 2 may greatly reduce the computation time needed for large +# code bases. Also note that the size of a graph can be further restricted by +# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. + +MAX_DOT_GRAPH_DEPTH = 0 + +# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent +# background. This is enabled by default, which results in a transparent +# background. Warning: Depending on the platform used, enabling this option +# may lead to badly anti-aliased labels on the edges of a graph (i.e. they +# become hard to read). + +DOT_TRANSPARENT = NO + +# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output +# files in one run (i.e. multiple -o and -T options on the command line). This +# makes dot run faster, but since only newer versions of dot (>1.8.10) +# support this, this feature is disabled by default. + +DOT_MULTI_TARGETS = NO + +# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will +# generate a legend page explaining the meaning of the various boxes and +# arrows in the dot generated graphs. + +GENERATE_LEGEND = YES + +# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will +# remove the intermediate dot files that are used to generate +# the various graphs. + +DOT_CLEANUP = YES + +#--------------------------------------------------------------------------- +# Configuration::additions related to the search engine +#--------------------------------------------------------------------------- + +# The SEARCHENGINE tag specifies whether or not a search engine should be +# used. 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